-- Version: v11.3 11.3.0.112

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity mas is

    port( mul_a_i    : in    std_logic_vector(17 downto 0);
          mul_b_i    : in    std_logic_vector(17 downto 0);
          add_c_i    : in    std_logic_vector(43 downto 0);
          product_o  : out   std_logic_vector(43 downto 0);
          reset_i    : in    std_logic;
          sys_clk_i  : in    std_logic;
          mas_en_i   : in    std_logic;
          sub_i      : in    std_logic;
          mas_done_o : out   std_logic
        );

end mas;

architecture DEF_ARCH of mas is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

    signal VCC_net_1, GND_net_1, \mas_done_sync[0]_net_1\
         : std_logic;
    signal nc34, nc9, nc13, nc23, nc33, nc16, nc26, nc27, nc17, 
        nc36, nc37, nc5, nc4, nc42, nc41, nc25, nc15, nc35, nc28, 
        nc18, nc38, nc1, nc2, nc22, nc12, nc21, nc11, nc3, nc32, 
        nc40, nc31, nc44, nc7, nc6, nc19, nc29, nc39, nc8, nc43, 
        nc20, nc10, nc24, nc14, nc30 : std_logic;

begin 


    \mas_done_o\ : SLE
      port map(D => \mas_done_sync[0]_net_1\, CLK => sys_clk_i, 
        EN => VCC_net_1, ALn => reset_i, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        mas_done_o);
    
    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    \mas_done_sync[0]\ : SLE
      port map(D => mas_en_i, CLK => sys_clk_i, EN => VCC_net_1, 
        ALn => reset_i, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \mas_done_sync[0]_net_1\);
    
    \op_mult.un3_product_o_muladd_0[35:0]\ : MACC
      port map(CLK(1) => sys_clk_i, CLK(0) => sys_clk_i, A(17)
         => mul_a_i(17), A(16) => mul_a_i(16), A(15) => 
        mul_a_i(15), A(14) => mul_a_i(14), A(13) => mul_a_i(13), 
        A(12) => mul_a_i(12), A(11) => mul_a_i(11), A(10) => 
        mul_a_i(10), A(9) => mul_a_i(9), A(8) => mul_a_i(8), A(7)
         => mul_a_i(7), A(6) => mul_a_i(6), A(5) => mul_a_i(5), 
        A(4) => mul_a_i(4), A(3) => mul_a_i(3), A(2) => 
        mul_a_i(2), A(1) => mul_a_i(1), A(0) => mul_a_i(0), 
        A_EN(1) => VCC_net_1, A_EN(0) => VCC_net_1, A_ARST_N(1)
         => VCC_net_1, A_ARST_N(0) => VCC_net_1, A_SRST_N(1) => 
        VCC_net_1, A_SRST_N(0) => VCC_net_1, B(17) => mul_b_i(17), 
        B(16) => mul_b_i(16), B(15) => mul_b_i(15), B(14) => 
        mul_b_i(14), B(13) => mul_b_i(13), B(12) => mul_b_i(12), 
        B(11) => mul_b_i(11), B(10) => mul_b_i(10), B(9) => 
        mul_b_i(9), B(8) => mul_b_i(8), B(7) => mul_b_i(7), B(6)
         => mul_b_i(6), B(5) => mul_b_i(5), B(4) => mul_b_i(4), 
        B(3) => mul_b_i(3), B(2) => mul_b_i(2), B(1) => 
        mul_b_i(1), B(0) => mul_b_i(0), B_EN(1) => VCC_net_1, 
        B_EN(0) => VCC_net_1, B_ARST_N(1) => VCC_net_1, 
        B_ARST_N(0) => VCC_net_1, B_SRST_N(1) => VCC_net_1, 
        B_SRST_N(0) => VCC_net_1, C(43) => add_c_i(43), C(42) => 
        add_c_i(42), C(41) => add_c_i(41), C(40) => add_c_i(40), 
        C(39) => add_c_i(39), C(38) => add_c_i(38), C(37) => 
        add_c_i(37), C(36) => add_c_i(36), C(35) => add_c_i(35), 
        C(34) => add_c_i(34), C(33) => add_c_i(33), C(32) => 
        add_c_i(32), C(31) => add_c_i(31), C(30) => add_c_i(30), 
        C(29) => add_c_i(29), C(28) => add_c_i(28), C(27) => 
        add_c_i(27), C(26) => add_c_i(26), C(25) => add_c_i(25), 
        C(24) => add_c_i(24), C(23) => add_c_i(23), C(22) => 
        add_c_i(22), C(21) => add_c_i(21), C(20) => add_c_i(20), 
        C(19) => add_c_i(19), C(18) => add_c_i(18), C(17) => 
        add_c_i(17), C(16) => add_c_i(16), C(15) => add_c_i(15), 
        C(14) => add_c_i(14), C(13) => add_c_i(13), C(12) => 
        add_c_i(12), C(11) => add_c_i(11), C(10) => add_c_i(10), 
        C(9) => add_c_i(9), C(8) => add_c_i(8), C(7) => 
        add_c_i(7), C(6) => add_c_i(6), C(5) => add_c_i(5), C(4)
         => add_c_i(4), C(3) => add_c_i(3), C(2) => add_c_i(2), 
        C(1) => add_c_i(1), C(0) => add_c_i(0), C_EN(1) => 
        VCC_net_1, C_EN(0) => VCC_net_1, C_ARST_N(1) => VCC_net_1, 
        C_ARST_N(0) => VCC_net_1, C_SRST_N(1) => VCC_net_1, 
        C_SRST_N(0) => VCC_net_1, P_EN(1) => mas_en_i, P_EN(0)
         => mas_en_i, P_ARST_N(1) => reset_i, P_ARST_N(0) => 
        reset_i, P_SRST_N(1) => VCC_net_1, P_SRST_N(0) => 
        VCC_net_1, FDBKSEL => GND_net_1, FDBKSEL_EN => VCC_net_1, 
        FDBKSEL_AL_N => VCC_net_1, FDBKSEL_SL_N => VCC_net_1, 
        CDSEL => GND_net_1, CDSEL_EN => VCC_net_1, CDSEL_AL_N => 
        VCC_net_1, CDSEL_SL_N => VCC_net_1, ARSHFT17 => GND_net_1, 
        ARSHFT17_EN => VCC_net_1, ARSHFT17_AL_N => VCC_net_1, 
        ARSHFT17_SL_N => VCC_net_1, SUB => sub_i, SUB_EN => 
        VCC_net_1, SUB_AL_N => VCC_net_1, SUB_SL_N => VCC_net_1, 
        CARRYIN => GND_net_1, SIMD => GND_net_1, DOTP => 
        GND_net_1, OVFL_CARRYOUT_SEL => GND_net_1, A_BYPASS(1)
         => VCC_net_1, A_BYPASS(0) => VCC_net_1, B_BYPASS(1) => 
        VCC_net_1, B_BYPASS(0) => VCC_net_1, C_BYPASS(1) => 
        VCC_net_1, C_BYPASS(0) => VCC_net_1, P_BYPASS(1) => 
        GND_net_1, P_BYPASS(0) => GND_net_1, FDBKSEL_BYPASS => 
        VCC_net_1, FDBKSEL_AD => GND_net_1, FDBKSEL_SD_N => 
        GND_net_1, CDSEL_BYPASS => VCC_net_1, CDSEL_AD => 
        GND_net_1, CDSEL_SD_N => GND_net_1, ARSHFT17_BYPASS => 
        VCC_net_1, ARSHFT17_AD => GND_net_1, ARSHFT17_SD_N => 
        GND_net_1, SUB_BYPASS => VCC_net_1, SUB_AD => GND_net_1, 
        SUB_SD_N => GND_net_1, CDIN(43) => GND_net_1, CDIN(42)
         => GND_net_1, CDIN(41) => GND_net_1, CDIN(40) => 
        GND_net_1, CDIN(39) => GND_net_1, CDIN(38) => GND_net_1, 
        CDIN(37) => GND_net_1, CDIN(36) => GND_net_1, CDIN(35)
         => GND_net_1, CDIN(34) => GND_net_1, CDIN(33) => 
        GND_net_1, CDIN(32) => GND_net_1, CDIN(31) => GND_net_1, 
        CDIN(30) => GND_net_1, CDIN(29) => GND_net_1, CDIN(28)
         => GND_net_1, CDIN(27) => GND_net_1, CDIN(26) => 
        GND_net_1, CDIN(25) => GND_net_1, CDIN(24) => GND_net_1, 
        CDIN(23) => GND_net_1, CDIN(22) => GND_net_1, CDIN(21)
         => GND_net_1, CDIN(20) => GND_net_1, CDIN(19) => 
        GND_net_1, CDIN(18) => GND_net_1, CDIN(17) => GND_net_1, 
        CDIN(16) => GND_net_1, CDIN(15) => GND_net_1, CDIN(14)
         => GND_net_1, CDIN(13) => GND_net_1, CDIN(12) => 
        GND_net_1, CDIN(11) => GND_net_1, CDIN(10) => GND_net_1, 
        CDIN(9) => GND_net_1, CDIN(8) => GND_net_1, CDIN(7) => 
        GND_net_1, CDIN(6) => GND_net_1, CDIN(5) => GND_net_1, 
        CDIN(4) => GND_net_1, CDIN(3) => GND_net_1, CDIN(2) => 
        GND_net_1, CDIN(1) => GND_net_1, CDIN(0) => GND_net_1, 
        CDOUT(43) => nc34, CDOUT(42) => nc9, CDOUT(41) => nc13, 
        CDOUT(40) => nc23, CDOUT(39) => nc33, CDOUT(38) => nc16, 
        CDOUT(37) => nc26, CDOUT(36) => nc27, CDOUT(35) => nc17, 
        CDOUT(34) => nc36, CDOUT(33) => nc37, CDOUT(32) => nc5, 
        CDOUT(31) => nc4, CDOUT(30) => nc42, CDOUT(29) => nc41, 
        CDOUT(28) => nc25, CDOUT(27) => nc15, CDOUT(26) => nc35, 
        CDOUT(25) => nc28, CDOUT(24) => nc18, CDOUT(23) => nc38, 
        CDOUT(22) => nc1, CDOUT(21) => nc2, CDOUT(20) => nc22, 
        CDOUT(19) => nc12, CDOUT(18) => nc21, CDOUT(17) => nc11, 
        CDOUT(16) => nc3, CDOUT(15) => nc32, CDOUT(14) => nc40, 
        CDOUT(13) => nc31, CDOUT(12) => nc44, CDOUT(11) => nc7, 
        CDOUT(10) => nc6, CDOUT(9) => nc19, CDOUT(8) => nc29, 
        CDOUT(7) => nc39, CDOUT(6) => nc8, CDOUT(5) => nc43, 
        CDOUT(4) => nc20, CDOUT(3) => nc10, CDOUT(2) => nc24, 
        CDOUT(1) => nc14, CDOUT(0) => nc30, P(43) => 
        product_o(43), P(42) => product_o(42), P(41) => 
        product_o(41), P(40) => product_o(40), P(39) => 
        product_o(39), P(38) => product_o(38), P(37) => 
        product_o(37), P(36) => product_o(36), P(35) => 
        product_o(35), P(34) => product_o(34), P(33) => 
        product_o(33), P(32) => product_o(32), P(31) => 
        product_o(31), P(30) => product_o(30), P(29) => 
        product_o(29), P(28) => product_o(28), P(27) => 
        product_o(27), P(26) => product_o(26), P(25) => 
        product_o(25), P(24) => product_o(24), P(23) => 
        product_o(23), P(22) => product_o(22), P(21) => 
        product_o(21), P(20) => product_o(20), P(19) => 
        product_o(19), P(18) => product_o(18), P(17) => 
        product_o(17), P(16) => product_o(16), P(15) => 
        product_o(15), P(14) => product_o(14), P(13) => 
        product_o(13), P(12) => product_o(12), P(11) => 
        product_o(11), P(10) => product_o(10), P(9) => 
        product_o(9), P(8) => product_o(8), P(7) => product_o(7), 
        P(6) => product_o(6), P(5) => product_o(5), P(4) => 
        product_o(4), P(3) => product_o(3), P(2) => product_o(2), 
        P(1) => product_o(1), P(0) => product_o(0), OVFL_CARRYOUT
         => OPEN);
    

end DEF_ARCH; 
