Synopsys Generic Technology Mapper, Version mapact, Build 1350R, Built Oct 16 2014 10:02:37
Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
Product Version I-2014.03M-SP1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 135MB)

@N: BN114 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\work\mc_system_sb\mc_system_sb.vhd":687:0:687:11|Removing instance SYSRESET_POR of black_box view:smartfusion2.SYSRESET(syn_black_box) because there are no references to its outputs 

Available hyper_sources - for debug and ip models
	None Found

@W: MO129 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":781:8:781:9|Sequential instance MC_System_sb_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation
@N: FA239 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreapb3\4.0.100\rtl\vhdl\core\coreapb3.vhd":633:12:633:15|ROM CoreAPB3_0.iPSELS_raw_5[1:0] mapped in logic.
@N: FA239 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreapb3\4.0.100\rtl\vhdl\core\coreapb3.vhd":633:12:633:15|ROM CoreAPB3_0.iPSELS_raw_5[1:0] mapped in logic.
@N: MO106 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreapb3\4.0.100\rtl\vhdl\core\coreapb3.vhd":633:12:633:15|Found ROM, 'CoreAPB3_0.iPSELS_raw_5[1:0]', 16 words by 2 bits 
@W: MO129 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":781:8:781:9|Sequential instance MC_System_sb_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation
@W: MO129 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1331:8:1331:9|Sequential instance MC_System_sb_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)


Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)


Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
------------------------------------------------------------


Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)



#### START OF CLOCK OPTIMIZATION REPORT #####[

Clock optimization not enabled
1 non-gated/non-generated clock tree(s) driving 1 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=================================================== Non-Gated/Non-Generated Clocks ===================================================
Clock Tree ID     Driving Element                   Drive Element Type     Fanout     Sample Instance                                 
--------------------------------------------------------------------------------------------------------------------------------------
@K:CKID0001       MC_System_sb_0.CCC_0.GL0_INST     CLKINT                 1          MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST
======================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]

Writing Analyst data base D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\synthesis\MC_System.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 135MB)

Writing Analyst data base D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\synthesis\synwork\MC_System_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 135MB)

Writing EDIF Netlist and constraint files
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
I-2014.03M-SP1

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 135MB)

@W: MT246 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\work\mc_system_sb\ccc_0\mc_system_sb_ccc_0_fccc.vhd":110:4:110:11|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:MC_System_sb_0.CCC_0.GL0_net"



@S |##### START OF TIMING REPORT #####[
# Timing Report written on Tue Mar 10 11:25:07 2015
#


Top view:               MC_System
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: 2.048

                                                   Requested     Estimated      Requested     Estimated               Clock        Clock              
Starting Clock                                     Frequency     Frequency      Period        Period        Slack     Type         Group              
------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     125.7 MHz      10.000        7.952         2.048     inferred     Inferred_clkgroup_0
System                                             100.0 MHz     1029.4 MHz     10.000        0.971         9.029     system       system_clkgroup    
======================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                                          |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                        Ending                                          |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                          System                                          |  10.000      9.029  |  No paths    -      |  No paths    -      |  No paths    -    
MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  |  10.000      2.048  |  No paths    -      |  No paths    -      |  No paths    -    
======================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                     Starting                                                                                                                            Arrival          
Instance                                             Reference                                          Type        Pin                Net                                               Time        Slack
                                                     Clock                                                                                                                                                
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[13]     AMBA_SLAVE_1_PADDRS_c[13]                         3.101       2.048
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[14]     AMBA_SLAVE_1_PADDRS_c[14]                         3.105       2.258
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[15]     AMBA_SLAVE_1_PADDRS_c[15]                         3.044       2.428
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_SEL          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx     2.965       2.460
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[12]     AMBA_SLAVE_1_PADDRS_c[12]                         3.126       3.136
==========================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                     Starting                                                                                                                                  Required          
Instance                                             Reference                                          Type        Pin                 Net                                                    Time         Slack
                                                     Clock                                                                                                                                                       
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_READY         N_39_i_0                                               8.643        2.048
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RESP          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSLVERR        9.147        2.569
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[3]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]      9.483        2.905
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[4]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]      9.539        2.961
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[9]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[9]      9.594        3.016
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[23]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[23]     9.604        3.026
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[0]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[0]      9.617        3.039
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[29]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[29]     9.625        3.047
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[30]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[30]     9.629        3.051
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[13]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[13]     9.640        3.062
=================================================================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            1.357
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.643

    - Propagation time:                      6.595
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     2.048

    Number of logic level(s):                2
    Starting point:                          MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[13]
    Ending point:                            MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_READY
    The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
    The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

Instance / Net                                                   Pin                Pin               Arrival     No. of    
Name                                                 Type        Name               Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MSS_010     F_HM0_ADDR[13]     Out     3.101     3.101       -         
AMBA_SLAVE_1_PADDRS_c[13]                            Net         -                  -       0.980     -           3         
MC_System_sb_0.CoreAPB3_0.iPSELS_raw_0_a2_0[0]       CFG4        D                  In      -         4.080       -         
MC_System_sb_0.CoreAPB3_0.iPSELS_raw_0_a2_0[0]       CFG4        Y                  Out     0.411     4.491       -         
N_113                                                Net         -                  -       0.933     -           36        
MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.N_39_i       CFG4        C                  In      -         5.424       -         
MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.N_39_i       CFG4        Y                  Out     0.200     5.624       -         
N_39_i_0                                             Net         -                  -       0.971     -           1         
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MSS_010     F_HM0_READY        In      -         6.595       -         
============================================================================================================================
Total path delay (propagation time + setup) of 7.952 is 5.069(63.7%) logic and 2.884(36.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                             Starting                                                                                           Arrival          
Instance                                     Reference     Type               Pin        Net                                                    Time        Slack
                                             Clock                                                                                                               
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_sb_0.FABOSC_0.I_RCOSC_25_50MHZ     System        RCOSC_25_50MHZ     CLKOUT     FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     0.000       9.029
=================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                  Starting                                                                                         Required          
Instance                          Reference     Type     Pin                Net                                                    Time         Slack
                                  Clock                                                                                                              
-----------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_sb_0.CCC_0.CCC_INST     System        CCC      RCOSC_25_50MHZ     FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     10.000       9.029
=====================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         10.000

    - Propagation time:                      0.971
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 9.029

    Number of logic level(s):                0
    Starting point:                          MC_System_sb_0.FABOSC_0.I_RCOSC_25_50MHZ / CLKOUT
    Ending point:                            MC_System_sb_0.CCC_0.CCC_INST / RCOSC_25_50MHZ
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                            Pin                Pin               Arrival     No. of    
Name                                                   Type               Name               Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------
MC_System_sb_0.FABOSC_0.I_RCOSC_25_50MHZ               RCOSC_25_50MHZ     CLKOUT             Out     0.000     0.000       -         
FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     Net                -                  -       0.971     -           1         
MC_System_sb_0.CCC_0.CCC_INST                          CCC                RCOSC_25_50MHZ     In      -         0.971       -         
=====================================================================================================================================
Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report for MC_System 

Mapping to part: m2s010fbga484-1
Cell usage:
CCC             1 use
CLKINT          2 uses
MSS_010         1 use
RCOSC_25_50MHZ  1 use
CFG2           2 uses
CFG4           35 uses


Sequential Cells: 
SLE            0 uses

DSP Blocks:    0

I/O ports: 220
I/O primitives: 219
BIBUF          8 uses
INBUF          71 uses
OUTBUF         139 uses
TRIBUFF        1 use


Global Clock Buffers: 2


Total LUTs:    37

Extra resources required for RAM and MACC interface logic during P&R:

RAM64x18 Interface Logic : SLEs = 0; LUTs = 0;
RAM1K18  Interface Logic : SLEs = 0; LUTs = 0;
MACC     Interface Logic : SLEs = 0; LUTs = 0;

Total number of SLEs after P&R:  0 + 0 + 0 + 0 = 0;
Total number of LUTs after P&R:  37 + 0 + 0 + 0 = 37;

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 50MB peak: 135MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Mar 10 11:25:08 2015

###########################################################]
