
Starting:    F:\Microsemi\Libero_SoC_v11.8\SynplifyPro\bin64\mbin\synbatch.exe
Install:     F:\Microsemi\Libero_SoC_v11.8\SynplifyPro
Hostname:    W1064L-ASHWINM
Date:        Wed Nov 29 13:44:44 2017
Version:     L-2016.09M-2

Arguments:   -product synplify_pro -licensetype synplifypro_actel -batch -log synplify.log MC_System_top_syn.tcl
ProductType: synplify_pro

License checkout: synplifypro_actel
License: synplifypro_actel from server wilkie 
Licensed Vendor: actel
License Option: actel_oem

Running in Vendor Mode


auto_infer_blackbox is not supported in current product.

log file: "F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\synthesis\MC_System_top_1.srr"

Running: synthesis in foreground



Running MC_System_top_syn|synthesis


Running: compile (Compile) on MC_System_top_syn|synthesis
# Wed Nov 29 13:44:44 2017


Running: compile_flow (Compile Process) on MC_System_top_syn|synthesis
# Wed Nov 29 13:44:44 2017


Running: compiler (Compile Input) on MC_System_top_syn|synthesis
# Wed Nov 29 13:44:44 2017

Copied F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\synthesis\synwork\MC_System_top_1_comp.srs to F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\synthesis\MC_System_top_1.srs


compiler completed
# Wed Nov 29 13:44:49 2017

Return Code: 0
Run Time:00h:00m:05s


Running: multi_srs_gen (Multi-srs Generator) on MC_System_top_syn|synthesis
# Wed Nov 29 13:44:49 2017


multi_srs_gen completed
# Wed Nov 29 13:44:50 2017

Return Code: 0
Run Time:00h:00m:01s

Copied F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\synthesis\synwork\MC_System_top_1_mult.srs to F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\synthesis\MC_System_top_1.srs

Complete: Compile Process on MC_System_top_syn|synthesis


Running: premap (Pre-mapping) on MC_System_top_syn|synthesis
# Wed Nov 29 13:44:50 2017


premap completed with warnings
# Wed Nov 29 13:44:53 2017

Return Code: 1
Run Time:00h:00m:03s

Complete: Compile on MC_System_top_syn|synthesis


Running: map (Map) on MC_System_top_syn|synthesis
# Wed Nov 29 13:44:53 2017

License granted for 4 parallel jobs


Running: fpga_mapper (Map & Optimize) on MC_System_top_syn|synthesis
# Wed Nov 29 13:44:53 2017

Copied F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\synthesis\synwork\MC_System_top_1_m.srm to F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\synthesis\MC_System_top_1.srm


fpga_mapper completed with warnings
# Wed Nov 29 13:45:10 2017

Return Code: 1
Run Time:00h:00m:17s

Complete: Map on MC_System_top_syn|synthesis

Complete: Logic Synthesis on MC_System_top_syn|synthesis

TCL script complete: "MC_System_top_syn.tcl"

exit status=0

exit status=0

License checkin: synplifypro_actel

