--=================================================================================================
-- File Name                           : pwm3ph_tb.vhd

-- Description                         : This module implements the test environment for
--                                       pwm3ph block

-- Targeted device                     : Microsemi-SoC
-- Author                              : India Solutions Team
--
-- SVN Revision Information            :
-- SVN $Revision                       :
-- SVN $Date                           :
--
-- COPYRIGHT 2016 BY MICROSEMI
-- THE INFORMATION CONTAINED IN THIS DOCUMENT IS SUBJECT TO LICENSING RESTRICTIONS FROM MICROSEMI
-- CORP. IF YOU ARE NOT IN POSSESSION OF WRITTEN AUTHORIZATION FROM MICROSEMI FOR USE OF THIS
-- FILE, THEN THE FILE SHOULD BE IMMEDIATELY DESTROYED AND NO BACK-UP OF THE FILE SHOULD BE MADE.
--
--=================================================================================================

--=================================================================================================
-- Libraries
--=================================================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE STD.TEXTIO.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.MATH_REAL.ALL;   -- FOR UNIFORM, TRUNC FUNCTIONS
LIBRARY MODELSIM_LIB;
USE MODELSIM_LIB.UTIL.ALL;
USE work.sim_pkg.all;

--=================================================================================================
-- pwm3ph_tb entity declaration
--=================================================================================================
ENTITY pwm3ph_tb IS

END pwm3ph_tb;

--=================================================================================================
-- pwm3ph_tb architecture body
--=================================================================================================
ARCHITECTURE behavioral OF pwm3ph_tb IS

COMPONENT pwm3ph IS
PORT (
    reset_i                            : IN  STD_LOGIC;
    sys_clk_i                          : IN  STD_LOGIC;
    en_pwm_i                           : IN  STD_LOGIC;
    en_dual_trig_i                     : IN  STD_LOGIC;
    Va_i              	   		   	   : IN  STD_LOGIC_VECTOR (17 DOWNTO 0);
    Vb_i                	   		   : IN  STD_LOGIC_VECTOR (17 DOWNTO 0);
    Vc_i                	   		   : IN  STD_LOGIC_VECTOR (17 DOWNTO 0);
    pwm_period_i               	   	   : IN  STD_LOGIC_VECTOR (17 DOWNTO 0);
    dead_time_i           	   		   : IN  STD_LOGIC_VECTOR (17 DOWNTO 0);
    delay_time_i           	   		   : IN  STD_LOGIC_VECTOR (17 DOWNTO 0);
    midmatch_o                         : OUT STD_LOGIC;
    PWM_AH_o                           : OUT STD_LOGIC;
    PWM_BH_o                           : OUT STD_LOGIC;
    PWM_CH_o                           : OUT STD_LOGIC;
    PWM_AL_o                           : OUT STD_LOGIC;
    PWM_BL_o                           : OUT STD_LOGIC;
    PWM_CL_o                           : OUT STD_LOGIC
);
END COMPONENT;

--=================================================================================================
-- Signal declarations
--=================================================================================================
CONSTANT SYSCLK_PERIOD                 : TIME := 100 ns;
TYPE pwm_state IS (IDLE,ENABLE_PWM,ENABLE_PWM_WAIT,MID_MATCH_COMPARE,RESET_STATE,OUTPUT_COMPARE);
SIGNAL state                           : pwm_state;
SIGNAL sys_clk_tb                      : STD_LOGIC:= '0';
SIGNAL reset_tb                        : STD_LOGIC:= '0';
SIGNAL s_reset_tb                      : STD_LOGIC;
SIGNAL s_reset_tb_pul                  : STD_LOGIC;
SIGNAL s_reset_tb_dly                  : STD_LOGIC;
SIGNAL s_start_tb                      : STD_LOGIC;
SIGNAL s_flag_tb                       : STD_LOGIC;
SIGNAL s_flag_tb_pul                   : STD_LOGIC;
SIGNAL s_flag_tb_dly                   : STD_LOGIC;
SIGNAL s_en_pwm_tb                     : STD_LOGIC;
SIGNAL s_en_pwm_tb_dly                 : STD_LOGIC;
SIGNAL s_en_pwm_tb_pul                 : STD_LOGIC;
SIGNAL s_midmatch_tb                   : STD_LOGIC;
SIGNAL s_midmatch_down                 : STD_LOGIC;
SIGNAL s_midmatch_up                   : STD_LOGIC;
SIGNAL s_PWM_AH_tb                     : STD_LOGIC;
SIGNAL s_PWM_AH_tb_dly                 : STD_LOGIC;
SIGNAL s_PWM_AH_tb_pul                 : STD_LOGIC;
SIGNAL s_PWM_AH_tb_pul_dly             : STD_LOGIC;
SIGNAL s_PWM_BH_tb                     : STD_LOGIC;
SIGNAL s_PWM_BH_tb_dly                 : STD_LOGIC;
SIGNAL s_PWM_BH_tb_pul                 : STD_LOGIC;
SIGNAL s_PWM_BH_tb_pul_dly             : STD_LOGIC;
SIGNAL s_PWM_CH_tb                     : STD_LOGIC;
SIGNAL s_PWM_CH_tb_dly                 : STD_LOGIC;
SIGNAL s_PWM_CH_tb_pul                 : STD_LOGIC;
SIGNAL s_PWM_CH_tb_pul_dly             : STD_LOGIC;
SIGNAL s_PWM_AL_tb                     : STD_LOGIC;
SIGNAL s_PWM_AL_tb_dly                 : STD_LOGIC;
SIGNAL s_PWM_AL_tb_pul                 : STD_LOGIC;
SIGNAL s_PWM_AL_tb_pul_dly             : STD_LOGIC;
SIGNAL s_PWM_BL_tb                     : STD_LOGIC;
SIGNAL s_PWM_BL_tb_dly                 : STD_LOGIC;
SIGNAL s_PWM_BL_tb_pul                 : STD_LOGIC;
SIGNAL s_PWM_BL_tb_pul_dly             : STD_LOGIC;
SIGNAL s_PWM_CL_tb                     : STD_LOGIC;
SIGNAL s_PWM_CL_tb_dly                 : STD_LOGIC;
SIGNAL s_PWM_CL_tb_pul                 : STD_LOGIC;
SIGNAL s_PWM_CL_tb_pul_dly             : STD_LOGIC;
SIGNAL s_en_dual_trig                  : STD_LOGIC;
SIGNAL s_midmatch_tb_ext               : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL s_flag_tb_pul_ext               : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL counter                         : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL s_va_tb                         : STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL s_vb_tb                         : STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL s_vc_tb                         : STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL s_pwm_period_tb                 : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_delay_time_tb                 : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_counter_tb                    : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_cnt_pwmah_tb                  : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_cnt_pwmbh_tb                  : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_cnt_pwmch_tb                  : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_cnt_pwmal_tb                  : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_cnt_pwmbl_tb                  : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_cnt_pwmcl_tb                  : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_error_pwmah_tb                : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_error_pwmbh_tb                : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_error_pwmch_tb                : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_error_pwmal_tb                : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_error_pwmbl_tb                : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_error_pwmcl_tb                : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_error_count_pwmah_tb          : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL s_error_count_pwmbh_tb          : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL s_error_count_pwmch_tb          : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL s_error_count_pwmal_tb          : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL s_error_count_pwmbl_tb          : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL s_error_count_pwmcl_tb          : STD_LOGIC_VECTOR(11 DOWNTO 0);

--========================================================
-- File read operations
--========================================================
--NA--
--========================================================
-- File Write operations
--========================================================
--NA--

BEGIN

--========================================================
-- SIGNAL spy operations
--========================================================
--NA--
--------------------------------------------------------------------------
-- Name       : RESET_GEN_PROC
-- Description: Process generates the reset signal
--------------------------------------------------------------------------
RESET_GEN_PROC:
    PROCESS
        VARIABLE vhdl_initial : BOOLEAN := TRUE;
    BEGIN
        IF ( vhdl_initial ) THEN
            reset_tb <= '0';
            s_en_dual_trig <= '1';
            WAIT FOR ( SYSCLK_PERIOD * 10);
            reset_tb <= '1';
            WAIT FOR (10000 ns);
            s_en_dual_trig <= '0';
            print("Dual trigger disabled.");
            WAIT;
        END IF;
    END PROCESS;
--------------------------------------------------------------------------
-- Name       : CLOCK_GEN
-- Description: Logic generates 10 Mhz clock
--------------------------------------------------------------------------
sys_clk_tb <= NOT sys_clk_tb AFTER (SYSCLK_PERIOD / 2.0 );

--------------------------------------------------------------------------
-- Name       : RESET_PUL_GEN_PROC
-- Description: Process to generate a reset pulse 
--------------------------------------------------------------------------
RESET_PUL_GEN_PROC:
    PROCESS(reset_tb,sys_clk_tb)
    BEGIN
        IF(reset_tb = '0') THEN
            s_reset_tb_dly <= '0';
        ELSIF(RISING_EDGE (sys_clk_tb))THEN
            s_reset_tb_dly <= reset_tb;
        END IF;
    END PROCESS;

s_reset_tb_pul <= reset_tb AND (not(s_reset_tb_dly ));

 --------------------------------------------------------------------------
-- Name       : ENABLE_PUL_GEN_PROC
-- Description: Process to generate an enable pulse 
--------------------------------------------------------------------------
ENABLE_PUL_GEN_PROC:
    PROCESS(reset_tb,sys_clk_tb)
    BEGIN
        IF(reset_tb = '0') THEN
            s_en_pwm_tb_dly <= '0';
        ELSIF(RISING_EDGE (sys_clk_tb))THEN
            s_en_pwm_tb_dly <= s_en_pwm_tb;
        END IF;
    END PROCESS;
    
s_en_pwm_tb_pul <= s_en_pwm_tb AND (not(s_en_pwm_tb_dly ));
--------------------------------------------------------------------------
-- Name       : RESET_TEST_PROC
-- Description: PROCESS to check the state of all outputs at reset
--------------------------------------------------------------------------
RESET_TEST_PROC:
    PROCESS(s_reset_tb_pul,
            s_midmatch_tb,
            s_PWM_AH_tb,
            s_PWM_BH_tb,
            s_PWM_CH_tb,
            s_PWM_AL_tb,
            s_PWM_BL_tb,
            s_PWM_CL_tb)
    BEGIN
        IF (s_reset_tb_pul = '1') THEN
            IF((s_midmatch_tb = '0') AND (s_PWM_AH_tb = '0') AND (s_PWM_BH_tb = '0') AND (s_PWM_CH_tb = '0') AND
            (s_PWM_AL_tb = '0') AND(s_PWM_BL_tb = '0') AND(s_PWM_CL_tb = '0'))THEN
                print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                print(">>>>>>>>                     PWM3H IP INTEGRATED SIMULATION                         <<<<<<<");
                print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                print(">>>>>>>>     THIS TESTBENCH COMPARES THE FUNCTIONALITY W.R.T THE TESTBENCH MODEL    <<<<<<<");
                print(">>>>>>>>     WITH IN THE TOLERANCE RANGE [-1,0,+1]                                  <<<<<<<");
                print(">>>>>>>>                                                                            <<<<<<<");
                print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                print("                                                        ");
                print("                                                        ");
                print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                print(">>>>        PWM3H_RESET_TEST : PASSED               <<<<");
                print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                print(">>>>     midmatch_o     = 0                         <<<<");
                print(">>>>     PWM_AH_o       = 0                         <<<<");
                print(">>>>     PWM_BH_o       = 0                         <<<<");
                print(">>>>     PWM_CH_o       = 0                         <<<<");
                print(">>>>     PWM_AL_o       = 0                         <<<<");
                print(">>>>     PWM_BL_o       = 0                         <<<<");
                print(">>>>     PWM_CL_o       = 0                         <<<<");
                print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            ELSE
                print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                print(">>>>>>>>                     PWM3H IP INTEGRATED SIMULATION                         <<<<<<<");
                print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                print(">>>>>>>>     THIS TESTBENCH COMPARES THE FUNCTIONALITY W.R.T THE TESTBENCH MODEL    <<<<<<<");
                print(">>>>>>>>     WITH IN THE TOLERANCE RANGE [-1,0,+1]                                  <<<<<<<");
                print(">>>>>>>>                                                                            <<<<<<<");
                print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                print("                                                        ");
                print("                                                        ");
                print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                print(">>>>        PWM3H_RESET_TEST : FAILED               <<<<");
                print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                print(">>>>     midmatch_o     = 0                         <<<<");
                print(">>>>     PWM_AH_o       = 0                         <<<<");
                print(">>>>     PWM_BH_o       = 0                         <<<<");
                print(">>>>     PWM_CH_o       = 0                         <<<<");
                print(">>>>     PWM_AL_o       = 0                         <<<<");
                print(">>>>     PWM_BL_o       = 0                         <<<<");
                print(">>>>     PWM_CL_o       = 0                         <<<<");
                print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            END IF;
        END IF;
    END PROCESS;

--------------------------------------------------------------------------
-- Name       : COUNT_PROC
-- Description: Counter to decide the number of iterations
--------------------------------------------------------------------------
COUNT_PROC:
    PROCESS(reset_tb,sys_clk_tb)
    BEGIN
        IF(reset_tb = '0') THEN
            counter <= (OTHERS => '0');
        ELSIF RISING_EDGE (sys_clk_tb) THEN
            IF(state = RESET_STATE) THEN
                counter <= counter + '1';
            END IF;
        END IF;
    END PROCESS;

s_midmatch_tb_ext <= ("000"& s_midmatch_tb);

s_flag_tb_pul_ext <= ("000"&s_flag_tb_pul);

--------------------------------------------------------------------------
-- Name       : PMW3PH_TB_FSM_PROC
-- Description: FSM implements the pwm3ph testbench controller operation
--------------------------------------------------------------------------
PMW3PH_TB_FSM_PROC:
    PROCESS(sys_clk_tb,reset_tb)
    BEGIN
        IF(reset_tb = '0') THEN
            state            <= IDLE;
            s_reset_tb      <= '0';
            s_start_tb      <= '0';
            s_en_pwm_tb     <= '0';
        ELSIF (RISING_EDGE(sys_clk_tb)) THEN
            CASE(state)IS
--------------------
-- IDLE state
--------------------
            WHEN IDLE =>
                IF(counter < x"00B") THEN
                    state  <= ENABLE_PWM;
                    s_en_pwm_tb <= '1';                    
                ELSE
                    state  <= IDLE;
                    s_en_pwm_tb <= '0';
                END IF;
--------------------
-- ENABLE_PWM state
--------------------
            WHEN ENABLE_PWM =>
                state <= ENABLE_PWM_WAIT;
                s_en_pwm_tb <= '0';
--------------------
-- ENABLE_PWM_WAIT state
--------------------
            WHEN ENABLE_PWM_WAIT  =>
                state <= MID_MATCH_COMPARE;
                s_en_pwm_tb <= '1';               
                s_start_tb  <= '1';
--------------------
-- MID_MATCH_COMPARE state
--------------------
            WHEN MID_MATCH_COMPARE =>
                s_start_tb  <= '0';
                IF(counter < x"00B") THEN
                    s_en_pwm_tb <= '1';
                ELSE
                    s_en_pwm_tb <= '0';
                END IF;
                    state <= OUTPUT_COMPARE;
--------------------
-- OUTPUT_COMPARE state
--------------------
            WHEN OUTPUT_COMPARE =>
                    IF(s_PWM_AH_tb_pul = '1') THEN
                        IF(s_error_count_pwmah_tb = x"000") THEN
                            print("                                                                 ");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                            print("   INPUTS                                                      ");
                            print_text_val("         VA            =  ",(to_integer(signed(s_va_tb))),"                        ");
                            print("                                                                ");
                            print("     OUTPUTS                                                    ");
                            print_text_val("         PWMAH_ON_TIME =  ",(to_integer(signed(s_cnt_pwmah_tb))),"                       ");
                            print(">>>>                                                           <<<<");
                            print(">>>>     STATUS            :  PASSED                           <<<<");
                            print(">>>>     DESCRIPTION       :  TB AND DUT OUTPUTS MATCH         <<<<");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        ELSE
                            print("                                                                 ");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                            print("   INPUTS                                                      ");
                            print_text_val("         VA            =  ",(to_integer(signed(s_va_tb))),"                        ");
                            print("                                                                ");
                            print("     OUTPUTS                                                    ");
                            print_text_val("         PWMAH_ON_TIME =  ",(to_integer(signed(s_cnt_pwmah_tb))),"                       ");
                            print(">>>>                                                           <<<<");
                            print(">>>>     STATUS            :  FAILED                           <<<<");
                            print(">>>>     DESCRIPTION       :  TB AND DUT OUTPUTS DO NOT MATCH  <<<<");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        END IF;
                    END IF;
                    IF(s_PWM_BH_tb_pul = '1') THEN
                        IF(s_error_count_pwmbh_tb = x"000") THEN
                            print("                                                                 ");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                            print("   INPUTS                                                      ");
                            print_text_val("         VB            =  ",(to_integer(signed(s_vb_tb))),"                        ");
                            print("                                                                ");
                            print("     OUTPUTS                                                    ");
                            print_text_val("         PWMBH_ON_TIME =  ",(to_integer(signed(s_cnt_pwmbh_tb))),"                       ");
                            print(">>>>                                                           <<<<");
                            print(">>>>     STATUS            :  PASSED                           <<<<");
                            print(">>>>     DESCRIPTION       :  TB AND DUT OUTPUTS MATCH         <<<<");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        ELSE
                            print("                                                                 ");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                            print("   INPUTS                                                      ");
                            print_text_val("         VB            =  ",(to_integer(signed(s_vb_tb))),"                        ");
                            print("                                                                ");
                            print("     OUTPUTS                                                    ");
                            print_text_val("         PWMBH_ON_TIME =  ",(to_integer(signed(s_cnt_pwmbh_tb))),"                       ");
                            print(">>>>                                                           <<<<");
                            print(">>>>     STATUS            :  FAILED                           <<<<");
                            print(">>>>     DESCRIPTION       :  TB AND DUT OUTPUTS DO NOT MATCH  <<<<");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        END IF;
                    END IF;
                    IF(s_PWM_CH_tb_pul = '1') THEN
                        IF(s_error_count_pwmch_tb = x"000") THEN
                            print("                                                                 ");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                            print("   INPUTS                                                      ");
                            print_text_val("         VC            =  ",(to_integer(signed(s_vc_tb))),"                        ");
                            print("                                                                ");
                            print("     OUTPUTS                                                    ");
                            print_text_val("         PWMCH_ON_TIME =  ",(to_integer(signed(s_cnt_pwmch_tb))),"                       ");
                            print(">>>>                                                           <<<<");
                            print(">>>>     STATUS            :  PASSED                           <<<<");
                            print(">>>>     DESCRIPTION       :  TB AND DUT OUTPUTS MATCH         <<<<");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        ELSE
                            print("                                                                 ");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                            print("   INPUTS                                                      ");
                            print_text_val("         VC            =  ",(to_integer(signed(s_vc_tb))),"                        ");
                            print("                                                                ");
                            print("     OUTPUTS                                                    ");
                            print_text_val("         PWMCH_ON_TIME =  ",(to_integer(signed(s_cnt_pwmch_tb))),"                       ");
                            print(">>>>                                                           <<<<");
                            print(">>>>     STATUS            :  FAILED                           <<<<");
                            print(">>>>     DESCRIPTION       :  TB AND DUT OUTPUTS DO NOT MATCH  <<<<");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        END IF;
                    END IF;

                     IF(s_PWM_AL_tb_pul = '1') THEN
                        IF(s_error_count_pwmal_tb = x"000") THEN
                            print("                                                                 ");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                            print("   INPUTS                                                      ");
                            print_text_val("         VA            =  ",(to_integer(signed(s_va_tb))),"                        ");
                            print("                                                                ");
                            print("     OUTPUTS                                                    ");
                            print_text_val("        PWMAL_OFF_TIME =  ",(to_integer(signed(s_cnt_pwmal_tb))),"                       ");
                            print(">>>>                                                           <<<<");
                            print(">>>>     STATUS            :  PASSED                           <<<<");
                            print(">>>>     DESCRIPTION       :  TB AND DUT OUTPUTS MATCH         <<<<");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        ELSE
                            print("                                                                 ");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                            print("   INPUTS                                                      ");
                            print_text_val("         VA            =  ",(to_integer(signed(s_va_tb))),"                        ");
                            print("                                                                ");
                            print("     OUTPUTS                                                    ");
                            print_text_val("        PWMAL_OFF_TIME =  ",(to_integer(signed(s_cnt_pwmal_tb))),"                       ");
                            print(">>>>                                                           <<<<");
                            print(">>>>     STATUS            :  FAILED                           <<<<");
                            print(">>>>     DESCRIPTION       :  TB AND DUT OUTPUTS DO NOT MATCH  <<<<");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        END IF;
                    END IF;
                    IF(s_PWM_BL_tb_pul = '1') THEN
                        IF(s_error_count_pwmbl_tb = x"000") THEN
                            print("                                                                 ");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                            print("   INPUTS                                                      ");
                            print_text_val("         VB            =  ",(to_integer(signed(s_vb_tb))),"                        ");
                            print("                                                                ");
                            print("     OUTPUTS                                                    ");
                            print_text_val("        PWMBL_OFF_TIME =  ",(to_integer(signed(s_cnt_pwmbl_tb))),"                       ");
                            print(">>>>                                                           <<<<");
                            print(">>>>     STATUS            :  PASSED                           <<<<");
                            print(">>>>     DESCRIPTION       :  TB AND DUT OUTPUTS MATCH         <<<<");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        ELSE
                            print("                                                                 ");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                            print("   INPUTS                                                      ");
                            print_text_val("         VB            =  ",(to_integer(signed(s_vb_tb))),"                        ");
                            print("                                                                ");
                            print("     OUTPUTS                                                    ");
                            print_text_val("        PWMBL_OFF_TIME =  ",(to_integer(signed(s_cnt_pwmbl_tb))),"                       ");
                            print(">>>>                                                           <<<<");
                            print(">>>>     STATUS            :  FAILED                           <<<<");
                            print(">>>>     DESCRIPTION       :  TB AND DUT OUTPUTS DO NOT MATCH  <<<<");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        END IF;
                    END IF;
                    IF(s_PWM_CL_tb_pul = '1') THEN
                        IF(s_error_count_pwmcl_tb = x"000") THEN
                            print("                                                                 ");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                            print("   INPUTS                                                      ");
                            print_text_val("         VC            =  ",(to_integer(signed(s_vc_tb))),"                        ");
                            print("                                                                ");
                            print("     OUTPUTS                                                    ");
                            print_text_val("        PWMCL_OFF_TIME =  ",(to_integer(signed(s_cnt_pwmcl_tb))),"                       ");
                            print(">>>>                                                           <<<<");
                            print(">>>>     STATUS            :  PASSED                           <<<<");
                            print(">>>>     DESCRIPTION       :  TB AND DUT OUTPUTS MATCH         <<<<");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        ELSE
                            print("                                                                 ");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                            print("   INPUTS                                                      ");
                            print_text_val("         VC            =  ",(to_integer(signed(s_vc_tb))),"                        ");
                            print("                                                                ");
                            print("     OUTPUTS                                                    ");
                            print_text_val("        PWMCL_OFF_TIME =  ",(to_integer(signed(s_cnt_pwmcl_tb))),"                       ");
                            print(">>>>                                                           <<<<");
                            print(">>>>     STATUS            :  FAILED                           <<<<");
                            print(">>>>     DESCRIPTION       :  TB AND DUT OUTPUTS DO NOT MATCH  <<<<");
                            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        END IF;
                    END IF;
                IF(s_counter_tb < s_pwm_period_tb ) THEN
                    state <= OUTPUT_COMPARE;
                ELSE
                    IF(s_midmatch_tb = '1' AND s_flag_tb_pul = '1') THEN
                        print("                                                                 ");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        print_text_val("|  TESTCASE   :  ",(to_integer(signed(counter))),"                                               |");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        print("   INPUTS                                                      ");
                        print_text_val("         PERIOD            =  ",(to_integer(signed(s_pwm_period_tb))),"                        ");
                        print("                                                                ");
                        print("     OUTPUTS                                                    ");
                        print_text_val("         DUT_MIDMATCH      =  ",(to_integer(signed(s_midmatch_tb_ext))),"                       ");
                        print_text_val("         TB_MIDMATCH       =  ",(to_integer(signed(s_flag_tb_pul_ext))),"                       ");
                        print(">>>>                                                           <<<<");
                        print(">>>>     STATUS            :  PASSED                           <<<<");
                        print(">>>>     DESCRIPTION       :  TB AND DUT OUTPUTS MATCH         <<<<");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        state               <= RESET_STATE;
                        s_reset_tb  <= '1';
                    ELSE
                        state               <= RESET_STATE;
                        s_reset_tb          <= '1';
                        print("                                                                 ");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        print_text_val("|  TESTCASE   :  ",(to_integer(signed(counter))),"                                               |");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        print("   INPUTS                                                      ");
                        print_text_val("         PERIOD            =  ",(to_integer(signed(s_pwm_period_tb))),"                        ");
                        print("                                                                ");
                        print("     OUTPUTS                                                    ");
                        print_text_val("         DUT_MIDMATCH      =  ",(to_integer(signed(s_midmatch_tb_ext))),"                       ");
                        print_text_val("         TB_MIDMATCH       =  ",(to_integer(signed(s_flag_tb_pul_ext))),"                       ");
                        print(">>>>                                                           <<<<");
                        print(">>>>     STATUS            :  FAILED                           <<<<");
                        print(">>>>     DESCRIPTION       :  TB AND DUT OUTPUTS DO NOT MATCH         <<<<");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                    END IF;
                END IF;
--------------------
-- RESET_STATE state
--------------------
            WHEN RESET_STATE =>
                s_reset_tb  <= '0';
                IF(counter = x"00A") THEN
                    state <= IDLE;
                    print("");
                    print("");
                    print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                    print("<<<<                  END OF PWM3H IP SIMULATION               >>>>");
                    print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                END IF;
                state <= IDLE;
--------------------
-- OTHERS state
--------------------
            WHEN OTHERS =>
                state               <= IDLE;
            END CASE;
        END IF;
    END PROCESS;
--------------------------------------------------------------------------
-- Name       : INPUT_DRIVER_PROC
-- Description: Process to provide the input test vectors
--------------------------------------------------------------------------
-----------------------
--VA
-----------------------
PROCESS(reset_tb,sys_clk_tb)
  VARIABLE seed1, seed2: integer :=7;
  VARIABLE rand: real;
  VARIABLE int_rand: integer;
BEGIN
	IF(reset_tb = '0') THEN
		s_va_tb   <= (OTHERS => '0');
	ELSIF  RISING_EDGE(sys_clk_tb) THEN
		IF(s_start_tb = '1') THEN
			UNIFORM(seed1,seed2, rand);
			int_rand := INTEGER(rand*256.0);
			s_va_tb <= std_logic_vector(to_signed(int_rand, 20));
		END IF;
	END IF;
END PROCESS;
-----------------------
--VB
-----------------------
PROCESS(reset_tb,sys_clk_tb)
  VARIABLE seed3, seed4: integer := 2;
  VARIABLE rand1: real;
  VARIABLE int_rand1: integer;
BEGIN
	IF(reset_tb = '0') THEN
		s_vb_tb<= (OTHERS => '0');
	ELSIF  RISING_EDGE(sys_clk_tb) THEN
		IF(s_start_tb = '1') THEN
			UNIFORM(seed3, seed4, rand1);
			int_rand1 := INTEGER(rand1*256.0);
			s_vb_tb <= std_logic_vector(to_unsigned(int_rand1, 20));
		END IF;
	END IF;
END PROCESS;
-----------------------
--VC
-----------------------
PROCESS(reset_tb,sys_clk_tb)
  VARIABLE seed5, seed6: integer := 10;
  VARIABLE rand2: real;
  VARIABLE int_rand2: integer;
BEGIN
	IF(reset_tb = '0') THEN
		s_vc_tb<= (OTHERS => '0');
	ELSIF  RISING_EDGE(sys_clk_tb) THEN
		IF(s_start_tb = '1') THEN
			UNIFORM(seed5, seed6, rand2);
			int_rand2 := INTEGER(rand2*256.0);
			s_vc_tb <= std_logic_vector(to_unsigned(int_rand2, 20));
		END IF;
	END IF;
END PROCESS;
-----------------------
--PERIOD
-----------------------
PROCESS(reset_tb,sys_clk_tb)
  VARIABLE seed7, seed8: integer := 11;
  VARIABLE rand3: real;
  VARIABLE int_rand3: integer;
BEGIN
	IF(reset_tb = '0') THEN
		s_pwm_period_tb<= (OTHERS => '0');
	ELSIF  RISING_EDGE(sys_clk_tb) THEN
		IF(s_start_tb = '1') THEN
			UNIFORM(seed7, seed8, rand3);
			int_rand3 := INTEGER(rand3*4096.0);
			s_pwm_period_tb <= std_logic_vector(to_unsigned(int_rand3, 18));
		END IF;
	END IF;
END PROCESS;
-----------------------
--DELAY_TIME
-----------------------
PROCESS(reset_tb,sys_clk_tb)
  VARIABLE seed9, seed10: integer := 12;
  VARIABLE rand4: real;
  VARIABLE int_rand4: integer;
BEGIN
	IF(reset_tb = '0') THEN
		s_delay_time_tb<= (OTHERS => '0');
	ELSIF  RISING_EDGE(sys_clk_tb) THEN
		IF(s_start_tb = '1') THEN
			UNIFORM(seed9, seed10, rand4);
			int_rand4 := INTEGER(rand4*4096.0);
			s_delay_time_tb <= std_logic_vector(to_unsigned(int_rand4, 18));
		END IF;
	END IF;
END PROCESS;

--------------------------------------------------------------------------
-- Name       : TB_MODEL_PROC
-- Description: Process to model the pwm3ph implementation
--------------------------------------------------------------------------
TB_MODEL_PROC:
    PROCESS(reset_tb,sys_clk_tb)
    BEGIN
        IF(reset_tb = '0') THEN
            s_counter_tb      <= (OTHERS => '0');
            s_flag_tb              <= '0';
            s_flag_tb_dly     <= '0';
        ELSIF RISING_EDGE(sys_clk_tb) THEN
            IF(s_en_pwm_tb = '1') THEN
                IF(s_counter_tb = (s_pwm_period_tb - '1')) THEN
                    s_flag_tb <= '1';
                ELSIF(s_counter_tb = "00"&x"0001") THEN
                    s_flag_tb <= '0';
                END IF;
                IF(s_flag_tb = '0') THEN
                    s_counter_tb <= s_counter_tb + '1';
                ELSE
                    s_counter_tb <= s_counter_tb - '1';
                END IF;
            ELSE
                s_counter_tb	<= (OTHERS=>'0');
                s_flag_tb <= '0';
            END IF;
            s_flag_tb_dly  <= s_flag_tb;
        END IF;
    END PROCESS;

s_flag_tb_pul <=  (s_midmatch_up OR s_midmatch_down )  WHEN (s_en_dual_trig = '1')ELSE 
                   s_midmatch_up;
                   
s_midmatch_up   <= s_flag_tb AND (NOT(s_flag_tb_dly));
s_midmatch_down <= NOT(s_flag_tb) AND (s_flag_tb_dly);

--------------------------------------------------------------------------
-- Name       : DELAY_PROC
-- Description: Process to delay the input signal by one system clock
--------------------------------------------------------------------------
DELAY_PROC:
    PROCESS(reset_tb,sys_clk_tb)
    BEGIN
        IF(reset_tb = '0') THEN
            s_PWM_AH_tb_dly   <= '0';
            s_PWM_BH_tb_dly   <= '0';
            s_PWM_CH_tb_dly   <= '0';
            s_PWM_AL_tb_dly   <= '0';
            s_PWM_BL_tb_dly   <= '0';
            s_PWM_CL_tb_dly   <= '0';
        ELSIF RISING_EDGE (sys_clk_tb) THEN
            s_PWM_AH_tb_dly   <= s_PWM_AH_tb;
            s_PWM_BH_tb_dly   <= s_PWM_BH_tb;
            s_PWM_CH_tb_dly   <= s_PWM_CH_tb;
            s_PWM_AL_tb_dly   <= s_PWM_AL_tb;
            s_PWM_BL_tb_dly   <= s_PWM_BL_tb;
            s_PWM_CL_tb_dly   <= s_PWM_CL_tb;
        END IF;
    END PROCESS;
--------------------------------------------------------------------------
-- Name       : PUL_DELAY_PROC
-- Description: Process to delay the input pulse by one system clock
--------------------------------------------------------------------------
PUL_DELAY_PROC:
    PROCESS(reset_tb,sys_clk_tb)
    BEGIN
        IF(reset_tb = '0') THEN
            s_PWM_AH_tb_pul_dly   <= '0';
            s_PWM_BH_tb_pul_dly   <= '0';
            s_PWM_CH_tb_pul_dly   <= '0';
            s_PWM_AL_tb_pul_dly   <= '0';
            s_PWM_BL_tb_pul_dly   <= '0';
            s_PWM_CL_tb_pul_dly   <= '0';
        ELSIF RISING_EDGE (sys_clk_tb) THEN
            s_PWM_AH_tb_pul_dly   <= s_PWM_AH_tb_pul;
            s_PWM_BH_tb_pul_dly   <= s_PWM_BH_tb_pul;
            s_PWM_CH_tb_pul_dly   <= s_PWM_CH_tb_pul;
            s_PWM_AL_tb_pul_dly   <= s_PWM_AL_tb_pul;
            s_PWM_BL_tb_pul_dly   <= s_PWM_BL_tb_pul;
            s_PWM_CL_tb_pul_dly   <= s_PWM_CL_tb_pul;
        END IF;
    END PROCESS;

--------------------------------------------------------------------------
-- Name       : PUL_GEN_PROC
-- Description: Process to generate pulses to detect on time and off time
--------------------------------------------------------------------------
s_PWM_AH_tb_pul     <= NOT(s_PWM_AH_tb) AND s_PWM_AH_tb_dly;
s_PWM_BH_tb_pul     <= NOT(s_PWM_BH_tb) AND s_PWM_BH_tb_dly;
s_PWM_CH_tb_pul     <= NOT(s_PWM_CH_tb) AND s_PWM_CH_tb_dly;

s_PWM_AL_tb_pul     <= s_PWM_AL_tb AND NOT(s_PWM_AL_tb_dly);
s_PWM_BL_tb_pul     <= s_PWM_BL_tb AND NOT(s_PWM_BL_tb_dly);
s_PWM_CL_tb_pul     <= s_PWM_CL_tb AND NOT(s_PWM_CL_tb_dly);
--------------------------------------------------------------------------
-- Name       : ON_TIME_OFF_TIME_CAL_PROC
-- Description: Process to compute the on time and off time for pwm3h output signals
--------------------------------------------------------------------------
ON_TIME_OFF_TIME_CAL_PROC:
    PROCESS(reset_tb,sys_clk_tb)
    BEGIN
        IF(reset_tb = '0') THEN
            s_cnt_pwmah_tb    <= (OTHERS => '0');
            s_cnt_pwmbh_tb    <= (OTHERS => '0');
            s_cnt_pwmch_tb    <= (OTHERS => '0');
            s_cnt_pwmal_tb    <= (OTHERS => '0');
            s_cnt_pwmbl_tb    <= (OTHERS => '0');
            s_cnt_pwmcl_tb    <= (OTHERS => '0');
        ELSIF RISING_EDGE (sys_clk_tb) THEN
            IF(s_en_pwm_tb = '1') THEN
                IF(s_PWM_AH_tb = '1') THEN
                    s_cnt_pwmah_tb <= s_cnt_pwmah_tb + '1';
                END IF;
                IF(s_PWM_BH_tb = '1') THEN
                    s_cnt_pwmbh_tb <= s_cnt_pwmbh_tb + '1';
                END IF;
                IF(s_PWM_CH_tb = '1') THEN
                    s_cnt_pwmch_tb <= s_cnt_pwmch_tb + '1';
                END IF;
    
            ELSE
                s_cnt_pwmah_tb    <= (OTHERS => '0');
                s_cnt_pwmbh_tb    <= (OTHERS => '0');
                s_cnt_pwmch_tb    <= (OTHERS => '0');
            END IF;    
    
            IF(s_en_pwm_tb_dly = '1') THEN
                IF(s_PWM_AL_tb = '0') THEN
                    s_cnt_pwmal_tb <= s_cnt_pwmal_tb + '1';
                END IF;
                IF(s_PWM_BL_tb = '0') THEN
                    s_cnt_pwmbl_tb <= s_cnt_pwmbl_tb + '1';
                END IF;
                IF(s_PWM_CL_tb = '0') THEN
                    s_cnt_pwmcl_tb <= s_cnt_pwmcl_tb + '1';
                END IF;
            ELSE
                s_cnt_pwmal_tb    <= (OTHERS => '0');
                s_cnt_pwmbl_tb    <= (OTHERS => '0');
                s_cnt_pwmcl_tb    <= (OTHERS => '0');
            END IF;
        END IF;
    END PROCESS;

--------------------------------------------------------------------------
-- Name       : ERROR_COMPUTE_PROC
-- Description: Process to compute the error between actual and desired values
--------------------------------------------------------------------------
ERROR_COMPUTE_PROC:
    PROCESS(reset_tb,sys_clk_tb)
    BEGIN
        ERROR_COMPUTE_1 (reset_tb,sys_clk_tb,s_PWM_AH_tb_pul,s_PWM_AH_tb_pul_dly,s_va_tb,s_cnt_pwmah_tb,s_error_pwmah_tb,s_error_count_pwmah_tb);
        ERROR_COMPUTE_1 (reset_tb,sys_clk_tb,s_PWM_BH_tb_pul,s_PWM_BH_tb_pul_dly,s_vb_tb,s_cnt_pwmbh_tb,s_error_pwmbh_tb,s_error_count_pwmbh_tb);
        ERROR_COMPUTE_1 (reset_tb,sys_clk_tb,s_PWM_CH_tb_pul,s_PWM_CH_tb_pul_dly,s_vc_tb,s_cnt_pwmch_tb,s_error_pwmch_tb,s_error_count_pwmch_tb);
        ERROR_COMPUTE_1 (reset_tb,sys_clk_tb,s_PWM_AL_tb_pul,s_PWM_AL_tb_pul_dly,s_va_tb,s_cnt_pwmal_tb,s_error_pwmal_tb,s_error_count_pwmal_tb);
        ERROR_COMPUTE_1 (reset_tb,sys_clk_tb,s_PWM_BL_tb_pul,s_PWM_BL_tb_pul_dly,s_vb_tb,s_cnt_pwmbl_tb,s_error_pwmbl_tb,s_error_count_pwmbl_tb);
        ERROR_COMPUTE_1 (reset_tb,sys_clk_tb,s_PWM_CL_tb_pul,s_PWM_CL_tb_pul_dly,s_vc_tb,s_cnt_pwmcl_tb,s_error_pwmcl_tb,s_error_count_pwmcl_tb);
    END PROCESS;
--=================================================================================================
-- Component Instantiations
--=================================================================================================
-------------------------------------------------
-- PWM3PH_UUT_INST
-------------------------------------------------
PWM3PH_UUT_INST: pwm3ph
PORT MAP(
    reset_i                            => reset_tb,
    sys_clk_i                          => sys_clk_tb,
    en_pwm_i                           => s_en_pwm_tb,
    va_i              	   		   	   => s_va_tb(17 DOWNTO 0),
    en_dual_trig_i                     => s_en_dual_trig,
    vb_i                	   		   => s_vb_tb(17 DOWNTO 0),
    vc_i                	   		   => s_vc_tb(17 DOWNTO 0),
    pwm_period_i               	   	   => s_pwm_period_tb,
    dead_time_i           	   		   => (OTHERS => '0'),
    delay_time_i           	   		   => (OTHERS => '0'),
    midmatch_o                         => s_midmatch_tb,
    PWM_AH_o                           => s_PWM_AH_tb,
    PWM_BH_o                           => s_PWM_BH_tb,
    PWM_CH_o                           => s_PWM_CH_tb,
    PWM_AL_o                           => s_PWM_AL_tb,
    PWM_BL_o                           => s_PWM_BL_tb,
    PWM_CL_o                           => s_PWM_CL_tb
);
END behavioral;