#Build: Synplify Pro I-2014.03M-SP1, Build 097R, Oct  9 2014
#install: C:\Microsemi\Libero_v11.5\Synopsys\synplify_I201403MSP1
#OS: Windows 7 6.1
#Hostname: W764-BATTUP

#Implementation: synthesis

Synopsys VHDL Compiler, version comp201403sp1p1, Build 095R, built Oct  9 2014
@N|Running in 64-bit mode
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

@N: CD720 :"C:\Microsemi\Libero_v11.5\Synopsys\synplify_I201403MSP1\lib\vhd2008\std.vhd":146:18:146:21|Setting time resolution to ns
@N:"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\work\MC_System\MC_System.vhd":17:7:17:15|Top entity is set to MC_System.
VHDL syntax check successful!
@N: CD231 :"C:\Microsemi\Libero_v11.5\Synopsys\synplify_I201403MSP1\lib\vhd2008\std1164.vhd":913:16:913:17|Using onehot encoding for type mvl9plus ('U'="1000000000")
@N: CD630 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\work\MC_System\MC_System.vhd":17:7:17:15|Synthesizing work.mc_system.rtl 
@N: CD630 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\work\MC_System_sb\MC_System_sb.vhd":20:7:20:18|Synthesizing work.mc_system_sb.rtl 
@N: CD630 :"C:\Microsemi\Libero_v11.5\Synopsys\synplify_I201403MSP1\lib\generic\smartfusion2.vhd":779:10:779:17|Synthesizing smartfusion2.sysreset.syn_black_box 
Post processing for smartfusion2.sysreset.syn_black_box
@N: CD630 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\work\MC_System_sb_MSS\MC_System_sb_MSS.vhd":17:7:17:22|Synthesizing work.mc_system_sb_mss.rtl 
@N: CD630 :"C:\Microsemi\Libero_v11.5\Synopsys\synplify_I201403MSP1\lib\generic\smartfusion2.vhd":434:10:434:14|Synthesizing smartfusion2.bibuf.syn_black_box 
Post processing for smartfusion2.bibuf.syn_black_box
@N: CD630 :"C:\Microsemi\Libero_v11.5\Synopsys\synplify_I201403MSP1\lib\generic\smartfusion2.vhd":403:10:403:14|Synthesizing smartfusion2.inbuf.syn_black_box 
Post processing for smartfusion2.inbuf.syn_black_box
@N: CD630 :"C:\Microsemi\Libero_v11.5\Synopsys\synplify_I201403MSP1\lib\generic\smartfusion2.vhd":423:10:423:16|Synthesizing smartfusion2.tribuff.syn_black_box 
Post processing for smartfusion2.tribuff.syn_black_box
@N: CD630 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\work\MC_System_sb_MSS\MC_System_sb_MSS_syn.vhd":10:7:10:13|Synthesizing work.mss_010.def_arch 
Post processing for work.mss_010.def_arch
Post processing for work.mc_system_sb_mss.rtl
@N: CD630 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd":8:7:8:31|Synthesizing work.mc_system_sb_fabosc_0_osc.def_arch 
@N: CD630 :"C:\Microsemi\Libero_v11.5\Synopsys\synplify_I201403MSP1\lib\generic\smartfusion2.vhd":562:10:562:15|Synthesizing smartfusion2.clkint.syn_black_box 
Post processing for smartfusion2.clkint.syn_black_box
@N: CD630 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\SgCore\OSC\1.0.103\osc_comps.vhd":19:7:19:20|Synthesizing work.rcosc_25_50mhz.def_arch 
Post processing for work.rcosc_25_50mhz.def_arch
@N: CD630 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\SgCore\OSC\1.0.103\osc_comps.vhd":79:7:79:24|Synthesizing work.rcosc_25_50mhz_fab.def_arch 
Post processing for work.rcosc_25_50mhz_fab.def_arch
Post processing for work.mc_system_sb_fabosc_0_osc.def_arch
@W: CL240 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd":16:10:16:19|XTLOSC_O2F is not assigned a value (floating) -- simulation mismatch possible. 
@W: CL240 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd":15:10:15:19|XTLOSC_CCC is not assigned a value (floating) -- simulation mismatch possible. 
@W: CL240 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd":14:10:14:23|RCOSC_1MHZ_O2F is not assigned a value (floating) -- simulation mismatch possible. 
@W: CL240 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd":13:10:13:23|RCOSC_1MHZ_CCC is not assigned a value (floating) -- simulation mismatch possible. 
@N: CD630 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":27:7:27:16|Synthesizing work.coreresetp.rtl 
@W: CD434 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":477:8:477:25|Signal soft_ext_reset_out in the sensitivity list is not used in the process
@W: CD434 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":478:8:478:21|Signal soft_reset_f2m in the sensitivity list is not used in the process
@W: CD434 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":479:8:479:20|Signal soft_m3_reset in the sensitivity list is not used in the process
@W: CD434 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":480:8:480:37|Signal soft_mddr_ddr_axi_s_core_reset in the sensitivity list is not used in the process
@W: CD434 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":481:8:481:27|Signal soft_fddr_core_reset in the sensitivity list is not used in the process
@W: CD434 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":482:8:482:27|Signal soft_sdif0_phy_reset in the sensitivity list is not used in the process
@W: CD434 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":483:8:483:28|Signal soft_sdif0_core_reset in the sensitivity list is not used in the process
@W: CD434 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":484:8:484:27|Signal soft_sdif1_phy_reset in the sensitivity list is not used in the process
@W: CD434 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":485:8:485:28|Signal soft_sdif1_core_reset in the sensitivity list is not used in the process
@W: CD434 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":486:8:486:27|Signal soft_sdif2_phy_reset in the sensitivity list is not used in the process
@W: CD434 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":487:8:487:28|Signal soft_sdif2_core_reset in the sensitivity list is not used in the process
@W: CD434 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":488:8:488:27|Signal soft_sdif3_phy_reset in the sensitivity list is not used in the process
@W: CD434 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":489:8:489:28|Signal soft_sdif3_core_reset in the sensitivity list is not used in the process
@W: CD434 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":490:8:490:30|Signal soft_sdif0_0_core_reset in the sensitivity list is not used in the process
@W: CD434 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":491:8:491:30|Signal soft_sdif0_1_core_reset in the sensitivity list is not used in the process
Post processing for work.coreresetp.rtl
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1519:8:1519:9|Pruning register count_ddr_2(13 downto 0)  
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1495:8:1495:9|Pruning register count_sdif3_2(12 downto 0)  
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1471:8:1471:9|Pruning register count_sdif2_2(12 downto 0)  
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1447:8:1447:9|Pruning register count_sdif1_2(12 downto 0)  
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1423:8:1423:9|Pruning register count_sdif0_2(12 downto 0)  
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning register count_ddr_enable_rcosc_2  
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning register count_ddr_enable_q1_2  
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning register count_sdif3_enable_rcosc_2  
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning register count_sdif2_enable_rcosc_2  
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning register count_sdif1_enable_rcosc_2  
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning register count_sdif0_enable_rcosc_2  
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning register count_sdif3_enable_q1_2  
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning register count_sdif2_enable_q1_2  
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning register count_sdif1_enable_q1_2  
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning register count_sdif0_enable_q1_2  
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1311:8:1311:9|Pruning register count_sdif3_enable_3  
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1252:8:1252:9|Pruning register count_sdif2_enable_3  
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1193:8:1193:9|Pruning register count_sdif1_enable_3  
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1134:8:1134:9|Pruning register count_sdif0_enable_3  
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Pruning register count_ddr_enable_3  
@N: CL177 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1331:8:1331:9|Sharing sequential element M3_RESET_N_int.
@N: CL177 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif2_spll_lock_q1.
@N: CL177 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif1_spll_lock_q1.
@N: CL177 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif0_spll_lock_q1.
@N: CL177 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element fpll_lock_q1.
@W: CL190 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1376:8:1376:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Pruning register release_ext_reset  
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1376:8:1376:9|Pruning register EXT_RESET_OUT_int  
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1376:8:1376:9|Pruning register sm2_state(2 downto 0)  
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":792:8:792:9|Pruning register sm2_areset_n_q1  
@W: CL169 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":792:8:792:9|Pruning register sm2_areset_n_clk_base  
@N: CD630 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":34:7:34:14|Synthesizing coreapb3_lib.coreapb3.coreapb3_arch 
@W: CD604 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":650:16:650:29|OTHERS clause is not synthesized 
@W: CD434 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":1438:41:1438:46|Signal infill in the sensitivity list is not used in the process
@W: CD638 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":601:7:601:15|Signal ia_prdata is undriven 
@N: CD630 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3_muxptob3.vhd":33:7:33:23|Synthesizing coreapb3_lib.coreapb3_muxptob3.coreapb3_muxptob3_arch 
Post processing for coreapb3_lib.coreapb3_muxptob3.coreapb3_muxptob3_arch
Post processing for coreapb3_lib.coreapb3.coreapb3_arch
@N: CD630 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\work\MC_System_sb\CCC_0\MC_System_sb_CCC_0_FCCC.vhd":8:7:8:29|Synthesizing work.mc_system_sb_ccc_0_fccc.def_arch 
@N: CD630 :"C:\Microsemi\Libero_v11.5\Synopsys\synplify_I201403MSP1\lib\generic\smartfusion2.vhd":787:10:787:12|Synthesizing smartfusion2.ccc.syn_black_box 
Post processing for smartfusion2.ccc.syn_black_box
@N: CD630 :"C:\Microsemi\Libero_v11.5\Synopsys\synplify_I201403MSP1\lib\generic\smartfusion2.vhd":569:10:569:12|Synthesizing smartfusion2.gnd.syn_black_box 
Post processing for smartfusion2.gnd.syn_black_box
@N: CD630 :"C:\Microsemi\Libero_v11.5\Synopsys\synplify_I201403MSP1\lib\generic\smartfusion2.vhd":575:10:575:12|Synthesizing smartfusion2.vcc.syn_black_box 
Post processing for smartfusion2.vcc.syn_black_box
Post processing for work.mc_system_sb_ccc_0_fccc.def_arch
Post processing for work.mc_system_sb.rtl
Post processing for work.mc_system.rtl
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":74:0:74:4|Input IADDR is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":75:0:75:6|Input PRESETN is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":76:0:76:3|Input PCLK is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":108:0:108:7|Input PRDATAS2 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":109:0:109:7|Input PRDATAS3 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":110:0:110:7|Input PRDATAS4 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":111:0:111:7|Input PRDATAS5 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":112:0:112:7|Input PRDATAS6 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":113:0:113:7|Input PRDATAS7 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":114:0:114:7|Input PRDATAS8 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":115:0:115:7|Input PRDATAS9 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":116:0:116:8|Input PRDATAS10 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":117:0:117:8|Input PRDATAS11 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":118:0:118:8|Input PRDATAS12 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":119:0:119:8|Input PRDATAS13 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":120:0:120:8|Input PRDATAS14 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":121:0:121:8|Input PRDATAS15 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":125:0:125:7|Input PREADYS2 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":126:0:126:7|Input PREADYS3 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":127:0:127:7|Input PREADYS4 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":128:0:128:7|Input PREADYS5 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":129:0:129:7|Input PREADYS6 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":130:0:130:7|Input PREADYS7 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":131:0:131:7|Input PREADYS8 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":132:0:132:7|Input PREADYS9 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":133:0:133:8|Input PREADYS10 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":134:0:134:8|Input PREADYS11 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":135:0:135:8|Input PREADYS12 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":136:0:136:8|Input PREADYS13 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":137:0:137:8|Input PREADYS14 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":138:0:138:8|Input PREADYS15 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":142:0:142:8|Input PSLVERRS2 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":143:0:143:8|Input PSLVERRS3 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":144:0:144:8|Input PSLVERRS4 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":145:0:145:8|Input PSLVERRS5 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":146:0:146:8|Input PSLVERRS6 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":147:0:147:8|Input PSLVERRS7 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":148:0:148:8|Input PSLVERRS8 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":149:0:149:8|Input PSLVERRS9 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":150:0:150:9|Input PSLVERRS10 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":151:0:151:9|Input PSLVERRS11 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":152:0:152:9|Input PSLVERRS12 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":153:0:153:9|Input PSLVERRS13 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":154:0:154:9|Input PSLVERRS14 is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core\coreapb3.vhd":155:0:155:9|Input PSLVERRS15 is unused
@N: CL177 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif0_spll_lock_q2.
@N: CL177 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element fpll_lock_q2.
@N: CL177 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif1_spll_lock_q2.
@N: CL177 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif2_spll_lock_q2.
@N: CL201 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1311:8:1311:9|Trying to extract state machine for register sdif3_state
Extracted state machine for register sdif3_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1252:8:1252:9|Trying to extract state machine for register sdif2_state
Extracted state machine for register sdif2_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1193:8:1193:9|Trying to extract state machine for register sdif1_state
Extracted state machine for register sdif1_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1134:8:1134:9|Trying to extract state machine for register sdif0_state
Extracted state machine for register sdif0_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Trying to extract state machine for register sm0_state
Extracted state machine for register sm0_state
State machine has 7 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":96:4:96:12|Input CLK_LTSSM is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":123:4:123:12|Input FPLL_LOCK is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":126:4:126:18|Input SDIF0_SPLL_LOCK is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":135:4:135:18|Input SDIF1_SPLL_LOCK is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":139:4:139:18|Input SDIF2_SPLL_LOCK is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":143:4:143:18|Input SDIF3_SPLL_LOCK is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":157:4:157:13|Input SDIF0_PSEL is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":158:4:158:15|Input SDIF0_PWRITE is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":159:4:159:15|Input SDIF0_PRDATA is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":160:4:160:13|Input SDIF1_PSEL is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":161:4:161:15|Input SDIF1_PWRITE is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":162:4:162:15|Input SDIF1_PRDATA is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":163:4:163:13|Input SDIF2_PSEL is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":164:4:164:15|Input SDIF2_PWRITE is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":165:4:165:15|Input SDIF2_PRDATA is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":166:4:166:13|Input SDIF3_PSEL is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":167:4:167:15|Input SDIF3_PWRITE is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":168:4:168:15|Input SDIF3_PRDATA is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":174:4:174:21|Input SOFT_EXT_RESET_OUT is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":175:4:175:17|Input SOFT_RESET_F2M is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":176:4:176:16|Input SOFT_M3_RESET is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":177:4:177:33|Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":178:4:178:23|Input SOFT_FDDR_CORE_RESET is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":179:4:179:23|Input SOFT_SDIF0_PHY_RESET is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":180:4:180:24|Input SOFT_SDIF0_CORE_RESET is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":181:4:181:23|Input SOFT_SDIF1_PHY_RESET is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":182:4:182:24|Input SOFT_SDIF1_CORE_RESET is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":183:4:183:23|Input SOFT_SDIF2_PHY_RESET is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":184:4:184:24|Input SOFT_SDIF2_CORE_RESET is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":185:4:185:23|Input SOFT_SDIF3_PHY_RESET is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":186:4:186:24|Input SOFT_SDIF3_CORE_RESET is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":190:4:190:26|Input SOFT_SDIF0_0_CORE_RESET is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":191:4:191:26|Input SOFT_SDIF0_1_CORE_RESET is unused
@W: CL159 :"D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd":10:10:10:12|Input XTL is unused
@END

At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 88MB peak: 90MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Mar 10 11:25:04 2015

###########################################################]
Synopsys Netlist Linker, version comp201403sp1p1, Build 095R, built Oct  9 2014
@N|Running in 64-bit mode

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Mar 10 11:25:05 2015

###########################################################]
Pre-mapping Report

Synopsys Generic Technology Pre-mapping, Version mapact, Build 1350R, Built Oct 16 2014 10:02:37
Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
Product Version I-2014.03M-SP1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@L: D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\synthesis\MC_System_scck.rpt 
Printing clock  summary report in "D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\synthesis\MC_System_scck.rpt" file 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 107MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 107MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 107MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 108MB)

@W: BN132 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Removing sequential instance MC_System_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int,  because it is equivalent to instance MC_System_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Removing sequential instance SDIF_RELEASED_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1134:8:1134:9|Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1134:8:1134:9|Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1193:8:1193:9|Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1193:8:1193:9|Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1252:8:1252:9|Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1252:8:1252:9|Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1311:8:1311:9|Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1311:8:1311:9|Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Removing sequential instance INIT_DONE_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1134:8:1134:9|Removing sequential instance sdif0_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1193:8:1193:9|Removing sequential instance sdif1_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1252:8:1252:9|Removing sequential instance sdif2_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1311:8:1311:9|Removing sequential instance sdif3_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Removing sequential instance sm0_state[0:6] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":922:8:922:9|Removing sequential instance CONFIG2_DONE_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":803:8:803:9|Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":814:8:814:9|Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":825:8:825:9|Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":836:8:836:9|Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Removing sequential instance sdif3_spll_lock_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":908:8:908:9|Removing sequential instance CONFIG1_DONE_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif3_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif2_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif1_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":922:8:922:9|Removing sequential instance CONFIG2_DONE_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":803:8:803:9|Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":814:8:814:9|Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":825:8:825:9|Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":836:8:836:9|Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Removing sequential instance sdif3_spll_lock_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":908:8:908:9|Removing sequential instance CONFIG1_DONE_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif0_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance ddr_settled_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif3_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif2_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif1_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif0_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance ddr_settled_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1495:8:1495:9|Removing sequential instance release_sdif3_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1471:8:1471:9|Removing sequential instance release_sdif2_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1447:8:1447:9|Removing sequential instance release_sdif1_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1423:8:1423:9|Removing sequential instance release_sdif0_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1519:8:1519:9|Removing sequential instance ddr_settled of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":770:8:770:9|Removing sequential instance sm0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":894:8:894:9|Removing sequential instance sdif3_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":883:8:883:9|Removing sequential instance sdif2_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":872:8:872:9|Removing sequential instance sdif1_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":861:8:861:9|Removing sequential instance sdif0_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":770:8:770:9|Removing sequential instance sm0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":850:8:850:9|Removing sequential instance sm0_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":894:8:894:9|Removing sequential instance sdif3_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":883:8:883:9|Removing sequential instance sdif2_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":872:8:872:9|Removing sequential instance sdif1_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":861:8:861:9|Removing sequential instance sdif0_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":850:8:850:9|Removing sequential instance sm0_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":751:8:751:9|Removing sequential instance SDIF3_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":735:8:735:9|Removing sequential instance SDIF2_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":719:8:719:9|Removing sequential instance SDIF1_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":703:8:703:9|Removing sequential instance SDIF0_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":608:8:608:9|Removing sequential instance MSS_HPMS_READY_int of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN114 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\work\mc_system_sb\fabosc_0\mc_system_sb_fabosc_0_osc.vhd":49:4:49:23|Removing instance I_RCOSC_25_50MHZ_FAB of black_box view:work.RCOSC_25_50MHZ_FAB(def_arch) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":593:8:593:9|Removing sequential instance mss_ready_select of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":751:8:751:9|Removing sequential instance SDIF3_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":735:8:735:9|Removing sequential instance SDIF2_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":719:8:719:9|Removing sequential instance SDIF1_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":703:8:703:9|Removing sequential instance SDIF0_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":751:8:751:9|Removing sequential instance SDIF3_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":735:8:735:9|Removing sequential instance SDIF2_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":719:8:719:9|Removing sequential instance SDIF1_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":703:8:703:9|Removing sequential instance SDIF0_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":593:8:593:9|Removing sequential instance mss_ready_state of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":577:8:577:9|Removing sequential instance FIC_2_APB_M_PRESET_N_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":751:8:751:9|Removing sequential instance SDIF3_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":735:8:735:9|Removing sequential instance SDIF2_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":719:8:719:9|Removing sequential instance SDIF1_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":703:8:703:9|Removing sequential instance SDIF0_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":565:8:565:9|Removing sequential instance RESET_N_M2F_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":577:8:577:9|Removing sequential instance FIC_2_APB_M_PRESET_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":565:8:565:9|Removing sequential instance RESET_N_M2F_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":553:8:553:9|Removing sequential instance POWER_ON_RESET_N_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
@N: BN362 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":553:8:553:9|Removing sequential instance POWER_ON_RESET_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs 
syn_allowed_resources : blockrams=21  set on top level netlist MC_System


@S |Clock Summary
****************

Start                                              Requested     Requested     Clock        Clock              
Clock                                              Frequency     Period        Type         Group              
---------------------------------------------------------------------------------------------------------------
MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_0
System                                             1.0 MHz       1000.000      system       system_clkgroup    
===============================================================================================================

@W: MT530 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":781:8:781:9|Found inferred clock MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock which controls 3 sequential elements including MC_System_sb_0.CORERESETP_0.sm1_areset_n_clk_base. This clock has no specified timing constraint which may adversely impact design performance. 

Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\synthesis\MC_System.sap.
Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 136MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Mar 10 11:25:06 2015

###########################################################]
Map & Optimize Report

Synopsys Generic Technology Mapper, Version mapact, Build 1350R, Built Oct 16 2014 10:02:37
Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
Product Version I-2014.03M-SP1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 135MB)

@N: BN114 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\work\mc_system_sb\mc_system_sb.vhd":687:0:687:11|Removing instance SYSRESET_POR of black_box view:smartfusion2.SYSRESET(syn_black_box) because there are no references to its outputs 

Available hyper_sources - for debug and ip models
	None Found

@W: MO129 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":781:8:781:9|Sequential instance MC_System_sb_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation
@N: FA239 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreapb3\4.0.100\rtl\vhdl\core\coreapb3.vhd":633:12:633:15|ROM CoreAPB3_0.iPSELS_raw_5[1:0] mapped in logic.
@N: FA239 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreapb3\4.0.100\rtl\vhdl\core\coreapb3.vhd":633:12:633:15|ROM CoreAPB3_0.iPSELS_raw_5[1:0] mapped in logic.
@N: MO106 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreapb3\4.0.100\rtl\vhdl\core\coreapb3.vhd":633:12:633:15|Found ROM, 'CoreAPB3_0.iPSELS_raw_5[1:0]', 16 words by 2 bits 
@W: MO129 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":781:8:781:9|Sequential instance MC_System_sb_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation
@W: MO129 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1331:8:1331:9|Sequential instance MC_System_sb_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)


Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)


Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
------------------------------------------------------------


Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)



#### START OF CLOCK OPTIMIZATION REPORT #####[

Clock optimization not enabled
1 non-gated/non-generated clock tree(s) driving 1 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=================================================== Non-Gated/Non-Generated Clocks ===================================================
Clock Tree ID     Driving Element                   Drive Element Type     Fanout     Sample Instance                                 
--------------------------------------------------------------------------------------------------------------------------------------
@K:CKID0001       MC_System_sb_0.CCC_0.GL0_INST     CLKINT                 1          MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST
======================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]

Writing Analyst data base D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\synthesis\MC_System.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 135MB)

Writing Analyst data base D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\synthesis\synwork\MC_System_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 135MB)

Writing EDIF Netlist and constraint files
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
I-2014.03M-SP1

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 135MB)

@W: MT246 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\work\mc_system_sb\ccc_0\mc_system_sb_ccc_0_fccc.vhd":110:4:110:11|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:MC_System_sb_0.CCC_0.GL0_net"



@S |##### START OF TIMING REPORT #####[
# Timing Report written on Tue Mar 10 11:25:07 2015
#


Top view:               MC_System
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: 2.048

                                                   Requested     Estimated      Requested     Estimated               Clock        Clock              
Starting Clock                                     Frequency     Frequency      Period        Period        Slack     Type         Group              
------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     125.7 MHz      10.000        7.952         2.048     inferred     Inferred_clkgroup_0
System                                             100.0 MHz     1029.4 MHz     10.000        0.971         9.029     system       system_clkgroup    
======================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                                          |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                        Ending                                          |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                          System                                          |  10.000      9.029  |  No paths    -      |  No paths    -      |  No paths    -    
MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  |  10.000      2.048  |  No paths    -      |  No paths    -      |  No paths    -    
======================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                     Starting                                                                                                                            Arrival          
Instance                                             Reference                                          Type        Pin                Net                                               Time        Slack
                                                     Clock                                                                                                                                                
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[13]     AMBA_SLAVE_1_PADDRS_c[13]                         3.101       2.048
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[14]     AMBA_SLAVE_1_PADDRS_c[14]                         3.105       2.258
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[15]     AMBA_SLAVE_1_PADDRS_c[15]                         3.044       2.428
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_SEL          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx     2.965       2.460
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[12]     AMBA_SLAVE_1_PADDRS_c[12]                         3.126       3.136
==========================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                     Starting                                                                                                                                  Required          
Instance                                             Reference                                          Type        Pin                 Net                                                    Time         Slack
                                                     Clock                                                                                                                                                       
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_READY         N_39_i_0                                               8.643        2.048
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RESP          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSLVERR        9.147        2.569
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[3]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]      9.483        2.905
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[4]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]      9.539        2.961
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[9]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[9]      9.594        3.016
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[23]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[23]     9.604        3.026
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[0]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[0]      9.617        3.039
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[29]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[29]     9.625        3.047
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[30]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[30]     9.629        3.051
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[13]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[13]     9.640        3.062
=================================================================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            1.357
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.643

    - Propagation time:                      6.595
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     2.048

    Number of logic level(s):                2
    Starting point:                          MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[13]
    Ending point:                            MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_READY
    The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
    The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

Instance / Net                                                   Pin                Pin               Arrival     No. of    
Name                                                 Type        Name               Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MSS_010     F_HM0_ADDR[13]     Out     3.101     3.101       -         
AMBA_SLAVE_1_PADDRS_c[13]                            Net         -                  -       0.980     -           3         
MC_System_sb_0.CoreAPB3_0.iPSELS_raw_0_a2_0[0]       CFG4        D                  In      -         4.080       -         
MC_System_sb_0.CoreAPB3_0.iPSELS_raw_0_a2_0[0]       CFG4        Y                  Out     0.411     4.491       -         
N_113                                                Net         -                  -       0.933     -           36        
MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.N_39_i       CFG4        C                  In      -         5.424       -         
MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.N_39_i       CFG4        Y                  Out     0.200     5.624       -         
N_39_i_0                                             Net         -                  -       0.971     -           1         
MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MSS_010     F_HM0_READY        In      -         6.595       -         
============================================================================================================================
Total path delay (propagation time + setup) of 7.952 is 5.069(63.7%) logic and 2.884(36.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                             Starting                                                                                           Arrival          
Instance                                     Reference     Type               Pin        Net                                                    Time        Slack
                                             Clock                                                                                                               
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_sb_0.FABOSC_0.I_RCOSC_25_50MHZ     System        RCOSC_25_50MHZ     CLKOUT     FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     0.000       9.029
=================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                  Starting                                                                                         Required          
Instance                          Reference     Type     Pin                Net                                                    Time         Slack
                                  Clock                                                                                                              
-----------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_sb_0.CCC_0.CCC_INST     System        CCC      RCOSC_25_50MHZ     FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     10.000       9.029
=====================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         10.000

    - Propagation time:                      0.971
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 9.029

    Number of logic level(s):                0
    Starting point:                          MC_System_sb_0.FABOSC_0.I_RCOSC_25_50MHZ / CLKOUT
    Ending point:                            MC_System_sb_0.CCC_0.CCC_INST / RCOSC_25_50MHZ
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                            Pin                Pin               Arrival     No. of    
Name                                                   Type               Name               Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------
MC_System_sb_0.FABOSC_0.I_RCOSC_25_50MHZ               RCOSC_25_50MHZ     CLKOUT             Out     0.000     0.000       -         
FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     Net                -                  -       0.971     -           1         
MC_System_sb_0.CCC_0.CCC_INST                          CCC                RCOSC_25_50MHZ     In      -         0.971       -         
=====================================================================================================================================
Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report for MC_System 

Mapping to part: m2s010fbga484-1
Cell usage:
CCC             1 use
CLKINT          2 uses
MSS_010         1 use
RCOSC_25_50MHZ  1 use
CFG2           2 uses
CFG4           35 uses


Sequential Cells: 
SLE            0 uses

DSP Blocks:    0

I/O ports: 220
I/O primitives: 219
BIBUF          8 uses
INBUF          71 uses
OUTBUF         139 uses
TRIBUFF        1 use


Global Clock Buffers: 2


Total LUTs:    37

Extra resources required for RAM and MACC interface logic during P&R:

RAM64x18 Interface Logic : SLEs = 0; LUTs = 0;
RAM1K18  Interface Logic : SLEs = 0; LUTs = 0;
MACC     Interface Logic : SLEs = 0; LUTs = 0;

Total number of SLEs after P&R:  0 + 0 + 0 + 0 = 0;
Total number of LUTs after P&R:  37 + 0 + 0 + 0 = 37;

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 50MB peak: 135MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Mar 10 11:25:08 2015

###########################################################]
