

@S |##### START OF TIMING REPORT #####[
# Timing Report written on Thu Nov 03 13:52:19 2016
#


Top view:               MC_System_top
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    E:\SVN\MotorControl\Development\MCSK\SK1ABLHL10_5_1\synthesis\MC_System_top.fdc
                       
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: -0.673

                   Requested     Estimated     Requested     Estimated               Clock        Clock           
Starting Clock     Frequency     Frequency     Period        Period        Slack     Type         Group           
------------------------------------------------------------------------------------------------------------------
GL0                100.0 MHz     101.4 MHz     10.000        9.864         0.136     declared     default_clkgroup
System             100.0 MHz     157.6 MHz     10.000        6.343         3.657     system       system_clkgroup 
==================================================================================================================



Clock Relationships
*******************

Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------
Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------
System    System  |  0.000       0.680   |  No paths    -      |  No paths    -      |  No paths    -    
System    GL0     |  0.000       2.170   |  No paths    -      |  No paths    -      |  No paths    -    
GL0       System  |  0.000       0.541   |  No paths    -      |  No paths    -      |  No paths    -    
GL0       GL0     |  0.000       -0.673  |  No paths    -      |  No paths    -      |  No paths    -    
=========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: GL0
====================================



Starting Points with Worst Slack
********************************

                                                           Starting                                                                 Arrival           
Instance                                                   Reference     Type     Pin     Net                                       Time        Slack 
                                                           Clock                                                                                      
------------------------------------------------------------------------------------------------------------------------------------------------------
BLDC_HALL_Axis_0.apb3_hall_if_0.hall_speed_factor_o[0]     GL0           SLE      Q       apb3_hall_if_0_hall_speed_factor_o[0]     0.053       -0.673
BLDC_HALL_Axis_0.apb3_hall_if_0.hall_speed_factor_o[1]     GL0           SLE      Q       apb3_hall_if_0_hall_speed_factor_o[1]     0.053       -0.673
BLDC_HALL_Axis_0.apb3_hall_if_0.hall_speed_factor_o[2]     GL0           SLE      Q       apb3_hall_if_0_hall_speed_factor_o[2]     0.053       -0.673
BLDC_HALL_Axis_0.apb3_hall_if_0.hall_speed_factor_o[3]     GL0           SLE      Q       apb3_hall_if_0_hall_speed_factor_o[3]     0.053       -0.673
BLDC_HALL_Axis_0.apb3_hall_if_0.hall_speed_factor_o[4]     GL0           SLE      Q       apb3_hall_if_0_hall_speed_factor_o[4]     0.053       -0.673
BLDC_HALL_Axis_0.apb3_hall_if_0.hall_speed_factor_o[5]     GL0           SLE      Q       apb3_hall_if_0_hall_speed_factor_o[5]     0.053       -0.673
BLDC_HALL_Axis_0.apb3_hall_if_0.hall_speed_factor_o[6]     GL0           SLE      Q       apb3_hall_if_0_hall_speed_factor_o[6]     0.053       -0.673
BLDC_HALL_Axis_0.apb3_hall_if_0.hall_speed_factor_o[7]     GL0           SLE      Q       apb3_hall_if_0_hall_speed_factor_o[7]     0.053       -0.673
BLDC_HALL_Axis_0.apb3_hall_if_0.hall_speed_factor_o[8]     GL0           SLE      Q       apb3_hall_if_0_hall_speed_factor_o[8]     0.053       -0.673
BLDC_HALL_Axis_0.apb3_hall_if_0.hall_speed_factor_o[9]     GL0           SLE      Q       apb3_hall_if_0_hall_speed_factor_o[9]     0.053       -0.673
======================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                                                     Starting                                       Required           
Instance                                                                                                             Reference     Type     Pin      Net            Time         Slack 
                                                                                                                     Clock                                                             
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
BLDC_HALL_Axis_0.PWM_SCALING_0.MAS_PWM_SCALING_INST.MAS_PROC\.op_mult\.un3_product_o_muladd_0[35:0]                  GL0           MACC     A[0]     mul_a_i[0]     1.406        -0.673
BLDC_HALL_Axis_0.OLMNG_0.MAS_OLMNG_INST.MAS_PROC\.op_mult\.un3_product_o_muladd_0[35:0]                              GL0           MACC     A[0]     mul_a_i[0]     1.406        -0.673
BLDC_HALL_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.MAS_PI_INST.MAS_PROC\.op_mult\.un3_product_o_muladd_0[35:0]     GL0           MACC     A[0]     mul_a_i[0]     1.406        -0.673
BLDC_HALL_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.MAS_PI_INST.MAS_PROC\.op_mult\.un3_product_o_muladd_0[35:0]     GL0           MACC     A[1]     mul_a_i[1]     1.406        -0.673
BLDC_HALL_Axis_0.PWM_SCALING_0.MAS_PWM_SCALING_INST.MAS_PROC\.op_mult\.un3_product_o_muladd_0[35:0]                  GL0           MACC     A[1]     mul_a_i[1]     1.406        -0.673
BLDC_HALL_Axis_0.OLMNG_0.MAS_OLMNG_INST.MAS_PROC\.op_mult\.un3_product_o_muladd_0[35:0]                              GL0           MACC     A[1]     mul_a_i[1]     1.406        -0.673
BLDC_HALL_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.MAS_PI_INST.MAS_PROC\.op_mult\.un3_product_o_muladd_0[35:0]     GL0           MACC     A[2]     mul_a_i[2]     1.406        -0.673
BLDC_HALL_Axis_0.PWM_SCALING_0.MAS_PWM_SCALING_INST.MAS_PROC\.op_mult\.un3_product_o_muladd_0[35:0]                  GL0           MACC     A[2]     mul_a_i[2]     1.406        -0.673
BLDC_HALL_Axis_0.OLMNG_0.MAS_OLMNG_INST.MAS_PROC\.op_mult\.un3_product_o_muladd_0[35:0]                              GL0           MACC     A[2]     mul_a_i[2]     1.406        -0.673
BLDC_HALL_Axis_0.SPEED_ID_IQ_PI_0.PI_Controller_INST.MAS_PI_INST.MAS_PROC\.op_mult\.un3_product_o_muladd_0[35:0]     GL0           MACC     A[3]     mul_a_i[3]     1.406        -0.673
=======================================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Propagation time:                        0.733
    + Clock delay at starting point:         0.000 (ideal)
    - Requested Period:                      0.000
    - Hold time:                             1.406
    - Clock delay at ending point:           0.000 (ideal)
    = Slack (critical) :                     -0.673

    Number of logic level(s):                0
    Starting point:                          BLDC_HALL_Axis_0.apb3_hall_if_0.hall_speed_factor_o[0] / Q
    Ending point:                            BLDC_HALL_Axis_0.HALL_INTERFACE_1.omega_calc_mas_inst.MAS_PROC\.op_mult\.un3_product_o_mulonly_0[35:0] / A[0]
    The start point is clocked by            GL0 [rising] on pin CLK
    The end   point is clocked by            GL0 [rising] on pin CLK[0]

Instance / Net                                                                                                      Pin      Pin               Arrival     No. of    
Name                                                                                                       Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BLDC_HALL_Axis_0.apb3_hall_if_0.hall_speed_factor_o[0]                                                     SLE      Q        Out     0.053     0.053       -         
apb3_hall_if_0_hall_speed_factor_o[0]                                                                      Net      -        -       0.680     -           1         
BLDC_HALL_Axis_0.HALL_INTERFACE_1.omega_calc_mas_inst.MAS_PROC\.op_mult\.un3_product_o_mulonly_0[35:0]     MACC     A[0]     In      -         0.733       -         
=====================================================================================================================================================================


Path information for path number 2: 
    Propagation time:                        0.733
    + Clock delay at starting point:         0.000 (ideal)
    - Requested Period:                      0.000
    - Hold time:                             1.406
    - Clock delay at ending point:           0.000 (ideal)
    = Slack (critical) :                     -0.673

    Number of logic level(s):                0
    Starting point:                          BLDC_HALL_Axis_0.apb3_hall_if_0.hall_speed_factor_o[1] / Q
    Ending point:                            BLDC_HALL_Axis_0.HALL_INTERFACE_1.omega_calc_mas_inst.MAS_PROC\.op_mult\.un3_product_o_mulonly_0[35:0] / A[1]
    The start point is clocked by            GL0 [rising] on pin CLK
    The end   point is clocked by            GL0 [rising] on pin CLK[0]

Instance / Net                                                                                                      Pin      Pin               Arrival     No. of    
Name                                                                                                       Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BLDC_HALL_Axis_0.apb3_hall_if_0.hall_speed_factor_o[1]                                                     SLE      Q        Out     0.053     0.053       -         
apb3_hall_if_0_hall_speed_factor_o[1]                                                                      Net      -        -       0.680     -           1         
BLDC_HALL_Axis_0.HALL_INTERFACE_1.omega_calc_mas_inst.MAS_PROC\.op_mult\.un3_product_o_mulonly_0[35:0]     MACC     A[1]     In      -         0.733       -         
=====================================================================================================================================================================


Path information for path number 3: 
    Propagation time:                        0.733
    + Clock delay at starting point:         0.000 (ideal)
    - Requested Period:                      0.000
    - Hold time:                             1.406
    - Clock delay at ending point:           0.000 (ideal)
    = Slack (critical) :                     -0.673

    Number of logic level(s):                0
    Starting point:                          BLDC_HALL_Axis_0.apb3_hall_if_0.hall_speed_factor_o[2] / Q
    Ending point:                            BLDC_HALL_Axis_0.HALL_INTERFACE_1.omega_calc_mas_inst.MAS_PROC\.op_mult\.un3_product_o_mulonly_0[35:0] / A[2]
    The start point is clocked by            GL0 [rising] on pin CLK
    The end   point is clocked by            GL0 [rising] on pin CLK[0]

Instance / Net                                                                                                      Pin      Pin               Arrival     No. of    
Name                                                                                                       Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BLDC_HALL_Axis_0.apb3_hall_if_0.hall_speed_factor_o[2]                                                     SLE      Q        Out     0.053     0.053       -         
apb3_hall_if_0_hall_speed_factor_o[2]                                                                      Net      -        -       0.680     -           1         
BLDC_HALL_Axis_0.HALL_INTERFACE_1.omega_calc_mas_inst.MAS_PROC\.op_mult\.un3_product_o_mulonly_0[35:0]     MACC     A[2]     In      -         0.733       -         
=====================================================================================================================================================================


Path information for path number 4: 
    Propagation time:                        0.733
    + Clock delay at starting point:         0.000 (ideal)
    - Requested Period:                      0.000
    - Hold time:                             1.406
    - Clock delay at ending point:           0.000 (ideal)
    = Slack (critical) :                     -0.673

    Number of logic level(s):                0
    Starting point:                          BLDC_HALL_Axis_0.apb3_hall_if_0.hall_speed_factor_o[3] / Q
    Ending point:                            BLDC_HALL_Axis_0.HALL_INTERFACE_1.omega_calc_mas_inst.MAS_PROC\.op_mult\.un3_product_o_mulonly_0[35:0] / A[3]
    The start point is clocked by            GL0 [rising] on pin CLK
    The end   point is clocked by            GL0 [rising] on pin CLK[0]

Instance / Net                                                                                                      Pin      Pin               Arrival     No. of    
Name                                                                                                       Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BLDC_HALL_Axis_0.apb3_hall_if_0.hall_speed_factor_o[3]                                                     SLE      Q        Out     0.053     0.053       -         
apb3_hall_if_0_hall_speed_factor_o[3]                                                                      Net      -        -       0.680     -           1         
BLDC_HALL_Axis_0.HALL_INTERFACE_1.omega_calc_mas_inst.MAS_PROC\.op_mult\.un3_product_o_mulonly_0[35:0]     MACC     A[3]     In      -         0.733       -         
=====================================================================================================================================================================


Path information for path number 5: 
    Propagation time:                        0.733
    + Clock delay at starting point:         0.000 (ideal)
    - Requested Period:                      0.000
    - Hold time:                             1.406
    - Clock delay at ending point:           0.000 (ideal)
    = Slack (critical) :                     -0.673

    Number of logic level(s):                0
    Starting point:                          BLDC_HALL_Axis_0.apb3_hall_if_0.hall_speed_factor_o[4] / Q
    Ending point:                            BLDC_HALL_Axis_0.HALL_INTERFACE_1.omega_calc_mas_inst.MAS_PROC\.op_mult\.un3_product_o_mulonly_0[35:0] / A[4]
    The start point is clocked by            GL0 [rising] on pin CLK
    The end   point is clocked by            GL0 [rising] on pin CLK[0]

Instance / Net                                                                                                      Pin      Pin               Arrival     No. of    
Name                                                                                                       Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BLDC_HALL_Axis_0.apb3_hall_if_0.hall_speed_factor_o[4]                                                     SLE      Q        Out     0.053     0.053       -         
apb3_hall_if_0_hall_speed_factor_o[4]                                                                      Net      -        -       0.680     -           1         
BLDC_HALL_Axis_0.HALL_INTERFACE_1.omega_calc_mas_inst.MAS_PROC\.op_mult\.un3_product_o_mulonly_0[35:0]     MACC     A[4]     In      -         0.733       -         
=====================================================================================================================================================================




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                         Starting                                                                                           Arrival          
Instance                                                 Reference     Type               Pin        Net                                                    Time        Slack
                                                         Clock                                                                                                               
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.FABOSC_0.I_RCOSC_25_50MHZ     System        RCOSC_25_50MHZ     CLKOUT     FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     0.000       0.680
MC_System_0.MC_System_sb_0.CCC_0.CCC_INST                System        CCC                LOCK       LOCK                                                   0.000       2.170
=============================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                         Starting                                                                                         Required          
Instance                                                                                 Reference     Type     Pin                Net                                                    Time         Slack
                                                                                         Clock                                                                                                              
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.CCC_0.CCC_INST                                                System        CCC      RCOSC_25_50MHZ     FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     0.000        0.680
BLDC_HALL_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_theta_i[0]     System        SLE      D                  N_592                                                  0.155        2.170
BLDC_HALL_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_theta_i[1]     System        SLE      D                  N_593                                                  0.155        2.170
BLDC_HALL_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_theta_i[2]     System        SLE      D                  N_594                                                  0.155        2.170
BLDC_HALL_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_theta_i[3]     System        SLE      D                  N_595                                                  0.155        2.170
BLDC_HALL_Axis_0.FOC_TRANSFORMS_0.CORDIC_SCHEDULER_INST.CORDIC_ROT_INST.s_theta_i[4]     System        SLE      D                  N_596                                                  0.155        2.170
BLDC_HALL_Axis_0.OLMNG_0.ACCUMULATOR_OLMNG_INST.theta_scl_buff_o[0]                      System        SLE      D                  theta_scl_buff_o_3[0]                                  0.155        2.213
BLDC_HALL_Axis_0.OLMNG_0.ACCUMULATOR_OLMNG_INST.theta_scl_buff_o[1]                      System        SLE      D                  theta_scl_buff_o_3[1]                                  0.155        2.213
BLDC_HALL_Axis_0.OLMNG_0.ACCUMULATOR_OLMNG_INST.theta_scl_buff_o[2]                      System        SLE      D                  theta_scl_buff_o_3[2]                                  0.155        2.213
BLDC_HALL_Axis_0.OLMNG_0.ACCUMULATOR_OLMNG_INST.theta_scl_buff_o[3]                      System        SLE      D                  theta_scl_buff_o_3[3]                                  0.155        2.213
============================================================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Propagation time:                        0.680
    + Clock delay at starting point:         0.000 (ideal)
-0.000
    - Requested Period:                      0.000
    - Hold time:                             0.000
    - Clock delay at ending point:           0.000 (ideal)
0.000
    = Slack (non-critical) :                 0.680

    Number of logic level(s):                0
    Starting point:                          MC_System_0.MC_System_sb_0.FABOSC_0.I_RCOSC_25_50MHZ / CLKOUT
    Ending point:                            MC_System_0.MC_System_sb_0.CCC_0.CCC_INST / RCOSC_25_50MHZ
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                              Pin                Pin               Arrival     No. of    
Name                                                     Type               Name               Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.FABOSC_0.I_RCOSC_25_50MHZ     RCOSC_25_50MHZ     CLKOUT             Out     0.000     0.000       -         
FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC       Net                -                  -       0.680     -           1         
MC_System_0.MC_System_sb_0.CCC_0.CCC_INST                CCC                RCOSC_25_50MHZ     In      -         0.680       -         
=======================================================================================================================================



##### END OF TIMING REPORT #####]

