#Build: Synplify Pro I-2013.09M-SP1 , Build 034R, Jan 17 2014
#install: C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1
#OS: Windows 7 6.1
#Hostname: W764-PINNINTIA

#Implementation: synthesis

$ Start of Compile
#Wed Oct 08 12:10:09 2014

Synopsys VHDL Compiler, version comp201309rcp1, Build 078R, built Jan 14 2014
@N|Running in 64-bit mode
Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

@N: CD720 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":58:7:58:26|Top entity is set to MSMC_Fab_Toplevel_st.
@W: CD134 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\pi_controller.vhd":155:26:155:35|No such identifier, output_y_o, of proper type in current declarative region
@W: CD134 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\pi_controller.vhd":156:26:156:34|No such identifier, acc_out_o, of proper type in current declarative region
VHDL syntax check successful!
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":58:7:58:26|Synthesizing work.msmc_fab_toplevel_st.msmc_fab_toplevel_st 
@W: CD285 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1922:45:1922:60|Port map width mismatch (15 => 18) on port iq_pi_ki_scale_i of component speed_id_iq_pi 
@W: CD285 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1921:45:1921:60|Port map width mismatch (15 => 18) on port iq_pi_kp_scale_i of component speed_id_iq_pi 
@W: CD285 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1920:45:1920:57|Port map width mismatch (15 => 18) on port iq_pi_ymin_i of component speed_id_iq_pi 
@W: CD285 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1919:45:1919:57|Port map width mismatch (15 => 18) on port iq_pi_ymax_i of component speed_id_iq_pi 
@W: CD285 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1918:45:1918:54|Port map width mismatch (15 => 18) on port iq_pi_ki_i of component speed_id_iq_pi 
@W: CD285 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1917:45:1917:54|Port map width mismatch (15 => 18) on port iq_pi_kp_i of component speed_id_iq_pi 
@W: CD285 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1911:45:1911:64|Port map width mismatch (15 => 18) on port iq_pi_act_input_i of component speed_id_iq_pi 
@W: CD285 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1905:45:1905:60|Port map width mismatch (15 => 18) on port id_pi_ki_scale_i of component speed_id_iq_pi 
@W: CD285 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1904:45:1904:60|Port map width mismatch (15 => 18) on port id_pi_kp_scale_i of component speed_id_iq_pi 
@W: CD285 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1903:45:1903:57|Port map width mismatch (15 => 18) on port id_pi_ymin_i of component speed_id_iq_pi 
@W: CD285 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1902:45:1902:57|Port map width mismatch (15 => 18) on port id_pi_ymax_i of component speed_id_iq_pi 
@W: CD285 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1901:45:1901:54|Port map width mismatch (15 => 18) on port id_pi_ki_i of component speed_id_iq_pi 
@W: CD285 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1900:45:1900:54|Port map width mismatch (15 => 18) on port id_pi_kp_i of component speed_id_iq_pi 
@W: CD285 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1895:48:1895:67|Port map width mismatch (15 => 18) on port id_pi_act_input_i of component speed_id_iq_pi 
@W: CD285 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1894:45:1894:57|Port map width mismatch (15 => 18) on port id_pi_ref_input_i of component speed_id_iq_pi 
@W: CD285 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1877:48:1877:57|Port map width mismatch (15 => 18) on port iq_init_i of component speed_id_iq_pi 
@W: CD285 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":2237:48:2237:74|Port map width mismatch (12 => 14) on port adc_ch3_val_i of component APB3_IF_st 
@W: CD285 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":2236:48:2236:74|Port map width mismatch (12 => 14) on port adc_ch2_val_i of component APB3_IF_st 
@W: CD285 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":2235:48:2235:74|Port map width mismatch (12 => 14) on port adc_ch1_val_i of component APB3_IF_st 
@W: CD285 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":2234:48:2234:74|Port map width mismatch (12 => 14) on port adc_ch0_val_i of component APB3_IF_st 
@W: CD285 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":2312:45:2312:60|Port map width mismatch (16 => 18) on port PERIOD of component Core3PhasePWM_st 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":259:8:259:25|Signal ramp_start_count_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":260:8:260:19|Signal pi_start_pul is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":261:8:261:19|Signal pi_start_dly is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":262:8:262:23|Signal counter_pi_start is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":263:8:263:12|Signal waddr is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":264:8:264:15|Signal wdata_in is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":265:8:265:10|Signal wen is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":267:8:267:30|Signal start_clarke_from_apb_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":271:8:271:31|Signal ialpha_clarke_output_tmp is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":274:8:274:30|Signal ibeta_clarke_output_tmp is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":281:8:281:27|Signal i_alpha_park_input_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":282:8:282:26|Signal i_beta_park_input_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":293:11:293:25|Signal start_ipark_s_d is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":297:8:297:22|Signal start_iclarke_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":298:8:298:23|Signal valpha_iclarke_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":299:8:299:22|Signal vbeta_iclarke_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":318:8:318:11|Signal va_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":319:8:319:11|Signal vb_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":320:8:320:11|Signal vc_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":321:8:321:14|Signal v_mag_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":324:8:324:16|Signal a0_va3h_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":325:8:325:16|Signal a0_vb3h_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":326:8:326:16|Signal a0_vc3h_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":336:8:336:21|Signal ramp_ref_max_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":337:8:337:21|Signal ramp_ref_min_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":338:8:338:21|Signal ramp_set_ref_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":339:8:339:24|Signal ramp_slew_count_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":340:8:340:23|Signal ramp_ref_value_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":341:8:341:40|Signal ramp_ref_value_frm_ramp_profile_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":343:8:343:18|Signal ramp_done_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":344:8:344:22|Signal ramp_done_s_dly is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":345:8:345:20|Signal ramp_done_pul is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":347:8:347:17|Signal loop_sel_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":348:8:348:35|Signal satrt_open_lp_angle_inc_sync is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":349:8:349:30|Signal satrt_open_lp_angle_inc is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":350:8:350:24|Signal svpwm_done_s_sync is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":354:8:354:27|Signal a0_svpwm_done_s_sync is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":355:8:355:22|Signal a0_svpwm_done_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":357:8:357:19|Signal a0_sub_mvs_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":360:8:360:21|Signal a0_add_c_mvs_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":363:8:363:20|Signal a0_mvs_done_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":364:8:364:16|Signal a0_pwma_r is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":365:8:365:16|Signal a0_pwmb_r is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":366:8:366:16|Signal a0_pwmc_r is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":368:8:368:32|Signal adc_control_reg_frm_apb_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":370:8:370:32|Signal adc_control_reg_frm_adc_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":372:8:372:31|Signal adc_control_reg_update_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":374:8:374:31|Signal adc_result_ch0_frm_adc_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":375:8:375:31|Signal adc_result_ch1_frm_adc_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":376:8:376:31|Signal adc_result_ch2_frm_adc_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":377:8:377:31|Signal adc_result_ch3_frm_adc_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":378:8:378:31|Signal adc_result_ch4_frm_adc_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":379:8:379:31|Signal adc_result_ch5_frm_adc_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":388:8:388:35|Signal pwm_update_period_prescale_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":390:8:390:29|Signal pwm_update_dead_time_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":392:8:392:30|Signal pwm_update_delay_time_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":394:8:394:33|Signal pwm_update_compare_match_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":396:8:396:28|Signal pwm_load_config_reg_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":398:8:398:27|Signal pwm_period_frm_apb_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":399:8:399:29|Signal pwm_prescale_frm_apb_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":400:8:400:30|Signal pwm_dead_time_frm_apb_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":401:8:401:26|Signal pwm_delay_frm_apb_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":402:8:402:31|Signal pwm_config_reg_frm_apb_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":403:8:403:26|Signal pwm_period_to_pwm_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":405:8:405:35|Signal pwm_compare_match_a_to_pwm_i is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":406:8:406:35|Signal pwm_compare_match_b_to_pwm_i is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":407:8:407:35|Signal pwm_compare_match_c_to_pwm_i is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":422:8:422:38|Signal a0_pwm_compare_match_c_to_pwm_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":423:8:423:31|Signal sin_cos_start_angl_est_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":426:8:426:34|Signal sin_cos_avalbl_angl_est_s_r is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":428:8:428:22|Signal sine_angl_est_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":429:8:429:21|Signal cos_angl_est_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":432:8:432:29|Signal sine_angl_est_sgnext_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":433:8:433:28|Signal cos_angl_est_sgnext_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":435:8:435:26|Signal start_angl_est_sync is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":436:8:436:23|Signal direction_angl_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":437:8:437:18|Signal busy_angl_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":438:8:438:18|Signal done_angl_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":439:8:439:21|Signal i_alpha_angl_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":440:8:440:20|Signal i_beta_angl_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":441:8:441:21|Signal v_alpha_angl_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":442:8:442:20|Signal v_beta_angl_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":443:8:443:17|Signal angle_pi_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":444:8:444:20|Signal i_alpha_bar_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":445:8:445:19|Signal i_beta_bar_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":446:8:446:16|Signal e_alpha_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":447:8:447:15|Signal e_beta_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":448:8:448:25|Signal start_angl_frm_apb is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":449:8:449:18|Signal angle_i_max is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":450:8:450:18|Signal angle_i_min is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":451:8:451:18|Signal angle_e_max is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":452:8:452:18|Signal angle_e_min is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":458:8:458:20|Signal angle_pi_ymax is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":459:8:459:20|Signal angle_pi_ymin is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":474:8:474:21|Signal speed_ref_in_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":475:8:475:24|Signal a0_speed_ref_in_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":476:8:476:24|Signal a1_speed_ref_in_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":477:8:477:24|Signal a2_speed_ref_in_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":478:8:478:24|Signal a3_speed_ref_in_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":479:8:479:24|Signal a4_speed_ref_in_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":480:8:480:24|Signal a5_speed_ref_in_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":482:8:482:21|Signal speed_pi_start is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":484:8:484:22|Signal speed_pi_busy_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":485:8:485:22|Signal speed_pi_done_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":486:8:486:24|Signal speed_pi_output_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":487:8:487:18|Signal id_ref_in_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":494:8:494:23|Signal id_pi_output_s_d is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":497:8:497:18|Signal iq_pi_start is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":503:8:503:23|Signal iq_pi_output_s_d is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":505:8:505:22|Signal sin_cos_start_i is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":506:8:506:20|Signal park_done_s_d is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":507:8:507:21|Signal iq_pi_done_s_d is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":508:8:508:24|Signal speed_pi_done_s_d is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":509:8:509:22|Signal park_done_s_dtc is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":510:8:510:23|Signal iq_pi_done_s_dtc is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":511:8:511:26|Signal speed_pi_done_s_dtc is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":512:8:512:21|Signal ipark_done_s_d is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":513:8:513:21|Signal id_pi_done_s_d is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":514:8:514:22|Signal clarke_done_s_d is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":515:8:515:23|Signal ipark_done_s_dtc is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":516:8:516:23|Signal id_pi_done_s_dtc is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":517:8:517:24|Signal clarke_done_s_dtc is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":518:8:518:23|Signal iclarke_done_s_d is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":519:8:519:25|Signal iclarke_done_s_dtc is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":520:8:520:20|Signal done_angl_o_d is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":522:8:522:19|Signal done_speed_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":523:8:523:21|Signal done_speed_o_d is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":524:8:524:23|Signal done_speed_o_dtc is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":525:8:525:32|Signal sin_cos_done_angl_est_s_d is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":526:8:526:34|Signal sin_cos_done_angl_est_s_dtc is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":527:8:527:20|Signal id_pi_start_d is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":528:8:528:16|Signal angle_apb is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":529:8:529:14|Signal counter is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":530:8:530:20|Signal ag_done_o_dtc is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":532:8:532:21|Signal wdata_in_angle is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":533:8:533:16|Signal wen_angle is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":534:8:534:15|Signal angl_pul is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":535:8:535:18|Signal waddr_angle is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":536:8:536:20|Signal counter_angle is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":537:8:537:19|Signal en_speedpi_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":540:8:540:11|Signal cl_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":541:8:541:14|Signal theta_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":542:8:542:17|Signal ol_theta_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":543:8:543:19|Signal en_speedpi_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":544:8:544:17|Signal en_idqpi_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":545:8:545:21|Signal init_speedpi_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":546:8:546:18|Signal init_iqpi_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":547:8:547:19|Signal init_theta_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":548:8:548:18|Signal theta_scl_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":549:8:549:21|Signal mas_en_s_sqmng is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":550:8:550:23|Signal mas_done_s_sqmng is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":551:8:551:18|Signal sub_s_sqmng is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":552:8:552:23|Signal mult_out_s_sqmng is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":553:8:553:20|Signal mul_a_s_sqmng is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":554:8:554:20|Signal mul_b_s_sqmng is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":555:8:555:20|Signal add_c_s_sqmng is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":556:8:556:19|Signal mas_en_s_est is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":557:8:557:21|Signal mas_done_s_est is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":558:8:558:16|Signal sub_s_est is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":559:8:559:21|Signal mult_out_s_est is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":560:8:560:18|Signal mul_a_s_est is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":561:8:561:18|Signal mul_b_s_est is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":562:8:562:18|Signal add_c_s_est is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":563:8:563:12|Signal sub_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":565:8:565:21|Signal ramp_start_pul is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":566:8:566:21|Signal ramp_start_dly is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":579:8:579:25|Signal omega_filter_out_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":580:8:580:23|Signal omega_filter_out is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":581:8:581:14|Signal omega_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":582:8:582:16|Signal acc_out_o is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":583:8:583:16|Signal pi_done_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":584:8:584:16|Signal pi_busy_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":585:8:585:15|Signal pi_ref_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":586:8:586:15|Signal pi_act_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":588:8:588:23|Signal pll_theta_done_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":589:8:589:25|Signal pll_theta_done_dly is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":591:8:591:18|Signal pll_theta_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":592:8:592:22|Signal pll_theta_scl_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":593:8:593:20|Signal pll_theta_tmp is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":594:8:594:26|Signal e_beta_filter_out_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":596:8:596:24|Signal e_beta_filter_out is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":597:8:597:27|Signal e_alpha_filter_out_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":598:8:598:25|Signal e_alpha_filter_out is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":602:8:602:17|Signal est_done_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":603:8:603:17|Signal done_est_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":604:8:604:14|Signal add_c_i is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":605:8:605:18|Signal pi_done_i_d is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":606:8:606:20|Signal pi_done_i_dtc is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":608:8:608:19|Signal done_omega_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":609:8:609:20|Signal done_ealphs_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":610:8:610:22|Signal done_ealphs_dly is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":612:8:612:19|Signal done_ebeta_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":613:8:613:24|Signal pll_theta_start_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":614:8:614:19|Signal reset_ramp_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":616:8:616:22|Signal soft_stop_ack_s is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":628:11:628:24|Signal init_pll_theta is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":629:11:629:35|Signal rate_limit_ref_in_tmp_ext is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":630:11:630:33|Signal rate_limit_slew_cnt_ext is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":631:11:631:33|Signal rate_limit_rate_cnt_ext is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":632:11:632:33|Signal ramp_ref_value_buff_ext is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":637:11:637:26|Signal reset_ramp_tmp_s is undriven 
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":32:7:32:29|Synthesizing work.edge_detection_logic_st.edge_detection_logic_st 
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":200:0:200:6|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":202:17:202:29|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":225:0:225:6|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":227:17:227:29|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":246:23:246:29|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":248:17:248:29|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":268:15:268:21|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":270:17:270:29|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":290:0:290:6|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":292:20:292:32|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":311:6:311:12|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":313:20:313:32|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":321:6:321:12|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":323:20:323:32|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":335:3:335:9|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":337:20:337:32|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":346:0:346:6|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":348:15:348:27|Referenced variable s_reset_state is not in sensitivity list
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":119:9:119:23|Signal speed_pi_done_s is undriven 
Post processing for work.edge_detection_logic_st.edge_detection_logic_st
@W: CL169 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":202:3:202:4|Pruning register speed_pi_done_dly_2  
@N: CL177 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":227:3:227:4|Sharing sequential element iq_pi_start_o.
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":31:7:31:20|Synthesizing work.accumulator_st.accumulator_st 
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":138:4:138:10|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":140:20:140:32|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":154:3:154:9|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":156:20:156:32|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":168:0:168:6|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":170:20:170:32|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":177:4:177:10|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":179:15:179:27|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":190:1:190:7|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":192:15:192:27|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":203:1:203:7|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":205:16:205:28|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":215:1:215:7|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":217:16:217:28|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":226:1:226:7|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":228:16:228:28|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":237:1:237:7|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":239:16:239:28|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":249:1:249:7|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":251:16:251:28|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":261:1:261:7|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":263:16:263:28|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":272:1:272:7|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":274:16:274:28|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":284:1:284:7|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":286:16:286:28|Referenced variable s_reset_state is not in sensitivity list
Post processing for work.accumulator_st.accumulator_st
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\mas.vhd":32:7:32:9|Synthesizing work.mas.mas 
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\mas.vhd":117:27:117:33|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\mas.vhd":119:23:119:35|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\mas.vhd":149:5:149:11|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\mas.vhd":151:23:151:35|Referenced variable s_reset_state is not in sensitivity list
@W: CD796 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\mas.vhd":62:8:62:20|Bit 2 of signal mas_done_sync is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
Post processing for work.mas.mas
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\cpipic.vhd":39:7:39:12|Synthesizing work.cpipic.cpipic 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\cpipic.vhd":333:11:333:29|Signal start_clarke_i_sync is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\cpipic.vhd":334:11:334:30|Signal start_clarke_i_sync1 is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\cpipic.vhd":335:11:335:27|Signal start_park_i_sync is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\cpipic.vhd":336:11:336:28|Signal start_park_i_sync1 is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\cpipic.vhd":337:11:337:28|Signal start_ipark_i_sync is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\cpipic.vhd":338:11:338:29|Signal start_ipark_i_sync1 is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\cpipic.vhd":339:11:339:30|Signal start_iclarke_i_sync is undriven 
@W: CD638 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\cpipic.vhd":340:11:340:31|Signal start_iclarke_i_sync1 is undriven 
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\mas_scheduler.vhd":37:7:37:19|Synthesizing work.mas_scheduler.mas_scheduler 
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\mas_scheduler.vhd":121:29:121:35|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\mas_scheduler.vhd":123:20:123:32|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\mas_scheduler.vhd":139:27:139:33|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\mas_scheduler.vhd":141:20:141:32|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\mas_scheduler.vhd":156:28:156:34|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\mas_scheduler.vhd":158:20:158:32|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\mas_scheduler.vhd":175:30:175:36|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\mas_scheduler.vhd":177:20:177:32|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\mas_scheduler.vhd":198:17:198:23|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\mas_scheduler.vhd":200:20:200:32|Referenced variable s_reset_state is not in sensitivity list
Post processing for work.mas_scheduler.mas_scheduler
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\inverse_clarke.vhd":30:7:30:20|Synthesizing work.inverse_clarke.inverse_clarke 
@N: CD231 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\inverse_clarke.vhd":80:35:80:36|Using onehot encoding for type iclarke_trnsf_states (idle="100000")
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\inverse_clarke.vhd":140:23:140:29|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\inverse_clarke.vhd":142:20:142:32|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\inverse_clarke.vhd":157:27:157:33|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\inverse_clarke.vhd":159:20:159:32|Referenced variable s_reset_state is not in sensitivity list
Post processing for work.inverse_clarke.inverse_clarke
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\inverse_park.vhd":30:7:30:18|Synthesizing work.inverse_park.inverse_park 
@N: CD231 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\inverse_park.vhd":82:33:82:34|Using onehot encoding for type ipark_trnsf_states (idle="100000")
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\inverse_park.vhd":119:23:119:29|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\inverse_park.vhd":121:20:121:32|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\inverse_park.vhd":136:27:136:33|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\inverse_park.vhd":138:20:138:32|Referenced variable s_reset_state is not in sensitivity list
Post processing for work.inverse_park.inverse_park
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\park.vhd":31:7:31:10|Synthesizing work.park.park 
@N: CD231 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\park.vhd":73:27:73:28|Using onehot encoding for type park_trnsf_states (idle="100000")
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\park.vhd":110:11:110:17|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\park.vhd":112:18:112:30|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\park.vhd":127:24:127:30|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\park.vhd":129:18:129:30|Referenced variable s_reset_state is not in sensitivity list
Post processing for work.park.park
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":30:7:30:12|Synthesizing work.clarke.clarke 
@N: CD233 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":79:34:79:35|Using sequential encoding for type clarke_trnsf_states
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":126:14:126:20|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":128:20:128:32|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":143:27:143:33|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":145:20:145:32|Referenced variable s_reset_state is not in sensitivity list
Post processing for work.clarke.clarke
@A: CL282 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":145:6:145:7|Feedback mux created for signal mul_b_to_mas_o[17:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@W: CL189 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":145:6:145:7|Register bit mul_b_to_mas_o(1) is always 1, optimizing ...
@W: CL189 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":145:6:145:7|Register bit mul_b_to_mas_o(2) is always 1, optimizing ...
@W: CL189 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":145:6:145:7|Register bit mul_b_to_mas_o(3) is always 1, optimizing ...
@W: CL189 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":145:6:145:7|Register bit mul_b_to_mas_o(5) is always 0, optimizing ...
@W: CL189 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":145:6:145:7|Register bit mul_b_to_mas_o(8) is always 0, optimizing ...
@W: CL189 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":145:6:145:7|Register bit mul_b_to_mas_o(11) is always 0, optimizing ...
@W: CL189 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":145:6:145:7|Register bit mul_b_to_mas_o(12) is always 0, optimizing ...
@W: CL189 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":145:6:145:7|Register bit mul_b_to_mas_o(13) is always 0, optimizing ...
@W: CL189 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":145:6:145:7|Register bit mul_b_to_mas_o(14) is always 0, optimizing ...
@W: CL189 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":145:6:145:7|Register bit mul_b_to_mas_o(15) is always 0, optimizing ...
@W: CL189 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":145:6:145:7|Register bit mul_b_to_mas_o(16) is always 0, optimizing ...
@W: CL189 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":145:6:145:7|Register bit mul_b_to_mas_o(17) is always 0, optimizing ...
@W: CL279 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":145:6:145:7|Pruning register bits 17 to 11 of mul_b_to_mas_o(17 downto 0)  
@W: CL260 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":145:6:145:7|Pruning register bit 8 of mul_b_to_mas_o(17 downto 0)  
@W: CL260 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":145:6:145:7|Pruning register bit 5 of mul_b_to_mas_o(17 downto 0)  
@W: CL279 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":145:6:145:7|Pruning register bits 3 to 1 of mul_b_to_mas_o(17 downto 0)  
Post processing for work.cpipic.cpipic
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":31:7:31:22|Synthesizing work.adc_measurements.adc_measurements 
@N: CD231 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":117:26:117:27|Using onehot encoding for type adc_op_state (idle="1000000000")
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":228:20:228:26|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":230:22:230:34|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":250:18:250:24|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":252:22:252:34|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":270:16:270:22|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":272:22:272:34|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":293:20:293:26|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":295:22:295:34|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":338:23:338:29|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":340:22:340:34|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":404:16:404:22|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":406:19:406:31|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":439:23:439:29|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":441:20:441:32|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":505:20:505:26|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":507:20:507:32|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":526:22:526:28|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":528:20:528:32|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":565:28:565:34|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":567:20:567:32|Referenced variable s_reset_state is not in sensitivity list
@E: CD297 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":635:31:635:46|Width mismatch, location has width 14, value 12
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Oct 08 12:10:10 2014

###########################################################]
