-- Version: v11.7 SP1 11.7.1.14

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity MC_System_sb_FABOSC_0_OSC is

    port( FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC : out   std_logic
        );

end MC_System_sb_FABOSC_0_OSC;

architecture DEF_ARCH of MC_System_sb_FABOSC_0_OSC is 

  component RCOSC_25_50MHZ
    generic (FREQUENCY:real := 50.0);

    port( CLKOUT : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \GND\, \VCC\ : std_logic;

begin 


    I_RCOSC_25_50MHZ : RCOSC_25_50MHZ
      generic map(FREQUENCY => 50.000000)

      port map(CLKOUT => 
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC);
    
    VCC_Z : VCC
      port map(Y => \VCC\);
    
    GND_Z : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity COREAPB3_MUXPTOB3 is

    port( MC_System_0_AMBA_SLAVE_0_PADDR                    : in    std_logic_vector(2 to 2);
          prdata_o_1_iv_0_0_6                               : in    std_logic;
          prdata_o_1_iv_0_0_0                               : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_4                       : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_6                       : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_1                       : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_0                       : in    std_logic;
          prdata_o_1_iv_0_0_a3_2_0                          : in    std_logic_vector(9 to 9);
          prdata_o_1_iv_0_0_a1                              : in    std_logic_vector(6 downto 5);
          prdata_o_1_iv_0_12                                : in    std_logic_vector(5 to 5);
          OLMNG_0_theta_o_1                                 : in    std_logic;
          OLMNG_0_theta_o_4                                 : in    std_logic;
          OLMNG_0_theta_o_0                                 : in    std_logic;
          OLMNG_0_theta_o_6                                 : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_1                 : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_4                 : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_0                 : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_6                 : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_1                 : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_4                 : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_0                 : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_6                 : in    std_logic;
          prdata_o_1_iv_0_16_0                              : in    std_logic;
          prdata_o_1_iv_0_16_5                              : in    std_logic;
          prdata_o_1_iv_0_14_0                              : in    std_logic;
          prdata_o_1_iv_0_14_5                              : in    std_logic;
          prdata_o_1_0_iv_0_11                              : in    std_logic_vector(16 to 16);
          prdata_o_1_0_iv_0_5                               : in    std_logic_vector(16 to 16);
          prdata_o_1_0_iv_0_3                               : in    std_logic_vector(16 to 16);
          prdata_o_1_0_iv_0_4                               : in    std_logic_vector(16 to 16);
          FOC_TRANSFORMS_0_iq_o_0                           : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_3                           : in    std_logic;
          prdata_o_1_iv_0_0_13                              : in    std_logic_vector(7 to 7);
          prdata_o_1_iv_0_0_5                               : in    std_logic_vector(7 to 7);
          FOC_TRANSFORMS_0_id_o                             : in    std_logic_vector(4 to 4);
          adc_interface_0_result_ch1_o                      : in    std_logic_vector(4 to 4);
          prdata_o_1_iv_0_0_7                               : in    std_logic_vector(10 to 10);
          prdata_o_1_iv_0_8                                 : in    std_logic_vector(5 to 5);
          prdata_o_1_iv_0_7                                 : in    std_logic_vector(5 to 5);
          prdata_o_1_iv_0_9                                 : in    std_logic_vector(5 to 5);
          prdata_o_1_iv_0_6                                 : in    std_logic_vector(5 to 5);
          prdata_o_1_0_iv_0_0_8                             : in    std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_0_7                             : in    std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_0_11_a2                         : in    std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_0_11_a0                         : in    std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_0_6                             : in    std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_9                               : in    std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_8                               : in    std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_7_0                             : in    std_logic;
          prdata_o_1_0_iv_0_7_9                             : in    std_logic;
          prdata_o_1_0_iv_0_11_a2                           : in    std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_11_a0                           : in    std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_6_3                             : in    std_logic;
          prdata_o_1_0_iv_0_6_0                             : in    std_logic;
          prdata_o_1_0_iv_0_0_14                            : in    std_logic_vector(3 to 3);
          MC_System_0_AMBA_SLAVE_0_PRDATA                   : in    std_logic_vector(19 to 19);
          prdata_o_0_5                                      : in    std_logic_vector(17 to 17);
          prdata_o_0_3                                      : in    std_logic_vector(17 to 17);
          prdata_o_1_0_iv_0_1                               : in    std_logic_vector(17 to 17);
          prdata_o_1_iv_0_0_16                              : in    std_logic_vector(9 downto 8);
          prdata_o_1_iv_0_0_15                              : in    std_logic_vector(8 to 8);
          prdata_o_1_iv_0_0_14                              : in    std_logic_vector(10 downto 8);
          prdata_o_1_0_iv_0_16                              : in    std_logic_vector(2 downto 0);
          prdata_o_1_0_iv_0_15_4                            : in    std_logic;
          prdata_o_1_0_iv_0_15_0                            : in    std_logic;
          prdata_o_1_0_iv_0_15_1                            : in    std_logic;
          prdata_o_1_0_iv_0_15_2                            : in    std_logic;
          prdata_o_1_0_iv_0_14_4                            : in    std_logic;
          prdata_o_1_0_iv_0_14_0                            : in    std_logic;
          prdata_o_1_0_iv_0_14_1                            : in    std_logic;
          prdata_o_1_0_iv_0_14_2                            : in    std_logic;
          prdata_o_1_iv_0_0_12_0                            : in    std_logic;
          prdata_o_1_iv_0_0_12_3                            : in    std_logic;
          prdata_o_1_iv_0_0_12_5                            : in    std_logic;
          prdata_o_1_iv_0_0_11_0                            : in    std_logic;
          prdata_o_1_iv_0_0_11_2                            : in    std_logic;
          prdata_o_1_iv_0_0_10_0                            : in    std_logic;
          prdata_o_1_iv_0_0_10_2                            : in    std_logic;
          prdata_o_1_0_iv_0_0_10_0                          : in    std_logic;
          prdata_o_1_0_iv_0_0_10_12                         : in    std_logic;
          prdata_o_1_0_iv_0_0_11                            : in    std_logic_vector(15 to 15);
          prdata_o_1_0_iv_0_0_9_11                          : in    std_logic;
          prdata_o_1_0_iv_0_0_9_0                           : in    std_logic;
          prdata_o_1_0_iv_0_0_9_12                          : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15 : out   std_logic;
          N_737                                             : in    std_logic;
          N_730                                             : in    std_logic;
          prdata_o276                                       : in    std_logic;
          N_358                                             : in    std_logic;
          N_705                                             : in    std_logic;
          prdata_o_1_iv_0_0_a3_0_out                        : in    std_logic;
          prdata_m1_e_8_1                                   : in    std_logic;
          prdata_m1_e_12_1                                  : in    std_logic;
          prdata_o_1_iv_0_0_a3_9_out                        : in    std_logic;
          MC_System_0_AMBA_SLAVE_0_PSELx                    : in    std_logic;
          N_734                                             : in    std_logic;
          N_634                                             : in    std_logic;
          N_449                                             : in    std_logic;
          N_442                                             : in    std_logic;
          N_440                                             : in    std_logic;
          prdata_N_5_mux_6                                  : in    std_logic;
          prdata_m1_e_4_1                                   : in    std_logic;
          prdata_N_5_mux_7                                  : in    std_logic;
          N_759                                             : in    std_logic;
          prdata_o_1_iv_0_0_a3_27_out                       : in    std_logic;
          G_15_1                                            : in    std_logic;
          N_748                                             : in    std_logic;
          N_462                                             : in    std_logic
        );

end COREAPB3_MUXPTOB3;

architecture DEF_ARCH of COREAPB3_MUXPTOB3 is 

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal PRDATA_1 : std_logic_vector(16 downto 5);
    signal PRDATA_N_4L5_1_sx_Z, PRDATA_N_5L7_0_1_Z, 
        PRDATA_N_4L5_0_sx_Z, PRDATA_N_5L7_1_Z, PRDATA_N_2L1_Z, 
        PRDATA_N_5L7_1_0, PRDATA_N_5L7_Z, PRDATA_N_7L12_1_Z, 
        PRDATA_N_7L12_1_0, PRDATA_N_7L12_Z, PRDATA_N_4L6_Z, 
        PRDATA_N_2L1_1_Z, PRDATA_N_5L7_0_1_0, PRDATA_N_5L7_0_Z, 
        PRDATA_N_6L10_0_Z, PRDATA_N_7L12_0_1_Z, PRDATA_N_7L12_0_Z, 
        PRDATA_N_4L6_0_Z, PRDATA_N_2L1_2_Z, PRDATA_N_2L1_0_Z, 
        PRDATA_N_4L5_Z, PRDATA_N_5L9_Z, PRDATA_N_6L11_Z, 
        PRDATA_N_7L13_Z, \GND\, \VCC\ : std_logic;

begin 


    PRDATA_N_6L10_0 : CFG3
      generic map(INIT => x"0D")

      port map(A => HALL_INTERFACE_1_theta_output_o_0, B => 
        prdata_o276, C => prdata_o_1_iv_0_0_a1(5), Y => 
        PRDATA_N_6L10_0_Z);
    
    \PRDATA[14]\ : CFG4
      generic map(INIT => x"CC8C")

      port map(A => prdata_o_1_0_iv_0_0_9_11, B => 
        MC_System_0_AMBA_SLAVE_0_PSELx, C => PRDATA_1(14), D => 
        prdata_o_1_0_iv_0_0_8(14), Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14);
    
    \PRDATA_1[5]\ : CFG4
      generic map(INIT => x"0001")

      port map(A => prdata_o_1_iv_0_8(5), B => 
        prdata_o_1_iv_0_7(5), C => prdata_o_1_iv_0_9(5), D => 
        prdata_o_1_iv_0_6(5), Y => PRDATA_1(5));
    
    PRDATA_N_5L7_0_1 : CFG4
      generic map(INIT => x"3313")

      port map(A => prdata_o_1_iv_0_0_a3_0_out, B => 
        prdata_m1_e_12_1, C => FOC_TRANSFORMS_0_valpha_o_1, D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => 
        PRDATA_N_5L7_0_1_0);
    
    PRDATA_N_6L11 : CFG3
      generic map(INIT => x"13")

      port map(A => N_748, B => PRDATA_N_5L9_Z, C => 
        adc_interface_0_result_ch1_o(4), Y => PRDATA_N_6L11_Z);
    
    \PRDATA[4]\ : CFG4
      generic map(INIT => x"F0D0")

      port map(A => PRDATA_N_7L13_Z, B => prdata_o_1_0_iv_0_15_4, 
        C => MC_System_0_AMBA_SLAVE_0_PSELx, D => 
        prdata_o_1_0_iv_0_14_4, Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4);
    
    PRDATA_N_4L5_0_sx : CFG4
      generic map(INIT => x"C0EA")

      port map(A => HALL_INTERFACE_1_theta_output_o_4, B => 
        OLMNG_0_theta_o_4, C => N_730, D => prdata_o276, Y => 
        PRDATA_N_4L5_0_sx_Z);
    
    PRDATA_N_2L1 : CFG2
      generic map(INIT => x"7")

      port map(A => N_734, B => FOC_TRANSFORMS_0_iq_o_3, Y => 
        PRDATA_N_2L1_Z);
    
    \PRDATA[10]\ : CFG4
      generic map(INIT => x"F0B0")

      port map(A => prdata_o_1_iv_0_0_14(10), B => PRDATA_1(10), 
        C => MC_System_0_AMBA_SLAVE_0_PSELx, D => 
        prdata_o_1_iv_0_0_11_0, Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10);
    
    \PRDATA[2]\ : CFG4
      generic map(INIT => x"F0E0")

      port map(A => prdata_o_1_0_iv_0_16(2), B => 
        prdata_o_1_0_iv_0_15_2, C => 
        MC_System_0_AMBA_SLAVE_0_PSELx, D => 
        prdata_o_1_0_iv_0_14_2, Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2);
    
    \PRDATA[1]\ : CFG4
      generic map(INIT => x"F0E0")

      port map(A => prdata_o_1_0_iv_0_16(1), B => 
        prdata_o_1_0_iv_0_15_1, C => 
        MC_System_0_AMBA_SLAVE_0_PSELx, D => 
        prdata_o_1_0_iv_0_14_1, Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1);
    
    PRDATA_N_2L1_2 : CFG2
      generic map(INIT => x"7")

      port map(A => prdata_o_1_iv_0_0_a3_2_0(9), B => 
        OLMNG_0_theta_o_0, Y => PRDATA_N_2L1_2_Z);
    
    \PRDATA[8]\ : CFG4
      generic map(INIT => x"F0E0")

      port map(A => prdata_o_1_iv_0_0_16(8), B => 
        prdata_o_1_iv_0_0_15(8), C => 
        MC_System_0_AMBA_SLAVE_0_PSELx, D => 
        prdata_o_1_iv_0_0_14(8), Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8);
    
    \PRDATA[12]\ : CFG4
      generic map(INIT => x"F0E0")

      port map(A => prdata_o_1_iv_0_0_12_5, B => 
        prdata_o_1_iv_0_0_11_2, C => 
        MC_System_0_AMBA_SLAVE_0_PSELx, D => 
        prdata_o_1_iv_0_0_10_2, Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12);
    
    PRDATA_N_4L5_1_sx : CFG4
      generic map(INIT => x"C0EA")

      port map(A => HALL_INTERFACE_1_theta_output_o_1, B => 
        OLMNG_0_theta_o_1, C => N_730, D => prdata_o276, Y => 
        PRDATA_N_4L5_1_sx_Z);
    
    \PRDATA[5]\ : CFG4
      generic map(INIT => x"AA2A")

      port map(A => MC_System_0_AMBA_SLAVE_0_PSELx, B => 
        PRDATA_1(5), C => PRDATA_N_7L12_0_Z, D => 
        prdata_o_1_iv_0_12(5), Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5);
    
    PRDATA_N_4L6_0 : CFG4
      generic map(INIT => x"00B3")

      port map(A => prdata_o_1_iv_0_0_a3_9_out, B => 
        PRDATA_N_2L1_2_Z, C => SPEED_ID_IQ_PI_0_id_pi_output_o_0, 
        D => MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => 
        PRDATA_N_4L6_0_Z);
    
    PRDATA_N_4L5_1 : CFG4
      generic map(INIT => x"0007")

      port map(A => SPEED_ID_IQ_PI_0_id_pi_output_o_1, B => N_737, 
        C => prdata_o_1_iv_0_0_a1(6), D => PRDATA_N_4L5_1_sx_Z, Y
         => PRDATA_N_5L7_0_1_Z);
    
    \PRDATA_1[14]\ : CFG4
      generic map(INIT => x"0001")

      port map(A => prdata_o_1_0_iv_0_0_7(14), B => 
        prdata_o_1_0_iv_0_0_11_a2(14), C => 
        prdata_o_1_0_iv_0_0_11_a0(14), D => 
        prdata_o_1_0_iv_0_0_6(14), Y => PRDATA_1(14));
    
    \PRDATA[15]\ : CFG4
      generic map(INIT => x"F0E0")

      port map(A => prdata_o_1_0_iv_0_0_10_12, B => 
        prdata_o_1_0_iv_0_0_11(15), C => 
        MC_System_0_AMBA_SLAVE_0_PSELx, D => 
        prdata_o_1_0_iv_0_0_9_12, Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15);
    
    PRDATA_N_4L5_0 : CFG4
      generic map(INIT => x"0111")

      port map(A => N_358, B => PRDATA_N_4L5_0_sx_Z, C => 
        SPEED_ID_IQ_PI_0_id_pi_output_o_4, D => N_737, Y => 
        PRDATA_N_5L7_1_Z);
    
    PRDATA_N_7L12 : CFG4
      generic map(INIT => x"2202")

      port map(A => PRDATA_N_7L12_1_Z, B => prdata_o_1_iv_0_0_6, 
        C => N_705, D => PRDATA_N_7L12_1_0, Y => PRDATA_N_7L12_Z);
    
    \PRDATA_1[10]\ : CFG4
      generic map(INIT => x"0001")

      port map(A => prdata_o_1_iv_0_0_10_0, B => 
        prdata_o_1_iv_0_0_12_3, C => N_462, D => 
        prdata_o_1_iv_0_0_7(10), Y => PRDATA_1(10));
    
    \PRDATA[0]\ : CFG4
      generic map(INIT => x"F0E0")

      port map(A => prdata_o_1_0_iv_0_16(0), B => 
        prdata_o_1_0_iv_0_15_0, C => 
        MC_System_0_AMBA_SLAVE_0_PSELx, D => 
        prdata_o_1_0_iv_0_14_0, Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0);
    
    \PRDATA_1[7]\ : CFG4
      generic map(INIT => x"0001")

      port map(A => prdata_o_1_iv_0_0_12_0, B => N_449, C => 
        N_442, D => N_440, Y => PRDATA_1(7));
    
    \PRDATA[3]\ : CFG4
      generic map(INIT => x"AAA8")

      port map(A => MC_System_0_AMBA_SLAVE_0_PSELx, B => 
        prdata_o_1_0_iv_0_0_10_0, C => prdata_o_1_0_iv_0_0_14(3), 
        D => prdata_o_1_0_iv_0_0_9_0, Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3);
    
    PRDATA_N_2L1_0 : CFG2
      generic map(INIT => x"7")

      port map(A => prdata_o_1_iv_0_0_a3_2_0(9), B => 
        OLMNG_0_theta_o_6, Y => PRDATA_N_2L1_0_Z);
    
    \PRDATA[17]\ : CFG4
      generic map(INIT => x"F0E0")

      port map(A => prdata_o_0_5(17), B => prdata_o_0_3(17), C
         => MC_System_0_AMBA_SLAVE_0_PSELx, D => 
        prdata_o_1_0_iv_0_1(17), Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17);
    
    GND_Z : GND
      port map(Y => \GND\);
    
    VCC_Z : VCC
      port map(Y => \VCC\);
    
    \PRDATA_1[16]\ : CFG3
      generic map(INIT => x"01")

      port map(A => prdata_o_1_0_iv_0_5(16), B => 
        prdata_o_1_0_iv_0_3(16), C => prdata_o_1_0_iv_0_4(16), Y
         => PRDATA_1(16));
    
    PRDATA_N_7L12_0_1 : CFG4
      generic map(INIT => x"3313")

      port map(A => prdata_o_1_iv_0_0_a3_0_out, B => 
        PRDATA_N_4L6_0_Z, C => FOC_TRANSFORMS_0_valpha_o_0, D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => 
        PRDATA_N_7L12_0_1_Z);
    
    \PRDATA[9]\ : CFG4
      generic map(INIT => x"F0B0")

      port map(A => prdata_o_1_iv_0_0_16(9), B => PRDATA_N_5L7_Z, 
        C => MC_System_0_AMBA_SLAVE_0_PSELx, D => 
        prdata_o_1_iv_0_0_14(9), Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9);
    
    \PRDATA[6]\ : CFG4
      generic map(INIT => x"F0B0")

      port map(A => prdata_o_1_iv_0_16_0, B => PRDATA_N_5L7_0_Z, 
        C => MC_System_0_AMBA_SLAVE_0_PSELx, D => 
        prdata_o_1_iv_0_14_0, Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6);
    
    \PRDATA[13]\ : CFG4
      generic map(INIT => x"CC8C")

      port map(A => prdata_o_1_0_iv_0_9(13), B => 
        MC_System_0_AMBA_SLAVE_0_PSELx, C => PRDATA_1(13), D => 
        prdata_o_1_0_iv_0_8(13), Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13);
    
    PRDATA_N_6L10 : CFG3
      generic map(INIT => x"51")

      port map(A => N_634, B => HALL_INTERFACE_1_theta_output_o_6, 
        C => prdata_o276, Y => PRDATA_N_7L12_1_Z);
    
    \PRDATA[16]\ : CFG4
      generic map(INIT => x"CCC4")

      port map(A => PRDATA_1(16), B => 
        MC_System_0_AMBA_SLAVE_0_PSELx, C => 
        prdata_o_1_0_iv_0_11(16), D => prdata_o_1_0_iv_0_6_3, Y
         => MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16);
    
    PRDATA_N_5L9 : CFG4
      generic map(INIT => x"8000")

      port map(A => FOC_TRANSFORMS_0_id_o(4), B => N_759, C => 
        prdata_o_1_iv_0_0_a3_27_out, D => G_15_1, Y => 
        PRDATA_N_5L9_Z);
    
    PRDATA_N_4L6 : CFG4
      generic map(INIT => x"00B3")

      port map(A => prdata_o_1_iv_0_0_a3_9_out, B => 
        PRDATA_N_2L1_0_Z, C => SPEED_ID_IQ_PI_0_id_pi_output_o_6, 
        D => MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => 
        PRDATA_N_4L6_Z);
    
    \PRDATA_1[13]\ : CFG4
      generic map(INIT => x"0001")

      port map(A => prdata_o_1_0_iv_0_7_9, B => 
        prdata_o_1_0_iv_0_11_a2(13), C => 
        prdata_o_1_0_iv_0_11_a0(13), D => prdata_o_1_0_iv_0_6_0, 
        Y => PRDATA_1(13));
    
    \PRDATA[7]\ : CFG4
      generic map(INIT => x"F0B0")

      port map(A => prdata_o_1_iv_0_0_13(7), B => PRDATA_1(7), C
         => MC_System_0_AMBA_SLAVE_0_PSELx, D => 
        prdata_o_1_iv_0_0_5(7), Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7);
    
    \PRDATA[18]\ : CFG2
      generic map(INIT => x"8")

      port map(A => MC_System_0_AMBA_SLAVE_0_PSELx, B => 
        MC_System_0_AMBA_SLAVE_0_PRDATA(19), Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31);
    
    PRDATA_N_5L7_0 : CFG4
      generic map(INIT => x"8088")

      port map(A => PRDATA_N_2L1_1_Z, B => PRDATA_N_5L7_0_1_Z, C
         => PRDATA_N_5L7_0_1_0, D => N_705, Y => PRDATA_N_5L7_0_Z);
    
    PRDATA_N_7L13 : CFG4
      generic map(INIT => x"00B0")

      port map(A => PRDATA_N_4L5_Z, B => N_705, C => 
        PRDATA_N_6L11_Z, D => prdata_o_1_0_iv_0_7_0, Y => 
        PRDATA_N_7L13_Z);
    
    PRDATA_N_2L1_1 : CFG2
      generic map(INIT => x"7")

      port map(A => N_734, B => FOC_TRANSFORMS_0_iq_o_0, Y => 
        PRDATA_N_2L1_1_Z);
    
    PRDATA_N_4L5 : CFG3
      generic map(INIT => x"01")

      port map(A => prdata_N_5_mux_6, B => prdata_m1_e_4_1, C => 
        prdata_N_5_mux_7, Y => PRDATA_N_4L5_Z);
    
    PRDATA_N_7L12_1 : CFG4
      generic map(INIT => x"3313")

      port map(A => prdata_o_1_iv_0_0_a3_0_out, B => 
        PRDATA_N_4L6_Z, C => FOC_TRANSFORMS_0_valpha_o_6, D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => PRDATA_N_7L12_1_0);
    
    PRDATA_N_5L7_1 : CFG4
      generic map(INIT => x"3313")

      port map(A => prdata_o_1_iv_0_0_a3_0_out, B => 
        prdata_m1_e_8_1, C => FOC_TRANSFORMS_0_valpha_o_4, D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => PRDATA_N_5L7_1_0);
    
    \PRDATA[11]\ : CFG4
      generic map(INIT => x"CCC4")

      port map(A => PRDATA_N_7L12_Z, B => 
        MC_System_0_AMBA_SLAVE_0_PSELx, C => prdata_o_1_iv_0_16_5, 
        D => prdata_o_1_iv_0_14_5, Y => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11);
    
    PRDATA_N_7L12_0 : CFG4
      generic map(INIT => x"2202")

      port map(A => PRDATA_N_6L10_0_Z, B => prdata_o_1_iv_0_0_0, 
        C => N_705, D => PRDATA_N_7L12_0_1_Z, Y => 
        PRDATA_N_7L12_0_Z);
    
    PRDATA_N_5L7 : CFG4
      generic map(INIT => x"8088")

      port map(A => PRDATA_N_2L1_Z, B => PRDATA_N_5L7_1_Z, C => 
        PRDATA_N_5L7_1_0, D => N_705, Y => PRDATA_N_5L7_Z);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity CoreAPB3 is

    port( MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR     : in    std_logic_vector(15 downto 12);
          MC_System_0_AMBA_SLAVE_0_PADDR                    : in    std_logic_vector(2 to 2);
          prdata_o_1_iv_0_0_6                               : in    std_logic;
          prdata_o_1_iv_0_0_0                               : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_4                       : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_6                       : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_1                       : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_0                       : in    std_logic;
          prdata_o_1_iv_0_0_a3_2_0                          : in    std_logic_vector(9 to 9);
          prdata_o_1_iv_0_0_a1                              : in    std_logic_vector(6 downto 5);
          prdata_o_1_iv_0_12                                : in    std_logic_vector(5 to 5);
          OLMNG_0_theta_o_1                                 : in    std_logic;
          OLMNG_0_theta_o_4                                 : in    std_logic;
          OLMNG_0_theta_o_0                                 : in    std_logic;
          OLMNG_0_theta_o_6                                 : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_1                 : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_4                 : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_0                 : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_6                 : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_1                 : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_4                 : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_0                 : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_6                 : in    std_logic;
          prdata_o_1_iv_0_16_0                              : in    std_logic;
          prdata_o_1_iv_0_16_5                              : in    std_logic;
          prdata_o_1_iv_0_14_0                              : in    std_logic;
          prdata_o_1_iv_0_14_5                              : in    std_logic;
          prdata_o_1_0_iv_0_11                              : in    std_logic_vector(16 to 16);
          prdata_o_1_0_iv_0_5                               : in    std_logic_vector(16 to 16);
          prdata_o_1_0_iv_0_3                               : in    std_logic_vector(16 to 16);
          prdata_o_1_0_iv_0_4                               : in    std_logic_vector(16 to 16);
          FOC_TRANSFORMS_0_iq_o_0                           : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_3                           : in    std_logic;
          prdata_o_1_iv_0_0_13                              : in    std_logic_vector(7 to 7);
          prdata_o_1_iv_0_0_5                               : in    std_logic_vector(7 to 7);
          FOC_TRANSFORMS_0_id_o                             : in    std_logic_vector(4 to 4);
          adc_interface_0_result_ch1_o                      : in    std_logic_vector(4 to 4);
          prdata_o_1_iv_0_0_7                               : in    std_logic_vector(10 to 10);
          prdata_o_1_iv_0_8                                 : in    std_logic_vector(5 to 5);
          prdata_o_1_iv_0_7                                 : in    std_logic_vector(5 to 5);
          prdata_o_1_iv_0_9                                 : in    std_logic_vector(5 to 5);
          prdata_o_1_iv_0_6                                 : in    std_logic_vector(5 to 5);
          prdata_o_1_0_iv_0_0_8                             : in    std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_0_7                             : in    std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_0_11_a2                         : in    std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_0_11_a0                         : in    std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_0_6                             : in    std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_9                               : in    std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_8                               : in    std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_7_0                             : in    std_logic;
          prdata_o_1_0_iv_0_7_9                             : in    std_logic;
          prdata_o_1_0_iv_0_11_a2                           : in    std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_11_a0                           : in    std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_6_3                             : in    std_logic;
          prdata_o_1_0_iv_0_6_0                             : in    std_logic;
          prdata_o_1_0_iv_0_0_14                            : in    std_logic_vector(3 to 3);
          MC_System_0_AMBA_SLAVE_0_PRDATA                   : in    std_logic_vector(19 to 19);
          prdata_o_0_5                                      : in    std_logic_vector(17 to 17);
          prdata_o_0_3                                      : in    std_logic_vector(17 to 17);
          prdata_o_1_0_iv_0_1                               : in    std_logic_vector(17 to 17);
          prdata_o_1_iv_0_0_16                              : in    std_logic_vector(9 downto 8);
          prdata_o_1_iv_0_0_15                              : in    std_logic_vector(8 to 8);
          prdata_o_1_iv_0_0_14                              : in    std_logic_vector(10 downto 8);
          prdata_o_1_0_iv_0_16                              : in    std_logic_vector(2 downto 0);
          prdata_o_1_0_iv_0_15_4                            : in    std_logic;
          prdata_o_1_0_iv_0_15_0                            : in    std_logic;
          prdata_o_1_0_iv_0_15_1                            : in    std_logic;
          prdata_o_1_0_iv_0_15_2                            : in    std_logic;
          prdata_o_1_0_iv_0_14_4                            : in    std_logic;
          prdata_o_1_0_iv_0_14_0                            : in    std_logic;
          prdata_o_1_0_iv_0_14_1                            : in    std_logic;
          prdata_o_1_0_iv_0_14_2                            : in    std_logic;
          prdata_o_1_iv_0_0_12_0                            : in    std_logic;
          prdata_o_1_iv_0_0_12_3                            : in    std_logic;
          prdata_o_1_iv_0_0_12_5                            : in    std_logic;
          prdata_o_1_iv_0_0_11_0                            : in    std_logic;
          prdata_o_1_iv_0_0_11_2                            : in    std_logic;
          prdata_o_1_iv_0_0_10_0                            : in    std_logic;
          prdata_o_1_iv_0_0_10_2                            : in    std_logic;
          prdata_o_1_0_iv_0_0_10_0                          : in    std_logic;
          prdata_o_1_0_iv_0_0_10_12                         : in    std_logic;
          prdata_o_1_0_iv_0_0_11                            : in    std_logic_vector(15 to 15);
          prdata_o_1_0_iv_0_0_9_11                          : in    std_logic;
          prdata_o_1_0_iv_0_0_9_0                           : in    std_logic;
          prdata_o_1_0_iv_0_0_9_12                          : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx     : in    std_logic;
          MC_System_0_AMBA_SLAVE_0_PSELx                    : out   std_logic;
          N_737                                             : in    std_logic;
          N_730                                             : in    std_logic;
          prdata_o276                                       : in    std_logic;
          N_358                                             : in    std_logic;
          N_705                                             : in    std_logic;
          prdata_o_1_iv_0_0_a3_0_out                        : in    std_logic;
          prdata_m1_e_8_1                                   : in    std_logic;
          prdata_m1_e_12_1                                  : in    std_logic;
          prdata_o_1_iv_0_0_a3_9_out                        : in    std_logic;
          N_734                                             : in    std_logic;
          N_634                                             : in    std_logic;
          N_449                                             : in    std_logic;
          N_442                                             : in    std_logic;
          N_440                                             : in    std_logic;
          prdata_N_5_mux_6                                  : in    std_logic;
          prdata_m1_e_4_1                                   : in    std_logic;
          prdata_N_5_mux_7                                  : in    std_logic;
          N_759                                             : in    std_logic;
          prdata_o_1_iv_0_0_a3_27_out                       : in    std_logic;
          G_15_1                                            : in    std_logic;
          N_748                                             : in    std_logic;
          N_462                                             : in    std_logic
        );

end CoreAPB3;

architecture DEF_ARCH of CoreAPB3 is 

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component COREAPB3_MUXPTOB3
    port( MC_System_0_AMBA_SLAVE_0_PADDR                    : in    std_logic_vector(2 to 2) := (others => 'U');
          prdata_o_1_iv_0_0_6                               : in    std_logic := 'U';
          prdata_o_1_iv_0_0_0                               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_4                       : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_6                       : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_1                       : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_0                       : in    std_logic := 'U';
          prdata_o_1_iv_0_0_a3_2_0                          : in    std_logic_vector(9 to 9) := (others => 'U');
          prdata_o_1_iv_0_0_a1                              : in    std_logic_vector(6 downto 5) := (others => 'U');
          prdata_o_1_iv_0_12                                : in    std_logic_vector(5 to 5) := (others => 'U');
          OLMNG_0_theta_o_1                                 : in    std_logic := 'U';
          OLMNG_0_theta_o_4                                 : in    std_logic := 'U';
          OLMNG_0_theta_o_0                                 : in    std_logic := 'U';
          OLMNG_0_theta_o_6                                 : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_1                 : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_4                 : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_0                 : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_6                 : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_1                 : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_4                 : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_0                 : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_6                 : in    std_logic := 'U';
          prdata_o_1_iv_0_16_0                              : in    std_logic := 'U';
          prdata_o_1_iv_0_16_5                              : in    std_logic := 'U';
          prdata_o_1_iv_0_14_0                              : in    std_logic := 'U';
          prdata_o_1_iv_0_14_5                              : in    std_logic := 'U';
          prdata_o_1_0_iv_0_11                              : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_0_iv_0_5                               : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_0_iv_0_3                               : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_0_iv_0_4                               : in    std_logic_vector(16 to 16) := (others => 'U');
          FOC_TRANSFORMS_0_iq_o_0                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_3                           : in    std_logic := 'U';
          prdata_o_1_iv_0_0_13                              : in    std_logic_vector(7 to 7) := (others => 'U');
          prdata_o_1_iv_0_0_5                               : in    std_logic_vector(7 to 7) := (others => 'U');
          FOC_TRANSFORMS_0_id_o                             : in    std_logic_vector(4 to 4) := (others => 'U');
          adc_interface_0_result_ch1_o                      : in    std_logic_vector(4 to 4) := (others => 'U');
          prdata_o_1_iv_0_0_7                               : in    std_logic_vector(10 to 10) := (others => 'U');
          prdata_o_1_iv_0_8                                 : in    std_logic_vector(5 to 5) := (others => 'U');
          prdata_o_1_iv_0_7                                 : in    std_logic_vector(5 to 5) := (others => 'U');
          prdata_o_1_iv_0_9                                 : in    std_logic_vector(5 to 5) := (others => 'U');
          prdata_o_1_iv_0_6                                 : in    std_logic_vector(5 to 5) := (others => 'U');
          prdata_o_1_0_iv_0_0_8                             : in    std_logic_vector(14 to 14) := (others => 'U');
          prdata_o_1_0_iv_0_0_7                             : in    std_logic_vector(14 to 14) := (others => 'U');
          prdata_o_1_0_iv_0_0_11_a2                         : in    std_logic_vector(14 to 14) := (others => 'U');
          prdata_o_1_0_iv_0_0_11_a0                         : in    std_logic_vector(14 to 14) := (others => 'U');
          prdata_o_1_0_iv_0_0_6                             : in    std_logic_vector(14 to 14) := (others => 'U');
          prdata_o_1_0_iv_0_9                               : in    std_logic_vector(13 to 13) := (others => 'U');
          prdata_o_1_0_iv_0_8                               : in    std_logic_vector(13 to 13) := (others => 'U');
          prdata_o_1_0_iv_0_7_0                             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_7_9                             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_11_a2                           : in    std_logic_vector(13 to 13) := (others => 'U');
          prdata_o_1_0_iv_0_11_a0                           : in    std_logic_vector(13 to 13) := (others => 'U');
          prdata_o_1_0_iv_0_6_3                             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_6_0                             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_14                            : in    std_logic_vector(3 to 3) := (others => 'U');
          MC_System_0_AMBA_SLAVE_0_PRDATA                   : in    std_logic_vector(19 to 19) := (others => 'U');
          prdata_o_0_5                                      : in    std_logic_vector(17 to 17) := (others => 'U');
          prdata_o_0_3                                      : in    std_logic_vector(17 to 17) := (others => 'U');
          prdata_o_1_0_iv_0_1                               : in    std_logic_vector(17 to 17) := (others => 'U');
          prdata_o_1_iv_0_0_16                              : in    std_logic_vector(9 downto 8) := (others => 'U');
          prdata_o_1_iv_0_0_15                              : in    std_logic_vector(8 to 8) := (others => 'U');
          prdata_o_1_iv_0_0_14                              : in    std_logic_vector(10 downto 8) := (others => 'U');
          prdata_o_1_0_iv_0_16                              : in    std_logic_vector(2 downto 0) := (others => 'U');
          prdata_o_1_0_iv_0_15_4                            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_15_0                            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_15_1                            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_15_2                            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_14_4                            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_14_0                            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_14_1                            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_14_2                            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_12_0                            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_12_3                            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_12_5                            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_11_0                            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_11_2                            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_10_0                            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_10_2                            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_10_0                          : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_10_12                         : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_11                            : in    std_logic_vector(15 to 15) := (others => 'U');
          prdata_o_1_0_iv_0_0_9_11                          : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_9_0                           : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_9_12                          : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15 : out   std_logic;
          N_737                                             : in    std_logic := 'U';
          N_730                                             : in    std_logic := 'U';
          prdata_o276                                       : in    std_logic := 'U';
          N_358                                             : in    std_logic := 'U';
          N_705                                             : in    std_logic := 'U';
          prdata_o_1_iv_0_0_a3_0_out                        : in    std_logic := 'U';
          prdata_m1_e_8_1                                   : in    std_logic := 'U';
          prdata_m1_e_12_1                                  : in    std_logic := 'U';
          prdata_o_1_iv_0_0_a3_9_out                        : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_0_PSELx                    : in    std_logic := 'U';
          N_734                                             : in    std_logic := 'U';
          N_634                                             : in    std_logic := 'U';
          N_449                                             : in    std_logic := 'U';
          N_442                                             : in    std_logic := 'U';
          N_440                                             : in    std_logic := 'U';
          prdata_N_5_mux_6                                  : in    std_logic := 'U';
          prdata_m1_e_4_1                                   : in    std_logic := 'U';
          prdata_N_5_mux_7                                  : in    std_logic := 'U';
          N_759                                             : in    std_logic := 'U';
          prdata_o_1_iv_0_0_a3_27_out                       : in    std_logic := 'U';
          G_15_1                                            : in    std_logic := 'U';
          N_748                                             : in    std_logic := 'U';
          N_462                                             : in    std_logic := 'U'
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \MC_System_0_AMBA_SLAVE_0_PSELx\ : std_logic;
    signal iPSELS_raw_0_a2_1 : std_logic_vector(0 to 0);
    signal \GND\, \VCC\ : std_logic;

    for all : COREAPB3_MUXPTOB3
	Use entity work.COREAPB3_MUXPTOB3(DEF_ARCH);
begin 

    MC_System_0_AMBA_SLAVE_0_PSELx <= 
        \MC_System_0_AMBA_SLAVE_0_PSELx\;

    \iPSELS_raw_0_a2[0]\ : CFG4
      generic map(INIT => x"0200")

      port map(A => MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx, 
        B => MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(15), C
         => MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), D
         => iPSELS_raw_0_a2_1(0), Y => 
        \MC_System_0_AMBA_SLAVE_0_PSELx\);
    
    u_mux_p_to_b3 : COREAPB3_MUXPTOB3
      port map(MC_System_0_AMBA_SLAVE_0_PADDR(2) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), prdata_o_1_iv_0_0_6
         => prdata_o_1_iv_0_0_6, prdata_o_1_iv_0_0_0 => 
        prdata_o_1_iv_0_0_0, FOC_TRANSFORMS_0_valpha_o_4 => 
        FOC_TRANSFORMS_0_valpha_o_4, FOC_TRANSFORMS_0_valpha_o_6
         => FOC_TRANSFORMS_0_valpha_o_6, 
        FOC_TRANSFORMS_0_valpha_o_1 => 
        FOC_TRANSFORMS_0_valpha_o_1, FOC_TRANSFORMS_0_valpha_o_0
         => FOC_TRANSFORMS_0_valpha_o_0, 
        prdata_o_1_iv_0_0_a3_2_0(9) => 
        prdata_o_1_iv_0_0_a3_2_0(9), prdata_o_1_iv_0_0_a1(6) => 
        prdata_o_1_iv_0_0_a1(6), prdata_o_1_iv_0_0_a1(5) => 
        prdata_o_1_iv_0_0_a1(5), prdata_o_1_iv_0_12(5) => 
        prdata_o_1_iv_0_12(5), OLMNG_0_theta_o_1 => 
        OLMNG_0_theta_o_1, OLMNG_0_theta_o_4 => OLMNG_0_theta_o_4, 
        OLMNG_0_theta_o_0 => OLMNG_0_theta_o_0, OLMNG_0_theta_o_6
         => OLMNG_0_theta_o_6, SPEED_ID_IQ_PI_0_id_pi_output_o_1
         => SPEED_ID_IQ_PI_0_id_pi_output_o_1, 
        SPEED_ID_IQ_PI_0_id_pi_output_o_4 => 
        SPEED_ID_IQ_PI_0_id_pi_output_o_4, 
        SPEED_ID_IQ_PI_0_id_pi_output_o_0 => 
        SPEED_ID_IQ_PI_0_id_pi_output_o_0, 
        SPEED_ID_IQ_PI_0_id_pi_output_o_6 => 
        SPEED_ID_IQ_PI_0_id_pi_output_o_6, 
        HALL_INTERFACE_1_theta_output_o_1 => 
        HALL_INTERFACE_1_theta_output_o_1, 
        HALL_INTERFACE_1_theta_output_o_4 => 
        HALL_INTERFACE_1_theta_output_o_4, 
        HALL_INTERFACE_1_theta_output_o_0 => 
        HALL_INTERFACE_1_theta_output_o_0, 
        HALL_INTERFACE_1_theta_output_o_6 => 
        HALL_INTERFACE_1_theta_output_o_6, prdata_o_1_iv_0_16_0
         => prdata_o_1_iv_0_16_0, prdata_o_1_iv_0_16_5 => 
        prdata_o_1_iv_0_16_5, prdata_o_1_iv_0_14_0 => 
        prdata_o_1_iv_0_14_0, prdata_o_1_iv_0_14_5 => 
        prdata_o_1_iv_0_14_5, prdata_o_1_0_iv_0_11(16) => 
        prdata_o_1_0_iv_0_11(16), prdata_o_1_0_iv_0_5(16) => 
        prdata_o_1_0_iv_0_5(16), prdata_o_1_0_iv_0_3(16) => 
        prdata_o_1_0_iv_0_3(16), prdata_o_1_0_iv_0_4(16) => 
        prdata_o_1_0_iv_0_4(16), FOC_TRANSFORMS_0_iq_o_0 => 
        FOC_TRANSFORMS_0_iq_o_0, FOC_TRANSFORMS_0_iq_o_3 => 
        FOC_TRANSFORMS_0_iq_o_3, prdata_o_1_iv_0_0_13(7) => 
        prdata_o_1_iv_0_0_13(7), prdata_o_1_iv_0_0_5(7) => 
        prdata_o_1_iv_0_0_5(7), FOC_TRANSFORMS_0_id_o(4) => 
        FOC_TRANSFORMS_0_id_o(4), adc_interface_0_result_ch1_o(4)
         => adc_interface_0_result_ch1_o(4), 
        prdata_o_1_iv_0_0_7(10) => prdata_o_1_iv_0_0_7(10), 
        prdata_o_1_iv_0_8(5) => prdata_o_1_iv_0_8(5), 
        prdata_o_1_iv_0_7(5) => prdata_o_1_iv_0_7(5), 
        prdata_o_1_iv_0_9(5) => prdata_o_1_iv_0_9(5), 
        prdata_o_1_iv_0_6(5) => prdata_o_1_iv_0_6(5), 
        prdata_o_1_0_iv_0_0_8(14) => prdata_o_1_0_iv_0_0_8(14), 
        prdata_o_1_0_iv_0_0_7(14) => prdata_o_1_0_iv_0_0_7(14), 
        prdata_o_1_0_iv_0_0_11_a2(14) => 
        prdata_o_1_0_iv_0_0_11_a2(14), 
        prdata_o_1_0_iv_0_0_11_a0(14) => 
        prdata_o_1_0_iv_0_0_11_a0(14), prdata_o_1_0_iv_0_0_6(14)
         => prdata_o_1_0_iv_0_0_6(14), prdata_o_1_0_iv_0_9(13)
         => prdata_o_1_0_iv_0_9(13), prdata_o_1_0_iv_0_8(13) => 
        prdata_o_1_0_iv_0_8(13), prdata_o_1_0_iv_0_7_0 => 
        prdata_o_1_0_iv_0_7_0, prdata_o_1_0_iv_0_7_9 => 
        prdata_o_1_0_iv_0_7_9, prdata_o_1_0_iv_0_11_a2(13) => 
        prdata_o_1_0_iv_0_11_a2(13), prdata_o_1_0_iv_0_11_a0(13)
         => prdata_o_1_0_iv_0_11_a0(13), prdata_o_1_0_iv_0_6_3
         => prdata_o_1_0_iv_0_6_3, prdata_o_1_0_iv_0_6_0 => 
        prdata_o_1_0_iv_0_6_0, prdata_o_1_0_iv_0_0_14(3) => 
        prdata_o_1_0_iv_0_0_14(3), 
        MC_System_0_AMBA_SLAVE_0_PRDATA(19) => 
        MC_System_0_AMBA_SLAVE_0_PRDATA(19), prdata_o_0_5(17) => 
        prdata_o_0_5(17), prdata_o_0_3(17) => prdata_o_0_3(17), 
        prdata_o_1_0_iv_0_1(17) => prdata_o_1_0_iv_0_1(17), 
        prdata_o_1_iv_0_0_16(9) => prdata_o_1_iv_0_0_16(9), 
        prdata_o_1_iv_0_0_16(8) => prdata_o_1_iv_0_0_16(8), 
        prdata_o_1_iv_0_0_15(8) => prdata_o_1_iv_0_0_15(8), 
        prdata_o_1_iv_0_0_14(10) => prdata_o_1_iv_0_0_14(10), 
        prdata_o_1_iv_0_0_14(9) => prdata_o_1_iv_0_0_14(9), 
        prdata_o_1_iv_0_0_14(8) => prdata_o_1_iv_0_0_14(8), 
        prdata_o_1_0_iv_0_16(2) => prdata_o_1_0_iv_0_16(2), 
        prdata_o_1_0_iv_0_16(1) => prdata_o_1_0_iv_0_16(1), 
        prdata_o_1_0_iv_0_16(0) => prdata_o_1_0_iv_0_16(0), 
        prdata_o_1_0_iv_0_15_4 => prdata_o_1_0_iv_0_15_4, 
        prdata_o_1_0_iv_0_15_0 => prdata_o_1_0_iv_0_15_0, 
        prdata_o_1_0_iv_0_15_1 => prdata_o_1_0_iv_0_15_1, 
        prdata_o_1_0_iv_0_15_2 => prdata_o_1_0_iv_0_15_2, 
        prdata_o_1_0_iv_0_14_4 => prdata_o_1_0_iv_0_14_4, 
        prdata_o_1_0_iv_0_14_0 => prdata_o_1_0_iv_0_14_0, 
        prdata_o_1_0_iv_0_14_1 => prdata_o_1_0_iv_0_14_1, 
        prdata_o_1_0_iv_0_14_2 => prdata_o_1_0_iv_0_14_2, 
        prdata_o_1_iv_0_0_12_0 => prdata_o_1_iv_0_0_12_0, 
        prdata_o_1_iv_0_0_12_3 => prdata_o_1_iv_0_0_12_3, 
        prdata_o_1_iv_0_0_12_5 => prdata_o_1_iv_0_0_12_5, 
        prdata_o_1_iv_0_0_11_0 => prdata_o_1_iv_0_0_11_0, 
        prdata_o_1_iv_0_0_11_2 => prdata_o_1_iv_0_0_11_2, 
        prdata_o_1_iv_0_0_10_0 => prdata_o_1_iv_0_0_10_0, 
        prdata_o_1_iv_0_0_10_2 => prdata_o_1_iv_0_0_10_2, 
        prdata_o_1_0_iv_0_0_10_0 => prdata_o_1_0_iv_0_0_10_0, 
        prdata_o_1_0_iv_0_0_10_12 => prdata_o_1_0_iv_0_0_10_12, 
        prdata_o_1_0_iv_0_0_11(15) => prdata_o_1_0_iv_0_0_11(15), 
        prdata_o_1_0_iv_0_0_9_11 => prdata_o_1_0_iv_0_0_9_11, 
        prdata_o_1_0_iv_0_0_9_0 => prdata_o_1_0_iv_0_0_9_0, 
        prdata_o_1_0_iv_0_0_9_12 => prdata_o_1_0_iv_0_0_9_12, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15, N_737
         => N_737, N_730 => N_730, prdata_o276 => prdata_o276, 
        N_358 => N_358, N_705 => N_705, 
        prdata_o_1_iv_0_0_a3_0_out => prdata_o_1_iv_0_0_a3_0_out, 
        prdata_m1_e_8_1 => prdata_m1_e_8_1, prdata_m1_e_12_1 => 
        prdata_m1_e_12_1, prdata_o_1_iv_0_0_a3_9_out => 
        prdata_o_1_iv_0_0_a3_9_out, 
        MC_System_0_AMBA_SLAVE_0_PSELx => 
        \MC_System_0_AMBA_SLAVE_0_PSELx\, N_734 => N_734, N_634
         => N_634, N_449 => N_449, N_442 => N_442, N_440 => N_440, 
        prdata_N_5_mux_6 => prdata_N_5_mux_6, prdata_m1_e_4_1 => 
        prdata_m1_e_4_1, prdata_N_5_mux_7 => prdata_N_5_mux_7, 
        N_759 => N_759, prdata_o_1_iv_0_0_a3_27_out => 
        prdata_o_1_iv_0_0_a3_27_out, G_15_1 => G_15_1, N_748 => 
        N_748, N_462 => N_462);
    
    VCC_Z : VCC
      port map(Y => \VCC\);
    
    \iPSELS_raw_0_a2_1[0]\ : CFG2
      generic map(INIT => x"1")

      port map(A => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(14), B => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(13), Y => 
        iPSELS_raw_0_a2_1(0));
    
    GND_Z : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity MC_System_sb_CCC_0_FCCC is

    port( MC_System_0_FIC_0_LOCK                             : out   std_logic;
          MC_System_0_FIC_0_CLK                              : out   std_logic;
          FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC : in    std_logic
        );

end MC_System_sb_CCC_0_FCCC;

architecture DEF_ARCH of MC_System_sb_CCC_0_FCCC is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component CLKINT
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CCC

            generic (INIT:std_logic_vector(209 downto 0) := "00" & x"0000000000000000000000000000000000000000000000000000"; 
        VCOFREQUENCY:real := 0.0);

    port( Y0              : out   std_logic;
          Y1              : out   std_logic;
          Y2              : out   std_logic;
          Y3              : out   std_logic;
          PRDATA          : out   std_logic_vector(7 downto 0);
          LOCK            : out   std_logic;
          BUSY            : out   std_logic;
          CLK0            : in    std_logic := 'U';
          CLK1            : in    std_logic := 'U';
          CLK2            : in    std_logic := 'U';
          CLK3            : in    std_logic := 'U';
          NGMUX0_SEL      : in    std_logic := 'U';
          NGMUX1_SEL      : in    std_logic := 'U';
          NGMUX2_SEL      : in    std_logic := 'U';
          NGMUX3_SEL      : in    std_logic := 'U';
          NGMUX0_HOLD_N   : in    std_logic := 'U';
          NGMUX1_HOLD_N   : in    std_logic := 'U';
          NGMUX2_HOLD_N   : in    std_logic := 'U';
          NGMUX3_HOLD_N   : in    std_logic := 'U';
          NGMUX0_ARST_N   : in    std_logic := 'U';
          NGMUX1_ARST_N   : in    std_logic := 'U';
          NGMUX2_ARST_N   : in    std_logic := 'U';
          NGMUX3_ARST_N   : in    std_logic := 'U';
          PLL_BYPASS_N    : in    std_logic := 'U';
          PLL_ARST_N      : in    std_logic := 'U';
          PLL_POWERDOWN_N : in    std_logic := 'U';
          GPD0_ARST_N     : in    std_logic := 'U';
          GPD1_ARST_N     : in    std_logic := 'U';
          GPD2_ARST_N     : in    std_logic := 'U';
          GPD3_ARST_N     : in    std_logic := 'U';
          PRESET_N        : in    std_logic := 'U';
          PCLK            : in    std_logic := 'U';
          PSEL            : in    std_logic := 'U';
          PENABLE         : in    std_logic := 'U';
          PWRITE          : in    std_logic := 'U';
          PADDR           : in    std_logic_vector(7 downto 2) := (others => 'U');
          PWDATA          : in    std_logic_vector(7 downto 0) := (others => 'U');
          CLK0_PAD        : in    std_logic := 'U';
          CLK1_PAD        : in    std_logic := 'U';
          CLK2_PAD        : in    std_logic := 'U';
          CLK3_PAD        : in    std_logic := 'U';
          GL0             : out   std_logic;
          GL1             : out   std_logic;
          GL2             : out   std_logic;
          GL3             : out   std_logic;
          RCOSC_25_50MHZ  : in    std_logic := 'U';
          RCOSC_1MHZ      : in    std_logic := 'U';
          XTLOSC          : in    std_logic := 'U'
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal PRDATA : std_logic_vector(7 downto 0);
    signal LOCK, GL0_net, Y0, Y1, Y2, Y3, BUSY, \VCC\, \GND\, 
        GL1_net_i, GL2, GL3 : std_logic;

begin 


    VCC_Z : VCC
      port map(Y => \VCC\);
    
    GL0_INST : CLKINT
      port map(A => GL0_net, Y => MC_System_0_FIC_0_CLK);
    
    CCC_INST : CCC

              generic map(INIT => "00" & x"000007FB8000044D64000318C6307C1F18C61EC0404040400301",
         VCOFREQUENCY => 800.000000)

      port map(Y0 => Y0, Y1 => Y1, Y2 => Y2, Y3 => Y3, PRDATA(7)
         => PRDATA(7), PRDATA(6) => PRDATA(6), PRDATA(5) => 
        PRDATA(5), PRDATA(4) => PRDATA(4), PRDATA(3) => PRDATA(3), 
        PRDATA(2) => PRDATA(2), PRDATA(1) => PRDATA(1), PRDATA(0)
         => PRDATA(0), LOCK => LOCK, BUSY => BUSY, CLK0 => \VCC\, 
        CLK1 => \VCC\, CLK2 => \VCC\, CLK3 => \VCC\, NGMUX0_SEL
         => \GND\, NGMUX1_SEL => \GND\, NGMUX2_SEL => \GND\, 
        NGMUX3_SEL => \GND\, NGMUX0_HOLD_N => \VCC\, 
        NGMUX1_HOLD_N => \VCC\, NGMUX2_HOLD_N => \VCC\, 
        NGMUX3_HOLD_N => \VCC\, NGMUX0_ARST_N => \VCC\, 
        NGMUX1_ARST_N => \VCC\, NGMUX2_ARST_N => \VCC\, 
        NGMUX3_ARST_N => \VCC\, PLL_BYPASS_N => \VCC\, PLL_ARST_N
         => \VCC\, PLL_POWERDOWN_N => \VCC\, GPD0_ARST_N => \VCC\, 
        GPD1_ARST_N => \VCC\, GPD2_ARST_N => \VCC\, GPD3_ARST_N
         => \VCC\, PRESET_N => \GND\, PCLK => \VCC\, PSEL => 
        \VCC\, PENABLE => \VCC\, PWRITE => \VCC\, PADDR(7) => 
        \VCC\, PADDR(6) => \VCC\, PADDR(5) => \VCC\, PADDR(4) => 
        \VCC\, PADDR(3) => \VCC\, PADDR(2) => \VCC\, PWDATA(7)
         => \VCC\, PWDATA(6) => \VCC\, PWDATA(5) => \VCC\, 
        PWDATA(4) => \VCC\, PWDATA(3) => \VCC\, PWDATA(2) => 
        \VCC\, PWDATA(1) => \VCC\, PWDATA(0) => \VCC\, CLK0_PAD
         => \GND\, CLK1_PAD => \GND\, CLK2_PAD => \GND\, CLK3_PAD
         => \GND\, GL0 => GL0_net, GL1 => GL1_net_i, GL2 => GL2, 
        GL3 => GL3, RCOSC_25_50MHZ => 
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC, 
        RCOSC_1MHZ => \GND\, XTLOSC => \GND\);
    
    GND_Z : GND
      port map(Y => \GND\);
    
    CCC_INST_RNI2QPF : CLKINT
      port map(A => LOCK, Y => MC_System_0_FIC_0_LOCK);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity MC_System_sb_MSS is

    port( USB_ULPI_DATA                                     : inout std_logic_vector(7 downto 0) := (others => 'Z');
          MC_System_0_AMBA_SLAVE_0_PADDR                    : inout std_logic_vector(11 downto 0) := (others => 'Z');
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR     : out   std_logic_vector(15 downto 12);
          MC_System_0_AMBA_SLAVE_0_PWDATA                   : out   std_logic_vector(17 downto 0);
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0  : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1  : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2  : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3  : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4  : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5  : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6  : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7  : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8  : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9  : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10 : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11 : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12 : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13 : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14 : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15 : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16 : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17 : in    std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31 : in    std_logic;
          USB_ULPI_XCLK                                     : in    std_logic;
          USB_ULPI_STP                                      : out   std_logic;
          USB_ULPI_NXT                                      : in    std_logic;
          USB_ULPI_DIR                                      : in    std_logic;
          N_745                                             : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PENABLE                  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx     : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PWRITE                   : out   std_logic;
          GPIO_0_M2F_c                                      : out   std_logic;
          MC_System_0_FIC_0_LOCK                            : in    std_logic;
          MC_System_0_FIC_0_CLK                             : in    std_logic
        );

end MC_System_sb_MSS;

architecture DEF_ARCH of MC_System_sb_MSS is 

  component GND
    port( Y : out   std_logic
        );
  end component;

  component BIBUF
    generic (IOSTD:string := "");

    port( PAD : inout   std_logic;
          D   : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component INBUF
    generic (IOSTD:string := "");

    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component TRIBUFF
    generic (IOSTD:string := "");

    port( D   : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          PAD : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component MSS_010

            generic (INIT:std_logic_vector(1437 downto 0) := "00" & x"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; 
        ACT_UBITS:std_logic_vector(55 downto 0) := x"FFFFFFFFFFFFFF"; 
        MEMORYFILE:string := ""; RTC_MAIN_XTL_FREQ:real := 0.0; 
        RTC_MAIN_XTL_MODE:string := "1"; DDR_CLK_FREQ:real := 0.0
        );

    port( CAN_RXBUS_MGPIO3A_H2F_A                 : out   std_logic;
          CAN_RXBUS_MGPIO3A_H2F_B                 : out   std_logic;
          CAN_TX_EBL_MGPIO4A_H2F_A                : out   std_logic;
          CAN_TX_EBL_MGPIO4A_H2F_B                : out   std_logic;
          CAN_TXBUS_MGPIO2A_H2F_A                 : out   std_logic;
          CAN_TXBUS_MGPIO2A_H2F_B                 : out   std_logic;
          CLK_CONFIG_APB                          : out   std_logic;
          COMMS_INT                               : out   std_logic;
          CONFIG_PRESET_N                         : out   std_logic;
          EDAC_ERROR                              : out   std_logic_vector(7 downto 0);
          F_FM0_RDATA                             : out   std_logic_vector(31 downto 0);
          F_FM0_READYOUT                          : out   std_logic;
          F_FM0_RESP                              : out   std_logic;
          F_HM0_ADDR                              : out   std_logic_vector(31 downto 0);
          F_HM0_ENABLE                            : out   std_logic;
          F_HM0_SEL                               : out   std_logic;
          F_HM0_SIZE                              : out   std_logic_vector(1 downto 0);
          F_HM0_TRANS1                            : out   std_logic;
          F_HM0_WDATA                             : out   std_logic_vector(31 downto 0);
          F_HM0_WRITE                             : out   std_logic;
          FAB_CHRGVBUS                            : out   std_logic;
          FAB_DISCHRGVBUS                         : out   std_logic;
          FAB_DMPULLDOWN                          : out   std_logic;
          FAB_DPPULLDOWN                          : out   std_logic;
          FAB_DRVVBUS                             : out   std_logic;
          FAB_IDPULLUP                            : out   std_logic;
          FAB_OPMODE                              : out   std_logic_vector(1 downto 0);
          FAB_SUSPENDM                            : out   std_logic;
          FAB_TERMSEL                             : out   std_logic;
          FAB_TXVALID                             : out   std_logic;
          FAB_VCONTROL                            : out   std_logic_vector(3 downto 0);
          FAB_VCONTROLLOADM                       : out   std_logic;
          FAB_XCVRSEL                             : out   std_logic_vector(1 downto 0);
          FAB_XDATAOUT                            : out   std_logic_vector(7 downto 0);
          FACC_GLMUX_SEL                          : out   std_logic;
          FIC32_0_MASTER                          : out   std_logic_vector(1 downto 0);
          FIC32_1_MASTER                          : out   std_logic_vector(1 downto 0);
          FPGA_RESET_N                            : out   std_logic;
          GTX_CLK                                 : out   std_logic;
          H2F_INTERRUPT                           : out   std_logic_vector(15 downto 0);
          H2F_NMI                                 : out   std_logic;
          H2FCALIB                                : out   std_logic;
          I2C0_SCL_MGPIO31B_H2F_A                 : out   std_logic;
          I2C0_SCL_MGPIO31B_H2F_B                 : out   std_logic;
          I2C0_SDA_MGPIO30B_H2F_A                 : out   std_logic;
          I2C0_SDA_MGPIO30B_H2F_B                 : out   std_logic;
          I2C1_SCL_MGPIO1A_H2F_A                  : out   std_logic;
          I2C1_SCL_MGPIO1A_H2F_B                  : out   std_logic;
          I2C1_SDA_MGPIO0A_H2F_A                  : out   std_logic;
          I2C1_SDA_MGPIO0A_H2F_B                  : out   std_logic;
          MDCF                                    : out   std_logic;
          MDOENF                                  : out   std_logic;
          MDOF                                    : out   std_logic;
          MMUART0_CTS_MGPIO19B_H2F_A              : out   std_logic;
          MMUART0_CTS_MGPIO19B_H2F_B              : out   std_logic;
          MMUART0_DCD_MGPIO22B_H2F_A              : out   std_logic;
          MMUART0_DCD_MGPIO22B_H2F_B              : out   std_logic;
          MMUART0_DSR_MGPIO20B_H2F_A              : out   std_logic;
          MMUART0_DSR_MGPIO20B_H2F_B              : out   std_logic;
          MMUART0_DTR_MGPIO18B_H2F_A              : out   std_logic;
          MMUART0_DTR_MGPIO18B_H2F_B              : out   std_logic;
          MMUART0_RI_MGPIO21B_H2F_A               : out   std_logic;
          MMUART0_RI_MGPIO21B_H2F_B               : out   std_logic;
          MMUART0_RTS_MGPIO17B_H2F_A              : out   std_logic;
          MMUART0_RTS_MGPIO17B_H2F_B              : out   std_logic;
          MMUART0_RXD_MGPIO28B_H2F_A              : out   std_logic;
          MMUART0_RXD_MGPIO28B_H2F_B              : out   std_logic;
          MMUART0_SCK_MGPIO29B_H2F_A              : out   std_logic;
          MMUART0_SCK_MGPIO29B_H2F_B              : out   std_logic;
          MMUART0_TXD_MGPIO27B_H2F_A              : out   std_logic;
          MMUART0_TXD_MGPIO27B_H2F_B              : out   std_logic;
          MMUART1_DTR_MGPIO12B_H2F_A              : out   std_logic;
          MMUART1_RTS_MGPIO11B_H2F_A              : out   std_logic;
          MMUART1_RTS_MGPIO11B_H2F_B              : out   std_logic;
          MMUART1_RXD_MGPIO26B_H2F_A              : out   std_logic;
          MMUART1_RXD_MGPIO26B_H2F_B              : out   std_logic;
          MMUART1_SCK_MGPIO25B_H2F_A              : out   std_logic;
          MMUART1_SCK_MGPIO25B_H2F_B              : out   std_logic;
          MMUART1_TXD_MGPIO24B_H2F_A              : out   std_logic;
          MMUART1_TXD_MGPIO24B_H2F_B              : out   std_logic;
          MPLL_LOCK                               : out   std_logic;
          PER2_FABRIC_PADDR                       : out   std_logic_vector(15 downto 2);
          PER2_FABRIC_PENABLE                     : out   std_logic;
          PER2_FABRIC_PSEL                        : out   std_logic;
          PER2_FABRIC_PWDATA                      : out   std_logic_vector(31 downto 0);
          PER2_FABRIC_PWRITE                      : out   std_logic;
          RTC_MATCH                               : out   std_logic;
          SLEEPDEEP                               : out   std_logic;
          SLEEPHOLDACK                            : out   std_logic;
          SLEEPING                                : out   std_logic;
          SMBALERT_NO0                            : out   std_logic;
          SMBALERT_NO1                            : out   std_logic;
          SMBSUS_NO0                              : out   std_logic;
          SMBSUS_NO1                              : out   std_logic;
          SPI0_CLK_OUT                            : out   std_logic;
          SPI0_SDI_MGPIO5A_H2F_A                  : out   std_logic;
          SPI0_SDI_MGPIO5A_H2F_B                  : out   std_logic;
          SPI0_SDO_MGPIO6A_H2F_A                  : out   std_logic;
          SPI0_SDO_MGPIO6A_H2F_B                  : out   std_logic;
          SPI0_SS0_MGPIO7A_H2F_A                  : out   std_logic;
          SPI0_SS0_MGPIO7A_H2F_B                  : out   std_logic;
          SPI0_SS1_MGPIO8A_H2F_A                  : out   std_logic;
          SPI0_SS1_MGPIO8A_H2F_B                  : out   std_logic;
          SPI0_SS2_MGPIO9A_H2F_A                  : out   std_logic;
          SPI0_SS2_MGPIO9A_H2F_B                  : out   std_logic;
          SPI0_SS3_MGPIO10A_H2F_A                 : out   std_logic;
          SPI0_SS3_MGPIO10A_H2F_B                 : out   std_logic;
          SPI0_SS4_MGPIO19A_H2F_A                 : out   std_logic;
          SPI0_SS5_MGPIO20A_H2F_A                 : out   std_logic;
          SPI0_SS6_MGPIO21A_H2F_A                 : out   std_logic;
          SPI0_SS7_MGPIO22A_H2F_A                 : out   std_logic;
          SPI1_CLK_OUT                            : out   std_logic;
          SPI1_SDI_MGPIO11A_H2F_A                 : out   std_logic;
          SPI1_SDI_MGPIO11A_H2F_B                 : out   std_logic;
          SPI1_SDO_MGPIO12A_H2F_A                 : out   std_logic;
          SPI1_SDO_MGPIO12A_H2F_B                 : out   std_logic;
          SPI1_SS0_MGPIO13A_H2F_A                 : out   std_logic;
          SPI1_SS0_MGPIO13A_H2F_B                 : out   std_logic;
          SPI1_SS1_MGPIO14A_H2F_A                 : out   std_logic;
          SPI1_SS1_MGPIO14A_H2F_B                 : out   std_logic;
          SPI1_SS2_MGPIO15A_H2F_A                 : out   std_logic;
          SPI1_SS2_MGPIO15A_H2F_B                 : out   std_logic;
          SPI1_SS3_MGPIO16A_H2F_A                 : out   std_logic;
          SPI1_SS3_MGPIO16A_H2F_B                 : out   std_logic;
          SPI1_SS4_MGPIO17A_H2F_A                 : out   std_logic;
          SPI1_SS5_MGPIO18A_H2F_A                 : out   std_logic;
          SPI1_SS6_MGPIO23A_H2F_A                 : out   std_logic;
          SPI1_SS7_MGPIO24A_H2F_A                 : out   std_logic;
          TCGF                                    : out   std_logic_vector(9 downto 0);
          TRACECLK                                : out   std_logic;
          TRACEDATA                               : out   std_logic_vector(3 downto 0);
          TX_CLK                                  : out   std_logic;
          TX_ENF                                  : out   std_logic;
          TX_ERRF                                 : out   std_logic;
          TXCTL_EN_RIF                            : out   std_logic;
          TXD_RIF                                 : out   std_logic_vector(3 downto 0);
          TXDF                                    : out   std_logic_vector(7 downto 0);
          TXEV                                    : out   std_logic;
          WDOGTIMEOUT                             : out   std_logic;
          F_ARREADY_HREADYOUT1                    : out   std_logic;
          F_AWREADY_HREADYOUT0                    : out   std_logic;
          F_BID                                   : out   std_logic_vector(3 downto 0);
          F_BRESP_HRESP0                          : out   std_logic_vector(1 downto 0);
          F_BVALID                                : out   std_logic;
          F_RDATA_HRDATA01                        : out   std_logic_vector(63 downto 0);
          F_RID                                   : out   std_logic_vector(3 downto 0);
          F_RLAST                                 : out   std_logic;
          F_RRESP_HRESP1                          : out   std_logic_vector(1 downto 0);
          F_RVALID                                : out   std_logic;
          F_WREADY                                : out   std_logic;
          MDDR_FABRIC_PRDATA                      : out   std_logic_vector(15 downto 0);
          MDDR_FABRIC_PREADY                      : out   std_logic;
          MDDR_FABRIC_PSLVERR                     : out   std_logic;
          CAN_RXBUS_F2H_SCP                       : in    std_logic := 'U';
          CAN_TX_EBL_F2H_SCP                      : in    std_logic := 'U';
          CAN_TXBUS_F2H_SCP                       : in    std_logic := 'U';
          COLF                                    : in    std_logic := 'U';
          CRSF                                    : in    std_logic := 'U';
          F2_DMAREADY                             : in    std_logic_vector(1 downto 0) := (others => 'U');
          F2H_INTERRUPT                           : in    std_logic_vector(15 downto 0) := (others => 'U');
          F2HCALIB                                : in    std_logic := 'U';
          F_DMAREADY                              : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_FM0_ADDR                              : in    std_logic_vector(31 downto 0) := (others => 'U');
          F_FM0_ENABLE                            : in    std_logic := 'U';
          F_FM0_MASTLOCK                          : in    std_logic := 'U';
          F_FM0_READY                             : in    std_logic := 'U';
          F_FM0_SEL                               : in    std_logic := 'U';
          F_FM0_SIZE                              : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_FM0_TRANS1                            : in    std_logic := 'U';
          F_FM0_WDATA                             : in    std_logic_vector(31 downto 0) := (others => 'U');
          F_FM0_WRITE                             : in    std_logic := 'U';
          F_HM0_RDATA                             : in    std_logic_vector(31 downto 0) := (others => 'U');
          F_HM0_READY                             : in    std_logic := 'U';
          F_HM0_RESP                              : in    std_logic := 'U';
          FAB_AVALID                              : in    std_logic := 'U';
          FAB_HOSTDISCON                          : in    std_logic := 'U';
          FAB_IDDIG                               : in    std_logic := 'U';
          FAB_LINESTATE                           : in    std_logic_vector(1 downto 0) := (others => 'U');
          FAB_M3_RESET_N                          : in    std_logic := 'U';
          FAB_PLL_LOCK                            : in    std_logic := 'U';
          FAB_RXACTIVE                            : in    std_logic := 'U';
          FAB_RXERROR                             : in    std_logic := 'U';
          FAB_RXVALID                             : in    std_logic := 'U';
          FAB_RXVALIDH                            : in    std_logic := 'U';
          FAB_SESSEND                             : in    std_logic := 'U';
          FAB_TXREADY                             : in    std_logic := 'U';
          FAB_VBUSVALID                           : in    std_logic := 'U';
          FAB_VSTATUS                             : in    std_logic_vector(7 downto 0) := (others => 'U');
          FAB_XDATAIN                             : in    std_logic_vector(7 downto 0) := (others => 'U');
          GTX_CLKPF                               : in    std_logic := 'U';
          I2C0_BCLK                               : in    std_logic := 'U';
          I2C0_SCL_F2H_SCP                        : in    std_logic := 'U';
          I2C0_SDA_F2H_SCP                        : in    std_logic := 'U';
          I2C1_BCLK                               : in    std_logic := 'U';
          I2C1_SCL_F2H_SCP                        : in    std_logic := 'U';
          I2C1_SDA_F2H_SCP                        : in    std_logic := 'U';
          MDIF                                    : in    std_logic := 'U';
          MGPIO0A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO10A_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO11A_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO11B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO12A_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO13A_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO14A_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO15A_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO16A_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO17B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO18B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO19B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO1A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO20B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO21B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO22B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO24B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO25B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO26B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO27B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO28B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO29B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO2A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO30B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO31B_F2H_GPIN                       : in    std_logic := 'U';
          MGPIO3A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO4A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO5A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO6A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO7A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO8A_F2H_GPIN                        : in    std_logic := 'U';
          MGPIO9A_F2H_GPIN                        : in    std_logic := 'U';
          MMUART0_CTS_F2H_SCP                     : in    std_logic := 'U';
          MMUART0_DCD_F2H_SCP                     : in    std_logic := 'U';
          MMUART0_DSR_F2H_SCP                     : in    std_logic := 'U';
          MMUART0_DTR_F2H_SCP                     : in    std_logic := 'U';
          MMUART0_RI_F2H_SCP                      : in    std_logic := 'U';
          MMUART0_RTS_F2H_SCP                     : in    std_logic := 'U';
          MMUART0_RXD_F2H_SCP                     : in    std_logic := 'U';
          MMUART0_SCK_F2H_SCP                     : in    std_logic := 'U';
          MMUART0_TXD_F2H_SCP                     : in    std_logic := 'U';
          MMUART1_CTS_F2H_SCP                     : in    std_logic := 'U';
          MMUART1_DCD_F2H_SCP                     : in    std_logic := 'U';
          MMUART1_DSR_F2H_SCP                     : in    std_logic := 'U';
          MMUART1_RI_F2H_SCP                      : in    std_logic := 'U';
          MMUART1_RTS_F2H_SCP                     : in    std_logic := 'U';
          MMUART1_RXD_F2H_SCP                     : in    std_logic := 'U';
          MMUART1_SCK_F2H_SCP                     : in    std_logic := 'U';
          MMUART1_TXD_F2H_SCP                     : in    std_logic := 'U';
          PER2_FABRIC_PRDATA                      : in    std_logic_vector(31 downto 0) := (others => 'U');
          PER2_FABRIC_PREADY                      : in    std_logic := 'U';
          PER2_FABRIC_PSLVERR                     : in    std_logic := 'U';
          RCGF                                    : in    std_logic_vector(9 downto 0) := (others => 'U');
          RX_CLKPF                                : in    std_logic := 'U';
          RX_DVF                                  : in    std_logic := 'U';
          RX_ERRF                                 : in    std_logic := 'U';
          RX_EV                                   : in    std_logic := 'U';
          RXDF                                    : in    std_logic_vector(7 downto 0) := (others => 'U');
          SLEEPHOLDREQ                            : in    std_logic := 'U';
          SMBALERT_NI0                            : in    std_logic := 'U';
          SMBALERT_NI1                            : in    std_logic := 'U';
          SMBSUS_NI0                              : in    std_logic := 'U';
          SMBSUS_NI1                              : in    std_logic := 'U';
          SPI0_CLK_IN                             : in    std_logic := 'U';
          SPI0_SDI_F2H_SCP                        : in    std_logic := 'U';
          SPI0_SDO_F2H_SCP                        : in    std_logic := 'U';
          SPI0_SS0_F2H_SCP                        : in    std_logic := 'U';
          SPI0_SS1_F2H_SCP                        : in    std_logic := 'U';
          SPI0_SS2_F2H_SCP                        : in    std_logic := 'U';
          SPI0_SS3_F2H_SCP                        : in    std_logic := 'U';
          SPI1_CLK_IN                             : in    std_logic := 'U';
          SPI1_SDI_F2H_SCP                        : in    std_logic := 'U';
          SPI1_SDO_F2H_SCP                        : in    std_logic := 'U';
          SPI1_SS0_F2H_SCP                        : in    std_logic := 'U';
          SPI1_SS1_F2H_SCP                        : in    std_logic := 'U';
          SPI1_SS2_F2H_SCP                        : in    std_logic := 'U';
          SPI1_SS3_F2H_SCP                        : in    std_logic := 'U';
          TX_CLKPF                                : in    std_logic := 'U';
          USER_MSS_GPIO_RESET_N                   : in    std_logic := 'U';
          USER_MSS_RESET_N                        : in    std_logic := 'U';
          XCLK_FAB                                : in    std_logic := 'U';
          CLK_BASE                                : in    std_logic := 'U';
          CLK_MDDR_APB                            : in    std_logic := 'U';
          F_ARADDR_HADDR1                         : in    std_logic_vector(31 downto 0) := (others => 'U');
          F_ARBURST_HTRANS1                       : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_ARID_HSEL1                            : in    std_logic_vector(3 downto 0) := (others => 'U');
          F_ARLEN_HBURST1                         : in    std_logic_vector(3 downto 0) := (others => 'U');
          F_ARLOCK_HMASTLOCK1                     : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_ARSIZE_HSIZE1                         : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_ARVALID_HWRITE1                       : in    std_logic := 'U';
          F_AWADDR_HADDR0                         : in    std_logic_vector(31 downto 0) := (others => 'U');
          F_AWBURST_HTRANS0                       : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_AWID_HSEL0                            : in    std_logic_vector(3 downto 0) := (others => 'U');
          F_AWLEN_HBURST0                         : in    std_logic_vector(3 downto 0) := (others => 'U');
          F_AWLOCK_HMASTLOCK0                     : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_AWSIZE_HSIZE0                         : in    std_logic_vector(1 downto 0) := (others => 'U');
          F_AWVALID_HWRITE0                       : in    std_logic := 'U';
          F_BREADY                                : in    std_logic := 'U';
          F_RMW_AXI                               : in    std_logic := 'U';
          F_RREADY                                : in    std_logic := 'U';
          F_WDATA_HWDATA01                        : in    std_logic_vector(63 downto 0) := (others => 'U');
          F_WID_HREADY01                          : in    std_logic_vector(3 downto 0) := (others => 'U');
          F_WLAST                                 : in    std_logic := 'U';
          F_WSTRB                                 : in    std_logic_vector(7 downto 0) := (others => 'U');
          F_WVALID                                : in    std_logic := 'U';
          FPGA_MDDR_ARESET_N                      : in    std_logic := 'U';
          MDDR_FABRIC_PADDR                       : in    std_logic_vector(10 downto 2) := (others => 'U');
          MDDR_FABRIC_PENABLE                     : in    std_logic := 'U';
          MDDR_FABRIC_PSEL                        : in    std_logic := 'U';
          MDDR_FABRIC_PWDATA                      : in    std_logic_vector(15 downto 0) := (others => 'U');
          MDDR_FABRIC_PWRITE                      : in    std_logic := 'U';
          PRESET_N                                : in    std_logic := 'U';
          CAN_RXBUS_USBA_DATA1_MGPIO3A_IN         : in    std_logic := 'U';
          CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN        : in    std_logic := 'U';
          CAN_TXBUS_USBA_DATA0_MGPIO2A_IN         : in    std_logic := 'U';
          DM_IN                                   : in    std_logic_vector(2 downto 0) := (others => 'U');
          DRAM_DQ_IN                              : in    std_logic_vector(17 downto 0) := (others => 'U');
          DRAM_DQS_IN                             : in    std_logic_vector(2 downto 0) := (others => 'U');
          DRAM_FIFO_WE_IN                         : in    std_logic_vector(1 downto 0) := (others => 'U');
          I2C0_SCL_USBC_DATA1_MGPIO31B_IN         : in    std_logic := 'U';
          I2C0_SDA_USBC_DATA0_MGPIO30B_IN         : in    std_logic := 'U';
          I2C1_SCL_USBA_DATA4_MGPIO1A_IN          : in    std_logic := 'U';
          I2C1_SDA_USBA_DATA3_MGPIO0A_IN          : in    std_logic := 'U';
          MMUART0_CTS_USBC_DATA7_MGPIO19B_IN      : in    std_logic := 'U';
          MMUART0_DCD_MGPIO22B_IN                 : in    std_logic := 'U';
          MMUART0_DSR_MGPIO20B_IN                 : in    std_logic := 'U';
          MMUART0_DTR_USBC_DATA6_MGPIO18B_IN      : in    std_logic := 'U';
          MMUART0_RI_MGPIO21B_IN                  : in    std_logic := 'U';
          MMUART0_RTS_USBC_DATA5_MGPIO17B_IN      : in    std_logic := 'U';
          MMUART0_RXD_USBC_STP_MGPIO28B_IN        : in    std_logic := 'U';
          MMUART0_SCK_USBC_NXT_MGPIO29B_IN        : in    std_logic := 'U';
          MMUART0_TXD_USBC_DIR_MGPIO27B_IN        : in    std_logic := 'U';
          MMUART1_RXD_USBC_DATA3_MGPIO26B_IN      : in    std_logic := 'U';
          MMUART1_SCK_USBC_DATA4_MGPIO25B_IN      : in    std_logic := 'U';
          MMUART1_TXD_USBC_DATA2_MGPIO24B_IN      : in    std_logic := 'U';
          RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN     : in    std_logic := 'U';
          RGMII_MDC_RMII_MDC_IN                   : in    std_logic := 'U';
          RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN      : in    std_logic := 'U';
          RGMII_RX_CLK_IN                         : in    std_logic := 'U';
          RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN  : in    std_logic := 'U';
          RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN      : in    std_logic := 'U';
          RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN      : in    std_logic := 'U';
          RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN     : in    std_logic := 'U';
          RGMII_RXD3_USBB_DATA4_IN                : in    std_logic := 'U';
          RGMII_TX_CLK_IN                         : in    std_logic := 'U';
          RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN     : in    std_logic := 'U';
          RGMII_TXD0_RMII_TXD0_USBB_DIR_IN        : in    std_logic := 'U';
          RGMII_TXD1_RMII_TXD1_USBB_STP_IN        : in    std_logic := 'U';
          RGMII_TXD2_USBB_DATA5_IN                : in    std_logic := 'U';
          RGMII_TXD3_USBB_DATA6_IN                : in    std_logic := 'U';
          SPI0_SCK_USBA_XCLK_IN                   : in    std_logic := 'U';
          SPI0_SDI_USBA_DIR_MGPIO5A_IN            : in    std_logic := 'U';
          SPI0_SDO_USBA_STP_MGPIO6A_IN            : in    std_logic := 'U';
          SPI0_SS0_USBA_NXT_MGPIO7A_IN            : in    std_logic := 'U';
          SPI0_SS1_USBA_DATA5_MGPIO8A_IN          : in    std_logic := 'U';
          SPI0_SS2_USBA_DATA6_MGPIO9A_IN          : in    std_logic := 'U';
          SPI0_SS3_USBA_DATA7_MGPIO10A_IN         : in    std_logic := 'U';
          SPI1_SCK_IN                             : in    std_logic := 'U';
          SPI1_SDI_MGPIO11A_IN                    : in    std_logic := 'U';
          SPI1_SDO_MGPIO12A_IN                    : in    std_logic := 'U';
          SPI1_SS0_MGPIO13A_IN                    : in    std_logic := 'U';
          SPI1_SS1_MGPIO14A_IN                    : in    std_logic := 'U';
          SPI1_SS2_MGPIO15A_IN                    : in    std_logic := 'U';
          SPI1_SS3_MGPIO16A_IN                    : in    std_logic := 'U';
          SPI1_SS4_MGPIO17A_IN                    : in    std_logic := 'U';
          SPI1_SS5_MGPIO18A_IN                    : in    std_logic := 'U';
          SPI1_SS6_MGPIO23A_IN                    : in    std_logic := 'U';
          SPI1_SS7_MGPIO24A_IN                    : in    std_logic := 'U';
          USBC_XCLK_IN                            : in    std_logic := 'U';
          CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT        : out   std_logic;
          CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT       : out   std_logic;
          CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT        : out   std_logic;
          DRAM_ADDR                               : out   std_logic_vector(15 downto 0);
          DRAM_BA                                 : out   std_logic_vector(2 downto 0);
          DRAM_CASN                               : out   std_logic;
          DRAM_CKE                                : out   std_logic;
          DRAM_CLK                                : out   std_logic;
          DRAM_CSN                                : out   std_logic;
          DRAM_DM_RDQS_OUT                        : out   std_logic_vector(2 downto 0);
          DRAM_DQ_OUT                             : out   std_logic_vector(17 downto 0);
          DRAM_DQS_OUT                            : out   std_logic_vector(2 downto 0);
          DRAM_FIFO_WE_OUT                        : out   std_logic_vector(1 downto 0);
          DRAM_ODT                                : out   std_logic;
          DRAM_RASN                               : out   std_logic;
          DRAM_RSTN                               : out   std_logic;
          DRAM_WEN                                : out   std_logic;
          I2C0_SCL_USBC_DATA1_MGPIO31B_OUT        : out   std_logic;
          I2C0_SDA_USBC_DATA0_MGPIO30B_OUT        : out   std_logic;
          I2C1_SCL_USBA_DATA4_MGPIO1A_OUT         : out   std_logic;
          I2C1_SDA_USBA_DATA3_MGPIO0A_OUT         : out   std_logic;
          MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT     : out   std_logic;
          MMUART0_DCD_MGPIO22B_OUT                : out   std_logic;
          MMUART0_DSR_MGPIO20B_OUT                : out   std_logic;
          MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT     : out   std_logic;
          MMUART0_RI_MGPIO21B_OUT                 : out   std_logic;
          MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT     : out   std_logic;
          MMUART0_RXD_USBC_STP_MGPIO28B_OUT       : out   std_logic;
          MMUART0_SCK_USBC_NXT_MGPIO29B_OUT       : out   std_logic;
          MMUART0_TXD_USBC_DIR_MGPIO27B_OUT       : out   std_logic;
          MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT     : out   std_logic;
          MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT     : out   std_logic;
          MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT     : out   std_logic;
          RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT    : out   std_logic;
          RGMII_MDC_RMII_MDC_OUT                  : out   std_logic;
          RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT     : out   std_logic;
          RGMII_RX_CLK_OUT                        : out   std_logic;
          RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT : out   std_logic;
          RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT     : out   std_logic;
          RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT     : out   std_logic;
          RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT    : out   std_logic;
          RGMII_RXD3_USBB_DATA4_OUT               : out   std_logic;
          RGMII_TX_CLK_OUT                        : out   std_logic;
          RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT    : out   std_logic;
          RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT       : out   std_logic;
          RGMII_TXD1_RMII_TXD1_USBB_STP_OUT       : out   std_logic;
          RGMII_TXD2_USBB_DATA5_OUT               : out   std_logic;
          RGMII_TXD3_USBB_DATA6_OUT               : out   std_logic;
          SPI0_SCK_USBA_XCLK_OUT                  : out   std_logic;
          SPI0_SDI_USBA_DIR_MGPIO5A_OUT           : out   std_logic;
          SPI0_SDO_USBA_STP_MGPIO6A_OUT           : out   std_logic;
          SPI0_SS0_USBA_NXT_MGPIO7A_OUT           : out   std_logic;
          SPI0_SS1_USBA_DATA5_MGPIO8A_OUT         : out   std_logic;
          SPI0_SS2_USBA_DATA6_MGPIO9A_OUT         : out   std_logic;
          SPI0_SS3_USBA_DATA7_MGPIO10A_OUT        : out   std_logic;
          SPI1_SCK_OUT                            : out   std_logic;
          SPI1_SDI_MGPIO11A_OUT                   : out   std_logic;
          SPI1_SDO_MGPIO12A_OUT                   : out   std_logic;
          SPI1_SS0_MGPIO13A_OUT                   : out   std_logic;
          SPI1_SS1_MGPIO14A_OUT                   : out   std_logic;
          SPI1_SS2_MGPIO15A_OUT                   : out   std_logic;
          SPI1_SS3_MGPIO16A_OUT                   : out   std_logic;
          SPI1_SS4_MGPIO17A_OUT                   : out   std_logic;
          SPI1_SS5_MGPIO18A_OUT                   : out   std_logic;
          SPI1_SS6_MGPIO23A_OUT                   : out   std_logic;
          SPI1_SS7_MGPIO24A_OUT                   : out   std_logic;
          USBC_XCLK_OUT                           : out   std_logic;
          CAN_RXBUS_USBA_DATA1_MGPIO3A_OE         : out   std_logic;
          CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE        : out   std_logic;
          CAN_TXBUS_USBA_DATA0_MGPIO2A_OE         : out   std_logic;
          DM_OE                                   : out   std_logic_vector(2 downto 0);
          DRAM_DQ_OE                              : out   std_logic_vector(17 downto 0);
          DRAM_DQS_OE                             : out   std_logic_vector(2 downto 0);
          I2C0_SCL_USBC_DATA1_MGPIO31B_OE         : out   std_logic;
          I2C0_SDA_USBC_DATA0_MGPIO30B_OE         : out   std_logic;
          I2C1_SCL_USBA_DATA4_MGPIO1A_OE          : out   std_logic;
          I2C1_SDA_USBA_DATA3_MGPIO0A_OE          : out   std_logic;
          MMUART0_CTS_USBC_DATA7_MGPIO19B_OE      : out   std_logic;
          MMUART0_DCD_MGPIO22B_OE                 : out   std_logic;
          MMUART0_DSR_MGPIO20B_OE                 : out   std_logic;
          MMUART0_DTR_USBC_DATA6_MGPIO18B_OE      : out   std_logic;
          MMUART0_RI_MGPIO21B_OE                  : out   std_logic;
          MMUART0_RTS_USBC_DATA5_MGPIO17B_OE      : out   std_logic;
          MMUART0_RXD_USBC_STP_MGPIO28B_OE        : out   std_logic;
          MMUART0_SCK_USBC_NXT_MGPIO29B_OE        : out   std_logic;
          MMUART0_TXD_USBC_DIR_MGPIO27B_OE        : out   std_logic;
          MMUART1_RXD_USBC_DATA3_MGPIO26B_OE      : out   std_logic;
          MMUART1_SCK_USBC_DATA4_MGPIO25B_OE      : out   std_logic;
          MMUART1_TXD_USBC_DATA2_MGPIO24B_OE      : out   std_logic;
          RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE     : out   std_logic;
          RGMII_MDC_RMII_MDC_OE                   : out   std_logic;
          RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE      : out   std_logic;
          RGMII_RX_CLK_OE                         : out   std_logic;
          RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE  : out   std_logic;
          RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE      : out   std_logic;
          RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE      : out   std_logic;
          RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE     : out   std_logic;
          RGMII_RXD3_USBB_DATA4_OE                : out   std_logic;
          RGMII_TX_CLK_OE                         : out   std_logic;
          RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE     : out   std_logic;
          RGMII_TXD0_RMII_TXD0_USBB_DIR_OE        : out   std_logic;
          RGMII_TXD1_RMII_TXD1_USBB_STP_OE        : out   std_logic;
          RGMII_TXD2_USBB_DATA5_OE                : out   std_logic;
          RGMII_TXD3_USBB_DATA6_OE                : out   std_logic;
          SPI0_SCK_USBA_XCLK_OE                   : out   std_logic;
          SPI0_SDI_USBA_DIR_MGPIO5A_OE            : out   std_logic;
          SPI0_SDO_USBA_STP_MGPIO6A_OE            : out   std_logic;
          SPI0_SS0_USBA_NXT_MGPIO7A_OE            : out   std_logic;
          SPI0_SS1_USBA_DATA5_MGPIO8A_OE          : out   std_logic;
          SPI0_SS2_USBA_DATA6_MGPIO9A_OE          : out   std_logic;
          SPI0_SS3_USBA_DATA7_MGPIO10A_OE         : out   std_logic;
          SPI1_SCK_OE                             : out   std_logic;
          SPI1_SDI_MGPIO11A_OE                    : out   std_logic;
          SPI1_SDO_MGPIO12A_OE                    : out   std_logic;
          SPI1_SS0_MGPIO13A_OE                    : out   std_logic;
          SPI1_SS1_MGPIO14A_OE                    : out   std_logic;
          SPI1_SS2_MGPIO15A_OE                    : out   std_logic;
          SPI1_SS3_MGPIO16A_OE                    : out   std_logic;
          SPI1_SS4_MGPIO17A_OE                    : out   std_logic;
          SPI1_SS5_MGPIO18A_OE                    : out   std_logic;
          SPI1_SS6_MGPIO23A_OE                    : out   std_logic;
          SPI1_SS7_MGPIO24A_OE                    : out   std_logic;
          USBC_XCLK_OE                            : out   std_logic
        );
  end component;

    signal EDAC_ERROR : std_logic_vector(7 downto 0);
    signal F_FM0_RDATA : std_logic_vector(31 downto 0);
    signal FIC_0_APB_M_PADDR : std_logic_vector(31 downto 16);
    signal F_HM0_SIZE : std_logic_vector(1 downto 0);
    signal FIC_0_APB_M_PWDATA : std_logic_vector(31 downto 18);
    signal FAB_OPMODE : std_logic_vector(1 downto 0);
    signal FAB_VCONTROL : std_logic_vector(3 downto 0);
    signal FAB_XCVRSEL : std_logic_vector(1 downto 0);
    signal FAB_XDATAOUT : std_logic_vector(7 downto 0);
    signal FIC32_0_MASTER : std_logic_vector(1 downto 0);
    signal FIC32_1_MASTER : std_logic_vector(1 downto 0);
    signal H2F_INTERRUPT : std_logic_vector(15 downto 0);
    signal FIC_2_APB_M_PADDR : std_logic_vector(15 downto 2);
    signal FIC_2_APB_M_PWDATA : std_logic_vector(31 downto 0);
    signal TCGF : std_logic_vector(9 downto 0);
    signal TRACEDATA : std_logic_vector(3 downto 0);
    signal TXD_RIF : std_logic_vector(3 downto 0);
    signal TXDF : std_logic_vector(7 downto 0);
    signal F_BID : std_logic_vector(3 downto 0);
    signal F_BRESP_HRESP0 : std_logic_vector(1 downto 0);
    signal F_RDATA_HRDATA01 : std_logic_vector(63 downto 0);
    signal F_RID : std_logic_vector(3 downto 0);
    signal F_RRESP_HRESP1 : std_logic_vector(1 downto 0);
    signal MDDR_FABRIC_PRDATA : std_logic_vector(15 downto 0);
    signal DRAM_ADDR : std_logic_vector(15 downto 0);
    signal DRAM_BA : std_logic_vector(2 downto 0);
    signal DRAM_DM_RDQS_OUT : std_logic_vector(2 downto 0);
    signal DRAM_DQ_OUT : std_logic_vector(17 downto 0);
    signal DRAM_DQS_OUT : std_logic_vector(2 downto 0);
    signal DRAM_FIFO_WE_OUT : std_logic_vector(1 downto 0);
    signal DM_OE : std_logic_vector(2 downto 0);
    signal DRAM_DQ_OE : std_logic_vector(17 downto 0);
    signal DRAM_DQS_OE : std_logic_vector(2 downto 0);
    signal USB_ULPI_XCLK_PAD_Y, 
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OUT, 
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OE, 
        USB_ULPI_NXT_PAD_Y, USB_ULPI_DIR_PAD_Y, 
        USB_ULPI_DATA_7_PAD_Y, 
        MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT, 
        MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE, 
        USB_ULPI_DATA_6_PAD_Y, 
        MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OUT, 
        MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OE, 
        USB_ULPI_DATA_5_PAD_Y, 
        MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OUT, 
        MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OE, 
        USB_ULPI_DATA_4_PAD_Y, 
        MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OUT, 
        MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OE, 
        USB_ULPI_DATA_3_PAD_Y, 
        MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT, 
        MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE, 
        USB_ULPI_DATA_2_PAD_Y, 
        MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT, 
        MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE, 
        USB_ULPI_DATA_1_PAD_Y, 
        MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT, 
        MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE, 
        USB_ULPI_DATA_0_PAD_Y, 
        MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT, 
        MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE, m8_e_1, 
        G_15_1_0, G_15_sx, CAN_RXBUS_MGPIO3A_H2F_A, 
        CAN_RXBUS_MGPIO3A_H2F_B, CAN_TX_EBL_MGPIO4A_H2F_A, 
        CAN_TX_EBL_MGPIO4A_H2F_B, CAN_TXBUS_MGPIO2A_H2F_A, 
        CAN_TXBUS_MGPIO2A_H2F_B, FIC_2_APB_M_PCLK, COMMS_INT, 
        FIC_2_APB_M_PRESET_N, F_FM0_READYOUT, F_FM0_RESP, 
        F_HM0_TRANS1, FAB_CHRGVBUS, FAB_DISCHRGVBUS, 
        FAB_DMPULLDOWN, FAB_DPPULLDOWN, FAB_DRVVBUS, FAB_IDPULLUP, 
        FAB_SUSPENDM, FAB_TERMSEL, FAB_TXVALID, FAB_VCONTROLLOADM, 
        FACC_GLMUX_SEL, MSS_RESET_N_M2F, GTX_CLK, H2F_NMI, 
        H2FCALIB, I2C0_SCL_MGPIO31B_H2F_A, 
        I2C0_SCL_MGPIO31B_H2F_B, I2C0_SDA_MGPIO30B_H2F_A, 
        I2C0_SDA_MGPIO30B_H2F_B, I2C1_SCL_MGPIO1A_H2F_A, 
        I2C1_SCL_MGPIO1A_H2F_B, I2C1_SDA_MGPIO0A_H2F_A, MDCF, 
        MDOENF, MDOF, MMUART0_CTS_MGPIO19B_H2F_A, 
        MMUART0_CTS_MGPIO19B_H2F_B, MMUART0_DCD_MGPIO22B_H2F_A, 
        MMUART0_DCD_MGPIO22B_H2F_B, MMUART0_DSR_MGPIO20B_H2F_A, 
        MMUART0_DSR_MGPIO20B_H2F_B, MMUART0_DTR_MGPIO18B_H2F_A, 
        MMUART0_DTR_MGPIO18B_H2F_B, MMUART0_RI_MGPIO21B_H2F_A, 
        MMUART0_RI_MGPIO21B_H2F_B, MMUART0_RTS_MGPIO17B_H2F_A, 
        MMUART0_RTS_MGPIO17B_H2F_B, MMUART0_RXD_MGPIO28B_H2F_A, 
        MMUART0_RXD_MGPIO28B_H2F_B, MMUART0_SCK_MGPIO29B_H2F_A, 
        MMUART0_SCK_MGPIO29B_H2F_B, MMUART0_TXD_MGPIO27B_H2F_A, 
        MMUART0_TXD_MGPIO27B_H2F_B, MMUART1_DTR_MGPIO12B_H2F_A, 
        MMUART1_RTS_MGPIO11B_H2F_A, MMUART1_RTS_MGPIO11B_H2F_B, 
        MMUART1_RXD_MGPIO26B_H2F_A, MMUART1_RXD_MGPIO26B_H2F_B, 
        MMUART1_SCK_MGPIO25B_H2F_A, MMUART1_SCK_MGPIO25B_H2F_B, 
        MMUART1_TXD_MGPIO24B_H2F_A, MMUART1_TXD_MGPIO24B_H2F_B, 
        MPLL_LOCK, FIC_2_APB_M_PENABLE, FIC_2_APB_M_PSEL, 
        FIC_2_APB_M_PWRITE, RTC_MATCH, SLEEPDEEP, SLEEPHOLDACK, 
        SLEEPING, SMBALERT_NO0, SMBALERT_NO1, SMBSUS_NO0, 
        SMBSUS_NO1, SPI0_CLK_OUT, SPI0_SDI_MGPIO5A_H2F_A, 
        SPI0_SDI_MGPIO5A_H2F_B, SPI0_SDO_MGPIO6A_H2F_A, 
        SPI0_SDO_MGPIO6A_H2F_B, SPI0_SS0_MGPIO7A_H2F_A, 
        SPI0_SS0_MGPIO7A_H2F_B, SPI0_SS1_MGPIO8A_H2F_A, 
        SPI0_SS1_MGPIO8A_H2F_B, SPI0_SS2_MGPIO9A_H2F_A, 
        SPI0_SS2_MGPIO9A_H2F_B, SPI0_SS3_MGPIO10A_H2F_A, 
        SPI0_SS3_MGPIO10A_H2F_B, SPI0_SS4_MGPIO19A_H2F_A, 
        SPI0_SS5_MGPIO20A_H2F_A, SPI0_SS6_MGPIO21A_H2F_A, 
        SPI0_SS7_MGPIO22A_H2F_A, SPI1_CLK_OUT, 
        SPI1_SDI_MGPIO11A_H2F_A, SPI1_SDI_MGPIO11A_H2F_B, 
        SPI1_SDO_MGPIO12A_H2F_A, SPI1_SDO_MGPIO12A_H2F_B, 
        SPI1_SS0_MGPIO13A_H2F_A, SPI1_SS0_MGPIO13A_H2F_B, 
        SPI1_SS1_MGPIO14A_H2F_A, SPI1_SS1_MGPIO14A_H2F_B, 
        SPI1_SS2_MGPIO15A_H2F_A, SPI1_SS2_MGPIO15A_H2F_B, 
        SPI1_SS3_MGPIO16A_H2F_A, SPI1_SS3_MGPIO16A_H2F_B, 
        SPI1_SS4_MGPIO17A_H2F_A, SPI1_SS5_MGPIO18A_H2F_A, 
        SPI1_SS6_MGPIO23A_H2F_A, SPI1_SS7_MGPIO24A_H2F_A, 
        TRACECLK, TX_CLK, TX_ENF, TX_ERRF, TXCTL_EN_RIF, TXEV, 
        WDOGTIMEOUT, F_ARREADY_HREADYOUT1, F_AWREADY_HREADYOUT0, 
        F_BVALID, F_RLAST, F_RVALID, F_WREADY, MDDR_FABRIC_PREADY, 
        MDDR_FABRIC_PSLVERR, \VCC\, \GND\, 
        CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT, 
        CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT, 
        CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT, DRAM_CASN, DRAM_CKE, 
        DRAM_CLK, DRAM_CSN, DRAM_ODT, DRAM_RASN, DRAM_RSTN, 
        DRAM_WEN, I2C0_SCL_USBC_DATA1_MGPIO31B_OUT, 
        I2C0_SDA_USBC_DATA0_MGPIO30B_OUT, 
        I2C1_SCL_USBA_DATA4_MGPIO1A_OUT, 
        I2C1_SDA_USBA_DATA3_MGPIO0A_OUT, 
        MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT, 
        MMUART0_DCD_MGPIO22B_OUT, MMUART0_DSR_MGPIO20B_OUT, 
        MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT, 
        MMUART0_RI_MGPIO21B_OUT, 
        MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT, 
        MMUART0_RXD_USBC_STP_MGPIO28B_OUT, 
        MMUART0_SCK_USBC_NXT_MGPIO29B_OUT, 
        MMUART0_TXD_USBC_DIR_MGPIO27B_OUT, 
        MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT, 
        MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT, 
        MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT, 
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT, 
        RGMII_MDC_RMII_MDC_OUT, RGMII_RX_CLK_OUT, 
        RGMII_TX_CLK_OUT, RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT, 
        RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT, SPI0_SCK_USBA_XCLK_OUT, 
        SPI0_SDI_USBA_DIR_MGPIO5A_OUT, 
        SPI0_SDO_USBA_STP_MGPIO6A_OUT, 
        SPI0_SS0_USBA_NXT_MGPIO7A_OUT, 
        SPI0_SS1_USBA_DATA5_MGPIO8A_OUT, 
        SPI0_SS2_USBA_DATA6_MGPIO9A_OUT, 
        SPI0_SS3_USBA_DATA7_MGPIO10A_OUT, SPI1_SCK_OUT, 
        SPI1_SDI_MGPIO11A_OUT, SPI1_SDO_MGPIO12A_OUT, 
        SPI1_SS0_MGPIO13A_OUT, SPI1_SS1_MGPIO14A_OUT, 
        SPI1_SS2_MGPIO15A_OUT, SPI1_SS3_MGPIO16A_OUT, 
        SPI1_SS4_MGPIO17A_OUT, SPI1_SS5_MGPIO18A_OUT, 
        SPI1_SS6_MGPIO23A_OUT, SPI1_SS7_MGPIO24A_OUT, 
        USBC_XCLK_OUT, CAN_RXBUS_USBA_DATA1_MGPIO3A_OE, 
        CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE, 
        CAN_TXBUS_USBA_DATA0_MGPIO2A_OE, 
        I2C0_SCL_USBC_DATA1_MGPIO31B_OE, 
        I2C0_SDA_USBC_DATA0_MGPIO30B_OE, 
        I2C1_SCL_USBA_DATA4_MGPIO1A_OE, 
        I2C1_SDA_USBA_DATA3_MGPIO0A_OE, 
        MMUART0_CTS_USBC_DATA7_MGPIO19B_OE, 
        MMUART0_DCD_MGPIO22B_OE, MMUART0_DSR_MGPIO20B_OE, 
        MMUART0_DTR_USBC_DATA6_MGPIO18B_OE, 
        MMUART0_RI_MGPIO21B_OE, 
        MMUART0_RTS_USBC_DATA5_MGPIO17B_OE, 
        MMUART0_RXD_USBC_STP_MGPIO28B_OE, 
        MMUART0_SCK_USBC_NXT_MGPIO29B_OE, 
        MMUART0_TXD_USBC_DIR_MGPIO27B_OE, 
        MMUART1_RXD_USBC_DATA3_MGPIO26B_OE, 
        MMUART1_SCK_USBC_DATA4_MGPIO25B_OE, 
        MMUART1_TXD_USBC_DATA2_MGPIO24B_OE, 
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE, 
        RGMII_MDC_RMII_MDC_OE, RGMII_RX_CLK_OE, RGMII_TX_CLK_OE, 
        RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE, 
        RGMII_TXD0_RMII_TXD0_USBB_DIR_OE, SPI0_SCK_USBA_XCLK_OE, 
        SPI0_SDI_USBA_DIR_MGPIO5A_OE, 
        SPI0_SDO_USBA_STP_MGPIO6A_OE, 
        SPI0_SS0_USBA_NXT_MGPIO7A_OE, 
        SPI0_SS1_USBA_DATA5_MGPIO8A_OE, 
        SPI0_SS2_USBA_DATA6_MGPIO9A_OE, 
        SPI0_SS3_USBA_DATA7_MGPIO10A_OE, SPI1_SCK_OE, 
        SPI1_SDI_MGPIO11A_OE, SPI1_SDO_MGPIO12A_OE, 
        SPI1_SS0_MGPIO13A_OE, SPI1_SS1_MGPIO14A_OE, 
        SPI1_SS2_MGPIO15A_OE, SPI1_SS3_MGPIO16A_OE, 
        SPI1_SS4_MGPIO17A_OE, SPI1_SS5_MGPIO18A_OE, 
        SPI1_SS6_MGPIO23A_OE, SPI1_SS7_MGPIO24A_OE, USBC_XCLK_OE
         : std_logic;

begin 


    GND_Z : GND
      port map(Y => \GND\);
    
    USB_ULPI_DATA_5_PAD : BIBUF
      generic map(IOSTD => "")

      port map(PAD => USB_ULPI_DATA(5), D => 
        MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OUT, E => 
        MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OE, Y => 
        USB_ULPI_DATA_5_PAD_Y);
    
    VCC_Z : VCC
      port map(Y => \VCC\);
    
    USB_ULPI_DIR_PAD : INBUF
      generic map(IOSTD => "")

      port map(PAD => USB_ULPI_DIR, Y => USB_ULPI_DIR_PAD_Y);
    
    USB_ULPI_DATA_2_PAD : BIBUF
      generic map(IOSTD => "")

      port map(PAD => USB_ULPI_DATA(2), D => 
        MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT, E
         => MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE, 
        Y => USB_ULPI_DATA_2_PAD_Y);
    
    USB_ULPI_DATA_0_PAD : BIBUF
      generic map(IOSTD => "")

      port map(PAD => USB_ULPI_DATA(0), D => 
        MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT, E => 
        MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE, Y => 
        USB_ULPI_DATA_0_PAD_Y);
    
    USB_ULPI_NXT_PAD : INBUF
      generic map(IOSTD => "")

      port map(PAD => USB_ULPI_NXT, Y => USB_ULPI_NXT_PAD_Y);
    
    USB_ULPI_DATA_1_PAD : BIBUF
      generic map(IOSTD => "")

      port map(PAD => USB_ULPI_DATA(1), D => 
        MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT, E => 
        MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE, Y => 
        USB_ULPI_DATA_1_PAD_Y);
    
    USB_ULPI_XCLK_PAD : INBUF
      generic map(IOSTD => "")

      port map(PAD => USB_ULPI_XCLK, Y => USB_ULPI_XCLK_PAD_Y);
    
    USB_ULPI_DATA_4_PAD : BIBUF
      generic map(IOSTD => "")

      port map(PAD => USB_ULPI_DATA(4), D => 
        MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OUT, E => 
        MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OE, Y => 
        USB_ULPI_DATA_4_PAD_Y);
    
    USB_ULPI_DATA_7_PAD : BIBUF
      generic map(IOSTD => "")

      port map(PAD => USB_ULPI_DATA(7), D => 
        MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT, E => 
        MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE, Y => 
        USB_ULPI_DATA_7_PAD_Y);
    
    MSS_ADLIB_INST_RNI01T65 : CFG4
      generic map(INIT => x"0020")

      port map(A => m8_e_1, B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(10), C => G_15_1_0, D => 
        G_15_sx, Y => N_745);
    
    USB_ULPI_STP_PAD : TRIBUFF
      generic map(IOSTD => "")

      port map(D => 
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OUT, E => 
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OE, PAD => 
        USB_ULPI_STP);
    
    MSS_ADLIB_INST_RNI0BKN1_0 : CFG4
      generic map(INIT => x"FFFD")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(11), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(7), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(0), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(1), Y => G_15_sx);
    
    USB_ULPI_DATA_3_PAD : BIBUF
      generic map(IOSTD => "")

      port map(PAD => USB_ULPI_DATA(3), D => 
        MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT, E
         => MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE, Y
         => USB_ULPI_DATA_3_PAD_Y);
    
    MSS_ADLIB_INST_RNI0BKN1 : CFG4
      generic map(INIT => x"0002")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(6), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(8), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(9), Y => G_15_1_0);
    
    MSS_ADLIB_INST_RNI88N91 : CFG3
      generic map(INIT => x"10")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(4), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => m8_e_1);
    
    USB_ULPI_DATA_6_PAD : BIBUF
      generic map(IOSTD => "")

      port map(PAD => USB_ULPI_DATA(6), D => 
        MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OUT, E => 
        MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OE, Y => 
        USB_ULPI_DATA_6_PAD_Y);
    
    MSS_ADLIB_INST : MSS_010

              generic map(INIT => "00" & x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000120481204812048120D8120D8120E00000000F000000000000000000000000000000007FFFFFFFB000001007C33C000000006092C0104003FFFFE4000000000001100000000F0F01C00000182CFFC010842108421000001FE34001FF8000000400000000020091007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
         ACT_UBITS => x"FFFFFFFFFFFFFF",
         MEMORYFILE => "ENVM_init.mem",
         RTC_MAIN_XTL_FREQ => 0.000000, RTC_MAIN_XTL_MODE => "",
         DDR_CLK_FREQ => 0.000000)

      port map(CAN_RXBUS_MGPIO3A_H2F_A => CAN_RXBUS_MGPIO3A_H2F_A, 
        CAN_RXBUS_MGPIO3A_H2F_B => CAN_RXBUS_MGPIO3A_H2F_B, 
        CAN_TX_EBL_MGPIO4A_H2F_A => CAN_TX_EBL_MGPIO4A_H2F_A, 
        CAN_TX_EBL_MGPIO4A_H2F_B => CAN_TX_EBL_MGPIO4A_H2F_B, 
        CAN_TXBUS_MGPIO2A_H2F_A => CAN_TXBUS_MGPIO2A_H2F_A, 
        CAN_TXBUS_MGPIO2A_H2F_B => CAN_TXBUS_MGPIO2A_H2F_B, 
        CLK_CONFIG_APB => FIC_2_APB_M_PCLK, COMMS_INT => 
        COMMS_INT, CONFIG_PRESET_N => FIC_2_APB_M_PRESET_N, 
        EDAC_ERROR(7) => EDAC_ERROR(7), EDAC_ERROR(6) => 
        EDAC_ERROR(6), EDAC_ERROR(5) => EDAC_ERROR(5), 
        EDAC_ERROR(4) => EDAC_ERROR(4), EDAC_ERROR(3) => 
        EDAC_ERROR(3), EDAC_ERROR(2) => EDAC_ERROR(2), 
        EDAC_ERROR(1) => EDAC_ERROR(1), EDAC_ERROR(0) => 
        EDAC_ERROR(0), F_FM0_RDATA(31) => F_FM0_RDATA(31), 
        F_FM0_RDATA(30) => F_FM0_RDATA(30), F_FM0_RDATA(29) => 
        F_FM0_RDATA(29), F_FM0_RDATA(28) => F_FM0_RDATA(28), 
        F_FM0_RDATA(27) => F_FM0_RDATA(27), F_FM0_RDATA(26) => 
        F_FM0_RDATA(26), F_FM0_RDATA(25) => F_FM0_RDATA(25), 
        F_FM0_RDATA(24) => F_FM0_RDATA(24), F_FM0_RDATA(23) => 
        F_FM0_RDATA(23), F_FM0_RDATA(22) => F_FM0_RDATA(22), 
        F_FM0_RDATA(21) => F_FM0_RDATA(21), F_FM0_RDATA(20) => 
        F_FM0_RDATA(20), F_FM0_RDATA(19) => F_FM0_RDATA(19), 
        F_FM0_RDATA(18) => F_FM0_RDATA(18), F_FM0_RDATA(17) => 
        F_FM0_RDATA(17), F_FM0_RDATA(16) => F_FM0_RDATA(16), 
        F_FM0_RDATA(15) => F_FM0_RDATA(15), F_FM0_RDATA(14) => 
        F_FM0_RDATA(14), F_FM0_RDATA(13) => F_FM0_RDATA(13), 
        F_FM0_RDATA(12) => F_FM0_RDATA(12), F_FM0_RDATA(11) => 
        F_FM0_RDATA(11), F_FM0_RDATA(10) => F_FM0_RDATA(10), 
        F_FM0_RDATA(9) => F_FM0_RDATA(9), F_FM0_RDATA(8) => 
        F_FM0_RDATA(8), F_FM0_RDATA(7) => F_FM0_RDATA(7), 
        F_FM0_RDATA(6) => F_FM0_RDATA(6), F_FM0_RDATA(5) => 
        F_FM0_RDATA(5), F_FM0_RDATA(4) => F_FM0_RDATA(4), 
        F_FM0_RDATA(3) => F_FM0_RDATA(3), F_FM0_RDATA(2) => 
        F_FM0_RDATA(2), F_FM0_RDATA(1) => F_FM0_RDATA(1), 
        F_FM0_RDATA(0) => F_FM0_RDATA(0), F_FM0_READYOUT => 
        F_FM0_READYOUT, F_FM0_RESP => F_FM0_RESP, F_HM0_ADDR(31)
         => FIC_0_APB_M_PADDR(31), F_HM0_ADDR(30) => 
        FIC_0_APB_M_PADDR(30), F_HM0_ADDR(29) => 
        FIC_0_APB_M_PADDR(29), F_HM0_ADDR(28) => 
        FIC_0_APB_M_PADDR(28), F_HM0_ADDR(27) => 
        FIC_0_APB_M_PADDR(27), F_HM0_ADDR(26) => 
        FIC_0_APB_M_PADDR(26), F_HM0_ADDR(25) => 
        FIC_0_APB_M_PADDR(25), F_HM0_ADDR(24) => 
        FIC_0_APB_M_PADDR(24), F_HM0_ADDR(23) => 
        FIC_0_APB_M_PADDR(23), F_HM0_ADDR(22) => 
        FIC_0_APB_M_PADDR(22), F_HM0_ADDR(21) => 
        FIC_0_APB_M_PADDR(21), F_HM0_ADDR(20) => 
        FIC_0_APB_M_PADDR(20), F_HM0_ADDR(19) => 
        FIC_0_APB_M_PADDR(19), F_HM0_ADDR(18) => 
        FIC_0_APB_M_PADDR(18), F_HM0_ADDR(17) => 
        FIC_0_APB_M_PADDR(17), F_HM0_ADDR(16) => 
        FIC_0_APB_M_PADDR(16), F_HM0_ADDR(15) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(15), 
        F_HM0_ADDR(14) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(14), 
        F_HM0_ADDR(13) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(13), 
        F_HM0_ADDR(12) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), 
        F_HM0_ADDR(11) => MC_System_0_AMBA_SLAVE_0_PADDR(11), 
        F_HM0_ADDR(10) => MC_System_0_AMBA_SLAVE_0_PADDR(10), 
        F_HM0_ADDR(9) => MC_System_0_AMBA_SLAVE_0_PADDR(9), 
        F_HM0_ADDR(8) => MC_System_0_AMBA_SLAVE_0_PADDR(8), 
        F_HM0_ADDR(7) => MC_System_0_AMBA_SLAVE_0_PADDR(7), 
        F_HM0_ADDR(6) => MC_System_0_AMBA_SLAVE_0_PADDR(6), 
        F_HM0_ADDR(5) => MC_System_0_AMBA_SLAVE_0_PADDR(5), 
        F_HM0_ADDR(4) => MC_System_0_AMBA_SLAVE_0_PADDR(4), 
        F_HM0_ADDR(3) => MC_System_0_AMBA_SLAVE_0_PADDR(3), 
        F_HM0_ADDR(2) => MC_System_0_AMBA_SLAVE_0_PADDR(2), 
        F_HM0_ADDR(1) => MC_System_0_AMBA_SLAVE_0_PADDR(1), 
        F_HM0_ADDR(0) => MC_System_0_AMBA_SLAVE_0_PADDR(0), 
        F_HM0_ENABLE => MC_System_0_AMBA_SLAVE_0_PENABLE, 
        F_HM0_SEL => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx, 
        F_HM0_SIZE(1) => F_HM0_SIZE(1), F_HM0_SIZE(0) => 
        F_HM0_SIZE(0), F_HM0_TRANS1 => F_HM0_TRANS1, 
        F_HM0_WDATA(31) => FIC_0_APB_M_PWDATA(31), 
        F_HM0_WDATA(30) => FIC_0_APB_M_PWDATA(30), 
        F_HM0_WDATA(29) => FIC_0_APB_M_PWDATA(29), 
        F_HM0_WDATA(28) => FIC_0_APB_M_PWDATA(28), 
        F_HM0_WDATA(27) => FIC_0_APB_M_PWDATA(27), 
        F_HM0_WDATA(26) => FIC_0_APB_M_PWDATA(26), 
        F_HM0_WDATA(25) => FIC_0_APB_M_PWDATA(25), 
        F_HM0_WDATA(24) => FIC_0_APB_M_PWDATA(24), 
        F_HM0_WDATA(23) => FIC_0_APB_M_PWDATA(23), 
        F_HM0_WDATA(22) => FIC_0_APB_M_PWDATA(22), 
        F_HM0_WDATA(21) => FIC_0_APB_M_PWDATA(21), 
        F_HM0_WDATA(20) => FIC_0_APB_M_PWDATA(20), 
        F_HM0_WDATA(19) => FIC_0_APB_M_PWDATA(19), 
        F_HM0_WDATA(18) => FIC_0_APB_M_PWDATA(18), 
        F_HM0_WDATA(17) => MC_System_0_AMBA_SLAVE_0_PWDATA(17), 
        F_HM0_WDATA(16) => MC_System_0_AMBA_SLAVE_0_PWDATA(16), 
        F_HM0_WDATA(15) => MC_System_0_AMBA_SLAVE_0_PWDATA(15), 
        F_HM0_WDATA(14) => MC_System_0_AMBA_SLAVE_0_PWDATA(14), 
        F_HM0_WDATA(13) => MC_System_0_AMBA_SLAVE_0_PWDATA(13), 
        F_HM0_WDATA(12) => MC_System_0_AMBA_SLAVE_0_PWDATA(12), 
        F_HM0_WDATA(11) => MC_System_0_AMBA_SLAVE_0_PWDATA(11), 
        F_HM0_WDATA(10) => MC_System_0_AMBA_SLAVE_0_PWDATA(10), 
        F_HM0_WDATA(9) => MC_System_0_AMBA_SLAVE_0_PWDATA(9), 
        F_HM0_WDATA(8) => MC_System_0_AMBA_SLAVE_0_PWDATA(8), 
        F_HM0_WDATA(7) => MC_System_0_AMBA_SLAVE_0_PWDATA(7), 
        F_HM0_WDATA(6) => MC_System_0_AMBA_SLAVE_0_PWDATA(6), 
        F_HM0_WDATA(5) => MC_System_0_AMBA_SLAVE_0_PWDATA(5), 
        F_HM0_WDATA(4) => MC_System_0_AMBA_SLAVE_0_PWDATA(4), 
        F_HM0_WDATA(3) => MC_System_0_AMBA_SLAVE_0_PWDATA(3), 
        F_HM0_WDATA(2) => MC_System_0_AMBA_SLAVE_0_PWDATA(2), 
        F_HM0_WDATA(1) => MC_System_0_AMBA_SLAVE_0_PWDATA(1), 
        F_HM0_WDATA(0) => MC_System_0_AMBA_SLAVE_0_PWDATA(0), 
        F_HM0_WRITE => MC_System_0_AMBA_SLAVE_0_PWRITE, 
        FAB_CHRGVBUS => FAB_CHRGVBUS, FAB_DISCHRGVBUS => 
        FAB_DISCHRGVBUS, FAB_DMPULLDOWN => FAB_DMPULLDOWN, 
        FAB_DPPULLDOWN => FAB_DPPULLDOWN, FAB_DRVVBUS => 
        FAB_DRVVBUS, FAB_IDPULLUP => FAB_IDPULLUP, FAB_OPMODE(1)
         => FAB_OPMODE(1), FAB_OPMODE(0) => FAB_OPMODE(0), 
        FAB_SUSPENDM => FAB_SUSPENDM, FAB_TERMSEL => FAB_TERMSEL, 
        FAB_TXVALID => FAB_TXVALID, FAB_VCONTROL(3) => 
        FAB_VCONTROL(3), FAB_VCONTROL(2) => FAB_VCONTROL(2), 
        FAB_VCONTROL(1) => FAB_VCONTROL(1), FAB_VCONTROL(0) => 
        FAB_VCONTROL(0), FAB_VCONTROLLOADM => FAB_VCONTROLLOADM, 
        FAB_XCVRSEL(1) => FAB_XCVRSEL(1), FAB_XCVRSEL(0) => 
        FAB_XCVRSEL(0), FAB_XDATAOUT(7) => FAB_XDATAOUT(7), 
        FAB_XDATAOUT(6) => FAB_XDATAOUT(6), FAB_XDATAOUT(5) => 
        FAB_XDATAOUT(5), FAB_XDATAOUT(4) => FAB_XDATAOUT(4), 
        FAB_XDATAOUT(3) => FAB_XDATAOUT(3), FAB_XDATAOUT(2) => 
        FAB_XDATAOUT(2), FAB_XDATAOUT(1) => FAB_XDATAOUT(1), 
        FAB_XDATAOUT(0) => FAB_XDATAOUT(0), FACC_GLMUX_SEL => 
        FACC_GLMUX_SEL, FIC32_0_MASTER(1) => FIC32_0_MASTER(1), 
        FIC32_0_MASTER(0) => FIC32_0_MASTER(0), FIC32_1_MASTER(1)
         => FIC32_1_MASTER(1), FIC32_1_MASTER(0) => 
        FIC32_1_MASTER(0), FPGA_RESET_N => MSS_RESET_N_M2F, 
        GTX_CLK => GTX_CLK, H2F_INTERRUPT(15) => 
        H2F_INTERRUPT(15), H2F_INTERRUPT(14) => H2F_INTERRUPT(14), 
        H2F_INTERRUPT(13) => H2F_INTERRUPT(13), H2F_INTERRUPT(12)
         => H2F_INTERRUPT(12), H2F_INTERRUPT(11) => 
        H2F_INTERRUPT(11), H2F_INTERRUPT(10) => H2F_INTERRUPT(10), 
        H2F_INTERRUPT(9) => H2F_INTERRUPT(9), H2F_INTERRUPT(8)
         => H2F_INTERRUPT(8), H2F_INTERRUPT(7) => 
        H2F_INTERRUPT(7), H2F_INTERRUPT(6) => H2F_INTERRUPT(6), 
        H2F_INTERRUPT(5) => H2F_INTERRUPT(5), H2F_INTERRUPT(4)
         => H2F_INTERRUPT(4), H2F_INTERRUPT(3) => 
        H2F_INTERRUPT(3), H2F_INTERRUPT(2) => H2F_INTERRUPT(2), 
        H2F_INTERRUPT(1) => H2F_INTERRUPT(1), H2F_INTERRUPT(0)
         => H2F_INTERRUPT(0), H2F_NMI => H2F_NMI, H2FCALIB => 
        H2FCALIB, I2C0_SCL_MGPIO31B_H2F_A => 
        I2C0_SCL_MGPIO31B_H2F_A, I2C0_SCL_MGPIO31B_H2F_B => 
        I2C0_SCL_MGPIO31B_H2F_B, I2C0_SDA_MGPIO30B_H2F_A => 
        I2C0_SDA_MGPIO30B_H2F_A, I2C0_SDA_MGPIO30B_H2F_B => 
        I2C0_SDA_MGPIO30B_H2F_B, I2C1_SCL_MGPIO1A_H2F_A => 
        I2C1_SCL_MGPIO1A_H2F_A, I2C1_SCL_MGPIO1A_H2F_B => 
        I2C1_SCL_MGPIO1A_H2F_B, I2C1_SDA_MGPIO0A_H2F_A => 
        I2C1_SDA_MGPIO0A_H2F_A, I2C1_SDA_MGPIO0A_H2F_B => 
        GPIO_0_M2F_c, MDCF => MDCF, MDOENF => MDOENF, MDOF => 
        MDOF, MMUART0_CTS_MGPIO19B_H2F_A => 
        MMUART0_CTS_MGPIO19B_H2F_A, MMUART0_CTS_MGPIO19B_H2F_B
         => MMUART0_CTS_MGPIO19B_H2F_B, 
        MMUART0_DCD_MGPIO22B_H2F_A => MMUART0_DCD_MGPIO22B_H2F_A, 
        MMUART0_DCD_MGPIO22B_H2F_B => MMUART0_DCD_MGPIO22B_H2F_B, 
        MMUART0_DSR_MGPIO20B_H2F_A => MMUART0_DSR_MGPIO20B_H2F_A, 
        MMUART0_DSR_MGPIO20B_H2F_B => MMUART0_DSR_MGPIO20B_H2F_B, 
        MMUART0_DTR_MGPIO18B_H2F_A => MMUART0_DTR_MGPIO18B_H2F_A, 
        MMUART0_DTR_MGPIO18B_H2F_B => MMUART0_DTR_MGPIO18B_H2F_B, 
        MMUART0_RI_MGPIO21B_H2F_A => MMUART0_RI_MGPIO21B_H2F_A, 
        MMUART0_RI_MGPIO21B_H2F_B => MMUART0_RI_MGPIO21B_H2F_B, 
        MMUART0_RTS_MGPIO17B_H2F_A => MMUART0_RTS_MGPIO17B_H2F_A, 
        MMUART0_RTS_MGPIO17B_H2F_B => MMUART0_RTS_MGPIO17B_H2F_B, 
        MMUART0_RXD_MGPIO28B_H2F_A => MMUART0_RXD_MGPIO28B_H2F_A, 
        MMUART0_RXD_MGPIO28B_H2F_B => MMUART0_RXD_MGPIO28B_H2F_B, 
        MMUART0_SCK_MGPIO29B_H2F_A => MMUART0_SCK_MGPIO29B_H2F_A, 
        MMUART0_SCK_MGPIO29B_H2F_B => MMUART0_SCK_MGPIO29B_H2F_B, 
        MMUART0_TXD_MGPIO27B_H2F_A => MMUART0_TXD_MGPIO27B_H2F_A, 
        MMUART0_TXD_MGPIO27B_H2F_B => MMUART0_TXD_MGPIO27B_H2F_B, 
        MMUART1_DTR_MGPIO12B_H2F_A => MMUART1_DTR_MGPIO12B_H2F_A, 
        MMUART1_RTS_MGPIO11B_H2F_A => MMUART1_RTS_MGPIO11B_H2F_A, 
        MMUART1_RTS_MGPIO11B_H2F_B => MMUART1_RTS_MGPIO11B_H2F_B, 
        MMUART1_RXD_MGPIO26B_H2F_A => MMUART1_RXD_MGPIO26B_H2F_A, 
        MMUART1_RXD_MGPIO26B_H2F_B => MMUART1_RXD_MGPIO26B_H2F_B, 
        MMUART1_SCK_MGPIO25B_H2F_A => MMUART1_SCK_MGPIO25B_H2F_A, 
        MMUART1_SCK_MGPIO25B_H2F_B => MMUART1_SCK_MGPIO25B_H2F_B, 
        MMUART1_TXD_MGPIO24B_H2F_A => MMUART1_TXD_MGPIO24B_H2F_A, 
        MMUART1_TXD_MGPIO24B_H2F_B => MMUART1_TXD_MGPIO24B_H2F_B, 
        MPLL_LOCK => MPLL_LOCK, PER2_FABRIC_PADDR(15) => 
        FIC_2_APB_M_PADDR(15), PER2_FABRIC_PADDR(14) => 
        FIC_2_APB_M_PADDR(14), PER2_FABRIC_PADDR(13) => 
        FIC_2_APB_M_PADDR(13), PER2_FABRIC_PADDR(12) => 
        FIC_2_APB_M_PADDR(12), PER2_FABRIC_PADDR(11) => 
        FIC_2_APB_M_PADDR(11), PER2_FABRIC_PADDR(10) => 
        FIC_2_APB_M_PADDR(10), PER2_FABRIC_PADDR(9) => 
        FIC_2_APB_M_PADDR(9), PER2_FABRIC_PADDR(8) => 
        FIC_2_APB_M_PADDR(8), PER2_FABRIC_PADDR(7) => 
        FIC_2_APB_M_PADDR(7), PER2_FABRIC_PADDR(6) => 
        FIC_2_APB_M_PADDR(6), PER2_FABRIC_PADDR(5) => 
        FIC_2_APB_M_PADDR(5), PER2_FABRIC_PADDR(4) => 
        FIC_2_APB_M_PADDR(4), PER2_FABRIC_PADDR(3) => 
        FIC_2_APB_M_PADDR(3), PER2_FABRIC_PADDR(2) => 
        FIC_2_APB_M_PADDR(2), PER2_FABRIC_PENABLE => 
        FIC_2_APB_M_PENABLE, PER2_FABRIC_PSEL => FIC_2_APB_M_PSEL, 
        PER2_FABRIC_PWDATA(31) => FIC_2_APB_M_PWDATA(31), 
        PER2_FABRIC_PWDATA(30) => FIC_2_APB_M_PWDATA(30), 
        PER2_FABRIC_PWDATA(29) => FIC_2_APB_M_PWDATA(29), 
        PER2_FABRIC_PWDATA(28) => FIC_2_APB_M_PWDATA(28), 
        PER2_FABRIC_PWDATA(27) => FIC_2_APB_M_PWDATA(27), 
        PER2_FABRIC_PWDATA(26) => FIC_2_APB_M_PWDATA(26), 
        PER2_FABRIC_PWDATA(25) => FIC_2_APB_M_PWDATA(25), 
        PER2_FABRIC_PWDATA(24) => FIC_2_APB_M_PWDATA(24), 
        PER2_FABRIC_PWDATA(23) => FIC_2_APB_M_PWDATA(23), 
        PER2_FABRIC_PWDATA(22) => FIC_2_APB_M_PWDATA(22), 
        PER2_FABRIC_PWDATA(21) => FIC_2_APB_M_PWDATA(21), 
        PER2_FABRIC_PWDATA(20) => FIC_2_APB_M_PWDATA(20), 
        PER2_FABRIC_PWDATA(19) => FIC_2_APB_M_PWDATA(19), 
        PER2_FABRIC_PWDATA(18) => FIC_2_APB_M_PWDATA(18), 
        PER2_FABRIC_PWDATA(17) => FIC_2_APB_M_PWDATA(17), 
        PER2_FABRIC_PWDATA(16) => FIC_2_APB_M_PWDATA(16), 
        PER2_FABRIC_PWDATA(15) => FIC_2_APB_M_PWDATA(15), 
        PER2_FABRIC_PWDATA(14) => FIC_2_APB_M_PWDATA(14), 
        PER2_FABRIC_PWDATA(13) => FIC_2_APB_M_PWDATA(13), 
        PER2_FABRIC_PWDATA(12) => FIC_2_APB_M_PWDATA(12), 
        PER2_FABRIC_PWDATA(11) => FIC_2_APB_M_PWDATA(11), 
        PER2_FABRIC_PWDATA(10) => FIC_2_APB_M_PWDATA(10), 
        PER2_FABRIC_PWDATA(9) => FIC_2_APB_M_PWDATA(9), 
        PER2_FABRIC_PWDATA(8) => FIC_2_APB_M_PWDATA(8), 
        PER2_FABRIC_PWDATA(7) => FIC_2_APB_M_PWDATA(7), 
        PER2_FABRIC_PWDATA(6) => FIC_2_APB_M_PWDATA(6), 
        PER2_FABRIC_PWDATA(5) => FIC_2_APB_M_PWDATA(5), 
        PER2_FABRIC_PWDATA(4) => FIC_2_APB_M_PWDATA(4), 
        PER2_FABRIC_PWDATA(3) => FIC_2_APB_M_PWDATA(3), 
        PER2_FABRIC_PWDATA(2) => FIC_2_APB_M_PWDATA(2), 
        PER2_FABRIC_PWDATA(1) => FIC_2_APB_M_PWDATA(1), 
        PER2_FABRIC_PWDATA(0) => FIC_2_APB_M_PWDATA(0), 
        PER2_FABRIC_PWRITE => FIC_2_APB_M_PWRITE, RTC_MATCH => 
        RTC_MATCH, SLEEPDEEP => SLEEPDEEP, SLEEPHOLDACK => 
        SLEEPHOLDACK, SLEEPING => SLEEPING, SMBALERT_NO0 => 
        SMBALERT_NO0, SMBALERT_NO1 => SMBALERT_NO1, SMBSUS_NO0
         => SMBSUS_NO0, SMBSUS_NO1 => SMBSUS_NO1, SPI0_CLK_OUT
         => SPI0_CLK_OUT, SPI0_SDI_MGPIO5A_H2F_A => 
        SPI0_SDI_MGPIO5A_H2F_A, SPI0_SDI_MGPIO5A_H2F_B => 
        SPI0_SDI_MGPIO5A_H2F_B, SPI0_SDO_MGPIO6A_H2F_A => 
        SPI0_SDO_MGPIO6A_H2F_A, SPI0_SDO_MGPIO6A_H2F_B => 
        SPI0_SDO_MGPIO6A_H2F_B, SPI0_SS0_MGPIO7A_H2F_A => 
        SPI0_SS0_MGPIO7A_H2F_A, SPI0_SS0_MGPIO7A_H2F_B => 
        SPI0_SS0_MGPIO7A_H2F_B, SPI0_SS1_MGPIO8A_H2F_A => 
        SPI0_SS1_MGPIO8A_H2F_A, SPI0_SS1_MGPIO8A_H2F_B => 
        SPI0_SS1_MGPIO8A_H2F_B, SPI0_SS2_MGPIO9A_H2F_A => 
        SPI0_SS2_MGPIO9A_H2F_A, SPI0_SS2_MGPIO9A_H2F_B => 
        SPI0_SS2_MGPIO9A_H2F_B, SPI0_SS3_MGPIO10A_H2F_A => 
        SPI0_SS3_MGPIO10A_H2F_A, SPI0_SS3_MGPIO10A_H2F_B => 
        SPI0_SS3_MGPIO10A_H2F_B, SPI0_SS4_MGPIO19A_H2F_A => 
        SPI0_SS4_MGPIO19A_H2F_A, SPI0_SS5_MGPIO20A_H2F_A => 
        SPI0_SS5_MGPIO20A_H2F_A, SPI0_SS6_MGPIO21A_H2F_A => 
        SPI0_SS6_MGPIO21A_H2F_A, SPI0_SS7_MGPIO22A_H2F_A => 
        SPI0_SS7_MGPIO22A_H2F_A, SPI1_CLK_OUT => SPI1_CLK_OUT, 
        SPI1_SDI_MGPIO11A_H2F_A => SPI1_SDI_MGPIO11A_H2F_A, 
        SPI1_SDI_MGPIO11A_H2F_B => SPI1_SDI_MGPIO11A_H2F_B, 
        SPI1_SDO_MGPIO12A_H2F_A => SPI1_SDO_MGPIO12A_H2F_A, 
        SPI1_SDO_MGPIO12A_H2F_B => SPI1_SDO_MGPIO12A_H2F_B, 
        SPI1_SS0_MGPIO13A_H2F_A => SPI1_SS0_MGPIO13A_H2F_A, 
        SPI1_SS0_MGPIO13A_H2F_B => SPI1_SS0_MGPIO13A_H2F_B, 
        SPI1_SS1_MGPIO14A_H2F_A => SPI1_SS1_MGPIO14A_H2F_A, 
        SPI1_SS1_MGPIO14A_H2F_B => SPI1_SS1_MGPIO14A_H2F_B, 
        SPI1_SS2_MGPIO15A_H2F_A => SPI1_SS2_MGPIO15A_H2F_A, 
        SPI1_SS2_MGPIO15A_H2F_B => SPI1_SS2_MGPIO15A_H2F_B, 
        SPI1_SS3_MGPIO16A_H2F_A => SPI1_SS3_MGPIO16A_H2F_A, 
        SPI1_SS3_MGPIO16A_H2F_B => SPI1_SS3_MGPIO16A_H2F_B, 
        SPI1_SS4_MGPIO17A_H2F_A => SPI1_SS4_MGPIO17A_H2F_A, 
        SPI1_SS5_MGPIO18A_H2F_A => SPI1_SS5_MGPIO18A_H2F_A, 
        SPI1_SS6_MGPIO23A_H2F_A => SPI1_SS6_MGPIO23A_H2F_A, 
        SPI1_SS7_MGPIO24A_H2F_A => SPI1_SS7_MGPIO24A_H2F_A, 
        TCGF(9) => TCGF(9), TCGF(8) => TCGF(8), TCGF(7) => 
        TCGF(7), TCGF(6) => TCGF(6), TCGF(5) => TCGF(5), TCGF(4)
         => TCGF(4), TCGF(3) => TCGF(3), TCGF(2) => TCGF(2), 
        TCGF(1) => TCGF(1), TCGF(0) => TCGF(0), TRACECLK => 
        TRACECLK, TRACEDATA(3) => TRACEDATA(3), TRACEDATA(2) => 
        TRACEDATA(2), TRACEDATA(1) => TRACEDATA(1), TRACEDATA(0)
         => TRACEDATA(0), TX_CLK => TX_CLK, TX_ENF => TX_ENF, 
        TX_ERRF => TX_ERRF, TXCTL_EN_RIF => TXCTL_EN_RIF, 
        TXD_RIF(3) => TXD_RIF(3), TXD_RIF(2) => TXD_RIF(2), 
        TXD_RIF(1) => TXD_RIF(1), TXD_RIF(0) => TXD_RIF(0), 
        TXDF(7) => TXDF(7), TXDF(6) => TXDF(6), TXDF(5) => 
        TXDF(5), TXDF(4) => TXDF(4), TXDF(3) => TXDF(3), TXDF(2)
         => TXDF(2), TXDF(1) => TXDF(1), TXDF(0) => TXDF(0), TXEV
         => TXEV, WDOGTIMEOUT => WDOGTIMEOUT, 
        F_ARREADY_HREADYOUT1 => F_ARREADY_HREADYOUT1, 
        F_AWREADY_HREADYOUT0 => F_AWREADY_HREADYOUT0, F_BID(3)
         => F_BID(3), F_BID(2) => F_BID(2), F_BID(1) => F_BID(1), 
        F_BID(0) => F_BID(0), F_BRESP_HRESP0(1) => 
        F_BRESP_HRESP0(1), F_BRESP_HRESP0(0) => F_BRESP_HRESP0(0), 
        F_BVALID => F_BVALID, F_RDATA_HRDATA01(63) => 
        F_RDATA_HRDATA01(63), F_RDATA_HRDATA01(62) => 
        F_RDATA_HRDATA01(62), F_RDATA_HRDATA01(61) => 
        F_RDATA_HRDATA01(61), F_RDATA_HRDATA01(60) => 
        F_RDATA_HRDATA01(60), F_RDATA_HRDATA01(59) => 
        F_RDATA_HRDATA01(59), F_RDATA_HRDATA01(58) => 
        F_RDATA_HRDATA01(58), F_RDATA_HRDATA01(57) => 
        F_RDATA_HRDATA01(57), F_RDATA_HRDATA01(56) => 
        F_RDATA_HRDATA01(56), F_RDATA_HRDATA01(55) => 
        F_RDATA_HRDATA01(55), F_RDATA_HRDATA01(54) => 
        F_RDATA_HRDATA01(54), F_RDATA_HRDATA01(53) => 
        F_RDATA_HRDATA01(53), F_RDATA_HRDATA01(52) => 
        F_RDATA_HRDATA01(52), F_RDATA_HRDATA01(51) => 
        F_RDATA_HRDATA01(51), F_RDATA_HRDATA01(50) => 
        F_RDATA_HRDATA01(50), F_RDATA_HRDATA01(49) => 
        F_RDATA_HRDATA01(49), F_RDATA_HRDATA01(48) => 
        F_RDATA_HRDATA01(48), F_RDATA_HRDATA01(47) => 
        F_RDATA_HRDATA01(47), F_RDATA_HRDATA01(46) => 
        F_RDATA_HRDATA01(46), F_RDATA_HRDATA01(45) => 
        F_RDATA_HRDATA01(45), F_RDATA_HRDATA01(44) => 
        F_RDATA_HRDATA01(44), F_RDATA_HRDATA01(43) => 
        F_RDATA_HRDATA01(43), F_RDATA_HRDATA01(42) => 
        F_RDATA_HRDATA01(42), F_RDATA_HRDATA01(41) => 
        F_RDATA_HRDATA01(41), F_RDATA_HRDATA01(40) => 
        F_RDATA_HRDATA01(40), F_RDATA_HRDATA01(39) => 
        F_RDATA_HRDATA01(39), F_RDATA_HRDATA01(38) => 
        F_RDATA_HRDATA01(38), F_RDATA_HRDATA01(37) => 
        F_RDATA_HRDATA01(37), F_RDATA_HRDATA01(36) => 
        F_RDATA_HRDATA01(36), F_RDATA_HRDATA01(35) => 
        F_RDATA_HRDATA01(35), F_RDATA_HRDATA01(34) => 
        F_RDATA_HRDATA01(34), F_RDATA_HRDATA01(33) => 
        F_RDATA_HRDATA01(33), F_RDATA_HRDATA01(32) => 
        F_RDATA_HRDATA01(32), F_RDATA_HRDATA01(31) => 
        F_RDATA_HRDATA01(31), F_RDATA_HRDATA01(30) => 
        F_RDATA_HRDATA01(30), F_RDATA_HRDATA01(29) => 
        F_RDATA_HRDATA01(29), F_RDATA_HRDATA01(28) => 
        F_RDATA_HRDATA01(28), F_RDATA_HRDATA01(27) => 
        F_RDATA_HRDATA01(27), F_RDATA_HRDATA01(26) => 
        F_RDATA_HRDATA01(26), F_RDATA_HRDATA01(25) => 
        F_RDATA_HRDATA01(25), F_RDATA_HRDATA01(24) => 
        F_RDATA_HRDATA01(24), F_RDATA_HRDATA01(23) => 
        F_RDATA_HRDATA01(23), F_RDATA_HRDATA01(22) => 
        F_RDATA_HRDATA01(22), F_RDATA_HRDATA01(21) => 
        F_RDATA_HRDATA01(21), F_RDATA_HRDATA01(20) => 
        F_RDATA_HRDATA01(20), F_RDATA_HRDATA01(19) => 
        F_RDATA_HRDATA01(19), F_RDATA_HRDATA01(18) => 
        F_RDATA_HRDATA01(18), F_RDATA_HRDATA01(17) => 
        F_RDATA_HRDATA01(17), F_RDATA_HRDATA01(16) => 
        F_RDATA_HRDATA01(16), F_RDATA_HRDATA01(15) => 
        F_RDATA_HRDATA01(15), F_RDATA_HRDATA01(14) => 
        F_RDATA_HRDATA01(14), F_RDATA_HRDATA01(13) => 
        F_RDATA_HRDATA01(13), F_RDATA_HRDATA01(12) => 
        F_RDATA_HRDATA01(12), F_RDATA_HRDATA01(11) => 
        F_RDATA_HRDATA01(11), F_RDATA_HRDATA01(10) => 
        F_RDATA_HRDATA01(10), F_RDATA_HRDATA01(9) => 
        F_RDATA_HRDATA01(9), F_RDATA_HRDATA01(8) => 
        F_RDATA_HRDATA01(8), F_RDATA_HRDATA01(7) => 
        F_RDATA_HRDATA01(7), F_RDATA_HRDATA01(6) => 
        F_RDATA_HRDATA01(6), F_RDATA_HRDATA01(5) => 
        F_RDATA_HRDATA01(5), F_RDATA_HRDATA01(4) => 
        F_RDATA_HRDATA01(4), F_RDATA_HRDATA01(3) => 
        F_RDATA_HRDATA01(3), F_RDATA_HRDATA01(2) => 
        F_RDATA_HRDATA01(2), F_RDATA_HRDATA01(1) => 
        F_RDATA_HRDATA01(1), F_RDATA_HRDATA01(0) => 
        F_RDATA_HRDATA01(0), F_RID(3) => F_RID(3), F_RID(2) => 
        F_RID(2), F_RID(1) => F_RID(1), F_RID(0) => F_RID(0), 
        F_RLAST => F_RLAST, F_RRESP_HRESP1(1) => 
        F_RRESP_HRESP1(1), F_RRESP_HRESP1(0) => F_RRESP_HRESP1(0), 
        F_RVALID => F_RVALID, F_WREADY => F_WREADY, 
        MDDR_FABRIC_PRDATA(15) => MDDR_FABRIC_PRDATA(15), 
        MDDR_FABRIC_PRDATA(14) => MDDR_FABRIC_PRDATA(14), 
        MDDR_FABRIC_PRDATA(13) => MDDR_FABRIC_PRDATA(13), 
        MDDR_FABRIC_PRDATA(12) => MDDR_FABRIC_PRDATA(12), 
        MDDR_FABRIC_PRDATA(11) => MDDR_FABRIC_PRDATA(11), 
        MDDR_FABRIC_PRDATA(10) => MDDR_FABRIC_PRDATA(10), 
        MDDR_FABRIC_PRDATA(9) => MDDR_FABRIC_PRDATA(9), 
        MDDR_FABRIC_PRDATA(8) => MDDR_FABRIC_PRDATA(8), 
        MDDR_FABRIC_PRDATA(7) => MDDR_FABRIC_PRDATA(7), 
        MDDR_FABRIC_PRDATA(6) => MDDR_FABRIC_PRDATA(6), 
        MDDR_FABRIC_PRDATA(5) => MDDR_FABRIC_PRDATA(5), 
        MDDR_FABRIC_PRDATA(4) => MDDR_FABRIC_PRDATA(4), 
        MDDR_FABRIC_PRDATA(3) => MDDR_FABRIC_PRDATA(3), 
        MDDR_FABRIC_PRDATA(2) => MDDR_FABRIC_PRDATA(2), 
        MDDR_FABRIC_PRDATA(1) => MDDR_FABRIC_PRDATA(1), 
        MDDR_FABRIC_PRDATA(0) => MDDR_FABRIC_PRDATA(0), 
        MDDR_FABRIC_PREADY => MDDR_FABRIC_PREADY, 
        MDDR_FABRIC_PSLVERR => MDDR_FABRIC_PSLVERR, 
        CAN_RXBUS_F2H_SCP => \VCC\, CAN_TX_EBL_F2H_SCP => \VCC\, 
        CAN_TXBUS_F2H_SCP => \VCC\, COLF => \VCC\, CRSF => \VCC\, 
        F2_DMAREADY(1) => \VCC\, F2_DMAREADY(0) => \VCC\, 
        F2H_INTERRUPT(15) => \GND\, F2H_INTERRUPT(14) => \GND\, 
        F2H_INTERRUPT(13) => \GND\, F2H_INTERRUPT(12) => \GND\, 
        F2H_INTERRUPT(11) => \GND\, F2H_INTERRUPT(10) => \GND\, 
        F2H_INTERRUPT(9) => \GND\, F2H_INTERRUPT(8) => \GND\, 
        F2H_INTERRUPT(7) => \GND\, F2H_INTERRUPT(6) => \GND\, 
        F2H_INTERRUPT(5) => \GND\, F2H_INTERRUPT(4) => \GND\, 
        F2H_INTERRUPT(3) => \GND\, F2H_INTERRUPT(2) => \GND\, 
        F2H_INTERRUPT(1) => \GND\, F2H_INTERRUPT(0) => \GND\, 
        F2HCALIB => \VCC\, F_DMAREADY(1) => \VCC\, F_DMAREADY(0)
         => \VCC\, F_FM0_ADDR(31) => \GND\, F_FM0_ADDR(30) => 
        \GND\, F_FM0_ADDR(29) => \GND\, F_FM0_ADDR(28) => \GND\, 
        F_FM0_ADDR(27) => \GND\, F_FM0_ADDR(26) => \GND\, 
        F_FM0_ADDR(25) => \GND\, F_FM0_ADDR(24) => \GND\, 
        F_FM0_ADDR(23) => \GND\, F_FM0_ADDR(22) => \GND\, 
        F_FM0_ADDR(21) => \GND\, F_FM0_ADDR(20) => \GND\, 
        F_FM0_ADDR(19) => \GND\, F_FM0_ADDR(18) => \GND\, 
        F_FM0_ADDR(17) => \GND\, F_FM0_ADDR(16) => \GND\, 
        F_FM0_ADDR(15) => \GND\, F_FM0_ADDR(14) => \GND\, 
        F_FM0_ADDR(13) => \GND\, F_FM0_ADDR(12) => \GND\, 
        F_FM0_ADDR(11) => \GND\, F_FM0_ADDR(10) => \GND\, 
        F_FM0_ADDR(9) => \GND\, F_FM0_ADDR(8) => \GND\, 
        F_FM0_ADDR(7) => \GND\, F_FM0_ADDR(6) => \GND\, 
        F_FM0_ADDR(5) => \GND\, F_FM0_ADDR(4) => \GND\, 
        F_FM0_ADDR(3) => \GND\, F_FM0_ADDR(2) => \GND\, 
        F_FM0_ADDR(1) => \GND\, F_FM0_ADDR(0) => \GND\, 
        F_FM0_ENABLE => \GND\, F_FM0_MASTLOCK => \GND\, 
        F_FM0_READY => \VCC\, F_FM0_SEL => \GND\, F_FM0_SIZE(1)
         => \GND\, F_FM0_SIZE(0) => \GND\, F_FM0_TRANS1 => \GND\, 
        F_FM0_WDATA(31) => \GND\, F_FM0_WDATA(30) => \GND\, 
        F_FM0_WDATA(29) => \GND\, F_FM0_WDATA(28) => \GND\, 
        F_FM0_WDATA(27) => \GND\, F_FM0_WDATA(26) => \GND\, 
        F_FM0_WDATA(25) => \GND\, F_FM0_WDATA(24) => \GND\, 
        F_FM0_WDATA(23) => \GND\, F_FM0_WDATA(22) => \GND\, 
        F_FM0_WDATA(21) => \GND\, F_FM0_WDATA(20) => \GND\, 
        F_FM0_WDATA(19) => \GND\, F_FM0_WDATA(18) => \GND\, 
        F_FM0_WDATA(17) => \GND\, F_FM0_WDATA(16) => \GND\, 
        F_FM0_WDATA(15) => \GND\, F_FM0_WDATA(14) => \GND\, 
        F_FM0_WDATA(13) => \GND\, F_FM0_WDATA(12) => \GND\, 
        F_FM0_WDATA(11) => \GND\, F_FM0_WDATA(10) => \GND\, 
        F_FM0_WDATA(9) => \GND\, F_FM0_WDATA(8) => \GND\, 
        F_FM0_WDATA(7) => \GND\, F_FM0_WDATA(6) => \GND\, 
        F_FM0_WDATA(5) => \GND\, F_FM0_WDATA(4) => \GND\, 
        F_FM0_WDATA(3) => \GND\, F_FM0_WDATA(2) => \GND\, 
        F_FM0_WDATA(1) => \GND\, F_FM0_WDATA(0) => \GND\, 
        F_FM0_WRITE => \GND\, F_HM0_RDATA(31) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        F_HM0_RDATA(30) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        F_HM0_RDATA(29) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        F_HM0_RDATA(28) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        F_HM0_RDATA(27) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        F_HM0_RDATA(26) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        F_HM0_RDATA(25) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        F_HM0_RDATA(24) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        F_HM0_RDATA(23) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        F_HM0_RDATA(22) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        F_HM0_RDATA(21) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        F_HM0_RDATA(20) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        F_HM0_RDATA(19) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        F_HM0_RDATA(18) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        F_HM0_RDATA(17) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17, 
        F_HM0_RDATA(16) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16, 
        F_HM0_RDATA(15) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15, 
        F_HM0_RDATA(14) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14, 
        F_HM0_RDATA(13) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13, 
        F_HM0_RDATA(12) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12, 
        F_HM0_RDATA(11) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11, 
        F_HM0_RDATA(10) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10, 
        F_HM0_RDATA(9) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9, 
        F_HM0_RDATA(8) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8, 
        F_HM0_RDATA(7) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7, 
        F_HM0_RDATA(6) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6, 
        F_HM0_RDATA(5) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5, 
        F_HM0_RDATA(4) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4, 
        F_HM0_RDATA(3) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3, 
        F_HM0_RDATA(2) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2, 
        F_HM0_RDATA(1) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1, 
        F_HM0_RDATA(0) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0, 
        F_HM0_READY => \VCC\, F_HM0_RESP => \GND\, FAB_AVALID => 
        \VCC\, FAB_HOSTDISCON => \VCC\, FAB_IDDIG => \VCC\, 
        FAB_LINESTATE(1) => \VCC\, FAB_LINESTATE(0) => \VCC\, 
        FAB_M3_RESET_N => \VCC\, FAB_PLL_LOCK => 
        MC_System_0_FIC_0_LOCK, FAB_RXACTIVE => \VCC\, 
        FAB_RXERROR => \VCC\, FAB_RXVALID => \VCC\, FAB_RXVALIDH
         => \GND\, FAB_SESSEND => \VCC\, FAB_TXREADY => \VCC\, 
        FAB_VBUSVALID => \VCC\, FAB_VSTATUS(7) => \VCC\, 
        FAB_VSTATUS(6) => \VCC\, FAB_VSTATUS(5) => \VCC\, 
        FAB_VSTATUS(4) => \VCC\, FAB_VSTATUS(3) => \VCC\, 
        FAB_VSTATUS(2) => \VCC\, FAB_VSTATUS(1) => \VCC\, 
        FAB_VSTATUS(0) => \VCC\, FAB_XDATAIN(7) => \VCC\, 
        FAB_XDATAIN(6) => \VCC\, FAB_XDATAIN(5) => \VCC\, 
        FAB_XDATAIN(4) => \VCC\, FAB_XDATAIN(3) => \VCC\, 
        FAB_XDATAIN(2) => \VCC\, FAB_XDATAIN(1) => \VCC\, 
        FAB_XDATAIN(0) => \VCC\, GTX_CLKPF => \VCC\, I2C0_BCLK
         => \VCC\, I2C0_SCL_F2H_SCP => \VCC\, I2C0_SDA_F2H_SCP
         => \VCC\, I2C1_BCLK => \VCC\, I2C1_SCL_F2H_SCP => \VCC\, 
        I2C1_SDA_F2H_SCP => \VCC\, MDIF => \VCC\, 
        MGPIO0A_F2H_GPIN => \VCC\, MGPIO10A_F2H_GPIN => \VCC\, 
        MGPIO11A_F2H_GPIN => \VCC\, MGPIO11B_F2H_GPIN => \VCC\, 
        MGPIO12A_F2H_GPIN => \VCC\, MGPIO13A_F2H_GPIN => \VCC\, 
        MGPIO14A_F2H_GPIN => \VCC\, MGPIO15A_F2H_GPIN => \VCC\, 
        MGPIO16A_F2H_GPIN => \VCC\, MGPIO17B_F2H_GPIN => \VCC\, 
        MGPIO18B_F2H_GPIN => \VCC\, MGPIO19B_F2H_GPIN => \VCC\, 
        MGPIO1A_F2H_GPIN => \VCC\, MGPIO20B_F2H_GPIN => \VCC\, 
        MGPIO21B_F2H_GPIN => \VCC\, MGPIO22B_F2H_GPIN => \VCC\, 
        MGPIO24B_F2H_GPIN => \VCC\, MGPIO25B_F2H_GPIN => \VCC\, 
        MGPIO26B_F2H_GPIN => \VCC\, MGPIO27B_F2H_GPIN => \VCC\, 
        MGPIO28B_F2H_GPIN => \VCC\, MGPIO29B_F2H_GPIN => \VCC\, 
        MGPIO2A_F2H_GPIN => \VCC\, MGPIO30B_F2H_GPIN => \VCC\, 
        MGPIO31B_F2H_GPIN => \VCC\, MGPIO3A_F2H_GPIN => \VCC\, 
        MGPIO4A_F2H_GPIN => \VCC\, MGPIO5A_F2H_GPIN => \VCC\, 
        MGPIO6A_F2H_GPIN => \VCC\, MGPIO7A_F2H_GPIN => \VCC\, 
        MGPIO8A_F2H_GPIN => \VCC\, MGPIO9A_F2H_GPIN => \VCC\, 
        MMUART0_CTS_F2H_SCP => \VCC\, MMUART0_DCD_F2H_SCP => 
        \VCC\, MMUART0_DSR_F2H_SCP => \VCC\, MMUART0_DTR_F2H_SCP
         => \VCC\, MMUART0_RI_F2H_SCP => \VCC\, 
        MMUART0_RTS_F2H_SCP => \VCC\, MMUART0_RXD_F2H_SCP => 
        \VCC\, MMUART0_SCK_F2H_SCP => \VCC\, MMUART0_TXD_F2H_SCP
         => \VCC\, MMUART1_CTS_F2H_SCP => \VCC\, 
        MMUART1_DCD_F2H_SCP => \VCC\, MMUART1_DSR_F2H_SCP => 
        \VCC\, MMUART1_RI_F2H_SCP => \VCC\, MMUART1_RTS_F2H_SCP
         => \VCC\, MMUART1_RXD_F2H_SCP => \VCC\, 
        MMUART1_SCK_F2H_SCP => \VCC\, MMUART1_TXD_F2H_SCP => 
        \VCC\, PER2_FABRIC_PRDATA(31) => \GND\, 
        PER2_FABRIC_PRDATA(30) => \GND\, PER2_FABRIC_PRDATA(29)
         => \GND\, PER2_FABRIC_PRDATA(28) => \GND\, 
        PER2_FABRIC_PRDATA(27) => \GND\, PER2_FABRIC_PRDATA(26)
         => \GND\, PER2_FABRIC_PRDATA(25) => \GND\, 
        PER2_FABRIC_PRDATA(24) => \GND\, PER2_FABRIC_PRDATA(23)
         => \GND\, PER2_FABRIC_PRDATA(22) => \GND\, 
        PER2_FABRIC_PRDATA(21) => \GND\, PER2_FABRIC_PRDATA(20)
         => \GND\, PER2_FABRIC_PRDATA(19) => \GND\, 
        PER2_FABRIC_PRDATA(18) => \GND\, PER2_FABRIC_PRDATA(17)
         => \GND\, PER2_FABRIC_PRDATA(16) => \GND\, 
        PER2_FABRIC_PRDATA(15) => \GND\, PER2_FABRIC_PRDATA(14)
         => \GND\, PER2_FABRIC_PRDATA(13) => \GND\, 
        PER2_FABRIC_PRDATA(12) => \GND\, PER2_FABRIC_PRDATA(11)
         => \GND\, PER2_FABRIC_PRDATA(10) => \GND\, 
        PER2_FABRIC_PRDATA(9) => \GND\, PER2_FABRIC_PRDATA(8) => 
        \GND\, PER2_FABRIC_PRDATA(7) => \GND\, 
        PER2_FABRIC_PRDATA(6) => \GND\, PER2_FABRIC_PRDATA(5) => 
        \GND\, PER2_FABRIC_PRDATA(4) => \GND\, 
        PER2_FABRIC_PRDATA(3) => \GND\, PER2_FABRIC_PRDATA(2) => 
        \GND\, PER2_FABRIC_PRDATA(1) => \GND\, 
        PER2_FABRIC_PRDATA(0) => \GND\, PER2_FABRIC_PREADY => 
        \VCC\, PER2_FABRIC_PSLVERR => \GND\, RCGF(9) => \VCC\, 
        RCGF(8) => \VCC\, RCGF(7) => \VCC\, RCGF(6) => \VCC\, 
        RCGF(5) => \VCC\, RCGF(4) => \VCC\, RCGF(3) => \VCC\, 
        RCGF(2) => \VCC\, RCGF(1) => \VCC\, RCGF(0) => \VCC\, 
        RX_CLKPF => \VCC\, RX_DVF => \VCC\, RX_ERRF => \VCC\, 
        RX_EV => \VCC\, RXDF(7) => \VCC\, RXDF(6) => \VCC\, 
        RXDF(5) => \VCC\, RXDF(4) => \VCC\, RXDF(3) => \VCC\, 
        RXDF(2) => \VCC\, RXDF(1) => \VCC\, RXDF(0) => \VCC\, 
        SLEEPHOLDREQ => \GND\, SMBALERT_NI0 => \VCC\, 
        SMBALERT_NI1 => \VCC\, SMBSUS_NI0 => \VCC\, SMBSUS_NI1
         => \VCC\, SPI0_CLK_IN => \VCC\, SPI0_SDI_F2H_SCP => 
        \VCC\, SPI0_SDO_F2H_SCP => \VCC\, SPI0_SS0_F2H_SCP => 
        \VCC\, SPI0_SS1_F2H_SCP => \VCC\, SPI0_SS2_F2H_SCP => 
        \VCC\, SPI0_SS3_F2H_SCP => \VCC\, SPI1_CLK_IN => \VCC\, 
        SPI1_SDI_F2H_SCP => \VCC\, SPI1_SDO_F2H_SCP => \VCC\, 
        SPI1_SS0_F2H_SCP => \VCC\, SPI1_SS1_F2H_SCP => \VCC\, 
        SPI1_SS2_F2H_SCP => \VCC\, SPI1_SS3_F2H_SCP => \VCC\, 
        TX_CLKPF => \VCC\, USER_MSS_GPIO_RESET_N => \VCC\, 
        USER_MSS_RESET_N => \VCC\, XCLK_FAB => \VCC\, CLK_BASE
         => MC_System_0_FIC_0_CLK, CLK_MDDR_APB => \VCC\, 
        F_ARADDR_HADDR1(31) => \VCC\, F_ARADDR_HADDR1(30) => 
        \VCC\, F_ARADDR_HADDR1(29) => \VCC\, F_ARADDR_HADDR1(28)
         => \VCC\, F_ARADDR_HADDR1(27) => \VCC\, 
        F_ARADDR_HADDR1(26) => \VCC\, F_ARADDR_HADDR1(25) => 
        \VCC\, F_ARADDR_HADDR1(24) => \VCC\, F_ARADDR_HADDR1(23)
         => \VCC\, F_ARADDR_HADDR1(22) => \VCC\, 
        F_ARADDR_HADDR1(21) => \VCC\, F_ARADDR_HADDR1(20) => 
        \VCC\, F_ARADDR_HADDR1(19) => \VCC\, F_ARADDR_HADDR1(18)
         => \VCC\, F_ARADDR_HADDR1(17) => \VCC\, 
        F_ARADDR_HADDR1(16) => \VCC\, F_ARADDR_HADDR1(15) => 
        \VCC\, F_ARADDR_HADDR1(14) => \VCC\, F_ARADDR_HADDR1(13)
         => \VCC\, F_ARADDR_HADDR1(12) => \VCC\, 
        F_ARADDR_HADDR1(11) => \VCC\, F_ARADDR_HADDR1(10) => 
        \VCC\, F_ARADDR_HADDR1(9) => \VCC\, F_ARADDR_HADDR1(8)
         => \VCC\, F_ARADDR_HADDR1(7) => \VCC\, 
        F_ARADDR_HADDR1(6) => \VCC\, F_ARADDR_HADDR1(5) => \VCC\, 
        F_ARADDR_HADDR1(4) => \VCC\, F_ARADDR_HADDR1(3) => \VCC\, 
        F_ARADDR_HADDR1(2) => \VCC\, F_ARADDR_HADDR1(1) => \VCC\, 
        F_ARADDR_HADDR1(0) => \VCC\, F_ARBURST_HTRANS1(1) => 
        \GND\, F_ARBURST_HTRANS1(0) => \GND\, F_ARID_HSEL1(3) => 
        \GND\, F_ARID_HSEL1(2) => \GND\, F_ARID_HSEL1(1) => \GND\, 
        F_ARID_HSEL1(0) => \GND\, F_ARLEN_HBURST1(3) => \GND\, 
        F_ARLEN_HBURST1(2) => \GND\, F_ARLEN_HBURST1(1) => \GND\, 
        F_ARLEN_HBURST1(0) => \GND\, F_ARLOCK_HMASTLOCK1(1) => 
        \GND\, F_ARLOCK_HMASTLOCK1(0) => \GND\, 
        F_ARSIZE_HSIZE1(1) => \GND\, F_ARSIZE_HSIZE1(0) => \GND\, 
        F_ARVALID_HWRITE1 => \GND\, F_AWADDR_HADDR0(31) => \VCC\, 
        F_AWADDR_HADDR0(30) => \VCC\, F_AWADDR_HADDR0(29) => 
        \VCC\, F_AWADDR_HADDR0(28) => \VCC\, F_AWADDR_HADDR0(27)
         => \VCC\, F_AWADDR_HADDR0(26) => \VCC\, 
        F_AWADDR_HADDR0(25) => \VCC\, F_AWADDR_HADDR0(24) => 
        \VCC\, F_AWADDR_HADDR0(23) => \VCC\, F_AWADDR_HADDR0(22)
         => \VCC\, F_AWADDR_HADDR0(21) => \VCC\, 
        F_AWADDR_HADDR0(20) => \VCC\, F_AWADDR_HADDR0(19) => 
        \VCC\, F_AWADDR_HADDR0(18) => \VCC\, F_AWADDR_HADDR0(17)
         => \VCC\, F_AWADDR_HADDR0(16) => \VCC\, 
        F_AWADDR_HADDR0(15) => \VCC\, F_AWADDR_HADDR0(14) => 
        \VCC\, F_AWADDR_HADDR0(13) => \VCC\, F_AWADDR_HADDR0(12)
         => \VCC\, F_AWADDR_HADDR0(11) => \VCC\, 
        F_AWADDR_HADDR0(10) => \VCC\, F_AWADDR_HADDR0(9) => \VCC\, 
        F_AWADDR_HADDR0(8) => \VCC\, F_AWADDR_HADDR0(7) => \VCC\, 
        F_AWADDR_HADDR0(6) => \VCC\, F_AWADDR_HADDR0(5) => \VCC\, 
        F_AWADDR_HADDR0(4) => \VCC\, F_AWADDR_HADDR0(3) => \VCC\, 
        F_AWADDR_HADDR0(2) => \VCC\, F_AWADDR_HADDR0(1) => \VCC\, 
        F_AWADDR_HADDR0(0) => \VCC\, F_AWBURST_HTRANS0(1) => 
        \GND\, F_AWBURST_HTRANS0(0) => \GND\, F_AWID_HSEL0(3) => 
        \GND\, F_AWID_HSEL0(2) => \GND\, F_AWID_HSEL0(1) => \GND\, 
        F_AWID_HSEL0(0) => \GND\, F_AWLEN_HBURST0(3) => \GND\, 
        F_AWLEN_HBURST0(2) => \GND\, F_AWLEN_HBURST0(1) => \GND\, 
        F_AWLEN_HBURST0(0) => \GND\, F_AWLOCK_HMASTLOCK0(1) => 
        \GND\, F_AWLOCK_HMASTLOCK0(0) => \GND\, 
        F_AWSIZE_HSIZE0(1) => \GND\, F_AWSIZE_HSIZE0(0) => \GND\, 
        F_AWVALID_HWRITE0 => \GND\, F_BREADY => \GND\, F_RMW_AXI
         => \GND\, F_RREADY => \GND\, F_WDATA_HWDATA01(63) => 
        \VCC\, F_WDATA_HWDATA01(62) => \VCC\, 
        F_WDATA_HWDATA01(61) => \VCC\, F_WDATA_HWDATA01(60) => 
        \VCC\, F_WDATA_HWDATA01(59) => \VCC\, 
        F_WDATA_HWDATA01(58) => \VCC\, F_WDATA_HWDATA01(57) => 
        \VCC\, F_WDATA_HWDATA01(56) => \VCC\, 
        F_WDATA_HWDATA01(55) => \VCC\, F_WDATA_HWDATA01(54) => 
        \VCC\, F_WDATA_HWDATA01(53) => \VCC\, 
        F_WDATA_HWDATA01(52) => \VCC\, F_WDATA_HWDATA01(51) => 
        \VCC\, F_WDATA_HWDATA01(50) => \VCC\, 
        F_WDATA_HWDATA01(49) => \VCC\, F_WDATA_HWDATA01(48) => 
        \VCC\, F_WDATA_HWDATA01(47) => \VCC\, 
        F_WDATA_HWDATA01(46) => \VCC\, F_WDATA_HWDATA01(45) => 
        \VCC\, F_WDATA_HWDATA01(44) => \VCC\, 
        F_WDATA_HWDATA01(43) => \VCC\, F_WDATA_HWDATA01(42) => 
        \VCC\, F_WDATA_HWDATA01(41) => \VCC\, 
        F_WDATA_HWDATA01(40) => \VCC\, F_WDATA_HWDATA01(39) => 
        \VCC\, F_WDATA_HWDATA01(38) => \VCC\, 
        F_WDATA_HWDATA01(37) => \VCC\, F_WDATA_HWDATA01(36) => 
        \VCC\, F_WDATA_HWDATA01(35) => \VCC\, 
        F_WDATA_HWDATA01(34) => \VCC\, F_WDATA_HWDATA01(33) => 
        \VCC\, F_WDATA_HWDATA01(32) => \VCC\, 
        F_WDATA_HWDATA01(31) => \VCC\, F_WDATA_HWDATA01(30) => 
        \VCC\, F_WDATA_HWDATA01(29) => \VCC\, 
        F_WDATA_HWDATA01(28) => \VCC\, F_WDATA_HWDATA01(27) => 
        \VCC\, F_WDATA_HWDATA01(26) => \VCC\, 
        F_WDATA_HWDATA01(25) => \VCC\, F_WDATA_HWDATA01(24) => 
        \VCC\, F_WDATA_HWDATA01(23) => \VCC\, 
        F_WDATA_HWDATA01(22) => \VCC\, F_WDATA_HWDATA01(21) => 
        \VCC\, F_WDATA_HWDATA01(20) => \VCC\, 
        F_WDATA_HWDATA01(19) => \VCC\, F_WDATA_HWDATA01(18) => 
        \VCC\, F_WDATA_HWDATA01(17) => \VCC\, 
        F_WDATA_HWDATA01(16) => \VCC\, F_WDATA_HWDATA01(15) => 
        \VCC\, F_WDATA_HWDATA01(14) => \VCC\, 
        F_WDATA_HWDATA01(13) => \VCC\, F_WDATA_HWDATA01(12) => 
        \VCC\, F_WDATA_HWDATA01(11) => \VCC\, 
        F_WDATA_HWDATA01(10) => \VCC\, F_WDATA_HWDATA01(9) => 
        \VCC\, F_WDATA_HWDATA01(8) => \VCC\, F_WDATA_HWDATA01(7)
         => \VCC\, F_WDATA_HWDATA01(6) => \VCC\, 
        F_WDATA_HWDATA01(5) => \VCC\, F_WDATA_HWDATA01(4) => 
        \VCC\, F_WDATA_HWDATA01(3) => \VCC\, F_WDATA_HWDATA01(2)
         => \VCC\, F_WDATA_HWDATA01(1) => \VCC\, 
        F_WDATA_HWDATA01(0) => \VCC\, F_WID_HREADY01(3) => \GND\, 
        F_WID_HREADY01(2) => \GND\, F_WID_HREADY01(1) => \GND\, 
        F_WID_HREADY01(0) => \GND\, F_WLAST => \GND\, F_WSTRB(7)
         => \GND\, F_WSTRB(6) => \GND\, F_WSTRB(5) => \GND\, 
        F_WSTRB(4) => \GND\, F_WSTRB(3) => \GND\, F_WSTRB(2) => 
        \GND\, F_WSTRB(1) => \GND\, F_WSTRB(0) => \GND\, F_WVALID
         => \GND\, FPGA_MDDR_ARESET_N => \VCC\, 
        MDDR_FABRIC_PADDR(10) => \VCC\, MDDR_FABRIC_PADDR(9) => 
        \VCC\, MDDR_FABRIC_PADDR(8) => \VCC\, 
        MDDR_FABRIC_PADDR(7) => \VCC\, MDDR_FABRIC_PADDR(6) => 
        \VCC\, MDDR_FABRIC_PADDR(5) => \VCC\, 
        MDDR_FABRIC_PADDR(4) => \VCC\, MDDR_FABRIC_PADDR(3) => 
        \VCC\, MDDR_FABRIC_PADDR(2) => \VCC\, MDDR_FABRIC_PENABLE
         => \VCC\, MDDR_FABRIC_PSEL => \VCC\, 
        MDDR_FABRIC_PWDATA(15) => \VCC\, MDDR_FABRIC_PWDATA(14)
         => \VCC\, MDDR_FABRIC_PWDATA(13) => \VCC\, 
        MDDR_FABRIC_PWDATA(12) => \VCC\, MDDR_FABRIC_PWDATA(11)
         => \VCC\, MDDR_FABRIC_PWDATA(10) => \VCC\, 
        MDDR_FABRIC_PWDATA(9) => \VCC\, MDDR_FABRIC_PWDATA(8) => 
        \VCC\, MDDR_FABRIC_PWDATA(7) => \VCC\, 
        MDDR_FABRIC_PWDATA(6) => \VCC\, MDDR_FABRIC_PWDATA(5) => 
        \VCC\, MDDR_FABRIC_PWDATA(4) => \VCC\, 
        MDDR_FABRIC_PWDATA(3) => \VCC\, MDDR_FABRIC_PWDATA(2) => 
        \VCC\, MDDR_FABRIC_PWDATA(1) => \VCC\, 
        MDDR_FABRIC_PWDATA(0) => \VCC\, MDDR_FABRIC_PWRITE => 
        \VCC\, PRESET_N => \GND\, CAN_RXBUS_USBA_DATA1_MGPIO3A_IN
         => \GND\, CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN => \GND\, 
        CAN_TXBUS_USBA_DATA0_MGPIO2A_IN => \GND\, DM_IN(2) => 
        \GND\, DM_IN(1) => \GND\, DM_IN(0) => \GND\, 
        DRAM_DQ_IN(17) => \GND\, DRAM_DQ_IN(16) => \GND\, 
        DRAM_DQ_IN(15) => \GND\, DRAM_DQ_IN(14) => \GND\, 
        DRAM_DQ_IN(13) => \GND\, DRAM_DQ_IN(12) => \GND\, 
        DRAM_DQ_IN(11) => \GND\, DRAM_DQ_IN(10) => \GND\, 
        DRAM_DQ_IN(9) => \GND\, DRAM_DQ_IN(8) => \GND\, 
        DRAM_DQ_IN(7) => \GND\, DRAM_DQ_IN(6) => \GND\, 
        DRAM_DQ_IN(5) => \GND\, DRAM_DQ_IN(4) => \GND\, 
        DRAM_DQ_IN(3) => \GND\, DRAM_DQ_IN(2) => \GND\, 
        DRAM_DQ_IN(1) => \GND\, DRAM_DQ_IN(0) => \GND\, 
        DRAM_DQS_IN(2) => \GND\, DRAM_DQS_IN(1) => \GND\, 
        DRAM_DQS_IN(0) => \GND\, DRAM_FIFO_WE_IN(1) => \GND\, 
        DRAM_FIFO_WE_IN(0) => \GND\, 
        I2C0_SCL_USBC_DATA1_MGPIO31B_IN => \GND\, 
        I2C0_SDA_USBC_DATA0_MGPIO30B_IN => \GND\, 
        I2C1_SCL_USBA_DATA4_MGPIO1A_IN => \GND\, 
        I2C1_SDA_USBA_DATA3_MGPIO0A_IN => \GND\, 
        MMUART0_CTS_USBC_DATA7_MGPIO19B_IN => \GND\, 
        MMUART0_DCD_MGPIO22B_IN => \GND\, MMUART0_DSR_MGPIO20B_IN
         => \GND\, MMUART0_DTR_USBC_DATA6_MGPIO18B_IN => \GND\, 
        MMUART0_RI_MGPIO21B_IN => \GND\, 
        MMUART0_RTS_USBC_DATA5_MGPIO17B_IN => \GND\, 
        MMUART0_RXD_USBC_STP_MGPIO28B_IN => \GND\, 
        MMUART0_SCK_USBC_NXT_MGPIO29B_IN => \GND\, 
        MMUART0_TXD_USBC_DIR_MGPIO27B_IN => \GND\, 
        MMUART1_RXD_USBC_DATA3_MGPIO26B_IN => \GND\, 
        MMUART1_SCK_USBC_DATA4_MGPIO25B_IN => \GND\, 
        MMUART1_TXD_USBC_DATA2_MGPIO24B_IN => \GND\, 
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN => 
        USB_ULPI_XCLK_PAD_Y, RGMII_MDC_RMII_MDC_IN => \GND\, 
        RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN => 
        USB_ULPI_DATA_7_PAD_Y, RGMII_RX_CLK_IN => \GND\, 
        RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN => 
        USB_ULPI_DATA_2_PAD_Y, RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN
         => USB_ULPI_DATA_0_PAD_Y, 
        RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN => 
        USB_ULPI_DATA_1_PAD_Y, 
        RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN => 
        USB_ULPI_DATA_3_PAD_Y, RGMII_RXD3_USBB_DATA4_IN => 
        USB_ULPI_DATA_4_PAD_Y, RGMII_TX_CLK_IN => \GND\, 
        RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN => USB_ULPI_NXT_PAD_Y, 
        RGMII_TXD0_RMII_TXD0_USBB_DIR_IN => USB_ULPI_DIR_PAD_Y, 
        RGMII_TXD1_RMII_TXD1_USBB_STP_IN => \GND\, 
        RGMII_TXD2_USBB_DATA5_IN => USB_ULPI_DATA_5_PAD_Y, 
        RGMII_TXD3_USBB_DATA6_IN => USB_ULPI_DATA_6_PAD_Y, 
        SPI0_SCK_USBA_XCLK_IN => \GND\, 
        SPI0_SDI_USBA_DIR_MGPIO5A_IN => \GND\, 
        SPI0_SDO_USBA_STP_MGPIO6A_IN => \GND\, 
        SPI0_SS0_USBA_NXT_MGPIO7A_IN => \GND\, 
        SPI0_SS1_USBA_DATA5_MGPIO8A_IN => \GND\, 
        SPI0_SS2_USBA_DATA6_MGPIO9A_IN => \GND\, 
        SPI0_SS3_USBA_DATA7_MGPIO10A_IN => \GND\, SPI1_SCK_IN => 
        \GND\, SPI1_SDI_MGPIO11A_IN => \GND\, 
        SPI1_SDO_MGPIO12A_IN => \GND\, SPI1_SS0_MGPIO13A_IN => 
        \GND\, SPI1_SS1_MGPIO14A_IN => \GND\, 
        SPI1_SS2_MGPIO15A_IN => \GND\, SPI1_SS3_MGPIO16A_IN => 
        \GND\, SPI1_SS4_MGPIO17A_IN => \GND\, 
        SPI1_SS5_MGPIO18A_IN => \GND\, SPI1_SS6_MGPIO23A_IN => 
        \GND\, SPI1_SS7_MGPIO24A_IN => \GND\, USBC_XCLK_IN => 
        \GND\, CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT => 
        CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT, 
        CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT => 
        CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT, 
        CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT => 
        CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT, DRAM_ADDR(15) => 
        DRAM_ADDR(15), DRAM_ADDR(14) => DRAM_ADDR(14), 
        DRAM_ADDR(13) => DRAM_ADDR(13), DRAM_ADDR(12) => 
        DRAM_ADDR(12), DRAM_ADDR(11) => DRAM_ADDR(11), 
        DRAM_ADDR(10) => DRAM_ADDR(10), DRAM_ADDR(9) => 
        DRAM_ADDR(9), DRAM_ADDR(8) => DRAM_ADDR(8), DRAM_ADDR(7)
         => DRAM_ADDR(7), DRAM_ADDR(6) => DRAM_ADDR(6), 
        DRAM_ADDR(5) => DRAM_ADDR(5), DRAM_ADDR(4) => 
        DRAM_ADDR(4), DRAM_ADDR(3) => DRAM_ADDR(3), DRAM_ADDR(2)
         => DRAM_ADDR(2), DRAM_ADDR(1) => DRAM_ADDR(1), 
        DRAM_ADDR(0) => DRAM_ADDR(0), DRAM_BA(2) => DRAM_BA(2), 
        DRAM_BA(1) => DRAM_BA(1), DRAM_BA(0) => DRAM_BA(0), 
        DRAM_CASN => DRAM_CASN, DRAM_CKE => DRAM_CKE, DRAM_CLK
         => DRAM_CLK, DRAM_CSN => DRAM_CSN, DRAM_DM_RDQS_OUT(2)
         => DRAM_DM_RDQS_OUT(2), DRAM_DM_RDQS_OUT(1) => 
        DRAM_DM_RDQS_OUT(1), DRAM_DM_RDQS_OUT(0) => 
        DRAM_DM_RDQS_OUT(0), DRAM_DQ_OUT(17) => DRAM_DQ_OUT(17), 
        DRAM_DQ_OUT(16) => DRAM_DQ_OUT(16), DRAM_DQ_OUT(15) => 
        DRAM_DQ_OUT(15), DRAM_DQ_OUT(14) => DRAM_DQ_OUT(14), 
        DRAM_DQ_OUT(13) => DRAM_DQ_OUT(13), DRAM_DQ_OUT(12) => 
        DRAM_DQ_OUT(12), DRAM_DQ_OUT(11) => DRAM_DQ_OUT(11), 
        DRAM_DQ_OUT(10) => DRAM_DQ_OUT(10), DRAM_DQ_OUT(9) => 
        DRAM_DQ_OUT(9), DRAM_DQ_OUT(8) => DRAM_DQ_OUT(8), 
        DRAM_DQ_OUT(7) => DRAM_DQ_OUT(7), DRAM_DQ_OUT(6) => 
        DRAM_DQ_OUT(6), DRAM_DQ_OUT(5) => DRAM_DQ_OUT(5), 
        DRAM_DQ_OUT(4) => DRAM_DQ_OUT(4), DRAM_DQ_OUT(3) => 
        DRAM_DQ_OUT(3), DRAM_DQ_OUT(2) => DRAM_DQ_OUT(2), 
        DRAM_DQ_OUT(1) => DRAM_DQ_OUT(1), DRAM_DQ_OUT(0) => 
        DRAM_DQ_OUT(0), DRAM_DQS_OUT(2) => DRAM_DQS_OUT(2), 
        DRAM_DQS_OUT(1) => DRAM_DQS_OUT(1), DRAM_DQS_OUT(0) => 
        DRAM_DQS_OUT(0), DRAM_FIFO_WE_OUT(1) => 
        DRAM_FIFO_WE_OUT(1), DRAM_FIFO_WE_OUT(0) => 
        DRAM_FIFO_WE_OUT(0), DRAM_ODT => DRAM_ODT, DRAM_RASN => 
        DRAM_RASN, DRAM_RSTN => DRAM_RSTN, DRAM_WEN => DRAM_WEN, 
        I2C0_SCL_USBC_DATA1_MGPIO31B_OUT => 
        I2C0_SCL_USBC_DATA1_MGPIO31B_OUT, 
        I2C0_SDA_USBC_DATA0_MGPIO30B_OUT => 
        I2C0_SDA_USBC_DATA0_MGPIO30B_OUT, 
        I2C1_SCL_USBA_DATA4_MGPIO1A_OUT => 
        I2C1_SCL_USBA_DATA4_MGPIO1A_OUT, 
        I2C1_SDA_USBA_DATA3_MGPIO0A_OUT => 
        I2C1_SDA_USBA_DATA3_MGPIO0A_OUT, 
        MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT => 
        MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT, 
        MMUART0_DCD_MGPIO22B_OUT => MMUART0_DCD_MGPIO22B_OUT, 
        MMUART0_DSR_MGPIO20B_OUT => MMUART0_DSR_MGPIO20B_OUT, 
        MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT => 
        MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT, 
        MMUART0_RI_MGPIO21B_OUT => MMUART0_RI_MGPIO21B_OUT, 
        MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT => 
        MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT, 
        MMUART0_RXD_USBC_STP_MGPIO28B_OUT => 
        MMUART0_RXD_USBC_STP_MGPIO28B_OUT, 
        MMUART0_SCK_USBC_NXT_MGPIO29B_OUT => 
        MMUART0_SCK_USBC_NXT_MGPIO29B_OUT, 
        MMUART0_TXD_USBC_DIR_MGPIO27B_OUT => 
        MMUART0_TXD_USBC_DIR_MGPIO27B_OUT, 
        MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT => 
        MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT, 
        MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT => 
        MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT, 
        MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT => 
        MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT, 
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT => 
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT, 
        RGMII_MDC_RMII_MDC_OUT => RGMII_MDC_RMII_MDC_OUT, 
        RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT => 
        MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT, 
        RGMII_RX_CLK_OUT => RGMII_RX_CLK_OUT, 
        RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT => 
        MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT, 
        RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT => 
        MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT, 
        RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT => 
        MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT, 
        RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT => 
        MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT, 
        RGMII_RXD3_USBB_DATA4_OUT => 
        MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OUT, 
        RGMII_TX_CLK_OUT => RGMII_TX_CLK_OUT, 
        RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT => 
        RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT, 
        RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT => 
        RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT, 
        RGMII_TXD1_RMII_TXD1_USBB_STP_OUT => 
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OUT, 
        RGMII_TXD2_USBB_DATA5_OUT => 
        MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OUT, 
        RGMII_TXD3_USBB_DATA6_OUT => 
        MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OUT, 
        SPI0_SCK_USBA_XCLK_OUT => SPI0_SCK_USBA_XCLK_OUT, 
        SPI0_SDI_USBA_DIR_MGPIO5A_OUT => 
        SPI0_SDI_USBA_DIR_MGPIO5A_OUT, 
        SPI0_SDO_USBA_STP_MGPIO6A_OUT => 
        SPI0_SDO_USBA_STP_MGPIO6A_OUT, 
        SPI0_SS0_USBA_NXT_MGPIO7A_OUT => 
        SPI0_SS0_USBA_NXT_MGPIO7A_OUT, 
        SPI0_SS1_USBA_DATA5_MGPIO8A_OUT => 
        SPI0_SS1_USBA_DATA5_MGPIO8A_OUT, 
        SPI0_SS2_USBA_DATA6_MGPIO9A_OUT => 
        SPI0_SS2_USBA_DATA6_MGPIO9A_OUT, 
        SPI0_SS3_USBA_DATA7_MGPIO10A_OUT => 
        SPI0_SS3_USBA_DATA7_MGPIO10A_OUT, SPI1_SCK_OUT => 
        SPI1_SCK_OUT, SPI1_SDI_MGPIO11A_OUT => 
        SPI1_SDI_MGPIO11A_OUT, SPI1_SDO_MGPIO12A_OUT => 
        SPI1_SDO_MGPIO12A_OUT, SPI1_SS0_MGPIO13A_OUT => 
        SPI1_SS0_MGPIO13A_OUT, SPI1_SS1_MGPIO14A_OUT => 
        SPI1_SS1_MGPIO14A_OUT, SPI1_SS2_MGPIO15A_OUT => 
        SPI1_SS2_MGPIO15A_OUT, SPI1_SS3_MGPIO16A_OUT => 
        SPI1_SS3_MGPIO16A_OUT, SPI1_SS4_MGPIO17A_OUT => 
        SPI1_SS4_MGPIO17A_OUT, SPI1_SS5_MGPIO18A_OUT => 
        SPI1_SS5_MGPIO18A_OUT, SPI1_SS6_MGPIO23A_OUT => 
        SPI1_SS6_MGPIO23A_OUT, SPI1_SS7_MGPIO24A_OUT => 
        SPI1_SS7_MGPIO24A_OUT, USBC_XCLK_OUT => USBC_XCLK_OUT, 
        CAN_RXBUS_USBA_DATA1_MGPIO3A_OE => 
        CAN_RXBUS_USBA_DATA1_MGPIO3A_OE, 
        CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE => 
        CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE, 
        CAN_TXBUS_USBA_DATA0_MGPIO2A_OE => 
        CAN_TXBUS_USBA_DATA0_MGPIO2A_OE, DM_OE(2) => DM_OE(2), 
        DM_OE(1) => DM_OE(1), DM_OE(0) => DM_OE(0), 
        DRAM_DQ_OE(17) => DRAM_DQ_OE(17), DRAM_DQ_OE(16) => 
        DRAM_DQ_OE(16), DRAM_DQ_OE(15) => DRAM_DQ_OE(15), 
        DRAM_DQ_OE(14) => DRAM_DQ_OE(14), DRAM_DQ_OE(13) => 
        DRAM_DQ_OE(13), DRAM_DQ_OE(12) => DRAM_DQ_OE(12), 
        DRAM_DQ_OE(11) => DRAM_DQ_OE(11), DRAM_DQ_OE(10) => 
        DRAM_DQ_OE(10), DRAM_DQ_OE(9) => DRAM_DQ_OE(9), 
        DRAM_DQ_OE(8) => DRAM_DQ_OE(8), DRAM_DQ_OE(7) => 
        DRAM_DQ_OE(7), DRAM_DQ_OE(6) => DRAM_DQ_OE(6), 
        DRAM_DQ_OE(5) => DRAM_DQ_OE(5), DRAM_DQ_OE(4) => 
        DRAM_DQ_OE(4), DRAM_DQ_OE(3) => DRAM_DQ_OE(3), 
        DRAM_DQ_OE(2) => DRAM_DQ_OE(2), DRAM_DQ_OE(1) => 
        DRAM_DQ_OE(1), DRAM_DQ_OE(0) => DRAM_DQ_OE(0), 
        DRAM_DQS_OE(2) => DRAM_DQS_OE(2), DRAM_DQS_OE(1) => 
        DRAM_DQS_OE(1), DRAM_DQS_OE(0) => DRAM_DQS_OE(0), 
        I2C0_SCL_USBC_DATA1_MGPIO31B_OE => 
        I2C0_SCL_USBC_DATA1_MGPIO31B_OE, 
        I2C0_SDA_USBC_DATA0_MGPIO30B_OE => 
        I2C0_SDA_USBC_DATA0_MGPIO30B_OE, 
        I2C1_SCL_USBA_DATA4_MGPIO1A_OE => 
        I2C1_SCL_USBA_DATA4_MGPIO1A_OE, 
        I2C1_SDA_USBA_DATA3_MGPIO0A_OE => 
        I2C1_SDA_USBA_DATA3_MGPIO0A_OE, 
        MMUART0_CTS_USBC_DATA7_MGPIO19B_OE => 
        MMUART0_CTS_USBC_DATA7_MGPIO19B_OE, 
        MMUART0_DCD_MGPIO22B_OE => MMUART0_DCD_MGPIO22B_OE, 
        MMUART0_DSR_MGPIO20B_OE => MMUART0_DSR_MGPIO20B_OE, 
        MMUART0_DTR_USBC_DATA6_MGPIO18B_OE => 
        MMUART0_DTR_USBC_DATA6_MGPIO18B_OE, 
        MMUART0_RI_MGPIO21B_OE => MMUART0_RI_MGPIO21B_OE, 
        MMUART0_RTS_USBC_DATA5_MGPIO17B_OE => 
        MMUART0_RTS_USBC_DATA5_MGPIO17B_OE, 
        MMUART0_RXD_USBC_STP_MGPIO28B_OE => 
        MMUART0_RXD_USBC_STP_MGPIO28B_OE, 
        MMUART0_SCK_USBC_NXT_MGPIO29B_OE => 
        MMUART0_SCK_USBC_NXT_MGPIO29B_OE, 
        MMUART0_TXD_USBC_DIR_MGPIO27B_OE => 
        MMUART0_TXD_USBC_DIR_MGPIO27B_OE, 
        MMUART1_RXD_USBC_DATA3_MGPIO26B_OE => 
        MMUART1_RXD_USBC_DATA3_MGPIO26B_OE, 
        MMUART1_SCK_USBC_DATA4_MGPIO25B_OE => 
        MMUART1_SCK_USBC_DATA4_MGPIO25B_OE, 
        MMUART1_TXD_USBC_DATA2_MGPIO24B_OE => 
        MMUART1_TXD_USBC_DATA2_MGPIO24B_OE, 
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE => 
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE, 
        RGMII_MDC_RMII_MDC_OE => RGMII_MDC_RMII_MDC_OE, 
        RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE => 
        MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE, 
        RGMII_RX_CLK_OE => RGMII_RX_CLK_OE, 
        RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE => 
        MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE, 
        RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE => 
        MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE, 
        RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE => 
        MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE, 
        RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE => 
        MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE, 
        RGMII_RXD3_USBB_DATA4_OE => 
        MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OE, RGMII_TX_CLK_OE
         => RGMII_TX_CLK_OE, RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE
         => RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE, 
        RGMII_TXD0_RMII_TXD0_USBB_DIR_OE => 
        RGMII_TXD0_RMII_TXD0_USBB_DIR_OE, 
        RGMII_TXD1_RMII_TXD1_USBB_STP_OE => 
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OE, 
        RGMII_TXD2_USBB_DATA5_OE => 
        MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OE, 
        RGMII_TXD3_USBB_DATA6_OE => 
        MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OE, 
        SPI0_SCK_USBA_XCLK_OE => SPI0_SCK_USBA_XCLK_OE, 
        SPI0_SDI_USBA_DIR_MGPIO5A_OE => 
        SPI0_SDI_USBA_DIR_MGPIO5A_OE, 
        SPI0_SDO_USBA_STP_MGPIO6A_OE => 
        SPI0_SDO_USBA_STP_MGPIO6A_OE, 
        SPI0_SS0_USBA_NXT_MGPIO7A_OE => 
        SPI0_SS0_USBA_NXT_MGPIO7A_OE, 
        SPI0_SS1_USBA_DATA5_MGPIO8A_OE => 
        SPI0_SS1_USBA_DATA5_MGPIO8A_OE, 
        SPI0_SS2_USBA_DATA6_MGPIO9A_OE => 
        SPI0_SS2_USBA_DATA6_MGPIO9A_OE, 
        SPI0_SS3_USBA_DATA7_MGPIO10A_OE => 
        SPI0_SS3_USBA_DATA7_MGPIO10A_OE, SPI1_SCK_OE => 
        SPI1_SCK_OE, SPI1_SDI_MGPIO11A_OE => SPI1_SDI_MGPIO11A_OE, 
        SPI1_SDO_MGPIO12A_OE => SPI1_SDO_MGPIO12A_OE, 
        SPI1_SS0_MGPIO13A_OE => SPI1_SS0_MGPIO13A_OE, 
        SPI1_SS1_MGPIO14A_OE => SPI1_SS1_MGPIO14A_OE, 
        SPI1_SS2_MGPIO15A_OE => SPI1_SS2_MGPIO15A_OE, 
        SPI1_SS3_MGPIO16A_OE => SPI1_SS3_MGPIO16A_OE, 
        SPI1_SS4_MGPIO17A_OE => SPI1_SS4_MGPIO17A_OE, 
        SPI1_SS5_MGPIO18A_OE => SPI1_SS5_MGPIO18A_OE, 
        SPI1_SS6_MGPIO23A_OE => SPI1_SS6_MGPIO23A_OE, 
        SPI1_SS7_MGPIO24A_OE => SPI1_SS7_MGPIO24A_OE, 
        USBC_XCLK_OE => USBC_XCLK_OE);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity MC_System_sb is

    port( prdata_o_1_iv_0_0_6               : in    std_logic;
          prdata_o_1_iv_0_0_0               : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_4       : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_6       : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_1       : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_0       : in    std_logic;
          prdata_o_1_iv_0_0_a3_2_0          : in    std_logic_vector(9 to 9);
          prdata_o_1_iv_0_0_a1              : in    std_logic_vector(6 downto 5);
          prdata_o_1_iv_0_12                : in    std_logic_vector(5 to 5);
          OLMNG_0_theta_o_1                 : in    std_logic;
          OLMNG_0_theta_o_4                 : in    std_logic;
          OLMNG_0_theta_o_0                 : in    std_logic;
          OLMNG_0_theta_o_6                 : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_1 : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_4 : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_0 : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_6 : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_1 : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_4 : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_0 : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_6 : in    std_logic;
          prdata_o_1_iv_0_16_0              : in    std_logic;
          prdata_o_1_iv_0_16_5              : in    std_logic;
          prdata_o_1_iv_0_14_0              : in    std_logic;
          prdata_o_1_iv_0_14_5              : in    std_logic;
          prdata_o_1_0_iv_0_11              : in    std_logic_vector(16 to 16);
          prdata_o_1_0_iv_0_5               : in    std_logic_vector(16 to 16);
          prdata_o_1_0_iv_0_3               : in    std_logic_vector(16 to 16);
          prdata_o_1_0_iv_0_4               : in    std_logic_vector(16 to 16);
          FOC_TRANSFORMS_0_iq_o_0           : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_3           : in    std_logic;
          prdata_o_1_iv_0_0_13              : in    std_logic_vector(7 to 7);
          prdata_o_1_iv_0_0_5               : in    std_logic_vector(7 to 7);
          FOC_TRANSFORMS_0_id_o             : in    std_logic_vector(4 to 4);
          adc_interface_0_result_ch1_o      : in    std_logic_vector(4 to 4);
          prdata_o_1_iv_0_0_7               : in    std_logic_vector(10 to 10);
          prdata_o_1_iv_0_8                 : in    std_logic_vector(5 to 5);
          prdata_o_1_iv_0_7                 : in    std_logic_vector(5 to 5);
          prdata_o_1_iv_0_9                 : in    std_logic_vector(5 to 5);
          prdata_o_1_iv_0_6                 : in    std_logic_vector(5 to 5);
          prdata_o_1_0_iv_0_0_8             : in    std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_0_7             : in    std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_0_11_a2         : in    std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_0_11_a0         : in    std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_0_6             : in    std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_9               : in    std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_8               : in    std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_7_0             : in    std_logic;
          prdata_o_1_0_iv_0_7_9             : in    std_logic;
          prdata_o_1_0_iv_0_11_a2           : in    std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_11_a0           : in    std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_6_3             : in    std_logic;
          prdata_o_1_0_iv_0_6_0             : in    std_logic;
          prdata_o_1_0_iv_0_0_14            : in    std_logic_vector(3 to 3);
          MC_System_0_AMBA_SLAVE_0_PRDATA   : in    std_logic_vector(19 to 19);
          prdata_o_0_5                      : in    std_logic_vector(17 to 17);
          prdata_o_0_3                      : in    std_logic_vector(17 to 17);
          prdata_o_1_0_iv_0_1               : in    std_logic_vector(17 to 17);
          prdata_o_1_iv_0_0_16              : in    std_logic_vector(9 downto 8);
          prdata_o_1_iv_0_0_15              : in    std_logic_vector(8 to 8);
          prdata_o_1_iv_0_0_14              : in    std_logic_vector(10 downto 8);
          prdata_o_1_0_iv_0_16              : in    std_logic_vector(2 downto 0);
          prdata_o_1_0_iv_0_15_4            : in    std_logic;
          prdata_o_1_0_iv_0_15_0            : in    std_logic;
          prdata_o_1_0_iv_0_15_1            : in    std_logic;
          prdata_o_1_0_iv_0_15_2            : in    std_logic;
          prdata_o_1_0_iv_0_14_4            : in    std_logic;
          prdata_o_1_0_iv_0_14_0            : in    std_logic;
          prdata_o_1_0_iv_0_14_1            : in    std_logic;
          prdata_o_1_0_iv_0_14_2            : in    std_logic;
          prdata_o_1_iv_0_0_12_0            : in    std_logic;
          prdata_o_1_iv_0_0_12_3            : in    std_logic;
          prdata_o_1_iv_0_0_12_5            : in    std_logic;
          prdata_o_1_iv_0_0_11_0            : in    std_logic;
          prdata_o_1_iv_0_0_11_2            : in    std_logic;
          prdata_o_1_iv_0_0_10_0            : in    std_logic;
          prdata_o_1_iv_0_0_10_2            : in    std_logic;
          prdata_o_1_0_iv_0_0_10_0          : in    std_logic;
          prdata_o_1_0_iv_0_0_10_12         : in    std_logic;
          prdata_o_1_0_iv_0_0_11            : in    std_logic_vector(15 to 15);
          prdata_o_1_0_iv_0_0_9_11          : in    std_logic;
          prdata_o_1_0_iv_0_0_9_0           : in    std_logic;
          prdata_o_1_0_iv_0_0_9_12          : in    std_logic;
          USB_ULPI_DATA                     : inout std_logic_vector(7 downto 0) := (others => 'Z');
          MC_System_0_AMBA_SLAVE_0_PADDR    : inout std_logic_vector(11 downto 0) := (others => 'Z');
          MC_System_0_AMBA_SLAVE_0_PWDATA   : out   std_logic_vector(17 downto 0);
          MC_System_0_FIC_0_LOCK            : out   std_logic;
          MC_System_0_FIC_0_CLK             : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PSELx    : out   std_logic;
          N_737                             : in    std_logic;
          N_730                             : in    std_logic;
          prdata_o276                       : in    std_logic;
          N_358                             : in    std_logic;
          N_705                             : in    std_logic;
          prdata_o_1_iv_0_0_a3_0_out        : in    std_logic;
          prdata_m1_e_8_1                   : in    std_logic;
          prdata_m1_e_12_1                  : in    std_logic;
          prdata_o_1_iv_0_0_a3_9_out        : in    std_logic;
          N_734                             : in    std_logic;
          N_634                             : in    std_logic;
          N_449                             : in    std_logic;
          N_442                             : in    std_logic;
          N_440                             : in    std_logic;
          prdata_N_5_mux_6                  : in    std_logic;
          prdata_m1_e_4_1                   : in    std_logic;
          prdata_N_5_mux_7                  : in    std_logic;
          N_759                             : in    std_logic;
          prdata_o_1_iv_0_0_a3_27_out       : in    std_logic;
          G_15_1                            : in    std_logic;
          N_748                             : in    std_logic;
          N_462                             : in    std_logic;
          USB_ULPI_XCLK                     : in    std_logic;
          USB_ULPI_STP                      : out   std_logic;
          USB_ULPI_NXT                      : in    std_logic;
          USB_ULPI_DIR                      : in    std_logic;
          N_745                             : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PENABLE  : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PWRITE   : out   std_logic;
          GPIO_0_M2F_c                      : out   std_logic
        );

end MC_System_sb;

architecture DEF_ARCH of MC_System_sb is 

  component MC_System_sb_FABOSC_0_OSC
    port( FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC : out   std_logic
        );
  end component;

  component CoreAPB3
    port( MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR     : in    std_logic_vector(15 downto 12) := (others => 'U');
          MC_System_0_AMBA_SLAVE_0_PADDR                    : in    std_logic_vector(2 to 2) := (others => 'U');
          prdata_o_1_iv_0_0_6                               : in    std_logic := 'U';
          prdata_o_1_iv_0_0_0                               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_4                       : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_6                       : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_1                       : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_0                       : in    std_logic := 'U';
          prdata_o_1_iv_0_0_a3_2_0                          : in    std_logic_vector(9 to 9) := (others => 'U');
          prdata_o_1_iv_0_0_a1                              : in    std_logic_vector(6 downto 5) := (others => 'U');
          prdata_o_1_iv_0_12                                : in    std_logic_vector(5 to 5) := (others => 'U');
          OLMNG_0_theta_o_1                                 : in    std_logic := 'U';
          OLMNG_0_theta_o_4                                 : in    std_logic := 'U';
          OLMNG_0_theta_o_0                                 : in    std_logic := 'U';
          OLMNG_0_theta_o_6                                 : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_1                 : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_4                 : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_0                 : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_6                 : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_1                 : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_4                 : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_0                 : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_6                 : in    std_logic := 'U';
          prdata_o_1_iv_0_16_0                              : in    std_logic := 'U';
          prdata_o_1_iv_0_16_5                              : in    std_logic := 'U';
          prdata_o_1_iv_0_14_0                              : in    std_logic := 'U';
          prdata_o_1_iv_0_14_5                              : in    std_logic := 'U';
          prdata_o_1_0_iv_0_11                              : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_0_iv_0_5                               : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_0_iv_0_3                               : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_0_iv_0_4                               : in    std_logic_vector(16 to 16) := (others => 'U');
          FOC_TRANSFORMS_0_iq_o_0                           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_3                           : in    std_logic := 'U';
          prdata_o_1_iv_0_0_13                              : in    std_logic_vector(7 to 7) := (others => 'U');
          prdata_o_1_iv_0_0_5                               : in    std_logic_vector(7 to 7) := (others => 'U');
          FOC_TRANSFORMS_0_id_o                             : in    std_logic_vector(4 to 4) := (others => 'U');
          adc_interface_0_result_ch1_o                      : in    std_logic_vector(4 to 4) := (others => 'U');
          prdata_o_1_iv_0_0_7                               : in    std_logic_vector(10 to 10) := (others => 'U');
          prdata_o_1_iv_0_8                                 : in    std_logic_vector(5 to 5) := (others => 'U');
          prdata_o_1_iv_0_7                                 : in    std_logic_vector(5 to 5) := (others => 'U');
          prdata_o_1_iv_0_9                                 : in    std_logic_vector(5 to 5) := (others => 'U');
          prdata_o_1_iv_0_6                                 : in    std_logic_vector(5 to 5) := (others => 'U');
          prdata_o_1_0_iv_0_0_8                             : in    std_logic_vector(14 to 14) := (others => 'U');
          prdata_o_1_0_iv_0_0_7                             : in    std_logic_vector(14 to 14) := (others => 'U');
          prdata_o_1_0_iv_0_0_11_a2                         : in    std_logic_vector(14 to 14) := (others => 'U');
          prdata_o_1_0_iv_0_0_11_a0                         : in    std_logic_vector(14 to 14) := (others => 'U');
          prdata_o_1_0_iv_0_0_6                             : in    std_logic_vector(14 to 14) := (others => 'U');
          prdata_o_1_0_iv_0_9                               : in    std_logic_vector(13 to 13) := (others => 'U');
          prdata_o_1_0_iv_0_8                               : in    std_logic_vector(13 to 13) := (others => 'U');
          prdata_o_1_0_iv_0_7_0                             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_7_9                             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_11_a2                           : in    std_logic_vector(13 to 13) := (others => 'U');
          prdata_o_1_0_iv_0_11_a0                           : in    std_logic_vector(13 to 13) := (others => 'U');
          prdata_o_1_0_iv_0_6_3                             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_6_0                             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_14                            : in    std_logic_vector(3 to 3) := (others => 'U');
          MC_System_0_AMBA_SLAVE_0_PRDATA                   : in    std_logic_vector(19 to 19) := (others => 'U');
          prdata_o_0_5                                      : in    std_logic_vector(17 to 17) := (others => 'U');
          prdata_o_0_3                                      : in    std_logic_vector(17 to 17) := (others => 'U');
          prdata_o_1_0_iv_0_1                               : in    std_logic_vector(17 to 17) := (others => 'U');
          prdata_o_1_iv_0_0_16                              : in    std_logic_vector(9 downto 8) := (others => 'U');
          prdata_o_1_iv_0_0_15                              : in    std_logic_vector(8 to 8) := (others => 'U');
          prdata_o_1_iv_0_0_14                              : in    std_logic_vector(10 downto 8) := (others => 'U');
          prdata_o_1_0_iv_0_16                              : in    std_logic_vector(2 downto 0) := (others => 'U');
          prdata_o_1_0_iv_0_15_4                            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_15_0                            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_15_1                            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_15_2                            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_14_4                            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_14_0                            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_14_1                            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_14_2                            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_12_0                            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_12_3                            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_12_5                            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_11_0                            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_11_2                            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_10_0                            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_10_2                            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_10_0                          : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_10_12                         : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_11                            : in    std_logic_vector(15 to 15) := (others => 'U');
          prdata_o_1_0_iv_0_0_9_11                          : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_9_0                           : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_9_12                          : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15 : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx     : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_0_PSELx                    : out   std_logic;
          N_737                                             : in    std_logic := 'U';
          N_730                                             : in    std_logic := 'U';
          prdata_o276                                       : in    std_logic := 'U';
          N_358                                             : in    std_logic := 'U';
          N_705                                             : in    std_logic := 'U';
          prdata_o_1_iv_0_0_a3_0_out                        : in    std_logic := 'U';
          prdata_m1_e_8_1                                   : in    std_logic := 'U';
          prdata_m1_e_12_1                                  : in    std_logic := 'U';
          prdata_o_1_iv_0_0_a3_9_out                        : in    std_logic := 'U';
          N_734                                             : in    std_logic := 'U';
          N_634                                             : in    std_logic := 'U';
          N_449                                             : in    std_logic := 'U';
          N_442                                             : in    std_logic := 'U';
          N_440                                             : in    std_logic := 'U';
          prdata_N_5_mux_6                                  : in    std_logic := 'U';
          prdata_m1_e_4_1                                   : in    std_logic := 'U';
          prdata_N_5_mux_7                                  : in    std_logic := 'U';
          N_759                                             : in    std_logic := 'U';
          prdata_o_1_iv_0_0_a3_27_out                       : in    std_logic := 'U';
          G_15_1                                            : in    std_logic := 'U';
          N_748                                             : in    std_logic := 'U';
          N_462                                             : in    std_logic := 'U'
        );
  end component;

  component MC_System_sb_CCC_0_FCCC
    port( MC_System_0_FIC_0_LOCK                             : out   std_logic;
          MC_System_0_FIC_0_CLK                              : out   std_logic;
          FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC : in    std_logic := 'U'
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component MC_System_sb_MSS
    port( USB_ULPI_DATA                                     : inout   std_logic_vector(7 downto 0);
          MC_System_0_AMBA_SLAVE_0_PADDR                    : inout   std_logic_vector(11 downto 0);
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR     : out   std_logic_vector(15 downto 12);
          MC_System_0_AMBA_SLAVE_0_PWDATA                   : out   std_logic_vector(17 downto 0);
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0  : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1  : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2  : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3  : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4  : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5  : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6  : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7  : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8  : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9  : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10 : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11 : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12 : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13 : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14 : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15 : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16 : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17 : in    std_logic := 'U';
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31 : in    std_logic := 'U';
          USB_ULPI_XCLK                                     : in    std_logic := 'U';
          USB_ULPI_STP                                      : out   std_logic;
          USB_ULPI_NXT                                      : in    std_logic := 'U';
          USB_ULPI_DIR                                      : in    std_logic := 'U';
          N_745                                             : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PENABLE                  : out   std_logic;
          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx     : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PWRITE                   : out   std_logic;
          GPIO_0_M2F_c                                      : out   std_logic;
          MC_System_0_FIC_0_LOCK                            : in    std_logic := 'U';
          MC_System_0_FIC_0_CLK                             : in    std_logic := 'U'
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \MC_System_0_FIC_0_LOCK\, \MC_System_0_FIC_0_CLK\
         : std_logic;
    signal MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR : 
        std_logic_vector(15 downto 12);
    signal MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA : 
        std_logic_vector(31 downto 0);
    signal FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx, \GND\, 
        \VCC\ : std_logic;

    for all : MC_System_sb_FABOSC_0_OSC
	Use entity work.MC_System_sb_FABOSC_0_OSC(DEF_ARCH);
    for all : CoreAPB3
	Use entity work.CoreAPB3(DEF_ARCH);
    for all : MC_System_sb_CCC_0_FCCC
	Use entity work.MC_System_sb_CCC_0_FCCC(DEF_ARCH);
    for all : MC_System_sb_MSS
	Use entity work.MC_System_sb_MSS(DEF_ARCH);
begin 

    MC_System_0_FIC_0_LOCK <= \MC_System_0_FIC_0_LOCK\;
    MC_System_0_FIC_0_CLK <= \MC_System_0_FIC_0_CLK\;

    FABOSC_0 : MC_System_sb_FABOSC_0_OSC
      port map(FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
         => FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC);
    
    CoreAPB3_0 : CoreAPB3
      port map(MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(15)
         => MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(15), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(14) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(14), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(13) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(13), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), 
        MC_System_0_AMBA_SLAVE_0_PADDR(2) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), prdata_o_1_iv_0_0_6
         => prdata_o_1_iv_0_0_6, prdata_o_1_iv_0_0_0 => 
        prdata_o_1_iv_0_0_0, FOC_TRANSFORMS_0_valpha_o_4 => 
        FOC_TRANSFORMS_0_valpha_o_4, FOC_TRANSFORMS_0_valpha_o_6
         => FOC_TRANSFORMS_0_valpha_o_6, 
        FOC_TRANSFORMS_0_valpha_o_1 => 
        FOC_TRANSFORMS_0_valpha_o_1, FOC_TRANSFORMS_0_valpha_o_0
         => FOC_TRANSFORMS_0_valpha_o_0, 
        prdata_o_1_iv_0_0_a3_2_0(9) => 
        prdata_o_1_iv_0_0_a3_2_0(9), prdata_o_1_iv_0_0_a1(6) => 
        prdata_o_1_iv_0_0_a1(6), prdata_o_1_iv_0_0_a1(5) => 
        prdata_o_1_iv_0_0_a1(5), prdata_o_1_iv_0_12(5) => 
        prdata_o_1_iv_0_12(5), OLMNG_0_theta_o_1 => 
        OLMNG_0_theta_o_1, OLMNG_0_theta_o_4 => OLMNG_0_theta_o_4, 
        OLMNG_0_theta_o_0 => OLMNG_0_theta_o_0, OLMNG_0_theta_o_6
         => OLMNG_0_theta_o_6, SPEED_ID_IQ_PI_0_id_pi_output_o_1
         => SPEED_ID_IQ_PI_0_id_pi_output_o_1, 
        SPEED_ID_IQ_PI_0_id_pi_output_o_4 => 
        SPEED_ID_IQ_PI_0_id_pi_output_o_4, 
        SPEED_ID_IQ_PI_0_id_pi_output_o_0 => 
        SPEED_ID_IQ_PI_0_id_pi_output_o_0, 
        SPEED_ID_IQ_PI_0_id_pi_output_o_6 => 
        SPEED_ID_IQ_PI_0_id_pi_output_o_6, 
        HALL_INTERFACE_1_theta_output_o_1 => 
        HALL_INTERFACE_1_theta_output_o_1, 
        HALL_INTERFACE_1_theta_output_o_4 => 
        HALL_INTERFACE_1_theta_output_o_4, 
        HALL_INTERFACE_1_theta_output_o_0 => 
        HALL_INTERFACE_1_theta_output_o_0, 
        HALL_INTERFACE_1_theta_output_o_6 => 
        HALL_INTERFACE_1_theta_output_o_6, prdata_o_1_iv_0_16_0
         => prdata_o_1_iv_0_16_0, prdata_o_1_iv_0_16_5 => 
        prdata_o_1_iv_0_16_5, prdata_o_1_iv_0_14_0 => 
        prdata_o_1_iv_0_14_0, prdata_o_1_iv_0_14_5 => 
        prdata_o_1_iv_0_14_5, prdata_o_1_0_iv_0_11(16) => 
        prdata_o_1_0_iv_0_11(16), prdata_o_1_0_iv_0_5(16) => 
        prdata_o_1_0_iv_0_5(16), prdata_o_1_0_iv_0_3(16) => 
        prdata_o_1_0_iv_0_3(16), prdata_o_1_0_iv_0_4(16) => 
        prdata_o_1_0_iv_0_4(16), FOC_TRANSFORMS_0_iq_o_0 => 
        FOC_TRANSFORMS_0_iq_o_0, FOC_TRANSFORMS_0_iq_o_3 => 
        FOC_TRANSFORMS_0_iq_o_3, prdata_o_1_iv_0_0_13(7) => 
        prdata_o_1_iv_0_0_13(7), prdata_o_1_iv_0_0_5(7) => 
        prdata_o_1_iv_0_0_5(7), FOC_TRANSFORMS_0_id_o(4) => 
        FOC_TRANSFORMS_0_id_o(4), adc_interface_0_result_ch1_o(4)
         => adc_interface_0_result_ch1_o(4), 
        prdata_o_1_iv_0_0_7(10) => prdata_o_1_iv_0_0_7(10), 
        prdata_o_1_iv_0_8(5) => prdata_o_1_iv_0_8(5), 
        prdata_o_1_iv_0_7(5) => prdata_o_1_iv_0_7(5), 
        prdata_o_1_iv_0_9(5) => prdata_o_1_iv_0_9(5), 
        prdata_o_1_iv_0_6(5) => prdata_o_1_iv_0_6(5), 
        prdata_o_1_0_iv_0_0_8(14) => prdata_o_1_0_iv_0_0_8(14), 
        prdata_o_1_0_iv_0_0_7(14) => prdata_o_1_0_iv_0_0_7(14), 
        prdata_o_1_0_iv_0_0_11_a2(14) => 
        prdata_o_1_0_iv_0_0_11_a2(14), 
        prdata_o_1_0_iv_0_0_11_a0(14) => 
        prdata_o_1_0_iv_0_0_11_a0(14), prdata_o_1_0_iv_0_0_6(14)
         => prdata_o_1_0_iv_0_0_6(14), prdata_o_1_0_iv_0_9(13)
         => prdata_o_1_0_iv_0_9(13), prdata_o_1_0_iv_0_8(13) => 
        prdata_o_1_0_iv_0_8(13), prdata_o_1_0_iv_0_7_0 => 
        prdata_o_1_0_iv_0_7_0, prdata_o_1_0_iv_0_7_9 => 
        prdata_o_1_0_iv_0_7_9, prdata_o_1_0_iv_0_11_a2(13) => 
        prdata_o_1_0_iv_0_11_a2(13), prdata_o_1_0_iv_0_11_a0(13)
         => prdata_o_1_0_iv_0_11_a0(13), prdata_o_1_0_iv_0_6_3
         => prdata_o_1_0_iv_0_6_3, prdata_o_1_0_iv_0_6_0 => 
        prdata_o_1_0_iv_0_6_0, prdata_o_1_0_iv_0_0_14(3) => 
        prdata_o_1_0_iv_0_0_14(3), 
        MC_System_0_AMBA_SLAVE_0_PRDATA(19) => 
        MC_System_0_AMBA_SLAVE_0_PRDATA(19), prdata_o_0_5(17) => 
        prdata_o_0_5(17), prdata_o_0_3(17) => prdata_o_0_3(17), 
        prdata_o_1_0_iv_0_1(17) => prdata_o_1_0_iv_0_1(17), 
        prdata_o_1_iv_0_0_16(9) => prdata_o_1_iv_0_0_16(9), 
        prdata_o_1_iv_0_0_16(8) => prdata_o_1_iv_0_0_16(8), 
        prdata_o_1_iv_0_0_15(8) => prdata_o_1_iv_0_0_15(8), 
        prdata_o_1_iv_0_0_14(10) => prdata_o_1_iv_0_0_14(10), 
        prdata_o_1_iv_0_0_14(9) => prdata_o_1_iv_0_0_14(9), 
        prdata_o_1_iv_0_0_14(8) => prdata_o_1_iv_0_0_14(8), 
        prdata_o_1_0_iv_0_16(2) => prdata_o_1_0_iv_0_16(2), 
        prdata_o_1_0_iv_0_16(1) => prdata_o_1_0_iv_0_16(1), 
        prdata_o_1_0_iv_0_16(0) => prdata_o_1_0_iv_0_16(0), 
        prdata_o_1_0_iv_0_15_4 => prdata_o_1_0_iv_0_15_4, 
        prdata_o_1_0_iv_0_15_0 => prdata_o_1_0_iv_0_15_0, 
        prdata_o_1_0_iv_0_15_1 => prdata_o_1_0_iv_0_15_1, 
        prdata_o_1_0_iv_0_15_2 => prdata_o_1_0_iv_0_15_2, 
        prdata_o_1_0_iv_0_14_4 => prdata_o_1_0_iv_0_14_4, 
        prdata_o_1_0_iv_0_14_0 => prdata_o_1_0_iv_0_14_0, 
        prdata_o_1_0_iv_0_14_1 => prdata_o_1_0_iv_0_14_1, 
        prdata_o_1_0_iv_0_14_2 => prdata_o_1_0_iv_0_14_2, 
        prdata_o_1_iv_0_0_12_0 => prdata_o_1_iv_0_0_12_0, 
        prdata_o_1_iv_0_0_12_3 => prdata_o_1_iv_0_0_12_3, 
        prdata_o_1_iv_0_0_12_5 => prdata_o_1_iv_0_0_12_5, 
        prdata_o_1_iv_0_0_11_0 => prdata_o_1_iv_0_0_11_0, 
        prdata_o_1_iv_0_0_11_2 => prdata_o_1_iv_0_0_11_2, 
        prdata_o_1_iv_0_0_10_0 => prdata_o_1_iv_0_0_10_0, 
        prdata_o_1_iv_0_0_10_2 => prdata_o_1_iv_0_0_10_2, 
        prdata_o_1_0_iv_0_0_10_0 => prdata_o_1_0_iv_0_0_10_0, 
        prdata_o_1_0_iv_0_0_10_12 => prdata_o_1_0_iv_0_0_10_12, 
        prdata_o_1_0_iv_0_0_11(15) => prdata_o_1_0_iv_0_0_11(15), 
        prdata_o_1_0_iv_0_0_9_11 => prdata_o_1_0_iv_0_0_9_11, 
        prdata_o_1_0_iv_0_0_9_0 => prdata_o_1_0_iv_0_0_9_0, 
        prdata_o_1_0_iv_0_0_9_12 => prdata_o_1_0_iv_0_0_9_12, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(5), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(6), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(11), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(16), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(9), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(7), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(4), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(10), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(14), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(13), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(3), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(31), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(17), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(8), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(0), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(1), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(2), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(12), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(15), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx, 
        MC_System_0_AMBA_SLAVE_0_PSELx => 
        MC_System_0_AMBA_SLAVE_0_PSELx, N_737 => N_737, N_730 => 
        N_730, prdata_o276 => prdata_o276, N_358 => N_358, N_705
         => N_705, prdata_o_1_iv_0_0_a3_0_out => 
        prdata_o_1_iv_0_0_a3_0_out, prdata_m1_e_8_1 => 
        prdata_m1_e_8_1, prdata_m1_e_12_1 => prdata_m1_e_12_1, 
        prdata_o_1_iv_0_0_a3_9_out => prdata_o_1_iv_0_0_a3_9_out, 
        N_734 => N_734, N_634 => N_634, N_449 => N_449, N_442 => 
        N_442, N_440 => N_440, prdata_N_5_mux_6 => 
        prdata_N_5_mux_6, prdata_m1_e_4_1 => prdata_m1_e_4_1, 
        prdata_N_5_mux_7 => prdata_N_5_mux_7, N_759 => N_759, 
        prdata_o_1_iv_0_0_a3_27_out => 
        prdata_o_1_iv_0_0_a3_27_out, G_15_1 => G_15_1, N_748 => 
        N_748, N_462 => N_462);
    
    CCC_0 : MC_System_sb_CCC_0_FCCC
      port map(MC_System_0_FIC_0_LOCK => \MC_System_0_FIC_0_LOCK\, 
        MC_System_0_FIC_0_CLK => \MC_System_0_FIC_0_CLK\, 
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC => 
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC);
    
    VCC_Z : VCC
      port map(Y => \VCC\);
    
    MC_System_sb_MSS_0 : MC_System_sb_MSS
      port map(USB_ULPI_DATA(7) => USB_ULPI_DATA(7), 
        USB_ULPI_DATA(6) => USB_ULPI_DATA(6), USB_ULPI_DATA(5)
         => USB_ULPI_DATA(5), USB_ULPI_DATA(4) => 
        USB_ULPI_DATA(4), USB_ULPI_DATA(3) => USB_ULPI_DATA(3), 
        USB_ULPI_DATA(2) => USB_ULPI_DATA(2), USB_ULPI_DATA(1)
         => USB_ULPI_DATA(1), USB_ULPI_DATA(0) => 
        USB_ULPI_DATA(0), MC_System_0_AMBA_SLAVE_0_PADDR(11) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(11), 
        MC_System_0_AMBA_SLAVE_0_PADDR(10) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(10), 
        MC_System_0_AMBA_SLAVE_0_PADDR(9) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(9), 
        MC_System_0_AMBA_SLAVE_0_PADDR(8) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(8), 
        MC_System_0_AMBA_SLAVE_0_PADDR(7) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(7), 
        MC_System_0_AMBA_SLAVE_0_PADDR(6) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(6), 
        MC_System_0_AMBA_SLAVE_0_PADDR(5) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), 
        MC_System_0_AMBA_SLAVE_0_PADDR(4) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), 
        MC_System_0_AMBA_SLAVE_0_PADDR(3) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), 
        MC_System_0_AMBA_SLAVE_0_PADDR(2) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), 
        MC_System_0_AMBA_SLAVE_0_PADDR(1) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(1), 
        MC_System_0_AMBA_SLAVE_0_PADDR(0) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(0), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(15) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(15), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(14) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(14), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(13) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(13), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12) => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR(12), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(17) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(17), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(16) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(16), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(15) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(15), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(14) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(14), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(13) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(13), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(12) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(12), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(11) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(11), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(10) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(10), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(9) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(9), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(8) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(8), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(7) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(7), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(6) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(6), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(5) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(5), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(4) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(4), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(3) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(3), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(2) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(2), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(1) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(1), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(0) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(0), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(0), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(1), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(2), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(3), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(4), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(5), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(6), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(7), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(8), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(9), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(10), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(11), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(12), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(13), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(14), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(15), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(16), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(17), 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31 => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA(31), 
        USB_ULPI_XCLK => USB_ULPI_XCLK, USB_ULPI_STP => 
        USB_ULPI_STP, USB_ULPI_NXT => USB_ULPI_NXT, USB_ULPI_DIR
         => USB_ULPI_DIR, N_745 => N_745, 
        MC_System_0_AMBA_SLAVE_0_PENABLE => 
        MC_System_0_AMBA_SLAVE_0_PENABLE, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx => 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx, 
        MC_System_0_AMBA_SLAVE_0_PWRITE => 
        MC_System_0_AMBA_SLAVE_0_PWRITE, GPIO_0_M2F_c => 
        GPIO_0_M2F_c, MC_System_0_FIC_0_LOCK => 
        \MC_System_0_FIC_0_LOCK\, MC_System_0_FIC_0_CLK => 
        \MC_System_0_FIC_0_CLK\);
    
    GND_Z : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity MC_System is

    port( prdata_o_1_iv_0_0_6               : in    std_logic;
          prdata_o_1_iv_0_0_0               : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_4       : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_6       : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_1       : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_0       : in    std_logic;
          prdata_o_1_iv_0_0_a3_2_0          : in    std_logic_vector(9 to 9);
          prdata_o_1_iv_0_0_a1              : in    std_logic_vector(6 downto 5);
          prdata_o_1_iv_0_12                : in    std_logic_vector(5 to 5);
          OLMNG_0_theta_o_1                 : in    std_logic;
          OLMNG_0_theta_o_4                 : in    std_logic;
          OLMNG_0_theta_o_0                 : in    std_logic;
          OLMNG_0_theta_o_6                 : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_1 : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_4 : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_0 : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_6 : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_1 : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_4 : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_0 : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_6 : in    std_logic;
          prdata_o_1_iv_0_16_0              : in    std_logic;
          prdata_o_1_iv_0_16_5              : in    std_logic;
          prdata_o_1_iv_0_14_0              : in    std_logic;
          prdata_o_1_iv_0_14_5              : in    std_logic;
          prdata_o_1_0_iv_0_11              : in    std_logic_vector(16 to 16);
          prdata_o_1_0_iv_0_5               : in    std_logic_vector(16 to 16);
          prdata_o_1_0_iv_0_3               : in    std_logic_vector(16 to 16);
          prdata_o_1_0_iv_0_4               : in    std_logic_vector(16 to 16);
          FOC_TRANSFORMS_0_iq_o_0           : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_3           : in    std_logic;
          prdata_o_1_iv_0_0_13              : in    std_logic_vector(7 to 7);
          prdata_o_1_iv_0_0_5               : in    std_logic_vector(7 to 7);
          FOC_TRANSFORMS_0_id_o             : in    std_logic_vector(4 to 4);
          adc_interface_0_result_ch1_o      : in    std_logic_vector(4 to 4);
          prdata_o_1_iv_0_0_7               : in    std_logic_vector(10 to 10);
          prdata_o_1_iv_0_8                 : in    std_logic_vector(5 to 5);
          prdata_o_1_iv_0_7                 : in    std_logic_vector(5 to 5);
          prdata_o_1_iv_0_9                 : in    std_logic_vector(5 to 5);
          prdata_o_1_iv_0_6                 : in    std_logic_vector(5 to 5);
          prdata_o_1_0_iv_0_0_8             : in    std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_0_7             : in    std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_0_11_a2         : in    std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_0_11_a0         : in    std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_0_6             : in    std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_9               : in    std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_8               : in    std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_7_0             : in    std_logic;
          prdata_o_1_0_iv_0_7_9             : in    std_logic;
          prdata_o_1_0_iv_0_11_a2           : in    std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_11_a0           : in    std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_6_3             : in    std_logic;
          prdata_o_1_0_iv_0_6_0             : in    std_logic;
          prdata_o_1_0_iv_0_0_14            : in    std_logic_vector(3 to 3);
          MC_System_0_AMBA_SLAVE_0_PRDATA   : in    std_logic_vector(19 to 19);
          prdata_o_0_5                      : in    std_logic_vector(17 to 17);
          prdata_o_0_3                      : in    std_logic_vector(17 to 17);
          prdata_o_1_0_iv_0_1               : in    std_logic_vector(17 to 17);
          prdata_o_1_iv_0_0_16              : in    std_logic_vector(9 downto 8);
          prdata_o_1_iv_0_0_15              : in    std_logic_vector(8 to 8);
          prdata_o_1_iv_0_0_14              : in    std_logic_vector(10 downto 8);
          prdata_o_1_0_iv_0_16              : in    std_logic_vector(2 downto 0);
          prdata_o_1_0_iv_0_15_4            : in    std_logic;
          prdata_o_1_0_iv_0_15_0            : in    std_logic;
          prdata_o_1_0_iv_0_15_1            : in    std_logic;
          prdata_o_1_0_iv_0_15_2            : in    std_logic;
          prdata_o_1_0_iv_0_14_4            : in    std_logic;
          prdata_o_1_0_iv_0_14_0            : in    std_logic;
          prdata_o_1_0_iv_0_14_1            : in    std_logic;
          prdata_o_1_0_iv_0_14_2            : in    std_logic;
          prdata_o_1_iv_0_0_12_0            : in    std_logic;
          prdata_o_1_iv_0_0_12_3            : in    std_logic;
          prdata_o_1_iv_0_0_12_5            : in    std_logic;
          prdata_o_1_iv_0_0_11_0            : in    std_logic;
          prdata_o_1_iv_0_0_11_2            : in    std_logic;
          prdata_o_1_iv_0_0_10_0            : in    std_logic;
          prdata_o_1_iv_0_0_10_2            : in    std_logic;
          prdata_o_1_0_iv_0_0_10_0          : in    std_logic;
          prdata_o_1_0_iv_0_0_10_12         : in    std_logic;
          prdata_o_1_0_iv_0_0_11            : in    std_logic_vector(15 to 15);
          prdata_o_1_0_iv_0_0_9_11          : in    std_logic;
          prdata_o_1_0_iv_0_0_9_0           : in    std_logic;
          prdata_o_1_0_iv_0_0_9_12          : in    std_logic;
          USB_ULPI_DATA                     : inout std_logic_vector(7 downto 0) := (others => 'Z');
          MC_System_0_AMBA_SLAVE_0_PADDR    : inout std_logic_vector(11 downto 0) := (others => 'Z');
          MC_System_0_AMBA_SLAVE_0_PWDATA   : out   std_logic_vector(17 downto 0);
          MC_System_0_FIC_0_LOCK            : out   std_logic;
          MC_System_0_FIC_0_CLK             : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PSELx    : out   std_logic;
          N_737                             : in    std_logic;
          N_730                             : in    std_logic;
          prdata_o276                       : in    std_logic;
          N_358                             : in    std_logic;
          N_705                             : in    std_logic;
          prdata_o_1_iv_0_0_a3_0_out        : in    std_logic;
          prdata_m1_e_8_1                   : in    std_logic;
          prdata_m1_e_12_1                  : in    std_logic;
          prdata_o_1_iv_0_0_a3_9_out        : in    std_logic;
          N_734                             : in    std_logic;
          N_634                             : in    std_logic;
          N_449                             : in    std_logic;
          N_442                             : in    std_logic;
          N_440                             : in    std_logic;
          prdata_N_5_mux_6                  : in    std_logic;
          prdata_m1_e_4_1                   : in    std_logic;
          prdata_N_5_mux_7                  : in    std_logic;
          N_759                             : in    std_logic;
          prdata_o_1_iv_0_0_a3_27_out       : in    std_logic;
          G_15_1                            : in    std_logic;
          N_748                             : in    std_logic;
          N_462                             : in    std_logic;
          USB_ULPI_XCLK                     : in    std_logic;
          USB_ULPI_STP                      : out   std_logic;
          USB_ULPI_NXT                      : in    std_logic;
          USB_ULPI_DIR                      : in    std_logic;
          N_745                             : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PENABLE  : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PWRITE   : out   std_logic;
          GPIO_0_M2F_c                      : out   std_logic
        );

end MC_System;

architecture DEF_ARCH of MC_System is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component MC_System_sb
    port( prdata_o_1_iv_0_0_6               : in    std_logic := 'U';
          prdata_o_1_iv_0_0_0               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_4       : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_6       : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_1       : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_0       : in    std_logic := 'U';
          prdata_o_1_iv_0_0_a3_2_0          : in    std_logic_vector(9 to 9) := (others => 'U');
          prdata_o_1_iv_0_0_a1              : in    std_logic_vector(6 downto 5) := (others => 'U');
          prdata_o_1_iv_0_12                : in    std_logic_vector(5 to 5) := (others => 'U');
          OLMNG_0_theta_o_1                 : in    std_logic := 'U';
          OLMNG_0_theta_o_4                 : in    std_logic := 'U';
          OLMNG_0_theta_o_0                 : in    std_logic := 'U';
          OLMNG_0_theta_o_6                 : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_1 : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_4 : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_0 : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_6 : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_1 : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_4 : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_0 : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_6 : in    std_logic := 'U';
          prdata_o_1_iv_0_16_0              : in    std_logic := 'U';
          prdata_o_1_iv_0_16_5              : in    std_logic := 'U';
          prdata_o_1_iv_0_14_0              : in    std_logic := 'U';
          prdata_o_1_iv_0_14_5              : in    std_logic := 'U';
          prdata_o_1_0_iv_0_11              : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_0_iv_0_5               : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_0_iv_0_3               : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_0_iv_0_4               : in    std_logic_vector(16 to 16) := (others => 'U');
          FOC_TRANSFORMS_0_iq_o_0           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_3           : in    std_logic := 'U';
          prdata_o_1_iv_0_0_13              : in    std_logic_vector(7 to 7) := (others => 'U');
          prdata_o_1_iv_0_0_5               : in    std_logic_vector(7 to 7) := (others => 'U');
          FOC_TRANSFORMS_0_id_o             : in    std_logic_vector(4 to 4) := (others => 'U');
          adc_interface_0_result_ch1_o      : in    std_logic_vector(4 to 4) := (others => 'U');
          prdata_o_1_iv_0_0_7               : in    std_logic_vector(10 to 10) := (others => 'U');
          prdata_o_1_iv_0_8                 : in    std_logic_vector(5 to 5) := (others => 'U');
          prdata_o_1_iv_0_7                 : in    std_logic_vector(5 to 5) := (others => 'U');
          prdata_o_1_iv_0_9                 : in    std_logic_vector(5 to 5) := (others => 'U');
          prdata_o_1_iv_0_6                 : in    std_logic_vector(5 to 5) := (others => 'U');
          prdata_o_1_0_iv_0_0_8             : in    std_logic_vector(14 to 14) := (others => 'U');
          prdata_o_1_0_iv_0_0_7             : in    std_logic_vector(14 to 14) := (others => 'U');
          prdata_o_1_0_iv_0_0_11_a2         : in    std_logic_vector(14 to 14) := (others => 'U');
          prdata_o_1_0_iv_0_0_11_a0         : in    std_logic_vector(14 to 14) := (others => 'U');
          prdata_o_1_0_iv_0_0_6             : in    std_logic_vector(14 to 14) := (others => 'U');
          prdata_o_1_0_iv_0_9               : in    std_logic_vector(13 to 13) := (others => 'U');
          prdata_o_1_0_iv_0_8               : in    std_logic_vector(13 to 13) := (others => 'U');
          prdata_o_1_0_iv_0_7_0             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_7_9             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_11_a2           : in    std_logic_vector(13 to 13) := (others => 'U');
          prdata_o_1_0_iv_0_11_a0           : in    std_logic_vector(13 to 13) := (others => 'U');
          prdata_o_1_0_iv_0_6_3             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_6_0             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_14            : in    std_logic_vector(3 to 3) := (others => 'U');
          MC_System_0_AMBA_SLAVE_0_PRDATA   : in    std_logic_vector(19 to 19) := (others => 'U');
          prdata_o_0_5                      : in    std_logic_vector(17 to 17) := (others => 'U');
          prdata_o_0_3                      : in    std_logic_vector(17 to 17) := (others => 'U');
          prdata_o_1_0_iv_0_1               : in    std_logic_vector(17 to 17) := (others => 'U');
          prdata_o_1_iv_0_0_16              : in    std_logic_vector(9 downto 8) := (others => 'U');
          prdata_o_1_iv_0_0_15              : in    std_logic_vector(8 to 8) := (others => 'U');
          prdata_o_1_iv_0_0_14              : in    std_logic_vector(10 downto 8) := (others => 'U');
          prdata_o_1_0_iv_0_16              : in    std_logic_vector(2 downto 0) := (others => 'U');
          prdata_o_1_0_iv_0_15_4            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_15_0            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_15_1            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_15_2            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_14_4            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_14_0            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_14_1            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_14_2            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_12_0            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_12_3            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_12_5            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_11_0            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_11_2            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_10_0            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_10_2            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_10_0          : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_10_12         : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_11            : in    std_logic_vector(15 to 15) := (others => 'U');
          prdata_o_1_0_iv_0_0_9_11          : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_9_0           : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_9_12          : in    std_logic := 'U';
          USB_ULPI_DATA                     : inout   std_logic_vector(7 downto 0);
          MC_System_0_AMBA_SLAVE_0_PADDR    : inout   std_logic_vector(11 downto 0);
          MC_System_0_AMBA_SLAVE_0_PWDATA   : out   std_logic_vector(17 downto 0);
          MC_System_0_FIC_0_LOCK            : out   std_logic;
          MC_System_0_FIC_0_CLK             : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PSELx    : out   std_logic;
          N_737                             : in    std_logic := 'U';
          N_730                             : in    std_logic := 'U';
          prdata_o276                       : in    std_logic := 'U';
          N_358                             : in    std_logic := 'U';
          N_705                             : in    std_logic := 'U';
          prdata_o_1_iv_0_0_a3_0_out        : in    std_logic := 'U';
          prdata_m1_e_8_1                   : in    std_logic := 'U';
          prdata_m1_e_12_1                  : in    std_logic := 'U';
          prdata_o_1_iv_0_0_a3_9_out        : in    std_logic := 'U';
          N_734                             : in    std_logic := 'U';
          N_634                             : in    std_logic := 'U';
          N_449                             : in    std_logic := 'U';
          N_442                             : in    std_logic := 'U';
          N_440                             : in    std_logic := 'U';
          prdata_N_5_mux_6                  : in    std_logic := 'U';
          prdata_m1_e_4_1                   : in    std_logic := 'U';
          prdata_N_5_mux_7                  : in    std_logic := 'U';
          N_759                             : in    std_logic := 'U';
          prdata_o_1_iv_0_0_a3_27_out       : in    std_logic := 'U';
          G_15_1                            : in    std_logic := 'U';
          N_748                             : in    std_logic := 'U';
          N_462                             : in    std_logic := 'U';
          USB_ULPI_XCLK                     : in    std_logic := 'U';
          USB_ULPI_STP                      : out   std_logic;
          USB_ULPI_NXT                      : in    std_logic := 'U';
          USB_ULPI_DIR                      : in    std_logic := 'U';
          N_745                             : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PENABLE  : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PWRITE   : out   std_logic;
          GPIO_0_M2F_c                      : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \GND\, \VCC\ : std_logic;

    for all : MC_System_sb
	Use entity work.MC_System_sb(DEF_ARCH);
begin 


    VCC_Z : VCC
      port map(Y => \VCC\);
    
    MC_System_sb_0 : MC_System_sb
      port map(prdata_o_1_iv_0_0_6 => prdata_o_1_iv_0_0_6, 
        prdata_o_1_iv_0_0_0 => prdata_o_1_iv_0_0_0, 
        FOC_TRANSFORMS_0_valpha_o_4 => 
        FOC_TRANSFORMS_0_valpha_o_4, FOC_TRANSFORMS_0_valpha_o_6
         => FOC_TRANSFORMS_0_valpha_o_6, 
        FOC_TRANSFORMS_0_valpha_o_1 => 
        FOC_TRANSFORMS_0_valpha_o_1, FOC_TRANSFORMS_0_valpha_o_0
         => FOC_TRANSFORMS_0_valpha_o_0, 
        prdata_o_1_iv_0_0_a3_2_0(9) => 
        prdata_o_1_iv_0_0_a3_2_0(9), prdata_o_1_iv_0_0_a1(6) => 
        prdata_o_1_iv_0_0_a1(6), prdata_o_1_iv_0_0_a1(5) => 
        prdata_o_1_iv_0_0_a1(5), prdata_o_1_iv_0_12(5) => 
        prdata_o_1_iv_0_12(5), OLMNG_0_theta_o_1 => 
        OLMNG_0_theta_o_1, OLMNG_0_theta_o_4 => OLMNG_0_theta_o_4, 
        OLMNG_0_theta_o_0 => OLMNG_0_theta_o_0, OLMNG_0_theta_o_6
         => OLMNG_0_theta_o_6, SPEED_ID_IQ_PI_0_id_pi_output_o_1
         => SPEED_ID_IQ_PI_0_id_pi_output_o_1, 
        SPEED_ID_IQ_PI_0_id_pi_output_o_4 => 
        SPEED_ID_IQ_PI_0_id_pi_output_o_4, 
        SPEED_ID_IQ_PI_0_id_pi_output_o_0 => 
        SPEED_ID_IQ_PI_0_id_pi_output_o_0, 
        SPEED_ID_IQ_PI_0_id_pi_output_o_6 => 
        SPEED_ID_IQ_PI_0_id_pi_output_o_6, 
        HALL_INTERFACE_1_theta_output_o_1 => 
        HALL_INTERFACE_1_theta_output_o_1, 
        HALL_INTERFACE_1_theta_output_o_4 => 
        HALL_INTERFACE_1_theta_output_o_4, 
        HALL_INTERFACE_1_theta_output_o_0 => 
        HALL_INTERFACE_1_theta_output_o_0, 
        HALL_INTERFACE_1_theta_output_o_6 => 
        HALL_INTERFACE_1_theta_output_o_6, prdata_o_1_iv_0_16_0
         => prdata_o_1_iv_0_16_0, prdata_o_1_iv_0_16_5 => 
        prdata_o_1_iv_0_16_5, prdata_o_1_iv_0_14_0 => 
        prdata_o_1_iv_0_14_0, prdata_o_1_iv_0_14_5 => 
        prdata_o_1_iv_0_14_5, prdata_o_1_0_iv_0_11(16) => 
        prdata_o_1_0_iv_0_11(16), prdata_o_1_0_iv_0_5(16) => 
        prdata_o_1_0_iv_0_5(16), prdata_o_1_0_iv_0_3(16) => 
        prdata_o_1_0_iv_0_3(16), prdata_o_1_0_iv_0_4(16) => 
        prdata_o_1_0_iv_0_4(16), FOC_TRANSFORMS_0_iq_o_0 => 
        FOC_TRANSFORMS_0_iq_o_0, FOC_TRANSFORMS_0_iq_o_3 => 
        FOC_TRANSFORMS_0_iq_o_3, prdata_o_1_iv_0_0_13(7) => 
        prdata_o_1_iv_0_0_13(7), prdata_o_1_iv_0_0_5(7) => 
        prdata_o_1_iv_0_0_5(7), FOC_TRANSFORMS_0_id_o(4) => 
        FOC_TRANSFORMS_0_id_o(4), adc_interface_0_result_ch1_o(4)
         => adc_interface_0_result_ch1_o(4), 
        prdata_o_1_iv_0_0_7(10) => prdata_o_1_iv_0_0_7(10), 
        prdata_o_1_iv_0_8(5) => prdata_o_1_iv_0_8(5), 
        prdata_o_1_iv_0_7(5) => prdata_o_1_iv_0_7(5), 
        prdata_o_1_iv_0_9(5) => prdata_o_1_iv_0_9(5), 
        prdata_o_1_iv_0_6(5) => prdata_o_1_iv_0_6(5), 
        prdata_o_1_0_iv_0_0_8(14) => prdata_o_1_0_iv_0_0_8(14), 
        prdata_o_1_0_iv_0_0_7(14) => prdata_o_1_0_iv_0_0_7(14), 
        prdata_o_1_0_iv_0_0_11_a2(14) => 
        prdata_o_1_0_iv_0_0_11_a2(14), 
        prdata_o_1_0_iv_0_0_11_a0(14) => 
        prdata_o_1_0_iv_0_0_11_a0(14), prdata_o_1_0_iv_0_0_6(14)
         => prdata_o_1_0_iv_0_0_6(14), prdata_o_1_0_iv_0_9(13)
         => prdata_o_1_0_iv_0_9(13), prdata_o_1_0_iv_0_8(13) => 
        prdata_o_1_0_iv_0_8(13), prdata_o_1_0_iv_0_7_0 => 
        prdata_o_1_0_iv_0_7_0, prdata_o_1_0_iv_0_7_9 => 
        prdata_o_1_0_iv_0_7_9, prdata_o_1_0_iv_0_11_a2(13) => 
        prdata_o_1_0_iv_0_11_a2(13), prdata_o_1_0_iv_0_11_a0(13)
         => prdata_o_1_0_iv_0_11_a0(13), prdata_o_1_0_iv_0_6_3
         => prdata_o_1_0_iv_0_6_3, prdata_o_1_0_iv_0_6_0 => 
        prdata_o_1_0_iv_0_6_0, prdata_o_1_0_iv_0_0_14(3) => 
        prdata_o_1_0_iv_0_0_14(3), 
        MC_System_0_AMBA_SLAVE_0_PRDATA(19) => 
        MC_System_0_AMBA_SLAVE_0_PRDATA(19), prdata_o_0_5(17) => 
        prdata_o_0_5(17), prdata_o_0_3(17) => prdata_o_0_3(17), 
        prdata_o_1_0_iv_0_1(17) => prdata_o_1_0_iv_0_1(17), 
        prdata_o_1_iv_0_0_16(9) => prdata_o_1_iv_0_0_16(9), 
        prdata_o_1_iv_0_0_16(8) => prdata_o_1_iv_0_0_16(8), 
        prdata_o_1_iv_0_0_15(8) => prdata_o_1_iv_0_0_15(8), 
        prdata_o_1_iv_0_0_14(10) => prdata_o_1_iv_0_0_14(10), 
        prdata_o_1_iv_0_0_14(9) => prdata_o_1_iv_0_0_14(9), 
        prdata_o_1_iv_0_0_14(8) => prdata_o_1_iv_0_0_14(8), 
        prdata_o_1_0_iv_0_16(2) => prdata_o_1_0_iv_0_16(2), 
        prdata_o_1_0_iv_0_16(1) => prdata_o_1_0_iv_0_16(1), 
        prdata_o_1_0_iv_0_16(0) => prdata_o_1_0_iv_0_16(0), 
        prdata_o_1_0_iv_0_15_4 => prdata_o_1_0_iv_0_15_4, 
        prdata_o_1_0_iv_0_15_0 => prdata_o_1_0_iv_0_15_0, 
        prdata_o_1_0_iv_0_15_1 => prdata_o_1_0_iv_0_15_1, 
        prdata_o_1_0_iv_0_15_2 => prdata_o_1_0_iv_0_15_2, 
        prdata_o_1_0_iv_0_14_4 => prdata_o_1_0_iv_0_14_4, 
        prdata_o_1_0_iv_0_14_0 => prdata_o_1_0_iv_0_14_0, 
        prdata_o_1_0_iv_0_14_1 => prdata_o_1_0_iv_0_14_1, 
        prdata_o_1_0_iv_0_14_2 => prdata_o_1_0_iv_0_14_2, 
        prdata_o_1_iv_0_0_12_0 => prdata_o_1_iv_0_0_12_0, 
        prdata_o_1_iv_0_0_12_3 => prdata_o_1_iv_0_0_12_3, 
        prdata_o_1_iv_0_0_12_5 => prdata_o_1_iv_0_0_12_5, 
        prdata_o_1_iv_0_0_11_0 => prdata_o_1_iv_0_0_11_0, 
        prdata_o_1_iv_0_0_11_2 => prdata_o_1_iv_0_0_11_2, 
        prdata_o_1_iv_0_0_10_0 => prdata_o_1_iv_0_0_10_0, 
        prdata_o_1_iv_0_0_10_2 => prdata_o_1_iv_0_0_10_2, 
        prdata_o_1_0_iv_0_0_10_0 => prdata_o_1_0_iv_0_0_10_0, 
        prdata_o_1_0_iv_0_0_10_12 => prdata_o_1_0_iv_0_0_10_12, 
        prdata_o_1_0_iv_0_0_11(15) => prdata_o_1_0_iv_0_0_11(15), 
        prdata_o_1_0_iv_0_0_9_11 => prdata_o_1_0_iv_0_0_9_11, 
        prdata_o_1_0_iv_0_0_9_0 => prdata_o_1_0_iv_0_0_9_0, 
        prdata_o_1_0_iv_0_0_9_12 => prdata_o_1_0_iv_0_0_9_12, 
        USB_ULPI_DATA(7) => USB_ULPI_DATA(7), USB_ULPI_DATA(6)
         => USB_ULPI_DATA(6), USB_ULPI_DATA(5) => 
        USB_ULPI_DATA(5), USB_ULPI_DATA(4) => USB_ULPI_DATA(4), 
        USB_ULPI_DATA(3) => USB_ULPI_DATA(3), USB_ULPI_DATA(2)
         => USB_ULPI_DATA(2), USB_ULPI_DATA(1) => 
        USB_ULPI_DATA(1), USB_ULPI_DATA(0) => USB_ULPI_DATA(0), 
        MC_System_0_AMBA_SLAVE_0_PADDR(11) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(11), 
        MC_System_0_AMBA_SLAVE_0_PADDR(10) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(10), 
        MC_System_0_AMBA_SLAVE_0_PADDR(9) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(9), 
        MC_System_0_AMBA_SLAVE_0_PADDR(8) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(8), 
        MC_System_0_AMBA_SLAVE_0_PADDR(7) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(7), 
        MC_System_0_AMBA_SLAVE_0_PADDR(6) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(6), 
        MC_System_0_AMBA_SLAVE_0_PADDR(5) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), 
        MC_System_0_AMBA_SLAVE_0_PADDR(4) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), 
        MC_System_0_AMBA_SLAVE_0_PADDR(3) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), 
        MC_System_0_AMBA_SLAVE_0_PADDR(2) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), 
        MC_System_0_AMBA_SLAVE_0_PADDR(1) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(1), 
        MC_System_0_AMBA_SLAVE_0_PADDR(0) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(0), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(17) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(17), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(16) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(16), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(15) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(15), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(14) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(14), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(13) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(13), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(12) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(12), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(11) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(11), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(10) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(10), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(9) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(9), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(8) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(8), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(7) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(7), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(6) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(6), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(5) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(5), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(4) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(4), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(3) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(3), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(2) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(2), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(1) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(1), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(0) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(0), 
        MC_System_0_FIC_0_LOCK => MC_System_0_FIC_0_LOCK, 
        MC_System_0_FIC_0_CLK => MC_System_0_FIC_0_CLK, 
        MC_System_0_AMBA_SLAVE_0_PSELx => 
        MC_System_0_AMBA_SLAVE_0_PSELx, N_737 => N_737, N_730 => 
        N_730, prdata_o276 => prdata_o276, N_358 => N_358, N_705
         => N_705, prdata_o_1_iv_0_0_a3_0_out => 
        prdata_o_1_iv_0_0_a3_0_out, prdata_m1_e_8_1 => 
        prdata_m1_e_8_1, prdata_m1_e_12_1 => prdata_m1_e_12_1, 
        prdata_o_1_iv_0_0_a3_9_out => prdata_o_1_iv_0_0_a3_9_out, 
        N_734 => N_734, N_634 => N_634, N_449 => N_449, N_442 => 
        N_442, N_440 => N_440, prdata_N_5_mux_6 => 
        prdata_N_5_mux_6, prdata_m1_e_4_1 => prdata_m1_e_4_1, 
        prdata_N_5_mux_7 => prdata_N_5_mux_7, N_759 => N_759, 
        prdata_o_1_iv_0_0_a3_27_out => 
        prdata_o_1_iv_0_0_a3_27_out, G_15_1 => G_15_1, N_748 => 
        N_748, N_462 => N_462, USB_ULPI_XCLK => USB_ULPI_XCLK, 
        USB_ULPI_STP => USB_ULPI_STP, USB_ULPI_NXT => 
        USB_ULPI_NXT, USB_ULPI_DIR => USB_ULPI_DIR, N_745 => 
        N_745, MC_System_0_AMBA_SLAVE_0_PENABLE => 
        MC_System_0_AMBA_SLAVE_0_PENABLE, 
        MC_System_0_AMBA_SLAVE_0_PWRITE => 
        MC_System_0_AMBA_SLAVE_0_PWRITE, GPIO_0_M2F_c => 
        GPIO_0_M2F_c);
    
    GND_Z : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity PWM3PH is

    port( reset_i        : in    std_logic;
          sys_clk_i      : in    std_logic;
          en_pwm_i       : in    std_logic;
          en_dual_trig_i : in    std_logic;
          va_i           : in    std_logic_vector(17 downto 0);
          vb_i           : in    std_logic_vector(17 downto 0);
          vc_i           : in    std_logic_vector(17 downto 0);
          pwm_period_i   : in    std_logic_vector(17 downto 0);
          dead_time_i    : in    std_logic_vector(17 downto 0);
          delay_time_i   : in    std_logic_vector(17 downto 0);
          midmatch_o     : out   std_logic;
          PWM_AH_o       : out   std_logic;
          PWM_BH_o       : out   std_logic;
          PWM_CH_o       : out   std_logic;
          PWM_AL_o       : out   std_logic;
          PWM_BL_o       : out   std_logic;
          PWM_CL_o       : out   std_logic
        );

end PWM3PH;

architecture DEF_ARCH of PWM3PH is 

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component CFG1
    generic (INIT:std_logic_vector(1 downto 0) := "00");

    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

    signal MSC_net_116 : std_logic;
    signal s_pwm_counter : std_logic_vector(16 downto 0);
    signal s_delay_counter : std_logic_vector(17 downto 0);
    signal \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4\ : 
        std_logic_vector(17 downto 1);
    signal \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_0_data_tmp\
         : std_logic_vector(8 downto 0);
    signal s_pwm_counter_cry : std_logic_vector(16 downto 0);
    signal s_pwm_counter_s : std_logic_vector(17 downto 0);
    signal s_delay_counter_s : std_logic_vector(17 downto 0);
    signal s_delay_counter_cry : std_logic_vector(16 downto 1);
    signal s_pwm_counter_Z : std_logic_vector(17 to 17);
    signal s_delay_counter_cry_Y : std_logic_vector(16 downto 1);
    signal s_delay_counter_s_FCO : std_logic_vector(17 to 17);
    signal s_delay_counter_s_Y : std_logic_vector(17 to 17);
    signal s_pwm_counter_cry_Y : std_logic_vector(16 downto 0);
    signal s_pwm_counter_s_FCO : std_logic_vector(17 to 17);
    signal s_pwm_counter_s_Y : std_logic_vector(17 to 17);
    signal MSC_net_285, MSC_net_286, MSC_net_287, MSC_net_288, 
        MSC_net_289, MSC_net_290, MSC_net_291, MSC_net_292, 
        MSC_net_293, MSC_net_294, MSC_net_295, MSC_net_296, 
        MSC_net_297, MSC_net_298, MSC_net_299, MSC_net_300, 
        MSC_net_301, MSC_net_302, MSC_net_303, MSC_net_304, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i\, 
        \PWM_OUTPUT_GEN_PROC.va_i\, \PWM_OUTPUT_GEN_PROC.vb_i\, 
        \PWM_OUTPUT_GEN_PROC.vc_i\, MSC_net_309, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2\, MSC_net_313, MSC_net_314, 
        MSC_net_315, MSC_net_316, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_0_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_1_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_2_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_3_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_4_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_5_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_6_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_7_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_8_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_9_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_10_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_11_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_12_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_13_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_14_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_15_Z\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_16_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_0_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_1_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_2_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_3_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_4_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_5_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_6_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_7_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_8_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_9_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_10_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_11_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_12_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_13_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_14_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_15_Z\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_16_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_0_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_1_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_2_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_3_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_4_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_5_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_6_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_7_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_8_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_9_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_10_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_11_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_12_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_13_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_14_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_15_Z\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_16_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_0_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_1_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_2_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_3_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_4_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_5_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_6_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_7_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_8_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_9_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_10_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_11_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_12_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_13_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_14_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_15_Z\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_16_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_0_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_1_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_2_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_3_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_4_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_5_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_6_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_7_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_8_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_9_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_10_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_11_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_12_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_13_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_14_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_15_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_16_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_0_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_1_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_2_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_3_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_4_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_5_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_6_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_7_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_8_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_9_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_10_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_11_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_12_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_13_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_14_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_15_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_16_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_0_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_1_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_2_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_3_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_4_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_5_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_6_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_7_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_8_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_9_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_10_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_11_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_12_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_13_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_14_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_15_Z\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_16_Z\, MSC_net_436, 
        MSC_net_437, MSC_net_438, MSC_net_439, MSC_net_440, 
        MSC_net_441, MSC_net_442, MSC_net_443, MSC_net_444, 
        MSC_net_445, MSC_net_446, MSC_net_447, MSC_net_448, 
        MSC_net_449, MSC_net_450, MSC_net_451, MSC_net_452, 
        MSC_net_453, MSC_net_454, MSC_net_455, MSC_net_456, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_0_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_1_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_2_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_3_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_4_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_5_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_6_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_7_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_8_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_9_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_10_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_11_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_12_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_13_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_14_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_15_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_16_Z\, 
        MSC_net_474, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un11_en_pwm_i_3_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un11_en_pwm_i_9_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un11_en_pwm_i_11_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un11_en_pwm_i_12_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un11_en_pwm_i_14_Z\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un11_en_pwm_i_15_Z\, 
        MSC_net_481, MSC_net_482, MSC_net_483, MSC_net_484, 
        MSC_net_485, MSC_net_486, MSC_net_487, MSC_net_488, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_s_17_RNIIS8A5_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_s_17_RNIIS8A5_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_14_RNIV2JH4_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_14_RNIV2JH4_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_12_RNIP1IO3_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_12_RNIP1IO3_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_10_RNIR4HV2_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_10_RNIR4HV2_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_8_RNI5CG62_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_8_RNI5CG62_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_6_RNIJ44P1_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_6_RNIJ44P1_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_4_RNI91OB1_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_4_RNI91OB1_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_2_RNI72CU_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_2_RNI72CU_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_1_RNID70H_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_1_RNID70H_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_17_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_17_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_16_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_16_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_15_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_15_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_14_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_14_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_13_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_13_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_12_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_12_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_11_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_11_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_10_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_10_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_9_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_9_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_8_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_8_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_7_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_7_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_6_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_6_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_5_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_5_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_4_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_4_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_3_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_3_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_2_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_2_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_1_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_1_Y\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_0_S\, 
        \PWM_MIDMATCH_GEN_PROC.un18_en_pwm_i_cry_0_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_17_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_17_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_16_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_16_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_15_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_15_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_14_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_14_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_13_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_13_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_12_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_12_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_11_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_11_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_10_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_10_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_9_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_9_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_8_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_8_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_7_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_7_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_6_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_6_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_5_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_5_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_4_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_4_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_3_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_3_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_2_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_2_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_1_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_1_Y\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_0_S\, 
        \PWM_OUTPUT_GEN_PROC.va_i_cry_0_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_17_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_17_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_16_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_16_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_15_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_15_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_14_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_14_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_13_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_13_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_12_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_12_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_11_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_11_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_10_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_10_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_9_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_9_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_8_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_8_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_7_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_7_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_6_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_6_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_5_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_5_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_4_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_4_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_3_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_3_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_2_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_2_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_1_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_1_Y\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_0_S\, 
        \PWM_OUTPUT_GEN_PROC.vb_i_cry_0_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_17_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_17_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_16_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_16_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_15_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_15_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_14_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_14_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_13_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_13_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_12_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_12_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_11_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_11_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_10_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_10_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_9_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_9_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_8_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_8_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_7_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_7_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_6_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_6_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_5_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_5_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_4_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_4_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_3_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_3_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_2_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_2_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_1_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_1_Y\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_0_S\, 
        \PWM_OUTPUT_GEN_PROC.vc_i_cry_0_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_17_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_17_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_16_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_16_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_15_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_15_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_14_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_14_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_13_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_13_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_12_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_12_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_11_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_11_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_10_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_10_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_9_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_9_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_8_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_8_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_7_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_7_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_6_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_6_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_5_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_5_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_4_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_4_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_3_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_3_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_2_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_2_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_1_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_1_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_0_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ah_o2_cry_0_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_17_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_17_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_16_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_16_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_15_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_15_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_14_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_14_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_13_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_13_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_12_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_12_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_11_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_11_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_10_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_10_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_9_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_9_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_8_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_8_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_7_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_7_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_6_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_6_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_5_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_5_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_4_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_4_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_3_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_3_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_2_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_2_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_1_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_1_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_0_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_bh_o2_cry_0_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_17_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_17_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_16_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_16_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_15_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_15_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_14_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_14_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_13_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_13_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_12_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_12_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_11_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_11_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_10_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_10_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_9_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_9_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_8_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_8_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_7_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_7_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_6_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_6_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_5_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_5_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_4_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_4_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_3_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_3_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_2_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_2_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_1_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_1_Y\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_0_S\, 
        \PWM_OUTPUT_GEN_PROC.pwm_ch_o2_cry_0_Y\, MSC_net_759, 
        MSC_net_760, MSC_net_761, MSC_net_762, MSC_net_763, 
        MSC_net_764, MSC_net_765, MSC_net_766, MSC_net_767, 
        MSC_net_768, MSC_net_769, MSC_net_770, MSC_net_771, 
        MSC_net_772, MSC_net_773, MSC_net_774, MSC_net_775, 
        MSC_net_776, MSC_net_777, MSC_net_778, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_16_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_s_17_FCO\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_s_17_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_15_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_14_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_13_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_12_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_11_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_10_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_9_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_8_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_7_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_6_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_5_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_4_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_3_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_2_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_1_Y\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_0_S\, 
        \PWM_MIDMATCH_GEN_PROC.op_eq.un6_en_pwm_i_a_4_cry_0_Y\, 
        MSC_net_799, MSC_net_800, MSC_net_801, MSC_net_802
         : std_logic;

begin 

    PWM_AL_o <= MSC_net_116;
    PWM_BL_o <= MSC_net_116;
    PWM_CL_o <= MSC_net_116;


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
bJzLqSrFKa1N0Ipd8ySaMM+UMHRH4PAfLZx3j5xfOCSiamV27cyRe7Z5mR0X0WbG
F89judugWK7wXw/II6RHIGepCGdz3yPXzGboB6ihmgDOTrgh022PpiWlc5UWfacb
0CsOrd8mquRtaK3vE0/hTM9WwrDLVnJqxf0RTbA7anc=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=132820)
`protect data_block
[encoded data, 130752 characters]
YN5JJR/KFVDv4V0ojlWOfA==

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity SVM is

    port( reset_i   : in    std_logic;
          sys_clk_i : in    std_logic;
          start_i   : in    std_logic;
          va_i      : in    std_logic_vector(17 downto 0);
          vb_i      : in    std_logic_vector(17 downto 0);
          vc_i      : in    std_logic_vector(17 downto 0);
          va3h_o    : out   std_logic_vector(17 downto 0);
          vb3h_o    : out   std_logic_vector(17 downto 0);
          vc3h_o    : out   std_logic_vector(17 downto 0);
          done_o    : out   std_logic
        );

end SVM;

architecture DEF_ARCH of SVM is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

    signal s_min_value : std_logic_vector(17 downto 1);
    signal s_max_value : std_logic_vector(17 downto 0);
    signal \SVM_FSM_PROC.s_max_value_3\ : 
        std_logic_vector(17 downto 0);
    signal \SVM_FSM_PROC.s_min_value_4\ : 
        std_logic_vector(17 downto 0);
    signal s_state : std_logic_vector(1 downto 0);
    signal s_state_ns : std_logic_vector(0 to 0);
    signal \SVM_FSM_PROC.vc3h_o_1\ : 
        std_logic_vector(17 downto 1);
    signal \SVM_FSM_PROC.va3h_o_2\ : 
        std_logic_vector(17 downto 1);
    signal \SVM_FSM_PROC.vb3h_o_1\ : 
        std_logic_vector(17 downto 1);
    signal \SVM_FSM_PROC.s_min_value_4_3_ns_1\ : 
        std_logic_vector(17 downto 0);
    signal \SVM_FSM_PROC.s_max_value_3_3_ns_1\ : 
        std_logic_vector(17 downto 0);
    signal MSC_net_273, MSC_net_274, MSC_net_275, MSC_net_276, 
        MSC_net_277, MSC_net_278, MSC_net_279, MSC_net_280, 
        MSC_net_281, MSC_net_282, MSC_net_283, MSC_net_284, 
        MSC_net_285, MSC_net_286, MSC_net_287, MSC_net_288, 
        MSC_net_289, MSC_net_290, MSC_net_291, MSC_net_292, 
        MSC_net_293, MSC_net_294, MSC_net_295, MSC_net_296, 
        MSC_net_297, MSC_net_298, MSC_net_299, MSC_net_300, 
        MSC_net_301, MSC_net_302, MSC_net_303, MSC_net_304, 
        MSC_net_305, MSC_net_306, MSC_net_307, MSC_net_308, 
        MSC_net_309, MSC_net_310, MSC_net_311, MSC_net_312, 
        MSC_net_313, MSC_net_314, MSC_net_315, MSC_net_316, 
        MSC_net_317, MSC_net_318, MSC_net_319, MSC_net_320, 
        MSC_net_321, MSC_net_322, MSC_net_323, MSC_net_324, 
        MSC_net_325, MSC_net_326, MSC_net_327, MSC_net_328, 
        MSC_net_329, MSC_net_330, MSC_net_331, MSC_net_332, 
        MSC_net_333, MSC_net_334, MSC_net_335, MSC_net_336, 
        MSC_net_337, MSC_net_338, MSC_net_339, MSC_net_340, 
        MSC_net_341, MSC_net_342, MSC_net_343, MSC_net_344, 
        MSC_net_345, MSC_net_346, MSC_net_347, MSC_net_348, 
        MSC_net_349, \SVM_FSM_PROC.vc3h_o_1_cry_0_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_1_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_2_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_3_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_4_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_5_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_6_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_7_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_8_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_9_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_10_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_11_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_12_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_13_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_14_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_15_Z\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_16_Z\, MSC_net_367, 
        MSC_net_368, MSC_net_369, MSC_net_370, MSC_net_371, 
        MSC_net_372, MSC_net_373, MSC_net_374, MSC_net_375, 
        MSC_net_376, MSC_net_377, MSC_net_378, MSC_net_379, 
        MSC_net_380, MSC_net_381, MSC_net_382, MSC_net_383, 
        \SVM_FSM_PROC.va3h_o_2_cry_0_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_1_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_2_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_3_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_4_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_5_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_6_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_7_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_8_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_9_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_10_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_11_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_12_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_13_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_14_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_15_Z\, 
        \SVM_FSM_PROC.va3h_o_2_cry_16_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_0_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_1_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_2_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_3_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_4_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_5_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_6_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_7_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_8_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_9_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_10_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_11_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_12_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_13_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_14_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_15_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_16_Z\, MSC_net_418, 
        \SVM_FSM_PROC.vc3h_o_1_axb_0_i_0_Z\, 
        \SVM_FSM_PROC.vb3h_o_1_axb_0_i_0_Z\, 
        \SVM_FSM_PROC.va3h_o_2_axb_0_i_0_Z\, MSC_net_422, 
        MSC_net_423, MSC_net_424, MSC_net_425, MSC_net_426, 
        MSC_net_427, MSC_net_428, MSC_net_429, MSC_net_430, 
        MSC_net_431, MSC_net_432, MSC_net_433, MSC_net_434, 
        MSC_net_435, MSC_net_436, MSC_net_437, MSC_net_438, 
        MSC_net_439, MSC_net_440, MSC_net_441, MSC_net_442, 
        MSC_net_443, MSC_net_444, MSC_net_445, MSC_net_446, 
        MSC_net_447, MSC_net_448, MSC_net_449, MSC_net_450, 
        MSC_net_451, MSC_net_452, MSC_net_453, MSC_net_454, 
        MSC_net_455, MSC_net_456, MSC_net_457, MSC_net_458, 
        MSC_net_459, MSC_net_460, MSC_net_461, MSC_net_462, 
        MSC_net_463, MSC_net_464, MSC_net_465, MSC_net_466, 
        MSC_net_467, MSC_net_468, MSC_net_469, MSC_net_470, 
        MSC_net_471, MSC_net_472, MSC_net_473, MSC_net_474, 
        MSC_net_475, MSC_net_476, MSC_net_477, MSC_net_478, 
        MSC_net_479, MSC_net_480, MSC_net_481, MSC_net_482, 
        MSC_net_483, MSC_net_484, MSC_net_485, MSC_net_486, 
        MSC_net_487, MSC_net_488, MSC_net_489, MSC_net_490, 
        MSC_net_491, MSC_net_492, MSC_net_493, MSC_net_494, 
        MSC_net_495, MSC_net_496, MSC_net_497, MSC_net_498, 
        MSC_net_499, MSC_net_500, MSC_net_501, MSC_net_502, 
        MSC_net_503, MSC_net_504, MSC_net_505, MSC_net_506, 
        MSC_net_507, MSC_net_508, MSC_net_509, MSC_net_510, 
        MSC_net_511, MSC_net_512, MSC_net_513, MSC_net_514, 
        MSC_net_515, MSC_net_516, MSC_net_517, MSC_net_518, 
        MSC_net_519, MSC_net_520, MSC_net_521, MSC_net_522, 
        MSC_net_523, MSC_net_524, MSC_net_525, MSC_net_526, 
        MSC_net_527, MSC_net_528, MSC_net_529, 
        \SVM_FSM_PROC.vc3h_o_1_cry_16_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_s_17_FCO\, 
        \SVM_FSM_PROC.vc3h_o_1_s_17_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_15_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_14_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_13_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_12_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_11_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_10_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_9_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_8_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_7_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_6_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_5_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_4_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_3_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_2_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_1_Y\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_0_S\, 
        \SVM_FSM_PROC.vc3h_o_1_cry_0_Y\, MSC_net_550, MSC_net_551, 
        MSC_net_552, MSC_net_553, MSC_net_554, MSC_net_555, 
        MSC_net_556, MSC_net_557, MSC_net_558, MSC_net_559, 
        MSC_net_560, MSC_net_561, MSC_net_562, MSC_net_563, 
        MSC_net_564, MSC_net_565, MSC_net_566, MSC_net_567, 
        MSC_net_568, MSC_net_569, 
        \SVM_FSM_PROC.va3h_o_2_cry_16_Y\, 
        \SVM_FSM_PROC.va3h_o_2_s_17_FCO\, 
        \SVM_FSM_PROC.va3h_o_2_s_17_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_15_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_14_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_13_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_12_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_11_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_10_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_9_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_8_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_7_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_6_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_5_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_4_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_3_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_2_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_1_Y\, 
        \SVM_FSM_PROC.va3h_o_2_cry_0_S\, 
        \SVM_FSM_PROC.va3h_o_2_cry_0_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_16_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_s_17_FCO\, 
        \SVM_FSM_PROC.vb3h_o_1_s_17_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_15_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_14_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_13_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_12_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_11_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_10_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_9_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_8_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_7_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_6_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_5_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_4_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_3_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_2_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_1_Y\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_0_S\, 
        \SVM_FSM_PROC.vb3h_o_1_cry_0_Y\ : std_logic;

begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
PCjwPjVxsOoouuKmzNbe98Qm8UYQ0j0B6BrK6r1J2aNyP0Eby/85Pfh/uxrKEDqn
IuMcaRenbmY3QjGCvD8lIfUKNneyyR5K9TEeEDYrI5hIMob8EMcd7NBaw4uDdYTJ
BjJh3wHEoIxokJ1ia8YIG4Aqs0y28N9vkC4/f/fRcbQ=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=108095)
`protect data_block
[encoded data, 106432 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity mas_adc_scl is

    port( reset_i    : in    std_logic;
          sys_clk_i  : in    std_logic;
          mas_en_i   : in    std_logic;
          sub_i      : in    std_logic;
          mul_a_i    : in    std_logic_vector(17 downto 0);
          mul_b_i    : in    std_logic_vector(17 downto 0);
          add_c_i    : in    std_logic_vector(43 downto 0);
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );

end mas_adc_scl;

architecture DEF_ARCH of mas_adc_scl is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \product_o\ : std_logic_vector(43 downto 0);
    signal s_mas_done_dly : std_logic_vector(0 to 0);
    signal product_o_NC : std_logic_vector(43 downto 0);
    signal product_o_ONC : std_logic_vector(43 downto 36);
    signal MSC_net_157, MSC_net_158, MSC_net_159, MSC_net_160, 
        MSC_net_161, MSC_net_162, MSC_net_163, MSC_net_164, 
        MSC_net_165, MSC_net_166, MSC_net_167, MSC_net_168, 
        MSC_net_169, MSC_net_170, MSC_net_171, MSC_net_172, 
        MSC_net_173, MSC_net_174, MSC_net_175, MSC_net_176, 
        MSC_net_177, MSC_net_178, MSC_net_179, MSC_net_180, 
        MSC_net_181, MSC_net_182, MSC_net_183, MSC_net_184, 
        MSC_net_185, MSC_net_186, MSC_net_187, MSC_net_188, 
        MSC_net_189, MSC_net_190, MSC_net_191, MSC_net_192, 
        MSC_net_193, MSC_net_194, MSC_net_195, MSC_net_196, 
        MSC_net_197, MSC_net_198, MSC_net_199, MSC_net_200, 
        MSC_net_201, MSC_net_202, MSC_net_203, MSC_net_204, 
        MSC_net_205, MSC_net_206, MSC_net_207, MSC_net_208, 
        MSC_net_209, MSC_net_210, MSC_net_211, MSC_net_212, 
        MSC_net_213, MSC_net_214, MSC_net_215, MSC_net_216, 
        MSC_net_217, MSC_net_218, MSC_net_219, MSC_net_220
         : std_logic;

begin 

    \product_o\(43 downto 1) <= (OTHERS => 'U'); 
    product_o(43) <= \product_o\(0);
    product_o(42) <= \product_o\(0);
    product_o(41) <= \product_o\(0);
    product_o(40) <= \product_o\(0);
    product_o(39) <= \product_o\(0);
    product_o(38) <= \product_o\(0);
    product_o(37) <= \product_o\(0);
    product_o(36) <= \product_o\(0);
    product_o(35) <= \product_o\(0);
    product_o(34) <= \product_o\(0);
    product_o(33) <= \product_o\(0);
    product_o(32) <= \product_o\(0);
    product_o(31) <= \product_o\(0);
    product_o(30) <= \product_o\(0);
    product_o(29) <= \product_o\(0);
    product_o(28) <= \product_o\(0);
    product_o(27) <= \product_o\(0);
    product_o(26) <= \product_o\(0);
    product_o(7) <= \product_o\(0);
    product_o(6) <= \product_o\(0);
    product_o(5) <= \product_o\(0);
    product_o(4) <= \product_o\(0);
    product_o(3) <= \product_o\(0);
    product_o(2) <= \product_o\(0);
    product_o(1) <= \product_o\(0);
    product_o(0) <= \product_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
PNevtI2Jdr+++uTCZpKJp0KN7SvpXw3GZLCAK/FkdQvkD7e+Fj7HY71H8eXJ+xDE
kux9a8k6hoiNeoBCf4irwUDf2bV6VgGKS6ZW/2kxb2gSS0cTY+bYJwYrjm+QGbgT
rsE03MCicjlPS0nLZcpNMNfNfBdPmcgEUoTHLxf94wM=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=12525)
`protect data_block
[encoded data, 12288 characters]
f4omdSP1opEWmmP04s/jMsMA3c/II3JwiXrb6W/phqc=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity ADC_SCALING is

    port( reset_i              : in    std_logic;
          sys_clk_i            : in    std_logic;
          adc_results_rdy_i    : in    std_logic;
          adc_scale_val_i      : in    std_logic_vector(17 downto 0);
          adc_result_ch0_i     : in    std_logic_vector(11 downto 0);
          adc_result_ch1_i     : in    std_logic_vector(11 downto 0);
          fault_threshold_i    : in    std_logic_vector(17 downto 0);
          done_o               : out   std_logic;
          calib_done_o         : out   std_logic;
          over_current_fault_o : out   std_logic;
          ia_adc_o             : out   std_logic_vector(17 downto 0);
          ib_adc_o             : out   std_logic_vector(17 downto 0)
        );

end ADC_SCALING;

architecture DEF_ARCH of ADC_SCALING is 

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component mas_adc_scl
    port( reset_i    : in    std_logic := 'U';
          sys_clk_i  : in    std_logic := 'U';
          mas_en_i   : in    std_logic := 'U';
          sub_i      : in    std_logic := 'U';
          mul_a_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          mul_b_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          add_c_i    : in    std_logic_vector(43 downto 0) := (others => 'U');
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );
  end component;

    signal \ia_adc_o\ : std_logic_vector(17 downto 0);
    signal \ib_adc_o\ : std_logic_vector(17 downto 0);
    signal MSC_net_100 : std_logic;
    signal s_mult0_in : std_logic_vector(17 downto 0);
    signal s_product : std_logic_vector(25 downto 8);
    signal s_adc_ch1_offset : std_logic_vector(30 downto 0);
    signal s_adc_ch0_offset : std_logic_vector(30 downto 0);
    signal s_state : std_logic_vector(1 downto 0);
    signal s_state_ns : std_logic_vector(1 downto 0);
    signal inf_abs1 : std_logic_vector(17 downto 0);
    signal inf_abs0 : std_logic_vector(17 downto 0);
    signal s_calib_cnt : std_logic_vector(13 downto 0);
    signal s_calib_cnt_cry : std_logic_vector(12 downto 0);
    signal s_calib_cnt_s : std_logic_vector(13 downto 0);
    signal un1_s_mult0_in_0 : std_logic_vector(16 downto 6);
    signal s_calib_cnt_cry_Y : std_logic_vector(12 downto 0);
    signal s_calib_cnt_s_FCO : std_logic_vector(13 to 13);
    signal s_calib_cnt_s_Y : std_logic_vector(13 to 13);
    signal s_calib_cnt_cry_cy_S : std_logic_vector(0 to 0);
    signal s_calib_cnt_cry_cy_Y : std_logic_vector(0 to 0);
    signal product_o : std_logic_vector(43 downto 0);
    signal MSC_net_353, MSC_net_354, MSC_net_355, MSC_net_356, 
        MSC_net_357, MSC_net_358, MSC_net_359, MSC_net_360, 
        MSC_net_361, MSC_net_362, MSC_net_363, MSC_net_364, 
        MSC_net_365, MSC_net_366, MSC_net_367, MSC_net_368, 
        MSC_net_369, MSC_net_370, MSC_net_371, MSC_net_372, 
        MSC_net_373, MSC_net_374, MSC_net_375, MSC_net_376, 
        MSC_net_377, MSC_net_378, MSC_net_379, MSC_net_380, 
        MSC_net_381, MSC_net_382, MSC_net_383, MSC_net_384, 
        MSC_net_385, MSC_net_386, MSC_net_387, MSC_net_388, 
        MSC_net_389, MSC_net_390, MSC_net_391, MSC_net_392, 
        MSC_net_393, MSC_net_394, MSC_net_395, MSC_net_396, 
        MSC_net_397, MSC_net_398, MSC_net_399, MSC_net_400, 
        MSC_net_401, MSC_net_402, MSC_net_403, MSC_net_404, 
        MSC_net_405, MSC_net_406, MSC_net_407, MSC_net_408, 
        MSC_net_409, MSC_net_410, MSC_net_411, MSC_net_412, 
        MSC_net_413, MSC_net_414, MSC_net_415, MSC_net_416, 
        MSC_net_417, MSC_net_418, MSC_net_419, MSC_net_420, 
        MSC_net_421, MSC_net_422, MSC_net_423, MSC_net_424, 
        MSC_net_425, MSC_net_426, MSC_net_427, MSC_net_428, 
        MSC_net_429, MSC_net_430, MSC_net_431, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1\, 
        \OVER_CURRENT_FAULT_DET_PROC.over_current_fault_o2\, 
        MSC_net_435, MSC_net_436, MSC_net_437, MSC_net_438, 
        MSC_net_439, MSC_net_440, MSC_net_441, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_0_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_1_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_2_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_3_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_4_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_5_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_6_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_7_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_8_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_9_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_10_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_11_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_12_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_13_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_14_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_15_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_16_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_0_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_1_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_2_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_3_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_4_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_5_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_6_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_7_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_8_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_9_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_10_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_11_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_12_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_13_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_14_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_15_Z\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_16_Z\, 
        MSC_net_476, MSC_net_477, MSC_net_478, MSC_net_479, 
        MSC_net_480, MSC_net_481, MSC_net_482, MSC_net_483, 
        MSC_net_484, MSC_net_485, MSC_net_486, MSC_net_487, 
        MSC_net_488, MSC_net_489, MSC_net_490, MSC_net_491, 
        MSC_net_492, MSC_net_493, MSC_net_494, MSC_net_495, 
        MSC_net_496, MSC_net_497, MSC_net_498, MSC_net_499, 
        MSC_net_500, MSC_net_501, MSC_net_502, MSC_net_503, 
        MSC_net_504, MSC_net_505, MSC_net_506, MSC_net_507, 
        MSC_net_508, MSC_net_509, MSC_net_510, MSC_net_511, 
        MSC_net_512, MSC_net_513, MSC_net_514, MSC_net_515, 
        MSC_net_516, MSC_net_517, MSC_net_518, MSC_net_519, 
        MSC_net_520, MSC_net_521, MSC_net_522, MSC_net_523, 
        MSC_net_524, MSC_net_525, MSC_net_526, MSC_net_527, 
        MSC_net_528, MSC_net_529, MSC_net_530, MSC_net_531, 
        MSC_net_532, MSC_net_533, MSC_net_534, MSC_net_535, 
        MSC_net_536, MSC_net_537, MSC_net_538, MSC_net_539, 
        MSC_net_540, MSC_net_541, MSC_net_542, MSC_net_543, 
        MSC_net_544, MSC_net_545, MSC_net_546, MSC_net_547, 
        MSC_net_548, MSC_net_549, MSC_net_550, MSC_net_551, 
        MSC_net_552, MSC_net_553, MSC_net_554, MSC_net_555, 
        MSC_net_556, MSC_net_557, MSC_net_558, MSC_net_559, 
        MSC_net_560, MSC_net_561, MSC_net_562, MSC_net_563, 
        MSC_net_564, MSC_net_565, MSC_net_566, MSC_net_567, 
        MSC_net_568, MSC_net_569, MSC_net_570, MSC_net_571, 
        MSC_net_572, MSC_net_573, MSC_net_574, MSC_net_575, 
        MSC_net_576, MSC_net_577, MSC_net_578, MSC_net_579, 
        MSC_net_580, MSC_net_581, MSC_net_582, MSC_net_583, 
        MSC_net_584, MSC_net_585, MSC_net_586, MSC_net_587, 
        MSC_net_588, MSC_net_589, MSC_net_590, MSC_net_591, 
        MSC_net_592, MSC_net_593, MSC_net_594, MSC_net_595, 
        MSC_net_596, MSC_net_597, MSC_net_598, MSC_net_599, 
        MSC_net_600, MSC_net_601, MSC_net_602, MSC_net_603, 
        MSC_net_604, MSC_net_605, MSC_net_606, MSC_net_607, 
        MSC_net_608, MSC_net_609, MSC_net_610, MSC_net_611, 
        MSC_net_612, MSC_net_613, MSC_net_614, MSC_net_615, 
        MSC_net_616, MSC_net_617, MSC_net_618, MSC_net_619, 
        MSC_net_620, MSC_net_621, MSC_net_622, MSC_net_623, 
        MSC_net_624, MSC_net_625, MSC_net_626, MSC_net_627, 
        MSC_net_628, MSC_net_629, MSC_net_630, MSC_net_631, 
        MSC_net_632, MSC_net_633, MSC_net_634, MSC_net_635, 
        MSC_net_636, MSC_net_637, MSC_net_638, MSC_net_639, 
        MSC_net_640, MSC_net_641, MSC_net_642, MSC_net_643, 
        MSC_net_644, MSC_net_645, MSC_net_646, MSC_net_647, 
        MSC_net_648, MSC_net_649, MSC_net_650, MSC_net_651, 
        MSC_net_652, MSC_net_653, MSC_net_654, MSC_net_655, 
        MSC_net_656, MSC_net_657, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_17_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_17_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_16_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_16_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_15_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_15_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_14_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_14_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_13_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_13_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_12_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_12_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_11_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_11_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_10_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_10_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_9_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_9_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_8_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_8_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_7_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_7_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_6_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_6_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_5_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_5_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_4_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_4_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_3_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_3_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_2_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_2_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_1_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_1_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_0_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_0_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_17_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_17_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_16_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_16_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_15_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_15_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_14_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_14_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_13_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_13_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_12_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_12_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_11_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_11_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_10_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_10_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_9_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_9_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_8_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_8_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_7_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_7_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_6_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_6_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_5_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_5_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_4_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_4_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_3_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_3_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_2_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_2_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_1_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_1_Y\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_0_S\, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_0_Y\, 
        MSC_net_730, MSC_net_731, MSC_net_732, MSC_net_733, 
        MSC_net_734, MSC_net_735, MSC_net_736, MSC_net_737, 
        MSC_net_738, MSC_net_739, MSC_net_740, MSC_net_741, 
        MSC_net_742, MSC_net_743, MSC_net_744, MSC_net_745, 
        MSC_net_746, MSC_net_747, MSC_net_748, MSC_net_749, 
        MSC_net_750, MSC_net_751, MSC_net_752, MSC_net_753, 
        MSC_net_754, MSC_net_755, MSC_net_756, MSC_net_757, 
        MSC_net_758, MSC_net_759, MSC_net_760, MSC_net_761, 
        MSC_net_762, MSC_net_763, MSC_net_764, MSC_net_765, 
        MSC_net_766, MSC_net_767, MSC_net_768, MSC_net_769, 
        MSC_net_770, MSC_net_771, MSC_net_772, MSC_net_773, 
        MSC_net_774, MSC_net_775, MSC_net_776, MSC_net_777, 
        MSC_net_778, MSC_net_779, MSC_net_780, MSC_net_781, 
        MSC_net_782, MSC_net_783, MSC_net_784, MSC_net_785, 
        MSC_net_786, MSC_net_787, MSC_net_788, MSC_net_789, 
        MSC_net_790, MSC_net_791, MSC_net_792, MSC_net_793, 
        MSC_net_794, MSC_net_795, MSC_net_796, MSC_net_797, 
        MSC_net_798, MSC_net_799, MSC_net_800, MSC_net_801, 
        MSC_net_802, MSC_net_803, MSC_net_804, MSC_net_805, 
        MSC_net_806, MSC_net_807, MSC_net_808, MSC_net_809, 
        MSC_net_810, MSC_net_811, MSC_net_812, MSC_net_813, 
        MSC_net_814, MSC_net_815, MSC_net_816 : std_logic;

    for all : mas_adc_scl
	Use entity work.mas_adc_scl(DEF_ARCH);
begin 

    calib_done_o <= MSC_net_100;
    ia_adc_o(17) <= \ia_adc_o\(17);
    ia_adc_o(16) <= \ia_adc_o\(16);
    ia_adc_o(15) <= \ia_adc_o\(15);
    ia_adc_o(14) <= \ia_adc_o\(14);
    ia_adc_o(13) <= \ia_adc_o\(13);
    ia_adc_o(12) <= \ia_adc_o\(12);
    ia_adc_o(11) <= \ia_adc_o\(11);
    ia_adc_o(10) <= \ia_adc_o\(10);
    ia_adc_o(9) <= \ia_adc_o\(9);
    ia_adc_o(8) <= \ia_adc_o\(8);
    ia_adc_o(7) <= \ia_adc_o\(7);
    ia_adc_o(6) <= \ia_adc_o\(6);
    ia_adc_o(5) <= \ia_adc_o\(5);
    ia_adc_o(4) <= \ia_adc_o\(4);
    ia_adc_o(3) <= \ia_adc_o\(3);
    ia_adc_o(2) <= \ia_adc_o\(2);
    ia_adc_o(1) <= \ia_adc_o\(1);
    ia_adc_o(0) <= \ia_adc_o\(0);
    ib_adc_o(17) <= \ib_adc_o\(17);
    ib_adc_o(16) <= \ib_adc_o\(16);
    ib_adc_o(15) <= \ib_adc_o\(15);
    ib_adc_o(14) <= \ib_adc_o\(14);
    ib_adc_o(13) <= \ib_adc_o\(13);
    ib_adc_o(12) <= \ib_adc_o\(12);
    ib_adc_o(11) <= \ib_adc_o\(11);
    ib_adc_o(10) <= \ib_adc_o\(10);
    ib_adc_o(9) <= \ib_adc_o\(9);
    ib_adc_o(8) <= \ib_adc_o\(8);
    ib_adc_o(7) <= \ib_adc_o\(7);
    ib_adc_o(6) <= \ib_adc_o\(6);
    ib_adc_o(5) <= \ib_adc_o\(5);
    ib_adc_o(4) <= \ib_adc_o\(4);
    ib_adc_o(3) <= \ib_adc_o\(3);
    ib_adc_o(2) <= \ib_adc_o\(2);
    ib_adc_o(1) <= \ib_adc_o\(1);
    ib_adc_o(0) <= \ib_adc_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
jSiI9g8QbzJVv+ppX7epS910cK5xgfYoh9li5RBD5wspBlPeuVDWJ/c8hn2mTogp
CyHwaZ5kYm7UnlG9OrcexZqk+EOuH2IsnCQ9KRdss+sf5p5gDr/6E8zZb/Xx+Yv5
qTmc67DWdsMNdvRQKTQZzh7eM/8KFwL5qVdqjeRwOOc=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=141355)
`protect data_block
[encoded data, 139136 characters]
nvcZzl8Wx4Ebno4rqVCfvqyhL2SAnIqeaVMCWVAq/sU=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity mas_olmng is

    port( reset_i    : in    std_logic;
          sys_clk_i  : in    std_logic;
          mas_en_i   : in    std_logic;
          sub_i      : in    std_logic;
          mul_a_i    : in    std_logic_vector(17 downto 0);
          mul_b_i    : in    std_logic_vector(17 downto 0);
          add_c_i    : in    std_logic_vector(43 downto 0);
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );

end mas_olmng;

architecture DEF_ARCH of mas_olmng is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \product_o\ : std_logic_vector(43 downto 0);
    signal s_mas_done_dly : std_logic_vector(0 to 0);
    signal product_o_NC : std_logic_vector(43 downto 0);
    signal MSC_net_149, MSC_net_150, MSC_net_151, MSC_net_152, 
        MSC_net_153, MSC_net_154, MSC_net_155, MSC_net_156, 
        MSC_net_157, MSC_net_158, MSC_net_159, MSC_net_160, 
        MSC_net_161, MSC_net_162, MSC_net_163, MSC_net_164, 
        MSC_net_165, MSC_net_166, MSC_net_167, MSC_net_168, 
        MSC_net_169, MSC_net_170, MSC_net_171, MSC_net_172, 
        MSC_net_173, MSC_net_174, MSC_net_175, MSC_net_176
         : std_logic;

begin 

    \product_o\(43 downto 1) <= (OTHERS => 'U'); 
    product_o(43) <= \product_o\(0);
    product_o(42) <= \product_o\(0);
    product_o(41) <= \product_o\(0);
    product_o(40) <= \product_o\(0);
    product_o(39) <= \product_o\(0);
    product_o(38) <= \product_o\(0);
    product_o(37) <= \product_o\(0);
    product_o(36) <= \product_o\(0);
    product_o(35) <= \product_o\(0);
    product_o(34) <= \product_o\(0);
    product_o(33) <= \product_o\(0);
    product_o(32) <= \product_o\(0);
    product_o(31) <= \product_o\(0);
    product_o(12) <= \product_o\(0);
    product_o(11) <= \product_o\(0);
    product_o(10) <= \product_o\(0);
    product_o(9) <= \product_o\(0);
    product_o(8) <= \product_o\(0);
    product_o(7) <= \product_o\(0);
    product_o(6) <= \product_o\(0);
    product_o(5) <= \product_o\(0);
    product_o(4) <= \product_o\(0);
    product_o(3) <= \product_o\(0);
    product_o(2) <= \product_o\(0);
    product_o(1) <= \product_o\(0);
    product_o(0) <= \product_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
ZNcm8kDLyFBlcJAxFVj0GN8+j7qm1nd9zO9Voj4FTzreWj1sVBz4i1t5+hgX/1Ng
6JDG3OLFJ4MQGipzdQZ5+zYZaIDuNKFRhMhbhjEoX7xr0uXZmbsG6UA/94DPJkF2
h5aN5xRJ0OfEhQ3oNtfmiAJRihTDibscg0hDsTeGHwU=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=12375)
`protect data_block
[encoded data, 12160 characters]
aTmuUUulcCF9MrTPnw7ZTg==

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity accumulator_olmng is

    port( s_theta_buff   : out   std_logic_vector(17 downto 0);
          theta_o        : in    std_logic_vector(17 downto 0);
          reset_i        : in    std_logic;
          sys_clk_i      : in    std_logic;
          clear_buffer_i : in    std_logic;
          s_olmng_done   : in    std_logic
        );

end accumulator_olmng;

architecture DEF_ARCH of accumulator_olmng is 

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal theta_scl_buff_o_3 : std_logic_vector(17 downto 0);
    signal MSC_net_58, MSC_net_59, MSC_net_60 : std_logic;

begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
FPmmTRQY/2zb0wAZd38mz1Uplyg03GEe6H+BphxE3mDlOQoVJU0BTpDrPdg5GHN5
92sGNoeKL3Zq4dqLcFGHeQi4ZwrcXyGZCdWxQCNqxTiLO4hbconfKAe0sxX+X2Cq
znsm0hIGn/h7wxSVv7APhbSKf3jB5T172FfWbjokoD4=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=10985)
`protect data_block
[encoded data, 10816 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity OLMNG is

    port( reset_i            : in    std_logic;
          sys_clk_i          : in    std_logic;
          start_i            : in    std_logic;
          clear_buffer_i     : in    std_logic;
          direction_config_i : in    std_logic;
          cl_status_i        : in    std_logic;
          theta_factor_i     : in    std_logic_vector(17 downto 0);
          speed_ref_i        : in    std_logic_vector(17 downto 0);
          dv_i               : in    std_logic_vector(17 downto 0);
          theta_cl_i         : in    std_logic_vector(17 downto 0);
          iq_ref_in_i        : in    std_logic_vector(17 downto 0);
          done_o             : out   std_logic;
          theta_o            : out   std_logic_vector(17 downto 0);
          init_speedpi_o     : out   std_logic_vector(17 downto 0);
          init_iqpi_o        : out   std_logic_vector(17 downto 0)
        );

end OLMNG;

architecture DEF_ARCH of OLMNG is 

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component mas_olmng
    port( reset_i    : in    std_logic := 'U';
          sys_clk_i  : in    std_logic := 'U';
          mas_en_i   : in    std_logic := 'U';
          sub_i      : in    std_logic := 'U';
          mul_a_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          mul_b_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          add_c_i    : in    std_logic_vector(43 downto 0) := (others => 'U');
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );
  end component;

  component accumulator_olmng
    port( s_theta_buff   : out   std_logic_vector(17 downto 0);
          theta_o        : in    std_logic_vector(17 downto 0) := (others => 'U');
          reset_i        : in    std_logic := 'U';
          sys_clk_i      : in    std_logic := 'U';
          clear_buffer_i : in    std_logic := 'U';
          s_olmng_done   : in    std_logic := 'U'
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

    signal \theta_o\ : std_logic_vector(17 downto 0);
    signal MSC_net_150 : std_logic;
    signal s_mult0_input : std_logic_vector(17 downto 0);
    signal s_mult1_input : std_logic_vector(17 downto 0);
    signal s_addc_input : std_logic_vector(30 downto 13);
    signal s_product : std_logic_vector(30 downto 13);
    signal s_theta_buff : std_logic_vector(17 downto 0);
    signal s_theta_ol : std_logic_vector(17 downto 0);
    signal s_state : std_logic_vector(1 downto 0);
    signal s_state_d : std_logic_vector(2 to 2);
    signal s_state_ns : std_logic_vector(0 to 0);
    signal iq_ref_in_i_RNI4RTI3_S : std_logic_vector(0 to 0);
    signal init_speedpi_o_4 : std_logic_vector(17 downto 1);
    signal iq_ref_in_i_RNITO8O01_Y : std_logic_vector(16 to 16);
    signal init_speedpi_o_RNO_FCO : std_logic_vector(17 to 17);
    signal init_speedpi_o_RNO_Y : std_logic_vector(17 to 17);
    signal iq_ref_in_i_RNIM0K4V_Y : std_logic_vector(15 to 15);
    signal iq_ref_in_i_RNIG9VGT_Y : std_logic_vector(14 to 14);
    signal iq_ref_in_i_RNIBJATR_Y : std_logic_vector(13 to 13);
    signal iq_ref_in_i_RNI7UL9Q_Y : std_logic_vector(12 to 12);
    signal iq_ref_in_i_RNI4A1MO_Y : std_logic_vector(11 to 11);
    signal iq_ref_in_i_RNI2NC2N_Y : std_logic_vector(10 to 10);
    signal iq_ref_in_i_RNI15OEL_Y : std_logic_vector(9 to 9);
    signal iq_ref_in_i_RNI8S6FJ_Y : std_logic_vector(8 to 8);
    signal iq_ref_in_i_RNIGKLFH_Y : std_logic_vector(7 to 7);
    signal iq_ref_in_i_RNIPD4GF_Y : std_logic_vector(6 to 6);
    signal iq_ref_in_i_RNI38JGD_Y : std_logic_vector(5 to 5);
    signal iq_ref_in_i_RNIE32HB_Y : std_logic_vector(4 to 4);
    signal iq_ref_in_i_RNIQVGH9_Y : std_logic_vector(3 to 3);
    signal iq_ref_in_i_RNI7TVH7_Y : std_logic_vector(2 to 2);
    signal iq_ref_in_i_RNILREI5_Y : std_logic_vector(1 to 1);
    signal iq_ref_in_i_RNI4RTI3_Y : std_logic_vector(0 to 0);
    signal product_o : std_logic_vector(43 downto 0);
    signal MSC_net_344, MSC_net_345, MSC_net_346, MSC_net_347, 
        MSC_net_348, MSC_net_349, MSC_net_350, MSC_net_351, 
        MSC_net_352, MSC_net_353, MSC_net_354, MSC_net_355, 
        MSC_net_356, MSC_net_357, MSC_net_358, MSC_net_359, 
        MSC_net_360, MSC_net_361, MSC_net_362, MSC_net_363, 
        MSC_net_364, MSC_net_365, MSC_net_366, MSC_net_367, 
        MSC_net_368, MSC_net_369, MSC_net_370, MSC_net_371, 
        MSC_net_372, MSC_net_373, MSC_net_374, MSC_net_375, 
        MSC_net_376, MSC_net_377, MSC_net_378, MSC_net_379, 
        MSC_net_380, MSC_net_381, MSC_net_382, MSC_net_383, 
        MSC_net_384, MSC_net_385, MSC_net_386, MSC_net_387, 
        MSC_net_388, MSC_net_389, MSC_net_390, MSC_net_391, 
        MSC_net_392, MSC_net_393, MSC_net_394, MSC_net_395, 
        MSC_net_396, MSC_net_397, MSC_net_398, MSC_net_399, 
        MSC_net_400, MSC_net_401, MSC_net_402, MSC_net_403, 
        MSC_net_404, MSC_net_405, MSC_net_406, MSC_net_407, 
        MSC_net_408, MSC_net_409, MSC_net_410, MSC_net_411, 
        MSC_net_412, MSC_net_413, MSC_net_414, MSC_net_415, 
        MSC_net_416, MSC_net_417, MSC_net_418, MSC_net_419, 
        MSC_net_420, MSC_net_421, MSC_net_422, MSC_net_423, 
        MSC_net_424, MSC_net_425, MSC_net_426, MSC_net_427, 
        MSC_net_428, MSC_net_429, MSC_net_430, MSC_net_431
         : std_logic;

    for all : mas_olmng
	Use entity work.mas_olmng(DEF_ARCH);
    for all : accumulator_olmng
	Use entity work.accumulator_olmng(DEF_ARCH);
begin 

    done_o <= MSC_net_150;
    theta_o(17) <= \theta_o\(17);
    theta_o(16) <= \theta_o\(16);
    theta_o(15) <= \theta_o\(15);
    theta_o(14) <= \theta_o\(14);
    theta_o(13) <= \theta_o\(13);
    theta_o(12) <= \theta_o\(12);
    theta_o(11) <= \theta_o\(11);
    theta_o(10) <= \theta_o\(10);
    theta_o(9) <= \theta_o\(9);
    theta_o(8) <= \theta_o\(8);
    theta_o(7) <= \theta_o\(7);
    theta_o(6) <= \theta_o\(6);
    theta_o(5) <= \theta_o\(5);
    theta_o(4) <= \theta_o\(4);
    theta_o(3) <= \theta_o\(3);
    theta_o(2) <= \theta_o\(2);
    theta_o(1) <= \theta_o\(1);
    theta_o(0) <= \theta_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
TKWi8yZ4wAeRFaXYR8F6RcvxahX4FZdmfkYzgF3iPilhveVCvmouXjZarOFH9h5L
Okd2LP9A63oPfA0xnRwCm481PlC/Y3fHlBOTH7MxP+lHJAP0MWQU5BwM0/B0BEmk
FbcMmMqFiyW5Vy1CV/N9pNGQWxoufMw6JaiP1s9bCcM=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=67860)
`protect data_block
[encoded data, 66816 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity accumulator_rl is

    port( s_ref_val_buf : out   std_logic_vector(17 downto 0);
          s_ramp_out    : in    std_logic_vector(17 downto 0);
          reset_i       : in    std_logic;
          sys_clk_i     : in    std_logic;
          reset_rl_i    : in    std_logic;
          s_rl_done     : in    std_logic
        );

end accumulator_rl;

architecture DEF_ARCH of accumulator_rl is 

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal rl_out_prev_o_3 : std_logic_vector(17 downto 0);
    signal MSC_net_58, MSC_net_59, MSC_net_60 : std_logic;

begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
RzY70/EfwGvGU1Y8iT3ADTgmavHWxURrLEdM81L6qrG/SNHkm1zXuhcIKkV2l3jo
GEKTMUQibmu/2s8je97a3s44ZAJDLPr1T6YFcvkgoo/yCmX21uzXwf84aoOniJpd
pngDGteeET+sVuvDwU5HmvqYEmZjwlNoBu192ssgZWY=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=10685)
`protect data_block
[encoded data, 10496 characters]
eRJpyG9/BeBFnxes4MiStQ==

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity RATE_LIMITER is

    port( reset_i      : in    std_logic;
          sys_clk_i    : in    std_logic;
          start_i      : in    std_logic;
          soft_stop_i  : in    std_logic;
          reset_rl_i   : in    std_logic;
          direction_i  : in    std_logic;
          slew_count_i : in    std_logic_vector(17 downto 0);
          rate_count_i : in    std_logic_vector(17 downto 0);
          rl_in_i      : in    std_logic_vector(17 downto 0);
          rl_out_o     : out   std_logic_vector(17 downto 0);
          rl_done_o    : out   std_logic
        );

end RATE_LIMITER;

architecture DEF_ARCH of RATE_LIMITER is 

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG1
    generic (INIT:std_logic_vector(1 downto 0) := "00");

    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component accumulator_rl
    port( s_ref_val_buf : out   std_logic_vector(17 downto 0);
          s_ramp_out    : in    std_logic_vector(17 downto 0) := (others => 'U');
          reset_i       : in    std_logic := 'U';
          sys_clk_i     : in    std_logic := 'U';
          reset_rl_i    : in    std_logic := 'U';
          s_rl_done     : in    std_logic := 'U'
        );
  end component;

    signal \rl_out_o\ : std_logic_vector(17 downto 0);
    signal MSC_net_78 : std_logic;
    signal s_ref_val_buf : std_logic_vector(17 downto 0);
    signal s_set_ref : std_logic_vector(17 downto 0);
    signal s_count : std_logic_vector(18 downto 0);
    signal s_ramp_present_state : std_logic_vector(1 downto 0);
    signal s_ramp_present_state_ns : std_logic_vector(1 to 1);
    signal s_ramp_out_7 : std_logic_vector(17 downto 0);
    signal un1_s_ramp_out : std_logic_vector(17 downto 0);
    signal s_set_ref_4 : std_logic_vector(17 downto 0);
    signal s_rl_in : std_logic_vector(17 downto 1);
    signal \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref\ : 
        std_logic_vector(18 to 18);
    signal s_count_cry : std_logic_vector(17 downto 0);
    signal s_count_s : std_logic_vector(18 downto 0);
    signal s_ramp_present_state_i_0 : std_logic_vector(0 to 0);
    signal rate_count_i_i : std_logic_vector(0 to 0);
    signal s_count_i : std_logic_vector(0 to 0);
    signal un1_s_ramp_out_RNIEUSTL_Y : std_logic_vector(1 to 1);
    signal s_ramp_out_7_RNO_FCO : std_logic_vector(17 to 17);
    signal s_ramp_out_7_RNO_Y : std_logic_vector(17 to 17);
    signal un1_s_ramp_out_RNI4Q2KK_Y : std_logic_vector(2 to 2);
    signal un1_s_ramp_out_RNIRM8AJ_Y : std_logic_vector(3 to 3);
    signal un1_s_ramp_out_RNIJKE0I_Y : std_logic_vector(4 to 4);
    signal un1_s_ramp_out_RNICJKMG_Y : std_logic_vector(5 to 5);
    signal un1_s_ramp_out_RNI6JQCF_Y : std_logic_vector(6 to 6);
    signal un1_s_ramp_out_RNI1K03E_Y : std_logic_vector(7 to 7);
    signal un1_s_ramp_out_RNITL6PC_Y : std_logic_vector(8 to 8);
    signal un1_s_ramp_out_RNI8289B_Y : std_logic_vector(9 to 9);
    signal un1_s_ramp_out_RNIKF9P9_Y : 
        std_logic_vector(10 to 10);
    signal un1_s_ramp_out_RNIQTAJ8_Y : 
        std_logic_vector(11 to 11);
    signal un1_s_ramp_out_RNI1DCD7_Y : 
        std_logic_vector(12 to 12);
    signal un1_s_ramp_out_RNI9TD76_Y : 
        std_logic_vector(13 to 13);
    signal un1_s_ramp_out_RNIIEF15_Y : 
        std_logic_vector(14 to 14);
    signal un1_s_ramp_out_RNIS0HR3_Y : 
        std_logic_vector(15 to 15);
    signal un1_s_ramp_out_RNI7KIL2_Y : 
        std_logic_vector(16 to 16);
    signal un1_s_ramp_out_RNIJ8KF1_Y : 
        std_logic_vector(17 to 17);
    signal s_count_RNIT51DM_Y : std_logic_vector(17 to 17);
    signal s_count_RNO_FCO : std_logic_vector(18 to 18);
    signal s_count_RNO_Y : std_logic_vector(18 to 18);
    signal s_count_RNIGI45L_Y : std_logic_vector(16 to 16);
    signal s_count_RNI408TJ_Y : std_logic_vector(15 to 15);
    signal s_count_RNIPEBLI_Y : std_logic_vector(14 to 14);
    signal s_count_RNIFUEDH_Y : std_logic_vector(13 to 13);
    signal s_count_RNI6FI5G_Y : std_logic_vector(12 to 12);
    signal s_count_RNIU0MTE_Y : std_logic_vector(11 to 11);
    signal s_count_RNINJPLD_Y : std_logic_vector(10 to 10);
    signal s_count_RNIH7TDC_Y : std_logic_vector(9 to 9);
    signal s_count_RNIJBK8B_Y : std_logic_vector(8 to 8);
    signal s_count_RNIMGB3A_Y : std_logic_vector(7 to 7);
    signal s_count_RNIQM2U8_Y : std_logic_vector(6 to 6);
    signal s_count_RNIVTPO7_Y : std_logic_vector(5 to 5);
    signal s_count_RNI56HJ6_Y : std_logic_vector(4 to 4);
    signal s_count_RNICF8E5_Y : std_logic_vector(3 to 3);
    signal s_count_RNIKPV84_Y : std_logic_vector(2 to 2);
    signal s_count_RNIT4N33_Y : std_logic_vector(1 to 1);
    signal s_count_RNI7HEU1_Y : std_logic_vector(0 to 0);
    signal \FSM_RATE_LIM_PROC.un1_s_count_1\, 
        \FSM_RATE_LIM_PROC.un1_s_count_2\, 
        \FSM_RATE_LIM_PROC.un1_s_count_3\, 
        \FSM_RATE_LIM_PROC.un1_s_count_4\, 
        \FSM_RATE_LIM_PROC.un1_s_count_5\, 
        \FSM_RATE_LIM_PROC.un1_s_count_6\, 
        \FSM_RATE_LIM_PROC.un1_s_count_7\, 
        \FSM_RATE_LIM_PROC.un1_s_count_8\, 
        \FSM_RATE_LIM_PROC.un1_s_count_9\, 
        \FSM_RATE_LIM_PROC.un1_s_count_10\, 
        \FSM_RATE_LIM_PROC.un1_s_count_11\, 
        \FSM_RATE_LIM_PROC.un1_s_count_12\, 
        \FSM_RATE_LIM_PROC.un1_s_count_13\, 
        \FSM_RATE_LIM_PROC.un1_s_count_14\, 
        \FSM_RATE_LIM_PROC.un1_s_count_15\, 
        \FSM_RATE_LIM_PROC.un1_s_count_16\, 
        \FSM_RATE_LIM_PROC.un1_s_count_17\, MSC_net_305, 
        MSC_net_306, MSC_net_307, 
        \FSM_RATE_LIM_PROC.s_ramp_out19\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref\, 
        \FSM_RATE_LIM_PROC.un1_s_count\, MSC_net_311, MSC_net_312, 
        MSC_net_313, MSC_net_314, MSC_net_315, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_0_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_1_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_2_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_3_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_4_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_5_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_6_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_7_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_8_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_9_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_10_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_11_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_12_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_13_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_14_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_15_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_16_Z\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_17_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_0_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_1_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_2_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_3_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_4_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_5_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_6_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_7_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_8_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_9_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_10_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_11_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_12_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_13_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_14_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_15_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_16_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_17_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_0_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_1_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_2_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_3_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_4_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_5_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_6_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_7_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_8_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_9_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_10_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_11_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_12_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_13_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_14_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_15_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_16_Z\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_17_Z\, MSC_net_370, 
        MSC_net_371, MSC_net_372, MSC_net_373, MSC_net_374, 
        MSC_net_375, MSC_net_376, MSC_net_377, MSC_net_378, 
        MSC_net_379, MSC_net_380, MSC_net_381, MSC_net_382, 
        MSC_net_383, MSC_net_384, MSC_net_385, MSC_net_386, 
        MSC_net_387, MSC_net_388, MSC_net_389, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_1\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_2\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_3\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_4\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_5\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_6\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_7\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_8\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_9\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_10\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_11\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_12\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_13\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_14\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_15\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_16\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_17\, MSC_net_407, 
        MSC_net_408, MSC_net_409, MSC_net_410, MSC_net_411, 
        MSC_net_412, MSC_net_413, MSC_net_414, MSC_net_415, 
        MSC_net_416, MSC_net_417, MSC_net_418, MSC_net_419, 
        MSC_net_420, MSC_net_421, MSC_net_422, MSC_net_423, 
        MSC_net_424, MSC_net_425, MSC_net_426, MSC_net_427, 
        MSC_net_428, MSC_net_429, MSC_net_430, MSC_net_431, 
        MSC_net_432, MSC_net_433, MSC_net_434, MSC_net_435, 
        MSC_net_436, MSC_net_437, MSC_net_438, MSC_net_439, 
        MSC_net_440, MSC_net_441, MSC_net_442, MSC_net_443, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_1\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_2\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_3\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_4\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_5\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_6\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_7\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_8\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_9\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_10\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_11\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_12\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_13\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_14\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_15\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_16\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_17\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_0_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_1_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_2_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_3_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_4_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_5_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_6_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_7_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_8_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_9_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_10_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_11_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_12_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_13_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_14_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_15_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_16_Z\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_17_Z\, 
        MSC_net_479, MSC_net_480, MSC_net_481, MSC_net_482, 
        MSC_net_483, MSC_net_484, MSC_net_485, MSC_net_486, 
        MSC_net_487, MSC_net_488, MSC_net_489, MSC_net_490, 
        MSC_net_491, MSC_net_492, MSC_net_493, MSC_net_494, 
        MSC_net_495, MSC_net_496, MSC_net_497, MSC_net_498, 
        MSC_net_499, MSC_net_500, MSC_net_501, MSC_net_502, 
        MSC_net_503, MSC_net_504, MSC_net_505, MSC_net_506, 
        MSC_net_507, MSC_net_508, MSC_net_509, MSC_net_510, 
        MSC_net_511, MSC_net_512, MSC_net_513, MSC_net_514, 
        MSC_net_515, MSC_net_516, MSC_net_517, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_18_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_18_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_17_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_17_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_16_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_16_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_15_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_15_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_14_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_14_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_13_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_13_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_12_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_12_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_11_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_11_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_10_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_10_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_9_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_9_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_8_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_8_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_7_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_7_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_6_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_6_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_5_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_5_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_4_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_4_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_3_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_3_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_2_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_2_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_1_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_1_Y\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_0_S\, 
        \FSM_RATE_LIM_PROC.s_ramp_out19_cry_0_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_18_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_18_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_17_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_17_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_16_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_16_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_15_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_15_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_14_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_14_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_13_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_13_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_12_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_12_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_11_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_11_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_10_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_10_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_9_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_9_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_8_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_8_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_7_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_7_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_6_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_6_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_5_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_5_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_4_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_4_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_3_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_3_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_2_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_2_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_1_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_1_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_0_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_0_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_18_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_18_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_17_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_17_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_16_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_16_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_15_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_15_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_14_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_14_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_13_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_13_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_12_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_12_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_11_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_11_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_10_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_10_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_9_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_9_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_8_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_8_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_7_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_7_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_6_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_6_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_5_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_5_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_4_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_4_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_3_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_3_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_2_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_2_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_1_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_1_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_0_S\, 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_0_Y\, MSC_net_632, 
        MSC_net_633, MSC_net_634, MSC_net_635, MSC_net_636, 
        MSC_net_637, MSC_net_638, MSC_net_639, MSC_net_640, 
        MSC_net_641, MSC_net_642, MSC_net_643, MSC_net_644, 
        MSC_net_645, MSC_net_646, MSC_net_647, MSC_net_648, 
        MSC_net_649, MSC_net_650, MSC_net_651, MSC_net_652, 
        MSC_net_653, MSC_net_654, MSC_net_655, MSC_net_656, 
        MSC_net_657, MSC_net_658, MSC_net_659, MSC_net_660, 
        MSC_net_661, MSC_net_662, MSC_net_663, MSC_net_664, 
        MSC_net_665, MSC_net_666, MSC_net_667, MSC_net_668, 
        MSC_net_669, MSC_net_670, MSC_net_671, MSC_net_672, 
        MSC_net_673, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_17_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_s_18_FCO\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_s_18_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_16_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_15_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_14_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_13_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_12_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_11_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_10_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_9_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_8_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_7_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_6_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_5_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_4_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_3_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_2_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_1_Y\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_0_S\, 
        \FSM_RATE_LIM_PROC.op_minus.un1_s_set_ref_cry_0_Y\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_18_RNI0UL9_S\, 
        \FSM_RATE_LIM_PROC.un1_s_set_ref_cry_18_RNI0UL9_Y\, 
        MSC_net_697, MSC_net_698, MSC_net_699, MSC_net_700, 
        MSC_net_701, MSC_net_702, MSC_net_703, MSC_net_704, 
        MSC_net_705, MSC_net_706, MSC_net_707, MSC_net_708, 
        MSC_net_709, MSC_net_710, MSC_net_711, MSC_net_712, 
        MSC_net_713, MSC_net_714, MSC_net_715, MSC_net_716, 
        MSC_net_717, MSC_net_718, MSC_net_719 : std_logic;

    for all : accumulator_rl
	Use entity work.accumulator_rl(DEF_ARCH);
begin 

    rl_out_o(17) <= \rl_out_o\(17);
    rl_out_o(16) <= \rl_out_o\(16);
    rl_out_o(15) <= \rl_out_o\(15);
    rl_out_o(14) <= \rl_out_o\(14);
    rl_out_o(13) <= \rl_out_o\(13);
    rl_out_o(12) <= \rl_out_o\(12);
    rl_out_o(11) <= \rl_out_o\(11);
    rl_out_o(10) <= \rl_out_o\(10);
    rl_out_o(9) <= \rl_out_o\(9);
    rl_out_o(8) <= \rl_out_o\(8);
    rl_out_o(7) <= \rl_out_o\(7);
    rl_out_o(6) <= \rl_out_o\(6);
    rl_out_o(5) <= \rl_out_o\(5);
    rl_out_o(4) <= \rl_out_o\(4);
    rl_out_o(3) <= \rl_out_o\(3);
    rl_out_o(2) <= \rl_out_o\(2);
    rl_out_o(1) <= \rl_out_o\(1);
    rl_out_o(0) <= \rl_out_o\(0);
    rl_done_o <= MSC_net_78;


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
RvOGG0e2YCud8xyyGBkBzqN+xa2l3QY/96SAF0e3E/8/MYps61fifnU1EGwK80Fw
3b5Yo9U7sNevL8r4TZTkgFd/egSL1x/6lGZTAaTVZfeQ8yRvkq/glDrmBo7ykl+T
jOjQirijCJIwm67EDp60oMIgWPRSeKE228MX2PQEY3E=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=120275)
`protect data_block
[encoded data, 118400 characters]
35Oq/yQE0hVsWGdU3ucD9Q==

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity mas_pi_spi is

    port( reset_i    : in    std_logic;
          sys_clk_i  : in    std_logic;
          mas_en_i   : in    std_logic;
          sub_i      : in    std_logic;
          mul_a_i    : in    std_logic_vector(17 downto 0);
          mul_b_i    : in    std_logic_vector(17 downto 0);
          add_c_i    : in    std_logic_vector(43 downto 0);
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );

end mas_pi_spi;

architecture DEF_ARCH of mas_pi_spi is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal s_mas_done_dly : std_logic_vector(0 to 0);
    signal product_o_NC : std_logic_vector(43 downto 0);
    signal MSC_net_174, MSC_net_175, MSC_net_176 : std_logic;

begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
gEK98J1G4SEMCrEfkNet9IFMk9yCQSEwgDcHqzpP1V5v3uSkzbwqFEKvT6O4W0Hn
5i2u3EDv91CaDKt1B3AYWEosirk7CL8bvcN5SDB0GoP2nFBazrRDwSln9TMz2jr2
njM/7nDfW8dMX6rSqy50qihseH1NRAm4Zx4YGI9N1gs=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=12005)
`protect data_block
[encoded data, 11776 characters]
zJ2fKdR6nC8OjaojCwTrOA6aJyRE9vjRfc8+1vpN3JI=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity pi_controller_spi is

    port( s_acc_in_0           : in    std_logic_vector(43 downto 0);
          s_acc_out            : out   std_logic_vector(43 downto 0);
          s_output_y           : out   std_logic_vector(17 downto 0);
          s_init               : in    std_logic_vector(17 downto 0);
          s_pi_sel_fast        : in    std_logic_vector(1 to 1);
          id_pi_act_input_i    : in    std_logic_vector(17 to 17);
          s_act_input          : in    std_logic_vector(16 downto 0);
          s_pi_sel_i_0         : in    std_logic_vector(1 to 1);
          iq_pi_ref_input_i    : in    std_logic_vector(17 to 17);
          speed_pi_ref_input_i : in    std_logic_vector(17 to 17);
          speed_pi_kp_i        : in    std_logic_vector(17 downto 0);
          iq_pi_kp_i           : in    std_logic_vector(17 downto 0);
          iq_pi_ki_i           : in    std_logic_vector(17 downto 0);
          speed_pi_ki_i        : in    std_logic_vector(17 downto 0);
          reset_i              : in    std_logic;
          sys_clk_i            : in    std_logic;
          s_done               : out   std_logic;
          s_en                 : in    std_logic;
          N_1338               : in    std_logic;
          N_1339               : in    std_logic;
          N_1340               : in    std_logic;
          N_1341               : in    std_logic;
          N_1342               : in    std_logic;
          N_1343               : in    std_logic;
          N_1344               : in    std_logic;
          N_1345               : in    std_logic;
          N_1346               : in    std_logic;
          N_1347               : in    std_logic;
          N_1348               : in    std_logic;
          N_1349               : in    std_logic;
          N_1350               : in    std_logic;
          N_1351               : in    std_logic;
          N_1352               : in    std_logic;
          N_1353               : in    std_logic;
          N_1423               : in    std_logic;
          s_pi_sel_1_rep1      : in    std_logic;
          N_1354               : in    std_logic;
          N_1320               : in    std_logic;
          N_1321               : in    std_logic;
          N_1322               : in    std_logic;
          N_1323               : in    std_logic;
          N_1324               : in    std_logic;
          N_1325               : in    std_logic;
          N_1326               : in    std_logic;
          N_1327               : in    std_logic;
          N_1328               : in    std_logic;
          N_1329               : in    std_logic;
          N_1330               : in    std_logic;
          N_1331               : in    std_logic;
          N_1332               : in    std_logic;
          N_1333               : in    std_logic;
          N_1334               : in    std_logic;
          N_1335               : in    std_logic;
          N_1337               : in    std_logic;
          N_1336               : in    std_logic;
          s_pi_sel_0_rep1      : in    std_logic;
          s_pi_sel_0_rep2      : in    std_logic;
          un3_init_o           : in    std_logic;
          s_start              : in    std_logic
        );

end pi_controller_spi;

architecture DEF_ARCH of pi_controller_spi is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG1
    generic (INIT:std_logic_vector(1 downto 0) := "00");

    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component mas_pi_spi
    port( reset_i    : in    std_logic := 'U';
          sys_clk_i  : in    std_logic := 'U';
          mas_en_i   : in    std_logic := 'U';
          sub_i      : in    std_logic := 'U';
          mul_a_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          mul_b_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          add_c_i    : in    std_logic_vector(43 downto 0) := (others => 'U');
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal s_inew_RNIKNMR_Y : std_logic_vector(16 to 16);
    signal s_piout_i : std_logic_vector(16 downto 0);
    signal s_piout : std_logic_vector(34 downto 1);
    signal s_acc_in : std_logic_vector(43 downto 0);
    signal s_inew : std_logic_vector(43 downto 0);
    signal s_product : std_logic_vector(43 downto 0);
    signal s_pout : std_logic_vector(43 downto 10);
    signal s_mult1_input : std_logic_vector(17 downto 0);
    signal s_mult1_input_6 : std_logic_vector(17 downto 0);
    signal s_add_cin : std_logic_vector(43 downto 0);
    signal s_add_cin_5 : std_logic_vector(43 downto 0);
    signal s_i_init_ds : std_logic_vector(17 downto 0);
    signal s_i_init_ds_2 : std_logic_vector(17 downto 1);
    signal s_state : std_logic_vector(4 downto 0);
    signal s_mult0_input : std_logic_vector(17 downto 0);
    signal s_error : std_logic_vector(17 downto 1);
    signal acc_out_o_3 : std_logic_vector(43 downto 0);
    signal output_y_o_5 : std_logic_vector(17 downto 1);
    signal s_state_ns : std_logic_vector(1 to 1);
    signal s_inew_RNIKNMR_S : std_logic_vector(16 to 16);
    signal s_pout_RNIBIDN1_Y : std_logic_vector(11 to 11);
    signal s_pout_RNI5G4J2_Y : std_logic_vector(12 to 12);
    signal s_pout_RNI2HRE3_Y : std_logic_vector(13 to 13);
    signal s_pout_RNIPCJA4_Y : std_logic_vector(14 to 14);
    signal s_pout_RNIJBB65_Y : std_logic_vector(15 to 15);
    signal s_pout_RNIGD326_Y : std_logic_vector(16 to 16);
    signal s_pout_RNIGIRT6_Y : std_logic_vector(17 to 17);
    signal s_pout_RNIJQJP7_Y : std_logic_vector(18 to 18);
    signal s_pout_RNIP5CL8_Y : std_logic_vector(19 to 19);
    signal s_pout_RNI040G9_Y : std_logic_vector(20 to 20);
    signal s_pout_RNIA5KAA_Y : std_logic_vector(21 to 21);
    signal s_pout_RNIN985B_Y : std_logic_vector(22 to 22);
    signal s_pout_RNI7HSVB_Y : std_logic_vector(23 to 23);
    signal s_pout_RNIHJHQC_Y : std_logic_vector(24 to 24);
    signal s_pout_RNIUO6LD_Y : std_logic_vector(25 to 25);
    signal s_pout_RNIE1SFE_Y : std_logic_vector(26 to 26);
    signal s_pout_RNI1DHAF_Y : std_logic_vector(27 to 27);
    signal s_pout_RNIMQ65G_Y : std_logic_vector(28 to 28);
    signal s_pout_RNIDASVG_Y : std_logic_vector(29 to 29);
    signal s_pout_RNITJIQH_Y : std_logic_vector(30 to 30);
    signal s_pout_RNIFV8LI_Y : std_logic_vector(31 to 31);
    signal s_pout_RNI3DVFJ_Y : std_logic_vector(32 to 32);
    signal s_pout_RNIPSLAK_Y : std_logic_vector(33 to 33);
    signal s_pout_RNI86D5L_Y : std_logic_vector(34 to 34);
    signal s_pout_RNIPH40M_Y : std_logic_vector(35 to 35);
    signal s_pout_RNICVRQM_Y : std_logic_vector(36 to 36);
    signal s_pout_RNI1FJLN_Y : std_logic_vector(37 to 37);
    signal s_pout_RNINVAGO_Y : std_logic_vector(38 to 38);
    signal s_pout_RNIEH2BP_Y : std_logic_vector(39 to 39);
    signal s_pout_RNITRQ5Q_Y : std_logic_vector(40 to 40);
    signal s_pout_RNID7J0R_Y : std_logic_vector(41 to 41);
    signal s_pout_RNIUJBRR_Y : std_logic_vector(42 to 42);
    signal s_pout_RNI2FSGT_FCO : std_logic_vector(43 to 43);
    signal s_pout_RNI2FSGT_Y : std_logic_vector(43 to 43);
    signal s_pout_RNIG14MS_Y : std_logic_vector(43 to 43);
    signal s_piout_0 : std_logic_vector(0 to 0);
    signal s_mult1_input_6_1_1 : std_logic_vector(17 downto 0);
    signal s_state_ns_i_0 : std_logic_vector(0 to 0);
    signal s_iout : std_logic_vector(42 downto 0);
    signal acc_out_o_3_b_A : std_logic_vector(43 to 43);
    signal MSC_net_842, MSC_net_843, MSC_net_844, MSC_net_845, 
        MSC_net_846, MSC_net_847, MSC_net_848, MSC_net_849, 
        MSC_net_850, MSC_net_851, MSC_net_852, MSC_net_853, 
        MSC_net_854, MSC_net_855, MSC_net_856, MSC_net_857, 
        MSC_net_858, MSC_net_859, MSC_net_860, MSC_net_861, 
        MSC_net_862, MSC_net_863, MSC_net_864, MSC_net_865, 
        MSC_net_866, MSC_net_867, MSC_net_868, MSC_net_869, 
        MSC_net_870, MSC_net_871, MSC_net_872, MSC_net_873, 
        MSC_net_874, MSC_net_875, MSC_net_876, MSC_net_877, 
        MSC_net_878, MSC_net_879, MSC_net_880, MSC_net_881, 
        MSC_net_882, MSC_net_883, MSC_net_884, MSC_net_885, 
        MSC_net_886, MSC_net_887, MSC_net_888, MSC_net_889, 
        MSC_net_890, MSC_net_891, MSC_net_892, MSC_net_893, 
        MSC_net_894, MSC_net_895, MSC_net_896, MSC_net_897, 
        MSC_net_898, MSC_net_899, MSC_net_900, MSC_net_901, 
        MSC_net_902, MSC_net_903, MSC_net_904, MSC_net_905, 
        MSC_net_906, MSC_net_907, MSC_net_908, MSC_net_909, 
        MSC_net_910, MSC_net_911, MSC_net_912, MSC_net_913, 
        MSC_net_914, MSC_net_915, MSC_net_916, MSC_net_917, 
        MSC_net_918, MSC_net_919, MSC_net_920, MSC_net_921, 
        MSC_net_922, MSC_net_923, MSC_net_924, MSC_net_925, 
        MSC_net_926, MSC_net_927, MSC_net_928, MSC_net_929, 
        MSC_net_930, MSC_net_931, MSC_net_932, MSC_net_933, 
        MSC_net_934, MSC_net_935, MSC_net_936, MSC_net_937, 
        MSC_net_938, MSC_net_939, MSC_net_940, MSC_net_941, 
        MSC_net_942, MSC_net_943, MSC_net_944, MSC_net_945, 
        MSC_net_946, MSC_net_947, MSC_net_948, MSC_net_949, 
        MSC_net_950, MSC_net_951, MSC_net_952, MSC_net_953, 
        MSC_net_954, MSC_net_955, MSC_net_956, MSC_net_957, 
        MSC_net_958, MSC_net_959, MSC_net_960, MSC_net_961, 
        MSC_net_962, MSC_net_963, MSC_net_964, MSC_net_965, 
        MSC_net_966, MSC_net_967, MSC_net_968, MSC_net_969, 
        MSC_net_970, MSC_net_971, MSC_net_972, MSC_net_973, 
        MSC_net_974, MSC_net_975, MSC_net_976, MSC_net_977, 
        MSC_net_978, MSC_net_979, MSC_net_980, MSC_net_981, 
        MSC_net_982, MSC_net_983, MSC_net_984, MSC_net_985, 
        MSC_net_986, MSC_net_987, MSC_net_988, MSC_net_989, 
        MSC_net_990, MSC_net_991, MSC_net_992, MSC_net_993, 
        MSC_net_994, MSC_net_995, MSC_net_996, MSC_net_997, 
        MSC_net_998, MSC_net_999, MSC_net_1000, MSC_net_1001, 
        MSC_net_1002, MSC_net_1003, MSC_net_1004, MSC_net_1005, 
        MSC_net_1006, MSC_net_1007, MSC_net_1008, MSC_net_1009, 
        MSC_net_1010, MSC_net_1011, MSC_net_1012, MSC_net_1013, 
        MSC_net_1014, MSC_net_1015, MSC_net_1016, MSC_net_1017, 
        MSC_net_1018, MSC_net_1019, MSC_net_1020, MSC_net_1021, 
        MSC_net_1022, MSC_net_1023, MSC_net_1024, MSC_net_1025, 
        MSC_net_1026, MSC_net_1027, MSC_net_1028, MSC_net_1029, 
        MSC_net_1030, MSC_net_1031, MSC_net_1032, MSC_net_1033, 
        MSC_net_1034, MSC_net_1035, MSC_net_1036, MSC_net_1037, 
        MSC_net_1038, MSC_net_1039, MSC_net_1040, MSC_net_1041, 
        MSC_net_1042, MSC_net_1043, MSC_net_1044, MSC_net_1045, 
        MSC_net_1046, MSC_net_1047, MSC_net_1048, MSC_net_1049, 
        MSC_net_1050, MSC_net_1051, MSC_net_1052, MSC_net_1053, 
        MSC_net_1054, MSC_net_1055, MSC_net_1056, MSC_net_1057, 
        MSC_net_1058, MSC_net_1059, MSC_net_1060, MSC_net_1061, 
        MSC_net_1062, MSC_net_1063, MSC_net_1064, MSC_net_1065, 
        MSC_net_1066, MSC_net_1067, MSC_net_1068, MSC_net_1069, 
        MSC_net_1070, MSC_net_1071, MSC_net_1072, MSC_net_1073, 
        MSC_net_1074, MSC_net_1075, MSC_net_1076, MSC_net_1077, 
        MSC_net_1078, MSC_net_1079, MSC_net_1080, MSC_net_1081, 
        MSC_net_1082, MSC_net_1083, MSC_net_1084, MSC_net_1085, 
        MSC_net_1086, MSC_net_1087, MSC_net_1088, MSC_net_1089, 
        MSC_net_1090, MSC_net_1091, MSC_net_1092, MSC_net_1093, 
        MSC_net_1094, MSC_net_1095, MSC_net_1096, MSC_net_1097, 
        MSC_net_1098, MSC_net_1099, MSC_net_1100, MSC_net_1101, 
        MSC_net_1102, MSC_net_1103, MSC_net_1104, MSC_net_1105, 
        MSC_net_1106, MSC_net_1107, MSC_net_1108, MSC_net_1109, 
        MSC_net_1110, MSC_net_1111, MSC_net_1112, MSC_net_1113, 
        MSC_net_1114, MSC_net_1115, MSC_net_1116, MSC_net_1117, 
        MSC_net_1118, MSC_net_1119, MSC_net_1120, MSC_net_1121, 
        MSC_net_1122, MSC_net_1123, MSC_net_1124, MSC_net_1125, 
        MSC_net_1126, MSC_net_1127, MSC_net_1128, MSC_net_1129, 
        MSC_net_1130, MSC_net_1131, MSC_net_1132, MSC_net_1133, 
        MSC_net_1134, MSC_net_1135, MSC_net_1136, MSC_net_1137, 
        MSC_net_1138, MSC_net_1139, MSC_net_1140, MSC_net_1141, 
        MSC_net_1142, MSC_net_1143, MSC_net_1144, MSC_net_1145, 
        MSC_net_1146, MSC_net_1147, MSC_net_1148, MSC_net_1149, 
        MSC_net_1150, MSC_net_1151, MSC_net_1152, MSC_net_1153, 
        MSC_net_1154, MSC_net_1155, MSC_net_1156, MSC_net_1157, 
        MSC_net_1158, MSC_net_1159, MSC_net_1160, MSC_net_1161, 
        MSC_net_1162, MSC_net_1163, MSC_net_1164, MSC_net_1165, 
        MSC_net_1166, MSC_net_1167, MSC_net_1168, MSC_net_1169, 
        MSC_net_1170, MSC_net_1171, MSC_net_1172, MSC_net_1173, 
        MSC_net_1174, MSC_net_1175, MSC_net_1176, MSC_net_1177, 
        MSC_net_1178, MSC_net_1179, MSC_net_1180, MSC_net_1181, 
        MSC_net_1182, MSC_net_1183, MSC_net_1184, MSC_net_1185, 
        MSC_net_1186, MSC_net_1187, MSC_net_1188, MSC_net_1189, 
        MSC_net_1190, MSC_net_1191, MSC_net_1192, MSC_net_1193, 
        MSC_net_1194, MSC_net_1195, MSC_net_1196, MSC_net_1197, 
        MSC_net_1198 : std_logic;

    for all : mas_pi_spi
	Use entity work.mas_pi_spi(DEF_ARCH);
begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
Jn2b+uoaLv/d8XdahtNenjptjvO08CiM+q+G1h2FAOvT5LTuzO4RokW7BWXoElg+
f8hV7Kzm72ET9DqhHn/8Ul2mC9/zvXh6Fgw5l4eu/Ql4En/Z9tD8tr0hcDqC3w26
hYDzYYneOcdAelA5r37xnQITA3U8R+haMgKyM/MyO8A=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=204165)
`protect data_block
[encoded data, 201024 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity pi_scheduler_spi is

    port( s_pi_sel_fast_1      : out   std_logic;
          s_pi_sel_i_0         : out   std_logic_vector(1 to 1);
          speed_pi_output_o    : out   std_logic_vector(17 downto 0);
          iq_pi_output_o       : out   std_logic_vector(17 downto 0);
          id_pi_output_o       : out   std_logic_vector(17 downto 0);
          s_init               : out   std_logic_vector(17 downto 0);
          s_output_y           : in    std_logic_vector(17 downto 0);
          s_acc_out            : in    std_logic_vector(43 downto 0);
          speed_pi_act_input_i : in    std_logic_vector(17 downto 0);
          iq_pi_act_input_i    : in    std_logic_vector(17 downto 0);
          speed_pi_ref_input_i : in    std_logic_vector(16 downto 0);
          iq_pi_ref_input_i    : in    std_logic_vector(16 downto 0);
          speed_init_i         : in    std_logic_vector(17 downto 0);
          iq_init_i            : in    std_logic_vector(17 downto 0);
          id_pi_act_input_i    : in    std_logic_vector(16 downto 0);
          s_act_input          : out   std_logic_vector(16 downto 0);
          s_acc_in             : out   std_logic_vector(43 downto 0);
          reset_i              : in    std_logic;
          sys_clk_i            : in    std_logic;
          id_pi_done_o         : out   std_logic;
          s_done               : in    std_logic;
          iq_pi_done_o         : out   std_logic;
          s_start              : out   std_logic;
          s_pi_sel_1_rep1      : out   std_logic;
          s_pi_sel_0_rep1      : out   std_logic;
          s_pi_sel_0_rep2      : out   std_logic;
          speed_en_i           : in    std_logic;
          idq_en_i             : in    std_logic;
          s_en                 : out   std_logic;
          clear_buffer_i       : in    std_logic;
          speed_pi_start_i     : in    std_logic;
          iq_pi_start_i        : in    std_logic;
          N_1337               : out   std_logic;
          N_1336               : out   std_logic;
          N_1335               : out   std_logic;
          N_1334               : out   std_logic;
          N_1333               : out   std_logic;
          N_1332               : out   std_logic;
          N_1330               : out   std_logic;
          N_1329               : out   std_logic;
          N_1328               : out   std_logic;
          N_1327               : out   std_logic;
          N_1326               : out   std_logic;
          N_1325               : out   std_logic;
          N_1324               : out   std_logic;
          N_1323               : out   std_logic;
          N_1322               : out   std_logic;
          N_1320               : out   std_logic;
          un3_init_o           : out   std_logic;
          N_1423               : out   std_logic;
          N_1354               : out   std_logic;
          N_1353               : out   std_logic;
          N_1352               : out   std_logic;
          N_1351               : out   std_logic;
          N_1350               : out   std_logic;
          N_1349               : out   std_logic;
          N_1348               : out   std_logic;
          N_1347               : out   std_logic;
          N_1346               : out   std_logic;
          N_1345               : out   std_logic;
          N_1344               : out   std_logic;
          N_1343               : out   std_logic;
          N_1342               : out   std_logic;
          N_1341               : out   std_logic;
          N_1340               : out   std_logic;
          N_1339               : out   std_logic;
          N_1338               : out   std_logic;
          N_1331               : out   std_logic;
          N_1321               : out   std_logic;
          id_pi_start_i        : in    std_logic
        );

end pi_scheduler_spi;

architecture DEF_ARCH of pi_scheduler_spi is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component CFG1
    generic (INIT:std_logic_vector(1 downto 0) := "00");

    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

    signal \s_pi_sel_i_0\ : std_logic_vector(1 to 1);
    signal MSC_net_319, MSC_net_322, MSC_net_324, MSC_net_326, 
        MSC_net_327, MSC_net_328, MSC_net_335, MSC_net_336, 
        MSC_net_337, MSC_net_338, MSC_net_339, MSC_net_340, 
        MSC_net_341, MSC_net_342, MSC_net_343, MSC_net_344, 
        MSC_net_345, MSC_net_346, MSC_net_347, MSC_net_348, 
        MSC_net_349, MSC_net_350 : std_logic;
    signal s_speed_pi_acc_in : std_logic_vector(43 downto 0);
    signal s_speed_pi_acc_in_4 : std_logic_vector(43 downto 0);
    signal s_pi_sel : std_logic_vector(1 downto 0);
    signal s_pi_sel_dly : std_logic_vector(1 downto 0);
    signal s_iq_acc_in : std_logic_vector(43 downto 0);
    signal s_id_acc_in : std_logic_vector(43 downto 0);
    signal speed_pi_output_y_o_5 : std_logic_vector(17 downto 0);
    signal s_pi_sel_fast : std_logic_vector(0 to 0);
    signal MSC_net_572, MSC_net_573, MSC_net_574, MSC_net_575, 
        MSC_net_576, MSC_net_577, MSC_net_578, MSC_net_579, 
        MSC_net_580, MSC_net_581, MSC_net_582, MSC_net_583, 
        MSC_net_584, MSC_net_585, MSC_net_586, MSC_net_587, 
        MSC_net_588, MSC_net_589, MSC_net_590, MSC_net_591, 
        MSC_net_592, MSC_net_593, MSC_net_594, MSC_net_595, 
        MSC_net_596, MSC_net_597, MSC_net_598, MSC_net_599, 
        MSC_net_600, MSC_net_601, MSC_net_602, MSC_net_603, 
        MSC_net_604, MSC_net_605, MSC_net_606, MSC_net_607, 
        MSC_net_608, MSC_net_609, MSC_net_610, MSC_net_611, 
        MSC_net_612, MSC_net_613, MSC_net_614, MSC_net_615, 
        MSC_net_616, MSC_net_617, MSC_net_618, MSC_net_619, 
        MSC_net_620, MSC_net_621, MSC_net_622, MSC_net_623, 
        MSC_net_624, MSC_net_625, MSC_net_626, MSC_net_627, 
        MSC_net_628, MSC_net_629, MSC_net_630, MSC_net_631, 
        MSC_net_632, MSC_net_633, MSC_net_634, MSC_net_635, 
        MSC_net_636, MSC_net_637, MSC_net_638, MSC_net_639, 
        MSC_net_640, MSC_net_641, MSC_net_642, MSC_net_643, 
        MSC_net_644, MSC_net_645, MSC_net_646, MSC_net_647, 
        MSC_net_648, MSC_net_649, MSC_net_650, MSC_net_651, 
        MSC_net_652 : std_logic;

begin 

    s_pi_sel_fast_1 <= MSC_net_319;
    s_pi_sel_i_0(1) <= \s_pi_sel_i_0\(1);
    id_pi_done_o <= MSC_net_322;
    iq_pi_done_o <= MSC_net_324;
    s_pi_sel_1_rep1 <= MSC_net_326;
    s_pi_sel_0_rep1 <= MSC_net_327;
    s_pi_sel_0_rep2 <= MSC_net_328;
    N_1337 <= MSC_net_335;
    N_1336 <= MSC_net_336;
    N_1335 <= MSC_net_337;
    N_1334 <= MSC_net_338;
    N_1333 <= MSC_net_339;
    N_1332 <= MSC_net_340;
    N_1330 <= MSC_net_341;
    N_1329 <= MSC_net_342;
    N_1328 <= MSC_net_343;
    N_1327 <= MSC_net_344;
    N_1326 <= MSC_net_345;
    N_1325 <= MSC_net_346;
    N_1324 <= MSC_net_347;
    N_1323 <= MSC_net_348;
    N_1322 <= MSC_net_349;
    N_1320 <= MSC_net_350;


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
GwwS/k9jUAnwWXvXLt3Uja+wEBN5xruuw81W5WIkZuy7twf93HdG8GJWZxrdvUaE
OaSc1UJDt29BB9KtA5D1+lfVDFXAW56QAwUe3WqtY7Wh/KKTSDYEhtimCtWYwmyN
86AF/eVgW6RWl1GdHISE4EekYo/cOfqGq8LWaJJYKj8=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=133120)
`protect data_block
[encoded data, 131072 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity SPEED_ID_IQ_PI is

    port( reset_i              : in    std_logic;
          sys_clk_i            : in    std_logic;
          clear_buffer_i       : in    std_logic;
          speed_en_i           : in    std_logic;
          idq_en_i             : in    std_logic;
          speed_pi_start_i     : in    std_logic;
          id_pi_start_i        : in    std_logic;
          iq_pi_start_i        : in    std_logic;
          speed_init_i         : in    std_logic_vector(17 downto 0);
          id_init_i            : in    std_logic_vector(17 downto 0);
          iq_init_i            : in    std_logic_vector(17 downto 0);
          speed_pi_ref_input_i : in    std_logic_vector(17 downto 0);
          speed_pi_act_input_i : in    std_logic_vector(17 downto 0);
          speed_pi_kp_i        : in    std_logic_vector(17 downto 0);
          speed_pi_ki_i        : in    std_logic_vector(17 downto 0);
          speed_pi_ymax_i      : in    std_logic_vector(17 downto 0);
          speed_pi_ymin_i      : in    std_logic_vector(17 downto 0);
          id_pi_ref_input_i    : in    std_logic_vector(17 downto 0);
          id_pi_act_input_i    : in    std_logic_vector(17 downto 0);
          id_pi_kp_i           : in    std_logic_vector(17 downto 0);
          id_pi_ki_i           : in    std_logic_vector(17 downto 0);
          idq_pi_ymax_i        : in    std_logic_vector(17 downto 0);
          idq_pi_ymin_i        : in    std_logic_vector(17 downto 0);
          iq_pi_ref_input_i    : in    std_logic_vector(17 downto 0);
          iq_pi_act_input_i    : in    std_logic_vector(17 downto 0);
          iq_pi_kp_i           : in    std_logic_vector(17 downto 0);
          iq_pi_ki_i           : in    std_logic_vector(17 downto 0);
          speed_pi_done_o      : out   std_logic;
          id_pi_done_o         : out   std_logic;
          iq_pi_done_o         : out   std_logic;
          speed_pi_output_o    : out   std_logic_vector(17 downto 0);
          id_pi_output_o       : out   std_logic_vector(17 downto 0);
          iq_pi_output_o       : out   std_logic_vector(17 downto 0)
        );

end SPEED_ID_IQ_PI;

architecture DEF_ARCH of SPEED_ID_IQ_PI is 

  component pi_controller_spi
    port( s_acc_in_0           : in    std_logic_vector(43 downto 0) := (others => 'U');
          s_acc_out            : out   std_logic_vector(43 downto 0);
          s_output_y           : out   std_logic_vector(17 downto 0);
          s_init               : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_pi_sel_fast        : in    std_logic_vector(1 to 1) := (others => 'U');
          id_pi_act_input_i    : in    std_logic_vector(17 to 17) := (others => 'U');
          s_act_input          : in    std_logic_vector(16 downto 0) := (others => 'U');
          s_pi_sel_i_0         : in    std_logic_vector(1 to 1) := (others => 'U');
          iq_pi_ref_input_i    : in    std_logic_vector(17 to 17) := (others => 'U');
          speed_pi_ref_input_i : in    std_logic_vector(17 to 17) := (others => 'U');
          speed_pi_kp_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_pi_kp_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_pi_ki_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_ki_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          reset_i              : in    std_logic := 'U';
          sys_clk_i            : in    std_logic := 'U';
          s_done               : out   std_logic;
          s_en                 : in    std_logic := 'U';
          N_1338               : in    std_logic := 'U';
          N_1339               : in    std_logic := 'U';
          N_1340               : in    std_logic := 'U';
          N_1341               : in    std_logic := 'U';
          N_1342               : in    std_logic := 'U';
          N_1343               : in    std_logic := 'U';
          N_1344               : in    std_logic := 'U';
          N_1345               : in    std_logic := 'U';
          N_1346               : in    std_logic := 'U';
          N_1347               : in    std_logic := 'U';
          N_1348               : in    std_logic := 'U';
          N_1349               : in    std_logic := 'U';
          N_1350               : in    std_logic := 'U';
          N_1351               : in    std_logic := 'U';
          N_1352               : in    std_logic := 'U';
          N_1353               : in    std_logic := 'U';
          N_1423               : in    std_logic := 'U';
          s_pi_sel_1_rep1      : in    std_logic := 'U';
          N_1354               : in    std_logic := 'U';
          N_1320               : in    std_logic := 'U';
          N_1321               : in    std_logic := 'U';
          N_1322               : in    std_logic := 'U';
          N_1323               : in    std_logic := 'U';
          N_1324               : in    std_logic := 'U';
          N_1325               : in    std_logic := 'U';
          N_1326               : in    std_logic := 'U';
          N_1327               : in    std_logic := 'U';
          N_1328               : in    std_logic := 'U';
          N_1329               : in    std_logic := 'U';
          N_1330               : in    std_logic := 'U';
          N_1331               : in    std_logic := 'U';
          N_1332               : in    std_logic := 'U';
          N_1333               : in    std_logic := 'U';
          N_1334               : in    std_logic := 'U';
          N_1335               : in    std_logic := 'U';
          N_1337               : in    std_logic := 'U';
          N_1336               : in    std_logic := 'U';
          s_pi_sel_0_rep1      : in    std_logic := 'U';
          s_pi_sel_0_rep2      : in    std_logic := 'U';
          un3_init_o           : in    std_logic := 'U';
          s_start              : in    std_logic := 'U'
        );
  end component;

  component pi_scheduler_spi
    port( s_pi_sel_fast_1      : out   std_logic;
          s_pi_sel_i_0         : out   std_logic_vector(1 to 1);
          speed_pi_output_o    : out   std_logic_vector(17 downto 0);
          iq_pi_output_o       : out   std_logic_vector(17 downto 0);
          id_pi_output_o       : out   std_logic_vector(17 downto 0);
          s_init               : out   std_logic_vector(17 downto 0);
          s_output_y           : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_acc_out            : in    std_logic_vector(43 downto 0) := (others => 'U');
          speed_pi_act_input_i : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_pi_act_input_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_ref_input_i : in    std_logic_vector(16 downto 0) := (others => 'U');
          iq_pi_ref_input_i    : in    std_logic_vector(16 downto 0) := (others => 'U');
          speed_init_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_init_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          id_pi_act_input_i    : in    std_logic_vector(16 downto 0) := (others => 'U');
          s_act_input          : out   std_logic_vector(16 downto 0);
          s_acc_in             : out   std_logic_vector(43 downto 0);
          reset_i              : in    std_logic := 'U';
          sys_clk_i            : in    std_logic := 'U';
          id_pi_done_o         : out   std_logic;
          s_done               : in    std_logic := 'U';
          iq_pi_done_o         : out   std_logic;
          s_start              : out   std_logic;
          s_pi_sel_1_rep1      : out   std_logic;
          s_pi_sel_0_rep1      : out   std_logic;
          s_pi_sel_0_rep2      : out   std_logic;
          speed_en_i           : in    std_logic := 'U';
          idq_en_i             : in    std_logic := 'U';
          s_en                 : out   std_logic;
          clear_buffer_i       : in    std_logic := 'U';
          speed_pi_start_i     : in    std_logic := 'U';
          iq_pi_start_i        : in    std_logic := 'U';
          N_1337               : out   std_logic;
          N_1336               : out   std_logic;
          N_1335               : out   std_logic;
          N_1334               : out   std_logic;
          N_1333               : out   std_logic;
          N_1332               : out   std_logic;
          N_1330               : out   std_logic;
          N_1329               : out   std_logic;
          N_1328               : out   std_logic;
          N_1327               : out   std_logic;
          N_1326               : out   std_logic;
          N_1325               : out   std_logic;
          N_1324               : out   std_logic;
          N_1323               : out   std_logic;
          N_1322               : out   std_logic;
          N_1320               : out   std_logic;
          un3_init_o           : out   std_logic;
          N_1423               : out   std_logic;
          N_1354               : out   std_logic;
          N_1353               : out   std_logic;
          N_1352               : out   std_logic;
          N_1351               : out   std_logic;
          N_1350               : out   std_logic;
          N_1349               : out   std_logic;
          N_1348               : out   std_logic;
          N_1347               : out   std_logic;
          N_1346               : out   std_logic;
          N_1345               : out   std_logic;
          N_1344               : out   std_logic;
          N_1343               : out   std_logic;
          N_1342               : out   std_logic;
          N_1341               : out   std_logic;
          N_1340               : out   std_logic;
          N_1339               : out   std_logic;
          N_1338               : out   std_logic;
          N_1331               : out   std_logic;
          N_1321               : out   std_logic;
          id_pi_start_i        : in    std_logic := 'U'
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal s_acc_out : std_logic_vector(43 downto 0);
    signal s_output_y : std_logic_vector(17 downto 0);
    signal s_init : std_logic_vector(17 downto 0);
    signal s_acc_in : std_logic_vector(43 downto 0);
    signal s_act_input : std_logic_vector(16 downto 0);
    signal \PI_SCHEDULER_INST.s_pi_sel_i_0\ : 
        std_logic_vector(1 to 1);
    signal \PI_SCHEDULER_INST.s_pi_sel_fast\ : 
        std_logic_vector(1 to 1);
    signal MSC_net_550, MSC_net_551, MSC_net_552, MSC_net_553, 
        \PI_SCHEDULER_INST.op_eq.un3_init_o\, MSC_net_555, 
        MSC_net_556, MSC_net_557, MSC_net_558, MSC_net_559, 
        MSC_net_560, MSC_net_561, MSC_net_562, MSC_net_563, 
        MSC_net_564, MSC_net_565, MSC_net_566, MSC_net_567, 
        MSC_net_568, MSC_net_569, MSC_net_570, MSC_net_571, 
        MSC_net_572, MSC_net_573, MSC_net_574, MSC_net_575, 
        MSC_net_576, MSC_net_577, MSC_net_578, MSC_net_579, 
        MSC_net_580, MSC_net_581, MSC_net_582, MSC_net_583, 
        MSC_net_584, MSC_net_585, MSC_net_586, MSC_net_587, 
        MSC_net_588, MSC_net_589, MSC_net_590, 
        \PI_SCHEDULER_INST.s_pi_sel_1_rep1\, 
        \PI_SCHEDULER_INST.s_pi_sel_0_rep1\, 
        \PI_SCHEDULER_INST.s_pi_sel_0_rep2\ : std_logic;

    for all : pi_controller_spi
	Use entity work.pi_controller_spi(DEF_ARCH);
    for all : pi_scheduler_spi
	Use entity work.pi_scheduler_spi(DEF_ARCH);
begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
KmHpIdD8x9xohSc1k0lm6Cs/GTdkuQnFnt8bBCSKsMTSemFu8Xdmazfek7e75Ds5
zLYmfOcBa9I2kJGDa3+t5EHQ5E7LxSS0bvTddwP8gqaC39/Q0B409GwFoAgJ6DH4
T9W8P30dcURK+aSavQDN/VqbCElzOBEzx4QJrFYu86g=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=35600)
`protect data_block
[encoded data, 35008 characters]
FGJ+/qsP2FM0hDBfZ2YEX22CHUCBSu6lslzVxfVXQI8=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity SEQ_CONTROLLER is

    port( reset_i         : in    std_logic;
          sys_clk_i       : in    std_logic;
          fault_i         : in    std_logic;
          start_motor_i   : in    std_logic;
          stop_motor_i    : in    std_logic;
          fault_clear_i   : in    std_logic;
          speed_ref_i     : in    std_logic_vector(17 downto 0);
          speed_cl_i      : in    std_logic_vector(17 downto 0);
          vq_i            : in    std_logic_vector(17 downto 0);
          max_ar_i        : in    std_logic_vector(3 downto 0);
          calib_done_i    : in    std_logic;
          pwm_midmatch_i  : in    std_logic;
          foc_done_i      : in    std_logic;
          config_reg_i    : in    std_logic_vector(3 downto 0);
          adc_start_o     : out   std_logic;
          cl_status_o     : out   std_logic;
          en_idq_pi_o     : out   std_logic;
          en_pwm_o        : out   std_logic;
          motor_stopped_o : out   std_logic;
          reset_rl_o      : out   std_logic;
          soft_stop_o     : out   std_logic;
          sensor_reset_o  : out   std_logic;
          state_o         : out   std_logic_vector(3 downto 0)
        );

end SEQ_CONTROLLER;

architecture DEF_ARCH of SEQ_CONTROLLER is 

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal MSC_net_78, MSC_net_82 : std_logic;
    signal s_state : std_logic_vector(8 downto 1);
    signal s_restart_count : std_logic_vector(3 downto 0);
    signal s_adctrig_count : std_logic_vector(12 downto 0);
    signal s_state_ns : std_logic_vector(6 downto 0);
    signal s_state_ns_0_0_0_a2 : std_logic_vector(0 to 0);
    signal inf_abs1 : std_logic_vector(17 downto 0);
    signal inf_abs0 : std_logic_vector(17 downto 0);
    signal s_state_ns_0_a3_0 : std_logic_vector(6 to 6);
    signal s_adctrig_count_cry : std_logic_vector(11 downto 0);
    signal s_adctrig_count_s : std_logic_vector(12 downto 0);
    signal s_sensor_calib_count : std_logic_vector(13 downto 0);
    signal s_sensor_calib_count_cry : 
        std_logic_vector(12 downto 0);
    signal s_sensor_calib_count_s : 
        std_logic_vector(13 downto 0);
    signal s_state_ns_i_i_a4_0_0_o2_6 : std_logic_vector(2 to 2);
    signal s_state_ns_i_i_a4_0_0_o2_7 : std_logic_vector(2 to 2);
    signal s_state_ns_i_i_a4_0_0_o2_8 : std_logic_vector(2 to 2);
    signal s_state_ns_i_i_a4_0_0_o2_9 : std_logic_vector(2 to 2);
    signal s_state_ns_0_a3_1_0 : std_logic_vector(6 to 6);
    signal s_state_ns_i_i_a2_4_a2_0_a3_0 : 
        std_logic_vector(1 to 1);
    signal s_state_ns_0_0_0_a3_2_0 : std_logic_vector(4 to 4);
    signal s_state_ns_i_3_0_i_0_a3_2 : std_logic_vector(7 to 7);
    signal s_state_ns_0_0 : std_logic_vector(6 to 6);
    signal s_state_ns_0_0_0_1 : std_logic_vector(0 to 0);
    signal s_state_ns_0_0_0_0 : std_logic_vector(4 downto 3);
    signal s_state_ns_0_0_0_2 : std_logic_vector(4 downto 3);
    signal s_state_ns_0_0_0_1_1 : std_logic_vector(0 to 0);
    signal s_sensor_calib_count_RNICLE93_Y : 
        std_logic_vector(12 to 12);
    signal s_sensor_calib_count_RNO_FCO : 
        std_logic_vector(13 to 13);
    signal s_sensor_calib_count_RNO_Y : 
        std_logic_vector(13 to 13);
    signal s_sensor_calib_count_RNI3PI33_Y : 
        std_logic_vector(11 to 11);
    signal s_sensor_calib_count_RNIRTMT2_Y : 
        std_logic_vector(10 to 10);
    signal s_sensor_calib_count_RNIK3RN2_Y : 
        std_logic_vector(9 to 9);
    signal s_sensor_calib_count_RNILCCG2_Y : 
        std_logic_vector(8 to 8);
    signal s_sensor_calib_count_RNINMT82_Y : 
        std_logic_vector(7 to 7);
    signal s_sensor_calib_count_RNIQ1F12_Y : 
        std_logic_vector(6 to 6);
    signal s_sensor_calib_count_RNIUD0Q1_Y : 
        std_logic_vector(5 to 5);
    signal s_sensor_calib_count_RNI3RHI1_Y : 
        std_logic_vector(4 to 4);
    signal s_sensor_calib_count_RNI993B1_Y : 
        std_logic_vector(3 to 3);
    signal s_sensor_calib_count_RNIGOK31_Y : 
        std_logic_vector(2 to 2);
    signal s_sensor_calib_count_RNIO86S_Y : 
        std_logic_vector(1 to 1);
    signal s_sensor_calib_count_RNI1QNK_Y : 
        std_logic_vector(0 to 0);
    signal s_sensor_calib_count_RNIBC9D_S : 
        std_logic_vector(13 to 13);
    signal s_sensor_calib_count_RNIBC9D_Y : 
        std_logic_vector(13 to 13);
    signal s_adctrig_count_cry_Y : std_logic_vector(11 downto 0);
    signal s_adctrig_count_s_FCO : std_logic_vector(12 to 12);
    signal s_adctrig_count_s_Y : std_logic_vector(12 to 12);
    signal s_adctrig_count_cry_cy_S : std_logic_vector(0 to 0);
    signal s_adctrig_count_cry_cy_Y : std_logic_vector(0 to 0);
    signal MSC_net_267, MSC_net_268, MSC_net_269, MSC_net_270, 
        MSC_net_271, MSC_net_272, \ADC_START_PROC.adc_start_o_3\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs\, 
        \EN_SPEED_PI_PROC.un110_s_state\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs\, 
        \EN_SPEED_PI_PROC.un111_s_state\, MSC_net_278, 
        MSC_net_279, MSC_net_280, MSC_net_281, MSC_net_282, 
        MSC_net_283, MSC_net_284, MSC_net_285, MSC_net_286, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_0_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_1_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_2_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_3_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_4_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_5_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_6_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_7_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_8_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_9_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_10_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_11_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_12_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_13_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_14_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_15_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_16_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_0_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_1_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_2_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_3_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_4_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_5_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_6_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_7_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_8_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_9_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_10_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_11_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_12_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_13_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_14_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_15_Z\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_16_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_0_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_1_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_2_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_3_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_4_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_5_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_6_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_7_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_8_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_9_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_10_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_11_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_12_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_13_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_14\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_15\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_16\, 
        MSC_net_338, MSC_net_339, MSC_net_340, MSC_net_341, 
        \ADC_START_PROC.op_eq.un98_s_state_Z\, MSC_net_343, 
        MSC_net_344, MSC_net_345, MSC_net_346, MSC_net_347, 
        MSC_net_348, MSC_net_349, MSC_net_350, MSC_net_351, 
        MSC_net_352, MSC_net_353, MSC_net_354, MSC_net_355, 
        MSC_net_356, MSC_net_357, MSC_net_358, MSC_net_359, 
        MSC_net_360, MSC_net_361, MSC_net_362, MSC_net_363, 
        MSC_net_364, MSC_net_365, MSC_net_366, MSC_net_367, 
        MSC_net_368, MSC_net_369, MSC_net_370, MSC_net_371, 
        MSC_net_372, MSC_net_373, MSC_net_374, MSC_net_375, 
        MSC_net_376, MSC_net_377, MSC_net_378, MSC_net_379, 
        MSC_net_380, MSC_net_381, MSC_net_382, MSC_net_383, 
        MSC_net_384, MSC_net_385, MSC_net_386, MSC_net_387, 
        MSC_net_388, MSC_net_389, MSC_net_390, MSC_net_391, 
        MSC_net_392, MSC_net_393, MSC_net_394, MSC_net_395, 
        MSC_net_396, 
        \FSM_SEQ_CONTROLLER_PROC.op_eq.un8_fault_i_NE_0_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.op_eq.un8_fault_i_NE_1_Z\, 
        \ADC_START_PROC.op_eq.un98_s_state_7_Z\, 
        \ADC_START_PROC.op_eq.un98_s_state_8_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.op_eq.un6_s_soft_stop_9_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.op_eq.un6_s_soft_stop_10_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.op_eq.un6_s_soft_stop_11_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.op_eq.un6_s_soft_stop_12_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.op_eq.un6_s_soft_stop_14_Z\, 
        \FSM_SEQ_CONTROLLER_PROC.op_eq.un6_s_soft_stop_15_Z\, 
        MSC_net_407, MSC_net_408, MSC_net_409, MSC_net_410, 
        MSC_net_411, MSC_net_412, MSC_net_413, MSC_net_414, 
        MSC_net_415, MSC_net_416, MSC_net_417, MSC_net_418, 
        MSC_net_419, MSC_net_420, 
        \ADC_START_PROC.op_eq.un98_s_state_1_Z\, MSC_net_422, 
        MSC_net_423, MSC_net_424, MSC_net_425, MSC_net_426, 
        MSC_net_427, MSC_net_428, MSC_net_429, MSC_net_430, 
        MSC_net_431, MSC_net_432, MSC_net_433, MSC_net_434, 
        MSC_net_435, MSC_net_436, MSC_net_437, MSC_net_438, 
        MSC_net_439, MSC_net_440, MSC_net_441, MSC_net_442, 
        MSC_net_443, MSC_net_444, MSC_net_445, MSC_net_446, 
        MSC_net_447, MSC_net_448, MSC_net_449, MSC_net_450, 
        MSC_net_451, MSC_net_452, MSC_net_453, MSC_net_454, 
        MSC_net_455, MSC_net_456, MSC_net_457, MSC_net_458, 
        MSC_net_459, MSC_net_460, MSC_net_461, MSC_net_462, 
        MSC_net_463, MSC_net_464, MSC_net_465, MSC_net_466, 
        MSC_net_467, MSC_net_468, MSC_net_469, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_17_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_17_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_16_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_16_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_15_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_15_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_14_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_14_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_13_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_13_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_12_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_12_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_11_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_11_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_10_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_10_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_9_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_9_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_8_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_8_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_7_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_7_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_6_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_6_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_5_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_5_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_4_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_4_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_3_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_3_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_2_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_2_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_1_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_1_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_0_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un13_s_speed_ref_abs_cry_0_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_17_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_17_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_16_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_16_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_15_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_15_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_14_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_14_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_13_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_13_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_12_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_12_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_11_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_11_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_10_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_10_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_9_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_9_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_8_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_8_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_7_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_7_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_6_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_6_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_5_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_5_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_4_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_4_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_3_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_3_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_2_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_2_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_1_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_1_Y\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_0_S\, 
        \EN_SPEED_PI_PROC.un110_s_state_cry_0_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_13_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_13_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_12_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_12_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_11_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_11_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_10_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_10_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_9_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_9_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_8_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_8_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_7_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_7_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_6_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_6_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_5_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_5_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_4_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_4_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_3_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_3_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_2_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_2_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_1_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_1_Y\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_0_S\, 
        \FSM_SEQ_CONTROLLER_PROC.un12_s_vq_i_abs_cry_0_Y\
         : std_logic;

begin 

    en_pwm_o <= MSC_net_78;
    sensor_reset_o <= MSC_net_82;


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
dROrON+nPAtcuW2eU2NrKSekwznQwtqQLlZ31z9qRjxfh+XLrhIrpGzC0J1uV97w
dNkof7+PQDiWG2Rcpr2L+pxTTmDYRpQE3FuLc5550JB662zHRCqBpqJO8XSgxzqa
6JfmeWs8Q39XS6nQo6ZEyDBcYW3B+X8aqejlnJ/lPu4=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=101465)
`protect data_block
[encoded data, 99904 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity cordic_rot_foc is

    port( s_xo          : out   std_logic_vector(17 downto 0);
          s_yo          : out   std_logic_vector(17 downto 0);
          s_yi_0        : in    std_logic;
          s_yi_1        : in    std_logic;
          s_yi_2        : in    std_logic;
          s_yi_3        : in    std_logic;
          s_yi_4        : in    std_logic;
          s_yi_5        : in    std_logic;
          s_yi_6        : in    std_logic;
          s_yi_7        : in    std_logic;
          s_yi_8        : in    std_logic;
          s_yi_10       : in    std_logic;
          s_yi_11       : in    std_logic;
          s_yi_12       : in    std_logic;
          s_yi_13       : in    std_logic;
          s_yi_14       : in    std_logic;
          s_yi_15       : in    std_logic;
          s_yi_16       : in    std_logic;
          s_xi          : in    std_logic_vector(16 downto 0);
          ibeta_i       : in    std_logic_vector(10 to 10);
          vq_i          : in    std_logic_vector(10 to 10);
          reset_i       : in    std_logic;
          sys_clk_i     : in    std_logic;
          N_605         : in    std_logic;
          N_606         : in    std_logic;
          N_607         : in    std_logic;
          N_608         : in    std_logic;
          N_609         : in    std_logic;
          N_592         : in    std_logic;
          N_593         : in    std_logic;
          N_594         : in    std_logic;
          N_595         : in    std_logic;
          N_596         : in    std_logic;
          N_597         : in    std_logic;
          N_598         : in    std_logic;
          N_599         : in    std_logic;
          N_600         : in    std_logic;
          N_601         : in    std_logic;
          N_602         : in    std_logic;
          N_603         : in    std_logic;
          N_604         : in    std_logic;
          s_cordic_done : out   std_logic;
          start_ipark_i : in    std_logic;
          start_park_i  : in    std_logic;
          s_start       : in    std_logic
        );

end cordic_rot_foc;

architecture DEF_ARCH of cordic_rot_foc is 

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal x_o_5 : std_logic_vector(17 downto 0);
    signal s_index : std_logic_vector(3 downto 0);
    signal s_index_7 : std_logic_vector(0 to 0);
    signal s_index_7_iv_i_0 : std_logic_vector(3 downto 1);
    signal y_o_3_1 : std_logic_vector(17 downto 0);
    signal s_theta_c : std_logic_vector(17 downto 0);
    signal s_theta_c_9 : std_logic_vector(17 downto 0);
    signal un1_s_theta_c3_1_i_0 : std_logic_vector(0 to 0);
    signal s_xi_rot : std_logic_vector(17 downto 0);
    signal s_xi_rot_7 : std_logic_vector(17 downto 0);
    signal un1_s_theta_c3_i_0 : std_logic_vector(0 to 0);
    signal s_yi_rot : std_logic_vector(17 downto 1);
    signal s_yi_rot_7 : std_logic_vector(17 downto 0);
    signal s_theta_i : std_logic_vector(17 downto 0);
    signal s_state : std_logic_vector(0 to 0);
    signal un1_s_yout : std_logic_vector(17 downto 1);
    signal s_yi_rot_7_bm : std_logic_vector(9 to 9);
    signal un1_s_xout : std_logic_vector(17 downto 0);
    signal un4_s_theta_c : std_logic_vector(14 downto 12);
    signal y_o_3 : std_logic_vector(17 downto 1);
    signal s_theta_i_RNI0KP4_FCO : std_logic_vector(17 to 17);
    signal s_theta_i_RNI0KP4_S : std_logic_vector(17 to 17);
    signal s_theta_i_RNI0KP4_Y : std_logic_vector(17 to 17);
    signal s_xi_rot_RNIVHRG_Y : std_logic_vector(0 to 0);
    signal s_xi_rot_RNIVGTS_Y : std_logic_vector(1 to 1);
    signal s_xi_rot_RNI0HV81_Y : std_logic_vector(2 to 2);
    signal s_xi_rot_RNI2I1L1_Y : std_logic_vector(3 to 3);
    signal s_xi_rot_RNI5K312_Y : std_logic_vector(4 to 4);
    signal s_xi_rot_RNI9N5D2_Y : std_logic_vector(5 to 5);
    signal s_xi_rot_RNIER7P2_Y : std_logic_vector(6 to 6);
    signal s_xi_rot_RNIK0A53_Y : std_logic_vector(7 to 7);
    signal s_xi_rot_RNIR6CH3_Y : std_logic_vector(8 to 8);
    signal s_xi_rot_RNI3EET3_Y : std_logic_vector(9 to 9);
    signal s_xi_rot_RNIJ1QH4_Y : std_logic_vector(10 to 10);
    signal s_xi_rot_RNI4M565_Y : std_logic_vector(11 to 11);
    signal s_xi_rot_RNIMBHQ5_Y : std_logic_vector(12 to 12);
    signal s_xi_rot_RNI92TE6_Y : std_logic_vector(13 to 13);
    signal s_xi_rot_RNITP837_Y : std_logic_vector(14 to 14);
    signal s_xi_rot_RNIIIKN7_Y : std_logic_vector(15 to 15);
    signal s_xi_rot_RNIV6C09_FCO : std_logic_vector(17 to 17);
    signal s_xi_rot_RNIV6C09_Y : std_logic_vector(17 to 17);
    signal s_xi_rot_RNI8C0C8_Y : std_logic_vector(16 to 16);
    signal un4_s_theta_c_1 : std_logic_vector(1 to 1);
    signal MSC_net_346, MSC_net_347, MSC_net_348, MSC_net_349, 
        MSC_net_350, MSC_net_351, MSC_net_352, MSC_net_353, 
        MSC_net_354, MSC_net_355, MSC_net_356, MSC_net_357, 
        MSC_net_358, MSC_net_359, MSC_net_360, MSC_net_361, 
        MSC_net_362, MSC_net_363, MSC_net_364, MSC_net_365, 
        MSC_net_366, MSC_net_367, MSC_net_368, MSC_net_369, 
        MSC_net_370, MSC_net_371, MSC_net_372, MSC_net_373, 
        MSC_net_374, MSC_net_375, MSC_net_376, MSC_net_377, 
        MSC_net_378, MSC_net_379, MSC_net_380, MSC_net_381, 
        MSC_net_382, MSC_net_383, MSC_net_384, MSC_net_385, 
        MSC_net_386, MSC_net_387, MSC_net_388, MSC_net_389, 
        MSC_net_390, MSC_net_391, MSC_net_392, MSC_net_393, 
        MSC_net_394, MSC_net_395, MSC_net_396, MSC_net_397, 
        MSC_net_398, MSC_net_399, MSC_net_400, MSC_net_401, 
        MSC_net_402, MSC_net_403, MSC_net_404, MSC_net_405, 
        MSC_net_406, MSC_net_407, MSC_net_408, MSC_net_409, 
        MSC_net_410, MSC_net_411, MSC_net_412, MSC_net_413, 
        MSC_net_414, MSC_net_415, MSC_net_416, MSC_net_417, 
        MSC_net_418, MSC_net_419, MSC_net_420, MSC_net_421, 
        MSC_net_422, MSC_net_423, MSC_net_424, MSC_net_425, 
        MSC_net_426, MSC_net_427, MSC_net_428, MSC_net_429, 
        MSC_net_430, MSC_net_431, MSC_net_432, MSC_net_433, 
        MSC_net_434, MSC_net_435, MSC_net_436, MSC_net_437, 
        MSC_net_438, MSC_net_439, MSC_net_440, MSC_net_441, 
        MSC_net_442, MSC_net_443, MSC_net_444, MSC_net_445, 
        MSC_net_446, MSC_net_447, MSC_net_448, MSC_net_449, 
        MSC_net_450, MSC_net_451, MSC_net_452, MSC_net_453, 
        MSC_net_454, MSC_net_455, MSC_net_456, MSC_net_457, 
        MSC_net_458, MSC_net_459, MSC_net_460, MSC_net_461, 
        MSC_net_462, MSC_net_463, MSC_net_464, MSC_net_465, 
        MSC_net_466, MSC_net_467, MSC_net_468, MSC_net_469, 
        MSC_net_470, MSC_net_471, MSC_net_472, MSC_net_473, 
        MSC_net_474, MSC_net_475, MSC_net_476, MSC_net_477, 
        MSC_net_478, MSC_net_479, MSC_net_480, MSC_net_481, 
        MSC_net_482, MSC_net_483, MSC_net_484, MSC_net_485, 
        MSC_net_486, MSC_net_487, MSC_net_488, MSC_net_489, 
        MSC_net_490, MSC_net_491, MSC_net_492, MSC_net_493, 
        MSC_net_494, MSC_net_495, MSC_net_496, MSC_net_497, 
        MSC_net_498, MSC_net_499, MSC_net_500, MSC_net_501, 
        MSC_net_502, MSC_net_503, MSC_net_504, MSC_net_505, 
        MSC_net_506, MSC_net_507, MSC_net_508, MSC_net_509, 
        MSC_net_510, MSC_net_511, MSC_net_512, MSC_net_513, 
        MSC_net_514, MSC_net_515, MSC_net_516, MSC_net_517, 
        MSC_net_518, MSC_net_519, MSC_net_520, MSC_net_521, 
        MSC_net_522, MSC_net_523, MSC_net_524, MSC_net_525, 
        MSC_net_526, MSC_net_527, MSC_net_528, MSC_net_529, 
        MSC_net_530, MSC_net_531, MSC_net_532, MSC_net_533, 
        MSC_net_534, MSC_net_535, MSC_net_536, MSC_net_537, 
        MSC_net_538, MSC_net_539, MSC_net_540, MSC_net_541, 
        MSC_net_542, MSC_net_543, MSC_net_544, MSC_net_545, 
        MSC_net_546, MSC_net_547, MSC_net_548, MSC_net_549, 
        MSC_net_550, MSC_net_551, MSC_net_552, MSC_net_553, 
        MSC_net_554, MSC_net_555, MSC_net_556, MSC_net_557, 
        MSC_net_558, MSC_net_559, MSC_net_560, MSC_net_561, 
        MSC_net_562, MSC_net_563, MSC_net_564, MSC_net_565, 
        MSC_net_566, MSC_net_567, MSC_net_568, MSC_net_569, 
        MSC_net_570, MSC_net_571, MSC_net_572, MSC_net_573, 
        MSC_net_574, MSC_net_575, MSC_net_576, MSC_net_577, 
        MSC_net_578, MSC_net_579, MSC_net_580, MSC_net_581, 
        MSC_net_582, MSC_net_583, MSC_net_584, MSC_net_585, 
        MSC_net_586, MSC_net_587, MSC_net_588, MSC_net_589, 
        MSC_net_590, MSC_net_591, MSC_net_592, MSC_net_593, 
        MSC_net_594, MSC_net_595, MSC_net_596, MSC_net_597, 
        MSC_net_598, MSC_net_599, MSC_net_600, MSC_net_601, 
        MSC_net_602, MSC_net_603, MSC_net_604, MSC_net_605, 
        MSC_net_606, MSC_net_607, MSC_net_608, MSC_net_609, 
        MSC_net_610, MSC_net_611, MSC_net_612, MSC_net_613, 
        MSC_net_614, MSC_net_615, MSC_net_616, MSC_net_617, 
        MSC_net_618, MSC_net_619, MSC_net_620, MSC_net_621, 
        MSC_net_622, MSC_net_623, MSC_net_624, MSC_net_625, 
        MSC_net_626, MSC_net_627, MSC_net_628, MSC_net_629, 
        MSC_net_630, MSC_net_631, MSC_net_632, MSC_net_633, 
        MSC_net_634, MSC_net_635, MSC_net_636, MSC_net_637, 
        MSC_net_638, MSC_net_639, MSC_net_640, MSC_net_641, 
        MSC_net_642, MSC_net_643, MSC_net_644, MSC_net_645, 
        MSC_net_646, MSC_net_647, MSC_net_648, MSC_net_649, 
        MSC_net_650, MSC_net_651, MSC_net_652, MSC_net_653, 
        MSC_net_654, MSC_net_655, MSC_net_656, MSC_net_657, 
        MSC_net_658, MSC_net_659, MSC_net_660, MSC_net_661, 
        MSC_net_662, MSC_net_663, MSC_net_664, MSC_net_665, 
        MSC_net_666, MSC_net_667, MSC_net_668, MSC_net_669, 
        MSC_net_670, MSC_net_671, MSC_net_672, MSC_net_673, 
        MSC_net_674, MSC_net_675, MSC_net_676, MSC_net_677, 
        MSC_net_678, MSC_net_679, MSC_net_680, MSC_net_681, 
        MSC_net_682, MSC_net_683, MSC_net_684, MSC_net_685, 
        MSC_net_686, MSC_net_687, MSC_net_688, MSC_net_689, 
        MSC_net_690, MSC_net_691, MSC_net_692, MSC_net_693, 
        MSC_net_694, MSC_net_695, MSC_net_696, MSC_net_697, 
        MSC_net_698, MSC_net_699, MSC_net_700, MSC_net_701, 
        MSC_net_702, MSC_net_703, MSC_net_704, MSC_net_705, 
        MSC_net_706, MSC_net_707, MSC_net_708, MSC_net_709, 
        MSC_net_710, MSC_net_711, MSC_net_712, MSC_net_713, 
        MSC_net_714, MSC_net_715, MSC_net_716, MSC_net_717, 
        MSC_net_718, MSC_net_719, MSC_net_720, MSC_net_721, 
        MSC_net_722, MSC_net_723, MSC_net_724, MSC_net_725, 
        MSC_net_726, MSC_net_727, MSC_net_728, MSC_net_729, 
        MSC_net_730, MSC_net_731, MSC_net_732, MSC_net_733, 
        MSC_net_734, MSC_net_735, MSC_net_736, MSC_net_737, 
        MSC_net_738, MSC_net_739, MSC_net_740, MSC_net_741, 
        MSC_net_742, MSC_net_743, MSC_net_744, MSC_net_745, 
        MSC_net_746, MSC_net_747, MSC_net_748, MSC_net_749, 
        MSC_net_750, MSC_net_751, MSC_net_752, MSC_net_753, 
        MSC_net_754, MSC_net_755, MSC_net_756, MSC_net_757, 
        MSC_net_758, MSC_net_759, MSC_net_760, MSC_net_761, 
        MSC_net_762, MSC_net_763, MSC_net_764, MSC_net_765, 
        MSC_net_766 : std_logic;

begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
hev2EbEtWr3w+Pe+nS1BKEcBYM1vwSHxpUGKu14yQ/ow/TAkzHbgTg2/f2rYm08N
+DIucS9ZKjpe7XLuRb+F4qVcGdi9Fgxaffx1brc4votZckc/YjSWmD74sL7xxMFd
wxjRm4OMd7qjl7AJUjcQy/LkXowYAIQo6mubSymiSU8=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=140835)
`protect data_block
[encoded data, 138624 characters]
+Pc+0alc7wJ8yo4QOBHFGGk6vQTlfo/is/a+dSmOi/o=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity cordic_scale is

    port( s_xo_scale           : out   std_logic_vector(17 downto 0);
          s_product_from_mas   : in    std_logic_vector(26 downto 9);
          s_yo_scale           : out   std_logic_vector(17 downto 0);
          s_mul_a_from_cordic  : out   std_logic_vector(17 downto 0);
          s_mas_sel            : in    std_logic_vector(1 downto 0);
          s_yo                 : in    std_logic_vector(17 downto 0);
          s_xo                 : in    std_logic_vector(17 downto 0);
          reset_i              : in    std_logic;
          sys_clk_i            : in    std_logic;
          s_done_o             : out   std_logic;
          s_mas_en_from_cordic : out   std_logic;
          s_mas_done_to_cordic : in    std_logic;
          s_mas_done_from_mas  : in    std_logic;
          s_cordic_done        : in    std_logic
        );

end cordic_scale;

architecture DEF_ARCH of cordic_scale is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal s_state : std_logic_vector(1 downto 0);
    signal MSC_net_119, MSC_net_120, MSC_net_121, MSC_net_122, 
        MSC_net_123, MSC_net_124, MSC_net_125, MSC_net_126, 
        MSC_net_127, MSC_net_128, MSC_net_129, MSC_net_130, 
        MSC_net_131, MSC_net_132, MSC_net_133, MSC_net_134, 
        MSC_net_135, MSC_net_136, MSC_net_137, MSC_net_138, 
        MSC_net_139, MSC_net_140, MSC_net_141, MSC_net_142, 
        MSC_net_143, MSC_net_144, MSC_net_145, MSC_net_146, 
        MSC_net_147 : std_logic;

begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
ntka0gfVOC9fFgqkgj/t6c0oxgOFXFiQ97+jFOVN+m0dqQ+ct3a7B+yAuOcKXqLh
5kp5Dj/UII1HPRXS8Pas3YBsbAhPsE5vxJmzxL75QEENsgB7lcM/GMmexLT6aPEB
TiKI1HXIcU2dIytbo1rbYx8ZHyM3TTs0+HfZBGBEZzg=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=25850)
`protect data_block
[encoded data, 25408 characters]
gkVN9Eh6jPSrxGExiXSlKDYpeOzF8SLjYvoMf88TBFA=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity cordic_scheduler_foc is

    port( id_o                 : out   std_logic_vector(17 downto 0);
          iq_o                 : out   std_logic_vector(17 downto 0);
          valpha_o             : out   std_logic_vector(17 downto 0);
          vbeta_o              : out   std_logic_vector(17 downto 0);
          ialpha_i             : in    std_logic_vector(17 downto 1);
          vd_i                 : in    std_logic_vector(17 downto 1);
          theta_i              : in    std_logic_vector(17 downto 0);
          ibeta_i              : in    std_logic_vector(17 downto 1);
          vq_i                 : in    std_logic_vector(17 downto 1);
          s_product_from_mas   : in    std_logic_vector(26 downto 9);
          s_mul_a_from_cordic  : out   std_logic_vector(17 downto 0);
          s_mas_sel            : in    std_logic_vector(1 downto 0);
          reset_i              : in    std_logic;
          sys_clk_i            : in    std_logic;
          start_park_i_i_0     : in    std_logic;
          ipark_done_o         : out   std_logic;
          park_done_o          : out   std_logic;
          start_ipark_i        : in    std_logic;
          start_park_i         : in    std_logic;
          s_mas_en_from_cordic : out   std_logic;
          s_mas_done_to_cordic : in    std_logic;
          s_mas_done_from_mas  : in    std_logic
        );

end cordic_scheduler_foc;

architecture DEF_ARCH of cordic_scheduler_foc is 

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component cordic_rot_foc
    port( s_xo          : out   std_logic_vector(17 downto 0);
          s_yo          : out   std_logic_vector(17 downto 0);
          s_yi_0        : in    std_logic := 'U';
          s_yi_1        : in    std_logic := 'U';
          s_yi_2        : in    std_logic := 'U';
          s_yi_3        : in    std_logic := 'U';
          s_yi_4        : in    std_logic := 'U';
          s_yi_5        : in    std_logic := 'U';
          s_yi_6        : in    std_logic := 'U';
          s_yi_7        : in    std_logic := 'U';
          s_yi_8        : in    std_logic := 'U';
          s_yi_10       : in    std_logic := 'U';
          s_yi_11       : in    std_logic := 'U';
          s_yi_12       : in    std_logic := 'U';
          s_yi_13       : in    std_logic := 'U';
          s_yi_14       : in    std_logic := 'U';
          s_yi_15       : in    std_logic := 'U';
          s_yi_16       : in    std_logic := 'U';
          s_xi          : in    std_logic_vector(16 downto 0) := (others => 'U');
          ibeta_i       : in    std_logic_vector(10 to 10) := (others => 'U');
          vq_i          : in    std_logic_vector(10 to 10) := (others => 'U');
          reset_i       : in    std_logic := 'U';
          sys_clk_i     : in    std_logic := 'U';
          N_605         : in    std_logic := 'U';
          N_606         : in    std_logic := 'U';
          N_607         : in    std_logic := 'U';
          N_608         : in    std_logic := 'U';
          N_609         : in    std_logic := 'U';
          N_592         : in    std_logic := 'U';
          N_593         : in    std_logic := 'U';
          N_594         : in    std_logic := 'U';
          N_595         : in    std_logic := 'U';
          N_596         : in    std_logic := 'U';
          N_597         : in    std_logic := 'U';
          N_598         : in    std_logic := 'U';
          N_599         : in    std_logic := 'U';
          N_600         : in    std_logic := 'U';
          N_601         : in    std_logic := 'U';
          N_602         : in    std_logic := 'U';
          N_603         : in    std_logic := 'U';
          N_604         : in    std_logic := 'U';
          s_cordic_done : out   std_logic;
          start_ipark_i : in    std_logic := 'U';
          start_park_i  : in    std_logic := 'U';
          s_start       : in    std_logic := 'U'
        );
  end component;

  component cordic_scale
    port( s_xo_scale           : out   std_logic_vector(17 downto 0);
          s_product_from_mas   : in    std_logic_vector(26 downto 9) := (others => 'U');
          s_yo_scale           : out   std_logic_vector(17 downto 0);
          s_mul_a_from_cordic  : out   std_logic_vector(17 downto 0);
          s_mas_sel            : in    std_logic_vector(1 downto 0) := (others => 'U');
          s_yo                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_xo                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          reset_i              : in    std_logic := 'U';
          sys_clk_i            : in    std_logic := 'U';
          s_done_o             : out   std_logic;
          s_mas_en_from_cordic : out   std_logic;
          s_mas_done_to_cordic : in    std_logic := 'U';
          s_mas_done_from_mas  : in    std_logic := 'U';
          s_cordic_done        : in    std_logic := 'U'
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal s_xo_scale : std_logic_vector(17 downto 0);
    signal s_yo_scale : std_logic_vector(17 downto 0);
    signal s_xi : std_logic_vector(16 downto 0);
    signal s_yi : std_logic_vector(16 downto 0);
    signal s_xo : std_logic_vector(17 downto 0);
    signal s_yo : std_logic_vector(17 downto 0);
    signal MSC_net_312, MSC_net_313, MSC_net_314, MSC_net_315, 
        MSC_net_316, MSC_net_317, MSC_net_318, MSC_net_319, 
        MSC_net_320, MSC_net_321, MSC_net_322, MSC_net_323, 
        MSC_net_324, MSC_net_325, MSC_net_326, MSC_net_327, 
        MSC_net_328, MSC_net_329, MSC_net_330, MSC_net_331, 
        MSC_net_332, MSC_net_333, MSC_net_334, MSC_net_335, 
        MSC_net_336, MSC_net_337 : std_logic;

    for all : cordic_rot_foc
	Use entity work.cordic_rot_foc(DEF_ARCH);
    for all : cordic_scale
	Use entity work.cordic_scale(DEF_ARCH);
begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
TT5yPVLdK99VC6dMuVM2suvAnvV6Q04m8VXcGeowFfkveIgbFTSAhg2YcrRLjmUx
PbawCRKfBaXlO7NoUKcu5EyMH1WWPvQ1JgeCuC3YfSH3vheknKbe3vV7ZyHKByxc
mWZm79pWJR7EP7pEUPjlW5VG+zwpzmd4iexKVPaEEq0=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=46410)
`protect data_block
[encoded data, 45696 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity clarke_foc is

    port( ibeta_o              : out   std_logic_vector(17 downto 0);
          s_product_from_mas   : in    std_logic_vector(26 downto 9);
          ialpha_o             : out   std_logic_vector(17 downto 0);
          ia_i                 : in    std_logic_vector(17 downto 0);
          s_mul_a_from_clarke  : out   std_logic_vector(17 downto 0);
          s_mul_b_from_clarke  : out   std_logic_vector(1 to 1);
          ib_i                 : in    std_logic_vector(17 downto 0);
          s_mas_sel            : in    std_logic_vector(1 downto 0);
          s_mul_b_from_iclarke : in    std_logic_vector(2 to 2);
          s_mul_b_to_mas_0     : out   std_logic;
          s_mul_b_to_mas_7     : out   std_logic;
          reset_i              : in    std_logic;
          sys_clk_i            : in    std_logic;
          clarke_done_o        : out   std_logic;
          s_mas_en_from_clarke : out   std_logic;
          start_clarke_i       : in    std_logic;
          s_mas_done_from_mas  : in    std_logic
        );

end clarke_foc;

architecture DEF_ARCH of clarke_foc is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal \s_mul_b_from_clarke\ : std_logic_vector(1 to 1);
    signal s_state : std_logic_vector(0 to 0);
    signal MSC_net_121, MSC_net_122, MSC_net_123, MSC_net_124, 
        MSC_net_125, MSC_net_126, MSC_net_127, MSC_net_128, 
        MSC_net_129, MSC_net_130, MSC_net_131, MSC_net_132, 
        MSC_net_133, MSC_net_134, MSC_net_135, MSC_net_136, 
        MSC_net_137, MSC_net_138, MSC_net_139, MSC_net_140, 
        MSC_net_141, MSC_net_142, MSC_net_143, MSC_net_144, 
        MSC_net_145, MSC_net_146, MSC_net_147, MSC_net_148, 
        MSC_net_149, MSC_net_150, MSC_net_151, MSC_net_152, 
        MSC_net_153, MSC_net_154, MSC_net_155, MSC_net_156, 
        MSC_net_157, MSC_net_158, MSC_net_159, MSC_net_160, 
        MSC_net_161, MSC_net_162, MSC_net_163, MSC_net_164, 
        MSC_net_165, MSC_net_166, MSC_net_167, MSC_net_168, 
        MSC_net_169, MSC_net_170, MSC_net_171, MSC_net_172, 
        MSC_net_173, MSC_net_174, MSC_net_175, MSC_net_176, 
        MSC_net_177, MSC_net_178, MSC_net_179, MSC_net_180
         : std_logic;

begin 

    s_mul_b_from_clarke(1) <= \s_mul_b_from_clarke\(1);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
X2gCqS9MXEZKErl/O1FLqoxjhnA8nbBuPgBTWFiXCZjMG8g8/UGrEeO/Hc6IisxW
kl/a4RtDTM5DpHzG3V1HW4GkMdo3V8D2l9KEOYqscM2TvjahUJJEMaqhPqw7gUXO
dRMYNulZ0W/XZORt0x0g/DiF5DrYFwK6KumbyGLj/qc=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=27170)
`protect data_block
[encoded data, 26752 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity inverse_clarke_foc is

    port( s_product_from_mas    : in    std_logic_vector(28 downto 11);
          s_mul_a_from_iclarke  : out   std_logic_vector(17 downto 0);
          vbeta_i               : in    std_logic_vector(17 downto 0);
          va_o                  : out   std_logic_vector(17 downto 0);
          valpha_i              : in    std_logic_vector(17 downto 0);
          s_mul_b_from_iclarke  : out   std_logic_vector(2 to 2);
          vb_o                  : out   std_logic_vector(17 downto 1);
          vc_o                  : out   std_logic_vector(17 downto 0);
          s_mas_sel             : in    std_logic_vector(1 downto 0);
          reset_i               : in    std_logic;
          sys_clk_i             : in    std_logic;
          iclarke_done_o        : out   std_logic;
          s_mas_en_from_iclarke : out   std_logic;
          vb_output_o_axb_0_i_0 : out   std_logic;
          start_iclarke_i       : in    std_logic;
          s_mas_done_from_mas   : in    std_logic
        );

end inverse_clarke_foc;

architecture DEF_ARCH of inverse_clarke_foc is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

    signal \va_o\ : std_logic_vector(17 downto 0);
    signal \vc_o\ : std_logic_vector(17 downto 0);
    signal s_vc : std_logic_vector(17 downto 1);
    signal s_state : std_logic_vector(0 to 0);
    signal MSC_net_153, MSC_net_154, MSC_net_155, MSC_net_156, 
        MSC_net_157, MSC_net_158, MSC_net_159, MSC_net_160, 
        MSC_net_161, MSC_net_162, MSC_net_163, MSC_net_164, 
        MSC_net_165, MSC_net_166, MSC_net_167, MSC_net_168, 
        MSC_net_169, MSC_net_170, MSC_net_171, MSC_net_172, 
        MSC_net_173, MSC_net_174, MSC_net_175, MSC_net_176, 
        MSC_net_177, MSC_net_178, MSC_net_179, MSC_net_180, 
        MSC_net_181, MSC_net_182, MSC_net_183, MSC_net_184, 
        MSC_net_185, MSC_net_186, MSC_net_187, MSC_net_188, 
        MSC_net_189, MSC_net_190, MSC_net_191, MSC_net_192, 
        MSC_net_193, MSC_net_194, MSC_net_195, MSC_net_196, 
        MSC_net_197, MSC_net_198, MSC_net_199, MSC_net_200, 
        MSC_net_201, MSC_net_202, MSC_net_203, MSC_net_204, 
        MSC_net_205, MSC_net_206, MSC_net_207, MSC_net_208, 
        MSC_net_209, MSC_net_210, MSC_net_211, MSC_net_212, 
        MSC_net_213, MSC_net_214, MSC_net_215, MSC_net_216, 
        MSC_net_217, MSC_net_218, MSC_net_219, MSC_net_220, 
        MSC_net_221, MSC_net_222, MSC_net_223, MSC_net_224, 
        MSC_net_225, MSC_net_226, MSC_net_227, MSC_net_228, 
        MSC_net_229, MSC_net_230, MSC_net_231, MSC_net_232
         : std_logic;

begin 

    \vc_o\(17 downto 1) <= (OTHERS => 'U'); 
    va_o(17) <= \va_o\(17);
    va_o(16) <= \va_o\(16);
    va_o(15) <= \va_o\(15);
    va_o(14) <= \va_o\(14);
    va_o(13) <= \va_o\(13);
    va_o(12) <= \va_o\(12);
    va_o(11) <= \va_o\(11);
    va_o(10) <= \va_o\(10);
    va_o(9) <= \va_o\(9);
    va_o(8) <= \va_o\(8);
    va_o(7) <= \va_o\(7);
    va_o(6) <= \va_o\(6);
    va_o(5) <= \va_o\(5);
    va_o(4) <= \va_o\(4);
    va_o(3) <= \va_o\(3);
    va_o(2) <= \va_o\(2);
    va_o(1) <= \va_o\(1);
    va_o(0) <= \va_o\(0);
    vc_o(0) <= \vc_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
G/f7IAecReF8nNBbrcqnLdIRxuNZ8Uk52tsYNcr/Sz1xZGmD1DEFvxgHxQu3r3Ph
zunyIoRvLf4A4h/8TWmtVm+E+czV+U9iIEOgzb/MIC/3IRHxh0uKRcFoud6LyL05
PRAjMj7bwmT6OLEmNNq9wbll0gvNlzI5PpR6kvns+JI=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=33000)
`protect data_block
[encoded data, 32448 characters]
mx/dQ4ecEIQzoJcx3rKFutjipH+roENatfYUKordNKE=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity mas_scheduler_foc is

    port( s_mas_sel             : out   std_logic_vector(1 downto 0);
          s_mul_a_from_cordic   : in    std_logic_vector(17 downto 0);
          s_mul_a_from_clarke   : in    std_logic_vector(17 downto 0);
          va_o                  : in    std_logic_vector(17 downto 0);
          s_add_c_to_mas_0      : out   std_logic;
          s_add_c_to_mas_1      : out   std_logic;
          s_add_c_to_mas_2      : out   std_logic;
          s_add_c_to_mas_3      : out   std_logic;
          s_add_c_to_mas_4      : out   std_logic;
          s_add_c_to_mas_5      : out   std_logic;
          s_add_c_to_mas_6      : out   std_logic;
          s_add_c_to_mas_7      : out   std_logic;
          s_add_c_to_mas_8      : out   std_logic;
          s_add_c_to_mas_9      : out   std_logic;
          s_add_c_to_mas_10     : out   std_logic;
          s_add_c_to_mas_11     : out   std_logic;
          s_add_c_to_mas_12     : out   std_logic;
          s_add_c_to_mas_13     : out   std_logic;
          s_add_c_to_mas_14     : out   std_logic;
          s_add_c_to_mas_15     : out   std_logic;
          s_add_c_to_mas_16     : out   std_logic;
          s_add_c_to_mas_33     : out   std_logic;
          s_mul_b_from_iclarke  : in    std_logic_vector(2 to 2);
          s_mul_a_from_iclarke  : in    std_logic_vector(17 downto 0);
          s_mul_a_to_mas        : out   std_logic_vector(17 downto 0);
          s_mul_b_from_clarke   : in    std_logic_vector(1 to 1);
          s_mul_b_to_mas_0      : out   std_logic;
          s_mul_b_to_mas_4      : out   std_logic;
          start_park_i          : in    std_logic;
          start_park_i_i_0      : out   std_logic;
          reset_i               : in    std_logic;
          sys_clk_i             : in    std_logic;
          start_clarke_i        : in    std_logic;
          start_iclarke_i       : in    std_logic;
          start_ipark_i         : in    std_logic;
          s_mas_en_from_cordic  : in    std_logic;
          s_mas_en_from_clarke  : in    std_logic;
          s_mas_done_from_mas   : in    std_logic;
          s_mas_done_to_cordic  : out   std_logic;
          s_mas_en_from_iclarke : in    std_logic;
          s_mas_en_to_mas       : out   std_logic
        );

end mas_scheduler_foc;

architecture DEF_ARCH of mas_scheduler_foc is 

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG1
    generic (INIT:std_logic_vector(1 downto 0) := "00");

    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

    signal \s_mas_sel\ : std_logic_vector(1 downto 0);
    signal MSC_net_112, MSC_net_127, MSC_net_128, MSC_net_129, 
        MSC_net_130, MSC_net_131, MSC_net_132, MSC_net_133, 
        MSC_net_134, MSC_net_135, MSC_net_136, MSC_net_137, 
        MSC_net_138, MSC_net_139, MSC_net_140, MSC_net_141, 
        MSC_net_142, MSC_net_143, MSC_net_144, MSC_net_145, 
        MSC_net_146, MSC_net_147, MSC_net_148, MSC_net_149, 
        MSC_net_150 : std_logic;

begin 

    s_mas_sel(1) <= \s_mas_sel\(1);
    s_mas_sel(0) <= \s_mas_sel\(0);
    s_mul_b_to_mas_0 <= MSC_net_112;


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
WiT/xLWpk5J6ghSDfcog5o0WSVHFR2oTwx8stCvFxSe6hf70ClRInaE3GQ4TFMvQ
8SKI6dmgpHo+0BsCoOlTy54H/FpCS1U9n+d1pJGUA+6z98ptAiZZsAhGebOof3E9
5UjZbMgcw9n8ZAQbpKXqmgO1QUlLUqvprGPyuzfL7Gw=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=17920)
`protect data_block
[encoded data, 17600 characters]
GAzen9wz92pAe61R7yPPwGyly4pSNpzDMdMQHRmbUFU=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity mas_foc is

    port( reset_i    : in    std_logic;
          sys_clk_i  : in    std_logic;
          mas_en_i   : in    std_logic;
          sub_i      : in    std_logic;
          mul_a_i    : in    std_logic_vector(17 downto 0);
          mul_b_i    : in    std_logic_vector(17 downto 0);
          add_c_i    : in    std_logic_vector(43 downto 0);
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );

end mas_foc;

architecture DEF_ARCH of mas_foc is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \product_o\ : std_logic_vector(43 downto 0);
    signal s_mas_done_dly : std_logic_vector(0 to 0);
    signal product_o_NC : std_logic_vector(43 downto 0);
    signal MSC_net_151, MSC_net_152, MSC_net_153, MSC_net_154, 
        MSC_net_155, MSC_net_156, MSC_net_157, MSC_net_158, 
        MSC_net_159, MSC_net_160, MSC_net_161, MSC_net_162, 
        MSC_net_163, MSC_net_164, MSC_net_165, MSC_net_166, 
        MSC_net_167, MSC_net_168, MSC_net_169, MSC_net_170, 
        MSC_net_171, MSC_net_172, MSC_net_173, MSC_net_174, 
        MSC_net_175, MSC_net_176 : std_logic;

begin 

    \product_o\(43 downto 1) <= (OTHERS => 'U'); 
    product_o(43) <= \product_o\(0);
    product_o(42) <= \product_o\(0);
    product_o(41) <= \product_o\(0);
    product_o(40) <= \product_o\(0);
    product_o(39) <= \product_o\(0);
    product_o(38) <= \product_o\(0);
    product_o(37) <= \product_o\(0);
    product_o(36) <= \product_o\(0);
    product_o(35) <= \product_o\(0);
    product_o(34) <= \product_o\(0);
    product_o(33) <= \product_o\(0);
    product_o(32) <= \product_o\(0);
    product_o(31) <= \product_o\(0);
    product_o(30) <= \product_o\(0);
    product_o(29) <= \product_o\(0);
    product_o(8) <= \product_o\(0);
    product_o(7) <= \product_o\(0);
    product_o(6) <= \product_o\(0);
    product_o(5) <= \product_o\(0);
    product_o(4) <= \product_o\(0);
    product_o(3) <= \product_o\(0);
    product_o(2) <= \product_o\(0);
    product_o(1) <= \product_o\(0);
    product_o(0) <= \product_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
Rp88WpWSZn6ma5G6UWKs7DAJu/xU67Cs/xrPM4qOPOaz8LCawiOBfg9QKjJ1ktVu
+DvRYqhRxk7Xg+EvMtgHrGu5iiNVHUJx3nanvMrzbVlcJ3A6f4E2QyoDXqdvhigp
6QG5ZfqcVe0MOOcyEQsonjyfPt9gv+w9LlvSk799Pr4=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=12330)
`protect data_block
[encoded data, 12096 characters]
NFptZrUUN9lUdn6h54P86iQNYL/V07AOYX36zPbdZeY=

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity FOC_TRANSFORMS is

    port( reset_i         : in    std_logic;
          sys_clk_i       : in    std_logic;
          start_clarke_i  : in    std_logic;
          start_park_i    : in    std_logic;
          start_ipark_i   : in    std_logic;
          start_iclarke_i : in    std_logic;
          ia_i            : in    std_logic_vector(17 downto 0);
          ib_i            : in    std_logic_vector(17 downto 0);
          ialpha_i        : in    std_logic_vector(17 downto 0);
          ibeta_i         : in    std_logic_vector(17 downto 0);
          vd_i            : in    std_logic_vector(17 downto 0);
          vq_i            : in    std_logic_vector(17 downto 0);
          valpha_i        : in    std_logic_vector(17 downto 0);
          vbeta_i         : in    std_logic_vector(17 downto 0);
          theta_i         : in    std_logic_vector(17 downto 0);
          clarke_done_o   : out   std_logic;
          park_done_o     : out   std_logic;
          ipark_done_o    : out   std_logic;
          iclarke_done_o  : out   std_logic;
          ialpha_o        : out   std_logic_vector(17 downto 0);
          ibeta_o         : out   std_logic_vector(17 downto 0);
          id_o            : out   std_logic_vector(17 downto 0);
          iq_o            : out   std_logic_vector(17 downto 0);
          valpha_o        : out   std_logic_vector(17 downto 0);
          vbeta_o         : out   std_logic_vector(17 downto 0);
          va_o            : out   std_logic_vector(17 downto 0);
          vb_o            : out   std_logic_vector(17 downto 0);
          vc_o            : out   std_logic_vector(17 downto 0)
        );

end FOC_TRANSFORMS;

architecture DEF_ARCH of FOC_TRANSFORMS is 

  component cordic_scheduler_foc
    port( id_o                 : out   std_logic_vector(17 downto 0);
          iq_o                 : out   std_logic_vector(17 downto 0);
          valpha_o             : out   std_logic_vector(17 downto 0);
          vbeta_o              : out   std_logic_vector(17 downto 0);
          ialpha_i             : in    std_logic_vector(17 downto 1) := (others => 'U');
          vd_i                 : in    std_logic_vector(17 downto 1) := (others => 'U');
          theta_i              : in    std_logic_vector(17 downto 0) := (others => 'U');
          ibeta_i              : in    std_logic_vector(17 downto 1) := (others => 'U');
          vq_i                 : in    std_logic_vector(17 downto 1) := (others => 'U');
          s_product_from_mas   : in    std_logic_vector(26 downto 9) := (others => 'U');
          s_mul_a_from_cordic  : out   std_logic_vector(17 downto 0);
          s_mas_sel            : in    std_logic_vector(1 downto 0) := (others => 'U');
          reset_i              : in    std_logic := 'U';
          sys_clk_i            : in    std_logic := 'U';
          start_park_i_i_0     : in    std_logic := 'U';
          ipark_done_o         : out   std_logic;
          park_done_o          : out   std_logic;
          start_ipark_i        : in    std_logic := 'U';
          start_park_i         : in    std_logic := 'U';
          s_mas_en_from_cordic : out   std_logic;
          s_mas_done_to_cordic : in    std_logic := 'U';
          s_mas_done_from_mas  : in    std_logic := 'U'
        );
  end component;

  component clarke_foc
    port( ibeta_o              : out   std_logic_vector(17 downto 0);
          s_product_from_mas   : in    std_logic_vector(26 downto 9) := (others => 'U');
          ialpha_o             : out   std_logic_vector(17 downto 0);
          ia_i                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_mul_a_from_clarke  : out   std_logic_vector(17 downto 0);
          s_mul_b_from_clarke  : out   std_logic_vector(1 to 1);
          ib_i                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_mas_sel            : in    std_logic_vector(1 downto 0) := (others => 'U');
          s_mul_b_from_iclarke : in    std_logic_vector(2 to 2) := (others => 'U');
          s_mul_b_to_mas_0     : out   std_logic;
          s_mul_b_to_mas_7     : out   std_logic;
          reset_i              : in    std_logic := 'U';
          sys_clk_i            : in    std_logic := 'U';
          clarke_done_o        : out   std_logic;
          s_mas_en_from_clarke : out   std_logic;
          start_clarke_i       : in    std_logic := 'U';
          s_mas_done_from_mas  : in    std_logic := 'U'
        );
  end component;

  component inverse_clarke_foc
    port( s_product_from_mas    : in    std_logic_vector(28 downto 11) := (others => 'U');
          s_mul_a_from_iclarke  : out   std_logic_vector(17 downto 0);
          vbeta_i               : in    std_logic_vector(17 downto 0) := (others => 'U');
          va_o                  : out   std_logic_vector(17 downto 0);
          valpha_i              : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_mul_b_from_iclarke  : out   std_logic_vector(2 to 2);
          vb_o                  : out   std_logic_vector(17 downto 1);
          vc_o                  : out   std_logic_vector(17 downto 0);
          s_mas_sel             : in    std_logic_vector(1 downto 0) := (others => 'U');
          reset_i               : in    std_logic := 'U';
          sys_clk_i             : in    std_logic := 'U';
          iclarke_done_o        : out   std_logic;
          s_mas_en_from_iclarke : out   std_logic;
          vb_output_o_axb_0_i_0 : out   std_logic;
          start_iclarke_i       : in    std_logic := 'U';
          s_mas_done_from_mas   : in    std_logic := 'U'
        );
  end component;

  component mas_scheduler_foc
    port( s_mas_sel             : out   std_logic_vector(1 downto 0);
          s_mul_a_from_cordic   : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_mul_a_from_clarke   : in    std_logic_vector(17 downto 0) := (others => 'U');
          va_o                  : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_add_c_to_mas_0      : out   std_logic;
          s_add_c_to_mas_1      : out   std_logic;
          s_add_c_to_mas_2      : out   std_logic;
          s_add_c_to_mas_3      : out   std_logic;
          s_add_c_to_mas_4      : out   std_logic;
          s_add_c_to_mas_5      : out   std_logic;
          s_add_c_to_mas_6      : out   std_logic;
          s_add_c_to_mas_7      : out   std_logic;
          s_add_c_to_mas_8      : out   std_logic;
          s_add_c_to_mas_9      : out   std_logic;
          s_add_c_to_mas_10     : out   std_logic;
          s_add_c_to_mas_11     : out   std_logic;
          s_add_c_to_mas_12     : out   std_logic;
          s_add_c_to_mas_13     : out   std_logic;
          s_add_c_to_mas_14     : out   std_logic;
          s_add_c_to_mas_15     : out   std_logic;
          s_add_c_to_mas_16     : out   std_logic;
          s_add_c_to_mas_33     : out   std_logic;
          s_mul_b_from_iclarke  : in    std_logic_vector(2 to 2) := (others => 'U');
          s_mul_a_from_iclarke  : in    std_logic_vector(17 downto 0) := (others => 'U');
          s_mul_a_to_mas        : out   std_logic_vector(17 downto 0);
          s_mul_b_from_clarke   : in    std_logic_vector(1 to 1) := (others => 'U');
          s_mul_b_to_mas_0      : out   std_logic;
          s_mul_b_to_mas_4      : out   std_logic;
          start_park_i          : in    std_logic := 'U';
          start_park_i_i_0      : out   std_logic;
          reset_i               : in    std_logic := 'U';
          sys_clk_i             : in    std_logic := 'U';
          start_clarke_i        : in    std_logic := 'U';
          start_iclarke_i       : in    std_logic := 'U';
          start_ipark_i         : in    std_logic := 'U';
          s_mas_en_from_cordic  : in    std_logic := 'U';
          s_mas_en_from_clarke  : in    std_logic := 'U';
          s_mas_done_from_mas   : in    std_logic := 'U';
          s_mas_done_to_cordic  : out   std_logic;
          s_mas_en_from_iclarke : in    std_logic := 'U';
          s_mas_en_to_mas       : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component mas_foc
    port( reset_i    : in    std_logic := 'U';
          sys_clk_i  : in    std_logic := 'U';
          mas_en_i   : in    std_logic := 'U';
          sub_i      : in    std_logic := 'U';
          mul_a_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          mul_b_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          add_c_i    : in    std_logic_vector(43 downto 0) := (others => 'U');
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \va_o\ : std_logic_vector(17 downto 0);
    signal s_mul_a_from_clarke : std_logic_vector(17 downto 0);
    signal s_mul_b_from_clarke : std_logic_vector(1 to 1);
    signal s_mul_a_from_cordic : std_logic_vector(17 downto 0);
    signal s_mul_a_from_iclarke : std_logic_vector(17 downto 0);
    signal s_mul_b_from_iclarke : std_logic_vector(2 to 2);
    signal s_mul_a_to_mas : std_logic_vector(17 downto 0);
    signal s_mul_b_to_mas : std_logic_vector(9 downto 0);
    signal s_add_c_to_mas : std_logic_vector(43 downto 10);
    signal s_product_from_mas : std_logic_vector(28 downto 9);
    signal \MAS_SCHEDULER_INST.s_mas_sel\ : 
        std_logic_vector(1 downto 0);
    signal product_o : std_logic_vector(43 downto 0);
    signal MSC_net_518, MSC_net_519, MSC_net_520, MSC_net_521, 
        MSC_net_522, MSC_net_523, MSC_net_524, MSC_net_525, 
        MSC_net_526 : std_logic;

    for all : cordic_scheduler_foc
	Use entity work.cordic_scheduler_foc(DEF_ARCH);
    for all : clarke_foc
	Use entity work.clarke_foc(DEF_ARCH);
    for all : inverse_clarke_foc
	Use entity work.inverse_clarke_foc(DEF_ARCH);
    for all : mas_scheduler_foc
	Use entity work.mas_scheduler_foc(DEF_ARCH);
    for all : mas_foc
	Use entity work.mas_foc(DEF_ARCH);
begin 

    va_o(17) <= \va_o\(17);
    va_o(16) <= \va_o\(16);
    va_o(15) <= \va_o\(15);
    va_o(14) <= \va_o\(14);
    va_o(13) <= \va_o\(13);
    va_o(12) <= \va_o\(12);
    va_o(11) <= \va_o\(11);
    va_o(10) <= \va_o\(10);
    va_o(9) <= \va_o\(9);
    va_o(8) <= \va_o\(8);
    va_o(7) <= \va_o\(7);
    va_o(6) <= \va_o\(6);
    va_o(5) <= \va_o\(5);
    va_o(4) <= \va_o\(4);
    va_o(3) <= \va_o\(3);
    va_o(2) <= \va_o\(2);
    va_o(1) <= \va_o\(1);
    va_o(0) <= \va_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
Zqc+W8zWvEA261vGBwCzdvV6ZT6GUC9fp5sdcmBCeuwhIav7BblftPuhW8uJ9lZO
IvdTwp3DHRnGDkcqhNlNhbbUCP9B8fvFPmjq9CJmnfkq+7ZN2FevmSRqEpr+ClTP
KdL/uVh/IjWENOH92aME6tv6vbnxD6QeU+e4O+gKSug=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=39065)
`protect data_block
[encoded data, 38464 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity adc_interface is

    port( apb3_en_if_1_adc_control_reg_val_o : in    std_logic_vector(5 downto 0);
          adc_interface_0_result_ch0_o       : out   std_logic_vector(11 downto 0);
          adc_interface_0_result_ch1_o       : out   std_logic_vector(11 downto 0);
          adc_interface_0_result_ch2_o       : out   std_logic_vector(11 downto 0);
          adc_interface_0_result_ch3_o       : out   std_logic_vector(11 downto 0);
          apb3_en_if_1_adc_channel_ch2_o     : in    std_logic_vector(15 downto 0);
          apb3_en_if_1_adc_channel_ch0_o     : in    std_logic_vector(15 downto 0);
          apb3_en_if_1_adc_channel_ch1_o     : in    std_logic_vector(15 downto 0);
          apb3_en_if_1_adc_channel_ch3_o     : in    std_logic_vector(15 downto 0);
          MC_System_0_FIC_0_LOCK             : in    std_logic;
          MC_System_0_FIC_0_CLK              : in    std_logic;
          SEQ_CONTROLLER_1_adc_start_o       : in    std_logic;
          A0_ADC_SDI_I_c                     : in    std_logic;
          A0_ADC_SDO_O_c                     : out   std_logic;
          A0_ADC_CS_O_c                      : out   std_logic;
          A0_ADC_SCK_O_c                     : out   std_logic;
          adc_interface_0_results_rdy_o      : out   std_logic
        );

end adc_interface;

architecture DEF_ARCH of adc_interface is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal \A0_ADC_CS_O_c\, \A0_ADC_SCK_O_c\ : std_logic;
    signal s_r_sck_count : std_logic_vector(4 downto 0);
    signal s_channel_cnt : std_logic_vector(2 downto 0);
    signal s_channel_cnt_5 : std_logic_vector(2 downto 0);
    signal s_r_adc_chnls_4_samp : std_logic_vector(2 downto 0);
    signal s_r_sck_sel : std_logic_vector(2 downto 0);
    signal s_r_adc_data : std_logic_vector(15 downto 0);
    signal s_r_adc_data_4 : std_logic_vector(15 downto 0);
    signal s_sdo : std_logic_vector(15 downto 0);
    signal s_sdo_14 : std_logic_vector(15 downto 0);
    signal present_state : std_logic_vector(4 downto 0);
    signal next_state : std_logic_vector(4 to 4);
    signal present_state_ns : std_logic_vector(3 downto 1);
    signal next_state_i_0 : std_logic_vector(4 to 4);
    signal s_r_sck_max_count : std_logic_vector(3 to 3);
    signal s_r_clock_count : std_logic_vector(7 downto 0);
    signal s_r_clock_count_s : std_logic_vector(7 downto 0);
    signal s_r_clock_count_cry : std_logic_vector(6 downto 0);
    signal s_r_clock_count_cry_Y : std_logic_vector(6 downto 0);
    signal s_r_clock_count_s_FCO : std_logic_vector(7 to 7);
    signal s_r_clock_count_s_Y : std_logic_vector(7 to 7);
    signal s_sdo_14_bm : std_logic_vector(15 downto 0);
    signal s_sdo_14_am : std_logic_vector(15 downto 0);
    signal present_state_ns_a3_1 : std_logic_vector(1 to 1);
    signal s_sdo_14_m0 : std_logic_vector(15 downto 1);
    signal \VCC\, s_r_sck_count_n2_Z, s_r_sck_counte, \GND\, 
        s_r_sck_count_n3_Z, s_r_sck_count_n4_Z, N_1595_i_0, 
        s_r_sck_count_n1_Z, s_r_sck_count_0_sqmuxa_Z, 
        result_ch1_o_1_sqmuxa, result_ch0_o_0_sqmuxa, 
        result_ch2_o_1_sqmuxa, result_ch3_o_1_sqmuxa, 
        s_sdo_1_sqmuxa_3_i_0, s_start_sig_ext_Z, 
        un13_s_r_adc_results_ready, s_adc_sdi_Z, N_154_i_0, 
        N_277_i_0, N_173_i_0, s_r_sck_enable_Z, adc_sdo_dly_Z, 
        s_slave_select_2, s_r_sck_Z, s_r_sck_10, 
        s_r_adc_results_ready_1_sqmuxa_1, 
        s_r_clock_count_s_30_FCO, s_r_clock_count_s_30_S, 
        s_r_clock_count_s_30_Y, s_channel_cnt_0_sqmuxa_Z, 
        un13_s_r_sck, s_r_sck_10_7_am_1_1, s_r_sck_10_7_am, 
        s_r_sck_10_7_bm_1_1, s_r_sck_10_7_bm, s_sdo_14_sm2, 
        s_sdo_0_sqmuxa_1_1_Z, un1_s_r_sck, 
        result_ch3_o_1_sqmuxa_0_a2_0_3_Z, 
        result_ch3_o_1_sqmuxa_0_a2_0_2_Z, 
        un10_s_start_sig_ext_0_a3_2, s_r_sck_count_c2_Z, N_188, 
        un1_s_sdo_2_sqmuxa_tz_Z, s_sdo_14_m0s2, s_sdo_3_sqmuxa_Z, 
        N_1605, CO1, un1_s_sdo_1_sqmuxa_1_Z, un22_s_r_sck, 
        s_r_adc_results_ready_0_sqmuxa_1, CO0, N_120, N_119, 
        N_118, N_117, N_116 : std_logic;

begin 

    A0_ADC_CS_O_c <= \A0_ADC_CS_O_c\;
    A0_ADC_SCK_O_c <= \A0_ADC_SCK_O_c\;

    s_r_sck : SLE
      port map(D => s_r_sck_10, CLK => MC_System_0_FIC_0_CLK, EN
         => \VCC\, ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, 
        SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => s_r_sck_Z);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[7]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(7), B => s_sdo_14_am(7), C => 
        s_sdo_14_sm2, Y => s_sdo_14(7));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[14]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_en_if_1_adc_channel_ch1_o(14), B => 
        apb3_en_if_1_adc_channel_ch3_o(14), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(14));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[14]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_en_if_1_adc_channel_ch0_o(14), B => 
        s_sdo(13), C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(14));
    
    s_r_sck_enable : SLE
      port map(D => next_state_i_0(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_sck_enable_Z);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[8]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(8), B => s_sdo_14_am(8), C => 
        s_sdo_14_sm2, Y => s_sdo_14(8));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[12]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_en_if_1_adc_channel_ch1_o(12), B => 
        apb3_en_if_1_adc_channel_ch3_o(12), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(12));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[1]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(0), Y => 
        s_r_adc_data_4(1));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[0]\ : CFG4
      generic map(INIT => x"B830")

      port map(A => \A0_ADC_CS_O_c\, B => s_sdo_14_m0s2, C => 
        apb3_en_if_1_adc_channel_ch2_o(0), D => 
        apb3_en_if_1_adc_channel_ch0_o(0), Y => s_sdo_14_bm(0));
    
    \s_r_adc_data[13]\ : SLE
      port map(D => s_r_adc_data_4(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(13));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[15]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(15), B => s_sdo_14_am(15), C => 
        s_sdo_14_sm2, Y => s_sdo_14(15));
    
    \s_r_adc_data[4]\ : SLE
      port map(D => s_r_adc_data_4(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(4));
    
    s_slave_select : SLE
      port map(D => s_slave_select_2, CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => \A0_ADC_CS_O_c\);
    
    \s_r_adc_chnls_4_samp[0]\ : SLE
      port map(D => apb3_en_if_1_adc_control_reg_val_o(0), CLK
         => MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_adc_chnls_4_samp(0));
    
    \s_r_clock_count[4]\ : SLE
      port map(D => s_r_clock_count_s(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(4));
    
    \CHANNEL_CNT_PROC.s_channel_cnt_5[1]\ : CFG4
      generic map(INIT => x"1444")

      port map(A => present_state(4), B => s_channel_cnt(1), C
         => s_channel_cnt_0_sqmuxa_Z, D => s_channel_cnt(0), Y
         => s_channel_cnt_5(1));
    
    \s_r_clock_count_cry[1]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(1), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_cry(0), S => s_r_clock_count_s(1), Y => 
        s_r_clock_count_cry_Y(1), FCO => s_r_clock_count_cry(1));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[10]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(10), B => s_sdo_14_m0s2, C => 
        apb3_en_if_1_adc_channel_ch2_o(10), Y => s_sdo_14_bm(10));
    
    \SCK_GEN_PROC.s_r_sck_10_7_bm_1_1\ : CFG4
      generic map(INIT => x"3437")

      port map(A => s_r_clock_count(5), B => s_r_sck_sel(2), C
         => s_r_sck_sel(1), D => s_r_clock_count(1), Y => 
        s_r_sck_10_7_bm_1_1);
    
    \s_sdo[2]\ : SLE
      port map(D => s_sdo_14(2), CLK => MC_System_0_FIC_0_CLK, EN
         => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(2));
    
    s_sdo_1_sqmuxa_3_i : CFG2
      generic map(INIT => x"E")

      port map(A => un1_s_r_sck, B => \A0_ADC_CS_O_c\, Y => 
        s_sdo_1_sqmuxa_3_i_0);
    
    \s_r_clock_count_cry[4]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(4), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_cry(3), S => s_r_clock_count_s(4), Y => 
        s_r_clock_count_cry_Y(4), FCO => s_r_clock_count_cry(4));
    
    \result_ch0_o[4]\ : SLE
      port map(D => s_r_adc_data(4), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch0_o_0_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(4));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[12]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(11), Y => 
        s_r_adc_data_4(12));
    
    \s_r_clock_count_cry[0]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(0), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_s_30_FCO, S => s_r_clock_count_s(0), Y
         => s_r_clock_count_cry_Y(0), FCO => 
        s_r_clock_count_cry(0));
    
    \result_ch1_o[8]\ : SLE
      port map(D => s_r_adc_data(8), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch1_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(8));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[9]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(9), B => s_sdo_14_m0s2, C => 
        apb3_en_if_1_adc_channel_ch2_o(9), Y => s_sdo_14_bm(9));
    
    \SS_GEN_PROC.s_slave_select_2\ : CFG4
      generic map(INIT => x"5755")

      port map(A => s_start_sig_ext_Z, B => s_r_sck_count(4), C
         => s_r_sck_count(2), D => un10_s_start_sig_ext_0_a3_2, Y
         => s_slave_select_2);
    
    \s_sdo[5]\ : SLE
      port map(D => s_sdo_14(5), CLK => MC_System_0_FIC_0_CLK, EN
         => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(5));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[5]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(5), B => s_sdo_14_m0s2, C => 
        apb3_en_if_1_adc_channel_ch2_o(5), Y => s_sdo_14_bm(5));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[7]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_en_if_1_adc_channel_ch1_o(7), B => 
        apb3_en_if_1_adc_channel_ch3_o(7), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(7));
    
    \result_ch3_o[0]\ : SLE
      port map(D => s_r_adc_data(0), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch3_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch3_o(0));
    
    \s_r_sck_count[0]\ : SLE
      port map(D => N_1595_i_0, CLK => MC_System_0_FIC_0_CLK, EN
         => s_r_sck_counte, ALn => MC_System_0_FIC_0_LOCK, ADn
         => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        s_r_sck_count(0));
    
    \s_sdo[0]\ : SLE
      port map(D => s_sdo_14(0), CLK => MC_System_0_FIC_0_CLK, EN
         => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(0));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[5]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_en_if_1_adc_channel_ch0_o(5), B => 
        s_sdo(4), C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(5));
    
    s_start_sig_ext : SLE
      port map(D => SEQ_CONTROLLER_1_adc_start_o, CLK => 
        MC_System_0_FIC_0_CLK, EN => un13_s_r_adc_results_ready, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_start_sig_ext_Z);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[15]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_en_if_1_adc_channel_ch0_o(15), B => 
        s_sdo(14), C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(15));
    
    s_r_sck_count_n2 : CFG4
      generic map(INIT => x"6A00")

      port map(A => s_r_sck_count(2), B => s_r_sck_count(1), C
         => s_r_sck_count(0), D => N_277_i_0, Y => 
        s_r_sck_count_n2_Z);
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[3]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(2), Y => 
        s_r_adc_data_4(3));
    
    \result_ch2_o[3]\ : SLE
      port map(D => s_r_adc_data(3), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch2_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(3));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[2]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(2), B => s_sdo_14_am(2), C => 
        s_sdo_14_sm2, Y => s_sdo_14(2));
    
    \s_r_adc_data[6]\ : SLE
      port map(D => s_r_adc_data_4(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(6));
    
    \result_ch1_o[6]\ : SLE
      port map(D => s_r_adc_data(6), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch1_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(6));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[6]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(6), B => s_sdo_14_am(6), C => 
        s_sdo_14_sm2, Y => s_sdo_14(6));
    
    s_adc_sdi : SLE
      port map(D => A0_ADC_SDI_I_c, CLK => MC_System_0_FIC_0_CLK, 
        EN => N_154_i_0, ALn => MC_System_0_FIC_0_LOCK, ADn => 
        \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        s_adc_sdi_Z);
    
    \result_ch1_o[4]\ : SLE
      port map(D => s_r_adc_data(4), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch1_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(4));
    
    \START_SIG_PROC.un13_s_r_adc_results_ready_0\ : CFG2
      generic map(INIT => x"E")

      port map(A => s_r_adc_results_ready_1_sqmuxa_1, B => 
        SEQ_CONTROLLER_1_adc_start_o, Y => 
        un13_s_r_adc_results_ready);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[9]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(9), B => s_sdo_14_am(9), C => 
        s_sdo_14_sm2, Y => s_sdo_14(9));
    
    s_r_adc_results_ready_0_sqmuxa_1_0_a3 : CFG3
      generic map(INIT => x"80")

      port map(A => un22_s_r_sck, B => present_state(0), C => 
        un1_s_r_sck, Y => s_r_adc_results_ready_0_sqmuxa_1);
    
    s_adc_sdi_RNO : CFG2
      generic map(INIT => x"8")

      port map(A => un1_s_r_sck, B => N_277_i_0, Y => N_154_i_0);
    
    \s_sdo[1]\ : SLE
      port map(D => s_sdo_14(1), CLK => MC_System_0_FIC_0_CLK, EN
         => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(1));
    
    \present_state[2]\ : SLE
      port map(D => present_state_ns(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => present_state(2));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[4]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_en_if_1_adc_channel_ch1_o(4), B => 
        apb3_en_if_1_adc_channel_ch3_o(4), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(4));
    
    \s_r_clock_count[5]\ : SLE
      port map(D => s_r_clock_count_s(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(5));
    
    \result_ch3_o[3]\ : SLE
      port map(D => s_r_adc_data(3), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch3_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch3_o(3));
    
    \s_r_clock_count[2]\ : SLE
      port map(D => s_r_clock_count_s(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(2));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[6]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_en_if_1_adc_channel_ch0_o(6), B => 
        s_sdo(5), C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(6));
    
    s_r_sck_count_n4 : CFG4
      generic map(INIT => x"28A0")

      port map(A => N_277_i_0, B => s_r_sck_count_c2_Z, C => 
        s_r_sck_count(4), D => s_r_sck_count(3), Y => 
        s_r_sck_count_n4_Z);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[15]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_en_if_1_adc_channel_ch1_o(15), B => 
        apb3_en_if_1_adc_channel_ch3_o(15), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(15));
    
    \s_sdo[15]\ : SLE
      port map(D => s_sdo_14(15), CLK => MC_System_0_FIC_0_CLK, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(15));
    
    \s_sdo[12]\ : SLE
      port map(D => s_sdo_14(12), CLK => MC_System_0_FIC_0_CLK, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(12));
    
    \s_r_clock_count[3]\ : SLE
      port map(D => s_r_clock_count_s(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(3));
    
    \s_r_adc_data[14]\ : SLE
      port map(D => s_r_adc_data_4(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(14));
    
    results_rdy_o : SLE
      port map(D => s_r_adc_results_ready_1_sqmuxa_1, CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_results_rdy_o);
    
    \result_ch2_o[2]\ : SLE
      port map(D => s_r_adc_data(2), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch2_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(2));
    
    \s_r_sck_count[4]\ : SLE
      port map(D => s_r_sck_count_n4_Z, CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_counte, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_sck_count(4));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[12]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(12), B => s_sdo_14_am(12), C => 
        s_sdo_14_sm2, Y => s_sdo_14(12));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[10]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_en_if_1_adc_channel_ch0_o(10), B => 
        s_sdo(9), C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(10));
    
    \result_ch1_o[10]\ : SLE
      port map(D => s_r_adc_data(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => result_ch1_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(10));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[13]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_en_if_1_adc_channel_ch0_o(13), B => 
        s_sdo(12), C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(13));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[8]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_en_if_1_adc_channel_ch1_o(8), B => 
        apb3_en_if_1_adc_channel_ch3_o(8), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(8));
    
    \s_r_adc_data[7]\ : SLE
      port map(D => s_r_adc_data_4(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(7));
    
    \result_ch0_o[2]\ : SLE
      port map(D => s_r_adc_data(2), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch0_o_0_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(2));
    
    \s_channel_cnt[0]\ : SLE
      port map(D => s_channel_cnt_5(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_channel_cnt(0));
    
    result_ch2_o_1_sqmuxa_0_a2 : CFG3
      generic map(INIT => x"20")

      port map(A => s_r_adc_data(13), B => s_r_adc_data(12), C
         => N_1605, Y => result_ch2_o_1_sqmuxa);
    
    \result_ch1_o[5]\ : SLE
      port map(D => s_r_adc_data(5), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch1_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(5));
    
    \s_sdo[11]\ : SLE
      port map(D => s_sdo_14(11), CLK => MC_System_0_FIC_0_CLK, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(11));
    
    \s_r_sck_sel[0]\ : SLE
      port map(D => apb3_en_if_1_adc_control_reg_val_o(3), CLK
         => MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_sck_sel(0));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0s2\ : CFG4
      generic map(INIT => x"555D")

      port map(A => \A0_ADC_CS_O_c\, B => s_sdo_0_sqmuxa_1_1_Z, C
         => s_r_adc_chnls_4_samp(2), D => s_channel_cnt(0), Y => 
        s_sdo_14_m0s2);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[12]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(12), B => s_sdo_14_m0s2, C => 
        apb3_en_if_1_adc_channel_ch2_o(12), Y => s_sdo_14_bm(12));
    
    \s_r_adc_data[15]\ : SLE
      port map(D => s_r_adc_data_4(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(15));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[13]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_en_if_1_adc_channel_ch1_o(13), B => 
        apb3_en_if_1_adc_channel_ch3_o(13), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(13));
    
    \present_state_ns_i_m4[2]\ : CFG3
      generic map(INIT => x"A4")

      port map(A => present_state(3), B => present_state(2), C
         => un1_s_r_sck, Y => present_state_ns(2));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[7]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(7), B => s_sdo_14_m0s2, C => 
        apb3_en_if_1_adc_channel_ch2_o(7), Y => s_sdo_14_bm(7));
    
    \next_state_0[4]\ : CFG3
      generic map(INIT => x"DC")

      port map(A => SEQ_CONTROLLER_1_adc_start_o, B => 
        s_r_adc_results_ready_1_sqmuxa_1, C => present_state(4), 
        Y => next_state(4));
    
    \s_r_adc_data[5]\ : SLE
      port map(D => s_r_adc_data_4(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(5));
    
    \s_r_adc_data[11]\ : SLE
      port map(D => s_r_adc_data_4(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(11));
    
    \s_r_adc_chnls_4_samp[1]\ : SLE
      port map(D => apb3_en_if_1_adc_control_reg_val_o(1), CLK
         => MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_adc_chnls_4_samp(1));
    
    \s_sdo[9]\ : SLE
      port map(D => s_sdo_14(9), CLK => MC_System_0_FIC_0_CLK, EN
         => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(9));
    
    \result_ch0_o[1]\ : SLE
      port map(D => s_r_adc_data(1), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch0_o_0_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(1));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[11]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_en_if_1_adc_channel_ch0_o(11), B => 
        s_sdo(10), C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(11));
    
    \s_r_sck_count_RNO[0]\ : CFG2
      generic map(INIT => x"2")

      port map(A => N_277_i_0, B => s_r_sck_count(0), Y => 
        N_1595_i_0);
    
    \s_r_sck_max_count[3]\ : SLE
      port map(D => \VCC\, CLK => MC_System_0_FIC_0_CLK, EN => 
        \VCC\, ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn
         => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        s_r_sck_max_count(3));
    
    GND_Z : GND
      port map(Y => \GND\);
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[4]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(3), Y => 
        s_r_adc_data_4(4));
    
    \s_sdo[4]\ : SLE
      port map(D => s_sdo_14(4), CLK => MC_System_0_FIC_0_CLK, EN
         => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(4));
    
    \CHANNEL_CNT_PROC.s_channel_cnt_5[2]\ : CFG4
      generic map(INIT => x"006A")

      port map(A => s_channel_cnt(2), B => s_channel_cnt(1), C
         => CO0, D => present_state(4), Y => s_channel_cnt_5(2));
    
    result_ch3_o_1_sqmuxa_0_a2_0_2 : CFG4
      generic map(INIT => x"0401")

      port map(A => s_r_adc_data(15), B => s_r_sck_max_count(3), 
        C => s_r_adc_data(14), D => s_r_sck_count(4), Y => 
        result_ch3_o_1_sqmuxa_0_a2_0_2_Z);
    
    VCC_Z : VCC
      port map(Y => \VCC\);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[2]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_en_if_1_adc_channel_ch1_o(2), B => 
        apb3_en_if_1_adc_channel_ch3_o(2), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(2));
    
    s_channel_cnt_0_sqmuxa : CFG4
      generic map(INIT => x"0800")

      port map(A => present_state(0), B => s_r_sck_Z, C => 
        \A0_ADC_SCK_O_c\, D => un22_s_r_sck, Y => 
        s_channel_cnt_0_sqmuxa_Z);
    
    \s_r_sck_sel[2]\ : SLE
      port map(D => apb3_en_if_1_adc_control_reg_val_o(5), CLK
         => MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_sck_sel(2));
    
    \s_r_adc_data[10]\ : SLE
      port map(D => s_r_adc_data_4(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(10));
    
    \result_ch0_o[8]\ : SLE
      port map(D => s_r_adc_data(8), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch0_o_0_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(8));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[15]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(14), Y => 
        s_r_adc_data_4(15));
    
    \result_ch2_o[5]\ : SLE
      port map(D => s_r_adc_data(5), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch2_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(5));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[5]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(5), B => s_sdo_14_am(5), C => 
        s_sdo_14_sm2, Y => s_sdo_14(5));
    
    \result_ch2_o[10]\ : SLE
      port map(D => s_r_adc_data(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => result_ch2_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(10));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[10]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(9), Y => 
        s_r_adc_data_4(10));
    
    \result_ch3_o[4]\ : SLE
      port map(D => s_r_adc_data(4), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch3_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch3_o(4));
    
    result_ch1_o_1_sqmuxa_0_a2 : CFG3
      generic map(INIT => x"40")

      port map(A => s_r_adc_data(13), B => s_r_adc_data(12), C
         => N_1605, Y => result_ch1_o_1_sqmuxa);
    
    \result_ch0_o[9]\ : SLE
      port map(D => s_r_adc_data(9), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch0_o_0_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(9));
    
    \result_ch3_o[6]\ : SLE
      port map(D => s_r_adc_data(6), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch3_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch3_o(6));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[6]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_en_if_1_adc_channel_ch1_o(6), B => 
        apb3_en_if_1_adc_channel_ch3_o(6), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(6));
    
    sdo_o : SLE
      port map(D => adc_sdo_dly_Z, CLK => MC_System_0_FIC_0_CLK, 
        EN => \VCC\, ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, 
        SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        A0_ADC_SDO_O_c);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[4]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(4), B => s_sdo_14_m0s2, C => 
        apb3_en_if_1_adc_channel_ch2_o(4), Y => s_sdo_14_bm(4));
    
    \s_r_clock_count_s[7]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(7), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_cry(6), S => s_r_clock_count_s(7), Y => 
        s_r_clock_count_s_Y(7), FCO => s_r_clock_count_s_FCO(7));
    
    \result_ch1_o[11]\ : SLE
      port map(D => s_r_adc_data(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => result_ch1_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(11));
    
    \result_ch0_o[5]\ : SLE
      port map(D => s_r_adc_data(5), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch0_o_0_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(5));
    
    \result_ch0_o[0]\ : SLE
      port map(D => s_r_adc_data(0), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch0_o_0_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(0));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[11]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_en_if_1_adc_channel_ch1_o(11), B => 
        apb3_en_if_1_adc_channel_ch3_o(11), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(11));
    
    \present_state_ns[3]\ : CFG4
      generic map(INIT => x"EACC")

      port map(A => present_state(2), B => N_277_i_0, C => 
        un13_s_r_sck, D => un1_s_r_sck, Y => present_state_ns(3));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[13]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(13), B => s_sdo_14_m0s2, C => 
        apb3_en_if_1_adc_channel_ch2_o(13), Y => s_sdo_14_bm(13));
    
    \s_r_adc_data[8]\ : SLE
      port map(D => s_r_adc_data_4(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(8));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[0]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_adc_sdi_Z, Y => 
        s_r_adc_data_4(0));
    
    \s_r_clock_count[6]\ : SLE
      port map(D => s_r_clock_count_s(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(6));
    
    result_ch3_o_1_sqmuxa_0_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => s_r_adc_data(13), B => s_r_adc_data(12), C
         => N_1605, Y => result_ch3_o_1_sqmuxa);
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[2]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(1), Y => 
        s_r_adc_data_4(2));
    
    \present_state[0]\ : SLE
      port map(D => N_173_i_0, CLK => MC_System_0_FIC_0_CLK, EN
         => \VCC\, ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, 
        SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        present_state(0));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[7]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_en_if_1_adc_channel_ch0_o(7), B => 
        s_sdo(6), C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(7));
    
    \result_ch3_o[1]\ : SLE
      port map(D => s_r_adc_data(1), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch3_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch3_o(1));
    
    \result_ch2_o[6]\ : SLE
      port map(D => s_r_adc_data(6), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch2_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(6));
    
    \s_r_sck_count[3]\ : SLE
      port map(D => s_r_sck_count_n3_Z, CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_counte, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_sck_count(3));
    
    \s_r_sck_count[1]\ : SLE
      port map(D => s_r_sck_count_n1_Z, CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_counte, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_sck_count(1));
    
    \present_state[3]\ : SLE
      port map(D => present_state_ns(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => present_state(3));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[14]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(14), B => s_sdo_14_m0s2, C => 
        apb3_en_if_1_adc_channel_ch2_o(14), Y => s_sdo_14_bm(14));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[7]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(6), Y => 
        s_r_adc_data_4(7));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[8]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(8), B => s_sdo_14_m0s2, C => 
        apb3_en_if_1_adc_channel_ch2_o(8), Y => s_sdo_14_bm(8));
    
    \ADC_FSM_NS_PROC.un22_s_r_sck_1.CO1\ : CFG4
      generic map(INIT => x"1075")

      port map(A => s_r_adc_chnls_4_samp(1), B => 
        s_channel_cnt(0), C => s_r_adc_chnls_4_samp(0), D => 
        s_channel_cnt(1), Y => CO1);
    
    \s_r_clock_count_cry[6]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(6), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_cry(5), S => s_r_clock_count_s(6), Y => 
        s_r_clock_count_cry_Y(6), FCO => s_r_clock_count_cry(6));
    
    \s_channel_cnt[2]\ : SLE
      port map(D => s_channel_cnt_5(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_channel_cnt(2));
    
    \s_sdo[6]\ : SLE
      port map(D => s_sdo_14(6), CLK => MC_System_0_FIC_0_CLK, EN
         => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(6));
    
    \result_ch0_o[3]\ : SLE
      port map(D => s_r_adc_data(3), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch0_o_0_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(3));
    
    s_sdo_0_sqmuxa_1_1 : CFG2
      generic map(INIT => x"1")

      port map(A => s_channel_cnt(2), B => s_channel_cnt(1), Y
         => s_sdo_0_sqmuxa_1_1_Z);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[11]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(11), B => s_sdo_14_m0s2, C => 
        apb3_en_if_1_adc_channel_ch2_o(11), Y => s_sdo_14_bm(11));
    
    \result_ch0_o[7]\ : SLE
      port map(D => s_r_adc_data(7), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch0_o_0_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(7));
    
    \SS_GEN_PROC.un10_s_start_sig_ext_0_a3_2\ : CFG3
      generic map(INIT => x"01")

      port map(A => s_r_sck_count(3), B => s_r_sck_count(1), C
         => s_r_sck_count(0), Y => un10_s_start_sig_ext_0_a3_2);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[1]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(1), B => s_sdo_14_am(1), C => 
        s_sdo_14_sm2, Y => s_sdo_14(1));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[1]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_en_if_1_adc_channel_ch1_o(1), B => 
        apb3_en_if_1_adc_channel_ch3_o(1), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(1));
    
    \result_ch0_o[6]\ : SLE
      port map(D => s_r_adc_data(6), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch0_o_0_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(6));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[3]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_en_if_1_adc_channel_ch1_o(3), B => 
        apb3_en_if_1_adc_channel_ch3_o(3), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(3));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[9]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(8), Y => 
        s_r_adc_data_4(9));
    
    \result_ch3_o[10]\ : SLE
      port map(D => s_r_adc_data(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => result_ch3_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch3_o(10));
    
    \present_state[1]\ : SLE
      port map(D => present_state_ns(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => N_277_i_0);
    
    \next_state_0_a3_0[4]\ : CFG3
      generic map(INIT => x"40")

      port map(A => un22_s_r_sck, B => present_state(0), C => 
        un1_s_r_sck, Y => s_r_adc_results_ready_1_sqmuxa_1);
    
    \result_ch3_o[5]\ : SLE
      port map(D => s_r_adc_data(5), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch3_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch3_o(5));
    
    \present_state_ns_o4_RNINP6U[3]\ : CFG4
      generic map(INIT => x"7555")

      port map(A => N_277_i_0, B => s_r_sck_Z, C => un13_s_r_sck, 
        D => \A0_ADC_SCK_O_c\, Y => s_r_sck_counte);
    
    \present_state_ns[1]\ : CFG4
      generic map(INIT => x"FFF4")

      port map(A => un1_s_r_sck, B => present_state(3), C => 
        s_r_adc_results_ready_0_sqmuxa_1, D => N_188, Y => 
        present_state_ns(1));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[2]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_en_if_1_adc_channel_ch0_o(2), B => 
        s_sdo(1), C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(2));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[0]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(0), B => s_sdo_14_am(0), C => 
        s_sdo_14_sm2, Y => s_sdo_14(0));
    
    s_sdo_3_sqmuxa : CFG4
      generic map(INIT => x"0400")

      port map(A => s_r_adc_chnls_4_samp(2), B => 
        s_r_adc_chnls_4_samp(0), C => s_channel_cnt(2), D => 
        s_r_adc_chnls_4_samp(1), Y => s_sdo_3_sqmuxa_Z);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[10]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(10), B => s_sdo_14_am(10), C => 
        s_sdo_14_sm2, Y => s_sdo_14(10));
    
    \result_ch2_o[4]\ : SLE
      port map(D => s_r_adc_data(4), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch2_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(4));
    
    \SCK_GEN_PROC.s_r_sck_10_7_ns\ : CFG3
      generic map(INIT => x"E2")

      port map(A => s_r_sck_10_7_am, B => s_r_sck_sel(0), C => 
        s_r_sck_10_7_bm, Y => s_r_sck_10);
    
    \result_ch2_o[11]\ : SLE
      port map(D => s_r_adc_data(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => result_ch2_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(11));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[4]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_en_if_1_adc_channel_ch0_o(4), B => 
        s_sdo(3), C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(4));
    
    \s_r_clock_count_cry[5]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(5), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_cry(4), S => s_r_clock_count_s(5), Y => 
        s_r_clock_count_cry_Y(5), FCO => s_r_clock_count_cry(5));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[12]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_en_if_1_adc_channel_ch0_o(12), B => 
        s_sdo(11), C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(12));
    
    \s_sdo[13]\ : SLE
      port map(D => s_sdo_14(13), CLK => MC_System_0_FIC_0_CLK, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(13));
    
    s_r_sck_count_c2 : CFG3
      generic map(INIT => x"80")

      port map(A => s_r_sck_count(2), B => s_r_sck_count(1), C
         => s_r_sck_count(0), Y => s_r_sck_count_c2_Z);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[2]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(2), B => s_sdo_14_m0s2, C => 
        apb3_en_if_1_adc_channel_ch2_o(2), Y => s_sdo_14_bm(2));
    
    \result_ch2_o[0]\ : SLE
      port map(D => s_r_adc_data(0), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch2_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(0));
    
    \present_state_ns_a3[1]\ : CFG4
      generic map(INIT => x"0004")

      port map(A => N_277_i_0, B => present_state_ns_a3_1(1), C
         => present_state(3), D => present_state(2), Y => N_188);
    
    \s_sdo[7]\ : SLE
      port map(D => s_sdo_14(7), CLK => MC_System_0_FIC_0_CLK, EN
         => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(7));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[14]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(14), B => s_sdo_14_am(14), C => 
        s_sdo_14_sm2, Y => s_sdo_14(14));
    
    s_r_sck_count_n3 : CFG3
      generic map(INIT => x"28")

      port map(A => N_277_i_0, B => s_r_sck_count_c2_Z, C => 
        s_r_sck_count(3), Y => s_r_sck_count_n3_Z);
    
    s_r_clock_count_s_30 : ARI1
      generic map(INIT => x"4AA00")

      port map(A => \VCC\, B => s_r_sck_enable_Z, C => \GND\, D
         => \GND\, FCI => \VCC\, S => s_r_clock_count_s_30_S, Y
         => s_r_clock_count_s_30_Y, FCO => 
        s_r_clock_count_s_30_FCO);
    
    \result_ch3_o[2]\ : SLE
      port map(D => s_r_adc_data(2), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch3_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch3_o(2));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[11]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(10), Y => 
        s_r_adc_data_4(11));
    
    result_ch3_o_1_sqmuxa_0_a2_0_3 : CFG3
      generic map(INIT => x"18")

      port map(A => s_r_sck_max_count(3), B => s_r_sck_count(1), 
        C => s_r_sck_count(0), Y => 
        result_ch3_o_1_sqmuxa_0_a2_0_3_Z);
    
    \result_ch3_o[7]\ : SLE
      port map(D => s_r_adc_data(7), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch3_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch3_o(7));
    
    \result_ch1_o[1]\ : SLE
      port map(D => s_r_adc_data(1), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch1_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(1));
    
    \present_state_ns_a3_1[1]\ : CFG2
      generic map(INIT => x"2")

      port map(A => SEQ_CONTROLLER_1_adc_start_o, B => 
        present_state(0), Y => present_state_ns_a3_1(1));
    
    \SCK_GEN_PROC.s_r_sck_10_7_am_1_1\ : CFG4
      generic map(INIT => x"3437")

      port map(A => s_r_clock_count(4), B => s_r_sck_sel(2), C
         => s_r_sck_sel(1), D => s_r_clock_count(0), Y => 
        s_r_sck_10_7_am_1_1);
    
    \result_ch1_o[9]\ : SLE
      port map(D => s_r_adc_data(9), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch1_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(9));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[14]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(13), Y => 
        s_r_adc_data_4(14));
    
    \present_state_RNO[0]\ : CFG4
      generic map(INIT => x"0C2A")

      port map(A => present_state(0), B => N_277_i_0, C => 
        un13_s_r_sck, D => un1_s_r_sck, Y => N_173_i_0);
    
    \result_ch3_o[9]\ : SLE
      port map(D => s_r_adc_data(9), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch3_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch3_o(9));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[6]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(6), B => s_sdo_14_m0s2, C => 
        apb3_en_if_1_adc_channel_ch2_o(6), Y => s_sdo_14_bm(6));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[0]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_en_if_1_adc_channel_ch1_o(0), B => 
        apb3_en_if_1_adc_channel_ch3_o(0), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(0));
    
    \present_state[4]\ : SLE
      port map(D => next_state(4), CLK => MC_System_0_FIC_0_CLK, 
        EN => \VCC\, ALn => MC_System_0_FIC_0_LOCK, ADn => \GND\, 
        SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        present_state(4));
    
    \result_ch0_o[10]\ : SLE
      port map(D => s_r_adc_data(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => result_ch0_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(10));
    
    s_r_sck_count_n1 : CFG3
      generic map(INIT => x"60")

      port map(A => s_r_sck_count(1), B => s_r_sck_count(0), C
         => N_277_i_0, Y => s_r_sck_count_n1_Z);
    
    \s_r_adc_data[2]\ : SLE
      port map(D => s_r_adc_data_4(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(2));
    
    un1_s_sdo_2_sqmuxa_tz : CFG2
      generic map(INIT => x"2")

      port map(A => s_r_adc_chnls_4_samp(1), B => 
        s_r_adc_chnls_4_samp(2), Y => un1_s_sdo_2_sqmuxa_tz_Z);
    
    \ADC_FSM_NS_PROC.un22_s_r_sck_1.CO2\ : CFG4
      generic map(INIT => x"6F06")

      port map(A => s_r_adc_chnls_4_samp(2), B => 
        s_r_adc_chnls_4_samp(1), C => s_channel_cnt(2), D => CO1, 
        Y => un22_s_r_sck);
    
    \s_r_clock_count_cry[2]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(2), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_cry(1), S => s_r_clock_count_s(2), Y => 
        s_r_clock_count_cry_Y(2), FCO => s_r_clock_count_cry(2));
    
    \s_r_adc_data[12]\ : SLE
      port map(D => s_r_adc_data_4(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(12));
    
    \s_r_adc_data[1]\ : SLE
      port map(D => s_r_adc_data_4(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(1));
    
    \SCK_GEN_PROC.s_r_sck_10_7_am\ : CFG4
      generic map(INIT => x"B931")

      port map(A => s_r_sck_sel(1), B => s_r_sck_10_7_am_1_1, C
         => s_r_clock_count(6), D => s_r_clock_count(2), Y => 
        s_r_sck_10_7_am);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[9]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_en_if_1_adc_channel_ch0_o(9), B => 
        s_sdo(8), C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(9));
    
    \s_sdo[10]\ : SLE
      port map(D => s_sdo_14(10), CLK => MC_System_0_FIC_0_CLK, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(10));
    
    result_ch0_o_0_sqmuxa_0_a2 : CFG3
      generic map(INIT => x"10")

      port map(A => s_r_adc_data(13), B => s_r_adc_data(12), C
         => N_1605, Y => result_ch0_o_0_sqmuxa);
    
    un1_s_sdo_1_sqmuxa_1 : CFG4
      generic map(INIT => x"3200")

      port map(A => s_r_adc_chnls_4_samp(0), B => 
        s_r_adc_chnls_4_samp(2), C => s_r_adc_chnls_4_samp(1), D
         => s_sdo_0_sqmuxa_1_1_Z, Y => un1_s_sdo_1_sqmuxa_1_Z);
    
    \result_ch2_o[8]\ : SLE
      port map(D => s_r_adc_data(8), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch2_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(8));
    
    \ADC_FSM_NS_PROC.un1_s_r_sck\ : CFG2
      generic map(INIT => x"2")

      port map(A => \A0_ADC_SCK_O_c\, B => s_r_sck_Z, Y => 
        un1_s_r_sck);
    
    \s_r_clock_count_cry[3]\ : ARI1
      generic map(INIT => x"48800")

      port map(A => \VCC\, B => s_r_clock_count(3), C => 
        s_r_sck_enable_Z, D => \GND\, FCI => 
        s_r_clock_count_cry(2), S => s_r_clock_count_s(3), Y => 
        s_r_clock_count_cry_Y(3), FCO => s_r_clock_count_cry(3));
    
    \result_ch3_o[11]\ : SLE
      port map(D => s_r_adc_data(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => result_ch3_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch3_o(11));
    
    \DATA_TRANSMIT_PROC.s_sdo_14s2\ : CFG4
      generic map(INIT => x"F1F0")

      port map(A => s_channel_cnt(0), B => s_channel_cnt(2), C
         => s_sdo_14_m0s2, D => un1_s_sdo_2_sqmuxa_tz_Z, Y => 
        s_sdo_14_sm2);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[3]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_en_if_1_adc_channel_ch0_o(3), B => 
        s_sdo(2), C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(3));
    
    \s_r_adc_chnls_4_samp[2]\ : SLE
      port map(D => apb3_en_if_1_adc_control_reg_val_o(2), CLK
         => MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_adc_chnls_4_samp(2));
    
    \s_sdo[8]\ : SLE
      port map(D => s_sdo_14(8), CLK => MC_System_0_FIC_0_CLK, EN
         => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(8));
    
    \result_ch1_o[3]\ : SLE
      port map(D => s_r_adc_data(3), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch1_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(3));
    
    \next_state_0_i[4]\ : CFG3
      generic map(INIT => x"23")

      port map(A => SEQ_CONTROLLER_1_adc_start_o, B => 
        s_r_adc_results_ready_1_sqmuxa_1, C => present_state(4), 
        Y => next_state_i_0(4));
    
    \CHANNEL_CNT_PROC.s_channel_cnt_5[0]\ : CFG3
      generic map(INIT => x"14")

      port map(A => present_state(4), B => s_channel_cnt(0), C
         => s_channel_cnt_0_sqmuxa_Z, Y => s_channel_cnt_5(0));
    
    \result_ch2_o[9]\ : SLE
      port map(D => s_r_adc_data(9), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch2_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(9));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[1]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_en_if_1_adc_channel_ch0_o(1), B => 
        s_sdo(0), C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(1));
    
    \result_ch1_o[7]\ : SLE
      port map(D => s_r_adc_data(7), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch1_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(7));
    
    \present_state_ns_o4[3]\ : CFG4
      generic map(INIT => x"5557")

      port map(A => s_r_sck_count(4), B => s_r_sck_count(3), C
         => s_r_sck_count(2), D => s_r_sck_count(1), Y => 
        un13_s_r_sck);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[9]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_en_if_1_adc_channel_ch1_o(9), B => 
        apb3_en_if_1_adc_channel_ch3_o(9), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(9));
    
    result_ch3_o_1_sqmuxa_0_a2_0 : CFG4
      generic map(INIT => x"1000")

      port map(A => s_r_sck_count(3), B => s_r_sck_count(2), C
         => result_ch3_o_1_sqmuxa_0_a2_0_3_Z, D => 
        result_ch3_o_1_sqmuxa_0_a2_0_2_Z, Y => N_1605);
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[13]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(12), Y => 
        s_r_adc_data_4(13));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[1]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(1), B => s_sdo_14_m0s2, C => 
        apb3_en_if_1_adc_channel_ch2_o(1), Y => s_sdo_14_bm(1));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[5]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_en_if_1_adc_channel_ch1_o(5), B => 
        apb3_en_if_1_adc_channel_ch3_o(5), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(5));
    
    \s_r_adc_data[3]\ : SLE
      port map(D => s_r_adc_data_4(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(3));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[3]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(3), B => s_sdo_14_m0s2, C => 
        apb3_en_if_1_adc_channel_ch2_o(3), Y => s_sdo_14_bm(3));
    
    \SCK_GEN_PROC.s_r_sck_10_7_bm\ : CFG4
      generic map(INIT => x"B931")

      port map(A => s_r_sck_sel(1), B => s_r_sck_10_7_bm_1_1, C
         => s_r_clock_count(7), D => s_r_clock_count(3), Y => 
        s_r_sck_10_7_bm);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[3]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(3), B => s_sdo_14_am(3), C => 
        s_sdo_14_sm2, Y => s_sdo_14(3));
    
    \s_sdo[14]\ : SLE
      port map(D => s_sdo_14(14), CLK => MC_System_0_FIC_0_CLK, 
        EN => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(14));
    
    \result_ch2_o[7]\ : SLE
      port map(D => s_r_adc_data(7), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch2_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(7));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[6]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(5), Y => 
        s_r_adc_data_4(6));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[11]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(11), B => s_sdo_14_am(11), C => 
        s_sdo_14_sm2, Y => s_sdo_14(11));
    
    \result_ch1_o[0]\ : SLE
      port map(D => s_r_adc_data(0), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch1_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(0));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[5]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(4), Y => 
        s_r_adc_data_4(5));
    
    \s_r_sck_sel[1]\ : SLE
      port map(D => apb3_en_if_1_adc_control_reg_val_o(4), CLK
         => MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_sck_sel(1));
    
    \s_r_adc_data[0]\ : SLE
      port map(D => s_r_adc_data_4(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(0));
    
    \result_ch3_o[8]\ : SLE
      port map(D => s_r_adc_data(8), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch3_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch3_o(8));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_am[10]\ : CFG4
      generic map(INIT => x"ACA0")

      port map(A => apb3_en_if_1_adc_channel_ch1_o(10), B => 
        apb3_en_if_1_adc_channel_ch3_o(10), C => 
        un1_s_sdo_1_sqmuxa_1_Z, D => s_sdo_3_sqmuxa_Z, Y => 
        s_sdo_14_am(10));
    
    \CHANNEL_CNT_PROC.s_channel_cnt_5_RNO[2]\ : CFG2
      generic map(INIT => x"8")

      port map(A => s_channel_cnt_0_sqmuxa_Z, B => 
        s_channel_cnt(0), Y => CO0);
    
    s_r_sck_count_0_sqmuxa : CFG4
      generic map(INIT => x"4000")

      port map(A => s_r_sck_Z, B => N_277_i_0, C => 
        \A0_ADC_SCK_O_c\, D => un13_s_r_sck, Y => 
        s_r_sck_count_0_sqmuxa_Z);
    
    \s_r_clock_count[1]\ : SLE
      port map(D => s_r_clock_count_s(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(1));
    
    \s_r_clock_count[0]\ : SLE
      port map(D => s_r_clock_count_s(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(0));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_bm[15]\ : CFG3
      generic map(INIT => x"B8")

      port map(A => s_sdo_14_m0(15), B => s_sdo_14_m0s2, C => 
        apb3_en_if_1_adc_channel_ch2_o(15), Y => s_sdo_14_bm(15));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[13]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(13), B => s_sdo_14_am(13), C => 
        s_sdo_14_sm2, Y => s_sdo_14(13));
    
    adc_sdo_dly : SLE
      port map(D => s_sdo(15), CLK => MC_System_0_FIC_0_CLK, EN
         => \VCC\, ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, 
        SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        adc_sdo_dly_Z);
    
    \DATA_TRANSMIT_PROC.s_sdo_14_ns[4]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => s_sdo_14_bm(4), B => s_sdo_14_am(4), C => 
        s_sdo_14_sm2, Y => s_sdo_14(4));
    
    \s_sdo[3]\ : SLE
      port map(D => s_sdo_14(3), CLK => MC_System_0_FIC_0_CLK, EN
         => s_sdo_1_sqmuxa_3_i_0, ALn => MC_System_0_FIC_0_LOCK, 
        ADn => \VCC\, SLn => \VCC\, SD => \GND\, LAT => \GND\, Q
         => s_sdo(3));
    
    \DATA_CLOLLECTION_PROC.s_r_adc_data_4[8]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \A0_ADC_CS_O_c\, B => s_r_adc_data(7), Y => 
        s_r_adc_data_4(8));
    
    \DATA_TRANSMIT_PROC.s_sdo_14_m0[8]\ : CFG3
      generic map(INIT => x"AC")

      port map(A => apb3_en_if_1_adc_channel_ch0_o(8), B => 
        s_sdo(7), C => \A0_ADC_CS_O_c\, Y => s_sdo_14_m0(8));
    
    \s_r_sck_count[2]\ : SLE
      port map(D => s_r_sck_count_n2_Z, CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_counte, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_sck_count(2));
    
    \result_ch2_o[1]\ : SLE
      port map(D => s_r_adc_data(1), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch2_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch2_o(1));
    
    \s_r_adc_data[9]\ : SLE
      port map(D => s_r_adc_data_4(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => s_r_sck_count_0_sqmuxa_Z, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => s_r_adc_data(9));
    
    \result_ch1_o[2]\ : SLE
      port map(D => s_r_adc_data(2), CLK => MC_System_0_FIC_0_CLK, 
        EN => result_ch1_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch1_o(2));
    
    \s_channel_cnt[1]\ : SLE
      port map(D => s_channel_cnt_5(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_channel_cnt(1));
    
    \result_ch0_o[11]\ : SLE
      port map(D => s_r_adc_data(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => result_ch0_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        adc_interface_0_result_ch0_o(11));
    
    \s_r_clock_count[7]\ : SLE
      port map(D => s_r_clock_count_s(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => \VCC\, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => s_r_clock_count(7));
    
    sck_o : SLE
      port map(D => s_r_sck_Z, CLK => MC_System_0_FIC_0_CLK, EN
         => \VCC\, ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, 
        SLn => \VCC\, SD => \GND\, LAT => \GND\, Q => 
        \A0_ADC_SCK_O_c\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity mas_pwm_scl is

    port( reset_i    : in    std_logic;
          sys_clk_i  : in    std_logic;
          mas_en_i   : in    std_logic;
          sub_i      : in    std_logic;
          mul_a_i    : in    std_logic_vector(17 downto 0);
          mul_b_i    : in    std_logic_vector(17 downto 0);
          add_c_i    : in    std_logic_vector(43 downto 0);
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );

end mas_pwm_scl;

architecture DEF_ARCH of mas_pwm_scl is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \product_o\ : std_logic_vector(43 downto 0);
    signal s_mas_done_dly : std_logic_vector(0 to 0);
    signal product_o_NC : std_logic_vector(43 downto 0);
    signal MSC_net_149, MSC_net_150, MSC_net_151, MSC_net_152, 
        MSC_net_153, MSC_net_154, MSC_net_155, MSC_net_156, 
        MSC_net_157, MSC_net_158, MSC_net_159, MSC_net_160, 
        MSC_net_161, MSC_net_162, MSC_net_163, MSC_net_164, 
        MSC_net_165, MSC_net_166, MSC_net_167, MSC_net_168, 
        MSC_net_169, MSC_net_170, MSC_net_171, MSC_net_172, 
        MSC_net_173, MSC_net_174, MSC_net_175, MSC_net_176
         : std_logic;

begin 

    \product_o\(43 downto 1) <= (OTHERS => 'U'); 
    product_o(43) <= \product_o\(0);
    product_o(42) <= \product_o\(0);
    product_o(41) <= \product_o\(0);
    product_o(40) <= \product_o\(0);
    product_o(39) <= \product_o\(0);
    product_o(38) <= \product_o\(0);
    product_o(37) <= \product_o\(0);
    product_o(36) <= \product_o\(0);
    product_o(35) <= \product_o\(0);
    product_o(34) <= \product_o\(0);
    product_o(15) <= \product_o\(0);
    product_o(14) <= \product_o\(0);
    product_o(13) <= \product_o\(0);
    product_o(12) <= \product_o\(0);
    product_o(11) <= \product_o\(0);
    product_o(10) <= \product_o\(0);
    product_o(9) <= \product_o\(0);
    product_o(8) <= \product_o\(0);
    product_o(7) <= \product_o\(0);
    product_o(6) <= \product_o\(0);
    product_o(5) <= \product_o\(0);
    product_o(4) <= \product_o\(0);
    product_o(3) <= \product_o\(0);
    product_o(2) <= \product_o\(0);
    product_o(1) <= \product_o\(0);
    product_o(0) <= \product_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
kjt1gL/GMhUSJEhZjih33H3l8rxbnRJHZPfcfGN7sEx0OxgmSgAOFW0AiOFHMKff
zZNV7qKJSRm/JbC5/R5Oj2xx655IYGFH4eDdY8qY4CI1Scxi4H9V0vo585i9WV1N
XzegF/uB0QHP3kJ76pD7xxS8jEafAgP4LwkCU9/Eg7U=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=12375)
`protect data_block
[encoded data, 12160 characters]
by3cc1w7KAuWWvtpId+IIA==

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity PWM_SCALING is

    port( reset_i      : in    std_logic;
          sys_clk_i    : in    std_logic;
          start_i      : in    std_logic;
          va_i         : in    std_logic_vector(17 downto 0);
          vb_i         : in    std_logic_vector(17 downto 0);
          vc_i         : in    std_logic_vector(17 downto 0);
          pwm_period_i : in    std_logic_vector(17 downto 0);
          pwm_gain_i   : in    std_logic_vector(17 downto 0);
          Va_o         : out   std_logic_vector(17 downto 0);
          Vb_o         : out   std_logic_vector(17 downto 0);
          Vc_o         : out   std_logic_vector(17 downto 0);
          done_o       : out   std_logic
        );

end PWM_SCALING;

architecture DEF_ARCH of PWM_SCALING is 

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component mas_pwm_scl
    port( reset_i    : in    std_logic := 'U';
          sys_clk_i  : in    std_logic := 'U';
          mas_en_i   : in    std_logic := 'U';
          sub_i      : in    std_logic := 'U';
          mul_a_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          mul_b_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          add_c_i    : in    std_logic_vector(43 downto 0) := (others => 'U');
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal s_mult_in0 : std_logic_vector(17 downto 0);
    signal s_product : std_logic_vector(33 downto 16);
    signal s_state : std_logic_vector(4 downto 0);
    signal s_state_ns : std_logic_vector(1 to 1);
    signal \MUL_INP_GEN_PROC.s_mult_in0_4\ : 
        std_logic_vector(17 downto 0);
    signal product_o : std_logic_vector(43 downto 0);
    signal MSC_net_252, MSC_net_253, MSC_net_254, MSC_net_255, 
        MSC_net_256, MSC_net_257, MSC_net_258, MSC_net_259, 
        MSC_net_260, MSC_net_261, MSC_net_262, MSC_net_263, 
        MSC_net_264, MSC_net_265, MSC_net_266, MSC_net_267, 
        MSC_net_268, MSC_net_269, MSC_net_270, MSC_net_271, 
        MSC_net_272, MSC_net_273, MSC_net_274, MSC_net_275, 
        MSC_net_276, MSC_net_277, MSC_net_278, MSC_net_279, 
        MSC_net_280, MSC_net_281, MSC_net_282, MSC_net_283, 
        MSC_net_284, MSC_net_285, MSC_net_286, MSC_net_287
         : std_logic;

    for all : mas_pwm_scl
	Use entity work.mas_pwm_scl(DEF_ARCH);
begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
pkHlBiDwJ9VSEeIHnuf7mNDXmaefAzS3QNGDwOayAeBwQrmyUv+pntCLbhBnf+N3
ci/Mzwk11avjNoKS4lF29yvm72kdgBkbDwuL/yBmiL28t+hAOEr2C9Wwp6zpa0Qn
QMApnEmxbcWr5OMOrBqbXU2jRrqIdpIvIfVMDbDwPiM=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=43835)
`protect data_block
[encoded data, 43136 characters]
Nl4NXWuhfRDEMKWbHlSU1w==

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity hall_filter is

    port( s_filter_out      : out   std_logic_vector(33 downto 0);
          s_filter_val_prev : in    std_logic_vector(33 downto 0);
          s_spd_result      : in    std_logic_vector(25 downto 8);
          filter_factor_i   : in    std_logic_vector(3 downto 0);
          reset_i           : in    std_logic;
          sys_clk_i         : in    std_logic;
          fil_trig_i        : in    std_logic
        );

end hall_filter;

architecture DEF_ARCH of hall_filter is 

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

    signal s_filter_incr : std_logic_vector(32 downto 0);
    signal s_filter_incr_2 : std_logic_vector(33 downto 1);
    signal s_state : std_logic_vector(0 to 0);
    signal MSC_net_160, MSC_net_161, MSC_net_162, MSC_net_163, 
        MSC_net_164, MSC_net_165, MSC_net_166, MSC_net_167, 
        MSC_net_168, MSC_net_169, MSC_net_170, MSC_net_171, 
        MSC_net_172, MSC_net_173, MSC_net_174, MSC_net_175, 
        MSC_net_176, MSC_net_177, MSC_net_178, MSC_net_179, 
        MSC_net_180, MSC_net_181, MSC_net_182, MSC_net_183, 
        MSC_net_184, MSC_net_185, MSC_net_186, MSC_net_187, 
        MSC_net_188, MSC_net_189, MSC_net_190, MSC_net_191, 
        MSC_net_192, MSC_net_193, MSC_net_194, MSC_net_195, 
        MSC_net_196, MSC_net_197, MSC_net_198, MSC_net_199, 
        MSC_net_200, MSC_net_201, MSC_net_202, MSC_net_203, 
        MSC_net_204, MSC_net_205, MSC_net_206, MSC_net_207, 
        MSC_net_208, MSC_net_209, MSC_net_210, MSC_net_211, 
        MSC_net_212, MSC_net_213, MSC_net_214, MSC_net_215, 
        MSC_net_216, MSC_net_217, MSC_net_218, MSC_net_219, 
        MSC_net_220, MSC_net_221, MSC_net_222, MSC_net_223, 
        MSC_net_224, MSC_net_225, MSC_net_226, MSC_net_227, 
        MSC_net_228, MSC_net_229, MSC_net_230, MSC_net_231, 
        MSC_net_232, MSC_net_233, MSC_net_234, MSC_net_235, 
        MSC_net_236, MSC_net_237, MSC_net_238, MSC_net_239, 
        MSC_net_240, MSC_net_241, MSC_net_242, MSC_net_243, 
        MSC_net_244, MSC_net_245, MSC_net_246, MSC_net_247, 
        MSC_net_248, MSC_net_249, MSC_net_250, MSC_net_251, 
        MSC_net_252, MSC_net_253, MSC_net_254, MSC_net_255, 
        MSC_net_256, MSC_net_257, MSC_net_258, MSC_net_259, 
        MSC_net_260, MSC_net_261, MSC_net_262, MSC_net_263, 
        MSC_net_264, MSC_net_265, MSC_net_266, MSC_net_267, 
        MSC_net_268, MSC_net_269, MSC_net_270, MSC_net_271, 
        MSC_net_272, MSC_net_273, MSC_net_274, MSC_net_275, 
        MSC_net_276, MSC_net_277, MSC_net_278, MSC_net_279, 
        MSC_net_280, MSC_net_281, MSC_net_282, MSC_net_283, 
        MSC_net_284, MSC_net_285, MSC_net_286, MSC_net_287, 
        MSC_net_288, MSC_net_289, MSC_net_290, MSC_net_291, 
        MSC_net_292, MSC_net_293, MSC_net_294, MSC_net_295, 
        MSC_net_296, MSC_net_297, MSC_net_298, MSC_net_299, 
        MSC_net_300, MSC_net_301, MSC_net_302, MSC_net_303, 
        MSC_net_304, MSC_net_305, MSC_net_306, MSC_net_307, 
        MSC_net_308, MSC_net_309, MSC_net_310, MSC_net_311, 
        MSC_net_312, MSC_net_313, MSC_net_314, MSC_net_315, 
        MSC_net_316, MSC_net_317, MSC_net_318, MSC_net_319, 
        MSC_net_320, MSC_net_321, MSC_net_322, MSC_net_323, 
        MSC_net_324, MSC_net_325, MSC_net_326, MSC_net_327, 
        MSC_net_328, MSC_net_329, MSC_net_330, MSC_net_331, 
        MSC_net_332, MSC_net_333, MSC_net_334, MSC_net_335, 
        MSC_net_336, MSC_net_337, MSC_net_338, MSC_net_339, 
        MSC_net_340, MSC_net_341, MSC_net_342, MSC_net_343, 
        MSC_net_344, MSC_net_345, MSC_net_346, MSC_net_347, 
        MSC_net_348, MSC_net_349, MSC_net_350, MSC_net_351, 
        MSC_net_352, MSC_net_353, MSC_net_354, MSC_net_355, 
        MSC_net_356, MSC_net_357, MSC_net_358, MSC_net_359, 
        MSC_net_360, MSC_net_361, MSC_net_362, MSC_net_363, 
        MSC_net_364, MSC_net_365, MSC_net_366, MSC_net_367, 
        MSC_net_368, MSC_net_369, MSC_net_370, MSC_net_371, 
        MSC_net_372, MSC_net_373, MSC_net_374, MSC_net_375, 
        MSC_net_376, MSC_net_377, MSC_net_378, MSC_net_379, 
        MSC_net_380, MSC_net_381, MSC_net_382, MSC_net_383, 
        MSC_net_384, MSC_net_385, MSC_net_386, MSC_net_387, 
        MSC_net_388, MSC_net_389, MSC_net_390, MSC_net_391, 
        MSC_net_392, MSC_net_393, MSC_net_394, MSC_net_395, 
        MSC_net_396, MSC_net_397, MSC_net_398, MSC_net_399, 
        MSC_net_400, MSC_net_401, MSC_net_402, MSC_net_403, 
        MSC_net_404, MSC_net_405, MSC_net_406, MSC_net_407, 
        MSC_net_408, MSC_net_409, MSC_net_410, MSC_net_411, 
        MSC_net_412, MSC_net_413, MSC_net_414, MSC_net_415, 
        MSC_net_416, MSC_net_417, MSC_net_418, MSC_net_419, 
        MSC_net_420, MSC_net_421, MSC_net_422, MSC_net_423, 
        MSC_net_424, MSC_net_425, MSC_net_426, MSC_net_427, 
        MSC_net_428, MSC_net_429, MSC_net_430, MSC_net_431, 
        MSC_net_432, MSC_net_433, MSC_net_434, MSC_net_435, 
        MSC_net_436, MSC_net_437, MSC_net_438, MSC_net_439, 
        MSC_net_440, MSC_net_441, MSC_net_442, MSC_net_443, 
        MSC_net_444, MSC_net_445, MSC_net_446, MSC_net_447, 
        MSC_net_448, MSC_net_449, MSC_net_450, MSC_net_451, 
        MSC_net_452, MSC_net_453, MSC_net_454, MSC_net_455, 
        MSC_net_456, MSC_net_457, MSC_net_458, MSC_net_459, 
        MSC_net_460, MSC_net_461, MSC_net_462, MSC_net_463
         : std_logic;

begin 



`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
htdMAxPiyiIJFjG/SkJi5jGAHPVV31zP1F1VkVQsfhV35giZvZigS4UG7Qux9Ctn
QLVuq9msRmAR+wlUsLaUlAdQiCesI4wa6O+xUl7gD3GyVUeN757/hRQgi60TQshw
Vrj95epjXqNPpFJcy2usO94NMSPqLnpHHgBDm+d+uNE=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=84980)
`protect data_block
[encoded data, 83648 characters]
K53NFtB+wOcjmPaKXcVywg==

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity hall_mas_0 is

    port( reset_i    : in    std_logic;
          sys_clk_i  : in    std_logic;
          mas_en_i   : in    std_logic;
          sub_i      : in    std_logic;
          mul_a_i    : in    std_logic_vector(17 downto 0);
          mul_b_i    : in    std_logic_vector(17 downto 0);
          add_c_i    : in    std_logic_vector(43 downto 0);
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );

end hall_mas_0;

architecture DEF_ARCH of hall_mas_0 is 

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal \product_o\ : std_logic_vector(43 downto 0);
    signal \MAS_PROC.op_mult.un3_product_o\ : 
        std_logic_vector(27 downto 4);
    signal \MAS_PROC.op_mult.un3_product_o_NC\ : 
        std_logic_vector(43 downto 0);
    signal \MAS_PROC.op_mult.un3_product_o_ONC\ : 
        std_logic_vector(43 downto 24);
    signal MSC_net_185, MSC_net_186, MSC_net_187, MSC_net_188, 
        MSC_net_189, MSC_net_190, MSC_net_191, MSC_net_192, 
        MSC_net_193, MSC_net_194, MSC_net_195, MSC_net_196, 
        MSC_net_197, MSC_net_198, MSC_net_199, MSC_net_200, 
        MSC_net_201, MSC_net_202, MSC_net_203, MSC_net_204, 
        MSC_net_205, MSC_net_206, MSC_net_207, MSC_net_208, 
        MSC_net_209, MSC_net_210, MSC_net_211, MSC_net_212, 
        MSC_net_213, MSC_net_214 : std_logic;

begin 

    \product_o\(43 downto 34) <= (OTHERS => 'U'); 
    \product_o\(32 downto 1) <= (OTHERS => 'U'); 
    product_o(43) <= \product_o\(0);
    product_o(42) <= \product_o\(0);
    product_o(41) <= \product_o\(0);
    product_o(40) <= \product_o\(0);
    product_o(39) <= \product_o\(0);
    product_o(38) <= \product_o\(0);
    product_o(37) <= \product_o\(0);
    product_o(36) <= \product_o\(0);
    product_o(35) <= \product_o\(0);
    product_o(34) <= \product_o\(0);
    product_o(33) <= \product_o\(33);
    product_o(32) <= \product_o\(33);
    product_o(31) <= \product_o\(33);
    product_o(30) <= \product_o\(33);
    product_o(29) <= \product_o\(33);
    product_o(28) <= \product_o\(33);
    product_o(27) <= \product_o\(33);
    product_o(15) <= \product_o\(0);
    product_o(14) <= \product_o\(0);
    product_o(13) <= \product_o\(0);
    product_o(12) <= \product_o\(0);
    product_o(11) <= \product_o\(0);
    product_o(10) <= \product_o\(0);
    product_o(9) <= \product_o\(0);
    product_o(8) <= \product_o\(0);
    product_o(7) <= \product_o\(0);
    product_o(6) <= \product_o\(0);
    product_o(5) <= \product_o\(0);
    product_o(4) <= \product_o\(0);
    product_o(3) <= \product_o\(0);
    product_o(2) <= \product_o\(0);
    product_o(1) <= \product_o\(0);
    product_o(0) <= \product_o\(0);
    mas_done_o <= \product_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
a2lBLV1Ifzl9XJLgJbPRwUAoNOzUPIFilr6B4GdofaNeHOz7VCiJRhbYTwu/4nyB
+bRvJK47UzXIGHgG1YGgBetygDCS8D2FCti9/cfQZXKQVGKLWPsm5Jegr1t/cwjD
MoO6hYiib15u1eqLBeTU8pFUwScl2552GiaKuBI2xxE=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=19760)
`protect data_block
[encoded data, 19456 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity hall_mas_1 is

    port( reset_i    : in    std_logic;
          sys_clk_i  : in    std_logic;
          mas_en_i   : in    std_logic;
          sub_i      : in    std_logic;
          mul_a_i    : in    std_logic_vector(17 downto 0);
          mul_b_i    : in    std_logic_vector(17 downto 0);
          add_c_i    : in    std_logic_vector(43 downto 0);
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );

end hall_mas_1;

architecture DEF_ARCH of hall_mas_1 is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \product_o\ : std_logic_vector(43 downto 0);
    signal product_o_NC : std_logic_vector(43 downto 0);
    signal product_o_ONC : std_logic_vector(43 downto 36);
    signal MSC_net_155, MSC_net_156, MSC_net_157, MSC_net_158, 
        MSC_net_159, MSC_net_160, MSC_net_161, MSC_net_162, 
        MSC_net_163, MSC_net_164, MSC_net_165, MSC_net_166, 
        MSC_net_167, MSC_net_168, MSC_net_169, MSC_net_170, 
        MSC_net_171, MSC_net_172, MSC_net_173, MSC_net_174, 
        MSC_net_175, MSC_net_176, MSC_net_177, MSC_net_178, 
        MSC_net_179, MSC_net_180, MSC_net_181, MSC_net_182, 
        MSC_net_183, MSC_net_184, MSC_net_185, MSC_net_186, 
        MSC_net_187, MSC_net_188, MSC_net_189, MSC_net_190, 
        MSC_net_191, MSC_net_192, MSC_net_193, MSC_net_194, 
        MSC_net_195, MSC_net_196, MSC_net_197, MSC_net_198, 
        MSC_net_199, MSC_net_200, MSC_net_201, MSC_net_202, 
        MSC_net_203, MSC_net_204, MSC_net_205, MSC_net_206, 
        MSC_net_207, MSC_net_208, MSC_net_209, MSC_net_210, 
        MSC_net_211, MSC_net_212, MSC_net_213, MSC_net_214, 
        MSC_net_215, MSC_net_216, MSC_net_217, MSC_net_218, 
        MSC_net_219, MSC_net_220 : std_logic;

begin 

    \product_o\(43 downto 1) <= (OTHERS => 'U'); 
    product_o(43) <= \product_o\(0);
    product_o(42) <= \product_o\(0);
    product_o(41) <= \product_o\(0);
    product_o(40) <= \product_o\(0);
    product_o(39) <= \product_o\(0);
    product_o(38) <= \product_o\(0);
    product_o(37) <= \product_o\(0);
    product_o(36) <= \product_o\(0);
    product_o(35) <= \product_o\(0);
    product_o(34) <= \product_o\(0);
    product_o(33) <= \product_o\(0);
    product_o(32) <= \product_o\(0);
    product_o(31) <= \product_o\(0);
    product_o(30) <= \product_o\(0);
    product_o(29) <= \product_o\(0);
    product_o(28) <= \product_o\(0);
    product_o(27) <= \product_o\(0);
    product_o(26) <= \product_o\(0);
    product_o(7) <= \product_o\(0);
    product_o(6) <= \product_o\(0);
    product_o(5) <= \product_o\(0);
    product_o(4) <= \product_o\(0);
    product_o(3) <= \product_o\(0);
    product_o(2) <= \product_o\(0);
    product_o(1) <= \product_o\(0);
    product_o(0) <= \product_o\(0);
    mas_done_o <= \product_o\(0);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
DDbNr6ByHkR0dLEU80GFKx0vYVCcW0dGU6ZIjBwgdx42dFKm/BIoFIC5e3iee7vW
Zk+ycykwkhnWc8SjhtUWp03K/TQG4ZmrB++lY+IG/2f3G3+4ToYw2WYka5yzdsR8
wn4I5IIgU1GYQvsMdLjtWk3mDxrkYak6GByCqAIzsGI=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=11830)
`protect data_block
[encoded data, 11648 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity HALL_INTERFACE is

    port( reset_i           : in    std_logic;
          sys_clk_i         : in    std_logic;
          ha_i              : in    std_logic;
          hb_i              : in    std_logic;
          hc_i              : in    std_logic;
          clear_buffer_i    : in    std_logic;
          fil_trig_i        : in    std_logic;
          filter_factor_i   : in    std_logic_vector(3 downto 0);
          hall_sensor_pol_i : in    std_logic;
          speed_factor_i    : in    std_logic_vector(17 downto 0);
          omega_done_o      : out   std_logic;
          omega_out_o       : out   std_logic_vector(17 downto 0);
          angle_out_raw_o   : out   std_logic_vector(17 downto 0);
          theta_output_o    : out   std_logic_vector(17 downto 0)
        );

end HALL_INTERFACE;

architecture DEF_ARCH of HALL_INTERFACE is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector(19 downto 0) := x"00000");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component hall_filter
    port( s_filter_out      : out   std_logic_vector(33 downto 0);
          s_filter_val_prev : in    std_logic_vector(33 downto 0) := (others => 'U');
          s_spd_result      : in    std_logic_vector(25 downto 8) := (others => 'U');
          filter_factor_i   : in    std_logic_vector(3 downto 0) := (others => 'U');
          reset_i           : in    std_logic := 'U';
          sys_clk_i         : in    std_logic := 'U';
          fil_trig_i        : in    std_logic := 'U'
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component hall_mas_0
    port( reset_i    : in    std_logic := 'U';
          sys_clk_i  : in    std_logic := 'U';
          mas_en_i   : in    std_logic := 'U';
          sub_i      : in    std_logic := 'U';
          mul_a_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          mul_b_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          add_c_i    : in    std_logic_vector(43 downto 0) := (others => 'U');
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );
  end component;

  component CFG1
    generic (INIT:std_logic_vector(1 downto 0) := "00");

    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component hall_mas_1
    port( reset_i    : in    std_logic := 'U';
          sys_clk_i  : in    std_logic := 'U';
          mas_en_i   : in    std_logic := 'U';
          sub_i      : in    std_logic := 'U';
          mul_a_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          mul_b_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          add_c_i    : in    std_logic_vector(43 downto 0) := (others => 'U');
          product_o  : out   std_logic_vector(43 downto 0);
          mas_done_o : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \angle_out_raw_o\ : std_logic_vector(17 downto 0);
    signal \theta_output_o\ : std_logic_vector(17 downto 0);
    signal s_filter_out : std_logic_vector(33 downto 0);
    signal un12_0_iv : std_logic_vector(8 downto 0);
    signal s_spd_result : std_logic_vector(25 downto 8);
    signal s_filter_val_prev : std_logic_vector(33 downto 0);
    signal s_speed_raw_sig : std_logic_vector(16 downto 0);
    signal s_speed_count : std_logic_vector(17 downto 0);
    signal s_omega_out : std_logic_vector(33 downto 16);
    signal s_theta_buff : std_logic_vector(12 downto 0);
    signal s_theta_incr : std_logic_vector(12 downto 0);
    signal s_spd_window : std_logic_vector(3 downto 0);
    signal s_theta_output_buff : std_logic_vector(12 downto 0);
    signal s_hall_count_buff : std_logic_vector(17 downto 0);
    signal s_count_output : std_logic_vector(17 downto 0);
    signal s_spd_window_dly : std_logic_vector(3 downto 0);
    signal s_spd_window_dly1 : std_logic_vector(3 downto 0);
    signal \FILTER_ACC_PROC.s_filter_val_prev_3\ : 
        std_logic_vector(33 downto 0);
    signal \ANGLE_CNT_INCR_SIGNAL_DLY_GEN.s_speed_raw_sig_12\ : 
        std_logic_vector(14 downto 0);
    signal s_speed_raw : std_logic_vector(12 downto 0);
    signal s_count_1us : std_logic_vector(6 downto 0);
    signal s_count_terminal : std_logic_vector(10 downto 1);
    signal s_count_1us_3 : std_logic_vector(6 downto 2);
    signal s_count_in_spd_win_2 : std_logic_vector(10 downto 0);
    signal \THETA_SMOOTHEN_PROC.s_limit_angle_6\ : 
        std_logic_vector(17 downto 0);
    signal \COUNT_TERM_PROC.op_eq.s_count_in_spd_win6_0_data_tmp\
         : std_logic_vector(8 downto 0);
    signal s_speed_raw_m : std_logic_vector(12 downto 3);
    signal s_angle_out_raw : std_logic_vector(12 to 12);
    signal \op_abs.inf_abs0\ : std_logic_vector(12 downto 0);
    signal \THETA_INCR_PROC.s_theta_incr_2\ : 
        std_logic_vector(12 downto 1);
    signal s_count_in_spd_win_RNI5T0M1_S : 
        std_logic_vector(0 to 0);
    signal s_count_in_spd_win_RNIIGCS1_S : 
        std_logic_vector(1 to 1);
    signal s_count_in_spd_win_RNI05O22_S : 
        std_logic_vector(2 to 2);
    signal s_count_in_spd_win_RNIFQ392_S : 
        std_logic_vector(3 to 3);
    signal s_count_in_spd_win_RNIVGFF2_S : 
        std_logic_vector(4 to 4);
    signal s_count_in_spd_win_RNIG8RL2_S : 
        std_logic_vector(5 to 5);
    signal s_count_in_spd_win_RNI217S2_S : 
        std_logic_vector(6 to 6);
    signal s_count_in_spd_win_RNILQI23_S : 
        std_logic_vector(7 to 7);
    signal s_count_in_spd_win_RNI9LU83_S : 
        std_logic_vector(8 to 8);
    signal s_count_in_spd_win_RNIUGAF3_S : 
        std_logic_vector(9 to 9);
    signal s_count_in_spd_win_RNIR58H3_S : 
        std_logic_vector(10 to 10);
    signal s_count_in_spd_win_RNIPR5J3_S : 
        std_logic_vector(11 to 11);
    signal s_count_in_spd_win_RNIOI3L3_S : 
        std_logic_vector(12 to 12);
    signal s_count_in_spd_win_RNIOA1N3_S : 
        std_logic_vector(13 to 13);
    signal s_count_in_spd_win_RNIP3VO3_S : 
        std_logic_vector(14 to 14);
    signal s_count_in_spd_win_RNIRTSQ3_S : 
        std_logic_vector(15 to 15);
    signal s_count_in_spd_win_RNIUOQS3_S : 
        std_logic_vector(16 to 16);
    signal s_count_in_spd_win_RNO_S : std_logic_vector(17 to 17);
    signal s_count_in_spd_win : std_logic_vector(17 downto 0);
    signal s_limit_angle_RNI8ITU_S : std_logic_vector(0 to 0);
    signal s_limit_angle_RNI8K5V_S : std_logic_vector(1 to 1);
    signal s_limit_angle_RNI9NDV_S : std_logic_vector(2 to 2);
    signal s_limit_angle_RNIBRLV_S : std_logic_vector(3 to 3);
    signal s_limit_angle_RNIE0UV_S : std_logic_vector(4 to 4);
    signal s_limit_angle_RNII6601_S : std_logic_vector(5 to 5);
    signal s_limit_angle_RNINDE01_S : std_logic_vector(6 to 6);
    signal s_limit_angle_RNITLM01_S : std_logic_vector(7 to 7);
    signal s_limit_angle_RNI4VU01_S : std_logic_vector(8 to 8);
    signal s_limit_angle_RNIC9711_S : std_logic_vector(9 to 9);
    signal s_limit_angle_RNISVF91_S : std_logic_vector(10 to 10);
    signal s_limit_angle_RNIDNOH1_S : std_logic_vector(11 to 11);
    signal s_limit_angle_RNIVF1Q1_S : std_logic_vector(12 to 12);
    signal s_limit_angle_RNII9A22_S : std_logic_vector(13 to 13);
    signal s_limit_angle_RNI64JA2_S : std_logic_vector(14 to 14);
    signal s_limit_angle_RNIRVRI2_S : std_logic_vector(15 to 15);
    signal s_limit_angle_RNIHS4R2_S : std_logic_vector(16 to 16);
    signal \THETA_SMOOTHEN_PROC.s_limit_angle_6_RNO_S\ : 
        std_logic_vector(17 to 17);
    signal s_limit_angle : std_logic_vector(17 downto 0);
    signal s_speed_count_cry : std_logic_vector(16 downto 0);
    signal s_speed_count_s : std_logic_vector(17 downto 0);
    signal 
        \ANGLE_CNT_INCR_SIGNAL_DLY_GEN.s_speed_raw_sig_12_iv_0\
         : std_logic_vector(12 downto 2);
    signal 
        \ANGLE_CNT_INCR_SIGNAL_DLY_GEN.s_speed_raw_sig_12_0_iv_0\
         : std_logic_vector(13 to 13);
    signal 
        \COUNT_TERM_PROC.op_eq.s_count_in_spd_win6_0_data_tmp_i_0\
         : std_logic_vector(8 to 8);
    signal s_spd_window_i_0 : std_logic_vector(3 downto 1);
    signal s_count_1us_i_0 : std_logic_vector(0 to 0);
    signal un12_0_iv_0 : std_logic_vector(8 to 8);
    signal un12_0_iv_1 : std_logic_vector(8 to 8);
    signal un12_0_iv_2 : std_logic_vector(8 to 8);
    signal un12_0_iv_3 : std_logic_vector(8 to 8);
    signal s_speed_count_cry_Y : std_logic_vector(16 downto 0);
    signal s_speed_count_s_FCO : std_logic_vector(17 to 17);
    signal s_speed_count_s_Y : std_logic_vector(17 to 17);
    signal s_speed_count_cry_cy_S : std_logic_vector(0 to 0);
    signal s_speed_count_cry_cy_Y : std_logic_vector(0 to 0);
    signal s_limit_angle_RNIHS4R2_Y : std_logic_vector(16 to 16);
    signal \THETA_SMOOTHEN_PROC.s_limit_angle_6_RNO_FCO\ : 
        std_logic_vector(17 to 17);
    signal \THETA_SMOOTHEN_PROC.s_limit_angle_6_RNO_Y\ : 
        std_logic_vector(17 to 17);
    signal s_limit_angle_RNIRVRI2_Y : std_logic_vector(15 to 15);
    signal s_limit_angle_RNI64JA2_Y : std_logic_vector(14 to 14);
    signal s_limit_angle_RNII9A22_Y : std_logic_vector(13 to 13);
    signal s_limit_angle_RNIVF1Q1_Y : std_logic_vector(12 to 12);
    signal s_limit_angle_RNIDNOH1_Y : std_logic_vector(11 to 11);
    signal s_limit_angle_RNISVF91_Y : std_logic_vector(10 to 10);
    signal s_limit_angle_RNIC9711_Y : std_logic_vector(9 to 9);
    signal s_limit_angle_RNI4VU01_Y : std_logic_vector(8 to 8);
    signal s_limit_angle_RNITLM01_Y : std_logic_vector(7 to 7);
    signal s_limit_angle_RNINDE01_Y : std_logic_vector(6 to 6);
    signal s_limit_angle_RNII6601_Y : std_logic_vector(5 to 5);
    signal s_limit_angle_RNIE0UV_Y : std_logic_vector(4 to 4);
    signal s_limit_angle_RNIBRLV_Y : std_logic_vector(3 to 3);
    signal s_limit_angle_RNI9NDV_Y : std_logic_vector(2 to 2);
    signal s_limit_angle_RNI8K5V_Y : std_logic_vector(1 to 1);
    signal s_limit_angle_RNI8ITU_Y : std_logic_vector(0 to 0);
    signal s_count_in_spd_win_RNIUOQS3_Y : 
        std_logic_vector(16 to 16);
    signal s_count_in_spd_win_RNO_FCO : 
        std_logic_vector(17 to 17);
    signal s_count_in_spd_win_RNO_Y : std_logic_vector(17 to 17);
    signal s_count_in_spd_win_RNIRTSQ3_Y : 
        std_logic_vector(15 to 15);
    signal s_count_in_spd_win_RNIP3VO3_Y : 
        std_logic_vector(14 to 14);
    signal s_count_in_spd_win_RNIOA1N3_Y : 
        std_logic_vector(13 to 13);
    signal s_count_in_spd_win_RNIOI3L3_Y : 
        std_logic_vector(12 to 12);
    signal s_count_in_spd_win_RNIPR5J3_Y : 
        std_logic_vector(11 to 11);
    signal s_count_in_spd_win_RNIR58H3_Y : 
        std_logic_vector(10 to 10);
    signal s_count_in_spd_win_RNIUGAF3_Y : 
        std_logic_vector(9 to 9);
    signal s_count_in_spd_win_RNI9LU83_Y : 
        std_logic_vector(8 to 8);
    signal s_count_in_spd_win_RNILQI23_Y : 
        std_logic_vector(7 to 7);
    signal s_count_in_spd_win_RNI217S2_Y : 
        std_logic_vector(6 to 6);
    signal s_count_in_spd_win_RNIG8RL2_Y : 
        std_logic_vector(5 to 5);
    signal s_count_in_spd_win_RNIVGFF2_Y : 
        std_logic_vector(4 to 4);
    signal s_count_in_spd_win_RNIFQ392_Y : 
        std_logic_vector(3 to 3);
    signal s_count_in_spd_win_RNI05O22_Y : 
        std_logic_vector(2 to 2);
    signal s_count_in_spd_win_RNIIGCS1_Y : 
        std_logic_vector(1 to 1);
    signal s_count_in_spd_win_RNI5T0M1_Y : 
        std_logic_vector(0 to 0);
    signal product_o_0 : std_logic_vector(43 downto 0);
    signal product_o : std_logic_vector(43 downto 0);
    signal MSC_net_735, MSC_net_736, MSC_net_737, MSC_net_738, 
        MSC_net_739, MSC_net_740, MSC_net_741, MSC_net_742, 
        MSC_net_743, MSC_net_744, MSC_net_745, MSC_net_746, 
        MSC_net_747, MSC_net_748, MSC_net_749, MSC_net_750, 
        MSC_net_751, MSC_net_752, MSC_net_753, MSC_net_754, 
        MSC_net_755, MSC_net_756, MSC_net_757, MSC_net_758, 
        MSC_net_759, MSC_net_760, 
        \THETA_INCR_PROC.un5_s_spd_win_term_flag_Z\, 
        \THETA_INCR_ROLL_PROC.un5_s_theta_incr_calc_done_Z\, 
        MSC_net_763, \SPD_WIN_PROC.un5_s_theta_roll_calc_done_Z\, 
        MSC_net_765, 
        \ANGLE_CNT_INCR_SIGNAL_DLY_GEN.un20_s_spd_win_term_flag_Z\, 
        \SPD_WINDOW_TIME_GEN.un1_s_spd_window_Z\, MSC_net_768, 
        \EDGE_DETECT_PROC.s_hall_edge_det_1_Z\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us\, 
        \THETA_SMOOTHEN_PROC.un16_s_hall_edge_det\, 
        \THETA_SMOOTHEN_PROC.un25_s_trigger_1us\, 
        \COUNT_TERM_PROC.un14_s_trigger_1us_Z\, 
        \DIR_DETECT_PROC.un9_s_tmp5_Z\, MSC_net_775, MSC_net_776, 
        MSC_net_777, MSC_net_778, MSC_net_779, MSC_net_780, 
        \THETA_SMOOTHEN_PROC.un25_s_trigger_1uslt7\, 
        \THETA_SMOOTHEN_PROC.un25_s_trigger_1uslt4\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_0_Z\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_1_Z\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_2_Z\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_3_Z\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_4_Z\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_5_Z\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_6_Z\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_7_Z\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_8_Z\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_9_Z\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_10_Z\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_11_Z\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_12_Z\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_13_Z\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_14_Z\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_15_Z\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_16_Z\, 
        \THETA_SMOOTHEN_PROC.s_count_output_5_iv_10_262_Z\, 
        \THETA_SMOOTHEN_PROC.s_count_output_5_iv_6_298_Z\, 
        \THETA_SMOOTHEN_PROC.s_count_output_5_iv_4_316_Z\, 
        \THETA_SMOOTHEN_PROC.s_count_output_5_iv_0_352_Z\, 
        MSC_net_804, MSC_net_805, MSC_net_806, MSC_net_807, 
        \THETA_SMOOTHEN_PROC.un18_s_trigger_1us_Z\, 
        \THETA_SMOOTHEN_PROC.un19_s_trigger_1us_Z\, MSC_net_810, 
        MSC_net_811, MSC_net_812, MSC_net_813, MSC_net_814, 
        MSC_net_815, MSC_net_816, MSC_net_817, MSC_net_818, 
        MSC_net_819, MSC_net_820, MSC_net_821, MSC_net_822, 
        \SPD_WIN_PROC.un20_s_theta_roll_calc_done_Z\, 
        \SPD_WIN_PROC.un14_s_theta_roll_calc_done_Z\, 
        \SPD_WIN_PROC.un9_s_theta_roll_calc_done\, 
        \EDGE_DETECT_PROC.s_hall_edge_det_1_4_Z\, MSC_net_827, 
        MSC_net_828, MSC_net_829, MSC_net_830, MSC_net_831, 
        MSC_net_832, MSC_net_833, MSC_net_834, MSC_net_835, 
        MSC_net_836, MSC_net_837, MSC_net_838, MSC_net_839, 
        MSC_net_840, MSC_net_841, MSC_net_842, MSC_net_843, 
        \op_abs.inf_abs0_cry_0_Z\, \op_abs.inf_abs0_cry_1_Z\, 
        \op_abs.inf_abs0_cry_2_Z\, \op_abs.inf_abs0_cry_3_Z\, 
        \op_abs.inf_abs0_cry_4_Z\, \op_abs.inf_abs0_cry_5_Z\, 
        \op_abs.inf_abs0_cry_6_Z\, \op_abs.inf_abs0_cry_7_Z\, 
        \op_abs.inf_abs0_cry_8_Z\, \op_abs.inf_abs0_cry_9_Z\, 
        \op_abs.inf_abs0_cry_10_Z\, MSC_net_855, MSC_net_856, 
        MSC_net_857, MSC_net_858, MSC_net_859, MSC_net_860, 
        MSC_net_861, MSC_net_862, MSC_net_863, MSC_net_864, 
        MSC_net_865, MSC_net_866, MSC_net_867, MSC_net_868, 
        MSC_net_869, MSC_net_870, MSC_net_871, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_0_Z\, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_1_Z\, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_2_Z\, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_3_Z\, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_4_Z\, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_5_Z\, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_6_Z\, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_7_Z\, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_8_Z\, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_9_Z\, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_10_Z\, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_11_Z\, MSC_net_884, 
        MSC_net_885, MSC_net_886, MSC_net_887, MSC_net_888, 
        MSC_net_889, MSC_net_890, MSC_net_891, MSC_net_892, 
        MSC_net_893, MSC_net_894, MSC_net_895, MSC_net_896, 
        MSC_net_897, MSC_net_898, MSC_net_899, MSC_net_900, 
        MSC_net_901, MSC_net_902, MSC_net_903, MSC_net_904, 
        MSC_net_905, MSC_net_906, MSC_net_907, MSC_net_908, 
        MSC_net_909, MSC_net_910, MSC_net_911, MSC_net_912, 
        MSC_net_913, MSC_net_914, MSC_net_915, MSC_net_916, 
        MSC_net_917, MSC_net_918, MSC_net_919, MSC_net_920, 
        MSC_net_921, MSC_net_922, MSC_net_923, MSC_net_924, 
        MSC_net_925, MSC_net_926, MSC_net_927, MSC_net_928, 
        MSC_net_929, MSC_net_930, MSC_net_931, MSC_net_932, 
        MSC_net_933, MSC_net_934, MSC_net_935, MSC_net_936, 
        MSC_net_937, MSC_net_938, MSC_net_939, MSC_net_940, 
        MSC_net_941, MSC_net_942, MSC_net_943, MSC_net_944, 
        MSC_net_945, MSC_net_946, MSC_net_947, MSC_net_948, 
        MSC_net_949, MSC_net_950, MSC_net_951, MSC_net_952, 
        MSC_net_953, MSC_net_954, MSC_net_955, MSC_net_956, 
        MSC_net_957, MSC_net_958, MSC_net_959, MSC_net_960, 
        MSC_net_961, 
        \THETA_SMOOTHEN_PROC.op_eq.un13_s_hall_edge_det_9_Z\, 
        \THETA_SMOOTHEN_PROC.op_eq.un13_s_hall_edge_det_10_Z\, 
        \THETA_SMOOTHEN_PROC.op_eq.un13_s_hall_edge_det_11_Z\, 
        \THETA_SMOOTHEN_PROC.op_eq.un13_s_hall_edge_det_12_Z\, 
        \THETA_SMOOTHEN_PROC.op_eq.un13_s_hall_edge_det_15_Z\, 
        \THETA_SMOOTHEN_PROC.un25_s_trigger_1uslto16_4_Z\, 
        \THETA_SMOOTHEN_PROC.un25_s_trigger_1uslto16_5_Z\, 
        \THETA_SMOOTHEN_PROC.un25_s_trigger_1uslto16_7_Z\, 
        MSC_net_970, \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_i_0\, 
        \SPD_WIN_PROC.un18_s_theta_roll_calc_done_i_0\, 
        MSC_net_973, MSC_net_974, MSC_net_975, 
        \THETA_INCR_PROC.s_theta_incr_2_axb_0_i_0_Z\, MSC_net_977, 
        MSC_net_978, MSC_net_979, 
        \COUNT_1MS_PROC.s_count_1us7lto6_1_Z\, MSC_net_981, 
        MSC_net_982, \op_abs.inf_abs0_s_0_501_FCO\, MSC_net_984, 
        MSC_net_985, MSC_net_986, MSC_net_987, MSC_net_988, 
        MSC_net_989, MSC_net_990, MSC_net_991, MSC_net_992, 
        MSC_net_993, MSC_net_994, MSC_net_995, MSC_net_996, 
        MSC_net_997, MSC_net_998, MSC_net_999, MSC_net_1000, 
        MSC_net_1001, MSC_net_1002, MSC_net_1003, MSC_net_1004, 
        MSC_net_1005, \op_abs.inf_abs0_cry_11_Y\, 
        \op_abs.inf_abs0_cry_10_Y\, \op_abs.inf_abs0_cry_9_Y\, 
        \op_abs.inf_abs0_cry_8_Y\, \op_abs.inf_abs0_cry_7_Y\, 
        \op_abs.inf_abs0_cry_6_Y\, \op_abs.inf_abs0_cry_5_Y\, 
        \op_abs.inf_abs0_cry_4_Y\, \op_abs.inf_abs0_cry_3_Y\, 
        \op_abs.inf_abs0_cry_2_Y\, \op_abs.inf_abs0_cry_1_Y\, 
        \op_abs.inf_abs0_cry_0_Y\, \op_abs.inf_abs0_s_0_501_S\, 
        \op_abs.inf_abs0_s_0_501_Y\, MSC_net_1020, MSC_net_1021, 
        MSC_net_1022, MSC_net_1023, MSC_net_1024, MSC_net_1025, 
        MSC_net_1026, MSC_net_1027, MSC_net_1028, MSC_net_1029, 
        MSC_net_1030, MSC_net_1031, MSC_net_1032, MSC_net_1033, 
        MSC_net_1034, MSC_net_1035, MSC_net_1036, MSC_net_1037, 
        MSC_net_1038, MSC_net_1039, MSC_net_1040, MSC_net_1041, 
        MSC_net_1042, MSC_net_1043, MSC_net_1044, MSC_net_1045, 
        MSC_net_1046, MSC_net_1047, MSC_net_1048, 
        \COUNT_TERM_PROC.op_eq.s_count_in_spd_win6_0_I_51_S\, 
        \COUNT_TERM_PROC.op_eq.s_count_in_spd_win6_0_I_51_Y\, 
        \COUNT_TERM_PROC.op_eq.s_count_in_spd_win6_0_I_45_S\, 
        \COUNT_TERM_PROC.op_eq.s_count_in_spd_win6_0_I_45_Y\, 
        \COUNT_TERM_PROC.op_eq.s_count_in_spd_win6_0_I_39_S\, 
        \COUNT_TERM_PROC.op_eq.s_count_in_spd_win6_0_I_39_Y\, 
        \COUNT_TERM_PROC.op_eq.s_count_in_spd_win6_0_I_33_S\, 
        \COUNT_TERM_PROC.op_eq.s_count_in_spd_win6_0_I_33_Y\, 
        \COUNT_TERM_PROC.op_eq.s_count_in_spd_win6_0_I_27_S\, 
        \COUNT_TERM_PROC.op_eq.s_count_in_spd_win6_0_I_27_Y\, 
        \COUNT_TERM_PROC.op_eq.s_count_in_spd_win6_0_I_21_S\, 
        \COUNT_TERM_PROC.op_eq.s_count_in_spd_win6_0_I_21_Y\, 
        \COUNT_TERM_PROC.op_eq.s_count_in_spd_win6_0_I_15_S\, 
        \COUNT_TERM_PROC.op_eq.s_count_in_spd_win6_0_I_15_Y\, 
        \COUNT_TERM_PROC.op_eq.s_count_in_spd_win6_0_I_9_S\, 
        \COUNT_TERM_PROC.op_eq.s_count_in_spd_win6_0_I_9_Y\, 
        \COUNT_TERM_PROC.op_eq.s_count_in_spd_win6_0_I_1_S\, 
        \COUNT_TERM_PROC.op_eq.s_count_in_spd_win6_0_I_1_Y\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_17_S\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_17_Y\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_16_S\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_16_Y\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_15_S\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_15_Y\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_14_S\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_14_Y\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_13_S\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_13_Y\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_12_S\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_12_Y\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_11_S\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_11_Y\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_10_S\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_10_Y\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_9_S\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_9_Y\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_8_S\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_8_Y\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_7_S\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_7_Y\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_6_S\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_6_Y\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_5_S\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_5_Y\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_4_S\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_4_Y\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_3_S\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_3_Y\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_2_S\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_2_Y\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_1_S\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_1_Y\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_0_S\, 
        \THETA_SMOOTHEN_PROC.un22_s_trigger_1us_cry_0_Y\, 
        MSC_net_1103, MSC_net_1104, MSC_net_1105, MSC_net_1106, 
        MSC_net_1107, MSC_net_1108, MSC_net_1109, MSC_net_1110, 
        MSC_net_1111, MSC_net_1112, MSC_net_1113, MSC_net_1114, 
        MSC_net_1115, MSC_net_1116, MSC_net_1117, MSC_net_1118, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_11_Y\, 
        \THETA_INCR_PROC.s_theta_incr_2_s_12_FCO\, 
        \THETA_INCR_PROC.s_theta_incr_2_s_12_Y\, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_10_Y\, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_9_Y\, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_8_Y\, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_7_Y\, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_6_Y\, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_5_Y\, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_4_Y\, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_3_Y\, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_2_Y\, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_1_Y\, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_0_S\, 
        \THETA_INCR_PROC.s_theta_incr_2_cry_0_Y\, 
        \THETA_SMOOTHEN_PROC.un25_s_trigger_1uslto17_RNI9HLU_S\, 
        \THETA_SMOOTHEN_PROC.un25_s_trigger_1uslto17_RNI9HLU_Y\, 
        \COUNT_1MS_PROC.s_count_1us7lto6_1_RNIPALF1_S\, 
        \COUNT_1MS_PROC.s_count_1us7lto6_1_RNIPALF1_Y\, 
        MSC_net_1138, MSC_net_1139 : std_logic;

    for all : hall_filter
	Use entity work.hall_filter(DEF_ARCH);
    for all : hall_mas_0
	Use entity work.hall_mas_0(DEF_ARCH);
    for all : hall_mas_1
	Use entity work.hall_mas_1(DEF_ARCH);
begin 

    \theta_output_o\(4 downto 0) <= (OTHERS => 'U'); 
    \angle_out_raw_o\(17 downto 14) <= (OTHERS => 'U'); 
    \angle_out_raw_o\(12 downto 11) <= (OTHERS => 'U'); 
    \angle_out_raw_o\(8 downto 1) <= (OTHERS => 'U'); 
    omega_done_o <= \angle_out_raw_o\(13);
    angle_out_raw_o(17) <= \angle_out_raw_o\(13);
    angle_out_raw_o(16) <= \angle_out_raw_o\(13);
    angle_out_raw_o(15) <= \angle_out_raw_o\(13);
    angle_out_raw_o(14) <= \angle_out_raw_o\(13);
    angle_out_raw_o(13) <= \angle_out_raw_o\(13);
    angle_out_raw_o(10) <= \angle_out_raw_o\(10);
    angle_out_raw_o(9) <= \angle_out_raw_o\(9);
    angle_out_raw_o(8) <= \angle_out_raw_o\(10);
    angle_out_raw_o(7) <= \angle_out_raw_o\(9);
    angle_out_raw_o(6) <= \angle_out_raw_o\(10);
    angle_out_raw_o(5) <= \angle_out_raw_o\(9);
    angle_out_raw_o(4) <= \angle_out_raw_o\(10);
    angle_out_raw_o(3) <= \angle_out_raw_o\(9);
    angle_out_raw_o(2) <= \angle_out_raw_o\(10);
    angle_out_raw_o(1) <= \angle_out_raw_o\(9);
    angle_out_raw_o(0) <= \angle_out_raw_o\(0);
    theta_output_o(17) <= \theta_output_o\(17);
    theta_output_o(16) <= \theta_output_o\(16);
    theta_output_o(15) <= \theta_output_o\(15);
    theta_output_o(14) <= \theta_output_o\(14);
    theta_output_o(13) <= \theta_output_o\(13);
    theta_output_o(12) <= \theta_output_o\(12);
    theta_output_o(11) <= \theta_output_o\(11);
    theta_output_o(10) <= \theta_output_o\(10);
    theta_output_o(9) <= \theta_output_o\(9);
    theta_output_o(8) <= \theta_output_o\(8);
    theta_output_o(7) <= \theta_output_o\(7);
    theta_output_o(6) <= \theta_output_o\(6);
    theta_output_o(5) <= \theta_output_o\(5);
    theta_output_o(4) <= \angle_out_raw_o\(13);
    theta_output_o(3) <= \angle_out_raw_o\(13);
    theta_output_o(2) <= \angle_out_raw_o\(13);
    theta_output_o(1) <= \angle_out_raw_o\(13);
    theta_output_o(0) <= \angle_out_raw_o\(13);


`protect begin_protected
`protect version=1
`protect author="author-a", author_info="author-a-details"

`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding=(enctype="base64", line_length=76, bytes=128)
`protect key_block
kJCfNAKbN7H7UVYY+aleZpThVCW0wXln2/4jcnX5mlVRU1GcWQ3g8FkM+gGTCg4E
if/PJAVCZp6DGlH351cFljUXUbhp220CvViq/jQ8uF8wkPuAHReorbjItqS5pdmY
2zFmex2/tDXRxkZcJmMnzIRSJ9OZKzI8mHsiTymS3T4=

`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`protect encoding=(enctype="base64", line_length=76, bytes=268125)
`protect data_block
[encoded data, 264000 characters]

`protect end_protected

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity apb3_hall_if is

    port( apb3_en_if_1_idq_pi_ki_o              : out   std_logic_vector(17 downto 0);
          MC_System_0_AMBA_SLAVE_0_PWDATA       : in    std_logic_vector(17 downto 0);
          apb3_en_if_1_idq_pi_kp_o              : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_olmng_dv_o               : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_olmng_iq_ref_in_o        : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_olmng_theta_factor_o     : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_pwm_dead_time_val_o      : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_pwm_delay_time_val_o     : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_pwm_gain_val_o           : out   std_logic_vector(17 downto 1);
          apb3_en_if_1_pwm_period_val_o         : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_rate_limit_rate_cnt_o    : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_rate_limit_ref_in_o      : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_rate_limit_slew_cnt_o    : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_seq_cntl_cl_omega_o      : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_speed_pi_ki_o            : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_speed_pi_kp_o            : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_seq_cntl_config_o        : out   std_logic_vector(3 downto 0);
          apb3_hall_if_0_hall_filter_factor_o   : out   std_logic_vector(3 downto 0);
          apb3_en_if_1_auto_restart_no_o        : out   std_logic_vector(3 downto 0);
          apb3_en_if_1_adc_control_reg_val_o    : out   std_logic_vector(5 downto 0);
          apb3_en_if_1_adc_channel_ch0_o        : out   std_logic_vector(15 downto 0);
          apb3_en_if_1_adc_channel_ch1_o        : out   std_logic_vector(15 downto 0);
          apb3_en_if_1_adc_channel_ch2_o        : out   std_logic_vector(15 downto 0);
          apb3_en_if_1_adc_channel_ch3_o        : out   std_logic_vector(15 downto 0);
          apb3_en_if_1_adc_oc_thresh_o          : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_adc_scale_val_o          : out   std_logic_vector(17 downto 0);
          apb3_hall_if_0_hall_speed_factor_o    : out   std_logic_vector(17 downto 0);
          MC_System_0_AMBA_SLAVE_0_PRDATA       : out   std_logic_vector(19 to 19);
          prdata_o_1_iv_0_0_a3_2_0              : out   std_logic_vector(9 to 9);
          prdata_o_1_0_iv_0_8_13                : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PADDR        : in    std_logic_vector(11 downto 0);
          prdata_o_1_iv_0_0_7_2                 : out   std_logic;
          prdata_o_1_iv_0_0_15                  : out   std_logic_vector(8 to 8);
          prdata_o_0_5                          : out   std_logic_vector(17 to 17);
          prdata_o_1_iv_0_0_5_0                 : out   std_logic;
          prdata_o_1_iv_0_0_a1                  : out   std_logic_vector(6 downto 5);
          prdata_o_1_iv_0_0_0                   : out   std_logic;
          prdata_o_1_iv_0_0_6                   : out   std_logic;
          HALL_INTERFACE_1_theta_output_o_6     : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_1     : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_0     : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_9     : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_8     : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_5     : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_10    : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_3     : in    std_logic;
          HALL_INTERFACE_1_theta_output_o_7     : in    std_logic;
          FOC_TRANSFORMS_0_id_o_0               : in    std_logic;
          FOC_TRANSFORMS_0_id_o_10              : in    std_logic;
          FOC_TRANSFORMS_0_id_o_13              : in    std_logic;
          FOC_TRANSFORMS_0_id_o_17              : in    std_logic;
          FOC_TRANSFORMS_0_id_o_3               : in    std_logic;
          FOC_TRANSFORMS_0_id_o_11              : in    std_logic;
          FOC_TRANSFORMS_0_id_o_16              : in    std_logic;
          FOC_TRANSFORMS_0_id_o_1               : in    std_logic;
          FOC_TRANSFORMS_0_id_o_2               : in    std_logic;
          FOC_TRANSFORMS_0_id_o_15              : in    std_logic;
          FOC_TRANSFORMS_0_id_o_12              : in    std_logic;
          FOC_TRANSFORMS_0_id_o_7               : in    std_logic;
          FOC_TRANSFORMS_0_id_o_6               : in    std_logic;
          FOC_TRANSFORMS_0_id_o_5               : in    std_logic;
          FOC_TRANSFORMS_0_id_o_8               : in    std_logic;
          FOC_TRANSFORMS_0_id_o_9               : in    std_logic;
          FOC_TRANSFORMS_0_id_o_14              : in    std_logic;
          ADC_SCALING_0_ib_adc_o                : in    std_logic_vector(17 downto 0);
          FOC_TRANSFORMS_0_iq_o_2               : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_1               : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_8               : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_16              : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_7               : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_3               : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_0               : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_17              : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_5               : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_11              : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_10              : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_4               : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_14              : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_13              : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_15              : in    std_logic;
          FOC_TRANSFORMS_0_iq_o_12              : in    std_logic;
          prdata_o_1_0_iv_0_0_11_a2             : out   std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_0_11_a0             : out   std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_11_a2               : out   std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_11_a0               : out   std_logic_vector(13 to 13);
          SEQ_CONTROLLER_0_state_o              : in    std_logic_vector(3 downto 0);
          ADC_SCALING_0_ia_adc_o                : in    std_logic_vector(17 downto 0);
          prdata_o_1_0_iv_0_1_15                : out   std_logic;
          prdata_o_1_iv_0_9                     : out   std_logic_vector(5 to 5);
          prdata_o_1_iv_0_8_0                   : out   std_logic;
          prdata_o_1_iv_0_6_0                   : out   std_logic;
          adc_interface_0_result_ch3_o          : in    std_logic_vector(11 downto 0);
          prdata_o_1_iv_0_0_10_2                : out   std_logic;
          prdata_o_1_iv_0_0_10_0                : out   std_logic;
          prdata_o_1_0_iv_0_0_7_11              : out   std_logic;
          prdata_o_1_0_iv_0_0_6_11              : out   std_logic;
          prdata_o_1_0_iv_0_7_4                 : out   std_logic;
          prdata_o_1_0_iv_0_7_13                : out   std_logic;
          FOC_TRANSFORMS_0_ialpha_o             : in    std_logic_vector(17 downto 0);
          FOC_TRANSFORMS_0_valpha_o_17          : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_12          : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_7           : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_10          : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_3           : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_4           : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_16          : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_0           : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_1           : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_2           : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_15          : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_8           : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_14          : in    std_logic;
          FOC_TRANSFORMS_0_valpha_o_13          : in    std_logic;
          prdata_o_1_0_iv_0_6_16                : out   std_logic;
          prdata_o_1_0_iv_0_6_13                : out   std_logic;
          prdata_o_1_0_iv_0_5_16                : out   std_logic;
          FOC_TRANSFORMS_0_vbeta_o              : in    std_logic_vector(17 downto 0);
          prdata_o_1_0_iv_0_4_15                : out   std_logic;
          prdata_o_1_0_iv_0_3_16                : out   std_logic;
          OLMNG_0_theta_o_10                    : in    std_logic;
          OLMNG_0_theta_o_0                     : in    std_logic;
          OLMNG_0_theta_o_8                     : in    std_logic;
          OLMNG_0_theta_o_4                     : in    std_logic;
          OLMNG_0_theta_o_17                    : in    std_logic;
          OLMNG_0_theta_o_3                     : in    std_logic;
          OLMNG_0_theta_o_16                    : in    std_logic;
          OLMNG_0_theta_o_1                     : in    std_logic;
          OLMNG_0_theta_o_2                     : in    std_logic;
          OLMNG_0_theta_o_15                    : in    std_logic;
          OLMNG_0_theta_o_7                     : in    std_logic;
          OLMNG_0_theta_o_14                    : in    std_logic;
          OLMNG_0_theta_o_13                    : in    std_logic;
          OLMNG_0_theta_o_12                    : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_10    : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_7     : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_4     : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_3     : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_8     : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_17    : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_16    : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_0     : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_1     : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_2     : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_15    : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_14    : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_13    : in    std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_12    : in    std_logic;
          adc_interface_0_result_ch2_o          : in    std_logic_vector(11 downto 0);
          FOC_TRANSFORMS_0_ibeta_o              : in    std_logic_vector(17 downto 0);
          prdata_o_1_iv_0_12                    : out   std_logic_vector(5 to 5);
          prdata_o_1_iv_0_7_0                   : out   std_logic;
          prdata_o_1_iv_0_0_14                  : out   std_logic_vector(10 downto 8);
          prdata_o_1_iv_0_14_0                  : out   std_logic;
          prdata_o_1_iv_0_14_5                  : out   std_logic;
          SPEED_ID_IQ_PI_0_speed_pi_output_o    : in    std_logic_vector(17 downto 0);
          adc_interface_0_result_ch0_o          : in    std_logic_vector(11 downto 0);
          adc_interface_0_result_ch1_o_0        : in    std_logic;
          adc_interface_0_result_ch1_o_1        : in    std_logic;
          adc_interface_0_result_ch1_o_8        : in    std_logic;
          adc_interface_0_result_ch1_o_10       : in    std_logic;
          adc_interface_0_result_ch1_o_7        : in    std_logic;
          adc_interface_0_result_ch1_o_6        : in    std_logic;
          adc_interface_0_result_ch1_o_9        : in    std_logic;
          adc_interface_0_result_ch1_o_11       : in    std_logic;
          adc_interface_0_result_ch1_o_3        : in    std_logic;
          adc_interface_0_result_ch1_o_5        : in    std_logic;
          adc_interface_0_result_ch1_o_2        : in    std_logic;
          HALL_INTERFACE_1_omega_out_o          : in    std_logic_vector(17 downto 0);
          prdata_o_1_iv_0_0_11_2                : out   std_logic;
          prdata_o_1_iv_0_0_11_0                : out   std_logic;
          SPEED_ID_IQ_PI_0_iq_pi_output_o       : in    std_logic_vector(17 downto 0);
          prdata_o_1_0_iv_0_14_2                : out   std_logic;
          prdata_o_1_0_iv_0_14_0                : out   std_logic;
          prdata_o_1_0_iv_0_14_1                : out   std_logic;
          prdata_o_1_0_iv_0_14_4                : out   std_logic;
          prdata_o_1_0_iv_0_0_8_11              : out   std_logic;
          prdata_o_1_0_iv_0_9_12                : out   std_logic;
          prdata_o_1_0_iv_0_0_11                : out   std_logic_vector(15 to 15);
          prdata_o_1_0_iv_0_11                  : out   std_logic_vector(16 to 16);
          prdata_o_0_3                          : out   std_logic_vector(17 to 17);
          prdata_o_1_0_iv_0_15_0                : out   std_logic;
          prdata_o_1_0_iv_0_15_4                : out   std_logic;
          prdata_o_1_0_iv_0_15_2                : out   std_logic;
          prdata_o_1_0_iv_0_15_1                : out   std_logic;
          prdata_o_1_0_iv_0_0_14                : out   std_logic_vector(3 to 3);
          HALL_INTERFACE_1_angle_out_raw_o      : in    std_logic_vector(12 downto 0);
          prdata_o_1_0_iv_0_0_9_11              : out   std_logic;
          prdata_o_1_0_iv_0_0_9_12              : out   std_logic;
          prdata_o_1_0_iv_0_0_9_0               : out   std_logic;
          prdata_o_1_0_iv_0_0_10_0              : out   std_logic;
          prdata_o_1_0_iv_0_0_10_12             : out   std_logic;
          RATE_LIMITER_0_rl_out_o               : in    std_logic_vector(17 downto 0);
          prdata_o_1_iv_0_0_12_3                : out   std_logic;
          prdata_o_1_iv_0_0_12_0                : out   std_logic;
          prdata_o_1_iv_0_0_12_5                : out   std_logic;
          prdata_o_1_iv_0_0_16                  : out   std_logic_vector(9 downto 8);
          prdata_o_1_iv_0_16_0                  : out   std_logic;
          prdata_o_1_iv_0_16_5                  : out   std_logic;
          prdata_o_1_0_iv_0_16                  : out   std_logic_vector(2 downto 0);
          prdata_o_1_iv_0_0_13                  : out   std_logic_vector(7 to 7);
          MC_System_0_FIC_0_LOCK                : in    std_logic;
          MC_System_0_FIC_0_CLK                 : in    std_logic;
          apb3_en_if_1_stop_motor_o             : out   std_logic;
          apb3_en_if_1_start_motor_o            : out   std_logic;
          apb3_hall_if_0_hall_sensor_polarity_o : out   std_logic;
          apb3_en_if_1_fault_clr_o              : out   std_logic;
          apb3_en_if_0_direction_config_o       : out   std_logic;
          prdata_o276                           : out   std_logic;
          G_15_1                                : out   std_logic;
          N_730                                 : out   std_logic;
          N_748                                 : out   std_logic;
          prdata_o_1_iv_0_0_a3_27_out           : out   std_logic;
          prdata_o_1_iv_0_0_a3_9_out            : out   std_logic;
          N_737                                 : out   std_logic;
          N_759                                 : out   std_logic;
          N_705                                 : out   std_logic;
          prdata_o_1_iv_0_0_a3_0_out            : out   std_logic;
          N_734                                 : out   std_logic;
          N_745                                 : in    std_logic;
          prdata_m1_e_8_1                       : out   std_logic;
          prdata_m1_e_4_1                       : out   std_logic;
          prdata_m1_e_12_1                      : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PWRITE       : in    std_logic;
          MC_System_0_AMBA_SLAVE_0_PENABLE      : in    std_logic;
          prdata_N_5_mux_6                      : out   std_logic;
          prdata_N_5_mux_7                      : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PSELx        : in    std_logic;
          N_358                                 : out   std_logic;
          N_634                                 : out   std_logic;
          N_462                                 : out   std_logic;
          N_449                                 : out   std_logic;
          N_442                                 : out   std_logic;
          N_440                                 : out   std_logic
        );

end apb3_hall_if;

architecture DEF_ARCH of apb3_hall_if is 

  component CFG4
    generic (INIT:std_logic_vector(15 downto 0) := x"0000");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector(3 downto 0) := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector(7 downto 0) := x"00");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \prdata_o_1_iv_0_0_a3_2_0\ : 
        std_logic_vector(9 to 9);
    signal \prdata_o_0_5\ : std_logic_vector(17 to 17);
    signal \prdata_o_0_3\ : std_logic_vector(17 to 17);
    signal \prdata_o276\, \G_15_1\, \N_730\, \N_748\, 
        \prdata_o_1_iv_0_0_a3_27_out\, 
        \prdata_o_1_iv_0_0_a3_9_out\, \N_737\, \N_759\, \N_705\, 
        \prdata_o_1_iv_0_0_a3_0_out\, \N_734\ : std_logic;
    signal prdata_o_2 : std_logic_vector(31 to 31);
    signal prdata_o_1_0_iv_0_15_sx_RNO : 
        std_logic_vector(0 to 0);
    signal prdata_o_1_0_iv_0_0_a0_1_sx : 
        std_logic_vector(2 to 2);
    signal prdata_o_1_0_iv_0_0_a0_1 : 
        std_logic_vector(2 downto 1);
    signal prdata_o_1_iv_0_0_a3_2_sx : std_logic_vector(9 to 9);
    signal prdata_o_1_iv_0_0_a3_2_sx_0 : 
        std_logic_vector(9 to 9);
    signal prdata_o_1_iv_0_0_a3_16_sx : std_logic_vector(9 to 9);
    signal prdata_o_1_iv_0_0_a3_16_sx_0 : 
        std_logic_vector(9 to 9);
    signal prdata_o_1_iv_0_0_a3_16_0 : std_logic_vector(9 to 9);
    signal prdata_o_1_0_iv_0_3 : std_logic_vector(4 downto 0);
    signal prdata_o_1_0_iv_0_3_sx : std_logic_vector(0 to 0);
    signal prdata_o_1_0_iv_0_5 : std_logic_vector(2 downto 0);
    signal prdata_o_1_0_iv_0_0_a1_0 : 
        std_logic_vector(2 downto 1);
    signal prdata_o_1_0_iv_0_0_a1_sx : std_logic_vector(2 to 2);
    signal prdata_o_1_0_iv_0_0_a1 : std_logic_vector(2 downto 1);
    signal prdata_o_1_iv_0_0_a3_9_sx : std_logic_vector(9 to 9);
    signal prdata_o_1_iv_0_0_a3_8_sx : std_logic_vector(9 to 9);
    signal prdata_o_1_iv_0_0_a3_24_0 : std_logic_vector(9 to 9);
    signal prdata_o_1_0_iv_0_15_sx : std_logic_vector(0 to 0);
    signal prdata_o_1_0_iv_0_2 : std_logic_vector(0 to 0);
    signal prdata_o_1_iv_0_0_a3_17_sx : std_logic_vector(9 to 9);
    signal prdata_o_1_iv_0_0_a3_17_0 : std_logic_vector(9 to 9);
    signal prdata_o_1_iv_0_0_a2_14_0 : 
        std_logic_vector(10 to 10);
    signal prdata_o_1_0_iv_0_0 : std_logic_vector(17 downto 13);
    signal prdata_o_1_0_iv_0_8_1 : std_logic_vector(13 to 13);
    signal prdata_o_1_iv_0_0_a3_19_s_1 : 
        std_logic_vector(9 to 9);
    signal prdata_o_1_0_iv_0_0_a0 : std_logic_vector(2 downto 1);
    signal prdata_o_1_0_iv_0_5_1 : std_logic_vector(17 downto 1);
    signal prdata_o_1_iv_0_0_12_1 : std_logic_vector(10 to 10);
    signal prdata_o_1_0_iv_0_a2_3_0 : std_logic_vector(0 to 0);
    signal prdata_o_1_iv_0_0_0_Z : std_logic_vector(12 to 12);
    signal prdata_o_1_iv_0_0_11_1 : std_logic_vector(12 to 12);
    signal prdata_o_1_iv_0_0_16_1 : std_logic_vector(8 to 8);
    signal prdata_o_1_iv_0_0_6_Z : std_logic_vector(9 downto 8);
    signal prdata_o_1_iv_0_0_7 : std_logic_vector(9 downto 8);
    signal prdata_o_1_0_iv_0_6_1 : std_logic_vector(16 to 16);
    signal prdata_o_1_iv_0_0_5_1 : std_logic_vector(7 to 7);
    signal prdata_o_1_0_iv_0_12_1 : std_logic_vector(4 to 4);
    signal prdata_o_1_0_iv_0_1_0 : std_logic_vector(4 to 4);
    signal prdata_o_1_0_iv_0_15_1_Z : std_logic_vector(4 to 4);
    signal prdata_o_1_iv_0_0_10_1 : std_logic_vector(12 to 12);
    signal prdata_o_1_iv_0_0_5 : std_logic_vector(12 downto 9);
    signal prdata_o_1_iv_0_0_14_1 : std_logic_vector(10 to 10);
    signal prdata_o_1_iv_0_0_9 : std_logic_vector(10 downto 7);
    signal prdata_o_1_iv_0_0_a3_0 : std_logic_vector(9 to 9);
    signal prdata_o_1_0_iv_0_14_1_Z : std_logic_vector(2 to 2);
    signal prdata_o_1_0_iv_0_8 : std_logic_vector(2 downto 0);
    signal prdata_o_1_iv_0_0_a3_25_0 : std_logic_vector(9 to 9);
    signal prdata_o_1_0_iv_0_a2_20_0 : std_logic_vector(3 to 3);
    signal prdata_o_1_0_iv_0_0_a3_1_0 : std_logic_vector(3 to 3);
    signal prdata_o_1_0_iv_0_0_15_tz_1 : 
        std_logic_vector(3 to 3);
    signal prdata_o_1_0_iv_0_0_15_tz_0 : 
        std_logic_vector(3 to 3);
    signal prdata_o_1_iv_0_0_1_tz_1 : std_logic_vector(7 to 7);
    signal prdata_o_1_iv_0_0_1_tz_0 : std_logic_vector(7 to 7);
    signal prdata_o_1_iv_0_0_1_tz : std_logic_vector(7 to 7);
    signal prdata_o_1_iv_0_1 : std_logic_vector(11 downto 5);
    signal prdata_o_1_iv_0_0_1 : std_logic_vector(9 downto 8);
    signal prdata_o_1_0_iv_0_1 : std_logic_vector(2 to 2);
    signal prdata_o_1_0_iv_0_0_0 : std_logic_vector(15 downto 3);
    signal prdata_o_1_iv_0_0_3 : std_logic_vector(12 downto 10);
    signal prdata_o_1_iv_0_0_2 : std_logic_vector(10 downto 7);
    signal prdata_o_1_0_iv_0_0_1 : std_logic_vector(14 to 14);
    signal prdata_o_1_iv_0_8 : std_logic_vector(11 downto 6);
    signal prdata_o_1_iv_0_6 : std_logic_vector(11 downto 6);
    signal prdata_o_1_iv_0_5 : std_logic_vector(11 downto 6);
    signal prdata_o_1_iv_0_0_8 : std_logic_vector(12 downto 8);
    signal prdata_o_1_0_iv_0_7 : std_logic_vector(2 downto 0);
    signal prdata_o_1_0_iv_0_6 : std_logic_vector(2 downto 0);
    signal prdata_o_1_0_iv_0_4 : std_logic_vector(2 downto 1);
    signal prdata_o_1_0_iv_0_9 : std_logic_vector(4 downto 1);
    signal prdata_o_1_0_iv_0_0_8 : std_logic_vector(3 to 3);
    signal prdata_o_1_0_iv_0_0_7 : std_logic_vector(3 to 3);
    signal prdata_o_1_0_iv_0_0_6 : std_logic_vector(3 to 3);
    signal prdata_o_1_0_iv_0_0_3 : std_logic_vector(15 downto 3);
    signal prdata_o_1_0_iv_0_0_2 : std_logic_vector(3 to 3);
    signal prdata_o_1_0_iv_0_0_5 : std_logic_vector(15 to 15);
    signal prdata_o_1_0_iv_0_0_4 : std_logic_vector(15 to 15);
    signal prdata_o_1_iv_0_7 : std_logic_vector(11 downto 6);
    signal \VCC\, idq_pi_ki_o_1_sqmuxa, \GND\, 
        idq_pi_kp_o_1_sqmuxa, olmng_dv_o_1_sqmuxa, 
        olmng_iq_ref_in_o_1_sqmuxa, olmng_theta_factor_o_1_sqmuxa, 
        pwm_dead_time_val_o_1_sqmuxa, 
        pwm_delay_time_val_o_1_sqmuxa, pwm_gain_val_o_1_sqmuxa, 
        pwm_period_val_o_1_sqmuxa, rate_limit_rate_cnt_o_1_sqmuxa, 
        rate_limit_ref_in_o_1_sqmuxa, 
        rate_limit_slew_cnt_o_1_sqmuxa, 
        seq_cntl_cl_omega_o_1_sqmuxa, speed_pi_ki_o_1_sqmuxa, 
        speed_pi_kp_o_0_sqmuxa, auto_restart_no_o_1_sqmuxa, 
        adc_control_reg_val_o_1_sqmuxa, 
        seq_cntl_config_o_1_sqmuxa, hall_filter_factor_o_1_sqmuxa, 
        adc_channel_ch0_o_1_sqmuxa, adc_channel_ch1_o_1_sqmuxa, 
        adc_channel_ch2_o_1_sqmuxa, adc_channel_ch3_o_1_sqmuxa, 
        adc_oc_thresh_o_1_sqmuxa, adc_scale_val_o_1_sqmuxa, 
        hall_speed_factor_o_1_sqmuxa, stop_motor_o_1_sqmuxa, 
        start_motor_o_1_sqmuxa, hall_sensor_polarity_o_1_sqmuxa, 
        fault_clr_o_1_sqmuxa, direction_config_o_1_sqmuxa, 
        prdata_m1_e_9_1, N_711, N_595, N_749, 
        prdata_o276_0_a3_1_sx_x, N_704, N_761, N_742, N_736, 
        N_700, prdata_o276_0_a3_1_x, N_747, 
        adc_channel_ch1_o_1_sqmuxa_0_a3_0_x_Z, N_739, N_724, 
        N_731, N_587, N_589, prdata_o_1_0_iv_0_15_N_3L4_Z, 
        prdata_o_1_0_iv_0_15_N_5L9_Z, N_723, prdata_o276_0_a3_0_0, 
        prdata_o276_0_a3_1_sx, N_699, N_741, 
        prdata_o_1_0_iv_0_5_N_3L4_1_Z, 
        prdata_o_1_0_iv_0_5_N_3L4_Z, N_756, N_706, prdata_m3_e_2, 
        prdata_o_1_iv_0_0_7_N_9L18_1_Z, 
        prdata_o_1_iv_0_0_7_N_9L18_Z, N_740, 
        prdata_o_1_iv_0_0_a3_19_out, N_709, 
        adc_channel_ch1_o_1_sqmuxa_0_a3_0_0_Z, 
        prdata_m3_e_1_3_0_Z, N_566, prdata_o_1_iv_0_0_7_N_4L6_Z, 
        prdata_o_1_iv_0_0_7_N_5L9_Z, prdata_m1_e_16_1, 
        prdata_o_1_iv_0_0_7_N_8L15_Z, N_458, N_483, N_481, N_728, 
        N_382, N_373, prdata_o_1_iv_0_0_15_N_4L6_Z, 
        prdata_o_1_iv_0_0_15_N_5L9_Z, N_378, 
        prdata_o_1_iv_0_0_15_N_7L13_Z, 
        prdata_o_1_iv_0_0_15_N_8L16_Z, N_383, N_381, N_607, 
        prdata_m1_e_10_1, N_735, N_727, 
        prdata_o_1_0_iv_0_5_N_4L6_Z, N_438, N_663, N_662, N_715, 
        prdata_m3_0_a2_0, prdata_m2_0_a2_31_0, prdata_m1_e_19_1_0, 
        N_746, N_753, N_764, 
        hall_sensor_polarity_o_1_sqmuxa_0_a3_0_1_Z, 
        prdata_m2_e_3_0, prdata_m3_e_2_1, N_755, N_718, 
        prdata_m1_e_22_1, prdata_m1_e_5_1, prdata_m1_e_11_1, 
        prdata_m1_e_21_1, prdata_m1_e_17_1, prdata_m2_e_1_2, 
        rate_limit_slew_cnt_o_1_sqmuxa_0_a3_0_1_Z, 
        prdata_N_5_mux_1, prdata_N_5_mux_4, N_703, N_770, N_754, 
        N_526, N_533, N_729, N_733, N_738, N_523, N_530, N_744, 
        N_769, N_725, N_640, N_602, N_601, N_570, N_563, N_546, 
        N_540, N_512, N_507, N_506, N_476, N_475, N_444, N_424, 
        N_404, N_384, N_364, N_366, N_528, N_772, N_771, N_751, 
        N_750, N_648, N_642, N_638, N_615, N_613, N_612, N_611, 
        N_606, N_605, N_604, N_603, N_592, N_588, N_569, N_568, 
        N_567, N_565, N_555, N_554, N_545, N_544, N_543, N_514, 
        N_511, N_510, N_509, N_508, N_490, N_488, N_487, N_486, 
        N_435, N_433, N_432, N_431, N_430, N_425, N_422, N_402, 
        N_392, N_385, N_362, N_982 : std_logic;

begin 

    prdata_o_1_iv_0_0_a3_2_0(9) <= \prdata_o_1_iv_0_0_a3_2_0\(9);
    prdata_o_0_5(17) <= \prdata_o_0_5\(17);
    prdata_o_0_3(17) <= \prdata_o_0_3\(17);
    prdata_o276 <= \prdata_o276\;
    G_15_1 <= \G_15_1\;
    N_730 <= \N_730\;
    N_748 <= \N_748\;
    prdata_o_1_iv_0_0_a3_27_out <= \prdata_o_1_iv_0_0_a3_27_out\;
    prdata_o_1_iv_0_0_a3_9_out <= \prdata_o_1_iv_0_0_a3_9_out\;
    N_737 <= \N_737\;
    N_759 <= \N_759\;
    N_705 <= \N_705\;
    prdata_o_1_iv_0_0_a3_0_out <= \prdata_o_1_iv_0_0_a3_0_out\;
    N_734 <= \N_734\;

    \prdata_o_1_0_iv_3_a2_6[2]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        OLMNG_0_theta_o_2, C => \N_705\, D => 
        \prdata_o_1_iv_0_0_a3_2_0\(9), Y => N_543);
    
    \prdata_o_1_0_iv_0_0_a1_0[2]\ : CFG2
      generic map(INIT => x"4")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        ADC_SCALING_0_ia_adc_o(2), Y => 
        prdata_o_1_0_iv_0_0_a1_0(2));
    
    \idq_pi_ki_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_ki_o(6));
    
    \rate_limit_rate_cnt_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_rate_cnt_o(16));
    
    \prdata_o_1_iv_0_0_a2_15[9]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_706, B => \N_705\, C => 
        FOC_TRANSFORMS_0_ialpha_o(9), D => N_756, Y => N_366);
    
    \adc_channel_ch2_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch2_o(14));
    
    \adc_oc_thresh_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_oc_thresh_o(13));
    
    \rate_limit_slew_cnt_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_slew_cnt_o(8));
    
    prdata_o_1_iv_0_0_7_N_4L6 : CFG4
      generic map(INIT => x"8000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(5), B => N_756, 
        C => adc_interface_0_result_ch0_o(10), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), Y => 
        prdata_o_1_iv_0_0_7_N_4L6_Z);
    
    \prdata_o_1_0_iv_0_16_cZ[0]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => prdata_o_1_0_iv_0_7(0), B => 
        prdata_o_1_0_iv_0_5(0), C => N_588, D => 
        prdata_o_1_0_iv_0_6(0), Y => prdata_o_1_0_iv_0_16(0));
    
    \prdata_o_1_iv_0_0_a2_7[9]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_711, B => ADC_SCALING_0_ib_adc_o(9), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_358);
    
    \hall_speed_factor_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => hall_speed_factor_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_hall_if_0_hall_speed_factor_o(14));
    
    \olmng_theta_factor_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_theta_factor_o(4));
    
    \adc_channel_ch3_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch3_o(15));
    
    \prdata_o_1_iv_0_0_6[8]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => N_729, B => N_733, C => 
        FOC_TRANSFORMS_0_ibeta_o(8), D => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(8), Y => 
        prdata_o_1_iv_0_0_6_Z(8));
    
    \speed_pi_kp_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_kp_o(3));
    
    \idq_pi_kp_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_kp_o(14));
    
    \speed_pi_ki_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_ki_o(3));
    
    prdata_o_1_0_iv_0_5_N_4L6 : CFG4
      generic map(INIT => x"153F")

      port map(A => SPEED_ID_IQ_PI_0_speed_pi_output_o(17), B => 
        RATE_LIMITER_0_rl_out_o(17), C => N_740, D => N_727, Y
         => prdata_o_1_0_iv_0_5_N_4L6_Z);
    
    \olmng_iq_ref_in_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_iq_ref_in_o(11));
    
    \prdata_o_1_0_iv_0_4[16]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => FOC_TRANSFORMS_0_vbeta_o(16), B => 
        FOC_TRANSFORMS_0_ibeta_o(16), C => N_729, D => N_738, Y
         => prdata_o_1_0_iv_0_4_15);
    
    \idq_pi_kp_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_kp_o(12));
    
    \adc_channel_ch0_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch0_o(3));
    
    \prdata_o_1_iv_0_0_a3_8_sx[9]\ : CFG4
      generic map(INIT => x"FFFB")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(7), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(0), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(1), Y => 
        prdata_o_1_iv_0_0_a3_8_sx(9));
    
    \adc_channel_ch0_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch0_o(15));
    
    \prdata_o_1_iv_0_0_a3_27_s[9]\ : CFG4
      generic map(INIT => x"0004")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(9), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(11), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(8), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(6), Y => 
        \prdata_o_1_iv_0_0_a3_27_out\);
    
    \prdata_o_1_iv_0_a2_15[11]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_706, B => \N_705\, C => 
        FOC_TRANSFORMS_0_ialpha_o(11), D => N_756, Y => N_642);
    
    \prdata_o_1_0_iv_0_a2_7[16]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        SPEED_ID_IQ_PI_0_id_pi_output_o_16, C => \N_705\, D => 
        \prdata_o_1_iv_0_0_a3_9_out\, Y => N_604);
    
    \prdata_o_1_0_iv_0_0_9[14]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => N_490, B => N_488, C => N_487, D => N_486, Y
         => prdata_o_1_0_iv_0_0_9_11);
    
    \speed_pi_ki_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_ki_o(6));
    
    \prdata_o_1_0_iv_0_RNO_0[0]\ : CFG3
      generic map(INIT => x"80")

      port map(A => N_761, B => SEQ_CONTROLLER_0_state_o(0), C
         => N_742, Y => prdata_o_1_0_iv_0_3(0));
    
    \prdata_o_1_0_iv_0_8_1[13]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => N_739, B => N_740, C => 
        FOC_TRANSFORMS_0_id_o_13, D => 
        RATE_LIMITER_0_rl_out_o(13), Y => 
        prdata_o_1_0_iv_0_8_1(13));
    
    \prdata_o_1_0_iv_0_0_RNO_0[4]\ : CFG2
      generic map(INIT => x"8")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(11), B => 
        adc_interface_0_result_ch2_o(4), Y => prdata_m3_0_a2_0);
    
    \pwm_period_val_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_period_val_o(10));
    
    \rate_limit_ref_in_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_ref_in_o(7));
    
    \pwm_period_val_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_period_val_o(6));
    
    \idq_pi_kp_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_kp_o(13));
    
    idq_pi_ki_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(4), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), C => N_753, D => N_754, 
        Y => idq_pi_ki_o_1_sqmuxa);
    
    \prdata_o_1_iv_0_0_a2_0[7]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a3_9_out\, B => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(7), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_431);
    
    \prdata_o_1_iv_0_0_3[12]\ : CFG4
      generic map(INIT => x"FFEC")

      port map(A => SPEED_ID_IQ_PI_0_speed_pi_output_o(12), B => 
        N_476, C => N_727, D => N_475, Y => 
        prdata_o_1_iv_0_0_3(12));
    
    \hall_speed_factor_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => hall_speed_factor_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_hall_if_0_hall_speed_factor_o(6));
    
    \rate_limit_rate_cnt_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_rate_cnt_o(17));
    
    \prdata_o_1_0_iv_0_a2_12[14]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a3_0_out\, B => 
        FOC_TRANSFORMS_0_vbeta_o(14), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_488);
    
    \adc_channel_ch2_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch2_o(9));
    
    \prdata_o_1_iv_0_0_a3_16[9]\ : CFG4
      generic map(INIT => x"0100")

      port map(A => prdata_o_1_iv_0_0_a3_16_sx(9), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(10), C => 
        prdata_o_1_iv_0_0_a3_16_sx_0(9), D => 
        prdata_o_1_iv_0_0_a3_16_0(9), Y => \N_748\);
    
    \prdata_o_1_iv_0_0_11_1[12]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => FOC_TRANSFORMS_0_valpha_o_12, B => 
        HALL_INTERFACE_1_omega_out_o(12), C => N_728, D => N_731, 
        Y => prdata_o_1_iv_0_0_11_1(12));
    
    \pwm_delay_time_val_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_delay_time_val_o(1));
    
    \idq_pi_ki_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_ki_o(15));
    
    \speed_pi_kp_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_kp_o(15));
    
    \prdata_o_1_0_iv_0_0_6[3]\ : CFG4
      generic map(INIT => x"FFF8")

      port map(A => adc_interface_0_result_ch1_o_3, B => \N_748\, 
        C => N_530, D => N_523, Y => prdata_o_1_0_iv_0_0_6(3));
    
    \prdata_o_1_0_iv_0_15[4]\ : CFG4
      generic map(INIT => x"FFBF")

      port map(A => prdata_o_1_0_iv_0_3(4), B => 
        prdata_o_1_0_iv_0_12_1(4), C => prdata_o_1_0_iv_0_1_0(4), 
        D => N_663, Y => prdata_o_1_0_iv_0_15_4);
    
    \idq_pi_kp_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_kp_o(9));
    
    prdata_o_1_iv_0_0_15_N_8L16 : CFG4
      generic map(INIT => x"C0EA")

      port map(A => HALL_INTERFACE_1_theta_output_o_1, B => 
        FOC_TRANSFORMS_0_iq_o_8, C => \N_734\, D => \prdata_o276\, 
        Y => prdata_o_1_iv_0_0_15_N_8L16_Z);
    
    \prdata_o_1_0_iv_0_0_a3[3]\ : CFG3
      generic map(INIT => x"40")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(6), B => N_755, 
        C => N_718, Y => N_761);
    
    \idq_pi_kp_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_kp_o(8));
    
    \prdata_o_1_iv_0_0_tz_1_RNO_0[7]\ : CFG2
      generic map(INIT => x"4")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        SPEED_ID_IQ_PI_0_id_pi_output_o_7, Y => 
        prdata_m1_e_19_1_0);
    
    \prdata_o_1_0_iv_0_0_a0_1[2]\ : CFG4
      generic map(INIT => x"0001")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(6), B => 
        prdata_o_1_0_iv_0_0_a0_1_sx(2), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(1), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(0), Y => 
        prdata_o_1_0_iv_0_0_a0_1(2));
    
    \pwm_dead_time_val_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_dead_time_val_o(9));
    
    \prdata_o_1_iv_0_0_RNO[11]\ : CFG4
      generic map(INIT => x"0040")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => N_706, 
        C => ADC_SCALING_0_ia_adc_o(11), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), Y => prdata_m1_e_11_1);
    
    \prdata_o_1_0_iv_0_a2_17[15]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        OLMNG_0_theta_o_15, C => \N_705\, D => 
        \prdata_o_1_iv_0_0_a3_2_0\(9), Y => N_508);
    
    \olmng_iq_ref_in_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_iq_ref_in_o(0));
    
    \prdata_o_1_0_iv_0_7[2]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => SPEED_ID_IQ_PI_0_iq_pi_output_o(2), B => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(2), C => N_733, D => 
        N_727, Y => prdata_o_1_0_iv_0_7(2));
    
    \rate_limit_slew_cnt_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_slew_cnt_o(5));
    
    \hall_speed_factor_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => hall_speed_factor_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_hall_if_0_hall_speed_factor_o(9));
    
    \prdata_o_1_iv_0_0_a3_12[9]\ : CFG4
      generic map(INIT => x"0800")

      port map(A => \prdata_o_1_iv_0_0_a3_27_out\, B => \G_15_1\, 
        C => MC_System_0_AMBA_SLAVE_0_PADDR(2), D => 
        prdata_o_1_iv_0_0_a3_0(9), Y => N_740);
    
    \prdata_o_1_0_iv_0_4[2]\ : CFG4
      generic map(INIT => x"FFF8")

      port map(A => adc_interface_0_result_ch3_o(2), B => N_745, 
        C => N_546, D => N_540, Y => prdata_o_1_0_iv_0_4(2));
    
    \prdata_o_1_0_iv_0_a2_16[15]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_711, B => ADC_SCALING_0_ib_adc_o(15), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_507);
    
    \prdata_o_1_0_iv_0_15_1[4]\ : CFG4
      generic map(INIT => x"153F")

      port map(A => N_715, B => N_706, C => 
        FOC_TRANSFORMS_0_ialpha_o(4), D => 
        adc_interface_0_result_ch0_o(4), Y => 
        prdata_o_1_0_iv_0_15_1_Z(4));
    
    direction_config_o : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => direction_config_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_0_direction_config_o);
    
    \idq_pi_kp_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_kp_o(11));
    
    \prdata_o_1_iv_0_0_a3_2_sx[9]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(7), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(0), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(1), Y => 
        prdata_o_1_iv_0_0_a3_2_sx(9));
    
    \hall_speed_factor_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => hall_speed_factor_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_hall_if_0_hall_speed_factor_o(5));
    
    \adc_channel_ch3_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch3_o(13));
    
    \pwm_delay_time_val_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_delay_time_val_o(13));
    
    \prdata_o_1_iv_0_1[11]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => adc_interface_0_result_ch2_o(11), B => 
        adc_interface_0_result_ch3_o(11), C => N_749, D => N_745, 
        Y => prdata_o_1_iv_0_1(11));
    
    \prdata_o_1_iv_0_0_10_1[12]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => FOC_TRANSFORMS_0_ibeta_o(12), B => 
        FOC_TRANSFORMS_0_vbeta_o(12), C => N_724, D => 
        \prdata_o_1_iv_0_0_a3_0_out\, Y => 
        prdata_o_1_iv_0_0_10_1(12));
    
    \prdata_o_1_0_iv_0_15[0]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => prdata_o_1_0_iv_0_15_sx(0), B => N_587, C => 
        prdata_o_1_0_iv_0_2(0), D => N_589, Y => 
        prdata_o_1_0_iv_0_15_0);
    
    \prdata_o_1_0_iv_0_9[13]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => N_615, B => N_613, C => N_612, D => N_611, Y
         => prdata_o_1_0_iv_0_9_12);
    
    \olmng_dv_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_en_if_1_olmng_dv_o(6));
    
    \speed_pi_ki_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_ki_o(15));
    
    \READ_DECODE_PROC.prdata_o276_0_a3_1_x\ : CFG2
      generic map(INIT => x"1")

      port map(A => prdata_o276_0_a3_1_sx_x, B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(10), Y => 
        prdata_o276_0_a3_1_x);
    
    \prdata_o_1_iv_0_a2_13[11]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => FOC_TRANSFORMS_0_id_o_11, B => \N_759\, C => 
        \prdata_o_1_iv_0_0_a3_27_out\, D => \G_15_1\, Y => N_640);
    
    \prdata_o_1_0_iv_0_a2_12[0]\ : CFG4
      generic map(INIT => x"0080")

      port map(A => \prdata_o_1_iv_0_0_a3_0_out\, B => \N_705\, C
         => FOC_TRANSFORMS_0_valpha_o_0, D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => N_589);
    
    rate_limit_slew_cnt_o_1_sqmuxa_0_a3 : CFG4
      generic map(INIT => x"8000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PSELx, B => 
        rate_limit_slew_cnt_o_1_sqmuxa_0_a3_0_1_Z, C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(6), D => \G_15_1\, Y => 
        N_754);
    
    \prdata_o_1_0_iv_0_0_11_a0_cZ[14]\ : CFG4
      generic map(INIT => x"0080")

      port map(A => N_711, B => \N_705\, C => 
        ADC_SCALING_0_ia_adc_o(14), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => 
        prdata_o_1_0_iv_0_0_11_a0(14));
    
    \adc_control_reg_val_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        adc_control_reg_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_control_reg_val_o(3));
    
    \prdata_o_1[18]\ : SLE
      port map(D => prdata_o_2(31), CLK => \prdata_o276\, EN => 
        \VCC\, ALn => \VCC\, ADn => \VCC\, SLn => \VCC\, SD => 
        \GND\, LAT => \VCC\, Q => 
        MC_System_0_AMBA_SLAVE_0_PRDATA(19));
    
    \adc_channel_ch1_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch1_o(7));
    
    \adc_channel_ch0_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch0_o(13));
    
    \pwm_gain_val_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_gain_val_o(8));
    
    \rate_limit_rate_cnt_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_rate_cnt_o(11));
    
    \pwm_gain_val_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_gain_val_o(17));
    
    \pwm_delay_time_val_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_delay_time_val_o(7));
    
    \seq_cntl_cl_omega_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_seq_cntl_cl_omega_o(0));
    
    \adc_scale_val_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_scale_val_o(5));
    
    \prdata_o_1_iv_0_0_a2_11[8]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        RATE_LIMITER_0_rl_out_o(8), C => \N_705\, D => 
        prdata_o_1_iv_0_0_a3_0(9), Y => N_382);
    
    \prdata_o_1_iv_0_0_a2[7]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => prdata_o_1_iv_0_0_a3_16_0(9), B => 
        adc_interface_0_result_ch1_o_7, C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_430);
    
    \rate_limit_rate_cnt_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_rate_cnt_o(8));
    
    \adc_channel_ch2_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch2_o(5));
    
    \prdata_o_1_iv_0_0_a3_0_0[9]\ : CFG3
      generic map(INIT => x"04")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(3), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), Y => 
        prdata_o_1_iv_0_0_a3_0(9));
    
    \rate_limit_slew_cnt_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_slew_cnt_o(17));
    
    \olmng_theta_factor_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_theta_factor_o(16));
    
    \prdata_o_1_0_iv_0_a2_21[15]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => FOC_TRANSFORMS_0_id_o_15, B => \N_759\, C => 
        \prdata_o_1_iv_0_0_a3_27_out\, D => \G_15_1\, Y => N_512);
    
    \speed_pi_kp_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_kp_o(17));
    
    \prdata_o_1_iv_0_0_14_cZ[8]\ : CFG4
      generic map(INIT => x"FEEE")

      port map(A => prdata_o_1_iv_0_0_8(8), B => N_385, C => 
        adc_interface_0_result_ch0_o(8), D => N_744, Y => 
        prdata_o_1_iv_0_0_14(8));
    
    \pwm_period_val_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_period_val_o(15));
    
    \pwm_delay_time_val_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_delay_time_val_o(8));
    
    \prdata_o_1_iv_0_0_a2_2[7]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a3_0_out\, B => 
        FOC_TRANSFORMS_0_vbeta_o(7), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_433);
    
    \prdata_o_1_0_iv_0_0_a0[2]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_699, B => prdata_o_1_0_iv_0_0_a0_1(2), C
         => N_709, D => adc_channel_ch1_o_1_sqmuxa_0_a3_0_0_Z, Y
         => prdata_o_1_0_iv_0_0_a0(2));
    
    pwm_gain_val_o_1_sqmuxa_0_a2 : CFG2
      generic map(INIT => x"8")

      port map(A => N_754, B => N_741, Y => 
        pwm_gain_val_o_1_sqmuxa);
    
    \prdata_o_1_0_iv_0_6[0]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => FOC_TRANSFORMS_0_vbeta_o(0), B => 
        FOC_TRANSFORMS_0_ibeta_o(0), C => N_729, D => N_738, Y
         => prdata_o_1_0_iv_0_6(0));
    
    \adc_oc_thresh_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_oc_thresh_o(2));
    
    \prdata_o_1_iv_0_0_a3_5_0[9]\ : CFG3
      generic map(INIT => x"08")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(3), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), Y => 
        \prdata_o_1_iv_0_0_a3_9_out\);
    
    \adc_channel_ch3_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch3_o(7));
    
    \adc_channel_ch3_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch3_o(5));
    
    hall_sensor_polarity_o_1_sqmuxa_0_a3_1 : CFG2
      generic map(INIT => x"1")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(5), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), Y => N_706);
    
    \pwm_delay_time_val_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_delay_time_val_o(11));
    
    \prdata_o_1_iv_0_0_2[7]\ : CFG4
      generic map(INIT => x"F888")

      port map(A => prdata_o_1_iv_0_0_1_tz(7), B => \N_705\, C
         => adc_interface_0_result_ch2_o(7), D => N_749, Y => 
        prdata_o_1_iv_0_0_2(7));
    
    \prdata_o_1_0_iv_0_a2_20_0[3]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(10), B => 
        N_700, C => SEQ_CONTROLLER_0_state_o(3), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(7), Y => 
        prdata_o_1_0_iv_0_a2_20_0(3));
    
    \hall_speed_factor_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => hall_speed_factor_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_hall_if_0_hall_speed_factor_o(4));
    
    \seq_cntl_cl_omega_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_seq_cntl_cl_omega_o(10));
    
    \pwm_delay_time_val_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_delay_time_val_o(10));
    
    \prdata_o_1_0_iv_0_11_cZ[16]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => N_606, B => N_605, C => N_604, D => N_603, Y
         => prdata_o_1_0_iv_0_11(16));
    
    \pwm_delay_time_val_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_delay_time_val_o(15));
    
    \speed_pi_ki_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_ki_o(7));
    
    \prdata_o_1_0_iv_0_a2_10[1]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        SPEED_ID_IQ_PI_0_id_pi_output_o_1, C => \N_705\, D => 
        \prdata_o_1_iv_0_0_a3_9_out\, Y => N_567);
    
    \prdata_o_1_0_iv_0_0_a1_sx[2]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(0), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(10), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(7), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(1), Y => 
        prdata_o_1_0_iv_0_0_a1_sx(2));
    
    \prdata_o_1_iv_0_0_12_1[10]\ : CFG3
      generic map(INIT => x"08")

      port map(A => N_711, B => ADC_SCALING_0_ia_adc_o(10), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => 
        prdata_o_1_iv_0_0_12_1(10));
    
    \prdata_o_1_0_iv_0_a2_15[15]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_723, B => HALL_INTERFACE_1_theta_output_o_8, 
        C => N_704, D => prdata_o276_0_a3_0_0, Y => N_506);
    
    \pwm_gain_val_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_gain_val_o(2));
    
    \prdata_o_1_iv_0_0_7[8]\ : CFG4
      generic map(INIT => x"FEFA")

      port map(A => N_384, B => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(8), C => 
        prdata_o_1_iv_0_0_1(8), D => N_727, Y => 
        prdata_o_1_iv_0_0_7(8));
    
    \prdata_o_1_0_iv_0_a2_23[15]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_706, B => \N_705\, C => 
        FOC_TRANSFORMS_0_ialpha_o(15), D => N_756, Y => N_514);
    
    \adc_oc_thresh_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_oc_thresh_o(12));
    
    \rate_limit_ref_in_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_ref_in_o(9));
    
    \prdata_o_1_0_iv_0_7[13]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => OLMNG_0_theta_o_13, B => 
        SPEED_ID_IQ_PI_0_id_pi_output_o_13, C => \N_737\, D => 
        \N_730\, Y => prdata_o_1_0_iv_0_7_13);
    
    \olmng_iq_ref_in_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_iq_ref_in_o(10));
    
    \speed_pi_kp_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_kp_o(10));
    
    \rate_limit_rate_cnt_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_rate_cnt_o(3));
    
    VCC_Z : VCC
      port map(Y => \VCC\);
    
    \prdata_o_1_0_iv_0_8[0]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => HALL_INTERFACE_1_omega_out_o(0), B => 
        HALL_INTERFACE_1_angle_out_raw_o(0), C => N_731, D => 
        N_747, Y => prdata_o_1_0_iv_0_8(0));
    
    \prdata_o_1_iv_0_0_a3_9_sx[9]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(7), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(0), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(1), Y => 
        prdata_o_1_iv_0_0_a3_9_sx(9));
    
    \prdata_o_1_iv_0_0_12[10]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => prdata_o_1_iv_0_0_12_1(10), B => 
        OLMNG_0_theta_o_10, C => \N_705\, D => \N_730\, Y => 
        prdata_o_1_iv_0_0_12_3);
    
    \olmng_iq_ref_in_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_iq_ref_in_o(6));
    
    \prdata_o_1_iv_0_0_a3_24_0_RNI9BKG2[9]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_700, B => N_724, C => 
        prdata_o_1_iv_0_0_a3_24_0(9), D => prdata_o276_0_a3_1_x, 
        Y => N_731);
    
    \prdata_o_1_iv_0_0_a3_1_0[9]\ : CFG3
      generic map(INIT => x"02")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(3), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), Y => N_724);
    
    \prdata_o_1_0_iv_0_7[0]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => SPEED_ID_IQ_PI_0_iq_pi_output_o(0), B => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(0), C => N_733, D => 
        N_727, Y => prdata_o_1_0_iv_0_7(0));
    
    \prdata_o_1_0_iv_0_6[1]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => N_729, B => N_733, C => 
        FOC_TRANSFORMS_0_ibeta_o(1), D => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(1), Y => 
        prdata_o_1_0_iv_0_6(1));
    
    \idq_pi_ki_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_ki_o(14));
    
    \speed_pi_ki_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_ki_o(17));
    
    \pwm_gain_val_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_gain_val_o(15));
    
    \seq_cntl_cl_omega_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_seq_cntl_cl_omega_o(7));
    
    \prdata_o_1_0_iv_0_a2_20[15]\ : CFG4
      generic map(INIT => x"0080")

      port map(A => \prdata_o_1_iv_0_0_a3_0_out\, B => \N_705\, C
         => FOC_TRANSFORMS_0_valpha_o_15, D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => N_511);
    
    \prdata_o_1_iv_0_0_a2_13[7]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => FOC_TRANSFORMS_0_id_o_7, B => \N_759\, C => 
        \prdata_o_1_iv_0_0_a3_27_out\, D => \G_15_1\, Y => N_444);
    
    \prdata_o_1_0_iv_0_0_2[3]\ : CFG4
      generic map(INIT => x"FECC")

      port map(A => prdata_o_1_0_iv_0_0_15_tz_1(3), B => 
        prdata_o_1_0_iv_0_0_0(3), C => 
        prdata_o_1_0_iv_0_0_15_tz_0(3), D => \N_705\, Y => 
        prdata_o_1_0_iv_0_0_2(3));
    
    \idq_pi_ki_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_ki_o(12));
    
    \pwm_dead_time_val_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_dead_time_val_o(5));
    
    olmng_iq_ref_in_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"2000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(5), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), C => N_751, D => N_753, 
        Y => olmng_iq_ref_in_o_1_sqmuxa);
    
    \prdata_o_1_0_iv_0_a2_11[0]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        RATE_LIMITER_0_rl_out_o(0), C => \N_705\, D => 
        prdata_o_1_iv_0_0_a3_0(9), Y => N_588);
    
    idq_pi_kp_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(4), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), C => N_746, D => N_754, 
        Y => idq_pi_kp_o_1_sqmuxa);
    
    \rate_limit_rate_cnt_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_rate_cnt_o(7));
    
    \prdata_o_1_0_iv_0_0_14_cZ[3]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => prdata_o_1_0_iv_0_0_8(3), B => 
        prdata_o_1_0_iv_0_0_7(3), C => prdata_o_1_0_iv_0_0_6(3), 
        D => N_528, Y => prdata_o_1_0_iv_0_0_14(3));
    
    \prdata_o_1_0_iv_0_sx_RNO_0[0]\ : CFG4
      generic map(INIT => x"2000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(11), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(8), C => prdata_m1_e_9_1, 
        D => N_711, Y => N_595);
    
    \prdata_o_1_iv_0_8[11]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => HALL_INTERFACE_1_omega_out_o(11), B => 
        HALL_INTERFACE_1_angle_out_raw_o(11), C => N_731, D => 
        N_747, Y => prdata_o_1_iv_0_8(11));
    
    \olmng_dv_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_en_if_1_olmng_dv_o(2));
    
    \prdata_o_1_0_iv_0_15[1]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => prdata_o_1_0_iv_0_4(1), B => N_569, C => 
        N_567, D => N_565, Y => prdata_o_1_0_iv_0_15_1);
    
    \idq_pi_ki_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_ki_o(13));
    
    \rate_limit_rate_cnt_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_rate_cnt_o(0));
    
    \olmng_dv_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_en_if_1_olmng_dv_o(16));
    
    \prdata_o_1_iv_0_0_1[9]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => adc_interface_0_result_ch2_o(9), B => 
        adc_interface_0_result_ch3_o(9), C => N_749, D => N_745, 
        Y => prdata_o_1_iv_0_0_1(9));
    
    \rate_limit_ref_in_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_ref_in_o(15));
    
    \prdata_o_1_iv_0_0_a2_13[8]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => FOC_TRANSFORMS_0_id_o_8, B => \N_759\, C => 
        \prdata_o_1_iv_0_0_a3_27_out\, D => \G_15_1\, Y => N_384);
    
    \rate_limit_ref_in_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_ref_in_o(5));
    
    \pwm_delay_time_val_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_delay_time_val_o(12));
    
    \prdata_o_1_0_iv_0_a2_11[14]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => prdata_o_1_iv_0_0_a3_0(9), B => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(14), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_487);
    
    \prdata_o_1_0_iv_0_15[2]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => prdata_o_1_0_iv_0_4(2), B => N_545, C => 
        N_555, D => N_543, Y => prdata_o_1_0_iv_0_15_2);
    
    \seq_cntl_cl_omega_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_seq_cntl_cl_omega_o(12));
    
    \rate_limit_rate_cnt_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_rate_cnt_o(13));
    
    \rate_limit_ref_in_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_ref_in_o(4));
    
    auto_restart_no_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"8000")

      port map(A => N_742, B => N_725, C => N_753, D => N_715, Y
         => auto_restart_no_o_1_sqmuxa);
    
    \speed_pi_ki_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_ki_o(10));
    
    \prdata_o_1_iv_0_6[6]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => FOC_TRANSFORMS_0_vbeta_o(6), B => 
        FOC_TRANSFORMS_0_ibeta_o(6), C => N_729, D => N_738, Y
         => prdata_o_1_iv_0_6(6));
    
    \idq_pi_ki_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_ki_o(9));
    
    \adc_scale_val_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_scale_val_o(4));
    
    \adc_channel_ch0_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch0_o(2));
    
    \prdata_o_1_iv_0_0_1_tz_0[7]\ : CFG4
      generic map(INIT => x"EC00")

      port map(A => adc_interface_0_result_ch0_o(7), B => 
        prdata_m2_e_3_0, C => N_715, D => N_756, Y => 
        prdata_o_1_iv_0_0_1_tz_0(7));
    
    \pwm_period_val_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_period_val_o(7));
    
    \olmng_theta_factor_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_theta_factor_o(6));
    
    \hall_speed_factor_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => hall_speed_factor_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_hall_if_0_hall_speed_factor_o(7));
    
    \adc_channel_ch2_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch2_o(0));
    
    \rate_limit_ref_in_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_ref_in_o(8));
    
    \rate_limit_ref_in_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_ref_in_o(13));
    
    \prdata_o_1_0_iv_0_0_15_tz_0[3]\ : CFG4
      generic map(INIT => x"FF80")

      port map(A => FOC_TRANSFORMS_0_ialpha_o(3), B => N_756, C
         => N_706, D => prdata_N_5_mux_1, Y => 
        prdata_o_1_0_iv_0_0_15_tz_0(3));
    
    \idq_pi_ki_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_ki_o(5));
    
    seq_cntl_config_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"8000")

      port map(A => N_742, B => N_725, C => N_764, D => N_709, Y
         => seq_cntl_config_o_1_sqmuxa);
    
    \seq_cntl_cl_omega_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_seq_cntl_cl_omega_o(5));
    
    \pwm_dead_time_val_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_dead_time_val_o(8));
    
    olmng_dv_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(4), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), C => N_746, D => N_751, 
        Y => olmng_dv_o_1_sqmuxa);
    
    \prdata_o_1_0_iv_0_3[16]\ : CFG4
      generic map(INIT => x"FFEC")

      port map(A => SPEED_ID_IQ_PI_0_speed_pi_output_o(16), B => 
        N_602, C => N_727, D => N_601, Y => 
        prdata_o_1_0_iv_0_3_16);
    
    \prdata_o_1_0_iv_0_12_1[4]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => adc_interface_0_result_ch3_o(4), B => 
        RATE_LIMITER_0_rl_out_o(4), C => N_745, D => N_740, Y => 
        prdata_o_1_0_iv_0_12_1(4));
    
    \rate_limit_ref_in_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_ref_in_o(16));
    
    \adc_channel_ch3_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch3_o(4));
    
    prdata_o_1_iv_0_0_7_N_8L15 : CFG3
      generic map(INIT => x"10")

      port map(A => prdata_o_1_iv_0_0_7_N_4L6_Z, B => 
        prdata_m1_e_16_1, C => prdata_o_1_iv_0_0_7_N_5L9_Z, Y => 
        prdata_o_1_iv_0_0_7_N_8L15_Z);
    
    \prdata_o_1_iv_0_6[11]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => N_738, B => N_733, C => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(11), D => 
        FOC_TRANSFORMS_0_vbeta_o(11), Y => prdata_o_1_iv_0_6(11));
    
    \olmng_dv_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_en_if_1_olmng_dv_o(5));
    
    hall_filter_factor_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"8000")

      port map(A => hall_sensor_polarity_o_1_sqmuxa_0_a3_0_1_Z, B
         => N_725, C => MC_System_0_AMBA_SLAVE_0_PADDR(2), D => 
        N_724, Y => hall_filter_factor_o_1_sqmuxa);
    
    \adc_oc_thresh_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_oc_thresh_o(7));
    
    \olmng_iq_ref_in_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_iq_ref_in_o(3));
    
    \rate_limit_slew_cnt_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_slew_cnt_o(7));
    
    \prdata_o_1_0_iv_0_6_1[16]\ : CFG4
      generic map(INIT => x"153F")

      port map(A => FOC_TRANSFORMS_0_iq_o_16, B => 
        FOC_TRANSFORMS_0_ialpha_o(16), C => N_735, D => \N_734\, 
        Y => prdata_o_1_0_iv_0_6_1(16));
    
    \prdata_o_1_iv_0_0_12[12]\ : CFG4
      generic map(INIT => x"FFF8")

      port map(A => RATE_LIMITER_0_rl_out_o(12), B => N_740, C
         => prdata_o_1_iv_0_0_8(12), D => prdata_o_1_iv_0_0_3(12), 
        Y => prdata_o_1_iv_0_0_12_5);
    
    fault_clr_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"8000")

      port map(A => N_742, B => N_725, C => N_715, D => N_756, Y
         => fault_clr_o_1_sqmuxa);
    
    \adc_channel_ch2_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch2_o(12));
    
    \prdata_o_1_iv_0_0[11]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => \N_734\, B => \N_705\, C => 
        FOC_TRANSFORMS_0_iq_o_11, D => prdata_m1_e_11_1, Y => 
        prdata_o_1_iv_0_0_6);
    
    \auto_restart_no_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => auto_restart_no_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_auto_restart_no_o(2));
    
    fault_clr_o : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => fault_clr_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_en_if_1_fault_clr_o);
    
    \prdata_o_1_0_iv_0_0_10[15]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => prdata_o_1_0_iv_0_0_0(15), B => N_514, C => 
        N_512, D => prdata_o_1_0_iv_0_0_5(15), Y => 
        prdata_o_1_0_iv_0_0_10_12);
    
    \prdata_o_1_0_iv_0_a2_14[14]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_724, B => FOC_TRANSFORMS_0_ibeta_o(14), C
         => prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => 
        N_490);
    
    \prdata_o_1_iv_0_0_7[9]\ : CFG4
      generic map(INIT => x"FEFA")

      port map(A => N_364, B => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(9), C => 
        prdata_o_1_iv_0_0_1(9), D => N_727, Y => 
        prdata_o_1_iv_0_0_7(9));
    
    \prdata_o_1_0_iv_3_a2_3[2]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_711, B => ADC_SCALING_0_ib_adc_o(2), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_540);
    
    \prdata_o_1_0_iv_0_0_a1_0[1]\ : CFG2
      generic map(INIT => x"4")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        ADC_SCALING_0_ia_adc_o(1), Y => 
        prdata_o_1_0_iv_0_0_a1_0(1));
    
    \idq_pi_ki_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_ki_o(11));
    
    \pwm_dead_time_val_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_dead_time_val_o(2));
    
    \adc_channel_ch2_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch2_o(11));
    
    \prdata_o_1_iv_0_0_a2_14[6]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_706, B => \N_705\, C => 
        FOC_TRANSFORMS_0_ialpha_o(6), D => N_756, Y => N_425);
    
    \prdata_o_1_0_iv_0_1[2]\ : CFG4
      generic map(INIT => x"FFF8")

      port map(A => N_749, B => adc_interface_0_result_ch2_o(2), 
        C => prdata_o_1_0_iv_0_0_a1(2), D => 
        prdata_o_1_0_iv_0_0_a0(2), Y => prdata_o_1_0_iv_0_1(2));
    
    \adc_channel_ch2_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch2_o(7));
    
    \rate_limit_slew_cnt_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_slew_cnt_o(3));
    
    prdata_o_1_iv_0_0_7_N_8L15_RNO : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => N_709, 
        C => FOC_TRANSFORMS_0_valpha_o_10, D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), Y => prdata_m1_e_16_1);
    
    \adc_channel_ch1_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch1_o(14));
    
    \rate_limit_slew_cnt_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_slew_cnt_o(0));
    
    \adc_channel_ch3_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch3_o(8));
    
    \rate_limit_slew_cnt_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_slew_cnt_o(16));
    
    \prdata_o_1_0_iv_0_0_a2[14]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a3_9_out\, B => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(14), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_486);
    
    \pwm_dead_time_val_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_dead_time_val_o(1));
    
    \seq_cntl_cl_omega_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_seq_cntl_cl_omega_o(11));
    
    \hall_speed_factor_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => hall_speed_factor_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_hall_if_0_hall_speed_factor_o(3));
    
    speed_pi_ki_o_1_sqmuxa_0_a3 : CFG2
      generic map(INIT => x"4")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(5), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), Y => N_709);
    
    \prdata_o_1_0_iv_0_a2_6[16]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        OLMNG_0_theta_o_16, C => \N_705\, D => 
        \prdata_o_1_iv_0_0_a3_2_0\(9), Y => N_603);
    
    \adc_channel_ch3_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch3_o(3));
    
    \adc_scale_val_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_scale_val_o(1));
    
    \prdata_o_1_0_iv_0_a2_5[16]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_723, B => HALL_INTERFACE_1_theta_output_o_9, 
        C => N_704, D => prdata_o276_0_a3_0_0, Y => N_602);
    
    \prdata_o_1_iv_0_0_9[7]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => HALL_INTERFACE_1_omega_out_o(7), B => 
        HALL_INTERFACE_1_angle_out_raw_o(7), C => N_731, D => 
        N_747, Y => prdata_o_1_iv_0_0_9(7));
    
    \prdata_o_1_iv_0_0_a3_2[9]\ : CFG4
      generic map(INIT => x"0100")

      port map(A => prdata_o_1_iv_0_0_a3_2_sx(9), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(10), C => 
        prdata_o_1_iv_0_0_a3_2_sx_0(9), D => 
        \prdata_o_1_iv_0_0_a3_2_0\(9), Y => \N_730\);
    
    \pwm_gain_val_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_gain_val_o(14));
    
    \prdata_o_1_0_iv_0_14[0]\ : CFG4
      generic map(INIT => x"FEEE")

      port map(A => prdata_o_1_0_iv_0_8(0), B => N_592, C => 
        adc_interface_0_result_ch0_o(0), D => N_744, Y => 
        prdata_o_1_0_iv_0_14_0);
    
    \prdata_o_1_0_iv_0_a2_19[15]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        RATE_LIMITER_0_rl_out_o(15), C => \N_705\, D => 
        prdata_o_1_iv_0_0_a3_0(9), Y => N_510);
    
    \prdata_o_1_0_iv_0_14[4]\ : CFG4
      generic map(INIT => x"FEEE")

      port map(A => N_648, B => prdata_o_1_0_iv_0_9(4), C => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(4), D => N_733, Y => 
        prdata_o_1_0_iv_0_14_4);
    
    \prdata_o_1_iv_0_0_8[9]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => HALL_INTERFACE_1_omega_out_o(9), B => 
        HALL_INTERFACE_1_angle_out_raw_o(9), C => N_731, D => 
        N_747, Y => prdata_o_1_iv_0_0_8(9));
    
    \prdata_o_1_iv_0_0_a2_14_0[10]\ : CFG3
      generic map(INIT => x"02")

      port map(A => FOC_TRANSFORMS_0_ialpha_o(10), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), Y => 
        prdata_o_1_iv_0_0_a2_14_0(10));
    
    \prdata_o_1_0_iv_0_a2_1[2]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_718, B => SEQ_CONTROLLER_0_state_o(2), C
         => prdata_o_1_0_iv_0_0_a3_1_0(3), D => N_742, Y => N_554);
    
    \pwm_delay_time_val_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_delay_time_val_o(4));
    
    \adc_control_reg_val_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        adc_control_reg_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_control_reg_val_o(4));
    
    \speed_pi_kp_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_kp_o(6));
    
    \prdata_o_1_iv_0_0_a3[9]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a3_27_out\, B => \G_15_1\, 
        C => MC_System_0_AMBA_SLAVE_0_PADDR(2), D => 
        prdata_o_1_iv_0_0_a3_0(9), Y => N_727);
    
    adc_control_reg_val_o_1_sqmuxa_0_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => \G_15_1\, B => N_725, C => N_741, Y => 
        adc_control_reg_val_o_1_sqmuxa);
    
    \prdata_o_2_iv_0_a3_1[31]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a3_0_out\, B => 
        FOC_TRANSFORMS_0_vbeta_o(17), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_771);
    
    direction_config_o_1_sqmuxa_0_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => \N_759\, B => N_742, C => N_725, Y => 
        direction_config_o_1_sqmuxa);
    
    \prdata_o_1_0_iv_0_sx_RNO_1[0]\ : CFG4
      generic map(INIT => x"0004")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        ADC_SCALING_0_ia_adc_o(0), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(6), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(9), Y => prdata_m1_e_9_1);
    
    \pwm_gain_val_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_gain_val_o(11));
    
    \prdata_o_1_0_iv_0_a2_27[3]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => prdata_o_1_iv_0_0_a3_25_0(9), B => N_703, C
         => adc_interface_0_result_ch2_o(3), D => N_741, Y => 
        N_533);
    
    \prdata_o_1_0_iv_0_3[4]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => FOC_TRANSFORMS_0_iq_o_4, B => 
        ADC_SCALING_0_ib_adc_o(4), C => N_736, D => \N_734\, Y
         => prdata_o_1_0_iv_0_3(4));
    
    \prdata_o_1_0_iv_0_5[1]\ : CFG4
      generic map(INIT => x"FFEF")

      port map(A => prdata_o_1_0_iv_0_0_a0(1), B => 
        prdata_o_1_0_iv_0_0_a1(1), C => prdata_o_1_0_iv_0_5_1(1), 
        D => N_566, Y => prdata_o_1_0_iv_0_5(1));
    
    \rate_limit_ref_in_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_ref_in_o(17));
    
    \prdata_o_1_iv_0_0_a2_7[8]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_711, B => ADC_SCALING_0_ib_adc_o(8), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_378);
    
    \adc_scale_val_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_scale_val_o(13));
    
    \rate_limit_slew_cnt_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_slew_cnt_o(6));
    
    \rate_limit_slew_cnt_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_slew_cnt_o(15));
    
    \hall_filter_factor_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        hall_filter_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_hall_if_0_hall_filter_factor_o(0));
    
    \prdata_o_1_iv_0_0_a2_2[8]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a3_0_out\, B => 
        FOC_TRANSFORMS_0_vbeta_o(8), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_373);
    
    \seq_cntl_cl_omega_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_seq_cntl_cl_omega_o(8));
    
    \adc_oc_thresh_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_oc_thresh_o(4));
    
    pwm_delay_time_val_o_1_sqmuxa_0_a3 : CFG2
      generic map(INIT => x"8")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(5), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), Y => N_715);
    
    \rate_limit_ref_in_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_ref_in_o(1));
    
    \adc_channel_ch2_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch2_o(6));
    
    \adc_channel_ch1_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch1_o(6));
    
    \prdata_o_1_iv_0_0_a2_1[7]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => prdata_o_1_iv_0_0_a3_0(9), B => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(7), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_432);
    
    \adc_channel_ch0_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch0_o(7));
    
    \rate_limit_ref_in_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_ref_in_o(11));
    
    \rate_limit_rate_cnt_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_rate_cnt_o(10));
    
    \speed_pi_ki_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_ki_o(4));
    
    \prdata_o_1_0_iv_0_4[1]\ : CFG4
      generic map(INIT => x"FFF8")

      port map(A => adc_interface_0_result_ch3_o(1), B => N_745, 
        C => N_570, D => N_563, Y => prdata_o_1_0_iv_0_4(1));
    
    \auto_restart_no_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => auto_restart_no_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_auto_restart_no_o(1));
    
    \prdata_o_1_0_iv_0_a2_2[2]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        SPEED_ID_IQ_PI_0_id_pi_output_o_2, C => \N_705\, D => 
        \prdata_o_1_iv_0_0_a3_9_out\, Y => N_555);
    
    prdata_m1_e_6_0 : CFG2
      generic map(INIT => x"1")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), Y => N_746);
    
    \adc_channel_ch2_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch2_o(1));
    
    \adc_scale_val_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_scale_val_o(16));
    
    \idq_pi_kp_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_kp_o(1));
    
    stop_motor_o : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => stop_motor_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => apb3_en_if_1_stop_motor_o);
    
    \rate_limit_ref_in_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_ref_in_o(2));
    
    \prdata_o_1_iv_0_0_16_cZ[9]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => prdata_o_1_iv_0_0_7(9), B => N_362, C => 
        prdata_o_1_iv_0_0_6_Z(9), D => prdata_o_1_iv_0_0_5(9), Y
         => prdata_o_1_iv_0_0_16(9));
    
    \adc_channel_ch0_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch0_o(8));
    
    \hall_filter_factor_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        hall_filter_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_hall_if_0_hall_filter_factor_o(3));
    
    \prdata_o_1_iv_0_0_a3_26[9]\ : CFG4
      generic map(INIT => x"0200")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(11), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(1), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(0), D => 
        adc_channel_ch1_o_1_sqmuxa_0_a3_0_0_Z, Y => N_703);
    
    \adc_channel_ch1_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch1_o(3));
    
    \olmng_iq_ref_in_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_iq_ref_in_o(8));
    
    \seq_cntl_config_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_config_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_seq_cntl_config_o(3));
    
    \prdata_o_1_0_iv_0_0_8[14]\ : CFG4
      generic map(INIT => x"FFF8")

      port map(A => RATE_LIMITER_0_rl_out_o(14), B => N_740, C
         => prdata_o_1_0_iv_0_0_1(14), D => 
        prdata_o_1_0_iv_0_0_0(14), Y => prdata_o_1_0_iv_0_0_8_11);
    
    adc_channel_ch1_o_1_sqmuxa_0_a3_1 : CFG3
      generic map(INIT => x"08")

      port map(A => MC_System_0_AMBA_SLAVE_0_PSELx, B => 
        rate_limit_slew_cnt_o_1_sqmuxa_0_a3_0_1_Z, C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(6), Y => N_725);
    
    \pwm_delay_time_val_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_delay_time_val_o(17));
    
    \adc_oc_thresh_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_oc_thresh_o(1));
    
    \adc_channel_ch2_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch2_o(2));
    
    \seq_cntl_cl_omega_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_seq_cntl_cl_omega_o(16));
    
    \prdata_o_2_iv_0_a3[31]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_711, B => ADC_SCALING_0_ib_adc_o(17), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_769);
    
    \adc_oc_thresh_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_oc_thresh_o(5));
    
    \prdata_o_1_iv_0_0_a3_7[9]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_706, B => N_756, C => \G_15_1\, D => 
        \prdata_o_1_iv_0_0_a3_27_out\, Y => N_735);
    
    \prdata_o_1_0_iv_0_0_a3_1_0[3]\ : CFG4
      generic map(INIT => x"0004")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(6), B => N_715, 
        C => MC_System_0_AMBA_SLAVE_0_PADDR(3), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => 
        prdata_o_1_0_iv_0_0_a3_1_0(3));
    
    hall_speed_factor_o_1_sqmuxa_0_a3 : CFG4
      generic map(INIT => x"0010")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), Y => \N_759\);
    
    \adc_channel_ch1_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch1_o(8));
    
    \adc_channel_ch0_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch0_o(5));
    
    \prdata_o_1_0_iv_0_14[1]\ : CFG2
      generic map(INIT => x"E")

      port map(A => prdata_o_1_0_iv_0_8(1), B => 
        prdata_o_1_0_iv_0_9(1), Y => prdata_o_1_0_iv_0_14_1);
    
    stop_motor_o_1_sqmuxa_0_a3 : CFG2
      generic map(INIT => x"8")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), Y => N_764);
    
    \olmng_theta_factor_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_theta_factor_o(10));
    
    \olmng_theta_factor_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_theta_factor_o(15));
    
    \olmng_dv_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_en_if_1_olmng_dv_o(8));
    
    \idq_pi_ki_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_ki_o(1));
    
    \prdata_o_1_iv_0_0_5[12]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => N_733, B => N_747, C => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(12), D => 
        HALL_INTERFACE_1_angle_out_raw_o(12), Y => 
        prdata_o_1_iv_0_0_5(12));
    
    \prdata_o_1_0_iv_0_0_9[3]\ : CFG4
      generic map(INIT => x"FFF8")

      port map(A => N_747, B => 
        HALL_INTERFACE_1_angle_out_raw_o(3), C => 
        prdata_o_1_0_iv_0_0_2(3), D => prdata_o_1_0_iv_0_0_3(3), 
        Y => prdata_o_1_0_iv_0_0_9_0);
    
    prdata_m3_e_1_3_0 : CFG2
      generic map(INIT => x"2")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), Y => N_753);
    
    stop_motor_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"2000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(5), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), C => N_751, D => N_764, 
        Y => stop_motor_o_1_sqmuxa);
    
    \prdata_o_1_iv_0_14[11]\ : CFG4
      generic map(INIT => x"FEEE")

      port map(A => prdata_o_1_iv_0_8(11), B => N_642, C => 
        adc_interface_0_result_ch0_o(11), D => N_744, Y => 
        prdata_o_1_iv_0_14_5);
    
    \prdata_o_1_iv_0_0_a2_4[7]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_724, B => FOC_TRANSFORMS_0_ibeta_o(7), C
         => prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => 
        N_435);
    
    \pwm_dead_time_val_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_dead_time_val_o(4));
    
    \adc_scale_val_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_scale_val_o(14));
    
    \prdata_o_1_0_iv_0_16_cZ[1]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => prdata_o_1_0_iv_0_7(1), B => 
        prdata_o_1_0_iv_0_6(1), C => prdata_o_1_0_iv_0_5(1), D
         => N_568, Y => prdata_o_1_0_iv_0_16(1));
    
    \prdata_o_1_iv_0_a2_7[11]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_711, B => ADC_SCALING_0_ib_adc_o(11), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_634);
    
    \prdata_o_1_0_iv_0_0_3[15]\ : CFG4
      generic map(INIT => x"FFEC")

      port map(A => N_727, B => N_507, C => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(15), D => N_506, Y => 
        prdata_o_1_0_iv_0_0_3(15));
    
    \adc_control_reg_val_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        adc_control_reg_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_control_reg_val_o(5));
    
    \prdata_o_1_0_iv_0_a2_3_0[0]\ : CFG4
      generic map(INIT => x"0040")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(0), B => 
        adc_channel_ch1_o_1_sqmuxa_0_a3_0_0_Z, C => 
        FOC_TRANSFORMS_0_iq_o_0, D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(1), Y => 
        prdata_o_1_0_iv_0_a2_3_0(0));
    
    \adc_scale_val_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_scale_val_o(0));
    
    \prdata_o_1_iv_0_0_a3_17_0[9]\ : CFG2
      generic map(INIT => x"8")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(6), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(11), Y => 
        prdata_o_1_iv_0_0_a3_17_0(9));
    
    hall_speed_factor_o_1_sqmuxa_0_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => hall_sensor_polarity_o_1_sqmuxa_0_a3_0_1_Z, B
         => N_725, C => \N_759\, Y => 
        hall_speed_factor_o_1_sqmuxa);
    
    prdata_o_1_iv_0_0_7_N_9L18 : CFG3
      generic map(INIT => x"DF")

      port map(A => \G_15_1\, B => prdata_o_1_iv_0_0_7_N_9L18_1_Z, 
        C => \prdata_o_1_iv_0_0_a3_27_out\, Y => 
        prdata_o_1_iv_0_0_7_N_9L18_Z);
    
    \hall_speed_factor_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => hall_speed_factor_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_hall_if_0_hall_speed_factor_o(17));
    
    \pwm_period_val_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_period_val_o(17));
    
    \prdata_o_1_0_iv_0_a2_8[1]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        OLMNG_0_theta_o_1, C => \N_705\, D => 
        \prdata_o_1_iv_0_0_a3_2_0\(9), Y => N_565);
    
    \olmng_iq_ref_in_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_iq_ref_in_o(9));
    
    \hall_filter_factor_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        hall_filter_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_hall_if_0_hall_filter_factor_o(2));
    
    rate_limit_slew_cnt_o_1_sqmuxa_0_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => N_715, B => N_754, C => N_753, Y => 
        rate_limit_slew_cnt_o_1_sqmuxa);
    
    prdata_o_1_iv_0_0_7_N_9L18_1 : CFG4
      generic map(INIT => x"153F")

      port map(A => N_756, B => \N_759\, C => 
        FOC_TRANSFORMS_0_id_o_10, D => 
        prdata_o_1_iv_0_0_a2_14_0(10), Y => 
        prdata_o_1_iv_0_0_7_N_9L18_1_Z);
    
    \speed_pi_ki_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_ki_o(9));
    
    \idq_pi_ki_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_ki_o(3));
    
    olmng_theta_factor_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"8000")

      port map(A => N_742, B => N_725, C => N_709, D => N_756, Y
         => olmng_theta_factor_o_1_sqmuxa);
    
    \adc_oc_thresh_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_oc_thresh_o(0));
    
    \READ_DECODE_PROC.prdata_o276_0_a3_1_sx_x\ : CFG3
      generic map(INIT => x"FD")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(11), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(6), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(7), Y => 
        prdata_o276_0_a3_1_sx_x);
    
    \pwm_dead_time_val_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_dead_time_val_o(0));
    
    \prdata_o_1_0_iv_0_0_a1[2]\ : CFG4
      generic map(INIT => x"0080")

      port map(A => N_711, B => \prdata_o_1_iv_0_0_a3_27_out\, C
         => prdata_o_1_0_iv_0_0_a1_0(2), D => 
        prdata_o_1_0_iv_0_0_a1_sx(2), Y => 
        prdata_o_1_0_iv_0_0_a1(2));
    
    \adc_scale_val_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_scale_val_o(11));
    
    \olmng_iq_ref_in_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_iq_ref_in_o(13));
    
    \prdata_o_1_0_iv_0_a2_9[1]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_718, B => SEQ_CONTROLLER_0_state_o(1), C
         => prdata_o_1_0_iv_0_0_a3_1_0(3), D => N_742, Y => N_566);
    
    \prdata_o_2_iv_0_3[31]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => N_769, B => N_771, C => N_772, D => N_770, Y
         => \prdata_o_0_3\(17));
    
    \idq_pi_kp_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_kp_o(6));
    
    \prdata_o_1_iv_0_0_0_RNO[12]\ : CFG4
      generic map(INIT => x"0040")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => N_706, 
        C => ADC_SCALING_0_ia_adc_o(12), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), Y => prdata_m1_e_22_1);
    
    \olmng_theta_factor_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_theta_factor_o(11));
    
    \pwm_dead_time_val_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_dead_time_val_o(10));
    
    \olmng_theta_factor_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_theta_factor_o(7));
    
    \prdata_o_1_iv_0_0_RNO[5]\ : CFG4
      generic map(INIT => x"0040")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => N_706, 
        C => ADC_SCALING_0_ia_adc_o(5), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), Y => prdata_m1_e_17_1);
    
    \prdata_o_1_0_iv_0_0[13]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => FOC_TRANSFORMS_0_iq_o_13, B => 
        ADC_SCALING_0_ib_adc_o(13), C => N_736, D => \N_734\, Y
         => prdata_o_1_0_iv_0_0(13));
    
    \prdata_o_1_0_iv_0_6[13]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => FOC_TRANSFORMS_0_ialpha_o(13), B => 
        FOC_TRANSFORMS_0_valpha_o_13, C => N_728, D => N_735, Y
         => prdata_o_1_0_iv_0_6_13);
    
    \idq_pi_kp_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_kp_o(7));
    
    \pwm_dead_time_val_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_dead_time_val_o(13));
    
    adc_channel_ch1_o_1_sqmuxa_0_a3 : CFG4
      generic map(INIT => x"0800")

      port map(A => MC_System_0_AMBA_SLAVE_0_PSELx, B => 
        rate_limit_slew_cnt_o_1_sqmuxa_0_a3_0_1_Z, C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(6), D => \G_15_1\, Y => 
        N_750);
    
    \adc_channel_ch1_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch1_o(4));
    
    \prdata_o_1_iv_0_6[5]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => FOC_TRANSFORMS_0_vbeta_o(5), B => 
        FOC_TRANSFORMS_0_ibeta_o(5), C => N_729, D => N_738, Y
         => prdata_o_1_iv_0_6_0);
    
    rate_limit_ref_in_o_1_sqmuxa_0_a3 : CFG4
      generic map(INIT => x"0040")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), Y => N_755);
    
    \prdata_o_1_iv_0_0_11[10]\ : CFG4
      generic map(INIT => x"FFF8")

      port map(A => HALL_INTERFACE_1_omega_out_o(10), B => N_731, 
        C => prdata_o_1_iv_0_0_2(10), D => 
        prdata_o_1_iv_0_0_3(10), Y => prdata_o_1_iv_0_0_11_0);
    
    \olmng_dv_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_en_if_1_olmng_dv_o(4));
    
    auto_restart_no_o_1_sqmuxa_0_a3_1 : CFG4
      generic map(INIT => x"0010")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(0), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(10), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(7), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(1), Y => N_742);
    
    \adc_channel_ch1_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch1_o(5));
    
    \seq_cntl_cl_omega_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_seq_cntl_cl_omega_o(2));
    
    \prdata_o_1_0_iv_0_a2_1[4]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => prdata_o_1_iv_0_0_a3_0(9), B => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(4), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_648);
    
    rate_limit_rate_cnt_o_1_sqmuxa_0_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => N_754, B => N_715, C => N_756, Y => 
        rate_limit_rate_cnt_o_1_sqmuxa);
    
    \prdata_o_1_0_iv_0_0_4[15]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => FOC_TRANSFORMS_0_vbeta_o(15), B => 
        FOC_TRANSFORMS_0_ibeta_o(15), C => N_729, D => N_738, Y
         => prdata_o_1_0_iv_0_0_4(15));
    
    \prdata_o_1_0_iv_0_0_10[3]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => N_744, B => N_731, C => 
        adc_interface_0_result_ch0_o(3), D => 
        HALL_INTERFACE_1_omega_out_o(3), Y => 
        prdata_o_1_0_iv_0_0_10_0);
    
    \prdata_o_1_0_iv_0_0_15_tz_1[3]\ : CFG4
      generic map(INIT => x"CCEC")

      port map(A => \prdata_o_1_iv_0_0_a3_9_out\, B => 
        prdata_N_5_mux_4, C => SPEED_ID_IQ_PI_0_id_pi_output_o_3, 
        D => MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => 
        prdata_o_1_0_iv_0_0_15_tz_1(3));
    
    \adc_oc_thresh_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_oc_thresh_o(15));
    
    \idq_pi_ki_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_ki_o(7));
    
    \seq_cntl_config_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_config_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_seq_cntl_config_o(1));
    
    \pwm_gain_val_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_gain_val_o(16));
    
    \olmng_iq_ref_in_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_iq_ref_in_o(16));
    
    \pwm_delay_time_val_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_delay_time_val_o(6));
    
    \hall_speed_factor_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => hall_speed_factor_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_hall_if_0_hall_speed_factor_o(13));
    
    \prdata_o_1_iv_0_0_a2_4[12]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_711, B => ADC_SCALING_0_ib_adc_o(12), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_475);
    
    \prdata_o_1_iv_0_0_a2_1[5]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => prdata_o_1_iv_0_0_a3_0(9), B => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(5), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_392);
    
    \prdata_o_1_0_iv_0_0_0[15]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => \N_734\, B => \N_705\, C => 
        FOC_TRANSFORMS_0_iq_o_15, D => prdata_m1_e_21_1, Y => 
        prdata_o_1_0_iv_0_0_0(15));
    
    \olmng_iq_ref_in_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_iq_ref_in_o(5));
    
    \prdata_o_1_iv_0_0_a3_19_s[9]\ : CFG4
      generic map(INIT => x"0001")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(9), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(6), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(8), D => 
        prdata_o_1_iv_0_0_a3_19_s_1(9), Y => 
        prdata_o_1_iv_0_0_a3_19_out);
    
    \prdata_o_1_iv_0_0_a3_17[9]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => prdata_o_1_iv_0_0_a3_17_sx(9), B => N_699, C
         => prdata_o_1_iv_0_0_a3_17_0(9), D => N_741, Y => N_749);
    
    \prdata_o_1_iv_0_0_a2_12[12]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_706, B => \N_705\, C => 
        FOC_TRANSFORMS_0_ialpha_o(12), D => N_756, Y => N_483);
    
    \speed_pi_kp_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_kp_o(9));
    
    \speed_pi_ki_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_ki_o(0));
    
    \idq_pi_kp_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_kp_o(16));
    
    \prdata_o_1_iv_0_0_a3_0_s[9]\ : CFG3
      generic map(INIT => x"20")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(3), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), Y => 
        \prdata_o_1_iv_0_0_a3_0_out\);
    
    \olmng_dv_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_en_if_1_olmng_dv_o(9));
    
    \speed_pi_kp_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_kp_o(8));
    
    \seq_cntl_cl_omega_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_seq_cntl_cl_omega_o(3));
    
    \prdata_o_1_iv_0_0_a3_2_0_cZ[9]\ : CFG3
      generic map(INIT => x"40")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(3), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), Y => 
        \prdata_o_1_iv_0_0_a3_2_0\(9));
    
    \prdata_o_1_0_iv_0_0_7[14]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => OLMNG_0_theta_o_14, B => 
        SPEED_ID_IQ_PI_0_id_pi_output_o_14, C => \N_737\, D => 
        \N_730\, Y => prdata_o_1_0_iv_0_0_7_11);
    
    \olmng_iq_ref_in_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_iq_ref_in_o(17));
    
    \idq_pi_kp_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_kp_o(17));
    
    \prdata_o_1_iv_0_8[5]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => HALL_INTERFACE_1_omega_out_o(5), B => 
        HALL_INTERFACE_1_angle_out_raw_o(5), C => N_731, D => 
        N_747, Y => prdata_o_1_iv_0_8_0);
    
    prdata_o_1_0_iv_0_5_N_3L4_1_RNO : CFG4
      generic map(INIT => x"A0C0")

      port map(A => OLMNG_0_theta_o_17, B => 
        FOC_TRANSFORMS_0_id_o_17, C => prdata_m3_e_2_1, D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), Y => prdata_m3_e_2);
    
    \speed_pi_ki_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_ki_o(1));
    
    \adc_channel_ch3_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch3_o(14));
    
    \rate_limit_rate_cnt_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_rate_cnt_o(4));
    
    \pwm_period_val_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_period_val_o(1));
    
    \pwm_dead_time_val_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_dead_time_val_o(6));
    
    \prdata_o_1_0_iv_0_a2_10[0]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        SPEED_ID_IQ_PI_0_id_pi_output_o_0, C => \N_705\, D => 
        \prdata_o_1_iv_0_0_a3_9_out\, Y => N_587);
    
    \prdata_o_1_0_iv_0_5[17]\ : CFG4
      generic map(INIT => x"F2FF")

      port map(A => \N_705\, B => prdata_o_1_0_iv_0_5_N_3L4_Z, C
         => prdata_o_1_0_iv_0_5_1(17), D => 
        prdata_o_1_0_iv_0_5_N_4L6_Z, Y => \prdata_o_0_5\(17));
    
    \prdata_o_1_0_iv_0_6[2]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => FOC_TRANSFORMS_0_vbeta_o(2), B => 
        FOC_TRANSFORMS_0_ibeta_o(2), C => N_729, D => N_738, Y
         => prdata_o_1_0_iv_0_6(2));
    
    prdata_o_1_0_iv_0_5_N_3L4 : CFG4
      generic map(INIT => x"CC4C")

      port map(A => \prdata_o_1_iv_0_0_a3_0_out\, B => 
        prdata_o_1_0_iv_0_5_N_3L4_1_Z, C => 
        FOC_TRANSFORMS_0_valpha_o_17, D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => 
        prdata_o_1_0_iv_0_5_N_3L4_Z);
    
    \seq_cntl_cl_omega_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_seq_cntl_cl_omega_o(15));
    
    \prdata_o_1_iv_0_0_a3_8[9]\ : CFG4
      generic map(INIT => x"1000")

      port map(A => prdata_o_1_iv_0_0_a3_8_sx(9), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(10), C => 
        \prdata_o_1_iv_0_0_a3_27_out\, D => N_711, Y => N_736);
    
    \adc_channel_ch1_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch1_o(12));
    
    \seq_cntl_cl_omega_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_seq_cntl_cl_omega_o(13));
    
    \prdata_o_1_iv_0_0_a2_7[7]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_711, B => ADC_SCALING_0_ib_adc_o(7), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_438);
    
    \adc_channel_ch0_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch0_o(14));
    
    \adc_channel_ch2_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch2_o(10));
    
    \prdata_o_1_iv_0_0_a3_5_0_RNITLTP[9]\ : CFG3
      generic map(INIT => x"08")

      port map(A => \prdata_o_1_iv_0_0_a3_9_out\, B => 
        SPEED_ID_IQ_PI_0_id_pi_output_o_4, C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => prdata_N_5_mux_6);
    
    \pwm_gain_val_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_gain_val_o(1));
    
    \READ_DECODE_PROC.prdata_o276_0_a3_1_sx_RNIVOVP\ : CFG4
      generic map(INIT => x"FF7F")

      port map(A => N_700, B => N_723, C => prdata_o276_0_a3_0_0, 
        D => prdata_o276_0_a3_1_sx, Y => \prdata_o276\);
    
    \adc_channel_ch1_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch1_o(11));
    
    \prdata_o_1_iv_0_0_11[12]\ : CFG4
      generic map(INIT => x"FEFF")

      port map(A => prdata_o_1_iv_0_0_0_Z(12), B => N_483, C => 
        N_481, D => prdata_o_1_iv_0_0_11_1(12), Y => 
        prdata_o_1_iv_0_0_11_2);
    
    \prdata_o_1_0_iv_0_0_a1[1]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_711, B => prdata_o_1_0_iv_0_0_a1_0(1), C
         => \G_15_1\, D => \prdata_o_1_iv_0_0_a3_27_out\, Y => 
        prdata_o_1_0_iv_0_0_a1(1));
    
    \idq_pi_kp_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_kp_o(5));
    
    \prdata_o_1_0_iv_0_5[16]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => N_733, B => N_731, C => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(16), D => 
        HALL_INTERFACE_1_omega_out_o(16), Y => 
        prdata_o_1_0_iv_0_5_16);
    
    \prdata_o_1_iv_0_0_a3_29_RNIB80T2[9]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_699, B => \G_15_1\, C => N_709, D => 
        prdata_m3_e_1_3_0_Z, Y => \N_734\);
    
    \pwm_gain_val_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_gain_val_o(7));
    
    \adc_channel_ch0_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch0_o(1));
    
    \olmng_iq_ref_in_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_iq_ref_in_o(15));
    
    adc_channel_ch0_o_1_sqmuxa_0_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => N_725, B => N_723, C => \G_15_1\, Y => 
        adc_channel_ch0_o_1_sqmuxa);
    
    \speed_pi_ki_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_ki_o(2));
    
    \prdata_o_1_0_iv_0_0_15_tz_1_RNO[3]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => N_709, 
        C => FOC_TRANSFORMS_0_valpha_o_3, D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), Y => prdata_N_5_mux_4);
    
    \rate_limit_rate_cnt_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_rate_cnt_o(14));
    
    \prdata_o_1_0_iv_0_5_1[17]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => N_729, B => N_733, C => 
        FOC_TRANSFORMS_0_ibeta_o(17), D => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(17), Y => 
        prdata_o_1_0_iv_0_5_1(17));
    
    \prdata_o_1_iv_0_0_a3_19_s_1[9]\ : CFG2
      generic map(INIT => x"7")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(11), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => 
        prdata_o_1_iv_0_0_a3_19_s_1(9));
    
    hall_sensor_polarity_o_1_sqmuxa_0_a3_1_RNIBP161 : CFG4
      generic map(INIT => x"0040")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => N_706, 
        C => ADC_SCALING_0_ia_adc_o(6), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), Y => prdata_m1_e_12_1);
    
    prdata_o_1_iv_0_0_15_N_7L13 : CFG3
      generic map(INIT => x"07")

      port map(A => \N_705\, B => prdata_o_1_iv_0_0_15_N_5L9_Z, C
         => N_378, Y => prdata_o_1_iv_0_0_15_N_7L13_Z);
    
    \adc_channel_ch2_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch2_o(8));
    
    \prdata_o_1_0_iv_0_9[1]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => N_735, B => N_744, C => 
        FOC_TRANSFORMS_0_ialpha_o(1), D => 
        adc_interface_0_result_ch0_o(1), Y => 
        prdata_o_1_0_iv_0_9(1));
    
    \adc_scale_val_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_scale_val_o(17));
    
    \speed_pi_kp_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_kp_o(7));
    
    prdata_o_1_0_iv_0_5_N_3L4_1 : CFG4
      generic map(INIT => x"007F")

      port map(A => FOC_TRANSFORMS_0_ialpha_o(17), B => N_756, C
         => N_706, D => prdata_m3_e_2, Y => 
        prdata_o_1_0_iv_0_5_N_3L4_1_Z);
    
    hall_speed_factor_o_1_sqmuxa_0_a3_RNIFDJ12 : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(10), B => 
        adc_channel_ch1_o_1_sqmuxa_0_a3_0_x_Z, C => \N_759\, D
         => \prdata_o_1_iv_0_0_a3_27_out\, Y => N_739);
    
    \pwm_gain_val_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_gain_val_o(9));
    
    \prdata_o_1_iv_0_0_a2_11[7]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        RATE_LIMITER_0_rl_out_o(7), C => \N_705\, D => 
        prdata_o_1_iv_0_0_a3_0(9), Y => N_442);
    
    \olmng_theta_factor_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_theta_factor_o(0));
    
    \prdata_o_1_0_iv_0_1_0_RNO[4]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_741, B => prdata_m3_0_a2_0, C => \G_15_1\, 
        D => prdata_o_1_iv_0_0_a3_25_0(9), Y => N_662);
    
    \idq_pi_kp_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_kp_o(3));
    
    adc_channel_ch0_o_1_sqmuxa_0_a3 : CFG4
      generic map(INIT => x"0002")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), Y => N_723);
    
    \pwm_gain_val_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_gain_val_o(3));
    
    \prdata_o_1_iv_0_0_a3_1[9]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a3_27_out\, B => \G_15_1\, 
        C => MC_System_0_AMBA_SLAVE_0_PADDR(2), D => N_724, Y => 
        N_729);
    
    \pwm_dead_time_val_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_dead_time_val_o(15));
    
    \adc_control_reg_val_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        adc_control_reg_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_control_reg_val_o(1));
    
    \adc_oc_thresh_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_oc_thresh_o(9));
    
    \prdata_o_1_0_iv_0_0_0[14]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => FOC_TRANSFORMS_0_iq_o_14, B => 
        ADC_SCALING_0_ib_adc_o(14), C => N_736, D => \N_734\, Y
         => prdata_o_1_0_iv_0_0_0(14));
    
    \adc_control_reg_val_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        adc_control_reg_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_control_reg_val_o(2));
    
    \rate_limit_slew_cnt_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_slew_cnt_o(13));
    
    \prdata_o_1_iv_0_0_14_cZ[9]\ : CFG4
      generic map(INIT => x"FEEE")

      port map(A => prdata_o_1_iv_0_0_8(9), B => N_366, C => 
        adc_interface_0_result_ch0_o(9), D => N_744, Y => 
        prdata_o_1_iv_0_0_14(9));
    
    \adc_scale_val_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_scale_val_o(7));
    
    \rate_limit_rate_cnt_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_rate_cnt_o(5));
    
    \adc_channel_ch2_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch2_o(15));
    
    \rate_limit_rate_cnt_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_rate_cnt_o(6));
    
    \prdata_o_1_0_iv_0_0[17]\ : CFG4
      generic map(INIT => x"C0EA")

      port map(A => HALL_INTERFACE_1_theta_output_o_10, B => 
        FOC_TRANSFORMS_0_iq_o_17, C => \N_734\, D => 
        \prdata_o276\, Y => prdata_o_1_0_iv_0_0(17));
    
    \prdata_o_1_0_iv_0_a2_24[3]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => FOC_TRANSFORMS_0_id_o_3, B => \N_759\, C => 
        \prdata_o_1_iv_0_0_a3_27_out\, D => \G_15_1\, Y => N_530);
    
    \READ_DECODE_PROC.prdata_o276_0_a3_0_0\ : CFG2
      generic map(INIT => x"8")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(8), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(9), Y => 
        prdata_o276_0_a3_0_0);
    
    \idq_pi_kp_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_kp_o(10));
    
    \pwm_period_val_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_period_val_o(16));
    
    \prdata_o_1_iv_0_0_a2_10[8]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        SPEED_ID_IQ_PI_0_id_pi_output_o_8, C => \N_705\, D => 
        \prdata_o_1_iv_0_0_a3_9_out\, Y => N_381);
    
    \prdata_o_1_iv_0_0_a2_14[8]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_706, B => \N_705\, C => 
        FOC_TRANSFORMS_0_ialpha_o(8), D => N_756, Y => N_385);
    
    \olmng_dv_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_en_if_1_olmng_dv_o(12));
    
    \prdata_o_1_iv_0_0_13_cZ[7]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => N_444, B => N_431, C => 
        prdata_o_1_iv_0_0_9(7), D => prdata_o_1_iv_0_0_2(7), Y
         => prdata_o_1_iv_0_0_13(7));
    
    \olmng_theta_factor_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_theta_factor_o(8));
    
    \pwm_delay_time_val_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_delay_time_val_o(0));
    
    \pwm_gain_val_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_gain_val_o(4));
    
    \olmng_theta_factor_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_theta_factor_o(12));
    
    \pwm_dead_time_val_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_dead_time_val_o(7));
    
    \prdata_o_1_iv_0_0_a2_13[6]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => FOC_TRANSFORMS_0_id_o_6, B => \N_759\, C => 
        \prdata_o_1_iv_0_0_a3_27_out\, D => \G_15_1\, Y => N_424);
    
    \prdata_o_1_0_iv_0_0_5[15]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => N_733, B => N_731, C => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(15), D => 
        HALL_INTERFACE_1_omega_out_o(15), Y => 
        prdata_o_1_0_iv_0_0_5(15));
    
    \prdata_o_1_iv_0_7[5]\ : CFG4
      generic map(INIT => x"FEFA")

      port map(A => N_404, B => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(5), C => 
        prdata_o_1_iv_0_1(5), D => N_733, Y => 
        prdata_o_1_iv_0_7_0);
    
    \olmng_iq_ref_in_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_iq_ref_in_o(1));
    
    \prdata_o_1_iv_0_0_7[10]\ : CFG4
      generic map(INIT => x"F7F3")

      port map(A => prdata_o_1_iv_0_0_7_N_8L15_Z, B => 
        prdata_o_1_iv_0_0_7_N_9L18_Z, C => N_458, D => \N_705\, Y
         => prdata_o_1_iv_0_0_7_2);
    
    adc_channel_ch3_o_1_sqmuxa_0_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => \G_15_1\, B => N_725, C => \N_759\, Y => 
        adc_channel_ch3_o_1_sqmuxa);
    
    \prdata_o_1_0_iv_0_0_11_cZ[15]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => N_511, B => N_510, C => N_509, D => N_508, Y
         => prdata_o_1_0_iv_0_0_11(15));
    
    \prdata_o_1_0_iv_0_6[16]\ : CFG4
      generic map(INIT => x"EFAF")

      port map(A => N_607, B => prdata_m1_e_10_1, C => 
        prdata_o_1_0_iv_0_6_1(16), D => \N_705\, Y => 
        prdata_o_1_0_iv_0_6_16);
    
    \adc_channel_ch3_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch3_o(0));
    
    \seq_cntl_cl_omega_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_seq_cntl_cl_omega_o(17));
    
    \pwm_delay_time_val_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_delay_time_val_o(2));
    
    \prdata_o_1_0_iv_3_a2_7[2]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        RATE_LIMITER_0_rl_out_o(2), C => \N_705\, D => 
        prdata_o_1_iv_0_0_a3_0(9), Y => N_544);
    
    adc_channel_ch1_o_1_sqmuxa_0_a3_0 : CFG4
      generic map(INIT => x"0001")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(0), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(10), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(7), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(1), Y => \G_15_1\);
    
    \pwm_dead_time_val_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_dead_time_val_o(14));
    
    \prdata_o_1_0_iv_0_11_a2_cZ[13]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_724, B => HALL_INTERFACE_1_omega_out_o(13), 
        C => N_704, D => prdata_o_1_iv_0_0_a3_24_0(9), Y => 
        prdata_o_1_0_iv_0_11_a2(13));
    
    \prdata_o_1_0_iv_0_8[13]\ : CFG4
      generic map(INIT => x"F4FF")

      port map(A => \prdata_o276\, B => 
        HALL_INTERFACE_1_theta_output_o_6, C => 
        prdata_o_1_0_iv_0_0(13), D => prdata_o_1_0_iv_0_8_1(13), 
        Y => prdata_o_1_0_iv_0_8_13);
    
    start_motor_o : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => start_motor_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_start_motor_o);
    
    \prdata_o_1_0_iv_0_0_1[14]\ : CFG4
      generic map(INIT => x"C0EA")

      port map(A => HALL_INTERFACE_1_theta_output_o_7, B => 
        FOC_TRANSFORMS_0_id_o_14, C => N_739, D => \prdata_o276\, 
        Y => prdata_o_1_0_iv_0_0_1(14));
    
    rate_limit_slew_cnt_o_1_sqmuxa_0_a3_0_1 : CFG4
      generic map(INIT => x"2000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PWRITE, B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(11), C => N_699, D => 
        MC_System_0_AMBA_SLAVE_0_PENABLE, Y => 
        rate_limit_slew_cnt_o_1_sqmuxa_0_a3_0_1_Z);
    
    \olmng_theta_factor_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_theta_factor_o(14));
    
    \prdata_o_1_iv_0_8[6]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => HALL_INTERFACE_1_omega_out_o(6), B => 
        HALL_INTERFACE_1_angle_out_raw_o(6), C => N_731, D => 
        N_747, Y => prdata_o_1_iv_0_8(6));
    
    \rate_limit_rate_cnt_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_rate_cnt_o(2));
    
    prdata_m3_e_1_3_0_0 : CFG4
      generic map(INIT => x"0040")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(3), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(11), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(6), Y => 
        prdata_m3_e_1_3_0_Z);
    
    \olmng_theta_factor_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_theta_factor_o(1));
    
    \prdata_o_1_iv_0_0_a3_21_s[9]\ : CFG2
      generic map(INIT => x"4")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), Y => N_756);
    
    \speed_pi_kp_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_kp_o(14));
    
    \prdata_o_1_iv_0_0_a2_11[5]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        RATE_LIMITER_0_rl_out_o(5), C => \N_705\, D => 
        prdata_o_1_iv_0_0_a3_0(9), Y => N_402);
    
    \prdata_o_1_iv_0_0_a2_11[6]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        RATE_LIMITER_0_rl_out_o(6), C => \N_705\, D => 
        prdata_o_1_iv_0_0_a3_0(9), Y => N_422);
    
    \idq_pi_ki_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_ki_o(4));
    
    \idq_pi_ki_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_ki_o(16));
    
    \prdata_o_1_0_iv_0_6_RNO[16]\ : CFG4
      generic map(INIT => x"0040")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => N_706, 
        C => ADC_SCALING_0_ia_adc_o(16), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), Y => prdata_m1_e_10_1);
    
    \prdata_o_1_0_iv_0_1_0[4]\ : CFG4
      generic map(INIT => x"0D0F")

      port map(A => N_756, B => prdata_o_1_0_iv_0_15_1_Z(4), C
         => N_662, D => \N_705\, Y => prdata_o_1_0_iv_0_1_0(4));
    
    \olmng_iq_ref_in_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_iq_ref_in_o(2));
    
    \prdata_o_1_iv_0_1[5]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => adc_interface_0_result_ch2_o(5), B => 
        adc_interface_0_result_ch3_o(5), C => N_749, D => N_745, 
        Y => prdata_o_1_iv_0_1(5));
    
    \prdata_o_1_iv_0_0_1_tz[7]\ : CFG2
      generic map(INIT => x"E")

      port map(A => prdata_o_1_iv_0_0_1_tz_1(7), B => 
        prdata_o_1_iv_0_0_1_tz_0(7), Y => 
        prdata_o_1_iv_0_0_1_tz(7));
    
    \prdata_o_1_iv_0_0_12[7]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => N_435, B => N_433, C => N_432, D => N_430, Y
         => prdata_o_1_iv_0_0_12_0);
    
    \idq_pi_ki_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_ki_o(17));
    
    \pwm_period_val_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_period_val_o(4));
    
    \prdata_o_1_0_iv_0_15_sx_RNO[0]\ : CFG4
      generic map(INIT => x"153F")

      port map(A => adc_interface_0_result_ch2_o(0), B => 
        \G_15_1\, C => N_595, D => N_749, Y => 
        prdata_o_1_0_iv_0_15_sx_RNO(0));
    
    prdata_o_1_0_iv_0_15_N_3L4 : CFG3
      generic map(INIT => x"F7")

      port map(A => \prdata_o_1_iv_0_0_a3_2_0\(9), B => 
        OLMNG_0_theta_o_0, C => MC_System_0_AMBA_SLAVE_0_PADDR(2), 
        Y => prdata_o_1_0_iv_0_15_N_3L4_Z);
    
    \olmng_dv_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_en_if_1_olmng_dv_o(15));
    
    \pwm_gain_val_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_gain_val_o(12));
    
    \rate_limit_rate_cnt_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_rate_cnt_o(1));
    
    hall_sensor_polarity_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"0800")

      port map(A => hall_sensor_polarity_o_1_sqmuxa_0_a3_0_1_Z, B
         => N_725, C => MC_System_0_AMBA_SLAVE_0_PADDR(2), D => 
        N_724, Y => hall_sensor_polarity_o_1_sqmuxa);
    
    \adc_scale_val_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_scale_val_o(6));
    
    \adc_scale_val_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_scale_val_o(9));
    
    \adc_channel_ch2_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch2_o(13));
    
    \rate_limit_slew_cnt_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_slew_cnt_o(12));
    
    \prdata_o_1_iv_0_0_a2_12[8]\ : CFG4
      generic map(INIT => x"0080")

      port map(A => \prdata_o_1_iv_0_0_a3_0_out\, B => \N_705\, C
         => FOC_TRANSFORMS_0_valpha_o_8, D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => N_383);
    
    \prdata_o_1_iv_0_0_3[10]\ : CFG4
      generic map(INIT => x"C0EA")

      port map(A => HALL_INTERFACE_1_theta_output_o_3, B => 
        FOC_TRANSFORMS_0_iq_o_10, C => \N_734\, D => 
        \prdata_o276\, Y => prdata_o_1_iv_0_0_3(10));
    
    \prdata_o_1_0_iv_0_a2_17[3]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_711, B => ADC_SCALING_0_ib_adc_o(3), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_523);
    
    \hall_speed_factor_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => hall_speed_factor_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_hall_if_0_hall_speed_factor_o(2));
    
    \prdata_o_1_iv_0_0_2[10]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => adc_interface_0_result_ch2_o(10), B => 
        adc_interface_0_result_ch3_o(10), C => N_749, D => N_745, 
        Y => prdata_o_1_iv_0_0_2(10));
    
    \rate_limit_ref_in_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_ref_in_o(12));
    
    \adc_channel_ch3_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch3_o(1));
    
    \prdata_o_1_0_iv_0_0_6[14]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => FOC_TRANSFORMS_0_ialpha_o(14), B => 
        FOC_TRANSFORMS_0_valpha_o_14, C => N_728, D => N_735, Y
         => prdata_o_1_0_iv_0_0_6_11);
    
    \rate_limit_slew_cnt_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_slew_cnt_o(10));
    
    \seq_cntl_cl_omega_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_seq_cntl_cl_omega_o(14));
    
    \prdata_o_1_iv_0_0_a3_16_sx_0[9]\ : CFG4
      generic map(INIT => x"FFFB")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(9), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(11), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(8), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(6), Y => 
        prdata_o_1_iv_0_0_a3_16_sx_0(9));
    
    \READ_DECODE_PROC.prdata_o276_0_a3_1_sx\ : CFG4
      generic map(INIT => x"FFFB")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(7), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(11), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(6), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(10), Y => 
        prdata_o276_0_a3_1_sx);
    
    \pwm_dead_time_val_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_dead_time_val_o(11));
    
    \speed_pi_kp_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_kp_o(1));
    
    \prdata_o_1_0_iv_0_7[1]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => N_738, B => N_727, C => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(1), D => 
        FOC_TRANSFORMS_0_vbeta_o(1), Y => prdata_o_1_0_iv_0_7(1));
    
    \adc_oc_thresh_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_oc_thresh_o(16));
    
    \prdata_o_1_0_iv_0_15_RNO[4]\ : CFG4
      generic map(INIT => x"0080")

      port map(A => N_711, B => \N_705\, C => 
        ADC_SCALING_0_ia_adc_o(4), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => N_663);
    
    pwm_delay_time_val_o_1_sqmuxa_0_a3_RNIO2EC1 : CFG4
      generic map(INIT => x"0040")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(3), B => 
        OLMNG_0_theta_o_4, C => N_715, D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => prdata_m1_e_4_1);
    
    auto_restart_no_o_1_sqmuxa_0_a3 : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(6), B => N_742, 
        C => MC_System_0_AMBA_SLAVE_0_PSELx, D => 
        rate_limit_slew_cnt_o_1_sqmuxa_0_a3_0_1_Z, Y => N_751);
    
    prdata_o_1_iv_0_0_7_N_5L9 : CFG3
      generic map(INIT => x"F7")

      port map(A => \prdata_o_1_iv_0_0_a3_9_out\, B => 
        SPEED_ID_IQ_PI_0_id_pi_output_o_10, C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => 
        prdata_o_1_iv_0_0_7_N_5L9_Z);
    
    \prdata_o_1_0_iv_0_a2_12[1]\ : CFG4
      generic map(INIT => x"0080")

      port map(A => \prdata_o_1_iv_0_0_a3_0_out\, B => \N_705\, C
         => FOC_TRANSFORMS_0_valpha_o_1, D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => N_569);
    
    \speed_pi_ki_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_ki_o(14));
    
    \speed_pi_kp_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_kp_o(12));
    
    \auto_restart_no_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => auto_restart_no_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_auto_restart_no_o(0));
    
    \seq_cntl_config_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_config_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_seq_cntl_config_o(2));
    
    \pwm_delay_time_val_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_delay_time_val_o(5));
    
    \prdata_o_1_iv_0_a2_11[11]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        RATE_LIMITER_0_rl_out_o(11), C => \N_705\, D => 
        prdata_o_1_iv_0_0_a3_0(9), Y => N_638);
    
    \seq_cntl_cl_omega_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_seq_cntl_cl_omega_o(4));
    
    \prdata_o_1_0_iv_0_0_a0[1]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_699, B => prdata_o_1_0_iv_0_0_a0_1(1), C
         => N_709, D => adc_channel_ch1_o_1_sqmuxa_0_a3_0_0_Z, Y
         => prdata_o_1_0_iv_0_0_a0(1));
    
    \olmng_dv_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_en_if_1_olmng_dv_o(13));
    
    \adc_channel_ch1_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch1_o(1));
    
    \rate_limit_rate_cnt_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_rate_cnt_o(15));
    
    \olmng_theta_factor_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_theta_factor_o(13));
    
    \prdata_o_1_0_iv_0_a2_11[1]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        RATE_LIMITER_0_rl_out_o(1), C => \N_705\, D => 
        prdata_o_1_iv_0_0_a3_0(9), Y => N_568);
    
    \prdata_o_1_0_iv_0_a2_9[16]\ : CFG4
      generic map(INIT => x"0080")

      port map(A => \prdata_o_1_iv_0_0_a3_0_out\, B => \N_705\, C
         => FOC_TRANSFORMS_0_valpha_o_16, D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => N_606);
    
    prdata_o_1_0_iv_0_15_N_5L9 : CFG4
      generic map(INIT => x"8000")

      port map(A => N_699, B => prdata_o_1_0_iv_0_a2_3_0(0), C
         => N_709, D => prdata_m3_e_1_3_0_Z, Y => 
        prdata_o_1_0_iv_0_15_N_5L9_Z);
    
    \idq_pi_ki_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_ki_o(8));
    
    \prdata_o_1_0_iv_0_0_11_a2_cZ[14]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_724, B => HALL_INTERFACE_1_omega_out_o(14), 
        C => N_704, D => prdata_o_1_iv_0_0_a3_24_0(9), Y => 
        prdata_o_1_0_iv_0_0_11_a2(14));
    
    \prdata_o_1_iv_0_0_14_1[10]\ : CFG4
      generic map(INIT => x"153F")

      port map(A => adc_interface_0_result_ch1_o_10, B => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(10), C => 
        prdata_o_1_iv_0_0_a3_0(9), D => 
        prdata_o_1_iv_0_0_a3_16_0(9), Y => 
        prdata_o_1_iv_0_0_14_1(10));
    
    \adc_channel_ch0_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch0_o(4));
    
    \prdata_o_1_iv_0_5[11]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => \N_748\, B => N_729, C => 
        FOC_TRANSFORMS_0_ibeta_o(11), D => 
        adc_interface_0_result_ch1_o_11, Y => 
        prdata_o_1_iv_0_5(11));
    
    \prdata_o_1_iv_0_0_16_1[8]\ : CFG3
      generic map(INIT => x"07")

      port map(A => adc_interface_0_result_ch1_o_8, B => \N_748\, 
        C => N_373, Y => prdata_o_1_iv_0_0_16_1(8));
    
    speed_pi_ki_o_1_sqmuxa_0_a3_RNIH6KK1 : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => N_709, 
        C => FOC_TRANSFORMS_0_valpha_o_4, D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), Y => prdata_N_5_mux_7);
    
    \prdata_o_1_iv_0_0_a2_9[7]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        OLMNG_0_theta_o_7, C => \N_705\, D => 
        \prdata_o_1_iv_0_0_a3_2_0\(9), Y => N_440);
    
    \prdata_o_1_iv_0_0_14_cZ[10]\ : CFG4
      generic map(INIT => x"FF20")

      port map(A => \G_15_1\, B => prdata_o_1_iv_0_0_14_1(10), C
         => prdata_o_1_iv_0_0_a3_19_out, D => 
        prdata_o_1_iv_0_0_9(10), Y => prdata_o_1_iv_0_0_14(10));
    
    \prdata_o_1_iv_0_0_a3_13[9]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_715, B => N_756, C => 
        \prdata_o_1_iv_0_0_a3_27_out\, D => \G_15_1\, Y => N_744);
    
    \prdata_o_1_0_iv_0_0_15_tz_0_RNO[3]\ : CFG4
      generic map(INIT => x"0040")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(3), B => 
        OLMNG_0_theta_o_3, C => N_715, D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => prdata_N_5_mux_1);
    
    \olmng_theta_factor_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_theta_factor_o(17));
    
    \prdata_o_1_0_iv_0_0_0_RNO[3]\ : CFG4
      generic map(INIT => x"0040")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => N_706, 
        C => ADC_SCALING_0_ia_adc_o(3), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), Y => prdata_m1_e_5_1);
    
    \prdata_o_1_0_iv_0_0_0[3]\ : CFG4
      generic map(INIT => x"8880")

      port map(A => \G_15_1\, B => \prdata_o_1_iv_0_0_a3_27_out\, 
        C => prdata_m1_e_5_1, D => prdata_m2_e_1_2, Y => 
        prdata_o_1_0_iv_0_0_0(3));
    
    \prdata_o_1_iv_0_0_a2_11[9]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        RATE_LIMITER_0_rl_out_o(9), C => \N_705\, D => 
        prdata_o_1_iv_0_0_a3_0(9), Y => N_362);
    
    \olmng_theta_factor_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_theta_factor_o(5));
    
    \prdata_o_1_iv_0_0_a3_25_0[9]\ : CFG3
      generic map(INIT => x"10")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(8), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(9), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(6), Y => 
        prdata_o_1_iv_0_0_a3_25_0(9));
    
    \idq_pi_kp_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_kp_o(4));
    
    \adc_channel_ch2_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch2_o(4));
    
    \adc_channel_ch3_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch3_o(12));
    
    \hall_speed_factor_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => hall_speed_factor_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_hall_if_0_hall_speed_factor_o(8));
    
    \prdata_o_1_0_iv_0_a2_18[15]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        SPEED_ID_IQ_PI_0_id_pi_output_o_15, C => \N_705\, D => 
        \prdata_o_1_iv_0_0_a3_9_out\, Y => N_509);
    
    \prdata_o_1_0_iv_0_a2_0[13]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => prdata_o_1_iv_0_0_a3_0(9), B => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(13), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_612);
    
    \speed_pi_ki_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_ki_o(12));
    
    \pwm_gain_val_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_gain_val_o(10));
    
    \prdata_o_1_0_iv_0_a2_22[3]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        RATE_LIMITER_0_rl_out_o(3), C => \N_705\, D => 
        prdata_o_1_iv_0_0_a3_0(9), Y => N_528);
    
    \speed_pi_kp_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_kp_o(13));
    
    \idq_pi_ki_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_ki_o(10));
    
    \adc_scale_val_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_scale_val_o(8));
    
    \olmng_iq_ref_in_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_iq_ref_in_o(4));
    
    \adc_channel_ch0_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch0_o(0));
    
    \adc_channel_ch0_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch0_o(6));
    
    \adc_channel_ch3_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch3_o(11));
    
    \prdata_o_1_0_iv_0_1[17]\ : CFG3
      generic map(INIT => x"F8")

      port map(A => HALL_INTERFACE_1_omega_out_o(17), B => N_731, 
        C => prdata_o_1_0_iv_0_0(17), Y => prdata_o_1_0_iv_0_1_15);
    
    \rate_limit_ref_in_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_ref_in_o(0));
    
    \prdata_o_1_0_iv_0_a2_6[1]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_711, B => ADC_SCALING_0_ib_adc_o(1), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_563);
    
    hall_sensor_polarity_o_1_sqmuxa_0_a3_1_RNIES161 : CFG4
      generic map(INIT => x"0040")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => N_706, 
        C => ADC_SCALING_0_ia_adc_o(9), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), Y => prdata_m1_e_8_1);
    
    pwm_period_val_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"8000")

      port map(A => N_753, B => N_715, C => \G_15_1\, D => N_725, 
        Y => pwm_period_val_o_1_sqmuxa);
    
    \prdata_o_1_iv_0_0_a3_9[9]\ : CFG4
      generic map(INIT => x"1000")

      port map(A => prdata_o_1_iv_0_0_a3_9_sx(9), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(10), C => 
        \prdata_o_1_iv_0_0_a3_27_out\, D => 
        \prdata_o_1_iv_0_0_a3_9_out\, Y => \N_737\);
    
    hall_sensor_polarity_o : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        hall_sensor_polarity_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_hall_if_0_hall_sensor_polarity_o);
    
    \seq_cntl_cl_omega_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_seq_cntl_cl_omega_o(9));
    
    \prdata_o_1_0_iv_0_a2_13[1]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => FOC_TRANSFORMS_0_id_o_1, B => \N_759\, C => 
        \prdata_o_1_iv_0_0_a3_27_out\, D => \G_15_1\, Y => N_570);
    
    \olmng_dv_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_en_if_1_olmng_dv_o(0));
    
    \adc_channel_ch0_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch0_o(12));
    
    \prdata_o_1_iv_0_0_a2_18[7]\ : CFG4
      generic map(INIT => x"0080")

      port map(A => N_711, B => \N_705\, C => 
        ADC_SCALING_0_ia_adc_o(7), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => N_449);
    
    \prdata_o_1_0_iv_0_a2_10[16]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => FOC_TRANSFORMS_0_id_o_16, B => \N_759\, C => 
        \prdata_o_1_iv_0_0_a3_27_out\, D => \G_15_1\, Y => N_607);
    
    \adc_channel_ch2_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch2_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch2_o(3));
    
    \pwm_dead_time_val_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_dead_time_val_o(16));
    
    \prdata_o_1_iv_0_0_a3_24_0_RNINON82[9]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_700, B => prdata_o_1_iv_0_0_a3_24_0(9), C
         => N_711, D => prdata_o276_0_a3_1_x, Y => N_747);
    
    adc_channel_ch1_o_1_sqmuxa_0_a3_0_0 : CFG2
      generic map(INIT => x"1")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(10), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(7), Y => 
        adc_channel_ch1_o_1_sqmuxa_0_a3_0_0_Z);
    
    \prdata_o_1_iv_0_0_8[8]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => HALL_INTERFACE_1_omega_out_o(8), B => 
        HALL_INTERFACE_1_angle_out_raw_o(8), C => N_731, D => 
        N_747, Y => prdata_o_1_iv_0_0_8(8));
    
    \prdata_o_1_iv_0_0_1_tz_1[7]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => prdata_m2_0_a2_31_0, B => prdata_m1_e_19_1_0, 
        C => \prdata_o_1_iv_0_0_a3_9_out\, D => 
        \prdata_o_1_iv_0_0_a3_0_out\, Y => 
        prdata_o_1_iv_0_0_1_tz_1(7));
    
    \prdata_o_1_0_iv_0_15_sx[0]\ : CFG4
      generic map(INIT => x"FF3B")

      port map(A => \N_705\, B => prdata_o_1_0_iv_0_15_sx_RNO(0), 
        C => prdata_o_1_0_iv_0_15_N_3L4_Z, D => 
        prdata_o_1_0_iv_0_15_N_5L9_Z, Y => 
        prdata_o_1_0_iv_0_15_sx(0));
    
    \prdata_o_1_iv_0_0_a3_2_sx_0[9]\ : CFG4
      generic map(INIT => x"FFFB")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(9), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(11), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(8), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(6), Y => 
        prdata_o_1_iv_0_0_a3_2_sx_0(9));
    
    \hall_speed_factor_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => hall_speed_factor_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_hall_if_0_hall_speed_factor_o(1));
    
    \adc_channel_ch0_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch0_o(11));
    
    \prdata_o_1_iv_0_0_a2_11[10]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        RATE_LIMITER_0_rl_out_o(10), C => \N_705\, D => 
        prdata_o_1_iv_0_0_a3_0(9), Y => N_462);
    
    \auto_restart_no_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => auto_restart_no_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_auto_restart_no_o(3));
    
    \prdata_o_1_iv_0_0_a3_27[9]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(6), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(11), C => \G_15_1\, D => 
        N_699, Y => \N_705\);
    
    \adc_channel_ch1_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch1_o(10));
    
    pwm_dead_time_val_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"8000")

      port map(A => N_756, B => N_715, C => N_725, D => \G_15_1\, 
        Y => pwm_dead_time_val_o_1_sqmuxa);
    
    \seq_cntl_cl_omega_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_seq_cntl_cl_omega_o(1));
    
    \prdata_o_1_0_iv_0_2[0]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => N_745, B => N_736, C => 
        adc_interface_0_result_ch3_o(0), D => 
        ADC_SCALING_0_ib_adc_o(0), Y => prdata_o_1_0_iv_0_2(0));
    
    \rate_limit_slew_cnt_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_slew_cnt_o(9));
    
    adc_channel_ch2_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"8000")

      port map(A => \G_15_1\, B => N_725, C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), D => N_724, Y => 
        adc_channel_ch2_o_1_sqmuxa);
    
    \olmng_dv_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_en_if_1_olmng_dv_o(7));
    
    \prdata_o_2_iv_0_a3_2[31]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        SPEED_ID_IQ_PI_0_id_pi_output_o_17, C => \N_705\, D => 
        \prdata_o_1_iv_0_0_a3_9_out\, Y => N_772);
    
    \adc_channel_ch3_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch3_o(2));
    
    \idq_pi_ki_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_ki_o(2));
    
    pwm_delay_time_val_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"8000")

      port map(A => N_764, B => N_715, C => \G_15_1\, D => N_725, 
        Y => pwm_delay_time_val_o_1_sqmuxa);
    
    \adc_scale_val_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_scale_val_o(2));
    
    GND_Z : GND
      port map(Y => \GND\);
    
    \prdata_o_1_iv_0_0_a3_10[9]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a3_27_out\, B => \G_15_1\, 
        C => MC_System_0_AMBA_SLAVE_0_PADDR(2), D => 
        \prdata_o_1_iv_0_0_a3_0_out\, Y => N_738);
    
    prdata_o_1_0_iv_0_N_3L4_1_RNO_0 : CFG3
      generic map(INIT => x"02")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(4), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => prdata_m3_e_2_1);
    
    \adc_scale_val_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_scale_val_o(3));
    
    \speed_pi_ki_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_ki_o(13));
    
    \prdata_o_2_iv_0[31]\ : CFG4
      generic map(INIT => x"FFF8")

      port map(A => \N_734\, B => FOC_TRANSFORMS_0_iq_o_17, C => 
        \prdata_o_0_3\(17), D => \prdata_o_0_5\(17), Y => 
        prdata_o_2(31));
    
    \adc_channel_ch1_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch1_o(0));
    
    \seq_cntl_cl_omega_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_cl_omega_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_seq_cntl_cl_omega_o(6));
    
    \speed_pi_kp_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_kp_o(16));
    
    \prdata_o_1_0_iv_0_7[4]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => FOC_TRANSFORMS_0_vbeta_o(4), B => 
        FOC_TRANSFORMS_0_ibeta_o(4), C => N_729, D => N_738, Y
         => prdata_o_1_0_iv_0_7_4);
    
    \prdata_o_1_iv_0_0_a2_13[9]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => FOC_TRANSFORMS_0_id_o_9, B => \N_759\, C => 
        \prdata_o_1_iv_0_0_a3_27_out\, D => \G_15_1\, Y => N_364);
    
    \olmng_dv_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_en_if_1_olmng_dv_o(10));
    
    \adc_oc_thresh_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_oc_thresh_o(3));
    
    \adc_oc_thresh_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_oc_thresh_o(14));
    
    \olmng_iq_ref_in_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_iq_ref_in_o(14));
    
    \idq_pi_ki_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_ki_o(0));
    
    \prdata_o_2_iv_0_3_RNO[31]\ : CFG4
      generic map(INIT => x"0080")

      port map(A => N_711, B => \N_705\, C => 
        ADC_SCALING_0_ia_adc_o(17), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => N_770);
    
    \prdata_o_1_iv_0_7[6]\ : CFG4
      generic map(INIT => x"FEFA")

      port map(A => N_424, B => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(6), C => 
        prdata_o_1_iv_0_1(6), D => N_733, Y => 
        prdata_o_1_iv_0_7(6));
    
    \prdata_o_1_0_iv_3_a2_9[2]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => FOC_TRANSFORMS_0_id_o_2, B => \N_759\, C => 
        \prdata_o_1_iv_0_0_a3_27_out\, D => \G_15_1\, Y => N_546);
    
    \pwm_gain_val_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_gain_val_o(6));
    
    \rate_limit_slew_cnt_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_slew_cnt_o(2));
    
    \prdata_o_1_iv_0_0_a3_16_0[9]\ : CFG3
      generic map(INIT => x"80")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(3), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), Y => 
        prdata_o_1_iv_0_0_a3_16_0(9));
    
    \pwm_dead_time_val_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_dead_time_val_o(3));
    
    \rate_limit_slew_cnt_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_slew_cnt_o(1));
    
    \pwm_gain_val_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_gain_val_o(5));
    
    \prdata_o_1_0_iv_0_14[2]\ : CFG4
      generic map(INIT => x"FF20")

      port map(A => N_756, B => prdata_o_1_0_iv_0_14_1_Z(2), C
         => \N_705\, D => prdata_o_1_0_iv_0_8(2), Y => 
        prdata_o_1_0_iv_0_14_2);
    
    \prdata_o_1_iv_0_0_a2_5[12]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_723, B => HALL_INTERFACE_1_theta_output_o_5, 
        C => N_704, D => prdata_o276_0_a3_0_0, Y => N_476);
    
    \olmng_theta_factor_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_theta_factor_o(9));
    
    \speed_pi_ki_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_ki_o(5));
    
    \rate_limit_ref_in_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_ref_in_o(10));
    
    \prdata_o_1_iv_0_7[11]\ : CFG4
      generic map(INIT => x"FEFA")

      port map(A => N_640, B => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(11), C => 
        prdata_o_1_iv_0_1(11), D => N_727, Y => 
        prdata_o_1_iv_0_7(11));
    
    \prdata_o_1_0_iv_0_8[1]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => HALL_INTERFACE_1_omega_out_o(1), B => 
        HALL_INTERFACE_1_angle_out_raw_o(1), C => N_731, D => 
        N_747, Y => prdata_o_1_0_iv_0_8(1));
    
    \olmng_theta_factor_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_theta_factor_o(3));
    
    \prdata_o_1_iv_0_0_a3_24_0[9]\ : CFG3
      generic map(INIT => x"20")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(8), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(9), Y => 
        prdata_o_1_iv_0_0_a3_24_0(9));
    
    \prdata_o_1_iv_0_0_5_1[7]\ : CFG4
      generic map(INIT => x"135F")

      port map(A => N_745, B => \N_734\, C => 
        adc_interface_0_result_ch3_o(7), D => 
        FOC_TRANSFORMS_0_iq_o_7, Y => prdata_o_1_iv_0_0_5_1(7));
    
    \prdata_o_1_0_iv_0_11_a0_cZ[13]\ : CFG4
      generic map(INIT => x"0080")

      port map(A => N_711, B => \N_705\, C => 
        ADC_SCALING_0_ia_adc_o(13), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => 
        prdata_o_1_0_iv_0_11_a0(13));
    
    \idq_pi_kp_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_kp_o(0));
    
    \adc_channel_ch1_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch1_o(15));
    
    \prdata_o_1_0_iv_0_0_a0_1[1]\ : CFG4
      generic map(INIT => x"0040")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(0), B => 
        prdata_m3_e_1_3_0_Z, C => FOC_TRANSFORMS_0_iq_o_1, D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(1), Y => 
        prdata_o_1_0_iv_0_0_a0_1(1));
    
    \pwm_period_val_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_period_val_o(3));
    
    \speed_pi_kp_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_kp_o(5));
    
    \prdata_o_1_iv_0_16[6]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => prdata_o_1_iv_0_7(6), B => N_422, C => 
        prdata_o_1_iv_0_5(6), D => prdata_o_1_iv_0_6(6), Y => 
        prdata_o_1_iv_0_16_0);
    
    \speed_pi_ki_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_ki_o(8));
    
    \olmng_dv_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_en_if_1_olmng_dv_o(11));
    
    \hall_speed_factor_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => hall_speed_factor_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_hall_if_0_hall_speed_factor_o(16));
    
    rate_limit_slew_cnt_o_1_sqmuxa_0_a3_2 : CFG3
      generic map(INIT => x"01")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(11), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(9), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(8), Y => N_718);
    
    prdata_o_1_iv_0_0_15_N_4L6 : CFG3
      generic map(INIT => x"F7")

      port map(A => N_706, B => ADC_SCALING_0_ia_adc_o(8), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), Y => 
        prdata_o_1_iv_0_0_15_N_4L6_Z);
    
    \pwm_delay_time_val_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_delay_time_val_o(3));
    
    \prdata_o_1_iv_0_1[6]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => adc_interface_0_result_ch2_o(6), B => 
        adc_interface_0_result_ch3_o(6), C => N_749, D => N_745, 
        Y => prdata_o_1_iv_0_1(6));
    
    \speed_pi_ki_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_ki_o(16));
    
    adc_channel_ch1_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"0800")

      port map(A => \G_15_1\, B => N_725, C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), D => N_724, Y => 
        adc_channel_ch1_o_1_sqmuxa);
    
    \prdata_o_1_iv_0_0_a3_17_sx[9]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(0), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(10), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(7), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(1), Y => 
        prdata_o_1_iv_0_0_a3_17_sx(9));
    
    adc_oc_thresh_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"2000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(5), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), C => N_750, D => N_753, 
        Y => adc_oc_thresh_o_1_sqmuxa);
    
    \prdata_o_1_iv_0_0_0[12]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => \N_734\, B => \N_705\, C => 
        FOC_TRANSFORMS_0_iq_o_12, D => prdata_m1_e_22_1, Y => 
        prdata_o_1_iv_0_0_0_Z(12));
    
    \prdata_o_1_0_iv_0_a2_20[3]\ : CFG4
      generic map(INIT => x"2000")

      port map(A => N_755, B => MC_System_0_AMBA_SLAVE_0_PADDR(6), 
        C => prdata_o_1_0_iv_0_a2_20_0(3), D => N_718, Y => N_526);
    
    \pwm_delay_time_val_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_delay_time_val_o(14));
    
    \adc_oc_thresh_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_oc_thresh_o(11));
    
    \pwm_period_val_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_period_val_o(8));
    
    \prdata_o_1_0_iv_0_16_cZ[2]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => prdata_o_1_0_iv_0_6(2), B => 
        prdata_o_1_0_iv_0_7(2), C => prdata_o_1_0_iv_0_5(2), D
         => N_544, Y => prdata_o_1_0_iv_0_16(2));
    
    \prdata_o_1_iv_0_14[6]\ : CFG4
      generic map(INIT => x"FEEE")

      port map(A => prdata_o_1_iv_0_8(6), B => N_425, C => 
        adc_interface_0_result_ch0_o(6), D => N_744, Y => 
        prdata_o_1_iv_0_14_0);
    
    \idq_pi_kp_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_kp_o(2));
    
    \prdata_o_1_iv_0_16[11]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => prdata_o_1_iv_0_7(11), B => N_638, C => 
        prdata_o_1_iv_0_5(11), D => prdata_o_1_iv_0_6(11), Y => 
        prdata_o_1_iv_0_16_5);
    
    \olmng_dv_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_en_if_1_olmng_dv_o(17));
    
    \hall_speed_factor_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => hall_speed_factor_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_hall_if_0_hall_speed_factor_o(10));
    
    \adc_oc_thresh_o[8]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(8), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_oc_thresh_o(8));
    
    \READ_DECODE_PROC.prdata_o276_0_a3_1\ : CFG4
      generic map(INIT => x"0001")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(0), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(1), C => 
        prdata_o276_0_a3_1_sx_x, D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(10), Y => N_704);
    
    \prdata_o_1_0_iv_0_0_3[3]\ : CFG4
      generic map(INIT => x"FFF8")

      port map(A => N_745, B => adc_interface_0_result_ch3_o(3), 
        C => N_533, D => N_526, Y => prdata_o_1_0_iv_0_0_3(3));
    
    \pwm_period_val_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_period_val_o(12));
    
    hall_sensor_polarity_o_1_sqmuxa_0_a3_0_1 : CFG3
      generic map(INIT => x"08")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(10), B => 
        N_700, C => MC_System_0_AMBA_SLAVE_0_PADDR(7), Y => 
        hall_sensor_polarity_o_1_sqmuxa_0_a3_0_1_Z);
    
    \pwm_dead_time_val_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_dead_time_val_o(12));
    
    \prdata_o_1_iv_0_0_5[7]\ : CFG4
      generic map(INIT => x"F2FF")

      port map(A => HALL_INTERFACE_1_theta_output_o_0, B => 
        \prdata_o276\, C => N_438, D => prdata_o_1_iv_0_0_5_1(7), 
        Y => prdata_o_1_iv_0_0_5_0);
    
    \pwm_period_val_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_period_val_o(2));
    
    \rate_limit_slew_cnt_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_slew_cnt_o(4));
    
    \adc_channel_ch1_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch1_o(9));
    
    \prdata_o_1_iv_0_0_15_cZ[8]\ : CFG4
      generic map(INIT => x"FFFB")

      port map(A => prdata_o_1_iv_0_0_15_N_8L16_Z, B => 
        prdata_o_1_iv_0_0_15_N_7L13_Z, C => N_383, D => N_381, Y
         => prdata_o_1_iv_0_0_15(8));
    
    \adc_oc_thresh_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_oc_thresh_o(17));
    
    \rate_limit_rate_cnt_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_rate_cnt_o(9));
    
    \prdata_o_1_0_iv_0_9[4]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => HALL_INTERFACE_1_omega_out_o(4), B => 
        HALL_INTERFACE_1_angle_out_raw_o(4), C => N_731, D => 
        N_747, Y => prdata_o_1_0_iv_0_9(4));
    
    \seq_cntl_config_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => seq_cntl_config_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_seq_cntl_config_o(0));
    
    \prdata_o_1_iv_0_0_a3_0[9]\ : CFG4
      generic map(INIT => x"0800")

      port map(A => \prdata_o_1_iv_0_0_a3_27_out\, B => \G_15_1\, 
        C => MC_System_0_AMBA_SLAVE_0_PADDR(2), D => 
        \prdata_o_1_iv_0_0_a3_0_out\, Y => N_728);
    
    \prdata_o_1_iv_0_0_a2_10[12]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => FOC_TRANSFORMS_0_id_o_12, B => \N_759\, C => 
        \prdata_o_1_iv_0_0_a3_27_out\, D => \G_15_1\, Y => N_481);
    
    \prdata_o_1_0_iv_0_0_7[3]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => N_738, B => N_733, C => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(3), D => 
        FOC_TRANSFORMS_0_vbeta_o(3), Y => 
        prdata_o_1_0_iv_0_0_7(3));
    
    \pwm_period_val_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_period_val_o(13));
    
    \prdata_o_1_0_iv_0_0_8[3]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => N_727, B => N_729, C => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(3), D => 
        FOC_TRANSFORMS_0_ibeta_o(3), Y => 
        prdata_o_1_0_iv_0_0_8(3));
    
    \prdata_o_1_iv_0_0_6[9]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => FOC_TRANSFORMS_0_vbeta_o(9), B => 
        FOC_TRANSFORMS_0_ibeta_o(9), C => N_729, D => N_738, Y
         => prdata_o_1_iv_0_0_6_Z(9));
    
    \adc_control_reg_val_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        adc_control_reg_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_control_reg_val_o(0));
    
    adc_channel_ch0_o_1_sqmuxa_0_a3_0 : CFG3
      generic map(INIT => x"01")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(3), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), Y => N_711);
    
    \speed_pi_kp_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_kp_o(11));
    
    \prdata_o_1_iv_0_12_cZ[5]\ : CFG4
      generic map(INIT => x"FFF8")

      port map(A => \N_748\, B => adc_interface_0_result_ch1_o_5, 
        C => N_402, D => N_392, Y => prdata_o_1_iv_0_12(5));
    
    start_motor_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"8000")

      port map(A => N_742, B => N_725, C => N_753, D => N_709, Y
         => start_motor_o_1_sqmuxa);
    
    \prdata_o_1_iv_0_0_a2_7[10]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_711, B => ADC_SCALING_0_ib_adc_o(10), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_458);
    
    \prdata_o_1_0_iv_0_0_a0_1_sx[2]\ : CFG4
      generic map(INIT => x"DFFF")

      port map(A => FOC_TRANSFORMS_0_iq_o_2, B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(11), Y => 
        prdata_o_1_0_iv_0_0_a0_1_sx(2));
    
    \adc_oc_thresh_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_oc_thresh_o(10));
    
    \prdata_o_1_0_iv_0_a2_8[16]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        RATE_LIMITER_0_rl_out_o(16), C => \N_705\, D => 
        prdata_o_1_iv_0_0_a3_0(9), Y => N_605);
    
    adc_scale_val_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"4000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(4), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), C => N_746, D => N_750, 
        Y => adc_scale_val_o_1_sqmuxa);
    
    hall_sensor_polarity_o_1_sqmuxa_0_a3_3 : CFG2
      generic map(INIT => x"1")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(0), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(1), Y => N_700);
    
    \olmng_iq_ref_in_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_iq_ref_in_o(12));
    
    \prdata_o_1_iv_0_0_a3_16_sx[9]\ : CFG4
      generic map(INIT => x"FFFB")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(7), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(0), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(1), Y => 
        prdata_o_1_iv_0_0_a3_16_sx(9));
    
    \adc_channel_ch1_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch1_o(13));
    
    \adc_oc_thresh_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_oc_thresh_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_oc_thresh_o(6));
    
    \pwm_period_val_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_period_val_o(11));
    
    \speed_pi_kp_o[4]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(4), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_kp_o(4));
    
    \rate_limit_ref_in_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_ref_in_o(3));
    
    \adc_channel_ch0_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch0_o(9));
    
    \speed_pi_kp_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_kp_o(2));
    
    \rate_limit_slew_cnt_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_slew_cnt_o(14));
    
    \prdata_o_1_0_iv_0_a2_4[16]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_711, B => ADC_SCALING_0_ib_adc_o(16), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_601);
    
    \adc_scale_val_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_scale_val_o(10));
    
    pwm_gain_val_o_1_sqmuxa_0_a3 : CFG4
      generic map(INIT => x"0001")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), Y => N_741);
    
    \pwm_dead_time_val_o[17]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(17), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_dead_time_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_dead_time_val_o(17));
    
    \hall_filter_factor_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        hall_filter_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_hall_if_0_hall_filter_factor_o(1));
    
    \speed_pi_ki_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_ki_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_ki_o(11));
    
    rate_limit_ref_in_o_1_sqmuxa_0_a2 : CFG2
      generic map(INIT => x"8")

      port map(A => N_754, B => N_755, Y => 
        rate_limit_ref_in_o_1_sqmuxa);
    
    \rate_limit_slew_cnt_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_slew_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_slew_cnt_o(11));
    
    \olmng_dv_o[1]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(1), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_en_if_1_olmng_dv_o(1));
    
    \hall_speed_factor_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => hall_speed_factor_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_hall_if_0_hall_speed_factor_o(15));
    
    \idq_pi_kp_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => idq_pi_kp_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_idq_pi_kp_o(15));
    
    \prdata_o_1_iv_0_0_a3_5[9]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a3_27_out\, B => \G_15_1\, 
        C => MC_System_0_AMBA_SLAVE_0_PADDR(2), D => 
        \prdata_o_1_iv_0_0_a3_9_out\, Y => N_733);
    
    \prdata_o_1_0_iv_0_14_1[2]\ : CFG4
      generic map(INIT => x"153F")

      port map(A => N_715, B => N_706, C => 
        FOC_TRANSFORMS_0_ialpha_o(2), D => 
        adc_interface_0_result_ch0_o(2), Y => 
        prdata_o_1_0_iv_0_14_1_Z(2));
    
    \olmng_dv_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_en_if_1_olmng_dv_o(14));
    
    \rate_limit_ref_in_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_ref_in_o(6));
    
    \pwm_delay_time_val_o[16]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(16), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_delay_time_val_o(16));
    
    \prdata_o_1_iv_0_0_10[10]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => N_733, B => N_747, C => 
        HALL_INTERFACE_1_angle_out_raw_o(10), D => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(10), Y => 
        prdata_o_1_iv_0_0_10_0);
    
    \speed_pi_kp_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => speed_pi_kp_o_0_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_speed_pi_kp_o(0));
    
    \hall_speed_factor_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => hall_speed_factor_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_hall_if_0_hall_speed_factor_o(12));
    
    \prdata_o_1_iv_0_0_1_tz_0_RNO[7]\ : CFG3
      generic map(INIT => x"02")

      port map(A => FOC_TRANSFORMS_0_ialpha_o(7), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), Y => prdata_m2_e_3_0);
    
    seq_cntl_cl_omega_o_1_sqmuxa_0_a2 : CFG4
      generic map(INIT => x"2000")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(5), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), C => N_751, D => N_756, 
        Y => seq_cntl_cl_omega_o_1_sqmuxa);
    
    \prdata_o_1_iv_0_0_1[8]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => adc_interface_0_result_ch2_o(8), B => 
        adc_interface_0_result_ch3_o(8), C => N_749, D => N_745, 
        Y => prdata_o_1_iv_0_0_1(8));
    
    \prdata_o_1_0_iv_0_0_0_RNO[15]\ : CFG4
      generic map(INIT => x"0040")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => N_706, 
        C => ADC_SCALING_0_ia_adc_o(15), D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), Y => prdata_m1_e_21_1);
    
    \hall_speed_factor_o[11]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(11), CLK => 
        MC_System_0_FIC_0_CLK, EN => hall_speed_factor_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_hall_if_0_hall_speed_factor_o(11));
    
    \pwm_period_val_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_period_val_o(14));
    
    \prdata_o_1_iv_0_0_16_cZ[8]\ : CFG4
      generic map(INIT => x"FFFD")

      port map(A => prdata_o_1_iv_0_0_16_1(8), B => 
        prdata_o_1_iv_0_0_6_Z(8), C => N_382, D => 
        prdata_o_1_iv_0_0_7(8), Y => prdata_o_1_iv_0_0_16(8));
    
    \prdata_o_1_0_iv_0_a2_15[0]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_706, B => \N_705\, C => 
        FOC_TRANSFORMS_0_ialpha_o(0), D => N_756, Y => N_592);
    
    \prdata_o_1_0_iv_0_a2_1[13]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a3_0_out\, B => 
        FOC_TRANSFORMS_0_vbeta_o(13), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_613);
    
    \pwm_delay_time_val_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        pwm_delay_time_val_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_delay_time_val_o(9));
    
    \adc_scale_val_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_scale_val_o(12));
    
    \prdata_o_1_0_iv_0_16_RNO[0]\ : CFG4
      generic map(INIT => x"FFF8")

      port map(A => adc_interface_0_result_ch1_o_0, B => \N_748\, 
        C => prdata_o_1_0_iv_0_3_sx(0), D => 
        prdata_o_1_0_iv_0_3(0), Y => prdata_o_1_0_iv_0_5(0));
    
    \olmng_theta_factor_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        olmng_theta_factor_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_theta_factor_o(2));
    
    \pwm_period_val_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_period_val_o(9));
    
    \prdata_o_1_0_iv_0_8[2]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => HALL_INTERFACE_1_omega_out_o(2), B => 
        HALL_INTERFACE_1_angle_out_raw_o(2), C => N_731, D => 
        N_747, Y => prdata_o_1_0_iv_0_8(2));
    
    \pwm_period_val_o[5]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(5), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_period_val_o(5));
    
    \prdata_o_1_0_iv_0_0_RNO_0[3]\ : CFG4
      generic map(INIT => x"0080")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => N_709, 
        C => FOC_TRANSFORMS_0_iq_o_3, D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), Y => prdata_m2_e_1_2);
    
    \prdata_o_1_0_iv_0_0_9[15]\ : CFG2
      generic map(INIT => x"E")

      port map(A => prdata_o_1_0_iv_0_0_4(15), B => 
        prdata_o_1_0_iv_0_0_3(15), Y => prdata_o_1_0_iv_0_0_9_12);
    
    \prdata_o_1_iv_0_0_1_tz_1_RNO[7]\ : CFG2
      generic map(INIT => x"4")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(2), B => 
        FOC_TRANSFORMS_0_valpha_o_7, Y => prdata_m2_0_a2_31_0);
    
    \prdata_o_1_0_iv_3_a2_8[2]\ : CFG4
      generic map(INIT => x"0080")

      port map(A => \prdata_o_1_iv_0_0_a3_0_out\, B => \N_705\, C
         => FOC_TRANSFORMS_0_valpha_o_2, D => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => N_545);
    
    \prdata_o_1_iv_0_9_cZ[5]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => N_735, B => N_744, C => 
        FOC_TRANSFORMS_0_ialpha_o(5), D => 
        adc_interface_0_result_ch0_o(5), Y => 
        prdata_o_1_iv_0_9(5));
    
    \prdata_o_1_0_iv_0_a2_3[13]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_724, B => FOC_TRANSFORMS_0_ibeta_o(13), C
         => prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => 
        N_615);
    
    \adc_channel_ch3_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch3_o(10));
    
    \prdata_o_1_0_iv_0_3_sx[0]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => FOC_TRANSFORMS_0_id_o_0, B => \N_759\, C => 
        \prdata_o_1_iv_0_0_a3_27_out\, D => \G_15_1\, Y => 
        prdata_o_1_0_iv_0_3_sx(0));
    
    \prdata_o_1_iv_0_5[6]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => adc_interface_0_result_ch1_o_6, B => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(6), C => N_727, D => 
        \N_748\, Y => prdata_o_1_iv_0_5(6));
    
    \hall_speed_factor_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => hall_speed_factor_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_hall_if_0_hall_speed_factor_o(0));
    
    \rate_limit_ref_in_o[14]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(14), CLK => 
        MC_System_0_FIC_0_CLK, EN => rate_limit_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_ref_in_o(14));
    
    prdata_o_1_iv_0_0_15_N_5L9 : CFG4
      generic map(INIT => x"00B3")

      port map(A => \prdata_o_1_iv_0_0_a3_2_0\(9), B => 
        prdata_o_1_iv_0_0_15_N_4L6_Z, C => OLMNG_0_theta_o_8, D
         => MC_System_0_AMBA_SLAVE_0_PADDR(2), Y => 
        prdata_o_1_iv_0_0_15_N_5L9_Z);
    
    \prdata_o_1_0_iv_0_5_1[1]\ : CFG4
      generic map(INIT => x"153F")

      port map(A => adc_interface_0_result_ch1_o_1, B => 
        adc_interface_0_result_ch2_o(1), C => N_749, D => \N_748\, 
        Y => prdata_o_1_0_iv_0_5_1(1));
    
    \prdata_o_1_iv_0_0_8[12]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => OLMNG_0_theta_o_12, B => 
        SPEED_ID_IQ_PI_0_id_pi_output_o_12, C => \N_737\, D => 
        \N_730\, Y => prdata_o_1_iv_0_0_8(12));
    
    speed_pi_kp_o_0_sqmuxa_0_a2 : CFG2
      generic map(INIT => x"8")

      port map(A => N_754, B => \N_759\, Y => 
        speed_pi_kp_o_0_sqmuxa);
    
    \adc_channel_ch3_o[9]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(9), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch3_o(9));
    
    \prdata_o_1_iv_0_0[5]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => \N_734\, B => \N_705\, C => 
        FOC_TRANSFORMS_0_iq_o_5, D => prdata_m1_e_17_1, Y => 
        prdata_o_1_iv_0_0_0);
    
    \prdata_o_1_0_iv_0_5[2]\ : CFG4
      generic map(INIT => x"FEEE")

      port map(A => N_554, B => prdata_o_1_0_iv_0_1(2), C => 
        adc_interface_0_result_ch1_o_2, D => \N_748\, Y => 
        prdata_o_1_0_iv_0_5(2));
    
    \prdata_o_1_iv_0_0_9[10]\ : CFG4
      generic map(INIT => x"EAC0")

      port map(A => FOC_TRANSFORMS_0_vbeta_o(10), B => 
        FOC_TRANSFORMS_0_ibeta_o(10), C => N_729, D => N_738, Y
         => prdata_o_1_iv_0_0_9(10));
    
    \prdata_o_1_iv_0_0_a2_13[5]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => FOC_TRANSFORMS_0_id_o_5, B => \N_759\, C => 
        \prdata_o_1_iv_0_0_a3_27_out\, D => \G_15_1\, Y => N_404);
    
    \adc_scale_val_o[15]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(15), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_scale_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_scale_val_o(15));
    
    \adc_channel_ch0_o[10]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(10), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch0_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch0_o(10));
    
    adc_channel_ch1_o_1_sqmuxa_0_a3_0_x : CFG3
      generic map(INIT => x"01")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(7), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(1), C => 
        MC_System_0_AMBA_SLAVE_0_PADDR(0), Y => 
        adc_channel_ch1_o_1_sqmuxa_0_a3_0_x_Z);
    
    \olmng_iq_ref_in_o[7]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(7), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_iq_ref_in_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_olmng_iq_ref_in_o(7));
    
    \adc_channel_ch3_o[6]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(6), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch3_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch3_o(6));
    
    speed_pi_ki_o_1_sqmuxa_0_a2 : CFG3
      generic map(INIT => x"80")

      port map(A => N_709, B => N_754, C => N_753, Y => 
        speed_pi_ki_o_1_sqmuxa);
    
    \prdata_o_1_iv_0_0_a1_cZ[5]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_711, B => ADC_SCALING_0_ib_adc_o(5), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => 
        prdata_o_1_iv_0_0_a1(5));
    
    \pwm_period_val_o[0]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(0), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_period_val_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_period_val_o(0));
    
    \prdata_o_1_iv_0_0_10[12]\ : CFG4
      generic map(INIT => x"FF20")

      port map(A => \G_15_1\, B => prdata_o_1_iv_0_0_10_1(12), C
         => prdata_o_1_iv_0_0_a3_19_out, D => 
        prdata_o_1_iv_0_0_5(12), Y => prdata_o_1_iv_0_0_10_2);
    
    \pwm_gain_val_o[13]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(13), CLK => 
        MC_System_0_FIC_0_CLK, EN => pwm_gain_val_o_1_sqmuxa, ALn
         => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_pwm_gain_val_o(13));
    
    \prdata_o_1_iv_0_0_a3_29[9]\ : CFG2
      generic map(INIT => x"1")

      port map(A => MC_System_0_AMBA_SLAVE_0_PADDR(8), B => 
        MC_System_0_AMBA_SLAVE_0_PADDR(9), Y => N_699);
    
    \prdata_o_1_iv_0_0_5[9]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => adc_interface_0_result_ch1_o_9, B => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(9), C => \N_748\, D => 
        N_733, Y => prdata_o_1_iv_0_0_5(9));
    
    \prdata_o_1_0_iv_0_a2[13]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \prdata_o_1_iv_0_0_a3_9_out\, B => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(13), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => N_611);
    
    \adc_channel_ch1_o[2]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(2), CLK => 
        MC_System_0_FIC_0_CLK, EN => adc_channel_ch1_o_1_sqmuxa, 
        ALn => MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, 
        SD => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_adc_channel_ch1_o(2));
    
    \prdata_o_1_iv_0_0_a1_cZ[6]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => N_711, B => ADC_SCALING_0_ib_adc_o(6), C => 
        prdata_o_1_iv_0_0_a3_19_out, D => \G_15_1\, Y => 
        prdata_o_1_iv_0_0_a1(6));
    
    \olmng_dv_o[3]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(3), CLK => 
        MC_System_0_FIC_0_CLK, EN => olmng_dv_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => apb3_en_if_1_olmng_dv_o(3));
    
    \rate_limit_rate_cnt_o[12]\ : SLE
      port map(D => MC_System_0_AMBA_SLAVE_0_PWDATA(12), CLK => 
        MC_System_0_FIC_0_CLK, EN => 
        rate_limit_rate_cnt_o_1_sqmuxa, ALn => 
        MC_System_0_FIC_0_LOCK, ADn => \VCC\, SLn => \VCC\, SD
         => \GND\, LAT => \GND\, Q => 
        apb3_en_if_1_rate_limit_rate_cnt_o(12));
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity BLDC_HALL_Axis is

    port( FOC_TRANSFORMS_0_id_o_4            : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_6            : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_9            : out   std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_5  : out   std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_6  : out   std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_9  : out   std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_11 : out   std_logic;
          HALL_INTERFACE_1_theta_output_o_0  : out   std_logic;
          HALL_INTERFACE_1_theta_output_o_1  : out   std_logic;
          HALL_INTERFACE_1_theta_output_o_4  : out   std_logic;
          HALL_INTERFACE_1_theta_output_o_6  : out   std_logic;
          OLMNG_0_theta_o_5                  : out   std_logic;
          OLMNG_0_theta_o_6                  : out   std_logic;
          OLMNG_0_theta_o_9                  : out   std_logic;
          OLMNG_0_theta_o_11                 : out   std_logic;
          FOC_TRANSFORMS_0_valpha_o_5        : out   std_logic;
          FOC_TRANSFORMS_0_valpha_o_6        : out   std_logic;
          FOC_TRANSFORMS_0_valpha_o_9        : out   std_logic;
          FOC_TRANSFORMS_0_valpha_o_11       : out   std_logic;
          adc_interface_0_result_ch1_o_4     : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PWDATA    : in    std_logic_vector(17 downto 0);
          MC_System_0_AMBA_SLAVE_0_PRDATA    : out   std_logic_vector(19 to 19);
          prdata_o_1_iv_0_0_a3_2_0           : out   std_logic_vector(9 to 9);
          prdata_o_1_0_iv_0_8                : out   std_logic_vector(13 to 13);
          MC_System_0_AMBA_SLAVE_0_PADDR     : in    std_logic_vector(11 downto 0);
          prdata_o_1_iv_0_0_7                : out   std_logic_vector(10 to 10);
          prdata_o_1_iv_0_0_15               : out   std_logic_vector(8 to 8);
          prdata_o_0_5                       : out   std_logic_vector(17 to 17);
          prdata_o_1_iv_0_0_5                : out   std_logic_vector(7 to 7);
          prdata_o_1_iv_0_0_a1               : out   std_logic_vector(6 downto 5);
          prdata_o_1_iv_0_0_0                : out   std_logic;
          prdata_o_1_iv_0_0_6                : out   std_logic;
          prdata_o_1_0_iv_0_0_11_a2          : out   std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_0_11_a0          : out   std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_11_a2            : out   std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_11_a0            : out   std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_1                : out   std_logic_vector(17 to 17);
          prdata_o_1_iv_0_9                  : out   std_logic_vector(5 to 5);
          prdata_o_1_iv_0_8                  : out   std_logic_vector(5 to 5);
          prdata_o_1_iv_0_6                  : out   std_logic_vector(5 to 5);
          prdata_o_1_iv_0_0_10_2             : out   std_logic;
          prdata_o_1_iv_0_0_10_0             : out   std_logic;
          prdata_o_1_0_iv_0_0_7              : out   std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_0_6              : out   std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_7_0              : out   std_logic;
          prdata_o_1_0_iv_0_7_9              : out   std_logic;
          prdata_o_1_0_iv_0_6_3              : out   std_logic;
          prdata_o_1_0_iv_0_6_0              : out   std_logic;
          prdata_o_1_0_iv_0_5                : out   std_logic_vector(16 to 16);
          prdata_o_1_0_iv_0_4                : out   std_logic_vector(16 to 16);
          prdata_o_1_0_iv_0_3                : out   std_logic_vector(16 to 16);
          prdata_o_1_iv_0_12                 : out   std_logic_vector(5 to 5);
          prdata_o_1_iv_0_7                  : out   std_logic_vector(5 to 5);
          prdata_o_1_iv_0_0_14               : out   std_logic_vector(10 downto 8);
          prdata_o_1_iv_0_14_0               : out   std_logic;
          prdata_o_1_iv_0_14_5               : out   std_logic;
          prdata_o_1_iv_0_0_11_2             : out   std_logic;
          prdata_o_1_iv_0_0_11_0             : out   std_logic;
          prdata_o_1_0_iv_0_14_2             : out   std_logic;
          prdata_o_1_0_iv_0_14_0             : out   std_logic;
          prdata_o_1_0_iv_0_14_1             : out   std_logic;
          prdata_o_1_0_iv_0_14_4             : out   std_logic;
          prdata_o_1_0_iv_0_0_8              : out   std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_9                : out   std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_0_11             : out   std_logic_vector(15 to 15);
          prdata_o_1_0_iv_0_11               : out   std_logic_vector(16 to 16);
          prdata_o_0_3                       : out   std_logic_vector(17 to 17);
          prdata_o_1_0_iv_0_15_0             : out   std_logic;
          prdata_o_1_0_iv_0_15_4             : out   std_logic;
          prdata_o_1_0_iv_0_15_2             : out   std_logic;
          prdata_o_1_0_iv_0_15_1             : out   std_logic;
          prdata_o_1_0_iv_0_0_14             : out   std_logic_vector(3 to 3);
          prdata_o_1_0_iv_0_0_9_11           : out   std_logic;
          prdata_o_1_0_iv_0_0_9_12           : out   std_logic;
          prdata_o_1_0_iv_0_0_9_0            : out   std_logic;
          prdata_o_1_0_iv_0_0_10_0           : out   std_logic;
          prdata_o_1_0_iv_0_0_10_12          : out   std_logic;
          prdata_o_1_iv_0_0_12_3             : out   std_logic;
          prdata_o_1_iv_0_0_12_0             : out   std_logic;
          prdata_o_1_iv_0_0_12_5             : out   std_logic;
          prdata_o_1_iv_0_0_16               : out   std_logic_vector(9 downto 8);
          prdata_o_1_iv_0_16_0               : out   std_logic;
          prdata_o_1_iv_0_16_5               : out   std_logic;
          prdata_o_1_0_iv_0_16               : out   std_logic_vector(2 downto 0);
          prdata_o_1_iv_0_0_13               : out   std_logic_vector(7 to 7);
          MC_System_0_FIC_0_LOCK             : in    std_logic;
          MC_System_0_FIC_0_CLK              : in    std_logic;
          A0_PWM_VL_O_c                      : out   std_logic;
          A0_PWM_UH_O_c                      : out   std_logic;
          A0_PWM_VH_O_c                      : out   std_logic;
          A0_PWM_WH_O_c                      : out   std_logic;
          HA_i_c                             : in    std_logic;
          HB_i_c                             : in    std_logic;
          HC_i_c                             : in    std_logic;
          A0_ADC_SDI_I_c                     : in    std_logic;
          A0_ADC_SDO_O_c                     : out   std_logic;
          A0_ADC_CS_O_c                      : out   std_logic;
          A0_ADC_SCK_O_c                     : out   std_logic;
          prdata_o276                        : out   std_logic;
          G_15_1                             : out   std_logic;
          N_730                              : out   std_logic;
          N_748                              : out   std_logic;
          prdata_o_1_iv_0_0_a3_27_out        : out   std_logic;
          prdata_o_1_iv_0_0_a3_9_out         : out   std_logic;
          N_737                              : out   std_logic;
          N_759                              : out   std_logic;
          N_705                              : out   std_logic;
          prdata_o_1_iv_0_0_a3_0_out         : out   std_logic;
          N_734                              : out   std_logic;
          N_745                              : in    std_logic;
          prdata_m1_e_8_1                    : out   std_logic;
          prdata_m1_e_4_1                    : out   std_logic;
          prdata_m1_e_12_1                   : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PWRITE    : in    std_logic;
          MC_System_0_AMBA_SLAVE_0_PENABLE   : in    std_logic;
          prdata_N_5_mux_6                   : out   std_logic;
          prdata_N_5_mux_7                   : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PSELx     : in    std_logic;
          N_358                              : out   std_logic;
          N_634                              : out   std_logic;
          N_462                              : out   std_logic;
          N_449                              : out   std_logic;
          N_442                              : out   std_logic;
          N_440                              : out   std_logic
        );

end BLDC_HALL_Axis;

architecture DEF_ARCH of BLDC_HALL_Axis is 

  component PWM3PH
    port( reset_i        : in    std_logic := 'U';
          sys_clk_i      : in    std_logic := 'U';
          en_pwm_i       : in    std_logic := 'U';
          en_dual_trig_i : in    std_logic := 'U';
          va_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          vb_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          vc_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          pwm_period_i   : in    std_logic_vector(17 downto 0) := (others => 'U');
          dead_time_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          delay_time_i   : in    std_logic_vector(17 downto 0) := (others => 'U');
          midmatch_o     : out   std_logic;
          PWM_AH_o       : out   std_logic;
          PWM_BH_o       : out   std_logic;
          PWM_CH_o       : out   std_logic;
          PWM_AL_o       : out   std_logic;
          PWM_BL_o       : out   std_logic;
          PWM_CL_o       : out   std_logic
        );
  end component;

  component SVM
    port( reset_i   : in    std_logic := 'U';
          sys_clk_i : in    std_logic := 'U';
          start_i   : in    std_logic := 'U';
          va_i      : in    std_logic_vector(17 downto 0) := (others => 'U');
          vb_i      : in    std_logic_vector(17 downto 0) := (others => 'U');
          vc_i      : in    std_logic_vector(17 downto 0) := (others => 'U');
          va3h_o    : out   std_logic_vector(17 downto 0);
          vb3h_o    : out   std_logic_vector(17 downto 0);
          vc3h_o    : out   std_logic_vector(17 downto 0);
          done_o    : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component ADC_SCALING
    port( reset_i              : in    std_logic := 'U';
          sys_clk_i            : in    std_logic := 'U';
          adc_results_rdy_i    : in    std_logic := 'U';
          adc_scale_val_i      : in    std_logic_vector(17 downto 0) := (others => 'U');
          adc_result_ch0_i     : in    std_logic_vector(11 downto 0) := (others => 'U');
          adc_result_ch1_i     : in    std_logic_vector(11 downto 0) := (others => 'U');
          fault_threshold_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          done_o               : out   std_logic;
          calib_done_o         : out   std_logic;
          over_current_fault_o : out   std_logic;
          ia_adc_o             : out   std_logic_vector(17 downto 0);
          ib_adc_o             : out   std_logic_vector(17 downto 0)
        );
  end component;

  component OLMNG
    port( reset_i            : in    std_logic := 'U';
          sys_clk_i          : in    std_logic := 'U';
          start_i            : in    std_logic := 'U';
          clear_buffer_i     : in    std_logic := 'U';
          direction_config_i : in    std_logic := 'U';
          cl_status_i        : in    std_logic := 'U';
          theta_factor_i     : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_ref_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          dv_i               : in    std_logic_vector(17 downto 0) := (others => 'U');
          theta_cl_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_ref_in_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          done_o             : out   std_logic;
          theta_o            : out   std_logic_vector(17 downto 0);
          init_speedpi_o     : out   std_logic_vector(17 downto 0);
          init_iqpi_o        : out   std_logic_vector(17 downto 0)
        );
  end component;

  component RATE_LIMITER
    port( reset_i      : in    std_logic := 'U';
          sys_clk_i    : in    std_logic := 'U';
          start_i      : in    std_logic := 'U';
          soft_stop_i  : in    std_logic := 'U';
          reset_rl_i   : in    std_logic := 'U';
          direction_i  : in    std_logic := 'U';
          slew_count_i : in    std_logic_vector(17 downto 0) := (others => 'U');
          rate_count_i : in    std_logic_vector(17 downto 0) := (others => 'U');
          rl_in_i      : in    std_logic_vector(17 downto 0) := (others => 'U');
          rl_out_o     : out   std_logic_vector(17 downto 0);
          rl_done_o    : out   std_logic
        );
  end component;

  component SPEED_ID_IQ_PI
    port( reset_i              : in    std_logic := 'U';
          sys_clk_i            : in    std_logic := 'U';
          clear_buffer_i       : in    std_logic := 'U';
          speed_en_i           : in    std_logic := 'U';
          idq_en_i             : in    std_logic := 'U';
          speed_pi_start_i     : in    std_logic := 'U';
          id_pi_start_i        : in    std_logic := 'U';
          iq_pi_start_i        : in    std_logic := 'U';
          speed_init_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          id_init_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_init_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_ref_input_i : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_act_input_i : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_kp_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_ki_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_ymax_i      : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_ymin_i      : in    std_logic_vector(17 downto 0) := (others => 'U');
          id_pi_ref_input_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          id_pi_act_input_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          id_pi_kp_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          id_pi_ki_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          idq_pi_ymax_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          idq_pi_ymin_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_pi_ref_input_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_pi_act_input_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_pi_kp_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          iq_pi_ki_i           : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_pi_done_o      : out   std_logic;
          id_pi_done_o         : out   std_logic;
          iq_pi_done_o         : out   std_logic;
          speed_pi_output_o    : out   std_logic_vector(17 downto 0);
          id_pi_output_o       : out   std_logic_vector(17 downto 0);
          iq_pi_output_o       : out   std_logic_vector(17 downto 0)
        );
  end component;

  component SEQ_CONTROLLER
    port( reset_i         : in    std_logic := 'U';
          sys_clk_i       : in    std_logic := 'U';
          fault_i         : in    std_logic := 'U';
          start_motor_i   : in    std_logic := 'U';
          stop_motor_i    : in    std_logic := 'U';
          fault_clear_i   : in    std_logic := 'U';
          speed_ref_i     : in    std_logic_vector(17 downto 0) := (others => 'U');
          speed_cl_i      : in    std_logic_vector(17 downto 0) := (others => 'U');
          vq_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          max_ar_i        : in    std_logic_vector(3 downto 0) := (others => 'U');
          calib_done_i    : in    std_logic := 'U';
          pwm_midmatch_i  : in    std_logic := 'U';
          foc_done_i      : in    std_logic := 'U';
          config_reg_i    : in    std_logic_vector(3 downto 0) := (others => 'U');
          adc_start_o     : out   std_logic;
          cl_status_o     : out   std_logic;
          en_idq_pi_o     : out   std_logic;
          en_pwm_o        : out   std_logic;
          motor_stopped_o : out   std_logic;
          reset_rl_o      : out   std_logic;
          soft_stop_o     : out   std_logic;
          sensor_reset_o  : out   std_logic;
          state_o         : out   std_logic_vector(3 downto 0)
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component FOC_TRANSFORMS
    port( reset_i         : in    std_logic := 'U';
          sys_clk_i       : in    std_logic := 'U';
          start_clarke_i  : in    std_logic := 'U';
          start_park_i    : in    std_logic := 'U';
          start_ipark_i   : in    std_logic := 'U';
          start_iclarke_i : in    std_logic := 'U';
          ia_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          ib_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          ialpha_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          ibeta_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          vd_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          vq_i            : in    std_logic_vector(17 downto 0) := (others => 'U');
          valpha_i        : in    std_logic_vector(17 downto 0) := (others => 'U');
          vbeta_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          theta_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          clarke_done_o   : out   std_logic;
          park_done_o     : out   std_logic;
          ipark_done_o    : out   std_logic;
          iclarke_done_o  : out   std_logic;
          ialpha_o        : out   std_logic_vector(17 downto 0);
          ibeta_o         : out   std_logic_vector(17 downto 0);
          id_o            : out   std_logic_vector(17 downto 0);
          iq_o            : out   std_logic_vector(17 downto 0);
          valpha_o        : out   std_logic_vector(17 downto 0);
          vbeta_o         : out   std_logic_vector(17 downto 0);
          va_o            : out   std_logic_vector(17 downto 0);
          vb_o            : out   std_logic_vector(17 downto 0);
          vc_o            : out   std_logic_vector(17 downto 0)
        );
  end component;

  component adc_interface
    port( apb3_en_if_1_adc_control_reg_val_o : in    std_logic_vector(5 downto 0) := (others => 'U');
          adc_interface_0_result_ch0_o       : out   std_logic_vector(11 downto 0);
          adc_interface_0_result_ch1_o       : out   std_logic_vector(11 downto 0);
          adc_interface_0_result_ch2_o       : out   std_logic_vector(11 downto 0);
          adc_interface_0_result_ch3_o       : out   std_logic_vector(11 downto 0);
          apb3_en_if_1_adc_channel_ch2_o     : in    std_logic_vector(15 downto 0) := (others => 'U');
          apb3_en_if_1_adc_channel_ch0_o     : in    std_logic_vector(15 downto 0) := (others => 'U');
          apb3_en_if_1_adc_channel_ch1_o     : in    std_logic_vector(15 downto 0) := (others => 'U');
          apb3_en_if_1_adc_channel_ch3_o     : in    std_logic_vector(15 downto 0) := (others => 'U');
          MC_System_0_FIC_0_LOCK             : in    std_logic := 'U';
          MC_System_0_FIC_0_CLK              : in    std_logic := 'U';
          SEQ_CONTROLLER_1_adc_start_o       : in    std_logic := 'U';
          A0_ADC_SDI_I_c                     : in    std_logic := 'U';
          A0_ADC_SDO_O_c                     : out   std_logic;
          A0_ADC_CS_O_c                      : out   std_logic;
          A0_ADC_SCK_O_c                     : out   std_logic;
          adc_interface_0_results_rdy_o      : out   std_logic
        );
  end component;

  component PWM_SCALING
    port( reset_i      : in    std_logic := 'U';
          sys_clk_i    : in    std_logic := 'U';
          start_i      : in    std_logic := 'U';
          va_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          vb_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          vc_i         : in    std_logic_vector(17 downto 0) := (others => 'U');
          pwm_period_i : in    std_logic_vector(17 downto 0) := (others => 'U');
          pwm_gain_i   : in    std_logic_vector(17 downto 0) := (others => 'U');
          Va_o         : out   std_logic_vector(17 downto 0);
          Vb_o         : out   std_logic_vector(17 downto 0);
          Vc_o         : out   std_logic_vector(17 downto 0);
          done_o       : out   std_logic
        );
  end component;

  component HALL_INTERFACE
    port( reset_i           : in    std_logic := 'U';
          sys_clk_i         : in    std_logic := 'U';
          ha_i              : in    std_logic := 'U';
          hb_i              : in    std_logic := 'U';
          hc_i              : in    std_logic := 'U';
          clear_buffer_i    : in    std_logic := 'U';
          fil_trig_i        : in    std_logic := 'U';
          filter_factor_i   : in    std_logic_vector(3 downto 0) := (others => 'U');
          hall_sensor_pol_i : in    std_logic := 'U';
          speed_factor_i    : in    std_logic_vector(17 downto 0) := (others => 'U');
          omega_done_o      : out   std_logic;
          omega_out_o       : out   std_logic_vector(17 downto 0);
          angle_out_raw_o   : out   std_logic_vector(17 downto 0);
          theta_output_o    : out   std_logic_vector(17 downto 0)
        );
  end component;

  component apb3_hall_if
    port( apb3_en_if_1_idq_pi_ki_o              : out   std_logic_vector(17 downto 0);
          MC_System_0_AMBA_SLAVE_0_PWDATA       : in    std_logic_vector(17 downto 0) := (others => 'U');
          apb3_en_if_1_idq_pi_kp_o              : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_olmng_dv_o               : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_olmng_iq_ref_in_o        : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_olmng_theta_factor_o     : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_pwm_dead_time_val_o      : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_pwm_delay_time_val_o     : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_pwm_gain_val_o           : out   std_logic_vector(17 downto 1);
          apb3_en_if_1_pwm_period_val_o         : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_rate_limit_rate_cnt_o    : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_rate_limit_ref_in_o      : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_rate_limit_slew_cnt_o    : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_seq_cntl_cl_omega_o      : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_speed_pi_ki_o            : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_speed_pi_kp_o            : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_seq_cntl_config_o        : out   std_logic_vector(3 downto 0);
          apb3_hall_if_0_hall_filter_factor_o   : out   std_logic_vector(3 downto 0);
          apb3_en_if_1_auto_restart_no_o        : out   std_logic_vector(3 downto 0);
          apb3_en_if_1_adc_control_reg_val_o    : out   std_logic_vector(5 downto 0);
          apb3_en_if_1_adc_channel_ch0_o        : out   std_logic_vector(15 downto 0);
          apb3_en_if_1_adc_channel_ch1_o        : out   std_logic_vector(15 downto 0);
          apb3_en_if_1_adc_channel_ch2_o        : out   std_logic_vector(15 downto 0);
          apb3_en_if_1_adc_channel_ch3_o        : out   std_logic_vector(15 downto 0);
          apb3_en_if_1_adc_oc_thresh_o          : out   std_logic_vector(17 downto 0);
          apb3_en_if_1_adc_scale_val_o          : out   std_logic_vector(17 downto 0);
          apb3_hall_if_0_hall_speed_factor_o    : out   std_logic_vector(17 downto 0);
          MC_System_0_AMBA_SLAVE_0_PRDATA       : out   std_logic_vector(19 to 19);
          prdata_o_1_iv_0_0_a3_2_0              : out   std_logic_vector(9 to 9);
          prdata_o_1_0_iv_0_8_13                : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PADDR        : in    std_logic_vector(11 downto 0) := (others => 'U');
          prdata_o_1_iv_0_0_7_2                 : out   std_logic;
          prdata_o_1_iv_0_0_15                  : out   std_logic_vector(8 to 8);
          prdata_o_0_5                          : out   std_logic_vector(17 to 17);
          prdata_o_1_iv_0_0_5_0                 : out   std_logic;
          prdata_o_1_iv_0_0_a1                  : out   std_logic_vector(6 downto 5);
          prdata_o_1_iv_0_0_0                   : out   std_logic;
          prdata_o_1_iv_0_0_6                   : out   std_logic;
          HALL_INTERFACE_1_theta_output_o_6     : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_1     : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_0     : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_9     : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_8     : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_5     : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_10    : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_3     : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_7     : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_0               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_10              : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_13              : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_17              : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_3               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_11              : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_16              : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_1               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_2               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_15              : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_12              : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_7               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_6               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_5               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_8               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_9               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_id_o_14              : in    std_logic := 'U';
          ADC_SCALING_0_ib_adc_o                : in    std_logic_vector(17 downto 0) := (others => 'U');
          FOC_TRANSFORMS_0_iq_o_2               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_1               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_8               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_16              : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_7               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_3               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_0               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_17              : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_5               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_11              : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_10              : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_4               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_14              : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_13              : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_15              : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_12              : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_11_a2             : out   std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_0_11_a0             : out   std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_11_a2               : out   std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_11_a0               : out   std_logic_vector(13 to 13);
          SEQ_CONTROLLER_0_state_o              : in    std_logic_vector(3 downto 0) := (others => 'U');
          ADC_SCALING_0_ia_adc_o                : in    std_logic_vector(17 downto 0) := (others => 'U');
          prdata_o_1_0_iv_0_1_15                : out   std_logic;
          prdata_o_1_iv_0_9                     : out   std_logic_vector(5 to 5);
          prdata_o_1_iv_0_8_0                   : out   std_logic;
          prdata_o_1_iv_0_6_0                   : out   std_logic;
          adc_interface_0_result_ch3_o          : in    std_logic_vector(11 downto 0) := (others => 'U');
          prdata_o_1_iv_0_0_10_2                : out   std_logic;
          prdata_o_1_iv_0_0_10_0                : out   std_logic;
          prdata_o_1_0_iv_0_0_7_11              : out   std_logic;
          prdata_o_1_0_iv_0_0_6_11              : out   std_logic;
          prdata_o_1_0_iv_0_7_4                 : out   std_logic;
          prdata_o_1_0_iv_0_7_13                : out   std_logic;
          FOC_TRANSFORMS_0_ialpha_o             : in    std_logic_vector(17 downto 0) := (others => 'U');
          FOC_TRANSFORMS_0_valpha_o_17          : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_12          : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_7           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_10          : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_3           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_4           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_16          : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_0           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_1           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_2           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_15          : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_8           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_14          : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_13          : in    std_logic := 'U';
          prdata_o_1_0_iv_0_6_16                : out   std_logic;
          prdata_o_1_0_iv_0_6_13                : out   std_logic;
          prdata_o_1_0_iv_0_5_16                : out   std_logic;
          FOC_TRANSFORMS_0_vbeta_o              : in    std_logic_vector(17 downto 0) := (others => 'U');
          prdata_o_1_0_iv_0_4_15                : out   std_logic;
          prdata_o_1_0_iv_0_3_16                : out   std_logic;
          OLMNG_0_theta_o_10                    : in    std_logic := 'U';
          OLMNG_0_theta_o_0                     : in    std_logic := 'U';
          OLMNG_0_theta_o_8                     : in    std_logic := 'U';
          OLMNG_0_theta_o_4                     : in    std_logic := 'U';
          OLMNG_0_theta_o_17                    : in    std_logic := 'U';
          OLMNG_0_theta_o_3                     : in    std_logic := 'U';
          OLMNG_0_theta_o_16                    : in    std_logic := 'U';
          OLMNG_0_theta_o_1                     : in    std_logic := 'U';
          OLMNG_0_theta_o_2                     : in    std_logic := 'U';
          OLMNG_0_theta_o_15                    : in    std_logic := 'U';
          OLMNG_0_theta_o_7                     : in    std_logic := 'U';
          OLMNG_0_theta_o_14                    : in    std_logic := 'U';
          OLMNG_0_theta_o_13                    : in    std_logic := 'U';
          OLMNG_0_theta_o_12                    : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_10    : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_7     : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_4     : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_3     : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_8     : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_17    : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_16    : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_0     : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_1     : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_2     : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_15    : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_14    : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_13    : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_12    : in    std_logic := 'U';
          adc_interface_0_result_ch2_o          : in    std_logic_vector(11 downto 0) := (others => 'U');
          FOC_TRANSFORMS_0_ibeta_o              : in    std_logic_vector(17 downto 0) := (others => 'U');
          prdata_o_1_iv_0_12                    : out   std_logic_vector(5 to 5);
          prdata_o_1_iv_0_7_0                   : out   std_logic;
          prdata_o_1_iv_0_0_14                  : out   std_logic_vector(10 downto 8);
          prdata_o_1_iv_0_14_0                  : out   std_logic;
          prdata_o_1_iv_0_14_5                  : out   std_logic;
          SPEED_ID_IQ_PI_0_speed_pi_output_o    : in    std_logic_vector(17 downto 0) := (others => 'U');
          adc_interface_0_result_ch0_o          : in    std_logic_vector(11 downto 0) := (others => 'U');
          adc_interface_0_result_ch1_o_0        : in    std_logic := 'U';
          adc_interface_0_result_ch1_o_1        : in    std_logic := 'U';
          adc_interface_0_result_ch1_o_8        : in    std_logic := 'U';
          adc_interface_0_result_ch1_o_10       : in    std_logic := 'U';
          adc_interface_0_result_ch1_o_7        : in    std_logic := 'U';
          adc_interface_0_result_ch1_o_6        : in    std_logic := 'U';
          adc_interface_0_result_ch1_o_9        : in    std_logic := 'U';
          adc_interface_0_result_ch1_o_11       : in    std_logic := 'U';
          adc_interface_0_result_ch1_o_3        : in    std_logic := 'U';
          adc_interface_0_result_ch1_o_5        : in    std_logic := 'U';
          adc_interface_0_result_ch1_o_2        : in    std_logic := 'U';
          HALL_INTERFACE_1_omega_out_o          : in    std_logic_vector(17 downto 0) := (others => 'U');
          prdata_o_1_iv_0_0_11_2                : out   std_logic;
          prdata_o_1_iv_0_0_11_0                : out   std_logic;
          SPEED_ID_IQ_PI_0_iq_pi_output_o       : in    std_logic_vector(17 downto 0) := (others => 'U');
          prdata_o_1_0_iv_0_14_2                : out   std_logic;
          prdata_o_1_0_iv_0_14_0                : out   std_logic;
          prdata_o_1_0_iv_0_14_1                : out   std_logic;
          prdata_o_1_0_iv_0_14_4                : out   std_logic;
          prdata_o_1_0_iv_0_0_8_11              : out   std_logic;
          prdata_o_1_0_iv_0_9_12                : out   std_logic;
          prdata_o_1_0_iv_0_0_11                : out   std_logic_vector(15 to 15);
          prdata_o_1_0_iv_0_11                  : out   std_logic_vector(16 to 16);
          prdata_o_0_3                          : out   std_logic_vector(17 to 17);
          prdata_o_1_0_iv_0_15_0                : out   std_logic;
          prdata_o_1_0_iv_0_15_4                : out   std_logic;
          prdata_o_1_0_iv_0_15_2                : out   std_logic;
          prdata_o_1_0_iv_0_15_1                : out   std_logic;
          prdata_o_1_0_iv_0_0_14                : out   std_logic_vector(3 to 3);
          HALL_INTERFACE_1_angle_out_raw_o      : in    std_logic_vector(12 downto 0) := (others => 'U');
          prdata_o_1_0_iv_0_0_9_11              : out   std_logic;
          prdata_o_1_0_iv_0_0_9_12              : out   std_logic;
          prdata_o_1_0_iv_0_0_9_0               : out   std_logic;
          prdata_o_1_0_iv_0_0_10_0              : out   std_logic;
          prdata_o_1_0_iv_0_0_10_12             : out   std_logic;
          RATE_LIMITER_0_rl_out_o               : in    std_logic_vector(17 downto 0) := (others => 'U');
          prdata_o_1_iv_0_0_12_3                : out   std_logic;
          prdata_o_1_iv_0_0_12_0                : out   std_logic;
          prdata_o_1_iv_0_0_12_5                : out   std_logic;
          prdata_o_1_iv_0_0_16                  : out   std_logic_vector(9 downto 8);
          prdata_o_1_iv_0_16_0                  : out   std_logic;
          prdata_o_1_iv_0_16_5                  : out   std_logic;
          prdata_o_1_0_iv_0_16                  : out   std_logic_vector(2 downto 0);
          prdata_o_1_iv_0_0_13                  : out   std_logic_vector(7 to 7);
          MC_System_0_FIC_0_LOCK                : in    std_logic := 'U';
          MC_System_0_FIC_0_CLK                 : in    std_logic := 'U';
          apb3_en_if_1_stop_motor_o             : out   std_logic;
          apb3_en_if_1_start_motor_o            : out   std_logic;
          apb3_hall_if_0_hall_sensor_polarity_o : out   std_logic;
          apb3_en_if_1_fault_clr_o              : out   std_logic;
          apb3_en_if_0_direction_config_o       : out   std_logic;
          prdata_o276                           : out   std_logic;
          G_15_1                                : out   std_logic;
          N_730                                 : out   std_logic;
          N_748                                 : out   std_logic;
          prdata_o_1_iv_0_0_a3_27_out           : out   std_logic;
          prdata_o_1_iv_0_0_a3_9_out            : out   std_logic;
          N_737                                 : out   std_logic;
          N_759                                 : out   std_logic;
          N_705                                 : out   std_logic;
          prdata_o_1_iv_0_0_a3_0_out            : out   std_logic;
          N_734                                 : out   std_logic;
          N_745                                 : in    std_logic := 'U';
          prdata_m1_e_8_1                       : out   std_logic;
          prdata_m1_e_4_1                       : out   std_logic;
          prdata_m1_e_12_1                      : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PWRITE       : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_0_PENABLE      : in    std_logic := 'U';
          prdata_N_5_mux_6                      : out   std_logic;
          prdata_N_5_mux_7                      : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PSELx        : in    std_logic := 'U';
          N_358                                 : out   std_logic;
          N_634                                 : out   std_logic;
          N_462                                 : out   std_logic;
          N_449                                 : out   std_logic;
          N_442                                 : out   std_logic;
          N_440                                 : out   std_logic
        );
  end component;

    signal \FOC_TRANSFORMS_0_id_o_4\, \FOC_TRANSFORMS_0_iq_o_6\, 
        \FOC_TRANSFORMS_0_iq_o_9\, 
        \SPEED_ID_IQ_PI_0_id_pi_output_o_5\, 
        \SPEED_ID_IQ_PI_0_id_pi_output_o_6\, 
        \SPEED_ID_IQ_PI_0_id_pi_output_o_9\, 
        \SPEED_ID_IQ_PI_0_id_pi_output_o_11\, 
        \HALL_INTERFACE_1_theta_output_o_0\, 
        \HALL_INTERFACE_1_theta_output_o_1\, 
        \HALL_INTERFACE_1_theta_output_o_4\, 
        \HALL_INTERFACE_1_theta_output_o_6\, \OLMNG_0_theta_o_5\, 
        \OLMNG_0_theta_o_6\, \OLMNG_0_theta_o_9\, 
        \OLMNG_0_theta_o_11\, \FOC_TRANSFORMS_0_valpha_o_5\, 
        \FOC_TRANSFORMS_0_valpha_o_6\, 
        \FOC_TRANSFORMS_0_valpha_o_9\, 
        \FOC_TRANSFORMS_0_valpha_o_11\, 
        \adc_interface_0_result_ch1_o_4\, \A0_PWM_VL_O_c\
         : std_logic;
    signal FOC_TRANSFORMS_0_va_o : std_logic_vector(17 downto 0);
    signal FOC_TRANSFORMS_0_vb_o : std_logic_vector(17 downto 0);
    signal FOC_TRANSFORMS_0_vc_o : std_logic_vector(17 downto 0);
    signal SVM_0_va3h_o : std_logic_vector(17 downto 0);
    signal SVM_0_vb3h_o : std_logic_vector(17 downto 0);
    signal SVM_0_vc3h_o : std_logic_vector(17 downto 0);
    signal OLMNG_0_init_speedpi_o : 
        std_logic_vector(17 downto 0);
    signal OLMNG_0_init_iqpi_o : std_logic_vector(17 downto 0);
    signal RATE_LIMITER_0_rl_out_o : 
        std_logic_vector(17 downto 0);
    signal HALL_INTERFACE_1_omega_out_o : 
        std_logic_vector(17 downto 0);
    signal apb3_en_if_1_speed_pi_kp_o : 
        std_logic_vector(17 downto 0);
    signal apb3_en_if_1_speed_pi_ki_o : 
        std_logic_vector(17 downto 0);
    signal FOC_TRANSFORMS_0_id_o : std_logic_vector(17 downto 0);
    signal apb3_en_if_1_idq_pi_kp_o : 
        std_logic_vector(17 downto 0);
    signal apb3_en_if_1_idq_pi_ki_o : 
        std_logic_vector(17 downto 0);
    signal SPEED_ID_IQ_PI_0_speed_pi_output_o : 
        std_logic_vector(17 downto 0);
    signal FOC_TRANSFORMS_0_iq_o : std_logic_vector(17 downto 0);
    signal SPEED_ID_IQ_PI_0_id_pi_output_o : 
        std_logic_vector(17 downto 0);
    signal SPEED_ID_IQ_PI_0_iq_pi_output_o : 
        std_logic_vector(17 downto 0);
    signal apb3_en_if_1_seq_cntl_cl_omega_o : 
        std_logic_vector(17 downto 0);
    signal apb3_en_if_1_auto_restart_no_o : 
        std_logic_vector(3 downto 0);
    signal apb3_en_if_1_seq_cntl_config_o : 
        std_logic_vector(3 downto 0);
    signal SEQ_CONTROLLER_0_state_o : 
        std_logic_vector(3 downto 0);
    signal apb3_en_if_1_rate_limit_slew_cnt_o : 
        std_logic_vector(17 downto 0);
    signal apb3_en_if_1_rate_limit_rate_cnt_o : 
        std_logic_vector(17 downto 0);
    signal apb3_en_if_1_rate_limit_ref_in_o : 
        std_logic_vector(17 downto 0);
    signal apb3_en_if_1_pwm_period_val_o : 
        std_logic_vector(17 downto 0);
    signal apb3_en_if_1_pwm_gain_val_o : 
        std_logic_vector(17 downto 1);
    signal PWM_SCALING_0_Va_o : std_logic_vector(17 downto 0);
    signal PWM_SCALING_0_Vb_o : std_logic_vector(17 downto 0);
    signal PWM_SCALING_0_Vc_o : std_logic_vector(17 downto 0);
    signal apb3_en_if_1_pwm_dead_time_val_o : 
        std_logic_vector(17 downto 0);
    signal apb3_en_if_1_pwm_delay_time_val_o : 
        std_logic_vector(17 downto 0);
    signal apb3_en_if_1_olmng_theta_factor_o : 
        std_logic_vector(17 downto 0);
    signal apb3_en_if_1_olmng_dv_o : 
        std_logic_vector(17 downto 0);
    signal HALL_INTERFACE_1_theta_output_o : 
        std_logic_vector(17 downto 7);
    signal apb3_en_if_1_olmng_iq_ref_in_o : 
        std_logic_vector(17 downto 0);
    signal OLMNG_0_theta_o : std_logic_vector(17 downto 0);
    signal apb3_hall_if_0_hall_filter_factor_o : 
        std_logic_vector(3 downto 0);
    signal apb3_hall_if_0_hall_speed_factor_o : 
        std_logic_vector(17 downto 0);
    signal HALL_INTERFACE_1_angle_out_raw_o : 
        std_logic_vector(12 downto 0);
    signal angle_out_raw_o : std_logic_vector(17 downto 13);
    signal theta_output_o : std_logic_vector(4 downto 0);
    signal ADC_SCALING_0_ia_adc_o : 
        std_logic_vector(17 downto 0);
    signal ADC_SCALING_0_ib_adc_o : 
        std_logic_vector(17 downto 0);
    signal FOC_TRANSFORMS_0_ialpha_o : 
        std_logic_vector(17 downto 0);
    signal FOC_TRANSFORMS_0_ibeta_o : 
        std_logic_vector(17 downto 0);
    signal FOC_TRANSFORMS_0_valpha_o : 
        std_logic_vector(17 downto 0);
    signal FOC_TRANSFORMS_0_vbeta_o : 
        std_logic_vector(17 downto 0);
    signal apb3_en_if_1_adc_scale_val_o : 
        std_logic_vector(17 downto 0);
    signal adc_interface_0_result_ch0_o : 
        std_logic_vector(11 downto 0);
    signal adc_interface_0_result_ch1_o : 
        std_logic_vector(11 downto 0);
    signal apb3_en_if_1_adc_oc_thresh_o : 
        std_logic_vector(17 downto 0);
    signal apb3_en_if_1_adc_control_reg_val_o : 
        std_logic_vector(5 downto 0);
    signal adc_interface_0_result_ch2_o : 
        std_logic_vector(11 downto 0);
    signal adc_interface_0_result_ch3_o : 
        std_logic_vector(11 downto 0);
    signal apb3_en_if_1_adc_channel_ch2_o : 
        std_logic_vector(15 downto 0);
    signal apb3_en_if_1_adc_channel_ch0_o : 
        std_logic_vector(15 downto 0);
    signal apb3_en_if_1_adc_channel_ch1_o : 
        std_logic_vector(15 downto 0);
    signal apb3_en_if_1_adc_channel_ch3_o : 
        std_logic_vector(15 downto 0);
    signal FOC_TRANSFORMS_0_iclarke_done_o, SVM_0_done_o, 
        SEQ_CONTROLLER_0_motor_stopped_o, 
        SEQ_CONTROLLER_0_cl_status_o, 
        SEQ_CONTROLLER_0_en_idq_pi_o, RATE_LIMITER_0_rl_done_o, 
        SPEED_ID_IQ_PI_1_iq_pi_done_o, 
        FOC_TRANSFORMS_0_park_done_o, \GND\, \VCC\, 
        speed_pi_done_o, SPEED_ID_IQ_PI_1_id_pi_done_o, 
        ADC_SCALING_1_over_current_fault_o, 
        apb3_en_if_1_start_motor_o, apb3_en_if_1_stop_motor_o, 
        apb3_en_if_1_fault_clr_o, ADC_SCALING_0_calib_done_o, 
        PWM3PH_0_midmatch_o, PWM_SCALING_1_done_o, 
        SEQ_CONTROLLER_1_adc_start_o, SEQ_CONTROLLER_0_reset_rl_o, 
        SEQ_CONTROLLER_0_soft_stop_o, sensor_reset_o, 
        ADC_SCALING_0_done_o, apb3_en_if_0_direction_config_o, 
        PWM_AL_o, PWM_BL_o, PWM_CL_o, done_o, 
        apb3_hall_if_0_hall_sensor_polarity_o, omega_done_o, 
        FOC_TRANSFORMS_1_clarke_done_o_0, 
        FOC_TRANSFORMS_0_ipark_done_o, 
        adc_interface_0_results_rdy_o : std_logic;

    for all : PWM3PH
	Use entity work.PWM3PH(DEF_ARCH);
    for all : SVM
	Use entity work.SVM(DEF_ARCH);
    for all : ADC_SCALING
	Use entity work.ADC_SCALING(DEF_ARCH);
    for all : OLMNG
	Use entity work.OLMNG(DEF_ARCH);
    for all : RATE_LIMITER
	Use entity work.RATE_LIMITER(DEF_ARCH);
    for all : SPEED_ID_IQ_PI
	Use entity work.SPEED_ID_IQ_PI(DEF_ARCH);
    for all : SEQ_CONTROLLER
	Use entity work.SEQ_CONTROLLER(DEF_ARCH);
    for all : FOC_TRANSFORMS
	Use entity work.FOC_TRANSFORMS(DEF_ARCH);
    for all : adc_interface
	Use entity work.adc_interface(DEF_ARCH);
    for all : PWM_SCALING
	Use entity work.PWM_SCALING(DEF_ARCH);
    for all : HALL_INTERFACE
	Use entity work.HALL_INTERFACE(DEF_ARCH);
    for all : apb3_hall_if
	Use entity work.apb3_hall_if(DEF_ARCH);
begin 

    FOC_TRANSFORMS_0_id_o_4 <= \FOC_TRANSFORMS_0_id_o_4\;
    FOC_TRANSFORMS_0_iq_o_6 <= \FOC_TRANSFORMS_0_iq_o_6\;
    FOC_TRANSFORMS_0_iq_o_9 <= \FOC_TRANSFORMS_0_iq_o_9\;
    SPEED_ID_IQ_PI_0_id_pi_output_o_5 <= 
        \SPEED_ID_IQ_PI_0_id_pi_output_o_5\;
    SPEED_ID_IQ_PI_0_id_pi_output_o_6 <= 
        \SPEED_ID_IQ_PI_0_id_pi_output_o_6\;
    SPEED_ID_IQ_PI_0_id_pi_output_o_9 <= 
        \SPEED_ID_IQ_PI_0_id_pi_output_o_9\;
    SPEED_ID_IQ_PI_0_id_pi_output_o_11 <= 
        \SPEED_ID_IQ_PI_0_id_pi_output_o_11\;
    HALL_INTERFACE_1_theta_output_o_0 <= 
        \HALL_INTERFACE_1_theta_output_o_0\;
    HALL_INTERFACE_1_theta_output_o_1 <= 
        \HALL_INTERFACE_1_theta_output_o_1\;
    HALL_INTERFACE_1_theta_output_o_4 <= 
        \HALL_INTERFACE_1_theta_output_o_4\;
    HALL_INTERFACE_1_theta_output_o_6 <= 
        \HALL_INTERFACE_1_theta_output_o_6\;
    OLMNG_0_theta_o_5 <= \OLMNG_0_theta_o_5\;
    OLMNG_0_theta_o_6 <= \OLMNG_0_theta_o_6\;
    OLMNG_0_theta_o_9 <= \OLMNG_0_theta_o_9\;
    OLMNG_0_theta_o_11 <= \OLMNG_0_theta_o_11\;
    FOC_TRANSFORMS_0_valpha_o_5 <= \FOC_TRANSFORMS_0_valpha_o_5\;
    FOC_TRANSFORMS_0_valpha_o_6 <= \FOC_TRANSFORMS_0_valpha_o_6\;
    FOC_TRANSFORMS_0_valpha_o_9 <= \FOC_TRANSFORMS_0_valpha_o_9\;
    FOC_TRANSFORMS_0_valpha_o_11 <= 
        \FOC_TRANSFORMS_0_valpha_o_11\;
    adc_interface_0_result_ch1_o_4 <= 
        \adc_interface_0_result_ch1_o_4\;
    A0_PWM_VL_O_c <= \A0_PWM_VL_O_c\;

    MSC_i_27 : PWM3PH
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FIC_0_CLK, en_pwm_i => \A0_PWM_VL_O_c\, 
        en_dual_trig_i => \GND\, va_i(17) => 
        PWM_SCALING_0_Va_o(17), va_i(16) => 
        PWM_SCALING_0_Va_o(16), va_i(15) => 
        PWM_SCALING_0_Va_o(15), va_i(14) => 
        PWM_SCALING_0_Va_o(14), va_i(13) => 
        PWM_SCALING_0_Va_o(13), va_i(12) => 
        PWM_SCALING_0_Va_o(12), va_i(11) => 
        PWM_SCALING_0_Va_o(11), va_i(10) => 
        PWM_SCALING_0_Va_o(10), va_i(9) => PWM_SCALING_0_Va_o(9), 
        va_i(8) => PWM_SCALING_0_Va_o(8), va_i(7) => 
        PWM_SCALING_0_Va_o(7), va_i(6) => PWM_SCALING_0_Va_o(6), 
        va_i(5) => PWM_SCALING_0_Va_o(5), va_i(4) => 
        PWM_SCALING_0_Va_o(4), va_i(3) => PWM_SCALING_0_Va_o(3), 
        va_i(2) => PWM_SCALING_0_Va_o(2), va_i(1) => 
        PWM_SCALING_0_Va_o(1), va_i(0) => PWM_SCALING_0_Va_o(0), 
        vb_i(17) => PWM_SCALING_0_Vb_o(17), vb_i(16) => 
        PWM_SCALING_0_Vb_o(16), vb_i(15) => 
        PWM_SCALING_0_Vb_o(15), vb_i(14) => 
        PWM_SCALING_0_Vb_o(14), vb_i(13) => 
        PWM_SCALING_0_Vb_o(13), vb_i(12) => 
        PWM_SCALING_0_Vb_o(12), vb_i(11) => 
        PWM_SCALING_0_Vb_o(11), vb_i(10) => 
        PWM_SCALING_0_Vb_o(10), vb_i(9) => PWM_SCALING_0_Vb_o(9), 
        vb_i(8) => PWM_SCALING_0_Vb_o(8), vb_i(7) => 
        PWM_SCALING_0_Vb_o(7), vb_i(6) => PWM_SCALING_0_Vb_o(6), 
        vb_i(5) => PWM_SCALING_0_Vb_o(5), vb_i(4) => 
        PWM_SCALING_0_Vb_o(4), vb_i(3) => PWM_SCALING_0_Vb_o(3), 
        vb_i(2) => PWM_SCALING_0_Vb_o(2), vb_i(1) => 
        PWM_SCALING_0_Vb_o(1), vb_i(0) => PWM_SCALING_0_Vb_o(0), 
        vc_i(17) => PWM_SCALING_0_Vc_o(17), vc_i(16) => 
        PWM_SCALING_0_Vc_o(16), vc_i(15) => 
        PWM_SCALING_0_Vc_o(15), vc_i(14) => 
        PWM_SCALING_0_Vc_o(14), vc_i(13) => 
        PWM_SCALING_0_Vc_o(13), vc_i(12) => 
        PWM_SCALING_0_Vc_o(12), vc_i(11) => 
        PWM_SCALING_0_Vc_o(11), vc_i(10) => 
        PWM_SCALING_0_Vc_o(10), vc_i(9) => PWM_SCALING_0_Vc_o(9), 
        vc_i(8) => PWM_SCALING_0_Vc_o(8), vc_i(7) => 
        PWM_SCALING_0_Vc_o(7), vc_i(6) => PWM_SCALING_0_Vc_o(6), 
        vc_i(5) => PWM_SCALING_0_Vc_o(5), vc_i(4) => 
        PWM_SCALING_0_Vc_o(4), vc_i(3) => PWM_SCALING_0_Vc_o(3), 
        vc_i(2) => PWM_SCALING_0_Vc_o(2), vc_i(1) => 
        PWM_SCALING_0_Vc_o(1), vc_i(0) => PWM_SCALING_0_Vc_o(0), 
        pwm_period_i(17) => apb3_en_if_1_pwm_period_val_o(17), 
        pwm_period_i(16) => apb3_en_if_1_pwm_period_val_o(16), 
        pwm_period_i(15) => apb3_en_if_1_pwm_period_val_o(15), 
        pwm_period_i(14) => apb3_en_if_1_pwm_period_val_o(14), 
        pwm_period_i(13) => apb3_en_if_1_pwm_period_val_o(13), 
        pwm_period_i(12) => apb3_en_if_1_pwm_period_val_o(12), 
        pwm_period_i(11) => apb3_en_if_1_pwm_period_val_o(11), 
        pwm_period_i(10) => apb3_en_if_1_pwm_period_val_o(10), 
        pwm_period_i(9) => apb3_en_if_1_pwm_period_val_o(9), 
        pwm_period_i(8) => apb3_en_if_1_pwm_period_val_o(8), 
        pwm_period_i(7) => apb3_en_if_1_pwm_period_val_o(7), 
        pwm_period_i(6) => apb3_en_if_1_pwm_period_val_o(6), 
        pwm_period_i(5) => apb3_en_if_1_pwm_period_val_o(5), 
        pwm_period_i(4) => apb3_en_if_1_pwm_period_val_o(4), 
        pwm_period_i(3) => apb3_en_if_1_pwm_period_val_o(3), 
        pwm_period_i(2) => apb3_en_if_1_pwm_period_val_o(2), 
        pwm_period_i(1) => apb3_en_if_1_pwm_period_val_o(1), 
        pwm_period_i(0) => apb3_en_if_1_pwm_period_val_o(0), 
        dead_time_i(17) => apb3_en_if_1_pwm_dead_time_val_o(17), 
        dead_time_i(16) => apb3_en_if_1_pwm_dead_time_val_o(16), 
        dead_time_i(15) => apb3_en_if_1_pwm_dead_time_val_o(15), 
        dead_time_i(14) => apb3_en_if_1_pwm_dead_time_val_o(14), 
        dead_time_i(13) => apb3_en_if_1_pwm_dead_time_val_o(13), 
        dead_time_i(12) => apb3_en_if_1_pwm_dead_time_val_o(12), 
        dead_time_i(11) => apb3_en_if_1_pwm_dead_time_val_o(11), 
        dead_time_i(10) => apb3_en_if_1_pwm_dead_time_val_o(10), 
        dead_time_i(9) => apb3_en_if_1_pwm_dead_time_val_o(9), 
        dead_time_i(8) => apb3_en_if_1_pwm_dead_time_val_o(8), 
        dead_time_i(7) => apb3_en_if_1_pwm_dead_time_val_o(7), 
        dead_time_i(6) => apb3_en_if_1_pwm_dead_time_val_o(6), 
        dead_time_i(5) => apb3_en_if_1_pwm_dead_time_val_o(5), 
        dead_time_i(4) => apb3_en_if_1_pwm_dead_time_val_o(4), 
        dead_time_i(3) => apb3_en_if_1_pwm_dead_time_val_o(3), 
        dead_time_i(2) => apb3_en_if_1_pwm_dead_time_val_o(2), 
        dead_time_i(1) => apb3_en_if_1_pwm_dead_time_val_o(1), 
        dead_time_i(0) => apb3_en_if_1_pwm_dead_time_val_o(0), 
        delay_time_i(17) => apb3_en_if_1_pwm_delay_time_val_o(17), 
        delay_time_i(16) => apb3_en_if_1_pwm_delay_time_val_o(16), 
        delay_time_i(15) => apb3_en_if_1_pwm_delay_time_val_o(15), 
        delay_time_i(14) => apb3_en_if_1_pwm_delay_time_val_o(14), 
        delay_time_i(13) => apb3_en_if_1_pwm_delay_time_val_o(13), 
        delay_time_i(12) => apb3_en_if_1_pwm_delay_time_val_o(12), 
        delay_time_i(11) => apb3_en_if_1_pwm_delay_time_val_o(11), 
        delay_time_i(10) => apb3_en_if_1_pwm_delay_time_val_o(10), 
        delay_time_i(9) => apb3_en_if_1_pwm_delay_time_val_o(9), 
        delay_time_i(8) => apb3_en_if_1_pwm_delay_time_val_o(8), 
        delay_time_i(7) => apb3_en_if_1_pwm_delay_time_val_o(7), 
        delay_time_i(6) => apb3_en_if_1_pwm_delay_time_val_o(6), 
        delay_time_i(5) => apb3_en_if_1_pwm_delay_time_val_o(5), 
        delay_time_i(4) => apb3_en_if_1_pwm_delay_time_val_o(4), 
        delay_time_i(3) => apb3_en_if_1_pwm_delay_time_val_o(3), 
        delay_time_i(2) => apb3_en_if_1_pwm_delay_time_val_o(2), 
        delay_time_i(1) => apb3_en_if_1_pwm_delay_time_val_o(1), 
        delay_time_i(0) => apb3_en_if_1_pwm_delay_time_val_o(0), 
        midmatch_o => PWM3PH_0_midmatch_o, PWM_AH_o => 
        A0_PWM_UH_O_c, PWM_BH_o => A0_PWM_VH_O_c, PWM_CH_o => 
        A0_PWM_WH_O_c, PWM_AL_o => PWM_AL_o, PWM_BL_o => PWM_BL_o, 
        PWM_CL_o => PWM_CL_o);
    
    MSC_i_0 : SVM
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FIC_0_CLK, start_i => 
        FOC_TRANSFORMS_0_iclarke_done_o, va_i(17) => 
        FOC_TRANSFORMS_0_va_o(17), va_i(16) => 
        FOC_TRANSFORMS_0_va_o(16), va_i(15) => 
        FOC_TRANSFORMS_0_va_o(15), va_i(14) => 
        FOC_TRANSFORMS_0_va_o(14), va_i(13) => 
        FOC_TRANSFORMS_0_va_o(13), va_i(12) => 
        FOC_TRANSFORMS_0_va_o(12), va_i(11) => 
        FOC_TRANSFORMS_0_va_o(11), va_i(10) => 
        FOC_TRANSFORMS_0_va_o(10), va_i(9) => 
        FOC_TRANSFORMS_0_va_o(9), va_i(8) => 
        FOC_TRANSFORMS_0_va_o(8), va_i(7) => 
        FOC_TRANSFORMS_0_va_o(7), va_i(6) => 
        FOC_TRANSFORMS_0_va_o(6), va_i(5) => 
        FOC_TRANSFORMS_0_va_o(5), va_i(4) => 
        FOC_TRANSFORMS_0_va_o(4), va_i(3) => 
        FOC_TRANSFORMS_0_va_o(3), va_i(2) => 
        FOC_TRANSFORMS_0_va_o(2), va_i(1) => 
        FOC_TRANSFORMS_0_va_o(1), va_i(0) => 
        FOC_TRANSFORMS_0_va_o(0), vb_i(17) => 
        FOC_TRANSFORMS_0_vb_o(17), vb_i(16) => 
        FOC_TRANSFORMS_0_vb_o(16), vb_i(15) => 
        FOC_TRANSFORMS_0_vb_o(15), vb_i(14) => 
        FOC_TRANSFORMS_0_vb_o(14), vb_i(13) => 
        FOC_TRANSFORMS_0_vb_o(13), vb_i(12) => 
        FOC_TRANSFORMS_0_vb_o(12), vb_i(11) => 
        FOC_TRANSFORMS_0_vb_o(11), vb_i(10) => 
        FOC_TRANSFORMS_0_vb_o(10), vb_i(9) => 
        FOC_TRANSFORMS_0_vb_o(9), vb_i(8) => 
        FOC_TRANSFORMS_0_vb_o(8), vb_i(7) => 
        FOC_TRANSFORMS_0_vb_o(7), vb_i(6) => 
        FOC_TRANSFORMS_0_vb_o(6), vb_i(5) => 
        FOC_TRANSFORMS_0_vb_o(5), vb_i(4) => 
        FOC_TRANSFORMS_0_vb_o(4), vb_i(3) => 
        FOC_TRANSFORMS_0_vb_o(3), vb_i(2) => 
        FOC_TRANSFORMS_0_vb_o(2), vb_i(1) => 
        FOC_TRANSFORMS_0_vb_o(1), vb_i(0) => 
        FOC_TRANSFORMS_0_vb_o(0), vc_i(17) => 
        FOC_TRANSFORMS_0_vc_o(17), vc_i(16) => 
        FOC_TRANSFORMS_0_vc_o(16), vc_i(15) => 
        FOC_TRANSFORMS_0_vc_o(15), vc_i(14) => 
        FOC_TRANSFORMS_0_vc_o(14), vc_i(13) => 
        FOC_TRANSFORMS_0_vc_o(13), vc_i(12) => 
        FOC_TRANSFORMS_0_vc_o(12), vc_i(11) => 
        FOC_TRANSFORMS_0_vc_o(11), vc_i(10) => 
        FOC_TRANSFORMS_0_vc_o(10), vc_i(9) => 
        FOC_TRANSFORMS_0_vc_o(9), vc_i(8) => 
        FOC_TRANSFORMS_0_vc_o(8), vc_i(7) => 
        FOC_TRANSFORMS_0_vc_o(7), vc_i(6) => 
        FOC_TRANSFORMS_0_vc_o(6), vc_i(5) => 
        FOC_TRANSFORMS_0_vc_o(5), vc_i(4) => 
        FOC_TRANSFORMS_0_vc_o(4), vc_i(3) => 
        FOC_TRANSFORMS_0_vc_o(3), vc_i(2) => 
        FOC_TRANSFORMS_0_vc_o(2), vc_i(1) => 
        FOC_TRANSFORMS_0_vc_o(1), vc_i(0) => 
        FOC_TRANSFORMS_0_vc_o(0), va3h_o(17) => SVM_0_va3h_o(17), 
        va3h_o(16) => SVM_0_va3h_o(16), va3h_o(15) => 
        SVM_0_va3h_o(15), va3h_o(14) => SVM_0_va3h_o(14), 
        va3h_o(13) => SVM_0_va3h_o(13), va3h_o(12) => 
        SVM_0_va3h_o(12), va3h_o(11) => SVM_0_va3h_o(11), 
        va3h_o(10) => SVM_0_va3h_o(10), va3h_o(9) => 
        SVM_0_va3h_o(9), va3h_o(8) => SVM_0_va3h_o(8), va3h_o(7)
         => SVM_0_va3h_o(7), va3h_o(6) => SVM_0_va3h_o(6), 
        va3h_o(5) => SVM_0_va3h_o(5), va3h_o(4) => 
        SVM_0_va3h_o(4), va3h_o(3) => SVM_0_va3h_o(3), va3h_o(2)
         => SVM_0_va3h_o(2), va3h_o(1) => SVM_0_va3h_o(1), 
        va3h_o(0) => SVM_0_va3h_o(0), vb3h_o(17) => 
        SVM_0_vb3h_o(17), vb3h_o(16) => SVM_0_vb3h_o(16), 
        vb3h_o(15) => SVM_0_vb3h_o(15), vb3h_o(14) => 
        SVM_0_vb3h_o(14), vb3h_o(13) => SVM_0_vb3h_o(13), 
        vb3h_o(12) => SVM_0_vb3h_o(12), vb3h_o(11) => 
        SVM_0_vb3h_o(11), vb3h_o(10) => SVM_0_vb3h_o(10), 
        vb3h_o(9) => SVM_0_vb3h_o(9), vb3h_o(8) => 
        SVM_0_vb3h_o(8), vb3h_o(7) => SVM_0_vb3h_o(7), vb3h_o(6)
         => SVM_0_vb3h_o(6), vb3h_o(5) => SVM_0_vb3h_o(5), 
        vb3h_o(4) => SVM_0_vb3h_o(4), vb3h_o(3) => 
        SVM_0_vb3h_o(3), vb3h_o(2) => SVM_0_vb3h_o(2), vb3h_o(1)
         => SVM_0_vb3h_o(1), vb3h_o(0) => SVM_0_vb3h_o(0), 
        vc3h_o(17) => SVM_0_vc3h_o(17), vc3h_o(16) => 
        SVM_0_vc3h_o(16), vc3h_o(15) => SVM_0_vc3h_o(15), 
        vc3h_o(14) => SVM_0_vc3h_o(14), vc3h_o(13) => 
        SVM_0_vc3h_o(13), vc3h_o(12) => SVM_0_vc3h_o(12), 
        vc3h_o(11) => SVM_0_vc3h_o(11), vc3h_o(10) => 
        SVM_0_vc3h_o(10), vc3h_o(9) => SVM_0_vc3h_o(9), vc3h_o(8)
         => SVM_0_vc3h_o(8), vc3h_o(7) => SVM_0_vc3h_o(7), 
        vc3h_o(6) => SVM_0_vc3h_o(6), vc3h_o(5) => 
        SVM_0_vc3h_o(5), vc3h_o(4) => SVM_0_vc3h_o(4), vc3h_o(3)
         => SVM_0_vc3h_o(3), vc3h_o(2) => SVM_0_vc3h_o(2), 
        vc3h_o(1) => SVM_0_vc3h_o(1), vc3h_o(0) => 
        SVM_0_vc3h_o(0), done_o => SVM_0_done_o);
    
    GND_Z : GND
      port map(Y => \GND\);
    
    MSC_i_19 : ADC_SCALING
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FIC_0_CLK, adc_results_rdy_i => 
        adc_interface_0_results_rdy_o, adc_scale_val_i(17) => 
        apb3_en_if_1_adc_scale_val_o(17), adc_scale_val_i(16) => 
        apb3_en_if_1_adc_scale_val_o(16), adc_scale_val_i(15) => 
        apb3_en_if_1_adc_scale_val_o(15), adc_scale_val_i(14) => 
        apb3_en_if_1_adc_scale_val_o(14), adc_scale_val_i(13) => 
        apb3_en_if_1_adc_scale_val_o(13), adc_scale_val_i(12) => 
        apb3_en_if_1_adc_scale_val_o(12), adc_scale_val_i(11) => 
        apb3_en_if_1_adc_scale_val_o(11), adc_scale_val_i(10) => 
        apb3_en_if_1_adc_scale_val_o(10), adc_scale_val_i(9) => 
        apb3_en_if_1_adc_scale_val_o(9), adc_scale_val_i(8) => 
        apb3_en_if_1_adc_scale_val_o(8), adc_scale_val_i(7) => 
        apb3_en_if_1_adc_scale_val_o(7), adc_scale_val_i(6) => 
        apb3_en_if_1_adc_scale_val_o(6), adc_scale_val_i(5) => 
        apb3_en_if_1_adc_scale_val_o(5), adc_scale_val_i(4) => 
        apb3_en_if_1_adc_scale_val_o(4), adc_scale_val_i(3) => 
        apb3_en_if_1_adc_scale_val_o(3), adc_scale_val_i(2) => 
        apb3_en_if_1_adc_scale_val_o(2), adc_scale_val_i(1) => 
        apb3_en_if_1_adc_scale_val_o(1), adc_scale_val_i(0) => 
        apb3_en_if_1_adc_scale_val_o(0), adc_result_ch0_i(11) => 
        adc_interface_0_result_ch0_o(11), adc_result_ch0_i(10)
         => adc_interface_0_result_ch0_o(10), adc_result_ch0_i(9)
         => adc_interface_0_result_ch0_o(9), adc_result_ch0_i(8)
         => adc_interface_0_result_ch0_o(8), adc_result_ch0_i(7)
         => adc_interface_0_result_ch0_o(7), adc_result_ch0_i(6)
         => adc_interface_0_result_ch0_o(6), adc_result_ch0_i(5)
         => adc_interface_0_result_ch0_o(5), adc_result_ch0_i(4)
         => adc_interface_0_result_ch0_o(4), adc_result_ch0_i(3)
         => adc_interface_0_result_ch0_o(3), adc_result_ch0_i(2)
         => adc_interface_0_result_ch0_o(2), adc_result_ch0_i(1)
         => adc_interface_0_result_ch0_o(1), adc_result_ch0_i(0)
         => adc_interface_0_result_ch0_o(0), adc_result_ch1_i(11)
         => adc_interface_0_result_ch1_o(11), 
        adc_result_ch1_i(10) => adc_interface_0_result_ch1_o(10), 
        adc_result_ch1_i(9) => adc_interface_0_result_ch1_o(9), 
        adc_result_ch1_i(8) => adc_interface_0_result_ch1_o(8), 
        adc_result_ch1_i(7) => adc_interface_0_result_ch1_o(7), 
        adc_result_ch1_i(6) => adc_interface_0_result_ch1_o(6), 
        adc_result_ch1_i(5) => adc_interface_0_result_ch1_o(5), 
        adc_result_ch1_i(4) => \adc_interface_0_result_ch1_o_4\, 
        adc_result_ch1_i(3) => adc_interface_0_result_ch1_o(3), 
        adc_result_ch1_i(2) => adc_interface_0_result_ch1_o(2), 
        adc_result_ch1_i(1) => adc_interface_0_result_ch1_o(1), 
        adc_result_ch1_i(0) => adc_interface_0_result_ch1_o(0), 
        fault_threshold_i(17) => apb3_en_if_1_adc_oc_thresh_o(17), 
        fault_threshold_i(16) => apb3_en_if_1_adc_oc_thresh_o(16), 
        fault_threshold_i(15) => apb3_en_if_1_adc_oc_thresh_o(15), 
        fault_threshold_i(14) => apb3_en_if_1_adc_oc_thresh_o(14), 
        fault_threshold_i(13) => apb3_en_if_1_adc_oc_thresh_o(13), 
        fault_threshold_i(12) => apb3_en_if_1_adc_oc_thresh_o(12), 
        fault_threshold_i(11) => apb3_en_if_1_adc_oc_thresh_o(11), 
        fault_threshold_i(10) => apb3_en_if_1_adc_oc_thresh_o(10), 
        fault_threshold_i(9) => apb3_en_if_1_adc_oc_thresh_o(9), 
        fault_threshold_i(8) => apb3_en_if_1_adc_oc_thresh_o(8), 
        fault_threshold_i(7) => apb3_en_if_1_adc_oc_thresh_o(7), 
        fault_threshold_i(6) => apb3_en_if_1_adc_oc_thresh_o(6), 
        fault_threshold_i(5) => apb3_en_if_1_adc_oc_thresh_o(5), 
        fault_threshold_i(4) => apb3_en_if_1_adc_oc_thresh_o(4), 
        fault_threshold_i(3) => apb3_en_if_1_adc_oc_thresh_o(3), 
        fault_threshold_i(2) => apb3_en_if_1_adc_oc_thresh_o(2), 
        fault_threshold_i(1) => apb3_en_if_1_adc_oc_thresh_o(1), 
        fault_threshold_i(0) => apb3_en_if_1_adc_oc_thresh_o(0), 
        done_o => ADC_SCALING_0_done_o, calib_done_o => 
        ADC_SCALING_0_calib_done_o, over_current_fault_o => 
        ADC_SCALING_1_over_current_fault_o, ia_adc_o(17) => 
        ADC_SCALING_0_ia_adc_o(17), ia_adc_o(16) => 
        ADC_SCALING_0_ia_adc_o(16), ia_adc_o(15) => 
        ADC_SCALING_0_ia_adc_o(15), ia_adc_o(14) => 
        ADC_SCALING_0_ia_adc_o(14), ia_adc_o(13) => 
        ADC_SCALING_0_ia_adc_o(13), ia_adc_o(12) => 
        ADC_SCALING_0_ia_adc_o(12), ia_adc_o(11) => 
        ADC_SCALING_0_ia_adc_o(11), ia_adc_o(10) => 
        ADC_SCALING_0_ia_adc_o(10), ia_adc_o(9) => 
        ADC_SCALING_0_ia_adc_o(9), ia_adc_o(8) => 
        ADC_SCALING_0_ia_adc_o(8), ia_adc_o(7) => 
        ADC_SCALING_0_ia_adc_o(7), ia_adc_o(6) => 
        ADC_SCALING_0_ia_adc_o(6), ia_adc_o(5) => 
        ADC_SCALING_0_ia_adc_o(5), ia_adc_o(4) => 
        ADC_SCALING_0_ia_adc_o(4), ia_adc_o(3) => 
        ADC_SCALING_0_ia_adc_o(3), ia_adc_o(2) => 
        ADC_SCALING_0_ia_adc_o(2), ia_adc_o(1) => 
        ADC_SCALING_0_ia_adc_o(1), ia_adc_o(0) => 
        ADC_SCALING_0_ia_adc_o(0), ib_adc_o(17) => 
        ADC_SCALING_0_ib_adc_o(17), ib_adc_o(16) => 
        ADC_SCALING_0_ib_adc_o(16), ib_adc_o(15) => 
        ADC_SCALING_0_ib_adc_o(15), ib_adc_o(14) => 
        ADC_SCALING_0_ib_adc_o(14), ib_adc_o(13) => 
        ADC_SCALING_0_ib_adc_o(13), ib_adc_o(12) => 
        ADC_SCALING_0_ib_adc_o(12), ib_adc_o(11) => 
        ADC_SCALING_0_ib_adc_o(11), ib_adc_o(10) => 
        ADC_SCALING_0_ib_adc_o(10), ib_adc_o(9) => 
        ADC_SCALING_0_ib_adc_o(9), ib_adc_o(8) => 
        ADC_SCALING_0_ib_adc_o(8), ib_adc_o(7) => 
        ADC_SCALING_0_ib_adc_o(7), ib_adc_o(6) => 
        ADC_SCALING_0_ib_adc_o(6), ib_adc_o(5) => 
        ADC_SCALING_0_ib_adc_o(5), ib_adc_o(4) => 
        ADC_SCALING_0_ib_adc_o(4), ib_adc_o(3) => 
        ADC_SCALING_0_ib_adc_o(3), ib_adc_o(2) => 
        ADC_SCALING_0_ib_adc_o(2), ib_adc_o(1) => 
        ADC_SCALING_0_ib_adc_o(1), ib_adc_o(0) => 
        ADC_SCALING_0_ib_adc_o(0));
    
    MSC_i_12 : OLMNG
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FIC_0_CLK, start_i => 
        RATE_LIMITER_0_rl_done_o, clear_buffer_i => 
        SEQ_CONTROLLER_0_motor_stopped_o, direction_config_i => 
        apb3_en_if_0_direction_config_o, cl_status_i => 
        SEQ_CONTROLLER_0_cl_status_o, theta_factor_i(17) => 
        apb3_en_if_1_olmng_theta_factor_o(17), theta_factor_i(16)
         => apb3_en_if_1_olmng_theta_factor_o(16), 
        theta_factor_i(15) => 
        apb3_en_if_1_olmng_theta_factor_o(15), theta_factor_i(14)
         => apb3_en_if_1_olmng_theta_factor_o(14), 
        theta_factor_i(13) => 
        apb3_en_if_1_olmng_theta_factor_o(13), theta_factor_i(12)
         => apb3_en_if_1_olmng_theta_factor_o(12), 
        theta_factor_i(11) => 
        apb3_en_if_1_olmng_theta_factor_o(11), theta_factor_i(10)
         => apb3_en_if_1_olmng_theta_factor_o(10), 
        theta_factor_i(9) => apb3_en_if_1_olmng_theta_factor_o(9), 
        theta_factor_i(8) => apb3_en_if_1_olmng_theta_factor_o(8), 
        theta_factor_i(7) => apb3_en_if_1_olmng_theta_factor_o(7), 
        theta_factor_i(6) => apb3_en_if_1_olmng_theta_factor_o(6), 
        theta_factor_i(5) => apb3_en_if_1_olmng_theta_factor_o(5), 
        theta_factor_i(4) => apb3_en_if_1_olmng_theta_factor_o(4), 
        theta_factor_i(3) => apb3_en_if_1_olmng_theta_factor_o(3), 
        theta_factor_i(2) => apb3_en_if_1_olmng_theta_factor_o(2), 
        theta_factor_i(1) => apb3_en_if_1_olmng_theta_factor_o(1), 
        theta_factor_i(0) => apb3_en_if_1_olmng_theta_factor_o(0), 
        speed_ref_i(17) => RATE_LIMITER_0_rl_out_o(17), 
        speed_ref_i(16) => RATE_LIMITER_0_rl_out_o(16), 
        speed_ref_i(15) => RATE_LIMITER_0_rl_out_o(15), 
        speed_ref_i(14) => RATE_LIMITER_0_rl_out_o(14), 
        speed_ref_i(13) => RATE_LIMITER_0_rl_out_o(13), 
        speed_ref_i(12) => RATE_LIMITER_0_rl_out_o(12), 
        speed_ref_i(11) => RATE_LIMITER_0_rl_out_o(11), 
        speed_ref_i(10) => RATE_LIMITER_0_rl_out_o(10), 
        speed_ref_i(9) => RATE_LIMITER_0_rl_out_o(9), 
        speed_ref_i(8) => RATE_LIMITER_0_rl_out_o(8), 
        speed_ref_i(7) => RATE_LIMITER_0_rl_out_o(7), 
        speed_ref_i(6) => RATE_LIMITER_0_rl_out_o(6), 
        speed_ref_i(5) => RATE_LIMITER_0_rl_out_o(5), 
        speed_ref_i(4) => RATE_LIMITER_0_rl_out_o(4), 
        speed_ref_i(3) => RATE_LIMITER_0_rl_out_o(3), 
        speed_ref_i(2) => RATE_LIMITER_0_rl_out_o(2), 
        speed_ref_i(1) => RATE_LIMITER_0_rl_out_o(1), 
        speed_ref_i(0) => RATE_LIMITER_0_rl_out_o(0), dv_i(17)
         => apb3_en_if_1_olmng_dv_o(17), dv_i(16) => 
        apb3_en_if_1_olmng_dv_o(16), dv_i(15) => 
        apb3_en_if_1_olmng_dv_o(15), dv_i(14) => 
        apb3_en_if_1_olmng_dv_o(14), dv_i(13) => 
        apb3_en_if_1_olmng_dv_o(13), dv_i(12) => 
        apb3_en_if_1_olmng_dv_o(12), dv_i(11) => 
        apb3_en_if_1_olmng_dv_o(11), dv_i(10) => 
        apb3_en_if_1_olmng_dv_o(10), dv_i(9) => 
        apb3_en_if_1_olmng_dv_o(9), dv_i(8) => 
        apb3_en_if_1_olmng_dv_o(8), dv_i(7) => 
        apb3_en_if_1_olmng_dv_o(7), dv_i(6) => 
        apb3_en_if_1_olmng_dv_o(6), dv_i(5) => 
        apb3_en_if_1_olmng_dv_o(5), dv_i(4) => 
        apb3_en_if_1_olmng_dv_o(4), dv_i(3) => 
        apb3_en_if_1_olmng_dv_o(3), dv_i(2) => 
        apb3_en_if_1_olmng_dv_o(2), dv_i(1) => 
        apb3_en_if_1_olmng_dv_o(1), dv_i(0) => 
        apb3_en_if_1_olmng_dv_o(0), theta_cl_i(17) => 
        HALL_INTERFACE_1_theta_output_o(17), theta_cl_i(16) => 
        HALL_INTERFACE_1_theta_output_o(16), theta_cl_i(15) => 
        HALL_INTERFACE_1_theta_output_o(15), theta_cl_i(14) => 
        HALL_INTERFACE_1_theta_output_o(14), theta_cl_i(13) => 
        HALL_INTERFACE_1_theta_output_o(13), theta_cl_i(12) => 
        HALL_INTERFACE_1_theta_output_o(12), theta_cl_i(11) => 
        \HALL_INTERFACE_1_theta_output_o_6\, theta_cl_i(10) => 
        HALL_INTERFACE_1_theta_output_o(10), theta_cl_i(9) => 
        \HALL_INTERFACE_1_theta_output_o_4\, theta_cl_i(8) => 
        HALL_INTERFACE_1_theta_output_o(8), theta_cl_i(7) => 
        HALL_INTERFACE_1_theta_output_o(7), theta_cl_i(6) => 
        \HALL_INTERFACE_1_theta_output_o_1\, theta_cl_i(5) => 
        \HALL_INTERFACE_1_theta_output_o_0\, theta_cl_i(4) => 
        \GND\, theta_cl_i(3) => \GND\, theta_cl_i(2) => \GND\, 
        theta_cl_i(1) => \GND\, theta_cl_i(0) => \GND\, 
        iq_ref_in_i(17) => apb3_en_if_1_olmng_iq_ref_in_o(17), 
        iq_ref_in_i(16) => apb3_en_if_1_olmng_iq_ref_in_o(16), 
        iq_ref_in_i(15) => apb3_en_if_1_olmng_iq_ref_in_o(15), 
        iq_ref_in_i(14) => apb3_en_if_1_olmng_iq_ref_in_o(14), 
        iq_ref_in_i(13) => apb3_en_if_1_olmng_iq_ref_in_o(13), 
        iq_ref_in_i(12) => apb3_en_if_1_olmng_iq_ref_in_o(12), 
        iq_ref_in_i(11) => apb3_en_if_1_olmng_iq_ref_in_o(11), 
        iq_ref_in_i(10) => apb3_en_if_1_olmng_iq_ref_in_o(10), 
        iq_ref_in_i(9) => apb3_en_if_1_olmng_iq_ref_in_o(9), 
        iq_ref_in_i(8) => apb3_en_if_1_olmng_iq_ref_in_o(8), 
        iq_ref_in_i(7) => apb3_en_if_1_olmng_iq_ref_in_o(7), 
        iq_ref_in_i(6) => apb3_en_if_1_olmng_iq_ref_in_o(6), 
        iq_ref_in_i(5) => apb3_en_if_1_olmng_iq_ref_in_o(5), 
        iq_ref_in_i(4) => apb3_en_if_1_olmng_iq_ref_in_o(4), 
        iq_ref_in_i(3) => apb3_en_if_1_olmng_iq_ref_in_o(3), 
        iq_ref_in_i(2) => apb3_en_if_1_olmng_iq_ref_in_o(2), 
        iq_ref_in_i(1) => apb3_en_if_1_olmng_iq_ref_in_o(1), 
        iq_ref_in_i(0) => apb3_en_if_1_olmng_iq_ref_in_o(0), 
        done_o => done_o, theta_o(17) => OLMNG_0_theta_o(17), 
        theta_o(16) => OLMNG_0_theta_o(16), theta_o(15) => 
        OLMNG_0_theta_o(15), theta_o(14) => OLMNG_0_theta_o(14), 
        theta_o(13) => OLMNG_0_theta_o(13), theta_o(12) => 
        OLMNG_0_theta_o(12), theta_o(11) => \OLMNG_0_theta_o_11\, 
        theta_o(10) => OLMNG_0_theta_o(10), theta_o(9) => 
        \OLMNG_0_theta_o_9\, theta_o(8) => OLMNG_0_theta_o(8), 
        theta_o(7) => OLMNG_0_theta_o(7), theta_o(6) => 
        \OLMNG_0_theta_o_6\, theta_o(5) => \OLMNG_0_theta_o_5\, 
        theta_o(4) => OLMNG_0_theta_o(4), theta_o(3) => 
        OLMNG_0_theta_o(3), theta_o(2) => OLMNG_0_theta_o(2), 
        theta_o(1) => OLMNG_0_theta_o(1), theta_o(0) => 
        OLMNG_0_theta_o(0), init_speedpi_o(17) => 
        OLMNG_0_init_speedpi_o(17), init_speedpi_o(16) => 
        OLMNG_0_init_speedpi_o(16), init_speedpi_o(15) => 
        OLMNG_0_init_speedpi_o(15), init_speedpi_o(14) => 
        OLMNG_0_init_speedpi_o(14), init_speedpi_o(13) => 
        OLMNG_0_init_speedpi_o(13), init_speedpi_o(12) => 
        OLMNG_0_init_speedpi_o(12), init_speedpi_o(11) => 
        OLMNG_0_init_speedpi_o(11), init_speedpi_o(10) => 
        OLMNG_0_init_speedpi_o(10), init_speedpi_o(9) => 
        OLMNG_0_init_speedpi_o(9), init_speedpi_o(8) => 
        OLMNG_0_init_speedpi_o(8), init_speedpi_o(7) => 
        OLMNG_0_init_speedpi_o(7), init_speedpi_o(6) => 
        OLMNG_0_init_speedpi_o(6), init_speedpi_o(5) => 
        OLMNG_0_init_speedpi_o(5), init_speedpi_o(4) => 
        OLMNG_0_init_speedpi_o(4), init_speedpi_o(3) => 
        OLMNG_0_init_speedpi_o(3), init_speedpi_o(2) => 
        OLMNG_0_init_speedpi_o(2), init_speedpi_o(1) => 
        OLMNG_0_init_speedpi_o(1), init_speedpi_o(0) => 
        OLMNG_0_init_speedpi_o(0), init_iqpi_o(17) => 
        OLMNG_0_init_iqpi_o(17), init_iqpi_o(16) => 
        OLMNG_0_init_iqpi_o(16), init_iqpi_o(15) => 
        OLMNG_0_init_iqpi_o(15), init_iqpi_o(14) => 
        OLMNG_0_init_iqpi_o(14), init_iqpi_o(13) => 
        OLMNG_0_init_iqpi_o(13), init_iqpi_o(12) => 
        OLMNG_0_init_iqpi_o(12), init_iqpi_o(11) => 
        OLMNG_0_init_iqpi_o(11), init_iqpi_o(10) => 
        OLMNG_0_init_iqpi_o(10), init_iqpi_o(9) => 
        OLMNG_0_init_iqpi_o(9), init_iqpi_o(8) => 
        OLMNG_0_init_iqpi_o(8), init_iqpi_o(7) => 
        OLMNG_0_init_iqpi_o(7), init_iqpi_o(6) => 
        OLMNG_0_init_iqpi_o(6), init_iqpi_o(5) => 
        OLMNG_0_init_iqpi_o(5), init_iqpi_o(4) => 
        OLMNG_0_init_iqpi_o(4), init_iqpi_o(3) => 
        OLMNG_0_init_iqpi_o(3), init_iqpi_o(2) => 
        OLMNG_0_init_iqpi_o(2), init_iqpi_o(1) => 
        OLMNG_0_init_iqpi_o(1), init_iqpi_o(0) => 
        OLMNG_0_init_iqpi_o(0));
    
    MSC_i_9 : RATE_LIMITER
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FIC_0_CLK, start_i => ADC_SCALING_0_done_o, 
        soft_stop_i => SEQ_CONTROLLER_0_soft_stop_o, reset_rl_i
         => SEQ_CONTROLLER_0_reset_rl_o, direction_i => 
        apb3_en_if_0_direction_config_o, slew_count_i(17) => 
        apb3_en_if_1_rate_limit_slew_cnt_o(17), slew_count_i(16)
         => apb3_en_if_1_rate_limit_slew_cnt_o(16), 
        slew_count_i(15) => 
        apb3_en_if_1_rate_limit_slew_cnt_o(15), slew_count_i(14)
         => apb3_en_if_1_rate_limit_slew_cnt_o(14), 
        slew_count_i(13) => 
        apb3_en_if_1_rate_limit_slew_cnt_o(13), slew_count_i(12)
         => apb3_en_if_1_rate_limit_slew_cnt_o(12), 
        slew_count_i(11) => 
        apb3_en_if_1_rate_limit_slew_cnt_o(11), slew_count_i(10)
         => apb3_en_if_1_rate_limit_slew_cnt_o(10), 
        slew_count_i(9) => apb3_en_if_1_rate_limit_slew_cnt_o(9), 
        slew_count_i(8) => apb3_en_if_1_rate_limit_slew_cnt_o(8), 
        slew_count_i(7) => apb3_en_if_1_rate_limit_slew_cnt_o(7), 
        slew_count_i(6) => apb3_en_if_1_rate_limit_slew_cnt_o(6), 
        slew_count_i(5) => apb3_en_if_1_rate_limit_slew_cnt_o(5), 
        slew_count_i(4) => apb3_en_if_1_rate_limit_slew_cnt_o(4), 
        slew_count_i(3) => apb3_en_if_1_rate_limit_slew_cnt_o(3), 
        slew_count_i(2) => apb3_en_if_1_rate_limit_slew_cnt_o(2), 
        slew_count_i(1) => apb3_en_if_1_rate_limit_slew_cnt_o(1), 
        slew_count_i(0) => apb3_en_if_1_rate_limit_slew_cnt_o(0), 
        rate_count_i(17) => 
        apb3_en_if_1_rate_limit_rate_cnt_o(17), rate_count_i(16)
         => apb3_en_if_1_rate_limit_rate_cnt_o(16), 
        rate_count_i(15) => 
        apb3_en_if_1_rate_limit_rate_cnt_o(15), rate_count_i(14)
         => apb3_en_if_1_rate_limit_rate_cnt_o(14), 
        rate_count_i(13) => 
        apb3_en_if_1_rate_limit_rate_cnt_o(13), rate_count_i(12)
         => apb3_en_if_1_rate_limit_rate_cnt_o(12), 
        rate_count_i(11) => 
        apb3_en_if_1_rate_limit_rate_cnt_o(11), rate_count_i(10)
         => apb3_en_if_1_rate_limit_rate_cnt_o(10), 
        rate_count_i(9) => apb3_en_if_1_rate_limit_rate_cnt_o(9), 
        rate_count_i(8) => apb3_en_if_1_rate_limit_rate_cnt_o(8), 
        rate_count_i(7) => apb3_en_if_1_rate_limit_rate_cnt_o(7), 
        rate_count_i(6) => apb3_en_if_1_rate_limit_rate_cnt_o(6), 
        rate_count_i(5) => apb3_en_if_1_rate_limit_rate_cnt_o(5), 
        rate_count_i(4) => apb3_en_if_1_rate_limit_rate_cnt_o(4), 
        rate_count_i(3) => apb3_en_if_1_rate_limit_rate_cnt_o(3), 
        rate_count_i(2) => apb3_en_if_1_rate_limit_rate_cnt_o(2), 
        rate_count_i(1) => apb3_en_if_1_rate_limit_rate_cnt_o(1), 
        rate_count_i(0) => apb3_en_if_1_rate_limit_rate_cnt_o(0), 
        rl_in_i(17) => apb3_en_if_1_rate_limit_ref_in_o(17), 
        rl_in_i(16) => apb3_en_if_1_rate_limit_ref_in_o(16), 
        rl_in_i(15) => apb3_en_if_1_rate_limit_ref_in_o(15), 
        rl_in_i(14) => apb3_en_if_1_rate_limit_ref_in_o(14), 
        rl_in_i(13) => apb3_en_if_1_rate_limit_ref_in_o(13), 
        rl_in_i(12) => apb3_en_if_1_rate_limit_ref_in_o(12), 
        rl_in_i(11) => apb3_en_if_1_rate_limit_ref_in_o(11), 
        rl_in_i(10) => apb3_en_if_1_rate_limit_ref_in_o(10), 
        rl_in_i(9) => apb3_en_if_1_rate_limit_ref_in_o(9), 
        rl_in_i(8) => apb3_en_if_1_rate_limit_ref_in_o(8), 
        rl_in_i(7) => apb3_en_if_1_rate_limit_ref_in_o(7), 
        rl_in_i(6) => apb3_en_if_1_rate_limit_ref_in_o(6), 
        rl_in_i(5) => apb3_en_if_1_rate_limit_ref_in_o(5), 
        rl_in_i(4) => apb3_en_if_1_rate_limit_ref_in_o(4), 
        rl_in_i(3) => apb3_en_if_1_rate_limit_ref_in_o(3), 
        rl_in_i(2) => apb3_en_if_1_rate_limit_ref_in_o(2), 
        rl_in_i(1) => apb3_en_if_1_rate_limit_ref_in_o(1), 
        rl_in_i(0) => apb3_en_if_1_rate_limit_ref_in_o(0), 
        rl_out_o(17) => RATE_LIMITER_0_rl_out_o(17), rl_out_o(16)
         => RATE_LIMITER_0_rl_out_o(16), rl_out_o(15) => 
        RATE_LIMITER_0_rl_out_o(15), rl_out_o(14) => 
        RATE_LIMITER_0_rl_out_o(14), rl_out_o(13) => 
        RATE_LIMITER_0_rl_out_o(13), rl_out_o(12) => 
        RATE_LIMITER_0_rl_out_o(12), rl_out_o(11) => 
        RATE_LIMITER_0_rl_out_o(11), rl_out_o(10) => 
        RATE_LIMITER_0_rl_out_o(10), rl_out_o(9) => 
        RATE_LIMITER_0_rl_out_o(9), rl_out_o(8) => 
        RATE_LIMITER_0_rl_out_o(8), rl_out_o(7) => 
        RATE_LIMITER_0_rl_out_o(7), rl_out_o(6) => 
        RATE_LIMITER_0_rl_out_o(6), rl_out_o(5) => 
        RATE_LIMITER_0_rl_out_o(5), rl_out_o(4) => 
        RATE_LIMITER_0_rl_out_o(4), rl_out_o(3) => 
        RATE_LIMITER_0_rl_out_o(3), rl_out_o(2) => 
        RATE_LIMITER_0_rl_out_o(2), rl_out_o(1) => 
        RATE_LIMITER_0_rl_out_o(1), rl_out_o(0) => 
        RATE_LIMITER_0_rl_out_o(0), rl_done_o => 
        RATE_LIMITER_0_rl_done_o);
    
    MSC_i_21 : SPEED_ID_IQ_PI
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FIC_0_CLK, clear_buffer_i => 
        SEQ_CONTROLLER_0_motor_stopped_o, speed_en_i => 
        SEQ_CONTROLLER_0_cl_status_o, idq_en_i => 
        SEQ_CONTROLLER_0_en_idq_pi_o, speed_pi_start_i => 
        RATE_LIMITER_0_rl_done_o, id_pi_start_i => 
        SPEED_ID_IQ_PI_1_iq_pi_done_o, iq_pi_start_i => 
        FOC_TRANSFORMS_0_park_done_o, speed_init_i(17) => 
        OLMNG_0_init_speedpi_o(17), speed_init_i(16) => 
        OLMNG_0_init_speedpi_o(16), speed_init_i(15) => 
        OLMNG_0_init_speedpi_o(15), speed_init_i(14) => 
        OLMNG_0_init_speedpi_o(14), speed_init_i(13) => 
        OLMNG_0_init_speedpi_o(13), speed_init_i(12) => 
        OLMNG_0_init_speedpi_o(12), speed_init_i(11) => 
        OLMNG_0_init_speedpi_o(11), speed_init_i(10) => 
        OLMNG_0_init_speedpi_o(10), speed_init_i(9) => 
        OLMNG_0_init_speedpi_o(9), speed_init_i(8) => 
        OLMNG_0_init_speedpi_o(8), speed_init_i(7) => 
        OLMNG_0_init_speedpi_o(7), speed_init_i(6) => 
        OLMNG_0_init_speedpi_o(6), speed_init_i(5) => 
        OLMNG_0_init_speedpi_o(5), speed_init_i(4) => 
        OLMNG_0_init_speedpi_o(4), speed_init_i(3) => 
        OLMNG_0_init_speedpi_o(3), speed_init_i(2) => 
        OLMNG_0_init_speedpi_o(2), speed_init_i(1) => 
        OLMNG_0_init_speedpi_o(1), speed_init_i(0) => 
        OLMNG_0_init_speedpi_o(0), id_init_i(17) => \GND\, 
        id_init_i(16) => \GND\, id_init_i(15) => \GND\, 
        id_init_i(14) => \GND\, id_init_i(13) => \GND\, 
        id_init_i(12) => \GND\, id_init_i(11) => \GND\, 
        id_init_i(10) => \GND\, id_init_i(9) => \GND\, 
        id_init_i(8) => \GND\, id_init_i(7) => \GND\, 
        id_init_i(6) => \GND\, id_init_i(5) => \GND\, 
        id_init_i(4) => \GND\, id_init_i(3) => \GND\, 
        id_init_i(2) => \GND\, id_init_i(1) => \GND\, 
        id_init_i(0) => \GND\, iq_init_i(17) => 
        OLMNG_0_init_iqpi_o(17), iq_init_i(16) => 
        OLMNG_0_init_iqpi_o(16), iq_init_i(15) => 
        OLMNG_0_init_iqpi_o(15), iq_init_i(14) => 
        OLMNG_0_init_iqpi_o(14), iq_init_i(13) => 
        OLMNG_0_init_iqpi_o(13), iq_init_i(12) => 
        OLMNG_0_init_iqpi_o(12), iq_init_i(11) => 
        OLMNG_0_init_iqpi_o(11), iq_init_i(10) => 
        OLMNG_0_init_iqpi_o(10), iq_init_i(9) => 
        OLMNG_0_init_iqpi_o(9), iq_init_i(8) => 
        OLMNG_0_init_iqpi_o(8), iq_init_i(7) => 
        OLMNG_0_init_iqpi_o(7), iq_init_i(6) => 
        OLMNG_0_init_iqpi_o(6), iq_init_i(5) => 
        OLMNG_0_init_iqpi_o(5), iq_init_i(4) => 
        OLMNG_0_init_iqpi_o(4), iq_init_i(3) => 
        OLMNG_0_init_iqpi_o(3), iq_init_i(2) => 
        OLMNG_0_init_iqpi_o(2), iq_init_i(1) => 
        OLMNG_0_init_iqpi_o(1), iq_init_i(0) => 
        OLMNG_0_init_iqpi_o(0), speed_pi_ref_input_i(17) => 
        RATE_LIMITER_0_rl_out_o(17), speed_pi_ref_input_i(16) => 
        RATE_LIMITER_0_rl_out_o(16), speed_pi_ref_input_i(15) => 
        RATE_LIMITER_0_rl_out_o(15), speed_pi_ref_input_i(14) => 
        RATE_LIMITER_0_rl_out_o(14), speed_pi_ref_input_i(13) => 
        RATE_LIMITER_0_rl_out_o(13), speed_pi_ref_input_i(12) => 
        RATE_LIMITER_0_rl_out_o(12), speed_pi_ref_input_i(11) => 
        RATE_LIMITER_0_rl_out_o(11), speed_pi_ref_input_i(10) => 
        RATE_LIMITER_0_rl_out_o(10), speed_pi_ref_input_i(9) => 
        RATE_LIMITER_0_rl_out_o(9), speed_pi_ref_input_i(8) => 
        RATE_LIMITER_0_rl_out_o(8), speed_pi_ref_input_i(7) => 
        RATE_LIMITER_0_rl_out_o(7), speed_pi_ref_input_i(6) => 
        RATE_LIMITER_0_rl_out_o(6), speed_pi_ref_input_i(5) => 
        RATE_LIMITER_0_rl_out_o(5), speed_pi_ref_input_i(4) => 
        RATE_LIMITER_0_rl_out_o(4), speed_pi_ref_input_i(3) => 
        RATE_LIMITER_0_rl_out_o(3), speed_pi_ref_input_i(2) => 
        RATE_LIMITER_0_rl_out_o(2), speed_pi_ref_input_i(1) => 
        RATE_LIMITER_0_rl_out_o(1), speed_pi_ref_input_i(0) => 
        RATE_LIMITER_0_rl_out_o(0), speed_pi_act_input_i(17) => 
        HALL_INTERFACE_1_omega_out_o(17), 
        speed_pi_act_input_i(16) => 
        HALL_INTERFACE_1_omega_out_o(16), 
        speed_pi_act_input_i(15) => 
        HALL_INTERFACE_1_omega_out_o(15), 
        speed_pi_act_input_i(14) => 
        HALL_INTERFACE_1_omega_out_o(14), 
        speed_pi_act_input_i(13) => 
        HALL_INTERFACE_1_omega_out_o(13), 
        speed_pi_act_input_i(12) => 
        HALL_INTERFACE_1_omega_out_o(12), 
        speed_pi_act_input_i(11) => 
        HALL_INTERFACE_1_omega_out_o(11), 
        speed_pi_act_input_i(10) => 
        HALL_INTERFACE_1_omega_out_o(10), speed_pi_act_input_i(9)
         => HALL_INTERFACE_1_omega_out_o(9), 
        speed_pi_act_input_i(8) => 
        HALL_INTERFACE_1_omega_out_o(8), speed_pi_act_input_i(7)
         => HALL_INTERFACE_1_omega_out_o(7), 
        speed_pi_act_input_i(6) => 
        HALL_INTERFACE_1_omega_out_o(6), speed_pi_act_input_i(5)
         => HALL_INTERFACE_1_omega_out_o(5), 
        speed_pi_act_input_i(4) => 
        HALL_INTERFACE_1_omega_out_o(4), speed_pi_act_input_i(3)
         => HALL_INTERFACE_1_omega_out_o(3), 
        speed_pi_act_input_i(2) => 
        HALL_INTERFACE_1_omega_out_o(2), speed_pi_act_input_i(1)
         => HALL_INTERFACE_1_omega_out_o(1), 
        speed_pi_act_input_i(0) => 
        HALL_INTERFACE_1_omega_out_o(0), speed_pi_kp_i(17) => 
        apb3_en_if_1_speed_pi_kp_o(17), speed_pi_kp_i(16) => 
        apb3_en_if_1_speed_pi_kp_o(16), speed_pi_kp_i(15) => 
        apb3_en_if_1_speed_pi_kp_o(15), speed_pi_kp_i(14) => 
        apb3_en_if_1_speed_pi_kp_o(14), speed_pi_kp_i(13) => 
        apb3_en_if_1_speed_pi_kp_o(13), speed_pi_kp_i(12) => 
        apb3_en_if_1_speed_pi_kp_o(12), speed_pi_kp_i(11) => 
        apb3_en_if_1_speed_pi_kp_o(11), speed_pi_kp_i(10) => 
        apb3_en_if_1_speed_pi_kp_o(10), speed_pi_kp_i(9) => 
        apb3_en_if_1_speed_pi_kp_o(9), speed_pi_kp_i(8) => 
        apb3_en_if_1_speed_pi_kp_o(8), speed_pi_kp_i(7) => 
        apb3_en_if_1_speed_pi_kp_o(7), speed_pi_kp_i(6) => 
        apb3_en_if_1_speed_pi_kp_o(6), speed_pi_kp_i(5) => 
        apb3_en_if_1_speed_pi_kp_o(5), speed_pi_kp_i(4) => 
        apb3_en_if_1_speed_pi_kp_o(4), speed_pi_kp_i(3) => 
        apb3_en_if_1_speed_pi_kp_o(3), speed_pi_kp_i(2) => 
        apb3_en_if_1_speed_pi_kp_o(2), speed_pi_kp_i(1) => 
        apb3_en_if_1_speed_pi_kp_o(1), speed_pi_kp_i(0) => 
        apb3_en_if_1_speed_pi_kp_o(0), speed_pi_ki_i(17) => 
        apb3_en_if_1_speed_pi_ki_o(17), speed_pi_ki_i(16) => 
        apb3_en_if_1_speed_pi_ki_o(16), speed_pi_ki_i(15) => 
        apb3_en_if_1_speed_pi_ki_o(15), speed_pi_ki_i(14) => 
        apb3_en_if_1_speed_pi_ki_o(14), speed_pi_ki_i(13) => 
        apb3_en_if_1_speed_pi_ki_o(13), speed_pi_ki_i(12) => 
        apb3_en_if_1_speed_pi_ki_o(12), speed_pi_ki_i(11) => 
        apb3_en_if_1_speed_pi_ki_o(11), speed_pi_ki_i(10) => 
        apb3_en_if_1_speed_pi_ki_o(10), speed_pi_ki_i(9) => 
        apb3_en_if_1_speed_pi_ki_o(9), speed_pi_ki_i(8) => 
        apb3_en_if_1_speed_pi_ki_o(8), speed_pi_ki_i(7) => 
        apb3_en_if_1_speed_pi_ki_o(7), speed_pi_ki_i(6) => 
        apb3_en_if_1_speed_pi_ki_o(6), speed_pi_ki_i(5) => 
        apb3_en_if_1_speed_pi_ki_o(5), speed_pi_ki_i(4) => 
        apb3_en_if_1_speed_pi_ki_o(4), speed_pi_ki_i(3) => 
        apb3_en_if_1_speed_pi_ki_o(3), speed_pi_ki_i(2) => 
        apb3_en_if_1_speed_pi_ki_o(2), speed_pi_ki_i(1) => 
        apb3_en_if_1_speed_pi_ki_o(1), speed_pi_ki_i(0) => 
        apb3_en_if_1_speed_pi_ki_o(0), speed_pi_ymax_i(17) => 
        \GND\, speed_pi_ymax_i(16) => \VCC\, speed_pi_ymax_i(15)
         => \VCC\, speed_pi_ymax_i(14) => \VCC\, 
        speed_pi_ymax_i(13) => \VCC\, speed_pi_ymax_i(12) => 
        \VCC\, speed_pi_ymax_i(11) => \VCC\, speed_pi_ymax_i(10)
         => \VCC\, speed_pi_ymax_i(9) => \VCC\, 
        speed_pi_ymax_i(8) => \VCC\, speed_pi_ymax_i(7) => \VCC\, 
        speed_pi_ymax_i(6) => \VCC\, speed_pi_ymax_i(5) => \VCC\, 
        speed_pi_ymax_i(4) => \VCC\, speed_pi_ymax_i(3) => \VCC\, 
        speed_pi_ymax_i(2) => \VCC\, speed_pi_ymax_i(1) => \VCC\, 
        speed_pi_ymax_i(0) => \VCC\, speed_pi_ymin_i(17) => \VCC\, 
        speed_pi_ymin_i(16) => \GND\, speed_pi_ymin_i(15) => 
        \GND\, speed_pi_ymin_i(14) => \GND\, speed_pi_ymin_i(13)
         => \GND\, speed_pi_ymin_i(12) => \GND\, 
        speed_pi_ymin_i(11) => \GND\, speed_pi_ymin_i(10) => 
        \GND\, speed_pi_ymin_i(9) => \GND\, speed_pi_ymin_i(8)
         => \GND\, speed_pi_ymin_i(7) => \GND\, 
        speed_pi_ymin_i(6) => \GND\, speed_pi_ymin_i(5) => \GND\, 
        speed_pi_ymin_i(4) => \GND\, speed_pi_ymin_i(3) => \GND\, 
        speed_pi_ymin_i(2) => \GND\, speed_pi_ymin_i(1) => \GND\, 
        speed_pi_ymin_i(0) => \VCC\, id_pi_ref_input_i(17) => 
        \GND\, id_pi_ref_input_i(16) => \GND\, 
        id_pi_ref_input_i(15) => \GND\, id_pi_ref_input_i(14) => 
        \GND\, id_pi_ref_input_i(13) => \GND\, 
        id_pi_ref_input_i(12) => \GND\, id_pi_ref_input_i(11) => 
        \GND\, id_pi_ref_input_i(10) => \GND\, 
        id_pi_ref_input_i(9) => \GND\, id_pi_ref_input_i(8) => 
        \GND\, id_pi_ref_input_i(7) => \GND\, 
        id_pi_ref_input_i(6) => \GND\, id_pi_ref_input_i(5) => 
        \GND\, id_pi_ref_input_i(4) => \GND\, 
        id_pi_ref_input_i(3) => \GND\, id_pi_ref_input_i(2) => 
        \GND\, id_pi_ref_input_i(1) => \GND\, 
        id_pi_ref_input_i(0) => \GND\, id_pi_act_input_i(17) => 
        FOC_TRANSFORMS_0_id_o(17), id_pi_act_input_i(16) => 
        FOC_TRANSFORMS_0_id_o(16), id_pi_act_input_i(15) => 
        FOC_TRANSFORMS_0_id_o(15), id_pi_act_input_i(14) => 
        FOC_TRANSFORMS_0_id_o(14), id_pi_act_input_i(13) => 
        FOC_TRANSFORMS_0_id_o(13), id_pi_act_input_i(12) => 
        FOC_TRANSFORMS_0_id_o(12), id_pi_act_input_i(11) => 
        FOC_TRANSFORMS_0_id_o(11), id_pi_act_input_i(10) => 
        FOC_TRANSFORMS_0_id_o(10), id_pi_act_input_i(9) => 
        FOC_TRANSFORMS_0_id_o(9), id_pi_act_input_i(8) => 
        FOC_TRANSFORMS_0_id_o(8), id_pi_act_input_i(7) => 
        FOC_TRANSFORMS_0_id_o(7), id_pi_act_input_i(6) => 
        FOC_TRANSFORMS_0_id_o(6), id_pi_act_input_i(5) => 
        FOC_TRANSFORMS_0_id_o(5), id_pi_act_input_i(4) => 
        \FOC_TRANSFORMS_0_id_o_4\, id_pi_act_input_i(3) => 
        FOC_TRANSFORMS_0_id_o(3), id_pi_act_input_i(2) => 
        FOC_TRANSFORMS_0_id_o(2), id_pi_act_input_i(1) => 
        FOC_TRANSFORMS_0_id_o(1), id_pi_act_input_i(0) => 
        FOC_TRANSFORMS_0_id_o(0), id_pi_kp_i(17) => 
        apb3_en_if_1_idq_pi_kp_o(17), id_pi_kp_i(16) => 
        apb3_en_if_1_idq_pi_kp_o(16), id_pi_kp_i(15) => 
        apb3_en_if_1_idq_pi_kp_o(15), id_pi_kp_i(14) => 
        apb3_en_if_1_idq_pi_kp_o(14), id_pi_kp_i(13) => 
        apb3_en_if_1_idq_pi_kp_o(13), id_pi_kp_i(12) => 
        apb3_en_if_1_idq_pi_kp_o(12), id_pi_kp_i(11) => 
        apb3_en_if_1_idq_pi_kp_o(11), id_pi_kp_i(10) => 
        apb3_en_if_1_idq_pi_kp_o(10), id_pi_kp_i(9) => 
        apb3_en_if_1_idq_pi_kp_o(9), id_pi_kp_i(8) => 
        apb3_en_if_1_idq_pi_kp_o(8), id_pi_kp_i(7) => 
        apb3_en_if_1_idq_pi_kp_o(7), id_pi_kp_i(6) => 
        apb3_en_if_1_idq_pi_kp_o(6), id_pi_kp_i(5) => 
        apb3_en_if_1_idq_pi_kp_o(5), id_pi_kp_i(4) => 
        apb3_en_if_1_idq_pi_kp_o(4), id_pi_kp_i(3) => 
        apb3_en_if_1_idq_pi_kp_o(3), id_pi_kp_i(2) => 
        apb3_en_if_1_idq_pi_kp_o(2), id_pi_kp_i(1) => 
        apb3_en_if_1_idq_pi_kp_o(1), id_pi_kp_i(0) => 
        apb3_en_if_1_idq_pi_kp_o(0), id_pi_ki_i(17) => 
        apb3_en_if_1_idq_pi_ki_o(17), id_pi_ki_i(16) => 
        apb3_en_if_1_idq_pi_ki_o(16), id_pi_ki_i(15) => 
        apb3_en_if_1_idq_pi_ki_o(15), id_pi_ki_i(14) => 
        apb3_en_if_1_idq_pi_ki_o(14), id_pi_ki_i(13) => 
        apb3_en_if_1_idq_pi_ki_o(13), id_pi_ki_i(12) => 
        apb3_en_if_1_idq_pi_ki_o(12), id_pi_ki_i(11) => 
        apb3_en_if_1_idq_pi_ki_o(11), id_pi_ki_i(10) => 
        apb3_en_if_1_idq_pi_ki_o(10), id_pi_ki_i(9) => 
        apb3_en_if_1_idq_pi_ki_o(9), id_pi_ki_i(8) => 
        apb3_en_if_1_idq_pi_ki_o(8), id_pi_ki_i(7) => 
        apb3_en_if_1_idq_pi_ki_o(7), id_pi_ki_i(6) => 
        apb3_en_if_1_idq_pi_ki_o(6), id_pi_ki_i(5) => 
        apb3_en_if_1_idq_pi_ki_o(5), id_pi_ki_i(4) => 
        apb3_en_if_1_idq_pi_ki_o(4), id_pi_ki_i(3) => 
        apb3_en_if_1_idq_pi_ki_o(3), id_pi_ki_i(2) => 
        apb3_en_if_1_idq_pi_ki_o(2), id_pi_ki_i(1) => 
        apb3_en_if_1_idq_pi_ki_o(1), id_pi_ki_i(0) => 
        apb3_en_if_1_idq_pi_ki_o(0), idq_pi_ymax_i(17) => \GND\, 
        idq_pi_ymax_i(16) => \VCC\, idq_pi_ymax_i(15) => \GND\, 
        idq_pi_ymax_i(14) => \GND\, idq_pi_ymax_i(13) => \GND\, 
        idq_pi_ymax_i(12) => \GND\, idq_pi_ymax_i(11) => \GND\, 
        idq_pi_ymax_i(10) => \GND\, idq_pi_ymax_i(9) => \GND\, 
        idq_pi_ymax_i(8) => \GND\, idq_pi_ymax_i(7) => \GND\, 
        idq_pi_ymax_i(6) => \GND\, idq_pi_ymax_i(5) => \GND\, 
        idq_pi_ymax_i(4) => \GND\, idq_pi_ymax_i(3) => \GND\, 
        idq_pi_ymax_i(2) => \GND\, idq_pi_ymax_i(1) => \GND\, 
        idq_pi_ymax_i(0) => \GND\, idq_pi_ymin_i(17) => \VCC\, 
        idq_pi_ymin_i(16) => \VCC\, idq_pi_ymin_i(15) => \GND\, 
        idq_pi_ymin_i(14) => \GND\, idq_pi_ymin_i(13) => \GND\, 
        idq_pi_ymin_i(12) => \GND\, idq_pi_ymin_i(11) => \GND\, 
        idq_pi_ymin_i(10) => \GND\, idq_pi_ymin_i(9) => \GND\, 
        idq_pi_ymin_i(8) => \GND\, idq_pi_ymin_i(7) => \GND\, 
        idq_pi_ymin_i(6) => \GND\, idq_pi_ymin_i(5) => \GND\, 
        idq_pi_ymin_i(4) => \GND\, idq_pi_ymin_i(3) => \GND\, 
        idq_pi_ymin_i(2) => \GND\, idq_pi_ymin_i(1) => \GND\, 
        idq_pi_ymin_i(0) => \GND\, iq_pi_ref_input_i(17) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(17), 
        iq_pi_ref_input_i(16) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(16), 
        iq_pi_ref_input_i(15) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(15), 
        iq_pi_ref_input_i(14) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(14), 
        iq_pi_ref_input_i(13) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(13), 
        iq_pi_ref_input_i(12) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(12), 
        iq_pi_ref_input_i(11) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(11), 
        iq_pi_ref_input_i(10) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(10), 
        iq_pi_ref_input_i(9) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(9), 
        iq_pi_ref_input_i(8) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(8), 
        iq_pi_ref_input_i(7) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(7), 
        iq_pi_ref_input_i(6) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(6), 
        iq_pi_ref_input_i(5) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(5), 
        iq_pi_ref_input_i(4) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(4), 
        iq_pi_ref_input_i(3) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(3), 
        iq_pi_ref_input_i(2) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(2), 
        iq_pi_ref_input_i(1) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(1), 
        iq_pi_ref_input_i(0) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(0), 
        iq_pi_act_input_i(17) => FOC_TRANSFORMS_0_iq_o(17), 
        iq_pi_act_input_i(16) => FOC_TRANSFORMS_0_iq_o(16), 
        iq_pi_act_input_i(15) => FOC_TRANSFORMS_0_iq_o(15), 
        iq_pi_act_input_i(14) => FOC_TRANSFORMS_0_iq_o(14), 
        iq_pi_act_input_i(13) => FOC_TRANSFORMS_0_iq_o(13), 
        iq_pi_act_input_i(12) => FOC_TRANSFORMS_0_iq_o(12), 
        iq_pi_act_input_i(11) => FOC_TRANSFORMS_0_iq_o(11), 
        iq_pi_act_input_i(10) => FOC_TRANSFORMS_0_iq_o(10), 
        iq_pi_act_input_i(9) => \FOC_TRANSFORMS_0_iq_o_9\, 
        iq_pi_act_input_i(8) => FOC_TRANSFORMS_0_iq_o(8), 
        iq_pi_act_input_i(7) => FOC_TRANSFORMS_0_iq_o(7), 
        iq_pi_act_input_i(6) => \FOC_TRANSFORMS_0_iq_o_6\, 
        iq_pi_act_input_i(5) => FOC_TRANSFORMS_0_iq_o(5), 
        iq_pi_act_input_i(4) => FOC_TRANSFORMS_0_iq_o(4), 
        iq_pi_act_input_i(3) => FOC_TRANSFORMS_0_iq_o(3), 
        iq_pi_act_input_i(2) => FOC_TRANSFORMS_0_iq_o(2), 
        iq_pi_act_input_i(1) => FOC_TRANSFORMS_0_iq_o(1), 
        iq_pi_act_input_i(0) => FOC_TRANSFORMS_0_iq_o(0), 
        iq_pi_kp_i(17) => \GND\, iq_pi_kp_i(16) => \GND\, 
        iq_pi_kp_i(15) => \GND\, iq_pi_kp_i(14) => \GND\, 
        iq_pi_kp_i(13) => \GND\, iq_pi_kp_i(12) => \GND\, 
        iq_pi_kp_i(11) => \GND\, iq_pi_kp_i(10) => \GND\, 
        iq_pi_kp_i(9) => \GND\, iq_pi_kp_i(8) => \GND\, 
        iq_pi_kp_i(7) => \GND\, iq_pi_kp_i(6) => \GND\, 
        iq_pi_kp_i(5) => \GND\, iq_pi_kp_i(4) => \GND\, 
        iq_pi_kp_i(3) => \GND\, iq_pi_kp_i(2) => \GND\, 
        iq_pi_kp_i(1) => \GND\, iq_pi_kp_i(0) => \GND\, 
        iq_pi_ki_i(17) => \GND\, iq_pi_ki_i(16) => \GND\, 
        iq_pi_ki_i(15) => \GND\, iq_pi_ki_i(14) => \GND\, 
        iq_pi_ki_i(13) => \GND\, iq_pi_ki_i(12) => \GND\, 
        iq_pi_ki_i(11) => \GND\, iq_pi_ki_i(10) => \GND\, 
        iq_pi_ki_i(9) => \GND\, iq_pi_ki_i(8) => \GND\, 
        iq_pi_ki_i(7) => \GND\, iq_pi_ki_i(6) => \GND\, 
        iq_pi_ki_i(5) => \GND\, iq_pi_ki_i(4) => \GND\, 
        iq_pi_ki_i(3) => \GND\, iq_pi_ki_i(2) => \GND\, 
        iq_pi_ki_i(1) => \GND\, iq_pi_ki_i(0) => \GND\, 
        speed_pi_done_o => speed_pi_done_o, id_pi_done_o => 
        SPEED_ID_IQ_PI_1_id_pi_done_o, iq_pi_done_o => 
        SPEED_ID_IQ_PI_1_iq_pi_done_o, speed_pi_output_o(17) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(17), 
        speed_pi_output_o(16) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(16), 
        speed_pi_output_o(15) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(15), 
        speed_pi_output_o(14) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(14), 
        speed_pi_output_o(13) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(13), 
        speed_pi_output_o(12) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(12), 
        speed_pi_output_o(11) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(11), 
        speed_pi_output_o(10) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(10), 
        speed_pi_output_o(9) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(9), 
        speed_pi_output_o(8) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(8), 
        speed_pi_output_o(7) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(7), 
        speed_pi_output_o(6) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(6), 
        speed_pi_output_o(5) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(5), 
        speed_pi_output_o(4) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(4), 
        speed_pi_output_o(3) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(3), 
        speed_pi_output_o(2) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(2), 
        speed_pi_output_o(1) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(1), 
        speed_pi_output_o(0) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(0), id_pi_output_o(17)
         => SPEED_ID_IQ_PI_0_id_pi_output_o(17), 
        id_pi_output_o(16) => SPEED_ID_IQ_PI_0_id_pi_output_o(16), 
        id_pi_output_o(15) => SPEED_ID_IQ_PI_0_id_pi_output_o(15), 
        id_pi_output_o(14) => SPEED_ID_IQ_PI_0_id_pi_output_o(14), 
        id_pi_output_o(13) => SPEED_ID_IQ_PI_0_id_pi_output_o(13), 
        id_pi_output_o(12) => SPEED_ID_IQ_PI_0_id_pi_output_o(12), 
        id_pi_output_o(11) => 
        \SPEED_ID_IQ_PI_0_id_pi_output_o_11\, id_pi_output_o(10)
         => SPEED_ID_IQ_PI_0_id_pi_output_o(10), 
        id_pi_output_o(9) => \SPEED_ID_IQ_PI_0_id_pi_output_o_9\, 
        id_pi_output_o(8) => SPEED_ID_IQ_PI_0_id_pi_output_o(8), 
        id_pi_output_o(7) => SPEED_ID_IQ_PI_0_id_pi_output_o(7), 
        id_pi_output_o(6) => \SPEED_ID_IQ_PI_0_id_pi_output_o_6\, 
        id_pi_output_o(5) => \SPEED_ID_IQ_PI_0_id_pi_output_o_5\, 
        id_pi_output_o(4) => SPEED_ID_IQ_PI_0_id_pi_output_o(4), 
        id_pi_output_o(3) => SPEED_ID_IQ_PI_0_id_pi_output_o(3), 
        id_pi_output_o(2) => SPEED_ID_IQ_PI_0_id_pi_output_o(2), 
        id_pi_output_o(1) => SPEED_ID_IQ_PI_0_id_pi_output_o(1), 
        id_pi_output_o(0) => SPEED_ID_IQ_PI_0_id_pi_output_o(0), 
        iq_pi_output_o(17) => SPEED_ID_IQ_PI_0_iq_pi_output_o(17), 
        iq_pi_output_o(16) => SPEED_ID_IQ_PI_0_iq_pi_output_o(16), 
        iq_pi_output_o(15) => SPEED_ID_IQ_PI_0_iq_pi_output_o(15), 
        iq_pi_output_o(14) => SPEED_ID_IQ_PI_0_iq_pi_output_o(14), 
        iq_pi_output_o(13) => SPEED_ID_IQ_PI_0_iq_pi_output_o(13), 
        iq_pi_output_o(12) => SPEED_ID_IQ_PI_0_iq_pi_output_o(12), 
        iq_pi_output_o(11) => SPEED_ID_IQ_PI_0_iq_pi_output_o(11), 
        iq_pi_output_o(10) => SPEED_ID_IQ_PI_0_iq_pi_output_o(10), 
        iq_pi_output_o(9) => SPEED_ID_IQ_PI_0_iq_pi_output_o(9), 
        iq_pi_output_o(8) => SPEED_ID_IQ_PI_0_iq_pi_output_o(8), 
        iq_pi_output_o(7) => SPEED_ID_IQ_PI_0_iq_pi_output_o(7), 
        iq_pi_output_o(6) => SPEED_ID_IQ_PI_0_iq_pi_output_o(6), 
        iq_pi_output_o(5) => SPEED_ID_IQ_PI_0_iq_pi_output_o(5), 
        iq_pi_output_o(4) => SPEED_ID_IQ_PI_0_iq_pi_output_o(4), 
        iq_pi_output_o(3) => SPEED_ID_IQ_PI_0_iq_pi_output_o(3), 
        iq_pi_output_o(2) => SPEED_ID_IQ_PI_0_iq_pi_output_o(2), 
        iq_pi_output_o(1) => SPEED_ID_IQ_PI_0_iq_pi_output_o(1), 
        iq_pi_output_o(0) => SPEED_ID_IQ_PI_0_iq_pi_output_o(0));
    
    MSC_i_11 : SEQ_CONTROLLER
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FIC_0_CLK, fault_i => 
        ADC_SCALING_1_over_current_fault_o, start_motor_i => 
        apb3_en_if_1_start_motor_o, stop_motor_i => 
        apb3_en_if_1_stop_motor_o, fault_clear_i => 
        apb3_en_if_1_fault_clr_o, speed_ref_i(17) => 
        RATE_LIMITER_0_rl_out_o(17), speed_ref_i(16) => 
        RATE_LIMITER_0_rl_out_o(16), speed_ref_i(15) => 
        RATE_LIMITER_0_rl_out_o(15), speed_ref_i(14) => 
        RATE_LIMITER_0_rl_out_o(14), speed_ref_i(13) => 
        RATE_LIMITER_0_rl_out_o(13), speed_ref_i(12) => 
        RATE_LIMITER_0_rl_out_o(12), speed_ref_i(11) => 
        RATE_LIMITER_0_rl_out_o(11), speed_ref_i(10) => 
        RATE_LIMITER_0_rl_out_o(10), speed_ref_i(9) => 
        RATE_LIMITER_0_rl_out_o(9), speed_ref_i(8) => 
        RATE_LIMITER_0_rl_out_o(8), speed_ref_i(7) => 
        RATE_LIMITER_0_rl_out_o(7), speed_ref_i(6) => 
        RATE_LIMITER_0_rl_out_o(6), speed_ref_i(5) => 
        RATE_LIMITER_0_rl_out_o(5), speed_ref_i(4) => 
        RATE_LIMITER_0_rl_out_o(4), speed_ref_i(3) => 
        RATE_LIMITER_0_rl_out_o(3), speed_ref_i(2) => 
        RATE_LIMITER_0_rl_out_o(2), speed_ref_i(1) => 
        RATE_LIMITER_0_rl_out_o(1), speed_ref_i(0) => 
        RATE_LIMITER_0_rl_out_o(0), speed_cl_i(17) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(17), speed_cl_i(16) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(16), speed_cl_i(15) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(15), speed_cl_i(14) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(14), speed_cl_i(13) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(13), speed_cl_i(12) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(12), speed_cl_i(11) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(11), speed_cl_i(10) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(10), speed_cl_i(9) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(9), speed_cl_i(8) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(8), speed_cl_i(7) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(7), speed_cl_i(6) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(6), speed_cl_i(5) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(5), speed_cl_i(4) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(4), speed_cl_i(3) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(3), speed_cl_i(2) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(2), speed_cl_i(1) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(1), speed_cl_i(0) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(0), vq_i(17) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(17), vq_i(16) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(16), vq_i(15) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(15), vq_i(14) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(14), vq_i(13) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(13), vq_i(12) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(12), vq_i(11) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(11), vq_i(10) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(10), vq_i(9) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(9), vq_i(8) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(8), vq_i(7) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(7), vq_i(6) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(6), vq_i(5) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(5), vq_i(4) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(4), vq_i(3) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(3), vq_i(2) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(2), vq_i(1) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(1), vq_i(0) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(0), max_ar_i(3) => 
        apb3_en_if_1_auto_restart_no_o(3), max_ar_i(2) => 
        apb3_en_if_1_auto_restart_no_o(2), max_ar_i(1) => 
        apb3_en_if_1_auto_restart_no_o(1), max_ar_i(0) => 
        apb3_en_if_1_auto_restart_no_o(0), calib_done_i => 
        ADC_SCALING_0_calib_done_o, pwm_midmatch_i => 
        PWM3PH_0_midmatch_o, foc_done_i => PWM_SCALING_1_done_o, 
        config_reg_i(3) => apb3_en_if_1_seq_cntl_config_o(3), 
        config_reg_i(2) => apb3_en_if_1_seq_cntl_config_o(2), 
        config_reg_i(1) => apb3_en_if_1_seq_cntl_config_o(1), 
        config_reg_i(0) => apb3_en_if_1_seq_cntl_config_o(0), 
        adc_start_o => SEQ_CONTROLLER_1_adc_start_o, cl_status_o
         => SEQ_CONTROLLER_0_cl_status_o, en_idq_pi_o => 
        SEQ_CONTROLLER_0_en_idq_pi_o, en_pwm_o => \A0_PWM_VL_O_c\, 
        motor_stopped_o => SEQ_CONTROLLER_0_motor_stopped_o, 
        reset_rl_o => SEQ_CONTROLLER_0_reset_rl_o, soft_stop_o
         => SEQ_CONTROLLER_0_soft_stop_o, sensor_reset_o => 
        sensor_reset_o, state_o(3) => SEQ_CONTROLLER_0_state_o(3), 
        state_o(2) => SEQ_CONTROLLER_0_state_o(2), state_o(1) => 
        SEQ_CONTROLLER_0_state_o(1), state_o(0) => 
        SEQ_CONTROLLER_0_state_o(0));
    
    VCC_Z : VCC
      port map(Y => \VCC\);
    
    MSC_i_1 : FOC_TRANSFORMS
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FIC_0_CLK, start_clarke_i => 
        ADC_SCALING_0_done_o, start_park_i => 
        FOC_TRANSFORMS_1_clarke_done_o_0, start_ipark_i => 
        SPEED_ID_IQ_PI_1_id_pi_done_o, start_iclarke_i => 
        FOC_TRANSFORMS_0_ipark_done_o, ia_i(17) => 
        ADC_SCALING_0_ia_adc_o(17), ia_i(16) => 
        ADC_SCALING_0_ia_adc_o(16), ia_i(15) => 
        ADC_SCALING_0_ia_adc_o(15), ia_i(14) => 
        ADC_SCALING_0_ia_adc_o(14), ia_i(13) => 
        ADC_SCALING_0_ia_adc_o(13), ia_i(12) => 
        ADC_SCALING_0_ia_adc_o(12), ia_i(11) => 
        ADC_SCALING_0_ia_adc_o(11), ia_i(10) => 
        ADC_SCALING_0_ia_adc_o(10), ia_i(9) => 
        ADC_SCALING_0_ia_adc_o(9), ia_i(8) => 
        ADC_SCALING_0_ia_adc_o(8), ia_i(7) => 
        ADC_SCALING_0_ia_adc_o(7), ia_i(6) => 
        ADC_SCALING_0_ia_adc_o(6), ia_i(5) => 
        ADC_SCALING_0_ia_adc_o(5), ia_i(4) => 
        ADC_SCALING_0_ia_adc_o(4), ia_i(3) => 
        ADC_SCALING_0_ia_adc_o(3), ia_i(2) => 
        ADC_SCALING_0_ia_adc_o(2), ia_i(1) => 
        ADC_SCALING_0_ia_adc_o(1), ia_i(0) => 
        ADC_SCALING_0_ia_adc_o(0), ib_i(17) => 
        ADC_SCALING_0_ib_adc_o(17), ib_i(16) => 
        ADC_SCALING_0_ib_adc_o(16), ib_i(15) => 
        ADC_SCALING_0_ib_adc_o(15), ib_i(14) => 
        ADC_SCALING_0_ib_adc_o(14), ib_i(13) => 
        ADC_SCALING_0_ib_adc_o(13), ib_i(12) => 
        ADC_SCALING_0_ib_adc_o(12), ib_i(11) => 
        ADC_SCALING_0_ib_adc_o(11), ib_i(10) => 
        ADC_SCALING_0_ib_adc_o(10), ib_i(9) => 
        ADC_SCALING_0_ib_adc_o(9), ib_i(8) => 
        ADC_SCALING_0_ib_adc_o(8), ib_i(7) => 
        ADC_SCALING_0_ib_adc_o(7), ib_i(6) => 
        ADC_SCALING_0_ib_adc_o(6), ib_i(5) => 
        ADC_SCALING_0_ib_adc_o(5), ib_i(4) => 
        ADC_SCALING_0_ib_adc_o(4), ib_i(3) => 
        ADC_SCALING_0_ib_adc_o(3), ib_i(2) => 
        ADC_SCALING_0_ib_adc_o(2), ib_i(1) => 
        ADC_SCALING_0_ib_adc_o(1), ib_i(0) => 
        ADC_SCALING_0_ib_adc_o(0), ialpha_i(17) => 
        FOC_TRANSFORMS_0_ialpha_o(17), ialpha_i(16) => 
        FOC_TRANSFORMS_0_ialpha_o(16), ialpha_i(15) => 
        FOC_TRANSFORMS_0_ialpha_o(15), ialpha_i(14) => 
        FOC_TRANSFORMS_0_ialpha_o(14), ialpha_i(13) => 
        FOC_TRANSFORMS_0_ialpha_o(13), ialpha_i(12) => 
        FOC_TRANSFORMS_0_ialpha_o(12), ialpha_i(11) => 
        FOC_TRANSFORMS_0_ialpha_o(11), ialpha_i(10) => 
        FOC_TRANSFORMS_0_ialpha_o(10), ialpha_i(9) => 
        FOC_TRANSFORMS_0_ialpha_o(9), ialpha_i(8) => 
        FOC_TRANSFORMS_0_ialpha_o(8), ialpha_i(7) => 
        FOC_TRANSFORMS_0_ialpha_o(7), ialpha_i(6) => 
        FOC_TRANSFORMS_0_ialpha_o(6), ialpha_i(5) => 
        FOC_TRANSFORMS_0_ialpha_o(5), ialpha_i(4) => 
        FOC_TRANSFORMS_0_ialpha_o(4), ialpha_i(3) => 
        FOC_TRANSFORMS_0_ialpha_o(3), ialpha_i(2) => 
        FOC_TRANSFORMS_0_ialpha_o(2), ialpha_i(1) => 
        FOC_TRANSFORMS_0_ialpha_o(1), ialpha_i(0) => \GND\, 
        ibeta_i(17) => FOC_TRANSFORMS_0_ibeta_o(17), ibeta_i(16)
         => FOC_TRANSFORMS_0_ibeta_o(16), ibeta_i(15) => 
        FOC_TRANSFORMS_0_ibeta_o(15), ibeta_i(14) => 
        FOC_TRANSFORMS_0_ibeta_o(14), ibeta_i(13) => 
        FOC_TRANSFORMS_0_ibeta_o(13), ibeta_i(12) => 
        FOC_TRANSFORMS_0_ibeta_o(12), ibeta_i(11) => 
        FOC_TRANSFORMS_0_ibeta_o(11), ibeta_i(10) => 
        FOC_TRANSFORMS_0_ibeta_o(10), ibeta_i(9) => 
        FOC_TRANSFORMS_0_ibeta_o(9), ibeta_i(8) => 
        FOC_TRANSFORMS_0_ibeta_o(8), ibeta_i(7) => 
        FOC_TRANSFORMS_0_ibeta_o(7), ibeta_i(6) => 
        FOC_TRANSFORMS_0_ibeta_o(6), ibeta_i(5) => 
        FOC_TRANSFORMS_0_ibeta_o(5), ibeta_i(4) => 
        FOC_TRANSFORMS_0_ibeta_o(4), ibeta_i(3) => 
        FOC_TRANSFORMS_0_ibeta_o(3), ibeta_i(2) => 
        FOC_TRANSFORMS_0_ibeta_o(2), ibeta_i(1) => 
        FOC_TRANSFORMS_0_ibeta_o(1), ibeta_i(0) => \GND\, 
        vd_i(17) => SPEED_ID_IQ_PI_0_id_pi_output_o(17), vd_i(16)
         => SPEED_ID_IQ_PI_0_id_pi_output_o(16), vd_i(15) => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(15), vd_i(14) => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(14), vd_i(13) => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(13), vd_i(12) => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(12), vd_i(11) => 
        \SPEED_ID_IQ_PI_0_id_pi_output_o_11\, vd_i(10) => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(10), vd_i(9) => 
        \SPEED_ID_IQ_PI_0_id_pi_output_o_9\, vd_i(8) => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(8), vd_i(7) => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(7), vd_i(6) => 
        \SPEED_ID_IQ_PI_0_id_pi_output_o_6\, vd_i(5) => 
        \SPEED_ID_IQ_PI_0_id_pi_output_o_5\, vd_i(4) => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(4), vd_i(3) => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(3), vd_i(2) => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(2), vd_i(1) => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(1), vd_i(0) => \GND\, 
        vq_i(17) => SPEED_ID_IQ_PI_0_iq_pi_output_o(17), vq_i(16)
         => SPEED_ID_IQ_PI_0_iq_pi_output_o(16), vq_i(15) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(15), vq_i(14) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(14), vq_i(13) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(13), vq_i(12) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(12), vq_i(11) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(11), vq_i(10) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(10), vq_i(9) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(9), vq_i(8) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(8), vq_i(7) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(7), vq_i(6) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(6), vq_i(5) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(5), vq_i(4) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(4), vq_i(3) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(3), vq_i(2) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(2), vq_i(1) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(1), vq_i(0) => \GND\, 
        valpha_i(17) => FOC_TRANSFORMS_0_valpha_o(17), 
        valpha_i(16) => FOC_TRANSFORMS_0_valpha_o(16), 
        valpha_i(15) => FOC_TRANSFORMS_0_valpha_o(15), 
        valpha_i(14) => FOC_TRANSFORMS_0_valpha_o(14), 
        valpha_i(13) => FOC_TRANSFORMS_0_valpha_o(13), 
        valpha_i(12) => FOC_TRANSFORMS_0_valpha_o(12), 
        valpha_i(11) => \FOC_TRANSFORMS_0_valpha_o_11\, 
        valpha_i(10) => FOC_TRANSFORMS_0_valpha_o(10), 
        valpha_i(9) => \FOC_TRANSFORMS_0_valpha_o_9\, valpha_i(8)
         => FOC_TRANSFORMS_0_valpha_o(8), valpha_i(7) => 
        FOC_TRANSFORMS_0_valpha_o(7), valpha_i(6) => 
        \FOC_TRANSFORMS_0_valpha_o_6\, valpha_i(5) => 
        \FOC_TRANSFORMS_0_valpha_o_5\, valpha_i(4) => 
        FOC_TRANSFORMS_0_valpha_o(4), valpha_i(3) => 
        FOC_TRANSFORMS_0_valpha_o(3), valpha_i(2) => 
        FOC_TRANSFORMS_0_valpha_o(2), valpha_i(1) => 
        FOC_TRANSFORMS_0_valpha_o(1), valpha_i(0) => 
        FOC_TRANSFORMS_0_valpha_o(0), vbeta_i(17) => 
        FOC_TRANSFORMS_0_vbeta_o(17), vbeta_i(16) => 
        FOC_TRANSFORMS_0_vbeta_o(16), vbeta_i(15) => 
        FOC_TRANSFORMS_0_vbeta_o(15), vbeta_i(14) => 
        FOC_TRANSFORMS_0_vbeta_o(14), vbeta_i(13) => 
        FOC_TRANSFORMS_0_vbeta_o(13), vbeta_i(12) => 
        FOC_TRANSFORMS_0_vbeta_o(12), vbeta_i(11) => 
        FOC_TRANSFORMS_0_vbeta_o(11), vbeta_i(10) => 
        FOC_TRANSFORMS_0_vbeta_o(10), vbeta_i(9) => 
        FOC_TRANSFORMS_0_vbeta_o(9), vbeta_i(8) => 
        FOC_TRANSFORMS_0_vbeta_o(8), vbeta_i(7) => 
        FOC_TRANSFORMS_0_vbeta_o(7), vbeta_i(6) => 
        FOC_TRANSFORMS_0_vbeta_o(6), vbeta_i(5) => 
        FOC_TRANSFORMS_0_vbeta_o(5), vbeta_i(4) => 
        FOC_TRANSFORMS_0_vbeta_o(4), vbeta_i(3) => 
        FOC_TRANSFORMS_0_vbeta_o(3), vbeta_i(2) => 
        FOC_TRANSFORMS_0_vbeta_o(2), vbeta_i(1) => 
        FOC_TRANSFORMS_0_vbeta_o(1), vbeta_i(0) => 
        FOC_TRANSFORMS_0_vbeta_o(0), theta_i(17) => 
        OLMNG_0_theta_o(17), theta_i(16) => OLMNG_0_theta_o(16), 
        theta_i(15) => OLMNG_0_theta_o(15), theta_i(14) => 
        OLMNG_0_theta_o(14), theta_i(13) => OLMNG_0_theta_o(13), 
        theta_i(12) => OLMNG_0_theta_o(12), theta_i(11) => 
        \OLMNG_0_theta_o_11\, theta_i(10) => OLMNG_0_theta_o(10), 
        theta_i(9) => \OLMNG_0_theta_o_9\, theta_i(8) => 
        OLMNG_0_theta_o(8), theta_i(7) => OLMNG_0_theta_o(7), 
        theta_i(6) => \OLMNG_0_theta_o_6\, theta_i(5) => 
        \OLMNG_0_theta_o_5\, theta_i(4) => OLMNG_0_theta_o(4), 
        theta_i(3) => OLMNG_0_theta_o(3), theta_i(2) => 
        OLMNG_0_theta_o(2), theta_i(1) => OLMNG_0_theta_o(1), 
        theta_i(0) => OLMNG_0_theta_o(0), clarke_done_o => 
        FOC_TRANSFORMS_1_clarke_done_o_0, park_done_o => 
        FOC_TRANSFORMS_0_park_done_o, ipark_done_o => 
        FOC_TRANSFORMS_0_ipark_done_o, iclarke_done_o => 
        FOC_TRANSFORMS_0_iclarke_done_o, ialpha_o(17) => 
        FOC_TRANSFORMS_0_ialpha_o(17), ialpha_o(16) => 
        FOC_TRANSFORMS_0_ialpha_o(16), ialpha_o(15) => 
        FOC_TRANSFORMS_0_ialpha_o(15), ialpha_o(14) => 
        FOC_TRANSFORMS_0_ialpha_o(14), ialpha_o(13) => 
        FOC_TRANSFORMS_0_ialpha_o(13), ialpha_o(12) => 
        FOC_TRANSFORMS_0_ialpha_o(12), ialpha_o(11) => 
        FOC_TRANSFORMS_0_ialpha_o(11), ialpha_o(10) => 
        FOC_TRANSFORMS_0_ialpha_o(10), ialpha_o(9) => 
        FOC_TRANSFORMS_0_ialpha_o(9), ialpha_o(8) => 
        FOC_TRANSFORMS_0_ialpha_o(8), ialpha_o(7) => 
        FOC_TRANSFORMS_0_ialpha_o(7), ialpha_o(6) => 
        FOC_TRANSFORMS_0_ialpha_o(6), ialpha_o(5) => 
        FOC_TRANSFORMS_0_ialpha_o(5), ialpha_o(4) => 
        FOC_TRANSFORMS_0_ialpha_o(4), ialpha_o(3) => 
        FOC_TRANSFORMS_0_ialpha_o(3), ialpha_o(2) => 
        FOC_TRANSFORMS_0_ialpha_o(2), ialpha_o(1) => 
        FOC_TRANSFORMS_0_ialpha_o(1), ialpha_o(0) => 
        FOC_TRANSFORMS_0_ialpha_o(0), ibeta_o(17) => 
        FOC_TRANSFORMS_0_ibeta_o(17), ibeta_o(16) => 
        FOC_TRANSFORMS_0_ibeta_o(16), ibeta_o(15) => 
        FOC_TRANSFORMS_0_ibeta_o(15), ibeta_o(14) => 
        FOC_TRANSFORMS_0_ibeta_o(14), ibeta_o(13) => 
        FOC_TRANSFORMS_0_ibeta_o(13), ibeta_o(12) => 
        FOC_TRANSFORMS_0_ibeta_o(12), ibeta_o(11) => 
        FOC_TRANSFORMS_0_ibeta_o(11), ibeta_o(10) => 
        FOC_TRANSFORMS_0_ibeta_o(10), ibeta_o(9) => 
        FOC_TRANSFORMS_0_ibeta_o(9), ibeta_o(8) => 
        FOC_TRANSFORMS_0_ibeta_o(8), ibeta_o(7) => 
        FOC_TRANSFORMS_0_ibeta_o(7), ibeta_o(6) => 
        FOC_TRANSFORMS_0_ibeta_o(6), ibeta_o(5) => 
        FOC_TRANSFORMS_0_ibeta_o(5), ibeta_o(4) => 
        FOC_TRANSFORMS_0_ibeta_o(4), ibeta_o(3) => 
        FOC_TRANSFORMS_0_ibeta_o(3), ibeta_o(2) => 
        FOC_TRANSFORMS_0_ibeta_o(2), ibeta_o(1) => 
        FOC_TRANSFORMS_0_ibeta_o(1), ibeta_o(0) => 
        FOC_TRANSFORMS_0_ibeta_o(0), id_o(17) => 
        FOC_TRANSFORMS_0_id_o(17), id_o(16) => 
        FOC_TRANSFORMS_0_id_o(16), id_o(15) => 
        FOC_TRANSFORMS_0_id_o(15), id_o(14) => 
        FOC_TRANSFORMS_0_id_o(14), id_o(13) => 
        FOC_TRANSFORMS_0_id_o(13), id_o(12) => 
        FOC_TRANSFORMS_0_id_o(12), id_o(11) => 
        FOC_TRANSFORMS_0_id_o(11), id_o(10) => 
        FOC_TRANSFORMS_0_id_o(10), id_o(9) => 
        FOC_TRANSFORMS_0_id_o(9), id_o(8) => 
        FOC_TRANSFORMS_0_id_o(8), id_o(7) => 
        FOC_TRANSFORMS_0_id_o(7), id_o(6) => 
        FOC_TRANSFORMS_0_id_o(6), id_o(5) => 
        FOC_TRANSFORMS_0_id_o(5), id_o(4) => 
        \FOC_TRANSFORMS_0_id_o_4\, id_o(3) => 
        FOC_TRANSFORMS_0_id_o(3), id_o(2) => 
        FOC_TRANSFORMS_0_id_o(2), id_o(1) => 
        FOC_TRANSFORMS_0_id_o(1), id_o(0) => 
        FOC_TRANSFORMS_0_id_o(0), iq_o(17) => 
        FOC_TRANSFORMS_0_iq_o(17), iq_o(16) => 
        FOC_TRANSFORMS_0_iq_o(16), iq_o(15) => 
        FOC_TRANSFORMS_0_iq_o(15), iq_o(14) => 
        FOC_TRANSFORMS_0_iq_o(14), iq_o(13) => 
        FOC_TRANSFORMS_0_iq_o(13), iq_o(12) => 
        FOC_TRANSFORMS_0_iq_o(12), iq_o(11) => 
        FOC_TRANSFORMS_0_iq_o(11), iq_o(10) => 
        FOC_TRANSFORMS_0_iq_o(10), iq_o(9) => 
        \FOC_TRANSFORMS_0_iq_o_9\, iq_o(8) => 
        FOC_TRANSFORMS_0_iq_o(8), iq_o(7) => 
        FOC_TRANSFORMS_0_iq_o(7), iq_o(6) => 
        \FOC_TRANSFORMS_0_iq_o_6\, iq_o(5) => 
        FOC_TRANSFORMS_0_iq_o(5), iq_o(4) => 
        FOC_TRANSFORMS_0_iq_o(4), iq_o(3) => 
        FOC_TRANSFORMS_0_iq_o(3), iq_o(2) => 
        FOC_TRANSFORMS_0_iq_o(2), iq_o(1) => 
        FOC_TRANSFORMS_0_iq_o(1), iq_o(0) => 
        FOC_TRANSFORMS_0_iq_o(0), valpha_o(17) => 
        FOC_TRANSFORMS_0_valpha_o(17), valpha_o(16) => 
        FOC_TRANSFORMS_0_valpha_o(16), valpha_o(15) => 
        FOC_TRANSFORMS_0_valpha_o(15), valpha_o(14) => 
        FOC_TRANSFORMS_0_valpha_o(14), valpha_o(13) => 
        FOC_TRANSFORMS_0_valpha_o(13), valpha_o(12) => 
        FOC_TRANSFORMS_0_valpha_o(12), valpha_o(11) => 
        \FOC_TRANSFORMS_0_valpha_o_11\, valpha_o(10) => 
        FOC_TRANSFORMS_0_valpha_o(10), valpha_o(9) => 
        \FOC_TRANSFORMS_0_valpha_o_9\, valpha_o(8) => 
        FOC_TRANSFORMS_0_valpha_o(8), valpha_o(7) => 
        FOC_TRANSFORMS_0_valpha_o(7), valpha_o(6) => 
        \FOC_TRANSFORMS_0_valpha_o_6\, valpha_o(5) => 
        \FOC_TRANSFORMS_0_valpha_o_5\, valpha_o(4) => 
        FOC_TRANSFORMS_0_valpha_o(4), valpha_o(3) => 
        FOC_TRANSFORMS_0_valpha_o(3), valpha_o(2) => 
        FOC_TRANSFORMS_0_valpha_o(2), valpha_o(1) => 
        FOC_TRANSFORMS_0_valpha_o(1), valpha_o(0) => 
        FOC_TRANSFORMS_0_valpha_o(0), vbeta_o(17) => 
        FOC_TRANSFORMS_0_vbeta_o(17), vbeta_o(16) => 
        FOC_TRANSFORMS_0_vbeta_o(16), vbeta_o(15) => 
        FOC_TRANSFORMS_0_vbeta_o(15), vbeta_o(14) => 
        FOC_TRANSFORMS_0_vbeta_o(14), vbeta_o(13) => 
        FOC_TRANSFORMS_0_vbeta_o(13), vbeta_o(12) => 
        FOC_TRANSFORMS_0_vbeta_o(12), vbeta_o(11) => 
        FOC_TRANSFORMS_0_vbeta_o(11), vbeta_o(10) => 
        FOC_TRANSFORMS_0_vbeta_o(10), vbeta_o(9) => 
        FOC_TRANSFORMS_0_vbeta_o(9), vbeta_o(8) => 
        FOC_TRANSFORMS_0_vbeta_o(8), vbeta_o(7) => 
        FOC_TRANSFORMS_0_vbeta_o(7), vbeta_o(6) => 
        FOC_TRANSFORMS_0_vbeta_o(6), vbeta_o(5) => 
        FOC_TRANSFORMS_0_vbeta_o(5), vbeta_o(4) => 
        FOC_TRANSFORMS_0_vbeta_o(4), vbeta_o(3) => 
        FOC_TRANSFORMS_0_vbeta_o(3), vbeta_o(2) => 
        FOC_TRANSFORMS_0_vbeta_o(2), vbeta_o(1) => 
        FOC_TRANSFORMS_0_vbeta_o(1), vbeta_o(0) => 
        FOC_TRANSFORMS_0_vbeta_o(0), va_o(17) => 
        FOC_TRANSFORMS_0_va_o(17), va_o(16) => 
        FOC_TRANSFORMS_0_va_o(16), va_o(15) => 
        FOC_TRANSFORMS_0_va_o(15), va_o(14) => 
        FOC_TRANSFORMS_0_va_o(14), va_o(13) => 
        FOC_TRANSFORMS_0_va_o(13), va_o(12) => 
        FOC_TRANSFORMS_0_va_o(12), va_o(11) => 
        FOC_TRANSFORMS_0_va_o(11), va_o(10) => 
        FOC_TRANSFORMS_0_va_o(10), va_o(9) => 
        FOC_TRANSFORMS_0_va_o(9), va_o(8) => 
        FOC_TRANSFORMS_0_va_o(8), va_o(7) => 
        FOC_TRANSFORMS_0_va_o(7), va_o(6) => 
        FOC_TRANSFORMS_0_va_o(6), va_o(5) => 
        FOC_TRANSFORMS_0_va_o(5), va_o(4) => 
        FOC_TRANSFORMS_0_va_o(4), va_o(3) => 
        FOC_TRANSFORMS_0_va_o(3), va_o(2) => 
        FOC_TRANSFORMS_0_va_o(2), va_o(1) => 
        FOC_TRANSFORMS_0_va_o(1), va_o(0) => 
        FOC_TRANSFORMS_0_va_o(0), vb_o(17) => 
        FOC_TRANSFORMS_0_vb_o(17), vb_o(16) => 
        FOC_TRANSFORMS_0_vb_o(16), vb_o(15) => 
        FOC_TRANSFORMS_0_vb_o(15), vb_o(14) => 
        FOC_TRANSFORMS_0_vb_o(14), vb_o(13) => 
        FOC_TRANSFORMS_0_vb_o(13), vb_o(12) => 
        FOC_TRANSFORMS_0_vb_o(12), vb_o(11) => 
        FOC_TRANSFORMS_0_vb_o(11), vb_o(10) => 
        FOC_TRANSFORMS_0_vb_o(10), vb_o(9) => 
        FOC_TRANSFORMS_0_vb_o(9), vb_o(8) => 
        FOC_TRANSFORMS_0_vb_o(8), vb_o(7) => 
        FOC_TRANSFORMS_0_vb_o(7), vb_o(6) => 
        FOC_TRANSFORMS_0_vb_o(6), vb_o(5) => 
        FOC_TRANSFORMS_0_vb_o(5), vb_o(4) => 
        FOC_TRANSFORMS_0_vb_o(4), vb_o(3) => 
        FOC_TRANSFORMS_0_vb_o(3), vb_o(2) => 
        FOC_TRANSFORMS_0_vb_o(2), vb_o(1) => 
        FOC_TRANSFORMS_0_vb_o(1), vb_o(0) => 
        FOC_TRANSFORMS_0_vb_o(0), vc_o(17) => 
        FOC_TRANSFORMS_0_vc_o(17), vc_o(16) => 
        FOC_TRANSFORMS_0_vc_o(16), vc_o(15) => 
        FOC_TRANSFORMS_0_vc_o(15), vc_o(14) => 
        FOC_TRANSFORMS_0_vc_o(14), vc_o(13) => 
        FOC_TRANSFORMS_0_vc_o(13), vc_o(12) => 
        FOC_TRANSFORMS_0_vc_o(12), vc_o(11) => 
        FOC_TRANSFORMS_0_vc_o(11), vc_o(10) => 
        FOC_TRANSFORMS_0_vc_o(10), vc_o(9) => 
        FOC_TRANSFORMS_0_vc_o(9), vc_o(8) => 
        FOC_TRANSFORMS_0_vc_o(8), vc_o(7) => 
        FOC_TRANSFORMS_0_vc_o(7), vc_o(6) => 
        FOC_TRANSFORMS_0_vc_o(6), vc_o(5) => 
        FOC_TRANSFORMS_0_vc_o(5), vc_o(4) => 
        FOC_TRANSFORMS_0_vc_o(4), vc_o(3) => 
        FOC_TRANSFORMS_0_vc_o(3), vc_o(2) => 
        FOC_TRANSFORMS_0_vc_o(2), vc_o(1) => 
        FOC_TRANSFORMS_0_vc_o(1), vc_o(0) => 
        FOC_TRANSFORMS_0_vc_o(0));
    
    adc_interface_0 : adc_interface
      port map(apb3_en_if_1_adc_control_reg_val_o(5) => 
        apb3_en_if_1_adc_control_reg_val_o(5), 
        apb3_en_if_1_adc_control_reg_val_o(4) => 
        apb3_en_if_1_adc_control_reg_val_o(4), 
        apb3_en_if_1_adc_control_reg_val_o(3) => 
        apb3_en_if_1_adc_control_reg_val_o(3), 
        apb3_en_if_1_adc_control_reg_val_o(2) => 
        apb3_en_if_1_adc_control_reg_val_o(2), 
        apb3_en_if_1_adc_control_reg_val_o(1) => 
        apb3_en_if_1_adc_control_reg_val_o(1), 
        apb3_en_if_1_adc_control_reg_val_o(0) => 
        apb3_en_if_1_adc_control_reg_val_o(0), 
        adc_interface_0_result_ch0_o(11) => 
        adc_interface_0_result_ch0_o(11), 
        adc_interface_0_result_ch0_o(10) => 
        adc_interface_0_result_ch0_o(10), 
        adc_interface_0_result_ch0_o(9) => 
        adc_interface_0_result_ch0_o(9), 
        adc_interface_0_result_ch0_o(8) => 
        adc_interface_0_result_ch0_o(8), 
        adc_interface_0_result_ch0_o(7) => 
        adc_interface_0_result_ch0_o(7), 
        adc_interface_0_result_ch0_o(6) => 
        adc_interface_0_result_ch0_o(6), 
        adc_interface_0_result_ch0_o(5) => 
        adc_interface_0_result_ch0_o(5), 
        adc_interface_0_result_ch0_o(4) => 
        adc_interface_0_result_ch0_o(4), 
        adc_interface_0_result_ch0_o(3) => 
        adc_interface_0_result_ch0_o(3), 
        adc_interface_0_result_ch0_o(2) => 
        adc_interface_0_result_ch0_o(2), 
        adc_interface_0_result_ch0_o(1) => 
        adc_interface_0_result_ch0_o(1), 
        adc_interface_0_result_ch0_o(0) => 
        adc_interface_0_result_ch0_o(0), 
        adc_interface_0_result_ch1_o(11) => 
        adc_interface_0_result_ch1_o(11), 
        adc_interface_0_result_ch1_o(10) => 
        adc_interface_0_result_ch1_o(10), 
        adc_interface_0_result_ch1_o(9) => 
        adc_interface_0_result_ch1_o(9), 
        adc_interface_0_result_ch1_o(8) => 
        adc_interface_0_result_ch1_o(8), 
        adc_interface_0_result_ch1_o(7) => 
        adc_interface_0_result_ch1_o(7), 
        adc_interface_0_result_ch1_o(6) => 
        adc_interface_0_result_ch1_o(6), 
        adc_interface_0_result_ch1_o(5) => 
        adc_interface_0_result_ch1_o(5), 
        adc_interface_0_result_ch1_o(4) => 
        \adc_interface_0_result_ch1_o_4\, 
        adc_interface_0_result_ch1_o(3) => 
        adc_interface_0_result_ch1_o(3), 
        adc_interface_0_result_ch1_o(2) => 
        adc_interface_0_result_ch1_o(2), 
        adc_interface_0_result_ch1_o(1) => 
        adc_interface_0_result_ch1_o(1), 
        adc_interface_0_result_ch1_o(0) => 
        adc_interface_0_result_ch1_o(0), 
        adc_interface_0_result_ch2_o(11) => 
        adc_interface_0_result_ch2_o(11), 
        adc_interface_0_result_ch2_o(10) => 
        adc_interface_0_result_ch2_o(10), 
        adc_interface_0_result_ch2_o(9) => 
        adc_interface_0_result_ch2_o(9), 
        adc_interface_0_result_ch2_o(8) => 
        adc_interface_0_result_ch2_o(8), 
        adc_interface_0_result_ch2_o(7) => 
        adc_interface_0_result_ch2_o(7), 
        adc_interface_0_result_ch2_o(6) => 
        adc_interface_0_result_ch2_o(6), 
        adc_interface_0_result_ch2_o(5) => 
        adc_interface_0_result_ch2_o(5), 
        adc_interface_0_result_ch2_o(4) => 
        adc_interface_0_result_ch2_o(4), 
        adc_interface_0_result_ch2_o(3) => 
        adc_interface_0_result_ch2_o(3), 
        adc_interface_0_result_ch2_o(2) => 
        adc_interface_0_result_ch2_o(2), 
        adc_interface_0_result_ch2_o(1) => 
        adc_interface_0_result_ch2_o(1), 
        adc_interface_0_result_ch2_o(0) => 
        adc_interface_0_result_ch2_o(0), 
        adc_interface_0_result_ch3_o(11) => 
        adc_interface_0_result_ch3_o(11), 
        adc_interface_0_result_ch3_o(10) => 
        adc_interface_0_result_ch3_o(10), 
        adc_interface_0_result_ch3_o(9) => 
        adc_interface_0_result_ch3_o(9), 
        adc_interface_0_result_ch3_o(8) => 
        adc_interface_0_result_ch3_o(8), 
        adc_interface_0_result_ch3_o(7) => 
        adc_interface_0_result_ch3_o(7), 
        adc_interface_0_result_ch3_o(6) => 
        adc_interface_0_result_ch3_o(6), 
        adc_interface_0_result_ch3_o(5) => 
        adc_interface_0_result_ch3_o(5), 
        adc_interface_0_result_ch3_o(4) => 
        adc_interface_0_result_ch3_o(4), 
        adc_interface_0_result_ch3_o(3) => 
        adc_interface_0_result_ch3_o(3), 
        adc_interface_0_result_ch3_o(2) => 
        adc_interface_0_result_ch3_o(2), 
        adc_interface_0_result_ch3_o(1) => 
        adc_interface_0_result_ch3_o(1), 
        adc_interface_0_result_ch3_o(0) => 
        adc_interface_0_result_ch3_o(0), 
        apb3_en_if_1_adc_channel_ch2_o(15) => 
        apb3_en_if_1_adc_channel_ch2_o(15), 
        apb3_en_if_1_adc_channel_ch2_o(14) => 
        apb3_en_if_1_adc_channel_ch2_o(14), 
        apb3_en_if_1_adc_channel_ch2_o(13) => 
        apb3_en_if_1_adc_channel_ch2_o(13), 
        apb3_en_if_1_adc_channel_ch2_o(12) => 
        apb3_en_if_1_adc_channel_ch2_o(12), 
        apb3_en_if_1_adc_channel_ch2_o(11) => 
        apb3_en_if_1_adc_channel_ch2_o(11), 
        apb3_en_if_1_adc_channel_ch2_o(10) => 
        apb3_en_if_1_adc_channel_ch2_o(10), 
        apb3_en_if_1_adc_channel_ch2_o(9) => 
        apb3_en_if_1_adc_channel_ch2_o(9), 
        apb3_en_if_1_adc_channel_ch2_o(8) => 
        apb3_en_if_1_adc_channel_ch2_o(8), 
        apb3_en_if_1_adc_channel_ch2_o(7) => 
        apb3_en_if_1_adc_channel_ch2_o(7), 
        apb3_en_if_1_adc_channel_ch2_o(6) => 
        apb3_en_if_1_adc_channel_ch2_o(6), 
        apb3_en_if_1_adc_channel_ch2_o(5) => 
        apb3_en_if_1_adc_channel_ch2_o(5), 
        apb3_en_if_1_adc_channel_ch2_o(4) => 
        apb3_en_if_1_adc_channel_ch2_o(4), 
        apb3_en_if_1_adc_channel_ch2_o(3) => 
        apb3_en_if_1_adc_channel_ch2_o(3), 
        apb3_en_if_1_adc_channel_ch2_o(2) => 
        apb3_en_if_1_adc_channel_ch2_o(2), 
        apb3_en_if_1_adc_channel_ch2_o(1) => 
        apb3_en_if_1_adc_channel_ch2_o(1), 
        apb3_en_if_1_adc_channel_ch2_o(0) => 
        apb3_en_if_1_adc_channel_ch2_o(0), 
        apb3_en_if_1_adc_channel_ch0_o(15) => 
        apb3_en_if_1_adc_channel_ch0_o(15), 
        apb3_en_if_1_adc_channel_ch0_o(14) => 
        apb3_en_if_1_adc_channel_ch0_o(14), 
        apb3_en_if_1_adc_channel_ch0_o(13) => 
        apb3_en_if_1_adc_channel_ch0_o(13), 
        apb3_en_if_1_adc_channel_ch0_o(12) => 
        apb3_en_if_1_adc_channel_ch0_o(12), 
        apb3_en_if_1_adc_channel_ch0_o(11) => 
        apb3_en_if_1_adc_channel_ch0_o(11), 
        apb3_en_if_1_adc_channel_ch0_o(10) => 
        apb3_en_if_1_adc_channel_ch0_o(10), 
        apb3_en_if_1_adc_channel_ch0_o(9) => 
        apb3_en_if_1_adc_channel_ch0_o(9), 
        apb3_en_if_1_adc_channel_ch0_o(8) => 
        apb3_en_if_1_adc_channel_ch0_o(8), 
        apb3_en_if_1_adc_channel_ch0_o(7) => 
        apb3_en_if_1_adc_channel_ch0_o(7), 
        apb3_en_if_1_adc_channel_ch0_o(6) => 
        apb3_en_if_1_adc_channel_ch0_o(6), 
        apb3_en_if_1_adc_channel_ch0_o(5) => 
        apb3_en_if_1_adc_channel_ch0_o(5), 
        apb3_en_if_1_adc_channel_ch0_o(4) => 
        apb3_en_if_1_adc_channel_ch0_o(4), 
        apb3_en_if_1_adc_channel_ch0_o(3) => 
        apb3_en_if_1_adc_channel_ch0_o(3), 
        apb3_en_if_1_adc_channel_ch0_o(2) => 
        apb3_en_if_1_adc_channel_ch0_o(2), 
        apb3_en_if_1_adc_channel_ch0_o(1) => 
        apb3_en_if_1_adc_channel_ch0_o(1), 
        apb3_en_if_1_adc_channel_ch0_o(0) => 
        apb3_en_if_1_adc_channel_ch0_o(0), 
        apb3_en_if_1_adc_channel_ch1_o(15) => 
        apb3_en_if_1_adc_channel_ch1_o(15), 
        apb3_en_if_1_adc_channel_ch1_o(14) => 
        apb3_en_if_1_adc_channel_ch1_o(14), 
        apb3_en_if_1_adc_channel_ch1_o(13) => 
        apb3_en_if_1_adc_channel_ch1_o(13), 
        apb3_en_if_1_adc_channel_ch1_o(12) => 
        apb3_en_if_1_adc_channel_ch1_o(12), 
        apb3_en_if_1_adc_channel_ch1_o(11) => 
        apb3_en_if_1_adc_channel_ch1_o(11), 
        apb3_en_if_1_adc_channel_ch1_o(10) => 
        apb3_en_if_1_adc_channel_ch1_o(10), 
        apb3_en_if_1_adc_channel_ch1_o(9) => 
        apb3_en_if_1_adc_channel_ch1_o(9), 
        apb3_en_if_1_adc_channel_ch1_o(8) => 
        apb3_en_if_1_adc_channel_ch1_o(8), 
        apb3_en_if_1_adc_channel_ch1_o(7) => 
        apb3_en_if_1_adc_channel_ch1_o(7), 
        apb3_en_if_1_adc_channel_ch1_o(6) => 
        apb3_en_if_1_adc_channel_ch1_o(6), 
        apb3_en_if_1_adc_channel_ch1_o(5) => 
        apb3_en_if_1_adc_channel_ch1_o(5), 
        apb3_en_if_1_adc_channel_ch1_o(4) => 
        apb3_en_if_1_adc_channel_ch1_o(4), 
        apb3_en_if_1_adc_channel_ch1_o(3) => 
        apb3_en_if_1_adc_channel_ch1_o(3), 
        apb3_en_if_1_adc_channel_ch1_o(2) => 
        apb3_en_if_1_adc_channel_ch1_o(2), 
        apb3_en_if_1_adc_channel_ch1_o(1) => 
        apb3_en_if_1_adc_channel_ch1_o(1), 
        apb3_en_if_1_adc_channel_ch1_o(0) => 
        apb3_en_if_1_adc_channel_ch1_o(0), 
        apb3_en_if_1_adc_channel_ch3_o(15) => 
        apb3_en_if_1_adc_channel_ch3_o(15), 
        apb3_en_if_1_adc_channel_ch3_o(14) => 
        apb3_en_if_1_adc_channel_ch3_o(14), 
        apb3_en_if_1_adc_channel_ch3_o(13) => 
        apb3_en_if_1_adc_channel_ch3_o(13), 
        apb3_en_if_1_adc_channel_ch3_o(12) => 
        apb3_en_if_1_adc_channel_ch3_o(12), 
        apb3_en_if_1_adc_channel_ch3_o(11) => 
        apb3_en_if_1_adc_channel_ch3_o(11), 
        apb3_en_if_1_adc_channel_ch3_o(10) => 
        apb3_en_if_1_adc_channel_ch3_o(10), 
        apb3_en_if_1_adc_channel_ch3_o(9) => 
        apb3_en_if_1_adc_channel_ch3_o(9), 
        apb3_en_if_1_adc_channel_ch3_o(8) => 
        apb3_en_if_1_adc_channel_ch3_o(8), 
        apb3_en_if_1_adc_channel_ch3_o(7) => 
        apb3_en_if_1_adc_channel_ch3_o(7), 
        apb3_en_if_1_adc_channel_ch3_o(6) => 
        apb3_en_if_1_adc_channel_ch3_o(6), 
        apb3_en_if_1_adc_channel_ch3_o(5) => 
        apb3_en_if_1_adc_channel_ch3_o(5), 
        apb3_en_if_1_adc_channel_ch3_o(4) => 
        apb3_en_if_1_adc_channel_ch3_o(4), 
        apb3_en_if_1_adc_channel_ch3_o(3) => 
        apb3_en_if_1_adc_channel_ch3_o(3), 
        apb3_en_if_1_adc_channel_ch3_o(2) => 
        apb3_en_if_1_adc_channel_ch3_o(2), 
        apb3_en_if_1_adc_channel_ch3_o(1) => 
        apb3_en_if_1_adc_channel_ch3_o(1), 
        apb3_en_if_1_adc_channel_ch3_o(0) => 
        apb3_en_if_1_adc_channel_ch3_o(0), MC_System_0_FIC_0_LOCK
         => MC_System_0_FIC_0_LOCK, MC_System_0_FIC_0_CLK => 
        MC_System_0_FIC_0_CLK, SEQ_CONTROLLER_1_adc_start_o => 
        SEQ_CONTROLLER_1_adc_start_o, A0_ADC_SDI_I_c => 
        A0_ADC_SDI_I_c, A0_ADC_SDO_O_c => A0_ADC_SDO_O_c, 
        A0_ADC_CS_O_c => A0_ADC_CS_O_c, A0_ADC_SCK_O_c => 
        A0_ADC_SCK_O_c, adc_interface_0_results_rdy_o => 
        adc_interface_0_results_rdy_o);
    
    MSC_i_25 : PWM_SCALING
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FIC_0_CLK, start_i => SVM_0_done_o, va_i(17)
         => SVM_0_va3h_o(17), va_i(16) => SVM_0_va3h_o(16), 
        va_i(15) => SVM_0_va3h_o(15), va_i(14) => 
        SVM_0_va3h_o(14), va_i(13) => SVM_0_va3h_o(13), va_i(12)
         => SVM_0_va3h_o(12), va_i(11) => SVM_0_va3h_o(11), 
        va_i(10) => SVM_0_va3h_o(10), va_i(9) => SVM_0_va3h_o(9), 
        va_i(8) => SVM_0_va3h_o(8), va_i(7) => SVM_0_va3h_o(7), 
        va_i(6) => SVM_0_va3h_o(6), va_i(5) => SVM_0_va3h_o(5), 
        va_i(4) => SVM_0_va3h_o(4), va_i(3) => SVM_0_va3h_o(3), 
        va_i(2) => SVM_0_va3h_o(2), va_i(1) => SVM_0_va3h_o(1), 
        va_i(0) => SVM_0_va3h_o(0), vb_i(17) => SVM_0_vb3h_o(17), 
        vb_i(16) => SVM_0_vb3h_o(16), vb_i(15) => 
        SVM_0_vb3h_o(15), vb_i(14) => SVM_0_vb3h_o(14), vb_i(13)
         => SVM_0_vb3h_o(13), vb_i(12) => SVM_0_vb3h_o(12), 
        vb_i(11) => SVM_0_vb3h_o(11), vb_i(10) => 
        SVM_0_vb3h_o(10), vb_i(9) => SVM_0_vb3h_o(9), vb_i(8) => 
        SVM_0_vb3h_o(8), vb_i(7) => SVM_0_vb3h_o(7), vb_i(6) => 
        SVM_0_vb3h_o(6), vb_i(5) => SVM_0_vb3h_o(5), vb_i(4) => 
        SVM_0_vb3h_o(4), vb_i(3) => SVM_0_vb3h_o(3), vb_i(2) => 
        SVM_0_vb3h_o(2), vb_i(1) => SVM_0_vb3h_o(1), vb_i(0) => 
        SVM_0_vb3h_o(0), vc_i(17) => SVM_0_vc3h_o(17), vc_i(16)
         => SVM_0_vc3h_o(16), vc_i(15) => SVM_0_vc3h_o(15), 
        vc_i(14) => SVM_0_vc3h_o(14), vc_i(13) => 
        SVM_0_vc3h_o(13), vc_i(12) => SVM_0_vc3h_o(12), vc_i(11)
         => SVM_0_vc3h_o(11), vc_i(10) => SVM_0_vc3h_o(10), 
        vc_i(9) => SVM_0_vc3h_o(9), vc_i(8) => SVM_0_vc3h_o(8), 
        vc_i(7) => SVM_0_vc3h_o(7), vc_i(6) => SVM_0_vc3h_o(6), 
        vc_i(5) => SVM_0_vc3h_o(5), vc_i(4) => SVM_0_vc3h_o(4), 
        vc_i(3) => SVM_0_vc3h_o(3), vc_i(2) => SVM_0_vc3h_o(2), 
        vc_i(1) => SVM_0_vc3h_o(1), vc_i(0) => SVM_0_vc3h_o(0), 
        pwm_period_i(17) => apb3_en_if_1_pwm_period_val_o(17), 
        pwm_period_i(16) => apb3_en_if_1_pwm_period_val_o(16), 
        pwm_period_i(15) => apb3_en_if_1_pwm_period_val_o(15), 
        pwm_period_i(14) => apb3_en_if_1_pwm_period_val_o(14), 
        pwm_period_i(13) => apb3_en_if_1_pwm_period_val_o(13), 
        pwm_period_i(12) => apb3_en_if_1_pwm_period_val_o(12), 
        pwm_period_i(11) => apb3_en_if_1_pwm_period_val_o(11), 
        pwm_period_i(10) => apb3_en_if_1_pwm_period_val_o(10), 
        pwm_period_i(9) => apb3_en_if_1_pwm_period_val_o(9), 
        pwm_period_i(8) => apb3_en_if_1_pwm_period_val_o(8), 
        pwm_period_i(7) => apb3_en_if_1_pwm_period_val_o(7), 
        pwm_period_i(6) => apb3_en_if_1_pwm_period_val_o(6), 
        pwm_period_i(5) => apb3_en_if_1_pwm_period_val_o(5), 
        pwm_period_i(4) => apb3_en_if_1_pwm_period_val_o(4), 
        pwm_period_i(3) => apb3_en_if_1_pwm_period_val_o(3), 
        pwm_period_i(2) => apb3_en_if_1_pwm_period_val_o(2), 
        pwm_period_i(1) => apb3_en_if_1_pwm_period_val_o(1), 
        pwm_period_i(0) => apb3_en_if_1_pwm_period_val_o(0), 
        pwm_gain_i(17) => apb3_en_if_1_pwm_gain_val_o(17), 
        pwm_gain_i(16) => apb3_en_if_1_pwm_gain_val_o(16), 
        pwm_gain_i(15) => apb3_en_if_1_pwm_gain_val_o(15), 
        pwm_gain_i(14) => apb3_en_if_1_pwm_gain_val_o(14), 
        pwm_gain_i(13) => apb3_en_if_1_pwm_gain_val_o(13), 
        pwm_gain_i(12) => apb3_en_if_1_pwm_gain_val_o(12), 
        pwm_gain_i(11) => apb3_en_if_1_pwm_gain_val_o(11), 
        pwm_gain_i(10) => apb3_en_if_1_pwm_gain_val_o(10), 
        pwm_gain_i(9) => apb3_en_if_1_pwm_gain_val_o(9), 
        pwm_gain_i(8) => apb3_en_if_1_pwm_gain_val_o(8), 
        pwm_gain_i(7) => apb3_en_if_1_pwm_gain_val_o(7), 
        pwm_gain_i(6) => apb3_en_if_1_pwm_gain_val_o(6), 
        pwm_gain_i(5) => apb3_en_if_1_pwm_gain_val_o(5), 
        pwm_gain_i(4) => apb3_en_if_1_pwm_gain_val_o(4), 
        pwm_gain_i(3) => apb3_en_if_1_pwm_gain_val_o(3), 
        pwm_gain_i(2) => apb3_en_if_1_pwm_gain_val_o(2), 
        pwm_gain_i(1) => apb3_en_if_1_pwm_gain_val_o(1), 
        pwm_gain_i(0) => \GND\, Va_o(17) => 
        PWM_SCALING_0_Va_o(17), Va_o(16) => 
        PWM_SCALING_0_Va_o(16), Va_o(15) => 
        PWM_SCALING_0_Va_o(15), Va_o(14) => 
        PWM_SCALING_0_Va_o(14), Va_o(13) => 
        PWM_SCALING_0_Va_o(13), Va_o(12) => 
        PWM_SCALING_0_Va_o(12), Va_o(11) => 
        PWM_SCALING_0_Va_o(11), Va_o(10) => 
        PWM_SCALING_0_Va_o(10), Va_o(9) => PWM_SCALING_0_Va_o(9), 
        Va_o(8) => PWM_SCALING_0_Va_o(8), Va_o(7) => 
        PWM_SCALING_0_Va_o(7), Va_o(6) => PWM_SCALING_0_Va_o(6), 
        Va_o(5) => PWM_SCALING_0_Va_o(5), Va_o(4) => 
        PWM_SCALING_0_Va_o(4), Va_o(3) => PWM_SCALING_0_Va_o(3), 
        Va_o(2) => PWM_SCALING_0_Va_o(2), Va_o(1) => 
        PWM_SCALING_0_Va_o(1), Va_o(0) => PWM_SCALING_0_Va_o(0), 
        Vb_o(17) => PWM_SCALING_0_Vb_o(17), Vb_o(16) => 
        PWM_SCALING_0_Vb_o(16), Vb_o(15) => 
        PWM_SCALING_0_Vb_o(15), Vb_o(14) => 
        PWM_SCALING_0_Vb_o(14), Vb_o(13) => 
        PWM_SCALING_0_Vb_o(13), Vb_o(12) => 
        PWM_SCALING_0_Vb_o(12), Vb_o(11) => 
        PWM_SCALING_0_Vb_o(11), Vb_o(10) => 
        PWM_SCALING_0_Vb_o(10), Vb_o(9) => PWM_SCALING_0_Vb_o(9), 
        Vb_o(8) => PWM_SCALING_0_Vb_o(8), Vb_o(7) => 
        PWM_SCALING_0_Vb_o(7), Vb_o(6) => PWM_SCALING_0_Vb_o(6), 
        Vb_o(5) => PWM_SCALING_0_Vb_o(5), Vb_o(4) => 
        PWM_SCALING_0_Vb_o(4), Vb_o(3) => PWM_SCALING_0_Vb_o(3), 
        Vb_o(2) => PWM_SCALING_0_Vb_o(2), Vb_o(1) => 
        PWM_SCALING_0_Vb_o(1), Vb_o(0) => PWM_SCALING_0_Vb_o(0), 
        Vc_o(17) => PWM_SCALING_0_Vc_o(17), Vc_o(16) => 
        PWM_SCALING_0_Vc_o(16), Vc_o(15) => 
        PWM_SCALING_0_Vc_o(15), Vc_o(14) => 
        PWM_SCALING_0_Vc_o(14), Vc_o(13) => 
        PWM_SCALING_0_Vc_o(13), Vc_o(12) => 
        PWM_SCALING_0_Vc_o(12), Vc_o(11) => 
        PWM_SCALING_0_Vc_o(11), Vc_o(10) => 
        PWM_SCALING_0_Vc_o(10), Vc_o(9) => PWM_SCALING_0_Vc_o(9), 
        Vc_o(8) => PWM_SCALING_0_Vc_o(8), Vc_o(7) => 
        PWM_SCALING_0_Vc_o(7), Vc_o(6) => PWM_SCALING_0_Vc_o(6), 
        Vc_o(5) => PWM_SCALING_0_Vc_o(5), Vc_o(4) => 
        PWM_SCALING_0_Vc_o(4), Vc_o(3) => PWM_SCALING_0_Vc_o(3), 
        Vc_o(2) => PWM_SCALING_0_Vc_o(2), Vc_o(1) => 
        PWM_SCALING_0_Vc_o(1), Vc_o(0) => PWM_SCALING_0_Vc_o(0), 
        done_o => PWM_SCALING_1_done_o);
    
    MSC_i_15 : HALL_INTERFACE
      port map(reset_i => MC_System_0_FIC_0_LOCK, sys_clk_i => 
        MC_System_0_FIC_0_CLK, ha_i => HA_i_c, hb_i => HB_i_c, 
        hc_i => HC_i_c, clear_buffer_i => 
        SEQ_CONTROLLER_0_motor_stopped_o, fil_trig_i => 
        PWM3PH_0_midmatch_o, filter_factor_i(3) => 
        apb3_hall_if_0_hall_filter_factor_o(3), 
        filter_factor_i(2) => 
        apb3_hall_if_0_hall_filter_factor_o(2), 
        filter_factor_i(1) => 
        apb3_hall_if_0_hall_filter_factor_o(1), 
        filter_factor_i(0) => 
        apb3_hall_if_0_hall_filter_factor_o(0), hall_sensor_pol_i
         => apb3_hall_if_0_hall_sensor_polarity_o, 
        speed_factor_i(17) => 
        apb3_hall_if_0_hall_speed_factor_o(17), 
        speed_factor_i(16) => 
        apb3_hall_if_0_hall_speed_factor_o(16), 
        speed_factor_i(15) => 
        apb3_hall_if_0_hall_speed_factor_o(15), 
        speed_factor_i(14) => 
        apb3_hall_if_0_hall_speed_factor_o(14), 
        speed_factor_i(13) => 
        apb3_hall_if_0_hall_speed_factor_o(13), 
        speed_factor_i(12) => 
        apb3_hall_if_0_hall_speed_factor_o(12), 
        speed_factor_i(11) => 
        apb3_hall_if_0_hall_speed_factor_o(11), 
        speed_factor_i(10) => 
        apb3_hall_if_0_hall_speed_factor_o(10), speed_factor_i(9)
         => apb3_hall_if_0_hall_speed_factor_o(9), 
        speed_factor_i(8) => 
        apb3_hall_if_0_hall_speed_factor_o(8), speed_factor_i(7)
         => apb3_hall_if_0_hall_speed_factor_o(7), 
        speed_factor_i(6) => 
        apb3_hall_if_0_hall_speed_factor_o(6), speed_factor_i(5)
         => apb3_hall_if_0_hall_speed_factor_o(5), 
        speed_factor_i(4) => 
        apb3_hall_if_0_hall_speed_factor_o(4), speed_factor_i(3)
         => apb3_hall_if_0_hall_speed_factor_o(3), 
        speed_factor_i(2) => 
        apb3_hall_if_0_hall_speed_factor_o(2), speed_factor_i(1)
         => apb3_hall_if_0_hall_speed_factor_o(1), 
        speed_factor_i(0) => 
        apb3_hall_if_0_hall_speed_factor_o(0), omega_done_o => 
        omega_done_o, omega_out_o(17) => 
        HALL_INTERFACE_1_omega_out_o(17), omega_out_o(16) => 
        HALL_INTERFACE_1_omega_out_o(16), omega_out_o(15) => 
        HALL_INTERFACE_1_omega_out_o(15), omega_out_o(14) => 
        HALL_INTERFACE_1_omega_out_o(14), omega_out_o(13) => 
        HALL_INTERFACE_1_omega_out_o(13), omega_out_o(12) => 
        HALL_INTERFACE_1_omega_out_o(12), omega_out_o(11) => 
        HALL_INTERFACE_1_omega_out_o(11), omega_out_o(10) => 
        HALL_INTERFACE_1_omega_out_o(10), omega_out_o(9) => 
        HALL_INTERFACE_1_omega_out_o(9), omega_out_o(8) => 
        HALL_INTERFACE_1_omega_out_o(8), omega_out_o(7) => 
        HALL_INTERFACE_1_omega_out_o(7), omega_out_o(6) => 
        HALL_INTERFACE_1_omega_out_o(6), omega_out_o(5) => 
        HALL_INTERFACE_1_omega_out_o(5), omega_out_o(4) => 
        HALL_INTERFACE_1_omega_out_o(4), omega_out_o(3) => 
        HALL_INTERFACE_1_omega_out_o(3), omega_out_o(2) => 
        HALL_INTERFACE_1_omega_out_o(2), omega_out_o(1) => 
        HALL_INTERFACE_1_omega_out_o(1), omega_out_o(0) => 
        HALL_INTERFACE_1_omega_out_o(0), angle_out_raw_o(17) => 
        angle_out_raw_o(17), angle_out_raw_o(16) => 
        angle_out_raw_o(16), angle_out_raw_o(15) => 
        angle_out_raw_o(15), angle_out_raw_o(14) => 
        angle_out_raw_o(14), angle_out_raw_o(13) => 
        angle_out_raw_o(13), angle_out_raw_o(12) => 
        HALL_INTERFACE_1_angle_out_raw_o(12), angle_out_raw_o(11)
         => HALL_INTERFACE_1_angle_out_raw_o(11), 
        angle_out_raw_o(10) => 
        HALL_INTERFACE_1_angle_out_raw_o(10), angle_out_raw_o(9)
         => HALL_INTERFACE_1_angle_out_raw_o(9), 
        angle_out_raw_o(8) => HALL_INTERFACE_1_angle_out_raw_o(8), 
        angle_out_raw_o(7) => HALL_INTERFACE_1_angle_out_raw_o(7), 
        angle_out_raw_o(6) => HALL_INTERFACE_1_angle_out_raw_o(6), 
        angle_out_raw_o(5) => HALL_INTERFACE_1_angle_out_raw_o(5), 
        angle_out_raw_o(4) => HALL_INTERFACE_1_angle_out_raw_o(4), 
        angle_out_raw_o(3) => HALL_INTERFACE_1_angle_out_raw_o(3), 
        angle_out_raw_o(2) => HALL_INTERFACE_1_angle_out_raw_o(2), 
        angle_out_raw_o(1) => HALL_INTERFACE_1_angle_out_raw_o(1), 
        angle_out_raw_o(0) => HALL_INTERFACE_1_angle_out_raw_o(0), 
        theta_output_o(17) => HALL_INTERFACE_1_theta_output_o(17), 
        theta_output_o(16) => HALL_INTERFACE_1_theta_output_o(16), 
        theta_output_o(15) => HALL_INTERFACE_1_theta_output_o(15), 
        theta_output_o(14) => HALL_INTERFACE_1_theta_output_o(14), 
        theta_output_o(13) => HALL_INTERFACE_1_theta_output_o(13), 
        theta_output_o(12) => HALL_INTERFACE_1_theta_output_o(12), 
        theta_output_o(11) => \HALL_INTERFACE_1_theta_output_o_6\, 
        theta_output_o(10) => HALL_INTERFACE_1_theta_output_o(10), 
        theta_output_o(9) => \HALL_INTERFACE_1_theta_output_o_4\, 
        theta_output_o(8) => HALL_INTERFACE_1_theta_output_o(8), 
        theta_output_o(7) => HALL_INTERFACE_1_theta_output_o(7), 
        theta_output_o(6) => \HALL_INTERFACE_1_theta_output_o_1\, 
        theta_output_o(5) => \HALL_INTERFACE_1_theta_output_o_0\, 
        theta_output_o(4) => theta_output_o(4), theta_output_o(3)
         => theta_output_o(3), theta_output_o(2) => 
        theta_output_o(2), theta_output_o(1) => theta_output_o(1), 
        theta_output_o(0) => theta_output_o(0));
    
    apb3_hall_if_0 : apb3_hall_if
      port map(apb3_en_if_1_idq_pi_ki_o(17) => 
        apb3_en_if_1_idq_pi_ki_o(17), 
        apb3_en_if_1_idq_pi_ki_o(16) => 
        apb3_en_if_1_idq_pi_ki_o(16), 
        apb3_en_if_1_idq_pi_ki_o(15) => 
        apb3_en_if_1_idq_pi_ki_o(15), 
        apb3_en_if_1_idq_pi_ki_o(14) => 
        apb3_en_if_1_idq_pi_ki_o(14), 
        apb3_en_if_1_idq_pi_ki_o(13) => 
        apb3_en_if_1_idq_pi_ki_o(13), 
        apb3_en_if_1_idq_pi_ki_o(12) => 
        apb3_en_if_1_idq_pi_ki_o(12), 
        apb3_en_if_1_idq_pi_ki_o(11) => 
        apb3_en_if_1_idq_pi_ki_o(11), 
        apb3_en_if_1_idq_pi_ki_o(10) => 
        apb3_en_if_1_idq_pi_ki_o(10), apb3_en_if_1_idq_pi_ki_o(9)
         => apb3_en_if_1_idq_pi_ki_o(9), 
        apb3_en_if_1_idq_pi_ki_o(8) => 
        apb3_en_if_1_idq_pi_ki_o(8), apb3_en_if_1_idq_pi_ki_o(7)
         => apb3_en_if_1_idq_pi_ki_o(7), 
        apb3_en_if_1_idq_pi_ki_o(6) => 
        apb3_en_if_1_idq_pi_ki_o(6), apb3_en_if_1_idq_pi_ki_o(5)
         => apb3_en_if_1_idq_pi_ki_o(5), 
        apb3_en_if_1_idq_pi_ki_o(4) => 
        apb3_en_if_1_idq_pi_ki_o(4), apb3_en_if_1_idq_pi_ki_o(3)
         => apb3_en_if_1_idq_pi_ki_o(3), 
        apb3_en_if_1_idq_pi_ki_o(2) => 
        apb3_en_if_1_idq_pi_ki_o(2), apb3_en_if_1_idq_pi_ki_o(1)
         => apb3_en_if_1_idq_pi_ki_o(1), 
        apb3_en_if_1_idq_pi_ki_o(0) => 
        apb3_en_if_1_idq_pi_ki_o(0), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(17) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(17), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(16) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(16), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(15) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(15), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(14) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(14), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(13) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(13), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(12) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(12), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(11) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(11), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(10) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(10), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(9) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(9), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(8) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(8), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(7) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(7), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(6) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(6), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(5) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(5), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(4) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(4), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(3) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(3), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(2) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(2), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(1) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(1), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(0) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(0), 
        apb3_en_if_1_idq_pi_kp_o(17) => 
        apb3_en_if_1_idq_pi_kp_o(17), 
        apb3_en_if_1_idq_pi_kp_o(16) => 
        apb3_en_if_1_idq_pi_kp_o(16), 
        apb3_en_if_1_idq_pi_kp_o(15) => 
        apb3_en_if_1_idq_pi_kp_o(15), 
        apb3_en_if_1_idq_pi_kp_o(14) => 
        apb3_en_if_1_idq_pi_kp_o(14), 
        apb3_en_if_1_idq_pi_kp_o(13) => 
        apb3_en_if_1_idq_pi_kp_o(13), 
        apb3_en_if_1_idq_pi_kp_o(12) => 
        apb3_en_if_1_idq_pi_kp_o(12), 
        apb3_en_if_1_idq_pi_kp_o(11) => 
        apb3_en_if_1_idq_pi_kp_o(11), 
        apb3_en_if_1_idq_pi_kp_o(10) => 
        apb3_en_if_1_idq_pi_kp_o(10), apb3_en_if_1_idq_pi_kp_o(9)
         => apb3_en_if_1_idq_pi_kp_o(9), 
        apb3_en_if_1_idq_pi_kp_o(8) => 
        apb3_en_if_1_idq_pi_kp_o(8), apb3_en_if_1_idq_pi_kp_o(7)
         => apb3_en_if_1_idq_pi_kp_o(7), 
        apb3_en_if_1_idq_pi_kp_o(6) => 
        apb3_en_if_1_idq_pi_kp_o(6), apb3_en_if_1_idq_pi_kp_o(5)
         => apb3_en_if_1_idq_pi_kp_o(5), 
        apb3_en_if_1_idq_pi_kp_o(4) => 
        apb3_en_if_1_idq_pi_kp_o(4), apb3_en_if_1_idq_pi_kp_o(3)
         => apb3_en_if_1_idq_pi_kp_o(3), 
        apb3_en_if_1_idq_pi_kp_o(2) => 
        apb3_en_if_1_idq_pi_kp_o(2), apb3_en_if_1_idq_pi_kp_o(1)
         => apb3_en_if_1_idq_pi_kp_o(1), 
        apb3_en_if_1_idq_pi_kp_o(0) => 
        apb3_en_if_1_idq_pi_kp_o(0), apb3_en_if_1_olmng_dv_o(17)
         => apb3_en_if_1_olmng_dv_o(17), 
        apb3_en_if_1_olmng_dv_o(16) => 
        apb3_en_if_1_olmng_dv_o(16), apb3_en_if_1_olmng_dv_o(15)
         => apb3_en_if_1_olmng_dv_o(15), 
        apb3_en_if_1_olmng_dv_o(14) => 
        apb3_en_if_1_olmng_dv_o(14), apb3_en_if_1_olmng_dv_o(13)
         => apb3_en_if_1_olmng_dv_o(13), 
        apb3_en_if_1_olmng_dv_o(12) => 
        apb3_en_if_1_olmng_dv_o(12), apb3_en_if_1_olmng_dv_o(11)
         => apb3_en_if_1_olmng_dv_o(11), 
        apb3_en_if_1_olmng_dv_o(10) => 
        apb3_en_if_1_olmng_dv_o(10), apb3_en_if_1_olmng_dv_o(9)
         => apb3_en_if_1_olmng_dv_o(9), 
        apb3_en_if_1_olmng_dv_o(8) => apb3_en_if_1_olmng_dv_o(8), 
        apb3_en_if_1_olmng_dv_o(7) => apb3_en_if_1_olmng_dv_o(7), 
        apb3_en_if_1_olmng_dv_o(6) => apb3_en_if_1_olmng_dv_o(6), 
        apb3_en_if_1_olmng_dv_o(5) => apb3_en_if_1_olmng_dv_o(5), 
        apb3_en_if_1_olmng_dv_o(4) => apb3_en_if_1_olmng_dv_o(4), 
        apb3_en_if_1_olmng_dv_o(3) => apb3_en_if_1_olmng_dv_o(3), 
        apb3_en_if_1_olmng_dv_o(2) => apb3_en_if_1_olmng_dv_o(2), 
        apb3_en_if_1_olmng_dv_o(1) => apb3_en_if_1_olmng_dv_o(1), 
        apb3_en_if_1_olmng_dv_o(0) => apb3_en_if_1_olmng_dv_o(0), 
        apb3_en_if_1_olmng_iq_ref_in_o(17) => 
        apb3_en_if_1_olmng_iq_ref_in_o(17), 
        apb3_en_if_1_olmng_iq_ref_in_o(16) => 
        apb3_en_if_1_olmng_iq_ref_in_o(16), 
        apb3_en_if_1_olmng_iq_ref_in_o(15) => 
        apb3_en_if_1_olmng_iq_ref_in_o(15), 
        apb3_en_if_1_olmng_iq_ref_in_o(14) => 
        apb3_en_if_1_olmng_iq_ref_in_o(14), 
        apb3_en_if_1_olmng_iq_ref_in_o(13) => 
        apb3_en_if_1_olmng_iq_ref_in_o(13), 
        apb3_en_if_1_olmng_iq_ref_in_o(12) => 
        apb3_en_if_1_olmng_iq_ref_in_o(12), 
        apb3_en_if_1_olmng_iq_ref_in_o(11) => 
        apb3_en_if_1_olmng_iq_ref_in_o(11), 
        apb3_en_if_1_olmng_iq_ref_in_o(10) => 
        apb3_en_if_1_olmng_iq_ref_in_o(10), 
        apb3_en_if_1_olmng_iq_ref_in_o(9) => 
        apb3_en_if_1_olmng_iq_ref_in_o(9), 
        apb3_en_if_1_olmng_iq_ref_in_o(8) => 
        apb3_en_if_1_olmng_iq_ref_in_o(8), 
        apb3_en_if_1_olmng_iq_ref_in_o(7) => 
        apb3_en_if_1_olmng_iq_ref_in_o(7), 
        apb3_en_if_1_olmng_iq_ref_in_o(6) => 
        apb3_en_if_1_olmng_iq_ref_in_o(6), 
        apb3_en_if_1_olmng_iq_ref_in_o(5) => 
        apb3_en_if_1_olmng_iq_ref_in_o(5), 
        apb3_en_if_1_olmng_iq_ref_in_o(4) => 
        apb3_en_if_1_olmng_iq_ref_in_o(4), 
        apb3_en_if_1_olmng_iq_ref_in_o(3) => 
        apb3_en_if_1_olmng_iq_ref_in_o(3), 
        apb3_en_if_1_olmng_iq_ref_in_o(2) => 
        apb3_en_if_1_olmng_iq_ref_in_o(2), 
        apb3_en_if_1_olmng_iq_ref_in_o(1) => 
        apb3_en_if_1_olmng_iq_ref_in_o(1), 
        apb3_en_if_1_olmng_iq_ref_in_o(0) => 
        apb3_en_if_1_olmng_iq_ref_in_o(0), 
        apb3_en_if_1_olmng_theta_factor_o(17) => 
        apb3_en_if_1_olmng_theta_factor_o(17), 
        apb3_en_if_1_olmng_theta_factor_o(16) => 
        apb3_en_if_1_olmng_theta_factor_o(16), 
        apb3_en_if_1_olmng_theta_factor_o(15) => 
        apb3_en_if_1_olmng_theta_factor_o(15), 
        apb3_en_if_1_olmng_theta_factor_o(14) => 
        apb3_en_if_1_olmng_theta_factor_o(14), 
        apb3_en_if_1_olmng_theta_factor_o(13) => 
        apb3_en_if_1_olmng_theta_factor_o(13), 
        apb3_en_if_1_olmng_theta_factor_o(12) => 
        apb3_en_if_1_olmng_theta_factor_o(12), 
        apb3_en_if_1_olmng_theta_factor_o(11) => 
        apb3_en_if_1_olmng_theta_factor_o(11), 
        apb3_en_if_1_olmng_theta_factor_o(10) => 
        apb3_en_if_1_olmng_theta_factor_o(10), 
        apb3_en_if_1_olmng_theta_factor_o(9) => 
        apb3_en_if_1_olmng_theta_factor_o(9), 
        apb3_en_if_1_olmng_theta_factor_o(8) => 
        apb3_en_if_1_olmng_theta_factor_o(8), 
        apb3_en_if_1_olmng_theta_factor_o(7) => 
        apb3_en_if_1_olmng_theta_factor_o(7), 
        apb3_en_if_1_olmng_theta_factor_o(6) => 
        apb3_en_if_1_olmng_theta_factor_o(6), 
        apb3_en_if_1_olmng_theta_factor_o(5) => 
        apb3_en_if_1_olmng_theta_factor_o(5), 
        apb3_en_if_1_olmng_theta_factor_o(4) => 
        apb3_en_if_1_olmng_theta_factor_o(4), 
        apb3_en_if_1_olmng_theta_factor_o(3) => 
        apb3_en_if_1_olmng_theta_factor_o(3), 
        apb3_en_if_1_olmng_theta_factor_o(2) => 
        apb3_en_if_1_olmng_theta_factor_o(2), 
        apb3_en_if_1_olmng_theta_factor_o(1) => 
        apb3_en_if_1_olmng_theta_factor_o(1), 
        apb3_en_if_1_olmng_theta_factor_o(0) => 
        apb3_en_if_1_olmng_theta_factor_o(0), 
        apb3_en_if_1_pwm_dead_time_val_o(17) => 
        apb3_en_if_1_pwm_dead_time_val_o(17), 
        apb3_en_if_1_pwm_dead_time_val_o(16) => 
        apb3_en_if_1_pwm_dead_time_val_o(16), 
        apb3_en_if_1_pwm_dead_time_val_o(15) => 
        apb3_en_if_1_pwm_dead_time_val_o(15), 
        apb3_en_if_1_pwm_dead_time_val_o(14) => 
        apb3_en_if_1_pwm_dead_time_val_o(14), 
        apb3_en_if_1_pwm_dead_time_val_o(13) => 
        apb3_en_if_1_pwm_dead_time_val_o(13), 
        apb3_en_if_1_pwm_dead_time_val_o(12) => 
        apb3_en_if_1_pwm_dead_time_val_o(12), 
        apb3_en_if_1_pwm_dead_time_val_o(11) => 
        apb3_en_if_1_pwm_dead_time_val_o(11), 
        apb3_en_if_1_pwm_dead_time_val_o(10) => 
        apb3_en_if_1_pwm_dead_time_val_o(10), 
        apb3_en_if_1_pwm_dead_time_val_o(9) => 
        apb3_en_if_1_pwm_dead_time_val_o(9), 
        apb3_en_if_1_pwm_dead_time_val_o(8) => 
        apb3_en_if_1_pwm_dead_time_val_o(8), 
        apb3_en_if_1_pwm_dead_time_val_o(7) => 
        apb3_en_if_1_pwm_dead_time_val_o(7), 
        apb3_en_if_1_pwm_dead_time_val_o(6) => 
        apb3_en_if_1_pwm_dead_time_val_o(6), 
        apb3_en_if_1_pwm_dead_time_val_o(5) => 
        apb3_en_if_1_pwm_dead_time_val_o(5), 
        apb3_en_if_1_pwm_dead_time_val_o(4) => 
        apb3_en_if_1_pwm_dead_time_val_o(4), 
        apb3_en_if_1_pwm_dead_time_val_o(3) => 
        apb3_en_if_1_pwm_dead_time_val_o(3), 
        apb3_en_if_1_pwm_dead_time_val_o(2) => 
        apb3_en_if_1_pwm_dead_time_val_o(2), 
        apb3_en_if_1_pwm_dead_time_val_o(1) => 
        apb3_en_if_1_pwm_dead_time_val_o(1), 
        apb3_en_if_1_pwm_dead_time_val_o(0) => 
        apb3_en_if_1_pwm_dead_time_val_o(0), 
        apb3_en_if_1_pwm_delay_time_val_o(17) => 
        apb3_en_if_1_pwm_delay_time_val_o(17), 
        apb3_en_if_1_pwm_delay_time_val_o(16) => 
        apb3_en_if_1_pwm_delay_time_val_o(16), 
        apb3_en_if_1_pwm_delay_time_val_o(15) => 
        apb3_en_if_1_pwm_delay_time_val_o(15), 
        apb3_en_if_1_pwm_delay_time_val_o(14) => 
        apb3_en_if_1_pwm_delay_time_val_o(14), 
        apb3_en_if_1_pwm_delay_time_val_o(13) => 
        apb3_en_if_1_pwm_delay_time_val_o(13), 
        apb3_en_if_1_pwm_delay_time_val_o(12) => 
        apb3_en_if_1_pwm_delay_time_val_o(12), 
        apb3_en_if_1_pwm_delay_time_val_o(11) => 
        apb3_en_if_1_pwm_delay_time_val_o(11), 
        apb3_en_if_1_pwm_delay_time_val_o(10) => 
        apb3_en_if_1_pwm_delay_time_val_o(10), 
        apb3_en_if_1_pwm_delay_time_val_o(9) => 
        apb3_en_if_1_pwm_delay_time_val_o(9), 
        apb3_en_if_1_pwm_delay_time_val_o(8) => 
        apb3_en_if_1_pwm_delay_time_val_o(8), 
        apb3_en_if_1_pwm_delay_time_val_o(7) => 
        apb3_en_if_1_pwm_delay_time_val_o(7), 
        apb3_en_if_1_pwm_delay_time_val_o(6) => 
        apb3_en_if_1_pwm_delay_time_val_o(6), 
        apb3_en_if_1_pwm_delay_time_val_o(5) => 
        apb3_en_if_1_pwm_delay_time_val_o(5), 
        apb3_en_if_1_pwm_delay_time_val_o(4) => 
        apb3_en_if_1_pwm_delay_time_val_o(4), 
        apb3_en_if_1_pwm_delay_time_val_o(3) => 
        apb3_en_if_1_pwm_delay_time_val_o(3), 
        apb3_en_if_1_pwm_delay_time_val_o(2) => 
        apb3_en_if_1_pwm_delay_time_val_o(2), 
        apb3_en_if_1_pwm_delay_time_val_o(1) => 
        apb3_en_if_1_pwm_delay_time_val_o(1), 
        apb3_en_if_1_pwm_delay_time_val_o(0) => 
        apb3_en_if_1_pwm_delay_time_val_o(0), 
        apb3_en_if_1_pwm_gain_val_o(17) => 
        apb3_en_if_1_pwm_gain_val_o(17), 
        apb3_en_if_1_pwm_gain_val_o(16) => 
        apb3_en_if_1_pwm_gain_val_o(16), 
        apb3_en_if_1_pwm_gain_val_o(15) => 
        apb3_en_if_1_pwm_gain_val_o(15), 
        apb3_en_if_1_pwm_gain_val_o(14) => 
        apb3_en_if_1_pwm_gain_val_o(14), 
        apb3_en_if_1_pwm_gain_val_o(13) => 
        apb3_en_if_1_pwm_gain_val_o(13), 
        apb3_en_if_1_pwm_gain_val_o(12) => 
        apb3_en_if_1_pwm_gain_val_o(12), 
        apb3_en_if_1_pwm_gain_val_o(11) => 
        apb3_en_if_1_pwm_gain_val_o(11), 
        apb3_en_if_1_pwm_gain_val_o(10) => 
        apb3_en_if_1_pwm_gain_val_o(10), 
        apb3_en_if_1_pwm_gain_val_o(9) => 
        apb3_en_if_1_pwm_gain_val_o(9), 
        apb3_en_if_1_pwm_gain_val_o(8) => 
        apb3_en_if_1_pwm_gain_val_o(8), 
        apb3_en_if_1_pwm_gain_val_o(7) => 
        apb3_en_if_1_pwm_gain_val_o(7), 
        apb3_en_if_1_pwm_gain_val_o(6) => 
        apb3_en_if_1_pwm_gain_val_o(6), 
        apb3_en_if_1_pwm_gain_val_o(5) => 
        apb3_en_if_1_pwm_gain_val_o(5), 
        apb3_en_if_1_pwm_gain_val_o(4) => 
        apb3_en_if_1_pwm_gain_val_o(4), 
        apb3_en_if_1_pwm_gain_val_o(3) => 
        apb3_en_if_1_pwm_gain_val_o(3), 
        apb3_en_if_1_pwm_gain_val_o(2) => 
        apb3_en_if_1_pwm_gain_val_o(2), 
        apb3_en_if_1_pwm_gain_val_o(1) => 
        apb3_en_if_1_pwm_gain_val_o(1), 
        apb3_en_if_1_pwm_period_val_o(17) => 
        apb3_en_if_1_pwm_period_val_o(17), 
        apb3_en_if_1_pwm_period_val_o(16) => 
        apb3_en_if_1_pwm_period_val_o(16), 
        apb3_en_if_1_pwm_period_val_o(15) => 
        apb3_en_if_1_pwm_period_val_o(15), 
        apb3_en_if_1_pwm_period_val_o(14) => 
        apb3_en_if_1_pwm_period_val_o(14), 
        apb3_en_if_1_pwm_period_val_o(13) => 
        apb3_en_if_1_pwm_period_val_o(13), 
        apb3_en_if_1_pwm_period_val_o(12) => 
        apb3_en_if_1_pwm_period_val_o(12), 
        apb3_en_if_1_pwm_period_val_o(11) => 
        apb3_en_if_1_pwm_period_val_o(11), 
        apb3_en_if_1_pwm_period_val_o(10) => 
        apb3_en_if_1_pwm_period_val_o(10), 
        apb3_en_if_1_pwm_period_val_o(9) => 
        apb3_en_if_1_pwm_period_val_o(9), 
        apb3_en_if_1_pwm_period_val_o(8) => 
        apb3_en_if_1_pwm_period_val_o(8), 
        apb3_en_if_1_pwm_period_val_o(7) => 
        apb3_en_if_1_pwm_period_val_o(7), 
        apb3_en_if_1_pwm_period_val_o(6) => 
        apb3_en_if_1_pwm_period_val_o(6), 
        apb3_en_if_1_pwm_period_val_o(5) => 
        apb3_en_if_1_pwm_period_val_o(5), 
        apb3_en_if_1_pwm_period_val_o(4) => 
        apb3_en_if_1_pwm_period_val_o(4), 
        apb3_en_if_1_pwm_period_val_o(3) => 
        apb3_en_if_1_pwm_period_val_o(3), 
        apb3_en_if_1_pwm_period_val_o(2) => 
        apb3_en_if_1_pwm_period_val_o(2), 
        apb3_en_if_1_pwm_period_val_o(1) => 
        apb3_en_if_1_pwm_period_val_o(1), 
        apb3_en_if_1_pwm_period_val_o(0) => 
        apb3_en_if_1_pwm_period_val_o(0), 
        apb3_en_if_1_rate_limit_rate_cnt_o(17) => 
        apb3_en_if_1_rate_limit_rate_cnt_o(17), 
        apb3_en_if_1_rate_limit_rate_cnt_o(16) => 
        apb3_en_if_1_rate_limit_rate_cnt_o(16), 
        apb3_en_if_1_rate_limit_rate_cnt_o(15) => 
        apb3_en_if_1_rate_limit_rate_cnt_o(15), 
        apb3_en_if_1_rate_limit_rate_cnt_o(14) => 
        apb3_en_if_1_rate_limit_rate_cnt_o(14), 
        apb3_en_if_1_rate_limit_rate_cnt_o(13) => 
        apb3_en_if_1_rate_limit_rate_cnt_o(13), 
        apb3_en_if_1_rate_limit_rate_cnt_o(12) => 
        apb3_en_if_1_rate_limit_rate_cnt_o(12), 
        apb3_en_if_1_rate_limit_rate_cnt_o(11) => 
        apb3_en_if_1_rate_limit_rate_cnt_o(11), 
        apb3_en_if_1_rate_limit_rate_cnt_o(10) => 
        apb3_en_if_1_rate_limit_rate_cnt_o(10), 
        apb3_en_if_1_rate_limit_rate_cnt_o(9) => 
        apb3_en_if_1_rate_limit_rate_cnt_o(9), 
        apb3_en_if_1_rate_limit_rate_cnt_o(8) => 
        apb3_en_if_1_rate_limit_rate_cnt_o(8), 
        apb3_en_if_1_rate_limit_rate_cnt_o(7) => 
        apb3_en_if_1_rate_limit_rate_cnt_o(7), 
        apb3_en_if_1_rate_limit_rate_cnt_o(6) => 
        apb3_en_if_1_rate_limit_rate_cnt_o(6), 
        apb3_en_if_1_rate_limit_rate_cnt_o(5) => 
        apb3_en_if_1_rate_limit_rate_cnt_o(5), 
        apb3_en_if_1_rate_limit_rate_cnt_o(4) => 
        apb3_en_if_1_rate_limit_rate_cnt_o(4), 
        apb3_en_if_1_rate_limit_rate_cnt_o(3) => 
        apb3_en_if_1_rate_limit_rate_cnt_o(3), 
        apb3_en_if_1_rate_limit_rate_cnt_o(2) => 
        apb3_en_if_1_rate_limit_rate_cnt_o(2), 
        apb3_en_if_1_rate_limit_rate_cnt_o(1) => 
        apb3_en_if_1_rate_limit_rate_cnt_o(1), 
        apb3_en_if_1_rate_limit_rate_cnt_o(0) => 
        apb3_en_if_1_rate_limit_rate_cnt_o(0), 
        apb3_en_if_1_rate_limit_ref_in_o(17) => 
        apb3_en_if_1_rate_limit_ref_in_o(17), 
        apb3_en_if_1_rate_limit_ref_in_o(16) => 
        apb3_en_if_1_rate_limit_ref_in_o(16), 
        apb3_en_if_1_rate_limit_ref_in_o(15) => 
        apb3_en_if_1_rate_limit_ref_in_o(15), 
        apb3_en_if_1_rate_limit_ref_in_o(14) => 
        apb3_en_if_1_rate_limit_ref_in_o(14), 
        apb3_en_if_1_rate_limit_ref_in_o(13) => 
        apb3_en_if_1_rate_limit_ref_in_o(13), 
        apb3_en_if_1_rate_limit_ref_in_o(12) => 
        apb3_en_if_1_rate_limit_ref_in_o(12), 
        apb3_en_if_1_rate_limit_ref_in_o(11) => 
        apb3_en_if_1_rate_limit_ref_in_o(11), 
        apb3_en_if_1_rate_limit_ref_in_o(10) => 
        apb3_en_if_1_rate_limit_ref_in_o(10), 
        apb3_en_if_1_rate_limit_ref_in_o(9) => 
        apb3_en_if_1_rate_limit_ref_in_o(9), 
        apb3_en_if_1_rate_limit_ref_in_o(8) => 
        apb3_en_if_1_rate_limit_ref_in_o(8), 
        apb3_en_if_1_rate_limit_ref_in_o(7) => 
        apb3_en_if_1_rate_limit_ref_in_o(7), 
        apb3_en_if_1_rate_limit_ref_in_o(6) => 
        apb3_en_if_1_rate_limit_ref_in_o(6), 
        apb3_en_if_1_rate_limit_ref_in_o(5) => 
        apb3_en_if_1_rate_limit_ref_in_o(5), 
        apb3_en_if_1_rate_limit_ref_in_o(4) => 
        apb3_en_if_1_rate_limit_ref_in_o(4), 
        apb3_en_if_1_rate_limit_ref_in_o(3) => 
        apb3_en_if_1_rate_limit_ref_in_o(3), 
        apb3_en_if_1_rate_limit_ref_in_o(2) => 
        apb3_en_if_1_rate_limit_ref_in_o(2), 
        apb3_en_if_1_rate_limit_ref_in_o(1) => 
        apb3_en_if_1_rate_limit_ref_in_o(1), 
        apb3_en_if_1_rate_limit_ref_in_o(0) => 
        apb3_en_if_1_rate_limit_ref_in_o(0), 
        apb3_en_if_1_rate_limit_slew_cnt_o(17) => 
        apb3_en_if_1_rate_limit_slew_cnt_o(17), 
        apb3_en_if_1_rate_limit_slew_cnt_o(16) => 
        apb3_en_if_1_rate_limit_slew_cnt_o(16), 
        apb3_en_if_1_rate_limit_slew_cnt_o(15) => 
        apb3_en_if_1_rate_limit_slew_cnt_o(15), 
        apb3_en_if_1_rate_limit_slew_cnt_o(14) => 
        apb3_en_if_1_rate_limit_slew_cnt_o(14), 
        apb3_en_if_1_rate_limit_slew_cnt_o(13) => 
        apb3_en_if_1_rate_limit_slew_cnt_o(13), 
        apb3_en_if_1_rate_limit_slew_cnt_o(12) => 
        apb3_en_if_1_rate_limit_slew_cnt_o(12), 
        apb3_en_if_1_rate_limit_slew_cnt_o(11) => 
        apb3_en_if_1_rate_limit_slew_cnt_o(11), 
        apb3_en_if_1_rate_limit_slew_cnt_o(10) => 
        apb3_en_if_1_rate_limit_slew_cnt_o(10), 
        apb3_en_if_1_rate_limit_slew_cnt_o(9) => 
        apb3_en_if_1_rate_limit_slew_cnt_o(9), 
        apb3_en_if_1_rate_limit_slew_cnt_o(8) => 
        apb3_en_if_1_rate_limit_slew_cnt_o(8), 
        apb3_en_if_1_rate_limit_slew_cnt_o(7) => 
        apb3_en_if_1_rate_limit_slew_cnt_o(7), 
        apb3_en_if_1_rate_limit_slew_cnt_o(6) => 
        apb3_en_if_1_rate_limit_slew_cnt_o(6), 
        apb3_en_if_1_rate_limit_slew_cnt_o(5) => 
        apb3_en_if_1_rate_limit_slew_cnt_o(5), 
        apb3_en_if_1_rate_limit_slew_cnt_o(4) => 
        apb3_en_if_1_rate_limit_slew_cnt_o(4), 
        apb3_en_if_1_rate_limit_slew_cnt_o(3) => 
        apb3_en_if_1_rate_limit_slew_cnt_o(3), 
        apb3_en_if_1_rate_limit_slew_cnt_o(2) => 
        apb3_en_if_1_rate_limit_slew_cnt_o(2), 
        apb3_en_if_1_rate_limit_slew_cnt_o(1) => 
        apb3_en_if_1_rate_limit_slew_cnt_o(1), 
        apb3_en_if_1_rate_limit_slew_cnt_o(0) => 
        apb3_en_if_1_rate_limit_slew_cnt_o(0), 
        apb3_en_if_1_seq_cntl_cl_omega_o(17) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(17), 
        apb3_en_if_1_seq_cntl_cl_omega_o(16) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(16), 
        apb3_en_if_1_seq_cntl_cl_omega_o(15) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(15), 
        apb3_en_if_1_seq_cntl_cl_omega_o(14) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(14), 
        apb3_en_if_1_seq_cntl_cl_omega_o(13) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(13), 
        apb3_en_if_1_seq_cntl_cl_omega_o(12) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(12), 
        apb3_en_if_1_seq_cntl_cl_omega_o(11) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(11), 
        apb3_en_if_1_seq_cntl_cl_omega_o(10) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(10), 
        apb3_en_if_1_seq_cntl_cl_omega_o(9) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(9), 
        apb3_en_if_1_seq_cntl_cl_omega_o(8) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(8), 
        apb3_en_if_1_seq_cntl_cl_omega_o(7) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(7), 
        apb3_en_if_1_seq_cntl_cl_omega_o(6) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(6), 
        apb3_en_if_1_seq_cntl_cl_omega_o(5) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(5), 
        apb3_en_if_1_seq_cntl_cl_omega_o(4) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(4), 
        apb3_en_if_1_seq_cntl_cl_omega_o(3) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(3), 
        apb3_en_if_1_seq_cntl_cl_omega_o(2) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(2), 
        apb3_en_if_1_seq_cntl_cl_omega_o(1) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(1), 
        apb3_en_if_1_seq_cntl_cl_omega_o(0) => 
        apb3_en_if_1_seq_cntl_cl_omega_o(0), 
        apb3_en_if_1_speed_pi_ki_o(17) => 
        apb3_en_if_1_speed_pi_ki_o(17), 
        apb3_en_if_1_speed_pi_ki_o(16) => 
        apb3_en_if_1_speed_pi_ki_o(16), 
        apb3_en_if_1_speed_pi_ki_o(15) => 
        apb3_en_if_1_speed_pi_ki_o(15), 
        apb3_en_if_1_speed_pi_ki_o(14) => 
        apb3_en_if_1_speed_pi_ki_o(14), 
        apb3_en_if_1_speed_pi_ki_o(13) => 
        apb3_en_if_1_speed_pi_ki_o(13), 
        apb3_en_if_1_speed_pi_ki_o(12) => 
        apb3_en_if_1_speed_pi_ki_o(12), 
        apb3_en_if_1_speed_pi_ki_o(11) => 
        apb3_en_if_1_speed_pi_ki_o(11), 
        apb3_en_if_1_speed_pi_ki_o(10) => 
        apb3_en_if_1_speed_pi_ki_o(10), 
        apb3_en_if_1_speed_pi_ki_o(9) => 
        apb3_en_if_1_speed_pi_ki_o(9), 
        apb3_en_if_1_speed_pi_ki_o(8) => 
        apb3_en_if_1_speed_pi_ki_o(8), 
        apb3_en_if_1_speed_pi_ki_o(7) => 
        apb3_en_if_1_speed_pi_ki_o(7), 
        apb3_en_if_1_speed_pi_ki_o(6) => 
        apb3_en_if_1_speed_pi_ki_o(6), 
        apb3_en_if_1_speed_pi_ki_o(5) => 
        apb3_en_if_1_speed_pi_ki_o(5), 
        apb3_en_if_1_speed_pi_ki_o(4) => 
        apb3_en_if_1_speed_pi_ki_o(4), 
        apb3_en_if_1_speed_pi_ki_o(3) => 
        apb3_en_if_1_speed_pi_ki_o(3), 
        apb3_en_if_1_speed_pi_ki_o(2) => 
        apb3_en_if_1_speed_pi_ki_o(2), 
        apb3_en_if_1_speed_pi_ki_o(1) => 
        apb3_en_if_1_speed_pi_ki_o(1), 
        apb3_en_if_1_speed_pi_ki_o(0) => 
        apb3_en_if_1_speed_pi_ki_o(0), 
        apb3_en_if_1_speed_pi_kp_o(17) => 
        apb3_en_if_1_speed_pi_kp_o(17), 
        apb3_en_if_1_speed_pi_kp_o(16) => 
        apb3_en_if_1_speed_pi_kp_o(16), 
        apb3_en_if_1_speed_pi_kp_o(15) => 
        apb3_en_if_1_speed_pi_kp_o(15), 
        apb3_en_if_1_speed_pi_kp_o(14) => 
        apb3_en_if_1_speed_pi_kp_o(14), 
        apb3_en_if_1_speed_pi_kp_o(13) => 
        apb3_en_if_1_speed_pi_kp_o(13), 
        apb3_en_if_1_speed_pi_kp_o(12) => 
        apb3_en_if_1_speed_pi_kp_o(12), 
        apb3_en_if_1_speed_pi_kp_o(11) => 
        apb3_en_if_1_speed_pi_kp_o(11), 
        apb3_en_if_1_speed_pi_kp_o(10) => 
        apb3_en_if_1_speed_pi_kp_o(10), 
        apb3_en_if_1_speed_pi_kp_o(9) => 
        apb3_en_if_1_speed_pi_kp_o(9), 
        apb3_en_if_1_speed_pi_kp_o(8) => 
        apb3_en_if_1_speed_pi_kp_o(8), 
        apb3_en_if_1_speed_pi_kp_o(7) => 
        apb3_en_if_1_speed_pi_kp_o(7), 
        apb3_en_if_1_speed_pi_kp_o(6) => 
        apb3_en_if_1_speed_pi_kp_o(6), 
        apb3_en_if_1_speed_pi_kp_o(5) => 
        apb3_en_if_1_speed_pi_kp_o(5), 
        apb3_en_if_1_speed_pi_kp_o(4) => 
        apb3_en_if_1_speed_pi_kp_o(4), 
        apb3_en_if_1_speed_pi_kp_o(3) => 
        apb3_en_if_1_speed_pi_kp_o(3), 
        apb3_en_if_1_speed_pi_kp_o(2) => 
        apb3_en_if_1_speed_pi_kp_o(2), 
        apb3_en_if_1_speed_pi_kp_o(1) => 
        apb3_en_if_1_speed_pi_kp_o(1), 
        apb3_en_if_1_speed_pi_kp_o(0) => 
        apb3_en_if_1_speed_pi_kp_o(0), 
        apb3_en_if_1_seq_cntl_config_o(3) => 
        apb3_en_if_1_seq_cntl_config_o(3), 
        apb3_en_if_1_seq_cntl_config_o(2) => 
        apb3_en_if_1_seq_cntl_config_o(2), 
        apb3_en_if_1_seq_cntl_config_o(1) => 
        apb3_en_if_1_seq_cntl_config_o(1), 
        apb3_en_if_1_seq_cntl_config_o(0) => 
        apb3_en_if_1_seq_cntl_config_o(0), 
        apb3_hall_if_0_hall_filter_factor_o(3) => 
        apb3_hall_if_0_hall_filter_factor_o(3), 
        apb3_hall_if_0_hall_filter_factor_o(2) => 
        apb3_hall_if_0_hall_filter_factor_o(2), 
        apb3_hall_if_0_hall_filter_factor_o(1) => 
        apb3_hall_if_0_hall_filter_factor_o(1), 
        apb3_hall_if_0_hall_filter_factor_o(0) => 
        apb3_hall_if_0_hall_filter_factor_o(0), 
        apb3_en_if_1_auto_restart_no_o(3) => 
        apb3_en_if_1_auto_restart_no_o(3), 
        apb3_en_if_1_auto_restart_no_o(2) => 
        apb3_en_if_1_auto_restart_no_o(2), 
        apb3_en_if_1_auto_restart_no_o(1) => 
        apb3_en_if_1_auto_restart_no_o(1), 
        apb3_en_if_1_auto_restart_no_o(0) => 
        apb3_en_if_1_auto_restart_no_o(0), 
        apb3_en_if_1_adc_control_reg_val_o(5) => 
        apb3_en_if_1_adc_control_reg_val_o(5), 
        apb3_en_if_1_adc_control_reg_val_o(4) => 
        apb3_en_if_1_adc_control_reg_val_o(4), 
        apb3_en_if_1_adc_control_reg_val_o(3) => 
        apb3_en_if_1_adc_control_reg_val_o(3), 
        apb3_en_if_1_adc_control_reg_val_o(2) => 
        apb3_en_if_1_adc_control_reg_val_o(2), 
        apb3_en_if_1_adc_control_reg_val_o(1) => 
        apb3_en_if_1_adc_control_reg_val_o(1), 
        apb3_en_if_1_adc_control_reg_val_o(0) => 
        apb3_en_if_1_adc_control_reg_val_o(0), 
        apb3_en_if_1_adc_channel_ch0_o(15) => 
        apb3_en_if_1_adc_channel_ch0_o(15), 
        apb3_en_if_1_adc_channel_ch0_o(14) => 
        apb3_en_if_1_adc_channel_ch0_o(14), 
        apb3_en_if_1_adc_channel_ch0_o(13) => 
        apb3_en_if_1_adc_channel_ch0_o(13), 
        apb3_en_if_1_adc_channel_ch0_o(12) => 
        apb3_en_if_1_adc_channel_ch0_o(12), 
        apb3_en_if_1_adc_channel_ch0_o(11) => 
        apb3_en_if_1_adc_channel_ch0_o(11), 
        apb3_en_if_1_adc_channel_ch0_o(10) => 
        apb3_en_if_1_adc_channel_ch0_o(10), 
        apb3_en_if_1_adc_channel_ch0_o(9) => 
        apb3_en_if_1_adc_channel_ch0_o(9), 
        apb3_en_if_1_adc_channel_ch0_o(8) => 
        apb3_en_if_1_adc_channel_ch0_o(8), 
        apb3_en_if_1_adc_channel_ch0_o(7) => 
        apb3_en_if_1_adc_channel_ch0_o(7), 
        apb3_en_if_1_adc_channel_ch0_o(6) => 
        apb3_en_if_1_adc_channel_ch0_o(6), 
        apb3_en_if_1_adc_channel_ch0_o(5) => 
        apb3_en_if_1_adc_channel_ch0_o(5), 
        apb3_en_if_1_adc_channel_ch0_o(4) => 
        apb3_en_if_1_adc_channel_ch0_o(4), 
        apb3_en_if_1_adc_channel_ch0_o(3) => 
        apb3_en_if_1_adc_channel_ch0_o(3), 
        apb3_en_if_1_adc_channel_ch0_o(2) => 
        apb3_en_if_1_adc_channel_ch0_o(2), 
        apb3_en_if_1_adc_channel_ch0_o(1) => 
        apb3_en_if_1_adc_channel_ch0_o(1), 
        apb3_en_if_1_adc_channel_ch0_o(0) => 
        apb3_en_if_1_adc_channel_ch0_o(0), 
        apb3_en_if_1_adc_channel_ch1_o(15) => 
        apb3_en_if_1_adc_channel_ch1_o(15), 
        apb3_en_if_1_adc_channel_ch1_o(14) => 
        apb3_en_if_1_adc_channel_ch1_o(14), 
        apb3_en_if_1_adc_channel_ch1_o(13) => 
        apb3_en_if_1_adc_channel_ch1_o(13), 
        apb3_en_if_1_adc_channel_ch1_o(12) => 
        apb3_en_if_1_adc_channel_ch1_o(12), 
        apb3_en_if_1_adc_channel_ch1_o(11) => 
        apb3_en_if_1_adc_channel_ch1_o(11), 
        apb3_en_if_1_adc_channel_ch1_o(10) => 
        apb3_en_if_1_adc_channel_ch1_o(10), 
        apb3_en_if_1_adc_channel_ch1_o(9) => 
        apb3_en_if_1_adc_channel_ch1_o(9), 
        apb3_en_if_1_adc_channel_ch1_o(8) => 
        apb3_en_if_1_adc_channel_ch1_o(8), 
        apb3_en_if_1_adc_channel_ch1_o(7) => 
        apb3_en_if_1_adc_channel_ch1_o(7), 
        apb3_en_if_1_adc_channel_ch1_o(6) => 
        apb3_en_if_1_adc_channel_ch1_o(6), 
        apb3_en_if_1_adc_channel_ch1_o(5) => 
        apb3_en_if_1_adc_channel_ch1_o(5), 
        apb3_en_if_1_adc_channel_ch1_o(4) => 
        apb3_en_if_1_adc_channel_ch1_o(4), 
        apb3_en_if_1_adc_channel_ch1_o(3) => 
        apb3_en_if_1_adc_channel_ch1_o(3), 
        apb3_en_if_1_adc_channel_ch1_o(2) => 
        apb3_en_if_1_adc_channel_ch1_o(2), 
        apb3_en_if_1_adc_channel_ch1_o(1) => 
        apb3_en_if_1_adc_channel_ch1_o(1), 
        apb3_en_if_1_adc_channel_ch1_o(0) => 
        apb3_en_if_1_adc_channel_ch1_o(0), 
        apb3_en_if_1_adc_channel_ch2_o(15) => 
        apb3_en_if_1_adc_channel_ch2_o(15), 
        apb3_en_if_1_adc_channel_ch2_o(14) => 
        apb3_en_if_1_adc_channel_ch2_o(14), 
        apb3_en_if_1_adc_channel_ch2_o(13) => 
        apb3_en_if_1_adc_channel_ch2_o(13), 
        apb3_en_if_1_adc_channel_ch2_o(12) => 
        apb3_en_if_1_adc_channel_ch2_o(12), 
        apb3_en_if_1_adc_channel_ch2_o(11) => 
        apb3_en_if_1_adc_channel_ch2_o(11), 
        apb3_en_if_1_adc_channel_ch2_o(10) => 
        apb3_en_if_1_adc_channel_ch2_o(10), 
        apb3_en_if_1_adc_channel_ch2_o(9) => 
        apb3_en_if_1_adc_channel_ch2_o(9), 
        apb3_en_if_1_adc_channel_ch2_o(8) => 
        apb3_en_if_1_adc_channel_ch2_o(8), 
        apb3_en_if_1_adc_channel_ch2_o(7) => 
        apb3_en_if_1_adc_channel_ch2_o(7), 
        apb3_en_if_1_adc_channel_ch2_o(6) => 
        apb3_en_if_1_adc_channel_ch2_o(6), 
        apb3_en_if_1_adc_channel_ch2_o(5) => 
        apb3_en_if_1_adc_channel_ch2_o(5), 
        apb3_en_if_1_adc_channel_ch2_o(4) => 
        apb3_en_if_1_adc_channel_ch2_o(4), 
        apb3_en_if_1_adc_channel_ch2_o(3) => 
        apb3_en_if_1_adc_channel_ch2_o(3), 
        apb3_en_if_1_adc_channel_ch2_o(2) => 
        apb3_en_if_1_adc_channel_ch2_o(2), 
        apb3_en_if_1_adc_channel_ch2_o(1) => 
        apb3_en_if_1_adc_channel_ch2_o(1), 
        apb3_en_if_1_adc_channel_ch2_o(0) => 
        apb3_en_if_1_adc_channel_ch2_o(0), 
        apb3_en_if_1_adc_channel_ch3_o(15) => 
        apb3_en_if_1_adc_channel_ch3_o(15), 
        apb3_en_if_1_adc_channel_ch3_o(14) => 
        apb3_en_if_1_adc_channel_ch3_o(14), 
        apb3_en_if_1_adc_channel_ch3_o(13) => 
        apb3_en_if_1_adc_channel_ch3_o(13), 
        apb3_en_if_1_adc_channel_ch3_o(12) => 
        apb3_en_if_1_adc_channel_ch3_o(12), 
        apb3_en_if_1_adc_channel_ch3_o(11) => 
        apb3_en_if_1_adc_channel_ch3_o(11), 
        apb3_en_if_1_adc_channel_ch3_o(10) => 
        apb3_en_if_1_adc_channel_ch3_o(10), 
        apb3_en_if_1_adc_channel_ch3_o(9) => 
        apb3_en_if_1_adc_channel_ch3_o(9), 
        apb3_en_if_1_adc_channel_ch3_o(8) => 
        apb3_en_if_1_adc_channel_ch3_o(8), 
        apb3_en_if_1_adc_channel_ch3_o(7) => 
        apb3_en_if_1_adc_channel_ch3_o(7), 
        apb3_en_if_1_adc_channel_ch3_o(6) => 
        apb3_en_if_1_adc_channel_ch3_o(6), 
        apb3_en_if_1_adc_channel_ch3_o(5) => 
        apb3_en_if_1_adc_channel_ch3_o(5), 
        apb3_en_if_1_adc_channel_ch3_o(4) => 
        apb3_en_if_1_adc_channel_ch3_o(4), 
        apb3_en_if_1_adc_channel_ch3_o(3) => 
        apb3_en_if_1_adc_channel_ch3_o(3), 
        apb3_en_if_1_adc_channel_ch3_o(2) => 
        apb3_en_if_1_adc_channel_ch3_o(2), 
        apb3_en_if_1_adc_channel_ch3_o(1) => 
        apb3_en_if_1_adc_channel_ch3_o(1), 
        apb3_en_if_1_adc_channel_ch3_o(0) => 
        apb3_en_if_1_adc_channel_ch3_o(0), 
        apb3_en_if_1_adc_oc_thresh_o(17) => 
        apb3_en_if_1_adc_oc_thresh_o(17), 
        apb3_en_if_1_adc_oc_thresh_o(16) => 
        apb3_en_if_1_adc_oc_thresh_o(16), 
        apb3_en_if_1_adc_oc_thresh_o(15) => 
        apb3_en_if_1_adc_oc_thresh_o(15), 
        apb3_en_if_1_adc_oc_thresh_o(14) => 
        apb3_en_if_1_adc_oc_thresh_o(14), 
        apb3_en_if_1_adc_oc_thresh_o(13) => 
        apb3_en_if_1_adc_oc_thresh_o(13), 
        apb3_en_if_1_adc_oc_thresh_o(12) => 
        apb3_en_if_1_adc_oc_thresh_o(12), 
        apb3_en_if_1_adc_oc_thresh_o(11) => 
        apb3_en_if_1_adc_oc_thresh_o(11), 
        apb3_en_if_1_adc_oc_thresh_o(10) => 
        apb3_en_if_1_adc_oc_thresh_o(10), 
        apb3_en_if_1_adc_oc_thresh_o(9) => 
        apb3_en_if_1_adc_oc_thresh_o(9), 
        apb3_en_if_1_adc_oc_thresh_o(8) => 
        apb3_en_if_1_adc_oc_thresh_o(8), 
        apb3_en_if_1_adc_oc_thresh_o(7) => 
        apb3_en_if_1_adc_oc_thresh_o(7), 
        apb3_en_if_1_adc_oc_thresh_o(6) => 
        apb3_en_if_1_adc_oc_thresh_o(6), 
        apb3_en_if_1_adc_oc_thresh_o(5) => 
        apb3_en_if_1_adc_oc_thresh_o(5), 
        apb3_en_if_1_adc_oc_thresh_o(4) => 
        apb3_en_if_1_adc_oc_thresh_o(4), 
        apb3_en_if_1_adc_oc_thresh_o(3) => 
        apb3_en_if_1_adc_oc_thresh_o(3), 
        apb3_en_if_1_adc_oc_thresh_o(2) => 
        apb3_en_if_1_adc_oc_thresh_o(2), 
        apb3_en_if_1_adc_oc_thresh_o(1) => 
        apb3_en_if_1_adc_oc_thresh_o(1), 
        apb3_en_if_1_adc_oc_thresh_o(0) => 
        apb3_en_if_1_adc_oc_thresh_o(0), 
        apb3_en_if_1_adc_scale_val_o(17) => 
        apb3_en_if_1_adc_scale_val_o(17), 
        apb3_en_if_1_adc_scale_val_o(16) => 
        apb3_en_if_1_adc_scale_val_o(16), 
        apb3_en_if_1_adc_scale_val_o(15) => 
        apb3_en_if_1_adc_scale_val_o(15), 
        apb3_en_if_1_adc_scale_val_o(14) => 
        apb3_en_if_1_adc_scale_val_o(14), 
        apb3_en_if_1_adc_scale_val_o(13) => 
        apb3_en_if_1_adc_scale_val_o(13), 
        apb3_en_if_1_adc_scale_val_o(12) => 
        apb3_en_if_1_adc_scale_val_o(12), 
        apb3_en_if_1_adc_scale_val_o(11) => 
        apb3_en_if_1_adc_scale_val_o(11), 
        apb3_en_if_1_adc_scale_val_o(10) => 
        apb3_en_if_1_adc_scale_val_o(10), 
        apb3_en_if_1_adc_scale_val_o(9) => 
        apb3_en_if_1_adc_scale_val_o(9), 
        apb3_en_if_1_adc_scale_val_o(8) => 
        apb3_en_if_1_adc_scale_val_o(8), 
        apb3_en_if_1_adc_scale_val_o(7) => 
        apb3_en_if_1_adc_scale_val_o(7), 
        apb3_en_if_1_adc_scale_val_o(6) => 
        apb3_en_if_1_adc_scale_val_o(6), 
        apb3_en_if_1_adc_scale_val_o(5) => 
        apb3_en_if_1_adc_scale_val_o(5), 
        apb3_en_if_1_adc_scale_val_o(4) => 
        apb3_en_if_1_adc_scale_val_o(4), 
        apb3_en_if_1_adc_scale_val_o(3) => 
        apb3_en_if_1_adc_scale_val_o(3), 
        apb3_en_if_1_adc_scale_val_o(2) => 
        apb3_en_if_1_adc_scale_val_o(2), 
        apb3_en_if_1_adc_scale_val_o(1) => 
        apb3_en_if_1_adc_scale_val_o(1), 
        apb3_en_if_1_adc_scale_val_o(0) => 
        apb3_en_if_1_adc_scale_val_o(0), 
        apb3_hall_if_0_hall_speed_factor_o(17) => 
        apb3_hall_if_0_hall_speed_factor_o(17), 
        apb3_hall_if_0_hall_speed_factor_o(16) => 
        apb3_hall_if_0_hall_speed_factor_o(16), 
        apb3_hall_if_0_hall_speed_factor_o(15) => 
        apb3_hall_if_0_hall_speed_factor_o(15), 
        apb3_hall_if_0_hall_speed_factor_o(14) => 
        apb3_hall_if_0_hall_speed_factor_o(14), 
        apb3_hall_if_0_hall_speed_factor_o(13) => 
        apb3_hall_if_0_hall_speed_factor_o(13), 
        apb3_hall_if_0_hall_speed_factor_o(12) => 
        apb3_hall_if_0_hall_speed_factor_o(12), 
        apb3_hall_if_0_hall_speed_factor_o(11) => 
        apb3_hall_if_0_hall_speed_factor_o(11), 
        apb3_hall_if_0_hall_speed_factor_o(10) => 
        apb3_hall_if_0_hall_speed_factor_o(10), 
        apb3_hall_if_0_hall_speed_factor_o(9) => 
        apb3_hall_if_0_hall_speed_factor_o(9), 
        apb3_hall_if_0_hall_speed_factor_o(8) => 
        apb3_hall_if_0_hall_speed_factor_o(8), 
        apb3_hall_if_0_hall_speed_factor_o(7) => 
        apb3_hall_if_0_hall_speed_factor_o(7), 
        apb3_hall_if_0_hall_speed_factor_o(6) => 
        apb3_hall_if_0_hall_speed_factor_o(6), 
        apb3_hall_if_0_hall_speed_factor_o(5) => 
        apb3_hall_if_0_hall_speed_factor_o(5), 
        apb3_hall_if_0_hall_speed_factor_o(4) => 
        apb3_hall_if_0_hall_speed_factor_o(4), 
        apb3_hall_if_0_hall_speed_factor_o(3) => 
        apb3_hall_if_0_hall_speed_factor_o(3), 
        apb3_hall_if_0_hall_speed_factor_o(2) => 
        apb3_hall_if_0_hall_speed_factor_o(2), 
        apb3_hall_if_0_hall_speed_factor_o(1) => 
        apb3_hall_if_0_hall_speed_factor_o(1), 
        apb3_hall_if_0_hall_speed_factor_o(0) => 
        apb3_hall_if_0_hall_speed_factor_o(0), 
        MC_System_0_AMBA_SLAVE_0_PRDATA(19) => 
        MC_System_0_AMBA_SLAVE_0_PRDATA(19), 
        prdata_o_1_iv_0_0_a3_2_0(9) => 
        prdata_o_1_iv_0_0_a3_2_0(9), prdata_o_1_0_iv_0_8_13 => 
        prdata_o_1_0_iv_0_8(13), 
        MC_System_0_AMBA_SLAVE_0_PADDR(11) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(11), 
        MC_System_0_AMBA_SLAVE_0_PADDR(10) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(10), 
        MC_System_0_AMBA_SLAVE_0_PADDR(9) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(9), 
        MC_System_0_AMBA_SLAVE_0_PADDR(8) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(8), 
        MC_System_0_AMBA_SLAVE_0_PADDR(7) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(7), 
        MC_System_0_AMBA_SLAVE_0_PADDR(6) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(6), 
        MC_System_0_AMBA_SLAVE_0_PADDR(5) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), 
        MC_System_0_AMBA_SLAVE_0_PADDR(4) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), 
        MC_System_0_AMBA_SLAVE_0_PADDR(3) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), 
        MC_System_0_AMBA_SLAVE_0_PADDR(2) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), 
        MC_System_0_AMBA_SLAVE_0_PADDR(1) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(1), 
        MC_System_0_AMBA_SLAVE_0_PADDR(0) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(0), prdata_o_1_iv_0_0_7_2
         => prdata_o_1_iv_0_0_7(10), prdata_o_1_iv_0_0_15(8) => 
        prdata_o_1_iv_0_0_15(8), prdata_o_0_5(17) => 
        prdata_o_0_5(17), prdata_o_1_iv_0_0_5_0 => 
        prdata_o_1_iv_0_0_5(7), prdata_o_1_iv_0_0_a1(6) => 
        prdata_o_1_iv_0_0_a1(6), prdata_o_1_iv_0_0_a1(5) => 
        prdata_o_1_iv_0_0_a1(5), prdata_o_1_iv_0_0_0 => 
        prdata_o_1_iv_0_0_0, prdata_o_1_iv_0_0_6 => 
        prdata_o_1_iv_0_0_6, HALL_INTERFACE_1_theta_output_o_6
         => HALL_INTERFACE_1_theta_output_o(13), 
        HALL_INTERFACE_1_theta_output_o_1 => 
        HALL_INTERFACE_1_theta_output_o(8), 
        HALL_INTERFACE_1_theta_output_o_0 => 
        HALL_INTERFACE_1_theta_output_o(7), 
        HALL_INTERFACE_1_theta_output_o_9 => 
        HALL_INTERFACE_1_theta_output_o(16), 
        HALL_INTERFACE_1_theta_output_o_8 => 
        HALL_INTERFACE_1_theta_output_o(15), 
        HALL_INTERFACE_1_theta_output_o_5 => 
        HALL_INTERFACE_1_theta_output_o(12), 
        HALL_INTERFACE_1_theta_output_o_10 => 
        HALL_INTERFACE_1_theta_output_o(17), 
        HALL_INTERFACE_1_theta_output_o_3 => 
        HALL_INTERFACE_1_theta_output_o(10), 
        HALL_INTERFACE_1_theta_output_o_7 => 
        HALL_INTERFACE_1_theta_output_o(14), 
        FOC_TRANSFORMS_0_id_o_0 => FOC_TRANSFORMS_0_id_o(0), 
        FOC_TRANSFORMS_0_id_o_10 => FOC_TRANSFORMS_0_id_o(10), 
        FOC_TRANSFORMS_0_id_o_13 => FOC_TRANSFORMS_0_id_o(13), 
        FOC_TRANSFORMS_0_id_o_17 => FOC_TRANSFORMS_0_id_o(17), 
        FOC_TRANSFORMS_0_id_o_3 => FOC_TRANSFORMS_0_id_o(3), 
        FOC_TRANSFORMS_0_id_o_11 => FOC_TRANSFORMS_0_id_o(11), 
        FOC_TRANSFORMS_0_id_o_16 => FOC_TRANSFORMS_0_id_o(16), 
        FOC_TRANSFORMS_0_id_o_1 => FOC_TRANSFORMS_0_id_o(1), 
        FOC_TRANSFORMS_0_id_o_2 => FOC_TRANSFORMS_0_id_o(2), 
        FOC_TRANSFORMS_0_id_o_15 => FOC_TRANSFORMS_0_id_o(15), 
        FOC_TRANSFORMS_0_id_o_12 => FOC_TRANSFORMS_0_id_o(12), 
        FOC_TRANSFORMS_0_id_o_7 => FOC_TRANSFORMS_0_id_o(7), 
        FOC_TRANSFORMS_0_id_o_6 => FOC_TRANSFORMS_0_id_o(6), 
        FOC_TRANSFORMS_0_id_o_5 => FOC_TRANSFORMS_0_id_o(5), 
        FOC_TRANSFORMS_0_id_o_8 => FOC_TRANSFORMS_0_id_o(8), 
        FOC_TRANSFORMS_0_id_o_9 => FOC_TRANSFORMS_0_id_o(9), 
        FOC_TRANSFORMS_0_id_o_14 => FOC_TRANSFORMS_0_id_o(14), 
        ADC_SCALING_0_ib_adc_o(17) => ADC_SCALING_0_ib_adc_o(17), 
        ADC_SCALING_0_ib_adc_o(16) => ADC_SCALING_0_ib_adc_o(16), 
        ADC_SCALING_0_ib_adc_o(15) => ADC_SCALING_0_ib_adc_o(15), 
        ADC_SCALING_0_ib_adc_o(14) => ADC_SCALING_0_ib_adc_o(14), 
        ADC_SCALING_0_ib_adc_o(13) => ADC_SCALING_0_ib_adc_o(13), 
        ADC_SCALING_0_ib_adc_o(12) => ADC_SCALING_0_ib_adc_o(12), 
        ADC_SCALING_0_ib_adc_o(11) => ADC_SCALING_0_ib_adc_o(11), 
        ADC_SCALING_0_ib_adc_o(10) => ADC_SCALING_0_ib_adc_o(10), 
        ADC_SCALING_0_ib_adc_o(9) => ADC_SCALING_0_ib_adc_o(9), 
        ADC_SCALING_0_ib_adc_o(8) => ADC_SCALING_0_ib_adc_o(8), 
        ADC_SCALING_0_ib_adc_o(7) => ADC_SCALING_0_ib_adc_o(7), 
        ADC_SCALING_0_ib_adc_o(6) => ADC_SCALING_0_ib_adc_o(6), 
        ADC_SCALING_0_ib_adc_o(5) => ADC_SCALING_0_ib_adc_o(5), 
        ADC_SCALING_0_ib_adc_o(4) => ADC_SCALING_0_ib_adc_o(4), 
        ADC_SCALING_0_ib_adc_o(3) => ADC_SCALING_0_ib_adc_o(3), 
        ADC_SCALING_0_ib_adc_o(2) => ADC_SCALING_0_ib_adc_o(2), 
        ADC_SCALING_0_ib_adc_o(1) => ADC_SCALING_0_ib_adc_o(1), 
        ADC_SCALING_0_ib_adc_o(0) => ADC_SCALING_0_ib_adc_o(0), 
        FOC_TRANSFORMS_0_iq_o_2 => FOC_TRANSFORMS_0_iq_o(2), 
        FOC_TRANSFORMS_0_iq_o_1 => FOC_TRANSFORMS_0_iq_o(1), 
        FOC_TRANSFORMS_0_iq_o_8 => FOC_TRANSFORMS_0_iq_o(8), 
        FOC_TRANSFORMS_0_iq_o_16 => FOC_TRANSFORMS_0_iq_o(16), 
        FOC_TRANSFORMS_0_iq_o_7 => FOC_TRANSFORMS_0_iq_o(7), 
        FOC_TRANSFORMS_0_iq_o_3 => FOC_TRANSFORMS_0_iq_o(3), 
        FOC_TRANSFORMS_0_iq_o_0 => FOC_TRANSFORMS_0_iq_o(0), 
        FOC_TRANSFORMS_0_iq_o_17 => FOC_TRANSFORMS_0_iq_o(17), 
        FOC_TRANSFORMS_0_iq_o_5 => FOC_TRANSFORMS_0_iq_o(5), 
        FOC_TRANSFORMS_0_iq_o_11 => FOC_TRANSFORMS_0_iq_o(11), 
        FOC_TRANSFORMS_0_iq_o_10 => FOC_TRANSFORMS_0_iq_o(10), 
        FOC_TRANSFORMS_0_iq_o_4 => FOC_TRANSFORMS_0_iq_o(4), 
        FOC_TRANSFORMS_0_iq_o_14 => FOC_TRANSFORMS_0_iq_o(14), 
        FOC_TRANSFORMS_0_iq_o_13 => FOC_TRANSFORMS_0_iq_o(13), 
        FOC_TRANSFORMS_0_iq_o_15 => FOC_TRANSFORMS_0_iq_o(15), 
        FOC_TRANSFORMS_0_iq_o_12 => FOC_TRANSFORMS_0_iq_o(12), 
        prdata_o_1_0_iv_0_0_11_a2(14) => 
        prdata_o_1_0_iv_0_0_11_a2(14), 
        prdata_o_1_0_iv_0_0_11_a0(14) => 
        prdata_o_1_0_iv_0_0_11_a0(14), 
        prdata_o_1_0_iv_0_11_a2(13) => 
        prdata_o_1_0_iv_0_11_a2(13), prdata_o_1_0_iv_0_11_a0(13)
         => prdata_o_1_0_iv_0_11_a0(13), 
        SEQ_CONTROLLER_0_state_o(3) => 
        SEQ_CONTROLLER_0_state_o(3), SEQ_CONTROLLER_0_state_o(2)
         => SEQ_CONTROLLER_0_state_o(2), 
        SEQ_CONTROLLER_0_state_o(1) => 
        SEQ_CONTROLLER_0_state_o(1), SEQ_CONTROLLER_0_state_o(0)
         => SEQ_CONTROLLER_0_state_o(0), 
        ADC_SCALING_0_ia_adc_o(17) => ADC_SCALING_0_ia_adc_o(17), 
        ADC_SCALING_0_ia_adc_o(16) => ADC_SCALING_0_ia_adc_o(16), 
        ADC_SCALING_0_ia_adc_o(15) => ADC_SCALING_0_ia_adc_o(15), 
        ADC_SCALING_0_ia_adc_o(14) => ADC_SCALING_0_ia_adc_o(14), 
        ADC_SCALING_0_ia_adc_o(13) => ADC_SCALING_0_ia_adc_o(13), 
        ADC_SCALING_0_ia_adc_o(12) => ADC_SCALING_0_ia_adc_o(12), 
        ADC_SCALING_0_ia_adc_o(11) => ADC_SCALING_0_ia_adc_o(11), 
        ADC_SCALING_0_ia_adc_o(10) => ADC_SCALING_0_ia_adc_o(10), 
        ADC_SCALING_0_ia_adc_o(9) => ADC_SCALING_0_ia_adc_o(9), 
        ADC_SCALING_0_ia_adc_o(8) => ADC_SCALING_0_ia_adc_o(8), 
        ADC_SCALING_0_ia_adc_o(7) => ADC_SCALING_0_ia_adc_o(7), 
        ADC_SCALING_0_ia_adc_o(6) => ADC_SCALING_0_ia_adc_o(6), 
        ADC_SCALING_0_ia_adc_o(5) => ADC_SCALING_0_ia_adc_o(5), 
        ADC_SCALING_0_ia_adc_o(4) => ADC_SCALING_0_ia_adc_o(4), 
        ADC_SCALING_0_ia_adc_o(3) => ADC_SCALING_0_ia_adc_o(3), 
        ADC_SCALING_0_ia_adc_o(2) => ADC_SCALING_0_ia_adc_o(2), 
        ADC_SCALING_0_ia_adc_o(1) => ADC_SCALING_0_ia_adc_o(1), 
        ADC_SCALING_0_ia_adc_o(0) => ADC_SCALING_0_ia_adc_o(0), 
        prdata_o_1_0_iv_0_1_15 => prdata_o_1_0_iv_0_1(17), 
        prdata_o_1_iv_0_9(5) => prdata_o_1_iv_0_9(5), 
        prdata_o_1_iv_0_8_0 => prdata_o_1_iv_0_8(5), 
        prdata_o_1_iv_0_6_0 => prdata_o_1_iv_0_6(5), 
        adc_interface_0_result_ch3_o(11) => 
        adc_interface_0_result_ch3_o(11), 
        adc_interface_0_result_ch3_o(10) => 
        adc_interface_0_result_ch3_o(10), 
        adc_interface_0_result_ch3_o(9) => 
        adc_interface_0_result_ch3_o(9), 
        adc_interface_0_result_ch3_o(8) => 
        adc_interface_0_result_ch3_o(8), 
        adc_interface_0_result_ch3_o(7) => 
        adc_interface_0_result_ch3_o(7), 
        adc_interface_0_result_ch3_o(6) => 
        adc_interface_0_result_ch3_o(6), 
        adc_interface_0_result_ch3_o(5) => 
        adc_interface_0_result_ch3_o(5), 
        adc_interface_0_result_ch3_o(4) => 
        adc_interface_0_result_ch3_o(4), 
        adc_interface_0_result_ch3_o(3) => 
        adc_interface_0_result_ch3_o(3), 
        adc_interface_0_result_ch3_o(2) => 
        adc_interface_0_result_ch3_o(2), 
        adc_interface_0_result_ch3_o(1) => 
        adc_interface_0_result_ch3_o(1), 
        adc_interface_0_result_ch3_o(0) => 
        adc_interface_0_result_ch3_o(0), prdata_o_1_iv_0_0_10_2
         => prdata_o_1_iv_0_0_10_2, prdata_o_1_iv_0_0_10_0 => 
        prdata_o_1_iv_0_0_10_0, prdata_o_1_0_iv_0_0_7_11 => 
        prdata_o_1_0_iv_0_0_7(14), prdata_o_1_0_iv_0_0_6_11 => 
        prdata_o_1_0_iv_0_0_6(14), prdata_o_1_0_iv_0_7_4 => 
        prdata_o_1_0_iv_0_7_0, prdata_o_1_0_iv_0_7_13 => 
        prdata_o_1_0_iv_0_7_9, FOC_TRANSFORMS_0_ialpha_o(17) => 
        FOC_TRANSFORMS_0_ialpha_o(17), 
        FOC_TRANSFORMS_0_ialpha_o(16) => 
        FOC_TRANSFORMS_0_ialpha_o(16), 
        FOC_TRANSFORMS_0_ialpha_o(15) => 
        FOC_TRANSFORMS_0_ialpha_o(15), 
        FOC_TRANSFORMS_0_ialpha_o(14) => 
        FOC_TRANSFORMS_0_ialpha_o(14), 
        FOC_TRANSFORMS_0_ialpha_o(13) => 
        FOC_TRANSFORMS_0_ialpha_o(13), 
        FOC_TRANSFORMS_0_ialpha_o(12) => 
        FOC_TRANSFORMS_0_ialpha_o(12), 
        FOC_TRANSFORMS_0_ialpha_o(11) => 
        FOC_TRANSFORMS_0_ialpha_o(11), 
        FOC_TRANSFORMS_0_ialpha_o(10) => 
        FOC_TRANSFORMS_0_ialpha_o(10), 
        FOC_TRANSFORMS_0_ialpha_o(9) => 
        FOC_TRANSFORMS_0_ialpha_o(9), 
        FOC_TRANSFORMS_0_ialpha_o(8) => 
        FOC_TRANSFORMS_0_ialpha_o(8), 
        FOC_TRANSFORMS_0_ialpha_o(7) => 
        FOC_TRANSFORMS_0_ialpha_o(7), 
        FOC_TRANSFORMS_0_ialpha_o(6) => 
        FOC_TRANSFORMS_0_ialpha_o(6), 
        FOC_TRANSFORMS_0_ialpha_o(5) => 
        FOC_TRANSFORMS_0_ialpha_o(5), 
        FOC_TRANSFORMS_0_ialpha_o(4) => 
        FOC_TRANSFORMS_0_ialpha_o(4), 
        FOC_TRANSFORMS_0_ialpha_o(3) => 
        FOC_TRANSFORMS_0_ialpha_o(3), 
        FOC_TRANSFORMS_0_ialpha_o(2) => 
        FOC_TRANSFORMS_0_ialpha_o(2), 
        FOC_TRANSFORMS_0_ialpha_o(1) => 
        FOC_TRANSFORMS_0_ialpha_o(1), 
        FOC_TRANSFORMS_0_ialpha_o(0) => 
        FOC_TRANSFORMS_0_ialpha_o(0), 
        FOC_TRANSFORMS_0_valpha_o_17 => 
        FOC_TRANSFORMS_0_valpha_o(17), 
        FOC_TRANSFORMS_0_valpha_o_12 => 
        FOC_TRANSFORMS_0_valpha_o(12), 
        FOC_TRANSFORMS_0_valpha_o_7 => 
        FOC_TRANSFORMS_0_valpha_o(7), 
        FOC_TRANSFORMS_0_valpha_o_10 => 
        FOC_TRANSFORMS_0_valpha_o(10), 
        FOC_TRANSFORMS_0_valpha_o_3 => 
        FOC_TRANSFORMS_0_valpha_o(3), FOC_TRANSFORMS_0_valpha_o_4
         => FOC_TRANSFORMS_0_valpha_o(4), 
        FOC_TRANSFORMS_0_valpha_o_16 => 
        FOC_TRANSFORMS_0_valpha_o(16), 
        FOC_TRANSFORMS_0_valpha_o_0 => 
        FOC_TRANSFORMS_0_valpha_o(0), FOC_TRANSFORMS_0_valpha_o_1
         => FOC_TRANSFORMS_0_valpha_o(1), 
        FOC_TRANSFORMS_0_valpha_o_2 => 
        FOC_TRANSFORMS_0_valpha_o(2), 
        FOC_TRANSFORMS_0_valpha_o_15 => 
        FOC_TRANSFORMS_0_valpha_o(15), 
        FOC_TRANSFORMS_0_valpha_o_8 => 
        FOC_TRANSFORMS_0_valpha_o(8), 
        FOC_TRANSFORMS_0_valpha_o_14 => 
        FOC_TRANSFORMS_0_valpha_o(14), 
        FOC_TRANSFORMS_0_valpha_o_13 => 
        FOC_TRANSFORMS_0_valpha_o(13), prdata_o_1_0_iv_0_6_16 => 
        prdata_o_1_0_iv_0_6_3, prdata_o_1_0_iv_0_6_13 => 
        prdata_o_1_0_iv_0_6_0, prdata_o_1_0_iv_0_5_16 => 
        prdata_o_1_0_iv_0_5(16), FOC_TRANSFORMS_0_vbeta_o(17) => 
        FOC_TRANSFORMS_0_vbeta_o(17), 
        FOC_TRANSFORMS_0_vbeta_o(16) => 
        FOC_TRANSFORMS_0_vbeta_o(16), 
        FOC_TRANSFORMS_0_vbeta_o(15) => 
        FOC_TRANSFORMS_0_vbeta_o(15), 
        FOC_TRANSFORMS_0_vbeta_o(14) => 
        FOC_TRANSFORMS_0_vbeta_o(14), 
        FOC_TRANSFORMS_0_vbeta_o(13) => 
        FOC_TRANSFORMS_0_vbeta_o(13), 
        FOC_TRANSFORMS_0_vbeta_o(12) => 
        FOC_TRANSFORMS_0_vbeta_o(12), 
        FOC_TRANSFORMS_0_vbeta_o(11) => 
        FOC_TRANSFORMS_0_vbeta_o(11), 
        FOC_TRANSFORMS_0_vbeta_o(10) => 
        FOC_TRANSFORMS_0_vbeta_o(10), FOC_TRANSFORMS_0_vbeta_o(9)
         => FOC_TRANSFORMS_0_vbeta_o(9), 
        FOC_TRANSFORMS_0_vbeta_o(8) => 
        FOC_TRANSFORMS_0_vbeta_o(8), FOC_TRANSFORMS_0_vbeta_o(7)
         => FOC_TRANSFORMS_0_vbeta_o(7), 
        FOC_TRANSFORMS_0_vbeta_o(6) => 
        FOC_TRANSFORMS_0_vbeta_o(6), FOC_TRANSFORMS_0_vbeta_o(5)
         => FOC_TRANSFORMS_0_vbeta_o(5), 
        FOC_TRANSFORMS_0_vbeta_o(4) => 
        FOC_TRANSFORMS_0_vbeta_o(4), FOC_TRANSFORMS_0_vbeta_o(3)
         => FOC_TRANSFORMS_0_vbeta_o(3), 
        FOC_TRANSFORMS_0_vbeta_o(2) => 
        FOC_TRANSFORMS_0_vbeta_o(2), FOC_TRANSFORMS_0_vbeta_o(1)
         => FOC_TRANSFORMS_0_vbeta_o(1), 
        FOC_TRANSFORMS_0_vbeta_o(0) => 
        FOC_TRANSFORMS_0_vbeta_o(0), prdata_o_1_0_iv_0_4_15 => 
        prdata_o_1_0_iv_0_4(16), prdata_o_1_0_iv_0_3_16 => 
        prdata_o_1_0_iv_0_3(16), OLMNG_0_theta_o_10 => 
        OLMNG_0_theta_o(10), OLMNG_0_theta_o_0 => 
        OLMNG_0_theta_o(0), OLMNG_0_theta_o_8 => 
        OLMNG_0_theta_o(8), OLMNG_0_theta_o_4 => 
        OLMNG_0_theta_o(4), OLMNG_0_theta_o_17 => 
        OLMNG_0_theta_o(17), OLMNG_0_theta_o_3 => 
        OLMNG_0_theta_o(3), OLMNG_0_theta_o_16 => 
        OLMNG_0_theta_o(16), OLMNG_0_theta_o_1 => 
        OLMNG_0_theta_o(1), OLMNG_0_theta_o_2 => 
        OLMNG_0_theta_o(2), OLMNG_0_theta_o_15 => 
        OLMNG_0_theta_o(15), OLMNG_0_theta_o_7 => 
        OLMNG_0_theta_o(7), OLMNG_0_theta_o_14 => 
        OLMNG_0_theta_o(14), OLMNG_0_theta_o_13 => 
        OLMNG_0_theta_o(13), OLMNG_0_theta_o_12 => 
        OLMNG_0_theta_o(12), SPEED_ID_IQ_PI_0_id_pi_output_o_10
         => SPEED_ID_IQ_PI_0_id_pi_output_o(10), 
        SPEED_ID_IQ_PI_0_id_pi_output_o_7 => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(7), 
        SPEED_ID_IQ_PI_0_id_pi_output_o_4 => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(4), 
        SPEED_ID_IQ_PI_0_id_pi_output_o_3 => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(3), 
        SPEED_ID_IQ_PI_0_id_pi_output_o_8 => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(8), 
        SPEED_ID_IQ_PI_0_id_pi_output_o_17 => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(17), 
        SPEED_ID_IQ_PI_0_id_pi_output_o_16 => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(16), 
        SPEED_ID_IQ_PI_0_id_pi_output_o_0 => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(0), 
        SPEED_ID_IQ_PI_0_id_pi_output_o_1 => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(1), 
        SPEED_ID_IQ_PI_0_id_pi_output_o_2 => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(2), 
        SPEED_ID_IQ_PI_0_id_pi_output_o_15 => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(15), 
        SPEED_ID_IQ_PI_0_id_pi_output_o_14 => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(14), 
        SPEED_ID_IQ_PI_0_id_pi_output_o_13 => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(13), 
        SPEED_ID_IQ_PI_0_id_pi_output_o_12 => 
        SPEED_ID_IQ_PI_0_id_pi_output_o(12), 
        adc_interface_0_result_ch2_o(11) => 
        adc_interface_0_result_ch2_o(11), 
        adc_interface_0_result_ch2_o(10) => 
        adc_interface_0_result_ch2_o(10), 
        adc_interface_0_result_ch2_o(9) => 
        adc_interface_0_result_ch2_o(9), 
        adc_interface_0_result_ch2_o(8) => 
        adc_interface_0_result_ch2_o(8), 
        adc_interface_0_result_ch2_o(7) => 
        adc_interface_0_result_ch2_o(7), 
        adc_interface_0_result_ch2_o(6) => 
        adc_interface_0_result_ch2_o(6), 
        adc_interface_0_result_ch2_o(5) => 
        adc_interface_0_result_ch2_o(5), 
        adc_interface_0_result_ch2_o(4) => 
        adc_interface_0_result_ch2_o(4), 
        adc_interface_0_result_ch2_o(3) => 
        adc_interface_0_result_ch2_o(3), 
        adc_interface_0_result_ch2_o(2) => 
        adc_interface_0_result_ch2_o(2), 
        adc_interface_0_result_ch2_o(1) => 
        adc_interface_0_result_ch2_o(1), 
        adc_interface_0_result_ch2_o(0) => 
        adc_interface_0_result_ch2_o(0), 
        FOC_TRANSFORMS_0_ibeta_o(17) => 
        FOC_TRANSFORMS_0_ibeta_o(17), 
        FOC_TRANSFORMS_0_ibeta_o(16) => 
        FOC_TRANSFORMS_0_ibeta_o(16), 
        FOC_TRANSFORMS_0_ibeta_o(15) => 
        FOC_TRANSFORMS_0_ibeta_o(15), 
        FOC_TRANSFORMS_0_ibeta_o(14) => 
        FOC_TRANSFORMS_0_ibeta_o(14), 
        FOC_TRANSFORMS_0_ibeta_o(13) => 
        FOC_TRANSFORMS_0_ibeta_o(13), 
        FOC_TRANSFORMS_0_ibeta_o(12) => 
        FOC_TRANSFORMS_0_ibeta_o(12), 
        FOC_TRANSFORMS_0_ibeta_o(11) => 
        FOC_TRANSFORMS_0_ibeta_o(11), 
        FOC_TRANSFORMS_0_ibeta_o(10) => 
        FOC_TRANSFORMS_0_ibeta_o(10), FOC_TRANSFORMS_0_ibeta_o(9)
         => FOC_TRANSFORMS_0_ibeta_o(9), 
        FOC_TRANSFORMS_0_ibeta_o(8) => 
        FOC_TRANSFORMS_0_ibeta_o(8), FOC_TRANSFORMS_0_ibeta_o(7)
         => FOC_TRANSFORMS_0_ibeta_o(7), 
        FOC_TRANSFORMS_0_ibeta_o(6) => 
        FOC_TRANSFORMS_0_ibeta_o(6), FOC_TRANSFORMS_0_ibeta_o(5)
         => FOC_TRANSFORMS_0_ibeta_o(5), 
        FOC_TRANSFORMS_0_ibeta_o(4) => 
        FOC_TRANSFORMS_0_ibeta_o(4), FOC_TRANSFORMS_0_ibeta_o(3)
         => FOC_TRANSFORMS_0_ibeta_o(3), 
        FOC_TRANSFORMS_0_ibeta_o(2) => 
        FOC_TRANSFORMS_0_ibeta_o(2), FOC_TRANSFORMS_0_ibeta_o(1)
         => FOC_TRANSFORMS_0_ibeta_o(1), 
        FOC_TRANSFORMS_0_ibeta_o(0) => 
        FOC_TRANSFORMS_0_ibeta_o(0), prdata_o_1_iv_0_12(5) => 
        prdata_o_1_iv_0_12(5), prdata_o_1_iv_0_7_0 => 
        prdata_o_1_iv_0_7(5), prdata_o_1_iv_0_0_14(10) => 
        prdata_o_1_iv_0_0_14(10), prdata_o_1_iv_0_0_14(9) => 
        prdata_o_1_iv_0_0_14(9), prdata_o_1_iv_0_0_14(8) => 
        prdata_o_1_iv_0_0_14(8), prdata_o_1_iv_0_14_0 => 
        prdata_o_1_iv_0_14_0, prdata_o_1_iv_0_14_5 => 
        prdata_o_1_iv_0_14_5, 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(17) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(17), 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(16) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(16), 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(15) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(15), 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(14) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(14), 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(13) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(13), 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(12) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(12), 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(11) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(11), 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(10) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(10), 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(9) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(9), 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(8) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(8), 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(7) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(7), 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(6) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(6), 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(5) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(5), 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(4) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(4), 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(3) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(3), 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(2) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(2), 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(1) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(1), 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(0) => 
        SPEED_ID_IQ_PI_0_speed_pi_output_o(0), 
        adc_interface_0_result_ch0_o(11) => 
        adc_interface_0_result_ch0_o(11), 
        adc_interface_0_result_ch0_o(10) => 
        adc_interface_0_result_ch0_o(10), 
        adc_interface_0_result_ch0_o(9) => 
        adc_interface_0_result_ch0_o(9), 
        adc_interface_0_result_ch0_o(8) => 
        adc_interface_0_result_ch0_o(8), 
        adc_interface_0_result_ch0_o(7) => 
        adc_interface_0_result_ch0_o(7), 
        adc_interface_0_result_ch0_o(6) => 
        adc_interface_0_result_ch0_o(6), 
        adc_interface_0_result_ch0_o(5) => 
        adc_interface_0_result_ch0_o(5), 
        adc_interface_0_result_ch0_o(4) => 
        adc_interface_0_result_ch0_o(4), 
        adc_interface_0_result_ch0_o(3) => 
        adc_interface_0_result_ch0_o(3), 
        adc_interface_0_result_ch0_o(2) => 
        adc_interface_0_result_ch0_o(2), 
        adc_interface_0_result_ch0_o(1) => 
        adc_interface_0_result_ch0_o(1), 
        adc_interface_0_result_ch0_o(0) => 
        adc_interface_0_result_ch0_o(0), 
        adc_interface_0_result_ch1_o_0 => 
        adc_interface_0_result_ch1_o(0), 
        adc_interface_0_result_ch1_o_1 => 
        adc_interface_0_result_ch1_o(1), 
        adc_interface_0_result_ch1_o_8 => 
        adc_interface_0_result_ch1_o(8), 
        adc_interface_0_result_ch1_o_10 => 
        adc_interface_0_result_ch1_o(10), 
        adc_interface_0_result_ch1_o_7 => 
        adc_interface_0_result_ch1_o(7), 
        adc_interface_0_result_ch1_o_6 => 
        adc_interface_0_result_ch1_o(6), 
        adc_interface_0_result_ch1_o_9 => 
        adc_interface_0_result_ch1_o(9), 
        adc_interface_0_result_ch1_o_11 => 
        adc_interface_0_result_ch1_o(11), 
        adc_interface_0_result_ch1_o_3 => 
        adc_interface_0_result_ch1_o(3), 
        adc_interface_0_result_ch1_o_5 => 
        adc_interface_0_result_ch1_o(5), 
        adc_interface_0_result_ch1_o_2 => 
        adc_interface_0_result_ch1_o(2), 
        HALL_INTERFACE_1_omega_out_o(17) => 
        HALL_INTERFACE_1_omega_out_o(17), 
        HALL_INTERFACE_1_omega_out_o(16) => 
        HALL_INTERFACE_1_omega_out_o(16), 
        HALL_INTERFACE_1_omega_out_o(15) => 
        HALL_INTERFACE_1_omega_out_o(15), 
        HALL_INTERFACE_1_omega_out_o(14) => 
        HALL_INTERFACE_1_omega_out_o(14), 
        HALL_INTERFACE_1_omega_out_o(13) => 
        HALL_INTERFACE_1_omega_out_o(13), 
        HALL_INTERFACE_1_omega_out_o(12) => 
        HALL_INTERFACE_1_omega_out_o(12), 
        HALL_INTERFACE_1_omega_out_o(11) => 
        HALL_INTERFACE_1_omega_out_o(11), 
        HALL_INTERFACE_1_omega_out_o(10) => 
        HALL_INTERFACE_1_omega_out_o(10), 
        HALL_INTERFACE_1_omega_out_o(9) => 
        HALL_INTERFACE_1_omega_out_o(9), 
        HALL_INTERFACE_1_omega_out_o(8) => 
        HALL_INTERFACE_1_omega_out_o(8), 
        HALL_INTERFACE_1_omega_out_o(7) => 
        HALL_INTERFACE_1_omega_out_o(7), 
        HALL_INTERFACE_1_omega_out_o(6) => 
        HALL_INTERFACE_1_omega_out_o(6), 
        HALL_INTERFACE_1_omega_out_o(5) => 
        HALL_INTERFACE_1_omega_out_o(5), 
        HALL_INTERFACE_1_omega_out_o(4) => 
        HALL_INTERFACE_1_omega_out_o(4), 
        HALL_INTERFACE_1_omega_out_o(3) => 
        HALL_INTERFACE_1_omega_out_o(3), 
        HALL_INTERFACE_1_omega_out_o(2) => 
        HALL_INTERFACE_1_omega_out_o(2), 
        HALL_INTERFACE_1_omega_out_o(1) => 
        HALL_INTERFACE_1_omega_out_o(1), 
        HALL_INTERFACE_1_omega_out_o(0) => 
        HALL_INTERFACE_1_omega_out_o(0), prdata_o_1_iv_0_0_11_2
         => prdata_o_1_iv_0_0_11_2, prdata_o_1_iv_0_0_11_0 => 
        prdata_o_1_iv_0_0_11_0, 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(17) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(17), 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(16) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(16), 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(15) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(15), 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(14) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(14), 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(13) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(13), 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(12) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(12), 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(11) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(11), 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(10) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(10), 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(9) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(9), 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(8) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(8), 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(7) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(7), 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(6) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(6), 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(5) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(5), 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(4) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(4), 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(3) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(3), 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(2) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(2), 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(1) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(1), 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(0) => 
        SPEED_ID_IQ_PI_0_iq_pi_output_o(0), 
        prdata_o_1_0_iv_0_14_2 => prdata_o_1_0_iv_0_14_2, 
        prdata_o_1_0_iv_0_14_0 => prdata_o_1_0_iv_0_14_0, 
        prdata_o_1_0_iv_0_14_1 => prdata_o_1_0_iv_0_14_1, 
        prdata_o_1_0_iv_0_14_4 => prdata_o_1_0_iv_0_14_4, 
        prdata_o_1_0_iv_0_0_8_11 => prdata_o_1_0_iv_0_0_8(14), 
        prdata_o_1_0_iv_0_9_12 => prdata_o_1_0_iv_0_9(13), 
        prdata_o_1_0_iv_0_0_11(15) => prdata_o_1_0_iv_0_0_11(15), 
        prdata_o_1_0_iv_0_11(16) => prdata_o_1_0_iv_0_11(16), 
        prdata_o_0_3(17) => prdata_o_0_3(17), 
        prdata_o_1_0_iv_0_15_0 => prdata_o_1_0_iv_0_15_0, 
        prdata_o_1_0_iv_0_15_4 => prdata_o_1_0_iv_0_15_4, 
        prdata_o_1_0_iv_0_15_2 => prdata_o_1_0_iv_0_15_2, 
        prdata_o_1_0_iv_0_15_1 => prdata_o_1_0_iv_0_15_1, 
        prdata_o_1_0_iv_0_0_14(3) => prdata_o_1_0_iv_0_0_14(3), 
        HALL_INTERFACE_1_angle_out_raw_o(12) => 
        HALL_INTERFACE_1_angle_out_raw_o(12), 
        HALL_INTERFACE_1_angle_out_raw_o(11) => 
        HALL_INTERFACE_1_angle_out_raw_o(11), 
        HALL_INTERFACE_1_angle_out_raw_o(10) => 
        HALL_INTERFACE_1_angle_out_raw_o(10), 
        HALL_INTERFACE_1_angle_out_raw_o(9) => 
        HALL_INTERFACE_1_angle_out_raw_o(9), 
        HALL_INTERFACE_1_angle_out_raw_o(8) => 
        HALL_INTERFACE_1_angle_out_raw_o(8), 
        HALL_INTERFACE_1_angle_out_raw_o(7) => 
        HALL_INTERFACE_1_angle_out_raw_o(7), 
        HALL_INTERFACE_1_angle_out_raw_o(6) => 
        HALL_INTERFACE_1_angle_out_raw_o(6), 
        HALL_INTERFACE_1_angle_out_raw_o(5) => 
        HALL_INTERFACE_1_angle_out_raw_o(5), 
        HALL_INTERFACE_1_angle_out_raw_o(4) => 
        HALL_INTERFACE_1_angle_out_raw_o(4), 
        HALL_INTERFACE_1_angle_out_raw_o(3) => 
        HALL_INTERFACE_1_angle_out_raw_o(3), 
        HALL_INTERFACE_1_angle_out_raw_o(2) => 
        HALL_INTERFACE_1_angle_out_raw_o(2), 
        HALL_INTERFACE_1_angle_out_raw_o(1) => 
        HALL_INTERFACE_1_angle_out_raw_o(1), 
        HALL_INTERFACE_1_angle_out_raw_o(0) => 
        HALL_INTERFACE_1_angle_out_raw_o(0), 
        prdata_o_1_0_iv_0_0_9_11 => prdata_o_1_0_iv_0_0_9_11, 
        prdata_o_1_0_iv_0_0_9_12 => prdata_o_1_0_iv_0_0_9_12, 
        prdata_o_1_0_iv_0_0_9_0 => prdata_o_1_0_iv_0_0_9_0, 
        prdata_o_1_0_iv_0_0_10_0 => prdata_o_1_0_iv_0_0_10_0, 
        prdata_o_1_0_iv_0_0_10_12 => prdata_o_1_0_iv_0_0_10_12, 
        RATE_LIMITER_0_rl_out_o(17) => 
        RATE_LIMITER_0_rl_out_o(17), RATE_LIMITER_0_rl_out_o(16)
         => RATE_LIMITER_0_rl_out_o(16), 
        RATE_LIMITER_0_rl_out_o(15) => 
        RATE_LIMITER_0_rl_out_o(15), RATE_LIMITER_0_rl_out_o(14)
         => RATE_LIMITER_0_rl_out_o(14), 
        RATE_LIMITER_0_rl_out_o(13) => 
        RATE_LIMITER_0_rl_out_o(13), RATE_LIMITER_0_rl_out_o(12)
         => RATE_LIMITER_0_rl_out_o(12), 
        RATE_LIMITER_0_rl_out_o(11) => 
        RATE_LIMITER_0_rl_out_o(11), RATE_LIMITER_0_rl_out_o(10)
         => RATE_LIMITER_0_rl_out_o(10), 
        RATE_LIMITER_0_rl_out_o(9) => RATE_LIMITER_0_rl_out_o(9), 
        RATE_LIMITER_0_rl_out_o(8) => RATE_LIMITER_0_rl_out_o(8), 
        RATE_LIMITER_0_rl_out_o(7) => RATE_LIMITER_0_rl_out_o(7), 
        RATE_LIMITER_0_rl_out_o(6) => RATE_LIMITER_0_rl_out_o(6), 
        RATE_LIMITER_0_rl_out_o(5) => RATE_LIMITER_0_rl_out_o(5), 
        RATE_LIMITER_0_rl_out_o(4) => RATE_LIMITER_0_rl_out_o(4), 
        RATE_LIMITER_0_rl_out_o(3) => RATE_LIMITER_0_rl_out_o(3), 
        RATE_LIMITER_0_rl_out_o(2) => RATE_LIMITER_0_rl_out_o(2), 
        RATE_LIMITER_0_rl_out_o(1) => RATE_LIMITER_0_rl_out_o(1), 
        RATE_LIMITER_0_rl_out_o(0) => RATE_LIMITER_0_rl_out_o(0), 
        prdata_o_1_iv_0_0_12_3 => prdata_o_1_iv_0_0_12_3, 
        prdata_o_1_iv_0_0_12_0 => prdata_o_1_iv_0_0_12_0, 
        prdata_o_1_iv_0_0_12_5 => prdata_o_1_iv_0_0_12_5, 
        prdata_o_1_iv_0_0_16(9) => prdata_o_1_iv_0_0_16(9), 
        prdata_o_1_iv_0_0_16(8) => prdata_o_1_iv_0_0_16(8), 
        prdata_o_1_iv_0_16_0 => prdata_o_1_iv_0_16_0, 
        prdata_o_1_iv_0_16_5 => prdata_o_1_iv_0_16_5, 
        prdata_o_1_0_iv_0_16(2) => prdata_o_1_0_iv_0_16(2), 
        prdata_o_1_0_iv_0_16(1) => prdata_o_1_0_iv_0_16(1), 
        prdata_o_1_0_iv_0_16(0) => prdata_o_1_0_iv_0_16(0), 
        prdata_o_1_iv_0_0_13(7) => prdata_o_1_iv_0_0_13(7), 
        MC_System_0_FIC_0_LOCK => MC_System_0_FIC_0_LOCK, 
        MC_System_0_FIC_0_CLK => MC_System_0_FIC_0_CLK, 
        apb3_en_if_1_stop_motor_o => apb3_en_if_1_stop_motor_o, 
        apb3_en_if_1_start_motor_o => apb3_en_if_1_start_motor_o, 
        apb3_hall_if_0_hall_sensor_polarity_o => 
        apb3_hall_if_0_hall_sensor_polarity_o, 
        apb3_en_if_1_fault_clr_o => apb3_en_if_1_fault_clr_o, 
        apb3_en_if_0_direction_config_o => 
        apb3_en_if_0_direction_config_o, prdata_o276 => 
        prdata_o276, G_15_1 => G_15_1, N_730 => N_730, N_748 => 
        N_748, prdata_o_1_iv_0_0_a3_27_out => 
        prdata_o_1_iv_0_0_a3_27_out, prdata_o_1_iv_0_0_a3_9_out
         => prdata_o_1_iv_0_0_a3_9_out, N_737 => N_737, N_759 => 
        N_759, N_705 => N_705, prdata_o_1_iv_0_0_a3_0_out => 
        prdata_o_1_iv_0_0_a3_0_out, N_734 => N_734, N_745 => 
        N_745, prdata_m1_e_8_1 => prdata_m1_e_8_1, 
        prdata_m1_e_4_1 => prdata_m1_e_4_1, prdata_m1_e_12_1 => 
        prdata_m1_e_12_1, MC_System_0_AMBA_SLAVE_0_PWRITE => 
        MC_System_0_AMBA_SLAVE_0_PWRITE, 
        MC_System_0_AMBA_SLAVE_0_PENABLE => 
        MC_System_0_AMBA_SLAVE_0_PENABLE, prdata_N_5_mux_6 => 
        prdata_N_5_mux_6, prdata_N_5_mux_7 => prdata_N_5_mux_7, 
        MC_System_0_AMBA_SLAVE_0_PSELx => 
        MC_System_0_AMBA_SLAVE_0_PSELx, N_358 => N_358, N_634 => 
        N_634, N_462 => N_462, N_449 => N_449, N_442 => N_442, 
        N_440 => N_440);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;

entity MC_System_top is

    port( A0_ADC_SDI_I   : in    std_logic;
          DEVRST_N       : in    std_logic;
          HA_i           : in    std_logic;
          HB_i           : in    std_logic;
          HC_i           : in    std_logic;
          USB_ULPI_DIR   : in    std_logic;
          USB_ULPI_NXT   : in    std_logic;
          USB_ULPI_XCLK  : in    std_logic;
          A0_ADC_CS_O    : out   std_logic;
          A0_ADC_SCK_O   : out   std_logic;
          A0_ADC_SDO_O   : out   std_logic;
          A0_PWM_UH_O    : out   std_logic;
          A0_PWM_UL_O    : out   std_logic;
          A0_PWM_VH_O    : out   std_logic;
          A0_PWM_VL_O    : out   std_logic;
          A0_PWM_WH_O    : out   std_logic;
          A0_PWM_WL_O    : out   std_logic;
          A0_RUNNING_LED : out   std_logic;
          GPIO_0_M2F     : out   std_logic;
          USB_ULPI_STP   : out   std_logic;
          USB_ULPI_DATA  : inout std_logic_vector(7 downto 0) := (others => 'Z')
        );

end MC_System_top;

architecture DEF_ARCH of MC_System_top is 

  component GND
    port( Y : out   std_logic
        );
  end component;

  component OUTBUF
    generic (IOSTD:string := "");

    port( D   : in    std_logic := 'U';
          PAD : out   std_logic
        );
  end component;

  component INBUF
    generic (IOSTD:string := "");

    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component MC_System
    port( prdata_o_1_iv_0_0_6               : in    std_logic := 'U';
          prdata_o_1_iv_0_0_0               : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_4       : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_6       : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_1       : in    std_logic := 'U';
          FOC_TRANSFORMS_0_valpha_o_0       : in    std_logic := 'U';
          prdata_o_1_iv_0_0_a3_2_0          : in    std_logic_vector(9 to 9) := (others => 'U');
          prdata_o_1_iv_0_0_a1              : in    std_logic_vector(6 downto 5) := (others => 'U');
          prdata_o_1_iv_0_12                : in    std_logic_vector(5 to 5) := (others => 'U');
          OLMNG_0_theta_o_1                 : in    std_logic := 'U';
          OLMNG_0_theta_o_4                 : in    std_logic := 'U';
          OLMNG_0_theta_o_0                 : in    std_logic := 'U';
          OLMNG_0_theta_o_6                 : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_1 : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_4 : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_0 : in    std_logic := 'U';
          SPEED_ID_IQ_PI_0_id_pi_output_o_6 : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_1 : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_4 : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_0 : in    std_logic := 'U';
          HALL_INTERFACE_1_theta_output_o_6 : in    std_logic := 'U';
          prdata_o_1_iv_0_16_0              : in    std_logic := 'U';
          prdata_o_1_iv_0_16_5              : in    std_logic := 'U';
          prdata_o_1_iv_0_14_0              : in    std_logic := 'U';
          prdata_o_1_iv_0_14_5              : in    std_logic := 'U';
          prdata_o_1_0_iv_0_11              : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_0_iv_0_5               : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_0_iv_0_3               : in    std_logic_vector(16 to 16) := (others => 'U');
          prdata_o_1_0_iv_0_4               : in    std_logic_vector(16 to 16) := (others => 'U');
          FOC_TRANSFORMS_0_iq_o_0           : in    std_logic := 'U';
          FOC_TRANSFORMS_0_iq_o_3           : in    std_logic := 'U';
          prdata_o_1_iv_0_0_13              : in    std_logic_vector(7 to 7) := (others => 'U');
          prdata_o_1_iv_0_0_5               : in    std_logic_vector(7 to 7) := (others => 'U');
          FOC_TRANSFORMS_0_id_o             : in    std_logic_vector(4 to 4) := (others => 'U');
          adc_interface_0_result_ch1_o      : in    std_logic_vector(4 to 4) := (others => 'U');
          prdata_o_1_iv_0_0_7               : in    std_logic_vector(10 to 10) := (others => 'U');
          prdata_o_1_iv_0_8                 : in    std_logic_vector(5 to 5) := (others => 'U');
          prdata_o_1_iv_0_7                 : in    std_logic_vector(5 to 5) := (others => 'U');
          prdata_o_1_iv_0_9                 : in    std_logic_vector(5 to 5) := (others => 'U');
          prdata_o_1_iv_0_6                 : in    std_logic_vector(5 to 5) := (others => 'U');
          prdata_o_1_0_iv_0_0_8             : in    std_logic_vector(14 to 14) := (others => 'U');
          prdata_o_1_0_iv_0_0_7             : in    std_logic_vector(14 to 14) := (others => 'U');
          prdata_o_1_0_iv_0_0_11_a2         : in    std_logic_vector(14 to 14) := (others => 'U');
          prdata_o_1_0_iv_0_0_11_a0         : in    std_logic_vector(14 to 14) := (others => 'U');
          prdata_o_1_0_iv_0_0_6             : in    std_logic_vector(14 to 14) := (others => 'U');
          prdata_o_1_0_iv_0_9               : in    std_logic_vector(13 to 13) := (others => 'U');
          prdata_o_1_0_iv_0_8               : in    std_logic_vector(13 to 13) := (others => 'U');
          prdata_o_1_0_iv_0_7_0             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_7_9             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_11_a2           : in    std_logic_vector(13 to 13) := (others => 'U');
          prdata_o_1_0_iv_0_11_a0           : in    std_logic_vector(13 to 13) := (others => 'U');
          prdata_o_1_0_iv_0_6_3             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_6_0             : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_14            : in    std_logic_vector(3 to 3) := (others => 'U');
          MC_System_0_AMBA_SLAVE_0_PRDATA   : in    std_logic_vector(19 to 19) := (others => 'U');
          prdata_o_0_5                      : in    std_logic_vector(17 to 17) := (others => 'U');
          prdata_o_0_3                      : in    std_logic_vector(17 to 17) := (others => 'U');
          prdata_o_1_0_iv_0_1               : in    std_logic_vector(17 to 17) := (others => 'U');
          prdata_o_1_iv_0_0_16              : in    std_logic_vector(9 downto 8) := (others => 'U');
          prdata_o_1_iv_0_0_15              : in    std_logic_vector(8 to 8) := (others => 'U');
          prdata_o_1_iv_0_0_14              : in    std_logic_vector(10 downto 8) := (others => 'U');
          prdata_o_1_0_iv_0_16              : in    std_logic_vector(2 downto 0) := (others => 'U');
          prdata_o_1_0_iv_0_15_4            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_15_0            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_15_1            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_15_2            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_14_4            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_14_0            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_14_1            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_14_2            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_12_0            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_12_3            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_12_5            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_11_0            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_11_2            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_10_0            : in    std_logic := 'U';
          prdata_o_1_iv_0_0_10_2            : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_10_0          : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_10_12         : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_11            : in    std_logic_vector(15 to 15) := (others => 'U');
          prdata_o_1_0_iv_0_0_9_11          : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_9_0           : in    std_logic := 'U';
          prdata_o_1_0_iv_0_0_9_12          : in    std_logic := 'U';
          USB_ULPI_DATA                     : inout   std_logic_vector(7 downto 0);
          MC_System_0_AMBA_SLAVE_0_PADDR    : inout   std_logic_vector(11 downto 0);
          MC_System_0_AMBA_SLAVE_0_PWDATA   : out   std_logic_vector(17 downto 0);
          MC_System_0_FIC_0_LOCK            : out   std_logic;
          MC_System_0_FIC_0_CLK             : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PSELx    : out   std_logic;
          N_737                             : in    std_logic := 'U';
          N_730                             : in    std_logic := 'U';
          prdata_o276                       : in    std_logic := 'U';
          N_358                             : in    std_logic := 'U';
          N_705                             : in    std_logic := 'U';
          prdata_o_1_iv_0_0_a3_0_out        : in    std_logic := 'U';
          prdata_m1_e_8_1                   : in    std_logic := 'U';
          prdata_m1_e_12_1                  : in    std_logic := 'U';
          prdata_o_1_iv_0_0_a3_9_out        : in    std_logic := 'U';
          N_734                             : in    std_logic := 'U';
          N_634                             : in    std_logic := 'U';
          N_449                             : in    std_logic := 'U';
          N_442                             : in    std_logic := 'U';
          N_440                             : in    std_logic := 'U';
          prdata_N_5_mux_6                  : in    std_logic := 'U';
          prdata_m1_e_4_1                   : in    std_logic := 'U';
          prdata_N_5_mux_7                  : in    std_logic := 'U';
          N_759                             : in    std_logic := 'U';
          prdata_o_1_iv_0_0_a3_27_out       : in    std_logic := 'U';
          G_15_1                            : in    std_logic := 'U';
          N_748                             : in    std_logic := 'U';
          N_462                             : in    std_logic := 'U';
          USB_ULPI_XCLK                     : in    std_logic := 'U';
          USB_ULPI_STP                      : out   std_logic;
          USB_ULPI_NXT                      : in    std_logic := 'U';
          USB_ULPI_DIR                      : in    std_logic := 'U';
          N_745                             : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PENABLE  : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PWRITE   : out   std_logic;
          GPIO_0_M2F_c                      : out   std_logic
        );
  end component;

  component BLDC_HALL_Axis
    port( FOC_TRANSFORMS_0_id_o_4            : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_6            : out   std_logic;
          FOC_TRANSFORMS_0_iq_o_9            : out   std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_5  : out   std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_6  : out   std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_9  : out   std_logic;
          SPEED_ID_IQ_PI_0_id_pi_output_o_11 : out   std_logic;
          HALL_INTERFACE_1_theta_output_o_0  : out   std_logic;
          HALL_INTERFACE_1_theta_output_o_1  : out   std_logic;
          HALL_INTERFACE_1_theta_output_o_4  : out   std_logic;
          HALL_INTERFACE_1_theta_output_o_6  : out   std_logic;
          OLMNG_0_theta_o_5                  : out   std_logic;
          OLMNG_0_theta_o_6                  : out   std_logic;
          OLMNG_0_theta_o_9                  : out   std_logic;
          OLMNG_0_theta_o_11                 : out   std_logic;
          FOC_TRANSFORMS_0_valpha_o_5        : out   std_logic;
          FOC_TRANSFORMS_0_valpha_o_6        : out   std_logic;
          FOC_TRANSFORMS_0_valpha_o_9        : out   std_logic;
          FOC_TRANSFORMS_0_valpha_o_11       : out   std_logic;
          adc_interface_0_result_ch1_o_4     : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PWDATA    : in    std_logic_vector(17 downto 0) := (others => 'U');
          MC_System_0_AMBA_SLAVE_0_PRDATA    : out   std_logic_vector(19 to 19);
          prdata_o_1_iv_0_0_a3_2_0           : out   std_logic_vector(9 to 9);
          prdata_o_1_0_iv_0_8                : out   std_logic_vector(13 to 13);
          MC_System_0_AMBA_SLAVE_0_PADDR     : in    std_logic_vector(11 downto 0) := (others => 'U');
          prdata_o_1_iv_0_0_7                : out   std_logic_vector(10 to 10);
          prdata_o_1_iv_0_0_15               : out   std_logic_vector(8 to 8);
          prdata_o_0_5                       : out   std_logic_vector(17 to 17);
          prdata_o_1_iv_0_0_5                : out   std_logic_vector(7 to 7);
          prdata_o_1_iv_0_0_a1               : out   std_logic_vector(6 downto 5);
          prdata_o_1_iv_0_0_0                : out   std_logic;
          prdata_o_1_iv_0_0_6                : out   std_logic;
          prdata_o_1_0_iv_0_0_11_a2          : out   std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_0_11_a0          : out   std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_11_a2            : out   std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_11_a0            : out   std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_1                : out   std_logic_vector(17 to 17);
          prdata_o_1_iv_0_9                  : out   std_logic_vector(5 to 5);
          prdata_o_1_iv_0_8                  : out   std_logic_vector(5 to 5);
          prdata_o_1_iv_0_6                  : out   std_logic_vector(5 to 5);
          prdata_o_1_iv_0_0_10_2             : out   std_logic;
          prdata_o_1_iv_0_0_10_0             : out   std_logic;
          prdata_o_1_0_iv_0_0_7              : out   std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_0_6              : out   std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_7_0              : out   std_logic;
          prdata_o_1_0_iv_0_7_9              : out   std_logic;
          prdata_o_1_0_iv_0_6_3              : out   std_logic;
          prdata_o_1_0_iv_0_6_0              : out   std_logic;
          prdata_o_1_0_iv_0_5                : out   std_logic_vector(16 to 16);
          prdata_o_1_0_iv_0_4                : out   std_logic_vector(16 to 16);
          prdata_o_1_0_iv_0_3                : out   std_logic_vector(16 to 16);
          prdata_o_1_iv_0_12                 : out   std_logic_vector(5 to 5);
          prdata_o_1_iv_0_7                  : out   std_logic_vector(5 to 5);
          prdata_o_1_iv_0_0_14               : out   std_logic_vector(10 downto 8);
          prdata_o_1_iv_0_14_0               : out   std_logic;
          prdata_o_1_iv_0_14_5               : out   std_logic;
          prdata_o_1_iv_0_0_11_2             : out   std_logic;
          prdata_o_1_iv_0_0_11_0             : out   std_logic;
          prdata_o_1_0_iv_0_14_2             : out   std_logic;
          prdata_o_1_0_iv_0_14_0             : out   std_logic;
          prdata_o_1_0_iv_0_14_1             : out   std_logic;
          prdata_o_1_0_iv_0_14_4             : out   std_logic;
          prdata_o_1_0_iv_0_0_8              : out   std_logic_vector(14 to 14);
          prdata_o_1_0_iv_0_9                : out   std_logic_vector(13 to 13);
          prdata_o_1_0_iv_0_0_11             : out   std_logic_vector(15 to 15);
          prdata_o_1_0_iv_0_11               : out   std_logic_vector(16 to 16);
          prdata_o_0_3                       : out   std_logic_vector(17 to 17);
          prdata_o_1_0_iv_0_15_0             : out   std_logic;
          prdata_o_1_0_iv_0_15_4             : out   std_logic;
          prdata_o_1_0_iv_0_15_2             : out   std_logic;
          prdata_o_1_0_iv_0_15_1             : out   std_logic;
          prdata_o_1_0_iv_0_0_14             : out   std_logic_vector(3 to 3);
          prdata_o_1_0_iv_0_0_9_11           : out   std_logic;
          prdata_o_1_0_iv_0_0_9_12           : out   std_logic;
          prdata_o_1_0_iv_0_0_9_0            : out   std_logic;
          prdata_o_1_0_iv_0_0_10_0           : out   std_logic;
          prdata_o_1_0_iv_0_0_10_12          : out   std_logic;
          prdata_o_1_iv_0_0_12_3             : out   std_logic;
          prdata_o_1_iv_0_0_12_0             : out   std_logic;
          prdata_o_1_iv_0_0_12_5             : out   std_logic;
          prdata_o_1_iv_0_0_16               : out   std_logic_vector(9 downto 8);
          prdata_o_1_iv_0_16_0               : out   std_logic;
          prdata_o_1_iv_0_16_5               : out   std_logic;
          prdata_o_1_0_iv_0_16               : out   std_logic_vector(2 downto 0);
          prdata_o_1_iv_0_0_13               : out   std_logic_vector(7 to 7);
          MC_System_0_FIC_0_LOCK             : in    std_logic := 'U';
          MC_System_0_FIC_0_CLK              : in    std_logic := 'U';
          A0_PWM_VL_O_c                      : out   std_logic;
          A0_PWM_UH_O_c                      : out   std_logic;
          A0_PWM_VH_O_c                      : out   std_logic;
          A0_PWM_WH_O_c                      : out   std_logic;
          HA_i_c                             : in    std_logic := 'U';
          HB_i_c                             : in    std_logic := 'U';
          HC_i_c                             : in    std_logic := 'U';
          A0_ADC_SDI_I_c                     : in    std_logic := 'U';
          A0_ADC_SDO_O_c                     : out   std_logic;
          A0_ADC_CS_O_c                      : out   std_logic;
          A0_ADC_SCK_O_c                     : out   std_logic;
          prdata_o276                        : out   std_logic;
          G_15_1                             : out   std_logic;
          N_730                              : out   std_logic;
          N_748                              : out   std_logic;
          prdata_o_1_iv_0_0_a3_27_out        : out   std_logic;
          prdata_o_1_iv_0_0_a3_9_out         : out   std_logic;
          N_737                              : out   std_logic;
          N_759                              : out   std_logic;
          N_705                              : out   std_logic;
          prdata_o_1_iv_0_0_a3_0_out         : out   std_logic;
          N_734                              : out   std_logic;
          N_745                              : in    std_logic := 'U';
          prdata_m1_e_8_1                    : out   std_logic;
          prdata_m1_e_4_1                    : out   std_logic;
          prdata_m1_e_12_1                   : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PWRITE    : in    std_logic := 'U';
          MC_System_0_AMBA_SLAVE_0_PENABLE   : in    std_logic := 'U';
          prdata_N_5_mux_6                   : out   std_logic;
          prdata_N_5_mux_7                   : out   std_logic;
          MC_System_0_AMBA_SLAVE_0_PSELx     : in    std_logic := 'U';
          N_358                              : out   std_logic;
          N_634                              : out   std_logic;
          N_462                              : out   std_logic;
          N_449                              : out   std_logic;
          N_442                              : out   std_logic;
          N_440                              : out   std_logic
        );
  end component;

    signal MC_System_0_AMBA_SLAVE_0_PADDR : 
        std_logic_vector(11 downto 0);
    signal MC_System_0_AMBA_SLAVE_0_PWDATA : 
        std_logic_vector(17 downto 0);
    signal MC_System_0_AMBA_SLAVE_0_PRDATA : 
        std_logic_vector(19 to 19);
    signal \BLDC_HALL_Axis_0.adc_interface_0_result_ch1_o\ : 
        std_logic_vector(4 to 4);
    signal \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_id_o\ : 
        std_logic_vector(4 to 4);
    signal \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_iq_o\ : 
        std_logic_vector(9 downto 6);
    signal \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_valpha_o\ : 
        std_logic_vector(11 downto 5);
    signal \BLDC_HALL_Axis_0.SPEED_ID_IQ_PI_0_id_pi_output_o\ : 
        std_logic_vector(11 downto 5);
    signal \BLDC_HALL_Axis_0.OLMNG_0_theta_o\ : 
        std_logic_vector(11 downto 5);
    signal \BLDC_HALL_Axis_0.HALL_INTERFACE_1_theta_output_o\ : 
        std_logic_vector(11 downto 5);
    signal \BLDC_HALL_Axis_0.prdata_o_0_5\ : 
        std_logic_vector(17 to 17);
    signal \BLDC_HALL_Axis_0.prdata_o_0_3\ : 
        std_logic_vector(17 to 17);
    signal prdata_o_1_0_iv_0_11_a0 : std_logic_vector(13 to 13);
    signal prdata_o_1_0_iv_0_11_a2 : std_logic_vector(13 to 13);
    signal prdata_o_1_0_iv_0_0_11_a0 : 
        std_logic_vector(14 to 14);
    signal prdata_o_1_0_iv_0_0_11_a2 : 
        std_logic_vector(14 to 14);
    signal prdata_o_1_iv_0_0_a1 : std_logic_vector(6 downto 5);
    signal 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_a3_2_0\
         : std_logic_vector(9 to 9);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_5\
         : std_logic_vector(7 to 7);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_12\
         : std_logic_vector(12 downto 7);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_13\
         : std_logic_vector(7 to 7);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_10\
         : std_logic_vector(12 downto 10);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_11\
         : std_logic_vector(12 downto 10);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_3\
         : std_logic_vector(16 to 16);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_4\
         : std_logic_vector(16 to 16);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_5\
         : std_logic_vector(16 to 16);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_6\
         : std_logic_vector(16 downto 13);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_11\
         : std_logic_vector(16 to 16);
    signal 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_9\
         : std_logic_vector(15 downto 3);
    signal 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_10\
         : std_logic_vector(15 downto 3);
    signal 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_11\
         : std_logic_vector(15 to 15);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_7\
         : std_logic_vector(13 downto 4);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_8\
         : std_logic_vector(13 to 13);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_9\
         : std_logic_vector(13 to 13);
    signal 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_6\
         : std_logic_vector(14 to 14);
    signal 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_7\
         : std_logic_vector(14 to 14);
    signal 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_8\
         : std_logic_vector(14 to 14);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_14\
         : std_logic_vector(4 downto 0);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_15\
         : std_logic_vector(4 downto 0);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_7\
         : std_logic_vector(10 to 10);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_14\
         : std_logic_vector(10 downto 8);
    signal 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_14\
         : std_logic_vector(3 to 3);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_16\
         : std_logic_vector(2 downto 0);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0\ : 
        std_logic_vector(11 downto 5);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_14\
         : std_logic_vector(11 downto 6);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_16\
         : std_logic_vector(11 downto 6);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_16\
         : std_logic_vector(9 downto 8);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_15\
         : std_logic_vector(8 to 8);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_6\ : 
        std_logic_vector(5 to 5);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_7\ : 
        std_logic_vector(5 to 5);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_8\ : 
        std_logic_vector(5 to 5);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_9\ : 
        std_logic_vector(5 to 5);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_12\
         : std_logic_vector(5 to 5);
    signal \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_1\
         : std_logic_vector(17 to 17);
    signal MC_System_0_AMBA_SLAVE_0_PENABLE, 
        MC_System_0_AMBA_SLAVE_0_PWRITE, MC_System_0_FIC_0_LOCK, 
        MC_System_0_FIC_0_CLK, \GND\, \VCC\, 
        MC_System_0_AMBA_SLAVE_0_PSELx, 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o276\, 
        \BLDC_HALL_Axis_0.N_440\, \BLDC_HALL_Axis_0.N_442\, 
        \BLDC_HALL_Axis_0.N_449\, \BLDC_HALL_Axis_0.N_462\, 
        \BLDC_HALL_Axis_0.N_634\, G_15_1, 
        \BLDC_HALL_Axis_0.N_705\, \BLDC_HALL_Axis_0.N_730\, 
        \BLDC_HALL_Axis_0.N_734\, \BLDC_HALL_Axis_0.N_737\, 
        \BLDC_HALL_Axis_0.N_745\, \BLDC_HALL_Axis_0.N_748\, 
        A0_ADC_SDI_I_c, HA_i_c, HB_i_c, HC_i_c, A0_ADC_CS_O_c, 
        A0_ADC_SCK_O_c, A0_ADC_SDO_O_c, A0_PWM_UH_O_c, 
        A0_PWM_VH_O_c, A0_PWM_VL_O_c, A0_PWM_WH_O_c, GPIO_0_M2F_c, 
        \BLDC_HALL_Axis_0.N_759\, \BLDC_HALL_Axis_0.N_358\, 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_a3_0_out\, 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_a3_27_out\, 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_6\, 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_7\, 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_a3_9_out\, 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m1_e_12_1\, 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m1_e_4_1\, 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m1_e_8_1\
         : std_logic;

    for all : MC_System
	Use entity work.MC_System(DEF_ARCH);
    for all : BLDC_HALL_Axis
	Use entity work.BLDC_HALL_Axis(DEF_ARCH);
begin 


    GND_Z : GND
      port map(Y => \GND\);
    
    A0_PWM_VH_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A0_PWM_VH_O_c, PAD => A0_PWM_VH_O);
    
    A0_PWM_UH_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A0_PWM_UH_O_c, PAD => A0_PWM_UH_O);
    
    HB_i_ibuf : INBUF
      generic map(IOSTD => "")

      port map(PAD => HB_i, Y => HB_i_c);
    
    A0_PWM_WL_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A0_PWM_VL_O_c, PAD => A0_PWM_WL_O);
    
    VCC_Z : VCC
      port map(Y => \VCC\);
    
    MC_System_0 : MC_System
      port map(prdata_o_1_iv_0_0_6 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0\(11), 
        prdata_o_1_iv_0_0_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0\(5), 
        FOC_TRANSFORMS_0_valpha_o_4 => 
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_valpha_o\(9), 
        FOC_TRANSFORMS_0_valpha_o_6 => 
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_valpha_o\(11), 
        FOC_TRANSFORMS_0_valpha_o_1 => 
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_valpha_o\(6), 
        FOC_TRANSFORMS_0_valpha_o_0 => 
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_valpha_o\(5), 
        prdata_o_1_iv_0_0_a3_2_0(9) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_a3_2_0\(9), 
        prdata_o_1_iv_0_0_a1(6) => prdata_o_1_iv_0_0_a1(6), 
        prdata_o_1_iv_0_0_a1(5) => prdata_o_1_iv_0_0_a1(5), 
        prdata_o_1_iv_0_12(5) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_12\(5), 
        OLMNG_0_theta_o_1 => 
        \BLDC_HALL_Axis_0.OLMNG_0_theta_o\(6), OLMNG_0_theta_o_4
         => \BLDC_HALL_Axis_0.OLMNG_0_theta_o\(9), 
        OLMNG_0_theta_o_0 => 
        \BLDC_HALL_Axis_0.OLMNG_0_theta_o\(5), OLMNG_0_theta_o_6
         => \BLDC_HALL_Axis_0.OLMNG_0_theta_o\(11), 
        SPEED_ID_IQ_PI_0_id_pi_output_o_1 => 
        \BLDC_HALL_Axis_0.SPEED_ID_IQ_PI_0_id_pi_output_o\(6), 
        SPEED_ID_IQ_PI_0_id_pi_output_o_4 => 
        \BLDC_HALL_Axis_0.SPEED_ID_IQ_PI_0_id_pi_output_o\(9), 
        SPEED_ID_IQ_PI_0_id_pi_output_o_0 => 
        \BLDC_HALL_Axis_0.SPEED_ID_IQ_PI_0_id_pi_output_o\(5), 
        SPEED_ID_IQ_PI_0_id_pi_output_o_6 => 
        \BLDC_HALL_Axis_0.SPEED_ID_IQ_PI_0_id_pi_output_o\(11), 
        HALL_INTERFACE_1_theta_output_o_1 => 
        \BLDC_HALL_Axis_0.HALL_INTERFACE_1_theta_output_o\(6), 
        HALL_INTERFACE_1_theta_output_o_4 => 
        \BLDC_HALL_Axis_0.HALL_INTERFACE_1_theta_output_o\(9), 
        HALL_INTERFACE_1_theta_output_o_0 => 
        \BLDC_HALL_Axis_0.HALL_INTERFACE_1_theta_output_o\(5), 
        HALL_INTERFACE_1_theta_output_o_6 => 
        \BLDC_HALL_Axis_0.HALL_INTERFACE_1_theta_output_o\(11), 
        prdata_o_1_iv_0_16_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_16\(6), 
        prdata_o_1_iv_0_16_5 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_16\(11), 
        prdata_o_1_iv_0_14_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_14\(6), 
        prdata_o_1_iv_0_14_5 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_14\(11), 
        prdata_o_1_0_iv_0_11(16) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_11\(16), 
        prdata_o_1_0_iv_0_5(16) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_5\(16), 
        prdata_o_1_0_iv_0_3(16) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_3\(16), 
        prdata_o_1_0_iv_0_4(16) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_4\(16), 
        FOC_TRANSFORMS_0_iq_o_0 => 
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_iq_o\(6), 
        FOC_TRANSFORMS_0_iq_o_3 => 
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_iq_o\(9), 
        prdata_o_1_iv_0_0_13(7) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_13\(7), 
        prdata_o_1_iv_0_0_5(7) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_5\(7), 
        FOC_TRANSFORMS_0_id_o(4) => 
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_id_o\(4), 
        adc_interface_0_result_ch1_o(4) => 
        \BLDC_HALL_Axis_0.adc_interface_0_result_ch1_o\(4), 
        prdata_o_1_iv_0_0_7(10) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_7\(10), 
        prdata_o_1_iv_0_8(5) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_8\(5), 
        prdata_o_1_iv_0_7(5) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_7\(5), 
        prdata_o_1_iv_0_9(5) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_9\(5), 
        prdata_o_1_iv_0_6(5) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_6\(5), 
        prdata_o_1_0_iv_0_0_8(14) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_8\(14), 
        prdata_o_1_0_iv_0_0_7(14) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_7\(14), 
        prdata_o_1_0_iv_0_0_11_a2(14) => 
        prdata_o_1_0_iv_0_0_11_a2(14), 
        prdata_o_1_0_iv_0_0_11_a0(14) => 
        prdata_o_1_0_iv_0_0_11_a0(14), prdata_o_1_0_iv_0_0_6(14)
         => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_6\(14), 
        prdata_o_1_0_iv_0_9(13) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_9\(13), 
        prdata_o_1_0_iv_0_8(13) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_8\(13), 
        prdata_o_1_0_iv_0_7_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_7\(4), 
        prdata_o_1_0_iv_0_7_9 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_7\(13), 
        prdata_o_1_0_iv_0_11_a2(13) => 
        prdata_o_1_0_iv_0_11_a2(13), prdata_o_1_0_iv_0_11_a0(13)
         => prdata_o_1_0_iv_0_11_a0(13), prdata_o_1_0_iv_0_6_3
         => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_6\(16), 
        prdata_o_1_0_iv_0_6_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_6\(13), 
        prdata_o_1_0_iv_0_0_14(3) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_14\(3), 
        MC_System_0_AMBA_SLAVE_0_PRDATA(19) => 
        MC_System_0_AMBA_SLAVE_0_PRDATA(19), prdata_o_0_5(17) => 
        \BLDC_HALL_Axis_0.prdata_o_0_5\(17), prdata_o_0_3(17) => 
        \BLDC_HALL_Axis_0.prdata_o_0_3\(17), 
        prdata_o_1_0_iv_0_1(17) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_1\(17), 
        prdata_o_1_iv_0_0_16(9) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_16\(9), 
        prdata_o_1_iv_0_0_16(8) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_16\(8), 
        prdata_o_1_iv_0_0_15(8) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_15\(8), 
        prdata_o_1_iv_0_0_14(10) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_14\(10), 
        prdata_o_1_iv_0_0_14(9) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_14\(9), 
        prdata_o_1_iv_0_0_14(8) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_14\(8), 
        prdata_o_1_0_iv_0_16(2) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_16\(2), 
        prdata_o_1_0_iv_0_16(1) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_16\(1), 
        prdata_o_1_0_iv_0_16(0) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_16\(0), 
        prdata_o_1_0_iv_0_15_4 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_15\(4), 
        prdata_o_1_0_iv_0_15_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_15\(0), 
        prdata_o_1_0_iv_0_15_1 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_15\(1), 
        prdata_o_1_0_iv_0_15_2 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_15\(2), 
        prdata_o_1_0_iv_0_14_4 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_14\(4), 
        prdata_o_1_0_iv_0_14_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_14\(0), 
        prdata_o_1_0_iv_0_14_1 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_14\(1), 
        prdata_o_1_0_iv_0_14_2 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_14\(2), 
        prdata_o_1_iv_0_0_12_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_12\(7), 
        prdata_o_1_iv_0_0_12_3 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_12\(10), 
        prdata_o_1_iv_0_0_12_5 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_12\(12), 
        prdata_o_1_iv_0_0_11_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_11\(10), 
        prdata_o_1_iv_0_0_11_2 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_11\(12), 
        prdata_o_1_iv_0_0_10_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_10\(10), 
        prdata_o_1_iv_0_0_10_2 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_10\(12), 
        prdata_o_1_0_iv_0_0_10_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_10\(3), 
        prdata_o_1_0_iv_0_0_10_12 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_10\(15), 
        prdata_o_1_0_iv_0_0_11(15) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_11\(15), 
        prdata_o_1_0_iv_0_0_9_11 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_9\(14), 
        prdata_o_1_0_iv_0_0_9_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_9\(3), 
        prdata_o_1_0_iv_0_0_9_12 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_9\(15), 
        USB_ULPI_DATA(7) => USB_ULPI_DATA(7), USB_ULPI_DATA(6)
         => USB_ULPI_DATA(6), USB_ULPI_DATA(5) => 
        USB_ULPI_DATA(5), USB_ULPI_DATA(4) => USB_ULPI_DATA(4), 
        USB_ULPI_DATA(3) => USB_ULPI_DATA(3), USB_ULPI_DATA(2)
         => USB_ULPI_DATA(2), USB_ULPI_DATA(1) => 
        USB_ULPI_DATA(1), USB_ULPI_DATA(0) => USB_ULPI_DATA(0), 
        MC_System_0_AMBA_SLAVE_0_PADDR(11) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(11), 
        MC_System_0_AMBA_SLAVE_0_PADDR(10) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(10), 
        MC_System_0_AMBA_SLAVE_0_PADDR(9) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(9), 
        MC_System_0_AMBA_SLAVE_0_PADDR(8) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(8), 
        MC_System_0_AMBA_SLAVE_0_PADDR(7) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(7), 
        MC_System_0_AMBA_SLAVE_0_PADDR(6) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(6), 
        MC_System_0_AMBA_SLAVE_0_PADDR(5) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), 
        MC_System_0_AMBA_SLAVE_0_PADDR(4) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), 
        MC_System_0_AMBA_SLAVE_0_PADDR(3) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), 
        MC_System_0_AMBA_SLAVE_0_PADDR(2) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), 
        MC_System_0_AMBA_SLAVE_0_PADDR(1) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(1), 
        MC_System_0_AMBA_SLAVE_0_PADDR(0) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(0), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(17) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(17), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(16) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(16), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(15) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(15), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(14) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(14), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(13) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(13), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(12) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(12), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(11) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(11), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(10) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(10), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(9) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(9), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(8) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(8), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(7) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(7), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(6) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(6), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(5) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(5), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(4) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(4), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(3) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(3), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(2) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(2), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(1) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(1), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(0) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(0), 
        MC_System_0_FIC_0_LOCK => MC_System_0_FIC_0_LOCK, 
        MC_System_0_FIC_0_CLK => MC_System_0_FIC_0_CLK, 
        MC_System_0_AMBA_SLAVE_0_PSELx => 
        MC_System_0_AMBA_SLAVE_0_PSELx, N_737 => 
        \BLDC_HALL_Axis_0.N_737\, N_730 => 
        \BLDC_HALL_Axis_0.N_730\, prdata_o276 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o276\, 
        N_358 => \BLDC_HALL_Axis_0.N_358\, N_705 => 
        \BLDC_HALL_Axis_0.N_705\, prdata_o_1_iv_0_0_a3_0_out => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_a3_0_out\, 
        prdata_m1_e_8_1 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m1_e_8_1\, 
        prdata_m1_e_12_1 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m1_e_12_1\, 
        prdata_o_1_iv_0_0_a3_9_out => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_a3_9_out\, 
        N_734 => \BLDC_HALL_Axis_0.N_734\, N_634 => 
        \BLDC_HALL_Axis_0.N_634\, N_449 => 
        \BLDC_HALL_Axis_0.N_449\, N_442 => 
        \BLDC_HALL_Axis_0.N_442\, N_440 => 
        \BLDC_HALL_Axis_0.N_440\, prdata_N_5_mux_6 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_6\, 
        prdata_m1_e_4_1 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m1_e_4_1\, 
        prdata_N_5_mux_7 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_7\, N_759
         => \BLDC_HALL_Axis_0.N_759\, prdata_o_1_iv_0_0_a3_27_out
         => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_a3_27_out\, 
        G_15_1 => G_15_1, N_748 => \BLDC_HALL_Axis_0.N_748\, 
        N_462 => \BLDC_HALL_Axis_0.N_462\, USB_ULPI_XCLK => 
        USB_ULPI_XCLK, USB_ULPI_STP => USB_ULPI_STP, USB_ULPI_NXT
         => USB_ULPI_NXT, USB_ULPI_DIR => USB_ULPI_DIR, N_745 => 
        \BLDC_HALL_Axis_0.N_745\, 
        MC_System_0_AMBA_SLAVE_0_PENABLE => 
        MC_System_0_AMBA_SLAVE_0_PENABLE, 
        MC_System_0_AMBA_SLAVE_0_PWRITE => 
        MC_System_0_AMBA_SLAVE_0_PWRITE, GPIO_0_M2F_c => 
        GPIO_0_M2F_c);
    
    BLDC_HALL_Axis_0 : BLDC_HALL_Axis
      port map(FOC_TRANSFORMS_0_id_o_4 => 
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_id_o\(4), 
        FOC_TRANSFORMS_0_iq_o_6 => 
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_iq_o\(6), 
        FOC_TRANSFORMS_0_iq_o_9 => 
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_iq_o\(9), 
        SPEED_ID_IQ_PI_0_id_pi_output_o_5 => 
        \BLDC_HALL_Axis_0.SPEED_ID_IQ_PI_0_id_pi_output_o\(5), 
        SPEED_ID_IQ_PI_0_id_pi_output_o_6 => 
        \BLDC_HALL_Axis_0.SPEED_ID_IQ_PI_0_id_pi_output_o\(6), 
        SPEED_ID_IQ_PI_0_id_pi_output_o_9 => 
        \BLDC_HALL_Axis_0.SPEED_ID_IQ_PI_0_id_pi_output_o\(9), 
        SPEED_ID_IQ_PI_0_id_pi_output_o_11 => 
        \BLDC_HALL_Axis_0.SPEED_ID_IQ_PI_0_id_pi_output_o\(11), 
        HALL_INTERFACE_1_theta_output_o_0 => 
        \BLDC_HALL_Axis_0.HALL_INTERFACE_1_theta_output_o\(5), 
        HALL_INTERFACE_1_theta_output_o_1 => 
        \BLDC_HALL_Axis_0.HALL_INTERFACE_1_theta_output_o\(6), 
        HALL_INTERFACE_1_theta_output_o_4 => 
        \BLDC_HALL_Axis_0.HALL_INTERFACE_1_theta_output_o\(9), 
        HALL_INTERFACE_1_theta_output_o_6 => 
        \BLDC_HALL_Axis_0.HALL_INTERFACE_1_theta_output_o\(11), 
        OLMNG_0_theta_o_5 => 
        \BLDC_HALL_Axis_0.OLMNG_0_theta_o\(5), OLMNG_0_theta_o_6
         => \BLDC_HALL_Axis_0.OLMNG_0_theta_o\(6), 
        OLMNG_0_theta_o_9 => 
        \BLDC_HALL_Axis_0.OLMNG_0_theta_o\(9), OLMNG_0_theta_o_11
         => \BLDC_HALL_Axis_0.OLMNG_0_theta_o\(11), 
        FOC_TRANSFORMS_0_valpha_o_5 => 
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_valpha_o\(5), 
        FOC_TRANSFORMS_0_valpha_o_6 => 
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_valpha_o\(6), 
        FOC_TRANSFORMS_0_valpha_o_9 => 
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_valpha_o\(9), 
        FOC_TRANSFORMS_0_valpha_o_11 => 
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_valpha_o\(11), 
        adc_interface_0_result_ch1_o_4 => 
        \BLDC_HALL_Axis_0.adc_interface_0_result_ch1_o\(4), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(17) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(17), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(16) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(16), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(15) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(15), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(14) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(14), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(13) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(13), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(12) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(12), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(11) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(11), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(10) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(10), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(9) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(9), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(8) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(8), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(7) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(7), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(6) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(6), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(5) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(5), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(4) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(4), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(3) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(3), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(2) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(2), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(1) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(1), 
        MC_System_0_AMBA_SLAVE_0_PWDATA(0) => 
        MC_System_0_AMBA_SLAVE_0_PWDATA(0), 
        MC_System_0_AMBA_SLAVE_0_PRDATA(19) => 
        MC_System_0_AMBA_SLAVE_0_PRDATA(19), 
        prdata_o_1_iv_0_0_a3_2_0(9) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_a3_2_0\(9), 
        prdata_o_1_0_iv_0_8(13) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_8\(13), 
        MC_System_0_AMBA_SLAVE_0_PADDR(11) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(11), 
        MC_System_0_AMBA_SLAVE_0_PADDR(10) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(10), 
        MC_System_0_AMBA_SLAVE_0_PADDR(9) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(9), 
        MC_System_0_AMBA_SLAVE_0_PADDR(8) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(8), 
        MC_System_0_AMBA_SLAVE_0_PADDR(7) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(7), 
        MC_System_0_AMBA_SLAVE_0_PADDR(6) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(6), 
        MC_System_0_AMBA_SLAVE_0_PADDR(5) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(5), 
        MC_System_0_AMBA_SLAVE_0_PADDR(4) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(4), 
        MC_System_0_AMBA_SLAVE_0_PADDR(3) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(3), 
        MC_System_0_AMBA_SLAVE_0_PADDR(2) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(2), 
        MC_System_0_AMBA_SLAVE_0_PADDR(1) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(1), 
        MC_System_0_AMBA_SLAVE_0_PADDR(0) => 
        MC_System_0_AMBA_SLAVE_0_PADDR(0), 
        prdata_o_1_iv_0_0_7(10) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_7\(10), 
        prdata_o_1_iv_0_0_15(8) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_15\(8), 
        prdata_o_0_5(17) => \BLDC_HALL_Axis_0.prdata_o_0_5\(17), 
        prdata_o_1_iv_0_0_5(7) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_5\(7), 
        prdata_o_1_iv_0_0_a1(6) => prdata_o_1_iv_0_0_a1(6), 
        prdata_o_1_iv_0_0_a1(5) => prdata_o_1_iv_0_0_a1(5), 
        prdata_o_1_iv_0_0_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0\(5), 
        prdata_o_1_iv_0_0_6 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0\(11), 
        prdata_o_1_0_iv_0_0_11_a2(14) => 
        prdata_o_1_0_iv_0_0_11_a2(14), 
        prdata_o_1_0_iv_0_0_11_a0(14) => 
        prdata_o_1_0_iv_0_0_11_a0(14), 
        prdata_o_1_0_iv_0_11_a2(13) => 
        prdata_o_1_0_iv_0_11_a2(13), prdata_o_1_0_iv_0_11_a0(13)
         => prdata_o_1_0_iv_0_11_a0(13), prdata_o_1_0_iv_0_1(17)
         => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_1\(17), 
        prdata_o_1_iv_0_9(5) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_9\(5), 
        prdata_o_1_iv_0_8(5) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_8\(5), 
        prdata_o_1_iv_0_6(5) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_6\(5), 
        prdata_o_1_iv_0_0_10_2 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_10\(12), 
        prdata_o_1_iv_0_0_10_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_10\(10), 
        prdata_o_1_0_iv_0_0_7(14) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_7\(14), 
        prdata_o_1_0_iv_0_0_6(14) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_6\(14), 
        prdata_o_1_0_iv_0_7_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_7\(4), 
        prdata_o_1_0_iv_0_7_9 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_7\(13), 
        prdata_o_1_0_iv_0_6_3 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_6\(16), 
        prdata_o_1_0_iv_0_6_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_6\(13), 
        prdata_o_1_0_iv_0_5(16) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_5\(16), 
        prdata_o_1_0_iv_0_4(16) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_4\(16), 
        prdata_o_1_0_iv_0_3(16) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_3\(16), 
        prdata_o_1_iv_0_12(5) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_12\(5), 
        prdata_o_1_iv_0_7(5) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_7\(5), 
        prdata_o_1_iv_0_0_14(10) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_14\(10), 
        prdata_o_1_iv_0_0_14(9) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_14\(9), 
        prdata_o_1_iv_0_0_14(8) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_14\(8), 
        prdata_o_1_iv_0_14_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_14\(6), 
        prdata_o_1_iv_0_14_5 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_14\(11), 
        prdata_o_1_iv_0_0_11_2 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_11\(12), 
        prdata_o_1_iv_0_0_11_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_11\(10), 
        prdata_o_1_0_iv_0_14_2 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_14\(2), 
        prdata_o_1_0_iv_0_14_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_14\(0), 
        prdata_o_1_0_iv_0_14_1 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_14\(1), 
        prdata_o_1_0_iv_0_14_4 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_14\(4), 
        prdata_o_1_0_iv_0_0_8(14) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_8\(14), 
        prdata_o_1_0_iv_0_9(13) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_9\(13), 
        prdata_o_1_0_iv_0_0_11(15) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_11\(15), 
        prdata_o_1_0_iv_0_11(16) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_11\(16), 
        prdata_o_0_3(17) => \BLDC_HALL_Axis_0.prdata_o_0_3\(17), 
        prdata_o_1_0_iv_0_15_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_15\(0), 
        prdata_o_1_0_iv_0_15_4 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_15\(4), 
        prdata_o_1_0_iv_0_15_2 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_15\(2), 
        prdata_o_1_0_iv_0_15_1 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_15\(1), 
        prdata_o_1_0_iv_0_0_14(3) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_14\(3), 
        prdata_o_1_0_iv_0_0_9_11 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_9\(14), 
        prdata_o_1_0_iv_0_0_9_12 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_9\(15), 
        prdata_o_1_0_iv_0_0_9_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_9\(3), 
        prdata_o_1_0_iv_0_0_10_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_10\(3), 
        prdata_o_1_0_iv_0_0_10_12 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_0_10\(15), 
        prdata_o_1_iv_0_0_12_3 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_12\(10), 
        prdata_o_1_iv_0_0_12_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_12\(7), 
        prdata_o_1_iv_0_0_12_5 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_12\(12), 
        prdata_o_1_iv_0_0_16(9) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_16\(9), 
        prdata_o_1_iv_0_0_16(8) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_16\(8), 
        prdata_o_1_iv_0_16_0 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_16\(6), 
        prdata_o_1_iv_0_16_5 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_16\(11), 
        prdata_o_1_0_iv_0_16(2) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_16\(2), 
        prdata_o_1_0_iv_0_16(1) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_16\(1), 
        prdata_o_1_0_iv_0_16(0) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_16\(0), 
        prdata_o_1_iv_0_0_13(7) => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_13\(7), 
        MC_System_0_FIC_0_LOCK => MC_System_0_FIC_0_LOCK, 
        MC_System_0_FIC_0_CLK => MC_System_0_FIC_0_CLK, 
        A0_PWM_VL_O_c => A0_PWM_VL_O_c, A0_PWM_UH_O_c => 
        A0_PWM_UH_O_c, A0_PWM_VH_O_c => A0_PWM_VH_O_c, 
        A0_PWM_WH_O_c => A0_PWM_WH_O_c, HA_i_c => HA_i_c, HB_i_c
         => HB_i_c, HC_i_c => HC_i_c, A0_ADC_SDI_I_c => 
        A0_ADC_SDI_I_c, A0_ADC_SDO_O_c => A0_ADC_SDO_O_c, 
        A0_ADC_CS_O_c => A0_ADC_CS_O_c, A0_ADC_SCK_O_c => 
        A0_ADC_SCK_O_c, prdata_o276 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o276\, 
        G_15_1 => G_15_1, N_730 => \BLDC_HALL_Axis_0.N_730\, 
        N_748 => \BLDC_HALL_Axis_0.N_748\, 
        prdata_o_1_iv_0_0_a3_27_out => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_a3_27_out\, 
        prdata_o_1_iv_0_0_a3_9_out => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_a3_9_out\, 
        N_737 => \BLDC_HALL_Axis_0.N_737\, N_759 => 
        \BLDC_HALL_Axis_0.N_759\, N_705 => 
        \BLDC_HALL_Axis_0.N_705\, prdata_o_1_iv_0_0_a3_0_out => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_0_a3_0_out\, 
        N_734 => \BLDC_HALL_Axis_0.N_734\, N_745 => 
        \BLDC_HALL_Axis_0.N_745\, prdata_m1_e_8_1 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m1_e_8_1\, 
        prdata_m1_e_4_1 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m1_e_4_1\, 
        prdata_m1_e_12_1 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m1_e_12_1\, 
        MC_System_0_AMBA_SLAVE_0_PWRITE => 
        MC_System_0_AMBA_SLAVE_0_PWRITE, 
        MC_System_0_AMBA_SLAVE_0_PENABLE => 
        MC_System_0_AMBA_SLAVE_0_PENABLE, prdata_N_5_mux_6 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_6\, 
        prdata_N_5_mux_7 => 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_7\, 
        MC_System_0_AMBA_SLAVE_0_PSELx => 
        MC_System_0_AMBA_SLAVE_0_PSELx, N_358 => 
        \BLDC_HALL_Axis_0.N_358\, N_634 => 
        \BLDC_HALL_Axis_0.N_634\, N_462 => 
        \BLDC_HALL_Axis_0.N_462\, N_449 => 
        \BLDC_HALL_Axis_0.N_449\, N_442 => 
        \BLDC_HALL_Axis_0.N_442\, N_440 => 
        \BLDC_HALL_Axis_0.N_440\);
    
    HA_i_ibuf : INBUF
      generic map(IOSTD => "")

      port map(PAD => HA_i, Y => HA_i_c);
    
    A0_ADC_SCK_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A0_ADC_SCK_O_c, PAD => A0_ADC_SCK_O);
    
    A0_PWM_WH_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A0_PWM_WH_O_c, PAD => A0_PWM_WH_O);
    
    A0_PWM_VL_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A0_PWM_VL_O_c, PAD => A0_PWM_VL_O);
    
    A0_PWM_UL_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A0_PWM_VL_O_c, PAD => A0_PWM_UL_O);
    
    A0_ADC_SDO_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A0_ADC_SDO_O_c, PAD => A0_ADC_SDO_O);
    
    GPIO_0_M2F_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => GPIO_0_M2F_c, PAD => GPIO_0_M2F);
    
    A0_ADC_CS_O_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A0_ADC_CS_O_c, PAD => A0_ADC_CS_O);
    
    HC_i_ibuf : INBUF
      generic map(IOSTD => "")

      port map(PAD => HC_i, Y => HC_i_c);
    
    A0_RUNNING_LED_obuf : OUTBUF
      generic map(IOSTD => "")

      port map(D => A0_PWM_VL_O_c, PAD => A0_RUNNING_LED);
    
    A0_ADC_SDI_I_ibuf : INBUF
      generic map(IOSTD => "")

      port map(PAD => A0_ADC_SDI_I, Y => A0_ADC_SDI_I_c);
    

end DEF_ARCH; 
