# Microsemi Physical design constraints file

# Version: v11.5 11.5.0.26

# Design Name:  

# Input Netlist Format: EDIF 

# Family: SmartFusion2 , Die: M2S010 , Package: 484 FBGA , Speed grade: -1 

# Date generated: Tue Mar 10 11:25:16 2015 


#
# IO banks setting
#

set_iobank Bank2 -vcci 2.50 -fixed no

#
# Local clock constraints
#


#
# Region constraints
#


#
# I/O constraints
#

set_io USB_ULPI_DATA\[0\] -DIRECTION INOUT -pinname V22 -fixed yes
set_io USB_ULPI_DATA\[1\] -DIRECTION INOUT -pinname V21 -fixed yes
set_io USB_ULPI_DATA\[2\] -DIRECTION INOUT -pinname U22 -fixed yes
set_io USB_ULPI_DATA\[3\] -DIRECTION INOUT -pinname U21 -fixed yes
set_io USB_ULPI_DATA\[4\] -DIRECTION INOUT -pinname T20 -fixed yes
set_io USB_ULPI_DATA\[5\] -DIRECTION INOUT -pinname T21 -fixed yes
set_io USB_ULPI_DATA\[6\] -DIRECTION INOUT -pinname P17 -fixed yes
set_io USB_ULPI_DATA\[7\] -DIRECTION INOUT -pinname V19 -fixed yes
set_io USB_ULPI_DIR -DIRECTION INPUT -pinname R18 -fixed yes
set_io USB_ULPI_NXT -DIRECTION INPUT -pinname T19 -fixed yes
set_io USB_ULPI_STP -DIRECTION OUTPUT -pinname T18 -fixed yes
set_io USB_ULPI_XCLK -DIRECTION INPUT -pinname R17 -fixed yes

#
# Core cell constraints
#

