<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<title>Timing Report Min Delay Analysis
</title>
<text>SmartTime Version 11.8.2.4</text>
<text>Microsemi Corporation - Microsemi Libero Software Release Libero SoC v11.8 SP2 (Version 11.8.2.4)</text>
<text>Date: Wed Nov 29 13:51:40 2017
</text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>MC_System_top</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2S010</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>0 - 85 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Design State</cell>
 <cell>Post-Layout</cell>
</row>
<row>
 <cell>Data source</cell>
 <cell>Production</cell>
</row>
<row>
 <cell>Min Operating Conditions</cell>
 <cell>BEST - 1.26 V - 0 C</cell>
</row>
<row>
 <cell>Max Operating Conditions</cell>
 <cell>WORST - 1.14 V - 85 C</cell>
</row>
<row>
 <cell>Scenario for Timing Analysis</cell>
 <cell>Primary</cell>
</row>
</table>
<text></text>
<section>
<name>Summary</name>
<table>
<header>
 <cell>Clock Domain</cell>
 <cell>Period (ns)</cell>
 <cell>Frequency (MHz)</cell>
 <cell>Required Period (ns)</cell>
 <cell>Required Frequency (MHz)</cell>
 <cell>External Setup (ns)</cell>
 <cell>External Hold (ns)</cell>
 <cell>Min Clock-To-Out (ns)</cell>
 <cell>Max Clock-To-Out (ns)</cell>
</header>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>7.843</cell>
 <cell>127.502</cell>
 <cell>10.000</cell>
 <cell>100.000</cell>
 <cell>3.953</cell>
 <cell>1.834</cell>
 <cell>4.472</cell>
 <cell>11.842</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>10.000</cell>
 <cell>100.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
<text></text>
<table>
<header>
 <cell></cell>
 <cell>Min Delay (ns)</cell>
 <cell>Max Delay (ns)</cell>
</header>
<row>
 <cell>Input to Output</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
</section>
<section>
<name>Clock Domain MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>BLDC_HALL_Axis_0/MSC_i_15/s_count_output[8]:CLK</cell>
 <cell>BLDC_HALL_Axis_0/MSC_i_15/s_hall_count_buff[8]:D</cell>
 <cell>0.316</cell>
 <cell>0.297</cell>
 <cell>3.109</cell>
 <cell>2.812</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>BLDC_HALL_Axis_0/MSC_i_15/s_count_output[17]:CLK</cell>
 <cell>BLDC_HALL_Axis_0/MSC_i_15/s_hall_count_buff[17]:D</cell>
 <cell>0.316</cell>
 <cell>0.298</cell>
 <cell>3.122</cell>
 <cell>2.824</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>BLDC_HALL_Axis_0/MSC_i_21/MSC_i_22/MSC_i_23/s_mas_done_dly[0]:CLK</cell>
 <cell>BLDC_HALL_Axis_0/MSC_i_21/MSC_i_22/MSC_i_23/mas_done_o_Z:D</cell>
 <cell>0.319</cell>
 <cell>0.301</cell>
 <cell>3.114</cell>
 <cell>2.813</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>BLDC_HALL_Axis_0/apb3_hall_if_0/olmng_theta_factor_o[10]:CLK</cell>
 <cell>BLDC_HALL_Axis_0/MSC_i_12/s_mult1_input[10]:D</cell>
 <cell>0.313</cell>
 <cell>0.302</cell>
 <cell>3.112</cell>
 <cell>2.810</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>BLDC_HALL_Axis_0/MSC_i_1/MSC_i_5/MSC_i_6/x_o[14]:CLK</cell>
 <cell>BLDC_HALL_Axis_0/MSC_i_1/MSC_i_5/xo_ipark_o[14]:D</cell>
 <cell>0.321</cell>
 <cell>0.302</cell>
 <cell>3.123</cell>
 <cell>2.821</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: BLDC_HALL_Axis_0/MSC_i_15/s_count_output[8]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: BLDC_HALL_Axis_0/MSC_i_15/s_hall_count_buff[8]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.109</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>2.812</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.297</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.866</cell>
 <cell>1.866</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.132</cell>
 <cell>1.998</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.110</cell>
 <cell>2.108</cell>
 <cell>13</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB24:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>2.299</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB24:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.168</cell>
 <cell>2.467</cell>
 <cell>28</cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_HALL_Axis_0/MSC_i_15/s_count_output[8]:CLK</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB24_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.326</cell>
 <cell>2.793</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_HALL_Axis_0/MSC_i_15/s_count_output[8]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.058</cell>
 <cell>2.851</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_HALL_Axis_0/MSC_i_15/s_hall_count_buff[8]:D</cell>
 <cell>net</cell>
 <cell>BLDC_HALL_Axis_0/MSC_i_15/MSC_net_271</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.258</cell>
 <cell>3.109</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.109</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.866</cell>
 <cell>1.866</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.132</cell>
 <cell>1.998</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.110</cell>
 <cell>2.108</cell>
 <cell>13</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB24:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>2.299</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB24:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.168</cell>
 <cell>2.467</cell>
 <cell>28</cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_HALL_Axis_0/MSC_i_15/s_hall_count_buff[8]:CLK</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB24_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.345</cell>
 <cell>2.812</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_HALL_Axis_0/MSC_i_15/s_hall_count_buff[8]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.812</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.812</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
 <cell>External Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>A0_ADC_SDI_I</cell>
 <cell>BLDC_HALL_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D</cell>
 <cell>1.048</cell>
 <cell>1.332</cell>
 <cell>4.214</cell>
 <cell>2.882</cell>
 <cell>-0.018</cell>
 <cell>1.834</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>HA_i</cell>
 <cell>BLDC_HALL_Axis_0/MSC_i_15/s_ha_dly:D</cell>
 <cell>1.867</cell>
 <cell>2.146</cell>
 <cell>5.033</cell>
 <cell>2.887</cell>
 <cell>0.000</cell>
 <cell>1.020</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>HC_i</cell>
 <cell>BLDC_HALL_Axis_0/MSC_i_15/s_hc_dly:D</cell>
 <cell>2.248</cell>
 <cell>2.518</cell>
 <cell>5.414</cell>
 <cell>2.896</cell>
 <cell>0.000</cell>
 <cell>0.648</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>HB_i</cell>
 <cell>BLDC_HALL_Axis_0/MSC_i_15/s_hb_dly:D</cell>
 <cell>2.261</cell>
 <cell>2.532</cell>
 <cell>5.427</cell>
 <cell>2.895</cell>
 <cell>0.000</cell>
 <cell>0.634</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>HA_i</cell>
 <cell>BLDC_HALL_Axis_0/MSC_i_15/s_theta_output[1]:D</cell>
 <cell>2.424</cell>
 <cell>2.691</cell>
 <cell>5.590</cell>
 <cell>2.899</cell>
 <cell>0.000</cell>
 <cell>0.475</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: A0_ADC_SDI_I</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: BLDC_HALL_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.214</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>2.882</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.332</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.866</cell>
 <cell>1.866</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>A0_ADC_SDI_I</cell>
 <cell>Input Delay Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.300</cell>
 <cell>3.166</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>A0_ADC_SDI_I_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>A0_ADC_SDI_I</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.166</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>A0_ADC_SDI_I_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>0.796</cell>
 <cell>3.962</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_HALL_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D</cell>
 <cell>net</cell>
 <cell>A0_ADC_SDI_I_ibuf/U0/YIN1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.252</cell>
 <cell>4.214</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.214</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.923</cell>
 <cell>1.923</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.137</cell>
 <cell>2.060</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.114</cell>
 <cell>2.174</cell>
 <cell>13</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB19:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.195</cell>
 <cell>2.369</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB19:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.173</cell>
 <cell>2.542</cell>
 <cell>26</cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_HALL_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:CLK</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB19_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.358</cell>
 <cell>2.900</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_HALL_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:IOINFF</cell>
 <cell>+</cell>
 <cell>-0.018</cell>
 <cell>2.882</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.882</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>BLDC_HALL_Axis_0/MSC_i_27/PWM_CH_o_Z:CLK</cell>
 <cell>A0_PWM_WH_O</cell>
 <cell>1.661</cell>
 <cell>2.906</cell>
 <cell>4.472</cell>
 <cell>1.566</cell>
 <cell>4.472</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>BLDC_HALL_Axis_0/MSC_i_27/PWM_BH_o_Z:CLK</cell>
 <cell>A0_PWM_VH_O</cell>
 <cell>1.688</cell>
 <cell>2.933</cell>
 <cell>4.499</cell>
 <cell>1.566</cell>
 <cell>4.499</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>BLDC_HALL_Axis_0/MSC_i_27/PWM_AH_o_Z:CLK</cell>
 <cell>A0_PWM_UH_O</cell>
 <cell>1.725</cell>
 <cell>2.971</cell>
 <cell>4.537</cell>
 <cell>1.566</cell>
 <cell>4.537</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>BLDC_HALL_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdo:CLK</cell>
 <cell>A0_ADC_SDO_O</cell>
 <cell>1.970</cell>
 <cell>3.217</cell>
 <cell>4.783</cell>
 <cell>1.566</cell>
 <cell>4.783</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>BLDC_HALL_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sck:CLK</cell>
 <cell>A0_ADC_SCK_O</cell>
 <cell>3.108</cell>
 <cell>4.325</cell>
 <cell>5.891</cell>
 <cell>1.566</cell>
 <cell>5.891</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: BLDC_HALL_Axis_0/MSC_i_27/PWM_CH_o_Z:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: A0_PWM_WH_O</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.472</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>1.566</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.906</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.866</cell>
 <cell>1.866</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.132</cell>
 <cell>1.998</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.110</cell>
 <cell>2.108</cell>
 <cell>13</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB5:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.186</cell>
 <cell>2.294</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB5:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.168</cell>
 <cell>2.462</cell>
 <cell>89</cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_HALL_Axis_0/MSC_i_27/PWM_CH_o_Z:CLK</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB5_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.349</cell>
 <cell>2.811</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_HALL_Axis_0/MSC_i_27/PWM_CH_o_Z:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOOEFF</cell>
 <cell>+</cell>
 <cell>0.127</cell>
 <cell>2.938</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>A0_PWM_WH_O_obuf/U0/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>A0_PWM_WH_O_obuf/U0/DOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.071</cell>
 <cell>3.009</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>A0_PWM_WH_O_obuf/U0/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>1.463</cell>
 <cell>4.472</cell>
 <cell>0</cell>
 <cell>r</cell>
</row>
<row>
 <cell>A0_PWM_WH_O</cell>
 <cell>net</cell>
 <cell>A0_PWM_WH_O</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>4.472</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.472</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.866</cell>
 <cell>1.866</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>A0_PWM_WH_O</cell>
 <cell>Output Delay Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell>0.300</cell>
 <cell>1.566</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.566</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain MC_System_0/MC_System_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1</name>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set Pin to Pin</name>
<section>
<name>SET Input to Output</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set User Sets</name>
</section>
</doc>
