@W: BN132 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Removing sequential instance MC_System_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int,  because it is equivalent to instance MC_System_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int
@W: MT530 :"d:\svn solutions\motor control\development\mcsk\sk2ablstsl10_4_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":781:8:781:9|Found inferred clock MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock which controls 3 sequential elements including MC_System_sb_0.CORERESETP_0.sm1_areset_n_clk_base. This clock has no specified timing constraint which may adversely impact design performance. 
