Project Status Summary Page

Project Settings
Project Name | MC_System_top_syn | Implementation Name | synthesis
Top Module | work.MC_System_top | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 10000
Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0

Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 118 | 71 | 0 | - | 00m:04s | - | 29-11-2017 13:44:48
(premap) | Complete | 90 | 17 | 0 | 0m:01s | 0m:01s | 167MB | 29-11-2017 13:44:52
(fpga_mapper) | Complete | 10 | 26 | 0 | 0m:16s | 0m:16s | 243MB | 29-11-2017 13:45:09
Multi-srs Generator | Complete |  |  |  | 00m:01s |  |  | 29-11-2017 13:44:50

Area Summary
Carry Cells | 1524 | Sequential Cells | 2276
DSP Blocks (MACC) (dsp_used) | 7 | I/O Cells | 27
Global Clock Buffers | 2 | LUTs (total_luts) | 3456

Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
GL0 | 100.0 MHz | 106.8 MHz | 0.637
System | 100.0 MHz | 1029.4 MHz | 9.029

Optimizations Summary
Combined Clock Conversion | 1 / 0 |  |