

##### START OF TIMING REPORT #####[
# Timing Report written on Wed Oct 08 11:16:18 2014
#


Top view:               SQMNG
Requested Frequency:    50.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    C:\SK1ASTSL10_3_0_multi_axis\synthesis\MC_System_top_sdc.sdc
                       
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: 0.315

                                                     Requested     Estimated     Requested     Estimated               Clock        Clock              
Starting Clock                                       Frequency     Frequency     Period        Period        Slack     Type         Group              
-------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0/CCC_0/CCC_INST/INST_CCC_IP:GL0           50.0 MHz      NA            20.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock          100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1        100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_0      100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_1      100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_2      100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_3      100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_4      100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_5      100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_6      100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_7      100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_8      100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_9      100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_10     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_11     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_12     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_13     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_14     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_15     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_16     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_17     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_18     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_19     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_20     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_21     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_22     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_23     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_24     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_25     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_26     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_27     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_28     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_29     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_30     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_31     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_32     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_33     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_34     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_35     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_36     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_37     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_38     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_39     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_40     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_41     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_42     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_43     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_44     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_45     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_46     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_47     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_48     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_49     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_50     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_51     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_52     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_53     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_54     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_55     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_56     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_57     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_58     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_59     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_60     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_61     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_62     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_63     100.0 MHz     NA            10.000        NA            NA        declared     group_55_166       
MC_System_CCC_0_FCCC|GL1_net_inferred_clock          100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1        100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_0      100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_1      100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_2      100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_3      100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_4      100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_5      100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_6      100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_7      100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_8      100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_9      100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_10     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_11     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_12     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_13     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_14     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_15     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_16     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_17     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_18     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_19     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_20     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_21     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_22     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_23     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_24     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_25     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_26     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_27     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_28     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_29     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_30     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_31     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_32     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_33     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_34     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_35     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_36     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_37     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_38     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_39     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_40     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_41     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_42     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_43     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_44     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_45     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_46     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_47     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_48     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_49     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_50     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_51     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_52     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_53     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_54     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_55     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_56     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_57     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_58     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_59     100.0 MHz     NA            10.000        NA            NA        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_60     100.0 MHz     NA            10.000        NA            NA        declared     group_55_165       
SQMNG|sys_clk_i                                      100.0 MHz     337.0 MHz     10.000        2.967         7.033     inferred     Inferred_clkgroup_0
=======================================================================================================================================================
@W: MT548 :"c:/sk1astsl10_3_0_multi_axis/synthesis/mc_system_top_sdc.sdc":5:0:5:0|Source for clock MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_60 not found in netlist
@W: MT548 :"c:/sk1astsl10_3_0_multi_axis/synthesis/mc_system_top_sdc.sdc":6:0:6:0|Source for clock MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_63 not found in netlist



Clock Relationships
*******************

Clocks                            |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------
Starting         Ending           |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------
SQMNG|sys_clk_i  SQMNG|sys_clk_i  |  0.000       0.315  |  No paths    -      |  No paths    -      |  No paths    -    
========================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: SQMNG|sys_clk_i
====================================



Starting Points with Worst Slack
********************************

                       Starting                                                    Arrival          
Instance               Reference           Type     Pin     Net                    Time        Slack
                       Clock                                                                        
----------------------------------------------------------------------------------------------------
theta_scale_val[0]     SQMNG|sys_clk_i     SLE      Q       theta_scale_val[0]     0.053       0.494
theta_scale_val[1]     SQMNG|sys_clk_i     SLE      Q       theta_scale_val[1]     0.053       0.494
theta_scale_val[2]     SQMNG|sys_clk_i     SLE      Q       theta_scale_val[2]     0.053       0.494
theta_scale_val[3]     SQMNG|sys_clk_i     SLE      Q       theta_scale_val[3]     0.053       0.494
theta_scale_val[4]     SQMNG|sys_clk_i     SLE      Q       theta_scale_val[4]     0.053       0.494
theta_scale_val[5]     SQMNG|sys_clk_i     SLE      Q       theta_scale_val[5]     0.053       0.494
theta_scale_val[6]     SQMNG|sys_clk_i     SLE      Q       theta_scale_val[6]     0.053       0.494
theta_scale_val[7]     SQMNG|sys_clk_i     SLE      Q       theta_scale_val[7]     0.053       0.494
theta_scale_val[8]     SQMNG|sys_clk_i     SLE      Q       theta_scale_val[8]     0.053       0.494
theta_scale_val[9]     SQMNG|sys_clk_i     SLE      Q       theta_scale_val[9]     0.053       0.494
====================================================================================================


Ending Points with Worst Slack
******************************

                             Starting                                                    Required          
Instance                     Reference           Type     Pin     Net                    Time         Slack
                             Clock                                                                         
-----------------------------------------------------------------------------------------------------------
theta_scale_val_limit[0]     SQMNG|sys_clk_i     SLE      D       theta_scale_val[0]     0.155        0.315
theta_scale_val_limit[1]     SQMNG|sys_clk_i     SLE      D       theta_scale_val[1]     0.155        0.315
theta_scale_val_limit[2]     SQMNG|sys_clk_i     SLE      D       theta_scale_val[2]     0.155        0.315
theta_scale_val_limit[3]     SQMNG|sys_clk_i     SLE      D       theta_scale_val[3]     0.155        0.315
theta_scale_val_limit[4]     SQMNG|sys_clk_i     SLE      D       theta_scale_val[4]     0.155        0.315
theta_scale_val_limit[5]     SQMNG|sys_clk_i     SLE      D       theta_scale_val[5]     0.155        0.315
theta_scale_val_limit[6]     SQMNG|sys_clk_i     SLE      D       theta_scale_val[6]     0.155        0.315
theta_scale_val_limit[7]     SQMNG|sys_clk_i     SLE      D       theta_scale_val[7]     0.155        0.315
theta_scale_val_limit[8]     SQMNG|sys_clk_i     SLE      D       theta_scale_val[8]     0.155        0.315
theta_scale_val_limit[9]     SQMNG|sys_clk_i     SLE      D       theta_scale_val[9]     0.155        0.315
===========================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Propagation time:                        0.470
    + Clock delay at starting point:         0.000 (ideal)
    - Requested Period:                      0.000
    - Hold time:                             0.155
    - Clock delay at ending point:           0.000 (ideal)
    = Slack (critical) :                     0.315

    Number of logic level(s):                0
    Starting point:                          theta_scale_val[0] / Q
    Ending point:                            theta_scale_val_limit[0] / D
    The start point is clocked by            SQMNG|sys_clk_i [rising] on pin CLK
    The end   point is clocked by            SQMNG|sys_clk_i [rising] on pin CLK

Instance / Net                        Pin      Pin               Arrival     No. of    
Name                         Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
theta_scale_val[0]           SLE      Q        Out     0.053     0.053       -         
theta_scale_val[0]           Net      -        -       0.417     -           1         
theta_scale_val_limit[0]     SLE      D        In      -         0.470       -         
=======================================================================================



##### END OF TIMING REPORT #####]

