--=================================================================================================
-- File Name                           : pwm_scaling.vhd

-- Description                         : This module scales the input signals to fit within the
--                                       range of pwm generation module. It also adds offset to
--                                       remove negative component in the input

-- Targeted device                     : Microsemi-SoC
-- Author                              : India Solutions Team
--
-- SVN Revision Information            :
-- SVN $Revision                       :
-- SVN $Date                           :
--
-- COPYRIGHT 2016 BY MICROSEMI
-- THE INFORMATION CONTAINED IN THIS DOCUMENT IS SUBJECT TO LICENSING RESTRICTIONS FROM MICROSEMI
-- CORP. IF YOU ARE NOT IN POSSESSION OF WRITTEN AUTHORIZATION FROM MICROSEMI FOR USE OF THIS
-- FILE, THEN THE FILE SHOULD BE IMMEDIATELY DESTROYED AND NO BACK-UP OF THE FILE SHOULD BE MADE.
--
--=================================================================================================

--=================================================================================================
-- Libraries
--=================================================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;

--=================================================================================================
-- pwm_scaling entity declaration
--=================================================================================================
ENTITY PWM_SCALING IS
GENERIC(
-- Generic List

	-- Specifies number of clock cycles before math block asserts done
	g_NO_MCYCLE_PATH				   : INTEGER RANGE 0 TO 4 :=  2

);
PORT (
-- Port List
    -- System reset
    reset_i                            : IN STD_LOGIC;

    -- System clock
    sys_clk_i                          : IN STD_LOGIC;

	-- System clock
    start_i                            : IN STD_LOGIC;

    -- Va input 
    va_i              	   		   	   : IN  STD_LOGIC_VECTOR (17 downto 0);

    -- Vb input 
    vb_i                	   		   : IN  STD_LOGIC_VECTOR (17 downto 0);

	-- Vc input 
    vc_i                	   		   : IN  STD_LOGIC_VECTOR (17 downto 0);

	-- PWM period
    pwm_period_i               	   	   : IN  STD_LOGIC_VECTOR (17 downto 0);

	-- PWM gain
    pwm_gain_i                	   	   : IN  STD_LOGIC_VECTOR (17 downto 0);

    -- Scaled Va output
    Va_o           	   		   		   : OUT  STD_LOGIC_VECTOR (17 downto 0);

    -- Scaled Vb output
    Vb_o             	   		       : OUT  STD_LOGIC_VECTOR (17 downto 0);

    -- Scaled Vc output
    Vc_o           	   		   	       : OUT  STD_LOGIC_VECTOR (17 downto 0);

	-- Done signal 
    done_o                             : OUT STD_LOGIC

);
END pwm_scaling;
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