`timescale 1 ns/100 ps
// Version: v11.7 SP1 11.7.1.14


module RCOSC_25_50MHZ(
       CLKOUT
    );
output CLKOUT;

    parameter FREQUENCY = 50.0 ;
    
endmodule


module MSS_010(
       CAN_RXBUS_MGPIO3A_H2F_A,
       CAN_RXBUS_MGPIO3A_H2F_B,
       CAN_TX_EBL_MGPIO4A_H2F_A,
       CAN_TX_EBL_MGPIO4A_H2F_B,
       CAN_TXBUS_MGPIO2A_H2F_A,
       CAN_TXBUS_MGPIO2A_H2F_B,
       CLK_CONFIG_APB,
       COMMS_INT,
       CONFIG_PRESET_N,
       EDAC_ERROR,
       F_FM0_RDATA,
       F_FM0_READYOUT,
       F_FM0_RESP,
       F_HM0_ADDR,
       F_HM0_ENABLE,
       F_HM0_SEL,
       F_HM0_SIZE,
       F_HM0_TRANS1,
       F_HM0_WDATA,
       F_HM0_WRITE,
       FAB_CHRGVBUS,
       FAB_DISCHRGVBUS,
       FAB_DMPULLDOWN,
       FAB_DPPULLDOWN,
       FAB_DRVVBUS,
       FAB_IDPULLUP,
       FAB_OPMODE,
       FAB_SUSPENDM,
       FAB_TERMSEL,
       FAB_TXVALID,
       FAB_VCONTROL,
       FAB_VCONTROLLOADM,
       FAB_XCVRSEL,
       FAB_XDATAOUT,
       FACC_GLMUX_SEL,
       FIC32_0_MASTER,
       FIC32_1_MASTER,
       FPGA_RESET_N,
       GTX_CLK,
       H2F_INTERRUPT,
       H2F_NMI,
       H2FCALIB,
       I2C0_SCL_MGPIO31B_H2F_A,
       I2C0_SCL_MGPIO31B_H2F_B,
       I2C0_SDA_MGPIO30B_H2F_A,
       I2C0_SDA_MGPIO30B_H2F_B,
       I2C1_SCL_MGPIO1A_H2F_A,
       I2C1_SCL_MGPIO1A_H2F_B,
       I2C1_SDA_MGPIO0A_H2F_A,
       I2C1_SDA_MGPIO0A_H2F_B,
       MDCF,
       MDOENF,
       MDOF,
       MMUART0_CTS_MGPIO19B_H2F_A,
       MMUART0_CTS_MGPIO19B_H2F_B,
       MMUART0_DCD_MGPIO22B_H2F_A,
       MMUART0_DCD_MGPIO22B_H2F_B,
       MMUART0_DSR_MGPIO20B_H2F_A,
       MMUART0_DSR_MGPIO20B_H2F_B,
       MMUART0_DTR_MGPIO18B_H2F_A,
       MMUART0_DTR_MGPIO18B_H2F_B,
       MMUART0_RI_MGPIO21B_H2F_A,
       MMUART0_RI_MGPIO21B_H2F_B,
       MMUART0_RTS_MGPIO17B_H2F_A,
       MMUART0_RTS_MGPIO17B_H2F_B,
       MMUART0_RXD_MGPIO28B_H2F_A,
       MMUART0_RXD_MGPIO28B_H2F_B,
       MMUART0_SCK_MGPIO29B_H2F_A,
       MMUART0_SCK_MGPIO29B_H2F_B,
       MMUART0_TXD_MGPIO27B_H2F_A,
       MMUART0_TXD_MGPIO27B_H2F_B,
       MMUART1_DTR_MGPIO12B_H2F_A,
       MMUART1_RTS_MGPIO11B_H2F_A,
       MMUART1_RTS_MGPIO11B_H2F_B,
       MMUART1_RXD_MGPIO26B_H2F_A,
       MMUART1_RXD_MGPIO26B_H2F_B,
       MMUART1_SCK_MGPIO25B_H2F_A,
       MMUART1_SCK_MGPIO25B_H2F_B,
       MMUART1_TXD_MGPIO24B_H2F_A,
       MMUART1_TXD_MGPIO24B_H2F_B,
       MPLL_LOCK,
       PER2_FABRIC_PADDR,
       PER2_FABRIC_PENABLE,
       PER2_FABRIC_PSEL,
       PER2_FABRIC_PWDATA,
       PER2_FABRIC_PWRITE,
       RTC_MATCH,
       SLEEPDEEP,
       SLEEPHOLDACK,
       SLEEPING,
       SMBALERT_NO0,
       SMBALERT_NO1,
       SMBSUS_NO0,
       SMBSUS_NO1,
       SPI0_CLK_OUT,
       SPI0_SDI_MGPIO5A_H2F_A,
       SPI0_SDI_MGPIO5A_H2F_B,
       SPI0_SDO_MGPIO6A_H2F_A,
       SPI0_SDO_MGPIO6A_H2F_B,
       SPI0_SS0_MGPIO7A_H2F_A,
       SPI0_SS0_MGPIO7A_H2F_B,
       SPI0_SS1_MGPIO8A_H2F_A,
       SPI0_SS1_MGPIO8A_H2F_B,
       SPI0_SS2_MGPIO9A_H2F_A,
       SPI0_SS2_MGPIO9A_H2F_B,
       SPI0_SS3_MGPIO10A_H2F_A,
       SPI0_SS3_MGPIO10A_H2F_B,
       SPI0_SS4_MGPIO19A_H2F_A,
       SPI0_SS5_MGPIO20A_H2F_A,
       SPI0_SS6_MGPIO21A_H2F_A,
       SPI0_SS7_MGPIO22A_H2F_A,
       SPI1_CLK_OUT,
       SPI1_SDI_MGPIO11A_H2F_A,
       SPI1_SDI_MGPIO11A_H2F_B,
       SPI1_SDO_MGPIO12A_H2F_A,
       SPI1_SDO_MGPIO12A_H2F_B,
       SPI1_SS0_MGPIO13A_H2F_A,
       SPI1_SS0_MGPIO13A_H2F_B,
       SPI1_SS1_MGPIO14A_H2F_A,
       SPI1_SS1_MGPIO14A_H2F_B,
       SPI1_SS2_MGPIO15A_H2F_A,
       SPI1_SS2_MGPIO15A_H2F_B,
       SPI1_SS3_MGPIO16A_H2F_A,
       SPI1_SS3_MGPIO16A_H2F_B,
       SPI1_SS4_MGPIO17A_H2F_A,
       SPI1_SS5_MGPIO18A_H2F_A,
       SPI1_SS6_MGPIO23A_H2F_A,
       SPI1_SS7_MGPIO24A_H2F_A,
       TCGF,
       TRACECLK,
       TRACEDATA,
       TX_CLK,
       TX_ENF,
       TX_ERRF,
       TXCTL_EN_RIF,
       TXD_RIF,
       TXDF,
       TXEV,
       WDOGTIMEOUT,
       F_ARREADY_HREADYOUT1,
       F_AWREADY_HREADYOUT0,
       F_BID,
       F_BRESP_HRESP0,
       F_BVALID,
       F_RDATA_HRDATA01,
       F_RID,
       F_RLAST,
       F_RRESP_HRESP1,
       F_RVALID,
       F_WREADY,
       MDDR_FABRIC_PRDATA,
       MDDR_FABRIC_PREADY,
       MDDR_FABRIC_PSLVERR,
       CAN_RXBUS_F2H_SCP,
       CAN_TX_EBL_F2H_SCP,
       CAN_TXBUS_F2H_SCP,
       COLF,
       CRSF,
       F2_DMAREADY,
       F2H_INTERRUPT,
       F2HCALIB,
       F_DMAREADY,
       F_FM0_ADDR,
       F_FM0_ENABLE,
       F_FM0_MASTLOCK,
       F_FM0_READY,
       F_FM0_SEL,
       F_FM0_SIZE,
       F_FM0_TRANS1,
       F_FM0_WDATA,
       F_FM0_WRITE,
       F_HM0_RDATA,
       F_HM0_READY,
       F_HM0_RESP,
       FAB_AVALID,
       FAB_HOSTDISCON,
       FAB_IDDIG,
       FAB_LINESTATE,
       FAB_M3_RESET_N,
       FAB_PLL_LOCK,
       FAB_RXACTIVE,
       FAB_RXERROR,
       FAB_RXVALID,
       FAB_RXVALIDH,
       FAB_SESSEND,
       FAB_TXREADY,
       FAB_VBUSVALID,
       FAB_VSTATUS,
       FAB_XDATAIN,
       GTX_CLKPF,
       I2C0_BCLK,
       I2C0_SCL_F2H_SCP,
       I2C0_SDA_F2H_SCP,
       I2C1_BCLK,
       I2C1_SCL_F2H_SCP,
       I2C1_SDA_F2H_SCP,
       MDIF,
       MGPIO0A_F2H_GPIN,
       MGPIO10A_F2H_GPIN,
       MGPIO11A_F2H_GPIN,
       MGPIO11B_F2H_GPIN,
       MGPIO12A_F2H_GPIN,
       MGPIO13A_F2H_GPIN,
       MGPIO14A_F2H_GPIN,
       MGPIO15A_F2H_GPIN,
       MGPIO16A_F2H_GPIN,
       MGPIO17B_F2H_GPIN,
       MGPIO18B_F2H_GPIN,
       MGPIO19B_F2H_GPIN,
       MGPIO1A_F2H_GPIN,
       MGPIO20B_F2H_GPIN,
       MGPIO21B_F2H_GPIN,
       MGPIO22B_F2H_GPIN,
       MGPIO24B_F2H_GPIN,
       MGPIO25B_F2H_GPIN,
       MGPIO26B_F2H_GPIN,
       MGPIO27B_F2H_GPIN,
       MGPIO28B_F2H_GPIN,
       MGPIO29B_F2H_GPIN,
       MGPIO2A_F2H_GPIN,
       MGPIO30B_F2H_GPIN,
       MGPIO31B_F2H_GPIN,
       MGPIO3A_F2H_GPIN,
       MGPIO4A_F2H_GPIN,
       MGPIO5A_F2H_GPIN,
       MGPIO6A_F2H_GPIN,
       MGPIO7A_F2H_GPIN,
       MGPIO8A_F2H_GPIN,
       MGPIO9A_F2H_GPIN,
       MMUART0_CTS_F2H_SCP,
       MMUART0_DCD_F2H_SCP,
       MMUART0_DSR_F2H_SCP,
       MMUART0_DTR_F2H_SCP,
       MMUART0_RI_F2H_SCP,
       MMUART0_RTS_F2H_SCP,
       MMUART0_RXD_F2H_SCP,
       MMUART0_SCK_F2H_SCP,
       MMUART0_TXD_F2H_SCP,
       MMUART1_CTS_F2H_SCP,
       MMUART1_DCD_F2H_SCP,
       MMUART1_DSR_F2H_SCP,
       MMUART1_RI_F2H_SCP,
       MMUART1_RTS_F2H_SCP,
       MMUART1_RXD_F2H_SCP,
       MMUART1_SCK_F2H_SCP,
       MMUART1_TXD_F2H_SCP,
       PER2_FABRIC_PRDATA,
       PER2_FABRIC_PREADY,
       PER2_FABRIC_PSLVERR,
       RCGF,
       RX_CLKPF,
       RX_DVF,
       RX_ERRF,
       RX_EV,
       RXDF,
       SLEEPHOLDREQ,
       SMBALERT_NI0,
       SMBALERT_NI1,
       SMBSUS_NI0,
       SMBSUS_NI1,
       SPI0_CLK_IN,
       SPI0_SDI_F2H_SCP,
       SPI0_SDO_F2H_SCP,
       SPI0_SS0_F2H_SCP,
       SPI0_SS1_F2H_SCP,
       SPI0_SS2_F2H_SCP,
       SPI0_SS3_F2H_SCP,
       SPI1_CLK_IN,
       SPI1_SDI_F2H_SCP,
       SPI1_SDO_F2H_SCP,
       SPI1_SS0_F2H_SCP,
       SPI1_SS1_F2H_SCP,
       SPI1_SS2_F2H_SCP,
       SPI1_SS3_F2H_SCP,
       TX_CLKPF,
       USER_MSS_GPIO_RESET_N,
       USER_MSS_RESET_N,
       XCLK_FAB,
       CLK_BASE,
       CLK_MDDR_APB,
       F_ARADDR_HADDR1,
       F_ARBURST_HTRANS1,
       F_ARID_HSEL1,
       F_ARLEN_HBURST1,
       F_ARLOCK_HMASTLOCK1,
       F_ARSIZE_HSIZE1,
       F_ARVALID_HWRITE1,
       F_AWADDR_HADDR0,
       F_AWBURST_HTRANS0,
       F_AWID_HSEL0,
       F_AWLEN_HBURST0,
       F_AWLOCK_HMASTLOCK0,
       F_AWSIZE_HSIZE0,
       F_AWVALID_HWRITE0,
       F_BREADY,
       F_RMW_AXI,
       F_RREADY,
       F_WDATA_HWDATA01,
       F_WID_HREADY01,
       F_WLAST,
       F_WSTRB,
       F_WVALID,
       FPGA_MDDR_ARESET_N,
       MDDR_FABRIC_PADDR,
       MDDR_FABRIC_PENABLE,
       MDDR_FABRIC_PSEL,
       MDDR_FABRIC_PWDATA,
       MDDR_FABRIC_PWRITE,
       PRESET_N,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_IN,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_IN,
       DM_IN,
       DRAM_DQ_IN,
       DRAM_DQS_IN,
       DRAM_FIFO_WE_IN,
       I2C0_SCL_USBC_DATA1_MGPIO31B_IN,
       I2C0_SDA_USBC_DATA0_MGPIO30B_IN,
       I2C1_SCL_USBA_DATA4_MGPIO1A_IN,
       I2C1_SDA_USBA_DATA3_MGPIO0A_IN,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_IN,
       MMUART0_DCD_MGPIO22B_IN,
       MMUART0_DSR_MGPIO20B_IN,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_IN,
       MMUART0_RI_MGPIO21B_IN,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_IN,
       MMUART0_RXD_USBC_STP_MGPIO28B_IN,
       MMUART0_SCK_USBC_NXT_MGPIO29B_IN,
       MMUART0_TXD_USBC_DIR_MGPIO27B_IN,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_IN,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_IN,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_IN,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN,
       RGMII_MDC_RMII_MDC_IN,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN,
       RGMII_RX_CLK_IN,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN,
       RGMII_RXD3_USBB_DATA4_IN,
       RGMII_TX_CLK_IN,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_IN,
       RGMII_TXD1_RMII_TXD1_USBB_STP_IN,
       RGMII_TXD2_USBB_DATA5_IN,
       RGMII_TXD3_USBB_DATA6_IN,
       SPI0_SCK_USBA_XCLK_IN,
       SPI0_SDI_USBA_DIR_MGPIO5A_IN,
       SPI0_SDO_USBA_STP_MGPIO6A_IN,
       SPI0_SS0_USBA_NXT_MGPIO7A_IN,
       SPI0_SS1_USBA_DATA5_MGPIO8A_IN,
       SPI0_SS2_USBA_DATA6_MGPIO9A_IN,
       SPI0_SS3_USBA_DATA7_MGPIO10A_IN,
       SPI1_SCK_IN,
       SPI1_SDI_MGPIO11A_IN,
       SPI1_SDO_MGPIO12A_IN,
       SPI1_SS0_MGPIO13A_IN,
       SPI1_SS1_MGPIO14A_IN,
       SPI1_SS2_MGPIO15A_IN,
       SPI1_SS3_MGPIO16A_IN,
       SPI1_SS4_MGPIO17A_IN,
       SPI1_SS5_MGPIO18A_IN,
       SPI1_SS6_MGPIO23A_IN,
       SPI1_SS7_MGPIO24A_IN,
       USBC_XCLK_IN,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT,
       DRAM_ADDR,
       DRAM_BA,
       DRAM_CASN,
       DRAM_CKE,
       DRAM_CLK,
       DRAM_CSN,
       DRAM_DM_RDQS_OUT,
       DRAM_DQ_OUT,
       DRAM_DQS_OUT,
       DRAM_FIFO_WE_OUT,
       DRAM_ODT,
       DRAM_RASN,
       DRAM_RSTN,
       DRAM_WEN,
       I2C0_SCL_USBC_DATA1_MGPIO31B_OUT,
       I2C0_SDA_USBC_DATA0_MGPIO30B_OUT,
       I2C1_SCL_USBA_DATA4_MGPIO1A_OUT,
       I2C1_SDA_USBA_DATA3_MGPIO0A_OUT,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT,
       MMUART0_DCD_MGPIO22B_OUT,
       MMUART0_DSR_MGPIO20B_OUT,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT,
       MMUART0_RI_MGPIO21B_OUT,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT,
       MMUART0_RXD_USBC_STP_MGPIO28B_OUT,
       MMUART0_SCK_USBC_NXT_MGPIO29B_OUT,
       MMUART0_TXD_USBC_DIR_MGPIO27B_OUT,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT,
       RGMII_MDC_RMII_MDC_OUT,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT,
       RGMII_RX_CLK_OUT,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT,
       RGMII_RXD3_USBB_DATA4_OUT,
       RGMII_TX_CLK_OUT,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT,
       RGMII_TXD1_RMII_TXD1_USBB_STP_OUT,
       RGMII_TXD2_USBB_DATA5_OUT,
       RGMII_TXD3_USBB_DATA6_OUT,
       SPI0_SCK_USBA_XCLK_OUT,
       SPI0_SDI_USBA_DIR_MGPIO5A_OUT,
       SPI0_SDO_USBA_STP_MGPIO6A_OUT,
       SPI0_SS0_USBA_NXT_MGPIO7A_OUT,
       SPI0_SS1_USBA_DATA5_MGPIO8A_OUT,
       SPI0_SS2_USBA_DATA6_MGPIO9A_OUT,
       SPI0_SS3_USBA_DATA7_MGPIO10A_OUT,
       SPI1_SCK_OUT,
       SPI1_SDI_MGPIO11A_OUT,
       SPI1_SDO_MGPIO12A_OUT,
       SPI1_SS0_MGPIO13A_OUT,
       SPI1_SS1_MGPIO14A_OUT,
       SPI1_SS2_MGPIO15A_OUT,
       SPI1_SS3_MGPIO16A_OUT,
       SPI1_SS4_MGPIO17A_OUT,
       SPI1_SS5_MGPIO18A_OUT,
       SPI1_SS6_MGPIO23A_OUT,
       SPI1_SS7_MGPIO24A_OUT,
       USBC_XCLK_OUT,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_OE,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_OE,
       DM_OE,
       DRAM_DQ_OE,
       DRAM_DQS_OE,
       I2C0_SCL_USBC_DATA1_MGPIO31B_OE,
       I2C0_SDA_USBC_DATA0_MGPIO30B_OE,
       I2C1_SCL_USBA_DATA4_MGPIO1A_OE,
       I2C1_SDA_USBA_DATA3_MGPIO0A_OE,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_OE,
       MMUART0_DCD_MGPIO22B_OE,
       MMUART0_DSR_MGPIO20B_OE,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_OE,
       MMUART0_RI_MGPIO21B_OE,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_OE,
       MMUART0_RXD_USBC_STP_MGPIO28B_OE,
       MMUART0_SCK_USBC_NXT_MGPIO29B_OE,
       MMUART0_TXD_USBC_DIR_MGPIO27B_OE,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_OE,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_OE,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_OE,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE,
       RGMII_MDC_RMII_MDC_OE,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE,
       RGMII_RX_CLK_OE,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE,
       RGMII_RXD3_USBB_DATA4_OE,
       RGMII_TX_CLK_OE,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_OE,
       RGMII_TXD1_RMII_TXD1_USBB_STP_OE,
       RGMII_TXD2_USBB_DATA5_OE,
       RGMII_TXD3_USBB_DATA6_OE,
       SPI0_SCK_USBA_XCLK_OE,
       SPI0_SDI_USBA_DIR_MGPIO5A_OE,
       SPI0_SDO_USBA_STP_MGPIO6A_OE,
       SPI0_SS0_USBA_NXT_MGPIO7A_OE,
       SPI0_SS1_USBA_DATA5_MGPIO8A_OE,
       SPI0_SS2_USBA_DATA6_MGPIO9A_OE,
       SPI0_SS3_USBA_DATA7_MGPIO10A_OE,
       SPI1_SCK_OE,
       SPI1_SDI_MGPIO11A_OE,
       SPI1_SDO_MGPIO12A_OE,
       SPI1_SS0_MGPIO13A_OE,
       SPI1_SS1_MGPIO14A_OE,
       SPI1_SS2_MGPIO15A_OE,
       SPI1_SS3_MGPIO16A_OE,
       SPI1_SS4_MGPIO17A_OE,
       SPI1_SS5_MGPIO18A_OE,
       SPI1_SS6_MGPIO23A_OE,
       SPI1_SS7_MGPIO24A_OE,
       USBC_XCLK_OE
    );
output CAN_RXBUS_MGPIO3A_H2F_A;
output CAN_RXBUS_MGPIO3A_H2F_B;
output CAN_TX_EBL_MGPIO4A_H2F_A;
output CAN_TX_EBL_MGPIO4A_H2F_B;
output CAN_TXBUS_MGPIO2A_H2F_A;
output CAN_TXBUS_MGPIO2A_H2F_B;
output CLK_CONFIG_APB;
output COMMS_INT;
output CONFIG_PRESET_N;
output [7:0] EDAC_ERROR;
output [31:0] F_FM0_RDATA;
output F_FM0_READYOUT;
output F_FM0_RESP;
output [31:0] F_HM0_ADDR;
output F_HM0_ENABLE;
output F_HM0_SEL;
output [1:0] F_HM0_SIZE;
output F_HM0_TRANS1;
output [31:0] F_HM0_WDATA;
output F_HM0_WRITE;
output FAB_CHRGVBUS;
output FAB_DISCHRGVBUS;
output FAB_DMPULLDOWN;
output FAB_DPPULLDOWN;
output FAB_DRVVBUS;
output FAB_IDPULLUP;
output [1:0] FAB_OPMODE;
output FAB_SUSPENDM;
output FAB_TERMSEL;
output FAB_TXVALID;
output [3:0] FAB_VCONTROL;
output FAB_VCONTROLLOADM;
output [1:0] FAB_XCVRSEL;
output [7:0] FAB_XDATAOUT;
output FACC_GLMUX_SEL;
output [1:0] FIC32_0_MASTER;
output [1:0] FIC32_1_MASTER;
output FPGA_RESET_N;
output GTX_CLK;
output [15:0] H2F_INTERRUPT;
output H2F_NMI;
output H2FCALIB;
output I2C0_SCL_MGPIO31B_H2F_A;
output I2C0_SCL_MGPIO31B_H2F_B;
output I2C0_SDA_MGPIO30B_H2F_A;
output I2C0_SDA_MGPIO30B_H2F_B;
output I2C1_SCL_MGPIO1A_H2F_A;
output I2C1_SCL_MGPIO1A_H2F_B;
output I2C1_SDA_MGPIO0A_H2F_A;
output I2C1_SDA_MGPIO0A_H2F_B;
output MDCF;
output MDOENF;
output MDOF;
output MMUART0_CTS_MGPIO19B_H2F_A;
output MMUART0_CTS_MGPIO19B_H2F_B;
output MMUART0_DCD_MGPIO22B_H2F_A;
output MMUART0_DCD_MGPIO22B_H2F_B;
output MMUART0_DSR_MGPIO20B_H2F_A;
output MMUART0_DSR_MGPIO20B_H2F_B;
output MMUART0_DTR_MGPIO18B_H2F_A;
output MMUART0_DTR_MGPIO18B_H2F_B;
output MMUART0_RI_MGPIO21B_H2F_A;
output MMUART0_RI_MGPIO21B_H2F_B;
output MMUART0_RTS_MGPIO17B_H2F_A;
output MMUART0_RTS_MGPIO17B_H2F_B;
output MMUART0_RXD_MGPIO28B_H2F_A;
output MMUART0_RXD_MGPIO28B_H2F_B;
output MMUART0_SCK_MGPIO29B_H2F_A;
output MMUART0_SCK_MGPIO29B_H2F_B;
output MMUART0_TXD_MGPIO27B_H2F_A;
output MMUART0_TXD_MGPIO27B_H2F_B;
output MMUART1_DTR_MGPIO12B_H2F_A;
output MMUART1_RTS_MGPIO11B_H2F_A;
output MMUART1_RTS_MGPIO11B_H2F_B;
output MMUART1_RXD_MGPIO26B_H2F_A;
output MMUART1_RXD_MGPIO26B_H2F_B;
output MMUART1_SCK_MGPIO25B_H2F_A;
output MMUART1_SCK_MGPIO25B_H2F_B;
output MMUART1_TXD_MGPIO24B_H2F_A;
output MMUART1_TXD_MGPIO24B_H2F_B;
output MPLL_LOCK;
output [15:2] PER2_FABRIC_PADDR;
output PER2_FABRIC_PENABLE;
output PER2_FABRIC_PSEL;
output [31:0] PER2_FABRIC_PWDATA;
output PER2_FABRIC_PWRITE;
output RTC_MATCH;
output SLEEPDEEP;
output SLEEPHOLDACK;
output SLEEPING;
output SMBALERT_NO0;
output SMBALERT_NO1;
output SMBSUS_NO0;
output SMBSUS_NO1;
output SPI0_CLK_OUT;
output SPI0_SDI_MGPIO5A_H2F_A;
output SPI0_SDI_MGPIO5A_H2F_B;
output SPI0_SDO_MGPIO6A_H2F_A;
output SPI0_SDO_MGPIO6A_H2F_B;
output SPI0_SS0_MGPIO7A_H2F_A;
output SPI0_SS0_MGPIO7A_H2F_B;
output SPI0_SS1_MGPIO8A_H2F_A;
output SPI0_SS1_MGPIO8A_H2F_B;
output SPI0_SS2_MGPIO9A_H2F_A;
output SPI0_SS2_MGPIO9A_H2F_B;
output SPI0_SS3_MGPIO10A_H2F_A;
output SPI0_SS3_MGPIO10A_H2F_B;
output SPI0_SS4_MGPIO19A_H2F_A;
output SPI0_SS5_MGPIO20A_H2F_A;
output SPI0_SS6_MGPIO21A_H2F_A;
output SPI0_SS7_MGPIO22A_H2F_A;
output SPI1_CLK_OUT;
output SPI1_SDI_MGPIO11A_H2F_A;
output SPI1_SDI_MGPIO11A_H2F_B;
output SPI1_SDO_MGPIO12A_H2F_A;
output SPI1_SDO_MGPIO12A_H2F_B;
output SPI1_SS0_MGPIO13A_H2F_A;
output SPI1_SS0_MGPIO13A_H2F_B;
output SPI1_SS1_MGPIO14A_H2F_A;
output SPI1_SS1_MGPIO14A_H2F_B;
output SPI1_SS2_MGPIO15A_H2F_A;
output SPI1_SS2_MGPIO15A_H2F_B;
output SPI1_SS3_MGPIO16A_H2F_A;
output SPI1_SS3_MGPIO16A_H2F_B;
output SPI1_SS4_MGPIO17A_H2F_A;
output SPI1_SS5_MGPIO18A_H2F_A;
output SPI1_SS6_MGPIO23A_H2F_A;
output SPI1_SS7_MGPIO24A_H2F_A;
output [9:0] TCGF;
output TRACECLK;
output [3:0] TRACEDATA;
output TX_CLK;
output TX_ENF;
output TX_ERRF;
output TXCTL_EN_RIF;
output [3:0] TXD_RIF;
output [7:0] TXDF;
output TXEV;
output WDOGTIMEOUT;
output F_ARREADY_HREADYOUT1;
output F_AWREADY_HREADYOUT0;
output [3:0] F_BID;
output [1:0] F_BRESP_HRESP0;
output F_BVALID;
output [63:0] F_RDATA_HRDATA01;
output [3:0] F_RID;
output F_RLAST;
output [1:0] F_RRESP_HRESP1;
output F_RVALID;
output F_WREADY;
output [15:0] MDDR_FABRIC_PRDATA;
output MDDR_FABRIC_PREADY;
output MDDR_FABRIC_PSLVERR;
input  CAN_RXBUS_F2H_SCP;
input  CAN_TX_EBL_F2H_SCP;
input  CAN_TXBUS_F2H_SCP;
input  COLF;
input  CRSF;
input  [1:0] F2_DMAREADY;
input  [15:0] F2H_INTERRUPT;
input  F2HCALIB;
input  [1:0] F_DMAREADY;
input  [31:0] F_FM0_ADDR;
input  F_FM0_ENABLE;
input  F_FM0_MASTLOCK;
input  F_FM0_READY;
input  F_FM0_SEL;
input  [1:0] F_FM0_SIZE;
input  F_FM0_TRANS1;
input  [31:0] F_FM0_WDATA;
input  F_FM0_WRITE;
input  [31:0] F_HM0_RDATA;
input  F_HM0_READY;
input  F_HM0_RESP;
input  FAB_AVALID;
input  FAB_HOSTDISCON;
input  FAB_IDDIG;
input  [1:0] FAB_LINESTATE;
input  FAB_M3_RESET_N;
input  FAB_PLL_LOCK;
input  FAB_RXACTIVE;
input  FAB_RXERROR;
input  FAB_RXVALID;
input  FAB_RXVALIDH;
input  FAB_SESSEND;
input  FAB_TXREADY;
input  FAB_VBUSVALID;
input  [7:0] FAB_VSTATUS;
input  [7:0] FAB_XDATAIN;
input  GTX_CLKPF;
input  I2C0_BCLK;
input  I2C0_SCL_F2H_SCP;
input  I2C0_SDA_F2H_SCP;
input  I2C1_BCLK;
input  I2C1_SCL_F2H_SCP;
input  I2C1_SDA_F2H_SCP;
input  MDIF;
input  MGPIO0A_F2H_GPIN;
input  MGPIO10A_F2H_GPIN;
input  MGPIO11A_F2H_GPIN;
input  MGPIO11B_F2H_GPIN;
input  MGPIO12A_F2H_GPIN;
input  MGPIO13A_F2H_GPIN;
input  MGPIO14A_F2H_GPIN;
input  MGPIO15A_F2H_GPIN;
input  MGPIO16A_F2H_GPIN;
input  MGPIO17B_F2H_GPIN;
input  MGPIO18B_F2H_GPIN;
input  MGPIO19B_F2H_GPIN;
input  MGPIO1A_F2H_GPIN;
input  MGPIO20B_F2H_GPIN;
input  MGPIO21B_F2H_GPIN;
input  MGPIO22B_F2H_GPIN;
input  MGPIO24B_F2H_GPIN;
input  MGPIO25B_F2H_GPIN;
input  MGPIO26B_F2H_GPIN;
input  MGPIO27B_F2H_GPIN;
input  MGPIO28B_F2H_GPIN;
input  MGPIO29B_F2H_GPIN;
input  MGPIO2A_F2H_GPIN;
input  MGPIO30B_F2H_GPIN;
input  MGPIO31B_F2H_GPIN;
input  MGPIO3A_F2H_GPIN;
input  MGPIO4A_F2H_GPIN;
input  MGPIO5A_F2H_GPIN;
input  MGPIO6A_F2H_GPIN;
input  MGPIO7A_F2H_GPIN;
input  MGPIO8A_F2H_GPIN;
input  MGPIO9A_F2H_GPIN;
input  MMUART0_CTS_F2H_SCP;
input  MMUART0_DCD_F2H_SCP;
input  MMUART0_DSR_F2H_SCP;
input  MMUART0_DTR_F2H_SCP;
input  MMUART0_RI_F2H_SCP;
input  MMUART0_RTS_F2H_SCP;
input  MMUART0_RXD_F2H_SCP;
input  MMUART0_SCK_F2H_SCP;
input  MMUART0_TXD_F2H_SCP;
input  MMUART1_CTS_F2H_SCP;
input  MMUART1_DCD_F2H_SCP;
input  MMUART1_DSR_F2H_SCP;
input  MMUART1_RI_F2H_SCP;
input  MMUART1_RTS_F2H_SCP;
input  MMUART1_RXD_F2H_SCP;
input  MMUART1_SCK_F2H_SCP;
input  MMUART1_TXD_F2H_SCP;
input  [31:0] PER2_FABRIC_PRDATA;
input  PER2_FABRIC_PREADY;
input  PER2_FABRIC_PSLVERR;
input  [9:0] RCGF;
input  RX_CLKPF;
input  RX_DVF;
input  RX_ERRF;
input  RX_EV;
input  [7:0] RXDF;
input  SLEEPHOLDREQ;
input  SMBALERT_NI0;
input  SMBALERT_NI1;
input  SMBSUS_NI0;
input  SMBSUS_NI1;
input  SPI0_CLK_IN;
input  SPI0_SDI_F2H_SCP;
input  SPI0_SDO_F2H_SCP;
input  SPI0_SS0_F2H_SCP;
input  SPI0_SS1_F2H_SCP;
input  SPI0_SS2_F2H_SCP;
input  SPI0_SS3_F2H_SCP;
input  SPI1_CLK_IN;
input  SPI1_SDI_F2H_SCP;
input  SPI1_SDO_F2H_SCP;
input  SPI1_SS0_F2H_SCP;
input  SPI1_SS1_F2H_SCP;
input  SPI1_SS2_F2H_SCP;
input  SPI1_SS3_F2H_SCP;
input  TX_CLKPF;
input  USER_MSS_GPIO_RESET_N;
input  USER_MSS_RESET_N;
input  XCLK_FAB;
input  CLK_BASE;
input  CLK_MDDR_APB;
input  [31:0] F_ARADDR_HADDR1;
input  [1:0] F_ARBURST_HTRANS1;
input  [3:0] F_ARID_HSEL1;
input  [3:0] F_ARLEN_HBURST1;
input  [1:0] F_ARLOCK_HMASTLOCK1;
input  [1:0] F_ARSIZE_HSIZE1;
input  F_ARVALID_HWRITE1;
input  [31:0] F_AWADDR_HADDR0;
input  [1:0] F_AWBURST_HTRANS0;
input  [3:0] F_AWID_HSEL0;
input  [3:0] F_AWLEN_HBURST0;
input  [1:0] F_AWLOCK_HMASTLOCK0;
input  [1:0] F_AWSIZE_HSIZE0;
input  F_AWVALID_HWRITE0;
input  F_BREADY;
input  F_RMW_AXI;
input  F_RREADY;
input  [63:0] F_WDATA_HWDATA01;
input  [3:0] F_WID_HREADY01;
input  F_WLAST;
input  [7:0] F_WSTRB;
input  F_WVALID;
input  FPGA_MDDR_ARESET_N;
input  [10:2] MDDR_FABRIC_PADDR;
input  MDDR_FABRIC_PENABLE;
input  MDDR_FABRIC_PSEL;
input  [15:0] MDDR_FABRIC_PWDATA;
input  MDDR_FABRIC_PWRITE;
input  PRESET_N;
input  CAN_RXBUS_USBA_DATA1_MGPIO3A_IN;
input  CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN;
input  CAN_TXBUS_USBA_DATA0_MGPIO2A_IN;
input  [2:0] DM_IN;
input  [17:0] DRAM_DQ_IN;
input  [2:0] DRAM_DQS_IN;
input  [1:0] DRAM_FIFO_WE_IN;
input  I2C0_SCL_USBC_DATA1_MGPIO31B_IN;
input  I2C0_SDA_USBC_DATA0_MGPIO30B_IN;
input  I2C1_SCL_USBA_DATA4_MGPIO1A_IN;
input  I2C1_SDA_USBA_DATA3_MGPIO0A_IN;
input  MMUART0_CTS_USBC_DATA7_MGPIO19B_IN;
input  MMUART0_DCD_MGPIO22B_IN;
input  MMUART0_DSR_MGPIO20B_IN;
input  MMUART0_DTR_USBC_DATA6_MGPIO18B_IN;
input  MMUART0_RI_MGPIO21B_IN;
input  MMUART0_RTS_USBC_DATA5_MGPIO17B_IN;
input  MMUART0_RXD_USBC_STP_MGPIO28B_IN;
input  MMUART0_SCK_USBC_NXT_MGPIO29B_IN;
input  MMUART0_TXD_USBC_DIR_MGPIO27B_IN;
input  MMUART1_RXD_USBC_DATA3_MGPIO26B_IN;
input  MMUART1_SCK_USBC_DATA4_MGPIO25B_IN;
input  MMUART1_TXD_USBC_DATA2_MGPIO24B_IN;
input  RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN;
input  RGMII_MDC_RMII_MDC_IN;
input  RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN;
input  RGMII_RX_CLK_IN;
input  RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN;
input  RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN;
input  RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN;
input  RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN;
input  RGMII_RXD3_USBB_DATA4_IN;
input  RGMII_TX_CLK_IN;
input  RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN;
input  RGMII_TXD0_RMII_TXD0_USBB_DIR_IN;
input  RGMII_TXD1_RMII_TXD1_USBB_STP_IN;
input  RGMII_TXD2_USBB_DATA5_IN;
input  RGMII_TXD3_USBB_DATA6_IN;
input  SPI0_SCK_USBA_XCLK_IN;
input  SPI0_SDI_USBA_DIR_MGPIO5A_IN;
input  SPI0_SDO_USBA_STP_MGPIO6A_IN;
input  SPI0_SS0_USBA_NXT_MGPIO7A_IN;
input  SPI0_SS1_USBA_DATA5_MGPIO8A_IN;
input  SPI0_SS2_USBA_DATA6_MGPIO9A_IN;
input  SPI0_SS3_USBA_DATA7_MGPIO10A_IN;
input  SPI1_SCK_IN;
input  SPI1_SDI_MGPIO11A_IN;
input  SPI1_SDO_MGPIO12A_IN;
input  SPI1_SS0_MGPIO13A_IN;
input  SPI1_SS1_MGPIO14A_IN;
input  SPI1_SS2_MGPIO15A_IN;
input  SPI1_SS3_MGPIO16A_IN;
input  SPI1_SS4_MGPIO17A_IN;
input  SPI1_SS5_MGPIO18A_IN;
input  SPI1_SS6_MGPIO23A_IN;
input  SPI1_SS7_MGPIO24A_IN;
input  USBC_XCLK_IN;
output CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT;
output CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT;
output CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT;
output [15:0] DRAM_ADDR;
output [2:0] DRAM_BA;
output DRAM_CASN;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CSN;
output [2:0] DRAM_DM_RDQS_OUT;
output [17:0] DRAM_DQ_OUT;
output [2:0] DRAM_DQS_OUT;
output [1:0] DRAM_FIFO_WE_OUT;
output DRAM_ODT;
output DRAM_RASN;
output DRAM_RSTN;
output DRAM_WEN;
output I2C0_SCL_USBC_DATA1_MGPIO31B_OUT;
output I2C0_SDA_USBC_DATA0_MGPIO30B_OUT;
output I2C1_SCL_USBA_DATA4_MGPIO1A_OUT;
output I2C1_SDA_USBA_DATA3_MGPIO0A_OUT;
output MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT;
output MMUART0_DCD_MGPIO22B_OUT;
output MMUART0_DSR_MGPIO20B_OUT;
output MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT;
output MMUART0_RI_MGPIO21B_OUT;
output MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT;
output MMUART0_RXD_USBC_STP_MGPIO28B_OUT;
output MMUART0_SCK_USBC_NXT_MGPIO29B_OUT;
output MMUART0_TXD_USBC_DIR_MGPIO27B_OUT;
output MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT;
output MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT;
output MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT;
output RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT;
output RGMII_MDC_RMII_MDC_OUT;
output RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT;
output RGMII_RX_CLK_OUT;
output RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT;
output RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT;
output RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT;
output RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT;
output RGMII_RXD3_USBB_DATA4_OUT;
output RGMII_TX_CLK_OUT;
output RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT;
output RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT;
output RGMII_TXD1_RMII_TXD1_USBB_STP_OUT;
output RGMII_TXD2_USBB_DATA5_OUT;
output RGMII_TXD3_USBB_DATA6_OUT;
output SPI0_SCK_USBA_XCLK_OUT;
output SPI0_SDI_USBA_DIR_MGPIO5A_OUT;
output SPI0_SDO_USBA_STP_MGPIO6A_OUT;
output SPI0_SS0_USBA_NXT_MGPIO7A_OUT;
output SPI0_SS1_USBA_DATA5_MGPIO8A_OUT;
output SPI0_SS2_USBA_DATA6_MGPIO9A_OUT;
output SPI0_SS3_USBA_DATA7_MGPIO10A_OUT;
output SPI1_SCK_OUT;
output SPI1_SDI_MGPIO11A_OUT;
output SPI1_SDO_MGPIO12A_OUT;
output SPI1_SS0_MGPIO13A_OUT;
output SPI1_SS1_MGPIO14A_OUT;
output SPI1_SS2_MGPIO15A_OUT;
output SPI1_SS3_MGPIO16A_OUT;
output SPI1_SS4_MGPIO17A_OUT;
output SPI1_SS5_MGPIO18A_OUT;
output SPI1_SS6_MGPIO23A_OUT;
output SPI1_SS7_MGPIO24A_OUT;
output USBC_XCLK_OUT;
output CAN_RXBUS_USBA_DATA1_MGPIO3A_OE;
output CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE;
output CAN_TXBUS_USBA_DATA0_MGPIO2A_OE;
output [2:0] DM_OE;
output [17:0] DRAM_DQ_OE;
output [2:0] DRAM_DQS_OE;
output I2C0_SCL_USBC_DATA1_MGPIO31B_OE;
output I2C0_SDA_USBC_DATA0_MGPIO30B_OE;
output I2C1_SCL_USBA_DATA4_MGPIO1A_OE;
output I2C1_SDA_USBA_DATA3_MGPIO0A_OE;
output MMUART0_CTS_USBC_DATA7_MGPIO19B_OE;
output MMUART0_DCD_MGPIO22B_OE;
output MMUART0_DSR_MGPIO20B_OE;
output MMUART0_DTR_USBC_DATA6_MGPIO18B_OE;
output MMUART0_RI_MGPIO21B_OE;
output MMUART0_RTS_USBC_DATA5_MGPIO17B_OE;
output MMUART0_RXD_USBC_STP_MGPIO28B_OE;
output MMUART0_SCK_USBC_NXT_MGPIO29B_OE;
output MMUART0_TXD_USBC_DIR_MGPIO27B_OE;
output MMUART1_RXD_USBC_DATA3_MGPIO26B_OE;
output MMUART1_SCK_USBC_DATA4_MGPIO25B_OE;
output MMUART1_TXD_USBC_DATA2_MGPIO24B_OE;
output RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE;
output RGMII_MDC_RMII_MDC_OE;
output RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE;
output RGMII_RX_CLK_OE;
output RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE;
output RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE;
output RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE;
output RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE;
output RGMII_RXD3_USBB_DATA4_OE;
output RGMII_TX_CLK_OE;
output RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE;
output RGMII_TXD0_RMII_TXD0_USBB_DIR_OE;
output RGMII_TXD1_RMII_TXD1_USBB_STP_OE;
output RGMII_TXD2_USBB_DATA5_OE;
output RGMII_TXD3_USBB_DATA6_OE;
output SPI0_SCK_USBA_XCLK_OE;
output SPI0_SDI_USBA_DIR_MGPIO5A_OE;
output SPI0_SDO_USBA_STP_MGPIO6A_OE;
output SPI0_SS0_USBA_NXT_MGPIO7A_OE;
output SPI0_SS1_USBA_DATA5_MGPIO8A_OE;
output SPI0_SS2_USBA_DATA6_MGPIO9A_OE;
output SPI0_SS3_USBA_DATA7_MGPIO10A_OE;
output SPI1_SCK_OE;
output SPI1_SDI_MGPIO11A_OE;
output SPI1_SDO_MGPIO12A_OE;
output SPI1_SS0_MGPIO13A_OE;
output SPI1_SS1_MGPIO14A_OE;
output SPI1_SS2_MGPIO15A_OE;
output SPI1_SS3_MGPIO16A_OE;
output SPI1_SS4_MGPIO17A_OE;
output SPI1_SS5_MGPIO18A_OE;
output SPI1_SS6_MGPIO23A_OE;
output SPI1_SS7_MGPIO24A_OE;
output USBC_XCLK_OE;

    parameter INIT = 'h0 ;
    parameter ACT_UBITS = 'hFFFFFFFFFFFFFF ;
    parameter MEMORYFILE = "" ;
    parameter RTC_MAIN_XTL_FREQ = 0.0 ;
    parameter RTC_MAIN_XTL_MODE = "1" ;
    parameter DDR_CLK_FREQ = 0.0 ;
    
endmodule


module MC_System_sb_FABOSC_0_OSC(
       FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
    );
output FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;

    wire GND, VCC;
    
    RCOSC_25_50MHZ #( .FREQUENCY(50.000000) )  I_RCOSC_25_50MHZ (
        .CLKOUT(FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    VCC VCC_Z (.Y(VCC));
    GND GND_Z (.Y(GND));
    
endmodule


module COREAPB3_MUXPTOB3(
       FOC_TRANSFORMS_0_valpha_o,
       FOC_TRANSFORMS_0_valpha_o_m_0,
       FOC_TRANSFORMS_0_valpha_o_m_5,
       FOC_TRANSFORMS_0_ialpha_o_m,
       SPEED_ID_IQ_PI_0_iq_pi_output_o,
       adc_interface_0_result_ch3_o_m,
       MC_System_0_AMBA_SLAVE_0_PRDATA,
       SPEED_ID_IQ_PI_0_id_pi_output_o,
       HALL_INTERFACE_1_omega_out_o,
       FOC_TRANSFORMS_0_ialpha_o,
       adc_interface_0_result_ch1_o_2,
       adc_interface_0_result_ch1_o_0,
       SEQ_CONTROLLER_0_state_o_2,
       SEQ_CONTROLLER_0_state_o_0,
       adc_interface_0_result_ch0_o,
       FOC_TRANSFORMS_0_ibeta_o,
       prdata_o_1_0_iv_0_14,
       prdata_o_1_0_iv_0_15,
       prdata_o_1_0_iv_0_13,
       prdata_o_1_iv_10_0,
       FOC_TRANSFORMS_0_id_o_m,
       prdata_o_1_iv_13,
       prdata_o_1_iv_14_0,
       prdata_o_1_iv_14_2,
       prdata_o_1_iv_12,
       prdata_o_1_iv_10_12,
       prdata_o_1_iv_10_13,
       prdata_o_1_iv_10_11,
       prdata_o_1_iv_0_7,
       prdata_o_1_iv_0_6,
       prdata_o_1_iv_0_8,
       prdata_o_1_iv_0_7_0,
       prdata_o_1_iv_0_9,
       prdata_o_1_iv_10,
       prdata_o_1_iv_11,
       prdata_o_1_iv_9,
       prdata_o_1_iv_0_11_0,
       prdata_o_1_iv_0_11_2,
       prdata_o_1_iv_0_11_3,
       prdata_o_1_iv_0_12_0,
       prdata_o_1_iv_0_12_2,
       prdata_o_1_iv_0_10,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15,
       prdata_m2_e_5_6,
       prdata_m2_e_5_11,
       prdata_m2_e_5_1,
       prdata_N_5_mux_i_3_a0_7_1,
       prdata_o263,
       prdata_o274,
       prdata_m2_e_5_4,
       MC_System_0_AMBA_SLAVE_0_PSELx,
       prdata_m2_e_5_10,
       prdata_N_5_mux_i_3_a0_11,
       prdata_N_5_mux_i_3_a0_10,
       prdata_N_5_mux_i_3_a0_4,
       prdata_N_5_mux_i_3_a0_0,
       prdata_N_5_mux_i_3_a0_12,
       prdata_N_5_mux_i_2_a0_11,
       prdata_N_5_mux_i_2_a0_10,
       prdata_N_5_mux_i_2_a0_4,
       prdata_N_5_mux_i_2_a0_0,
       prdata_N_5_mux_i_2_a0_12,
       prdata_m2_0_a2_1_0,
       prdata_m2_0_a2_17_0,
       N_358,
       prdata_m2_e_5_6_1,
       prdata_N_5_mux_i_1_a0_13,
       prdata_N_5_mux_i_1_a0_12,
       prdata_o277,
       prdata_o267,
       N_296,
       prdata_o259,
       N_225,
       prdata_o270,
       N_283,
       N_286,
       prdata_o260,
       prdata_m2_e_0_9,
       prdata_m2_e_0_10,
       prdata_m2_e_0_8,
       prdata_m2_e_27_11,
       prdata_m2_e_27_12,
       prdata_m2_e_27_10,
       prdata_N_5_mux_i_4_a0_12,
       prdata_N_5_mux_i_4_a0_13,
       prdata_N_5_mux_i_4_a0_11,
       m7_i_2,
       N_435_4,
       N_157
    );
input  [2:2] FOC_TRANSFORMS_0_valpha_o;
input  FOC_TRANSFORMS_0_valpha_o_m_0;
input  FOC_TRANSFORMS_0_valpha_o_m_5;
input  [9:9] FOC_TRANSFORMS_0_ialpha_o_m;
input  [9:9] SPEED_ID_IQ_PI_0_iq_pi_output_o;
input  [9:9] adc_interface_0_result_ch3_o_m;
input  [19:19] MC_System_0_AMBA_SLAVE_0_PRDATA;
input  [0:0] SPEED_ID_IQ_PI_0_id_pi_output_o;
input  [0:0] HALL_INTERFACE_1_omega_out_o;
input  [0:0] FOC_TRANSFORMS_0_ialpha_o;
input  adc_interface_0_result_ch1_o_2;
input  adc_interface_0_result_ch1_o_0;
input  SEQ_CONTROLLER_0_state_o_2;
input  SEQ_CONTROLLER_0_state_o_0;
input  [0:0] adc_interface_0_result_ch0_o;
input  [0:0] FOC_TRANSFORMS_0_ibeta_o;
input  [1:1] prdata_o_1_0_iv_0_14;
input  [1:0] prdata_o_1_0_iv_0_15;
input  [1:1] prdata_o_1_0_iv_0_13;
input  [5:5] prdata_o_1_iv_10_0;
input  [5:5] FOC_TRANSFORMS_0_id_o_m;
input  [7:7] prdata_o_1_iv_13;
input  prdata_o_1_iv_14_0;
input  prdata_o_1_iv_14_2;
input  [7:7] prdata_o_1_iv_12;
input  [10:10] prdata_o_1_iv_10_12;
input  [10:10] prdata_o_1_iv_10_13;
input  [10:10] prdata_o_1_iv_10_11;
input  [12:12] prdata_o_1_iv_0_7;
input  [12:12] prdata_o_1_iv_0_6;
input  [13:13] prdata_o_1_iv_0_8;
input  [13:13] prdata_o_1_iv_0_7_0;
input  [14:14] prdata_o_1_iv_0_9;
input  [16:16] prdata_o_1_iv_10;
input  [16:16] prdata_o_1_iv_11;
input  [16:16] prdata_o_1_iv_9;
input  prdata_o_1_iv_0_11_0;
input  prdata_o_1_iv_0_11_2;
input  prdata_o_1_iv_0_11_3;
input  prdata_o_1_iv_0_12_0;
input  prdata_o_1_iv_0_12_2;
input  [15:14] prdata_o_1_iv_0_10;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15;
input  prdata_m2_e_5_6;
input  prdata_m2_e_5_11;
input  prdata_m2_e_5_1;
input  prdata_N_5_mux_i_3_a0_7_1;
input  prdata_o263;
input  prdata_o274;
input  prdata_m2_e_5_4;
input  MC_System_0_AMBA_SLAVE_0_PSELx;
input  prdata_m2_e_5_10;
input  prdata_N_5_mux_i_3_a0_11;
input  prdata_N_5_mux_i_3_a0_10;
input  prdata_N_5_mux_i_3_a0_4;
input  prdata_N_5_mux_i_3_a0_0;
input  prdata_N_5_mux_i_3_a0_12;
input  prdata_N_5_mux_i_2_a0_11;
input  prdata_N_5_mux_i_2_a0_10;
input  prdata_N_5_mux_i_2_a0_4;
input  prdata_N_5_mux_i_2_a0_0;
input  prdata_N_5_mux_i_2_a0_12;
input  prdata_m2_0_a2_1_0;
input  prdata_m2_0_a2_17_0;
input  N_358;
input  prdata_m2_e_5_6_1;
input  prdata_N_5_mux_i_1_a0_13;
input  prdata_N_5_mux_i_1_a0_12;
input  prdata_o277;
input  prdata_o267;
input  N_296;
input  prdata_o259;
input  N_225;
input  prdata_o270;
input  N_283;
input  N_286;
input  prdata_o260;
input  prdata_m2_e_0_9;
input  prdata_m2_e_0_10;
input  prdata_m2_e_0_8;
input  prdata_m2_e_27_11;
input  prdata_m2_e_27_12;
input  prdata_m2_e_27_10;
input  prdata_N_5_mux_i_4_a0_12;
input  prdata_N_5_mux_i_4_a0_13;
input  prdata_N_5_mux_i_4_a0_11;
input  m7_i_2;
input  N_435_4;
input  N_157;

    wire [11:6] PRDATA_1;
    wire PRDATA_N_4L5_1_Z, PRDATA_N_4L5_Z, PRDATA_N_3L3_Z, 
        PRDATA_N_3L4_Z, PRDATA_N_4L6_Z, PRDATA_m8_0_a2_3_Z, 
        PRDATA_m8_0_a2_1_Z, PRDATA_m8_0_a2_4_Z, PRDATA_m8_0_a2_2_Z, 
        PRDATA_m8_0_a2_9_Z, PRDATA_m8_0_a2_8_Z, GND, VCC;
    
    CFG4 #( .INIT(16'h4000) )  \PRDATA_1[6]  (.A(
        FOC_TRANSFORMS_0_valpha_o_m_0), .B(prdata_N_5_mux_i_3_a0_4), 
        .C(prdata_N_5_mux_i_3_a0_0), .D(prdata_N_5_mux_i_3_a0_12), .Y(
        PRDATA_1[6]));
    CFG4 #( .INIT(16'hCCC8) )  \PRDATA[14]  (.A(prdata_o_1_iv_0_10[14])
        , .B(MC_System_0_AMBA_SLAVE_0_PSELx), .C(prdata_o_1_iv_0_11_2), 
        .D(prdata_o_1_iv_0_9[14]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14));
    CFG4 #( .INIT(16'h4CCC) )  \PRDATA[4]  (.A(prdata_m2_e_0_9), .B(
        MC_System_0_AMBA_SLAVE_0_PSELx), .C(prdata_m2_e_0_10), .D(
        prdata_m2_e_0_8), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4));
    CFG4 #( .INIT(16'h4C00) )  PRDATA_m8_0_a2_8 (.A(
        FOC_TRANSFORMS_0_ibeta_o[0]), .B(PRDATA_m8_0_a2_1_Z), .C(
        prdata_o260), .D(PRDATA_m8_0_a2_2_Z), .Y(PRDATA_m8_0_a2_8_Z));
    CFG4 #( .INIT(16'hAAA8) )  \PRDATA[10]  (.A(
        MC_System_0_AMBA_SLAVE_0_PSELx), .B(prdata_o_1_iv_10_12[10]), 
        .C(prdata_o_1_iv_10_13[10]), .D(prdata_o_1_iv_10_11[10]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10));
    CFG3 #( .INIT(8'h15) )  PRDATA_m8_0_a2_1 (.A(N_296), .B(
        FOC_TRANSFORMS_0_ialpha_o[0]), .C(prdata_o259), .Y(
        PRDATA_m8_0_a2_1_Z));
    CFG4 #( .INIT(16'hC4CC) )  \PRDATA[2]  (.A(PRDATA_N_3L3_Z), .B(
        MC_System_0_AMBA_SLAVE_0_PSELx), .C(PRDATA_N_4L5_Z), .D(
        prdata_m2_e_5_10), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2));
    CFG4 #( .INIT(16'hAAA8) )  \PRDATA[1]  (.A(
        MC_System_0_AMBA_SLAVE_0_PSELx), .B(prdata_o_1_0_iv_0_14[1]), 
        .C(prdata_o_1_0_iv_0_15[1]), .D(prdata_o_1_0_iv_0_13[1]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1));
    CFG4 #( .INIT(16'h153F) )  PRDATA_m8_0_a2_3 (.A(
        SPEED_ID_IQ_PI_0_id_pi_output_o[0]), .B(
        HALL_INTERFACE_1_omega_out_o[0]), .C(prdata_o277), .D(
        prdata_o267), .Y(PRDATA_m8_0_a2_3_Z));
    CFG4 #( .INIT(16'h4CCC) )  \PRDATA[8]  (.A(
        prdata_N_5_mux_i_4_a0_12), .B(MC_System_0_AMBA_SLAVE_0_PSELx), 
        .C(prdata_N_5_mux_i_4_a0_13), .D(prdata_N_5_mux_i_4_a0_11), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8));
    CFG4 #( .INIT(16'h4000) )  \PRDATA_1[11]  (.A(
        FOC_TRANSFORMS_0_valpha_o_m_5), .B(prdata_N_5_mux_i_2_a0_4), 
        .C(prdata_N_5_mux_i_2_a0_0), .D(prdata_N_5_mux_i_2_a0_12), .Y(
        PRDATA_1[11]));
    CFG4 #( .INIT(16'hF0E0) )  \PRDATA[12]  (.A(prdata_o_1_iv_0_11_0), 
        .B(prdata_o_1_iv_0_7[12]), .C(MC_System_0_AMBA_SLAVE_0_PSELx), 
        .D(prdata_o_1_iv_0_6[12]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12));
    CFG4 #( .INIT(16'hF0E0) )  \PRDATA[5]  (.A(prdata_o_1_iv_10_0[5]), 
        .B(prdata_o_1_iv_14_0), .C(MC_System_0_AMBA_SLAVE_0_PSELx), .D(
        FOC_TRANSFORMS_0_id_o_m[5]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5));
    CFG4 #( .INIT(16'h153F) )  PRDATA_N_4L5_1 (.A(
        FOC_TRANSFORMS_0_valpha_o[2]), .B(
        adc_interface_0_result_ch1_o_2), .C(prdata_N_5_mux_i_3_a0_7_1), 
        .D(prdata_o263), .Y(PRDATA_N_4L5_1_Z));
    CFG3 #( .INIT(8'h70) )  PRDATA_N_3L3 (.A(prdata_o274), .B(
        SEQ_CONTROLLER_0_state_o_2), .C(prdata_m2_e_5_4), .Y(
        PRDATA_N_3L3_Z));
    CFG4 #( .INIT(16'h0400) )  PRDATA_m8_0_a2_9 (.A(N_283), .B(
        PRDATA_m8_0_a2_3_Z), .C(N_286), .D(PRDATA_m8_0_a2_4_Z), .Y(
        PRDATA_m8_0_a2_9_Z));
    CFG4 #( .INIT(16'hF0E0) )  \PRDATA[15]  (.A(prdata_o_1_iv_0_11_3), 
        .B(prdata_o_1_iv_0_12_2), .C(MC_System_0_AMBA_SLAVE_0_PSELx), 
        .D(prdata_o_1_iv_0_10[15]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15));
    CFG4 #( .INIT(16'h010F) )  PRDATA_N_3L4 (.A(prdata_m2_0_a2_1_0), 
        .B(prdata_m2_0_a2_17_0), .C(FOC_TRANSFORMS_0_ialpha_o_m[9]), 
        .D(N_358), .Y(PRDATA_N_3L4_Z));
    CFG4 #( .INIT(16'h4CCC) )  \PRDATA[3]  (.A(prdata_m2_e_27_11), .B(
        MC_System_0_AMBA_SLAVE_0_PSELx), .C(prdata_m2_e_27_12), .D(
        prdata_m2_e_27_10), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3));
    CFG4 #( .INIT(16'hAAA8) )  \PRDATA[17]  (.A(
        MC_System_0_AMBA_SLAVE_0_PSELx), .B(m7_i_2), .C(N_435_4), .D(
        N_157), .Y(MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17));
    GND GND_Z (.Y(GND));
    VCC VCC_Z (.Y(VCC));
    CFG4 #( .INIT(16'h153F) )  PRDATA_m8_0_a2_4 (.A(
        adc_interface_0_result_ch1_o_0), .B(SEQ_CONTROLLER_0_state_o_0)
        , .C(prdata_o274), .D(prdata_N_5_mux_i_3_a0_7_1), .Y(
        PRDATA_m8_0_a2_4_Z));
    CFG4 #( .INIT(16'h020A) )  PRDATA_m8_0_a2_2 (.A(
        MC_System_0_AMBA_SLAVE_0_PSELx), .B(
        adc_interface_0_result_ch0_o[0]), .C(N_225), .D(prdata_o270), 
        .Y(PRDATA_m8_0_a2_2_Z));
    CFG4 #( .INIT(16'hEA2A) )  \PRDATA_0[0]  (.A(
        MC_System_0_AMBA_SLAVE_0_PSELx), .B(PRDATA_m8_0_a2_8_Z), .C(
        PRDATA_m8_0_a2_9_Z), .D(prdata_o_1_0_iv_0_15[0]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0));
    CFG4 #( .INIT(16'h4CCC) )  \PRDATA[9]  (.A(PRDATA_N_4L6_Z), .B(
        MC_System_0_AMBA_SLAVE_0_PSELx), .C(prdata_N_5_mux_i_1_a0_13), 
        .D(prdata_N_5_mux_i_1_a0_12), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9));
    CFG4 #( .INIT(16'h70F0) )  \PRDATA[6]  (.A(
        prdata_N_5_mux_i_3_a0_11), .B(PRDATA_1[6]), .C(
        MC_System_0_AMBA_SLAVE_0_PSELx), .D(prdata_N_5_mux_i_3_a0_10), 
        .Y(MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6));
    CFG4 #( .INIT(16'hCCC8) )  \PRDATA[13]  (.A(prdata_o_1_iv_0_12_0), 
        .B(MC_System_0_AMBA_SLAVE_0_PSELx), .C(prdata_o_1_iv_0_8[13]), 
        .D(prdata_o_1_iv_0_7_0[13]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13));
    CFG4 #( .INIT(16'hAAA8) )  \PRDATA[16]  (.A(
        MC_System_0_AMBA_SLAVE_0_PSELx), .B(prdata_o_1_iv_10[16]), .C(
        prdata_o_1_iv_11[16]), .D(prdata_o_1_iv_9[16]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16));
    CFG4 #( .INIT(16'h0700) )  PRDATA_N_4L6 (.A(prdata_m2_e_5_6_1), .B(
        SPEED_ID_IQ_PI_0_iq_pi_output_o[9]), .C(
        adc_interface_0_result_ch3_o_m[9]), .D(PRDATA_N_3L4_Z), .Y(
        PRDATA_N_4L6_Z));
    CFG4 #( .INIT(16'hF0E0) )  \PRDATA[7]  (.A(prdata_o_1_iv_13[7]), 
        .B(prdata_o_1_iv_14_2), .C(MC_System_0_AMBA_SLAVE_0_PSELx), .D(
        prdata_o_1_iv_12[7]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7));
    CFG2 #( .INIT(4'h8) )  \PRDATA[18]  (.A(
        MC_System_0_AMBA_SLAVE_0_PSELx), .B(
        MC_System_0_AMBA_SLAVE_0_PRDATA[19]), .Y(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31));
    CFG4 #( .INIT(16'h7FFF) )  PRDATA_N_4L5 (.A(prdata_m2_e_5_6), .B(
        prdata_m2_e_5_11), .C(prdata_m2_e_5_1), .D(PRDATA_N_4L5_1_Z), 
        .Y(PRDATA_N_4L5_Z));
    CFG4 #( .INIT(16'h70F0) )  \PRDATA[11]  (.A(
        prdata_N_5_mux_i_2_a0_11), .B(PRDATA_1[11]), .C(
        MC_System_0_AMBA_SLAVE_0_PSELx), .D(prdata_N_5_mux_i_2_a0_10), 
        .Y(MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11));
    
endmodule


module 
        CoreAPB3_32_0_1_1_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_16_3_19(
        
       MC_System_0_AMBA_SLAVE_0_PADDR,
       FOC_TRANSFORMS_0_valpha_o,
       FOC_TRANSFORMS_0_valpha_o_m_0,
       FOC_TRANSFORMS_0_valpha_o_m_5,
       FOC_TRANSFORMS_0_ialpha_o_m,
       SPEED_ID_IQ_PI_0_iq_pi_output_o,
       adc_interface_0_result_ch3_o_m,
       MC_System_0_AMBA_SLAVE_0_PRDATA,
       SPEED_ID_IQ_PI_0_id_pi_output_o,
       HALL_INTERFACE_1_omega_out_o,
       FOC_TRANSFORMS_0_ialpha_o,
       adc_interface_0_result_ch1_o_2,
       adc_interface_0_result_ch1_o_0,
       SEQ_CONTROLLER_0_state_o_2,
       SEQ_CONTROLLER_0_state_o_0,
       adc_interface_0_result_ch0_o,
       FOC_TRANSFORMS_0_ibeta_o,
       prdata_o_1_0_iv_0_14,
       prdata_o_1_0_iv_0_15,
       prdata_o_1_0_iv_0_13,
       prdata_o_1_iv_10_0,
       FOC_TRANSFORMS_0_id_o_m,
       prdata_o_1_iv_13,
       prdata_o_1_iv_14_0,
       prdata_o_1_iv_14_2,
       prdata_o_1_iv_12,
       prdata_o_1_iv_10_12,
       prdata_o_1_iv_10_13,
       prdata_o_1_iv_10_11,
       prdata_o_1_iv_0_7,
       prdata_o_1_iv_0_6,
       prdata_o_1_iv_0_8,
       prdata_o_1_iv_0_7_0,
       prdata_o_1_iv_0_9,
       prdata_o_1_iv_10,
       prdata_o_1_iv_11,
       prdata_o_1_iv_9,
       prdata_o_1_iv_0_11_0,
       prdata_o_1_iv_0_11_2,
       prdata_o_1_iv_0_11_3,
       prdata_o_1_iv_0_12_0,
       prdata_o_1_iv_0_12_2,
       prdata_o_1_iv_0_10,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx,
       MC_System_0_AMBA_SLAVE_0_PSELx,
       prdata_m2_e_5_6,
       prdata_m2_e_5_11,
       prdata_m2_e_5_1,
       prdata_N_5_mux_i_3_a0_7_1,
       prdata_o263,
       prdata_o274,
       prdata_m2_e_5_4,
       prdata_m2_e_5_10,
       prdata_N_5_mux_i_3_a0_11,
       prdata_N_5_mux_i_3_a0_10,
       prdata_N_5_mux_i_3_a0_4,
       prdata_N_5_mux_i_3_a0_0,
       prdata_N_5_mux_i_3_a0_12,
       prdata_N_5_mux_i_2_a0_11,
       prdata_N_5_mux_i_2_a0_10,
       prdata_N_5_mux_i_2_a0_4,
       prdata_N_5_mux_i_2_a0_0,
       prdata_N_5_mux_i_2_a0_12,
       prdata_m2_0_a2_1_0,
       prdata_m2_0_a2_17_0,
       N_358,
       prdata_m2_e_5_6_1,
       prdata_N_5_mux_i_1_a0_13,
       prdata_N_5_mux_i_1_a0_12,
       prdata_o277,
       prdata_o267,
       N_296,
       prdata_o259,
       N_225,
       prdata_o270,
       N_283,
       N_286,
       prdata_o260,
       prdata_m2_e_0_9,
       prdata_m2_e_0_10,
       prdata_m2_e_0_8,
       prdata_m2_e_27_11,
       prdata_m2_e_27_12,
       prdata_m2_e_27_10,
       prdata_N_5_mux_i_4_a0_12,
       prdata_N_5_mux_i_4_a0_13,
       prdata_N_5_mux_i_4_a0_11,
       m7_i_2,
       N_435_4,
       N_157
    );
input  [15:12] MC_System_0_AMBA_SLAVE_0_PADDR;
input  [2:2] FOC_TRANSFORMS_0_valpha_o;
input  FOC_TRANSFORMS_0_valpha_o_m_0;
input  FOC_TRANSFORMS_0_valpha_o_m_5;
input  [9:9] FOC_TRANSFORMS_0_ialpha_o_m;
input  [9:9] SPEED_ID_IQ_PI_0_iq_pi_output_o;
input  [9:9] adc_interface_0_result_ch3_o_m;
input  [19:19] MC_System_0_AMBA_SLAVE_0_PRDATA;
input  [0:0] SPEED_ID_IQ_PI_0_id_pi_output_o;
input  [0:0] HALL_INTERFACE_1_omega_out_o;
input  [0:0] FOC_TRANSFORMS_0_ialpha_o;
input  adc_interface_0_result_ch1_o_2;
input  adc_interface_0_result_ch1_o_0;
input  SEQ_CONTROLLER_0_state_o_2;
input  SEQ_CONTROLLER_0_state_o_0;
input  [0:0] adc_interface_0_result_ch0_o;
input  [0:0] FOC_TRANSFORMS_0_ibeta_o;
input  [1:1] prdata_o_1_0_iv_0_14;
input  [1:0] prdata_o_1_0_iv_0_15;
input  [1:1] prdata_o_1_0_iv_0_13;
input  [5:5] prdata_o_1_iv_10_0;
input  [5:5] FOC_TRANSFORMS_0_id_o_m;
input  [7:7] prdata_o_1_iv_13;
input  prdata_o_1_iv_14_0;
input  prdata_o_1_iv_14_2;
input  [7:7] prdata_o_1_iv_12;
input  [10:10] prdata_o_1_iv_10_12;
input  [10:10] prdata_o_1_iv_10_13;
input  [10:10] prdata_o_1_iv_10_11;
input  [12:12] prdata_o_1_iv_0_7;
input  [12:12] prdata_o_1_iv_0_6;
input  [13:13] prdata_o_1_iv_0_8;
input  [13:13] prdata_o_1_iv_0_7_0;
input  [14:14] prdata_o_1_iv_0_9;
input  [16:16] prdata_o_1_iv_10;
input  [16:16] prdata_o_1_iv_11;
input  [16:16] prdata_o_1_iv_9;
input  prdata_o_1_iv_0_11_0;
input  prdata_o_1_iv_0_11_2;
input  prdata_o_1_iv_0_11_3;
input  prdata_o_1_iv_0_12_0;
input  prdata_o_1_iv_0_12_2;
input  [15:14] prdata_o_1_iv_0_10;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx;
output MC_System_0_AMBA_SLAVE_0_PSELx;
input  prdata_m2_e_5_6;
input  prdata_m2_e_5_11;
input  prdata_m2_e_5_1;
input  prdata_N_5_mux_i_3_a0_7_1;
input  prdata_o263;
input  prdata_o274;
input  prdata_m2_e_5_4;
input  prdata_m2_e_5_10;
input  prdata_N_5_mux_i_3_a0_11;
input  prdata_N_5_mux_i_3_a0_10;
input  prdata_N_5_mux_i_3_a0_4;
input  prdata_N_5_mux_i_3_a0_0;
input  prdata_N_5_mux_i_3_a0_12;
input  prdata_N_5_mux_i_2_a0_11;
input  prdata_N_5_mux_i_2_a0_10;
input  prdata_N_5_mux_i_2_a0_4;
input  prdata_N_5_mux_i_2_a0_0;
input  prdata_N_5_mux_i_2_a0_12;
input  prdata_m2_0_a2_1_0;
input  prdata_m2_0_a2_17_0;
input  N_358;
input  prdata_m2_e_5_6_1;
input  prdata_N_5_mux_i_1_a0_13;
input  prdata_N_5_mux_i_1_a0_12;
input  prdata_o277;
input  prdata_o267;
input  N_296;
input  prdata_o259;
input  N_225;
input  prdata_o270;
input  N_283;
input  N_286;
input  prdata_o260;
input  prdata_m2_e_0_9;
input  prdata_m2_e_0_10;
input  prdata_m2_e_0_8;
input  prdata_m2_e_27_11;
input  prdata_m2_e_27_12;
input  prdata_m2_e_27_10;
input  prdata_N_5_mux_i_4_a0_12;
input  prdata_N_5_mux_i_4_a0_13;
input  prdata_N_5_mux_i_4_a0_11;
input  m7_i_2;
input  N_435_4;
input  N_157;

    wire [0:0] iPSELS_raw_0_a2_1;
    wire GND, VCC;
    
    CFG4 #( .INIT(16'h0040) )  \iPSELS_raw_0_a2[0]  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[15]), .B(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx), .C(
        iPSELS_raw_0_a2_1[0]), .D(MC_System_0_AMBA_SLAVE_0_PADDR[12]), 
        .Y(MC_System_0_AMBA_SLAVE_0_PSELx));
    COREAPB3_MUXPTOB3 u_mux_p_to_b3 (.FOC_TRANSFORMS_0_valpha_o({
        FOC_TRANSFORMS_0_valpha_o[2]}), .FOC_TRANSFORMS_0_valpha_o_m_0(
        FOC_TRANSFORMS_0_valpha_o_m_0), .FOC_TRANSFORMS_0_valpha_o_m_5(
        FOC_TRANSFORMS_0_valpha_o_m_5), .FOC_TRANSFORMS_0_ialpha_o_m({
        FOC_TRANSFORMS_0_ialpha_o_m[9]}), 
        .SPEED_ID_IQ_PI_0_iq_pi_output_o({
        SPEED_ID_IQ_PI_0_iq_pi_output_o[9]}), 
        .adc_interface_0_result_ch3_o_m({
        adc_interface_0_result_ch3_o_m[9]}), 
        .MC_System_0_AMBA_SLAVE_0_PRDATA({
        MC_System_0_AMBA_SLAVE_0_PRDATA[19]}), 
        .SPEED_ID_IQ_PI_0_id_pi_output_o({
        SPEED_ID_IQ_PI_0_id_pi_output_o[0]}), 
        .HALL_INTERFACE_1_omega_out_o({HALL_INTERFACE_1_omega_out_o[0]})
        , .FOC_TRANSFORMS_0_ialpha_o({FOC_TRANSFORMS_0_ialpha_o[0]}), 
        .adc_interface_0_result_ch1_o_2(adc_interface_0_result_ch1_o_2)
        , .adc_interface_0_result_ch1_o_0(
        adc_interface_0_result_ch1_o_0), .SEQ_CONTROLLER_0_state_o_2(
        SEQ_CONTROLLER_0_state_o_2), .SEQ_CONTROLLER_0_state_o_0(
        SEQ_CONTROLLER_0_state_o_0), .adc_interface_0_result_ch0_o({
        adc_interface_0_result_ch0_o[0]}), .FOC_TRANSFORMS_0_ibeta_o({
        FOC_TRANSFORMS_0_ibeta_o[0]}), .prdata_o_1_0_iv_0_14({
        prdata_o_1_0_iv_0_14[1]}), .prdata_o_1_0_iv_0_15({
        prdata_o_1_0_iv_0_15[1], prdata_o_1_0_iv_0_15[0]}), 
        .prdata_o_1_0_iv_0_13({prdata_o_1_0_iv_0_13[1]}), 
        .prdata_o_1_iv_10_0({prdata_o_1_iv_10_0[5]}), 
        .FOC_TRANSFORMS_0_id_o_m({FOC_TRANSFORMS_0_id_o_m[5]}), 
        .prdata_o_1_iv_13({prdata_o_1_iv_13[7]}), .prdata_o_1_iv_14_0(
        prdata_o_1_iv_14_0), .prdata_o_1_iv_14_2(prdata_o_1_iv_14_2), 
        .prdata_o_1_iv_12({prdata_o_1_iv_12[7]}), .prdata_o_1_iv_10_12({
        prdata_o_1_iv_10_12[10]}), .prdata_o_1_iv_10_13({
        prdata_o_1_iv_10_13[10]}), .prdata_o_1_iv_10_11({
        prdata_o_1_iv_10_11[10]}), .prdata_o_1_iv_0_7({
        prdata_o_1_iv_0_7[12]}), .prdata_o_1_iv_0_6({
        prdata_o_1_iv_0_6[12]}), .prdata_o_1_iv_0_8({
        prdata_o_1_iv_0_8[13]}), .prdata_o_1_iv_0_7_0({
        prdata_o_1_iv_0_7_0[13]}), .prdata_o_1_iv_0_9({
        prdata_o_1_iv_0_9[14]}), .prdata_o_1_iv_10({
        prdata_o_1_iv_10[16]}), .prdata_o_1_iv_11({
        prdata_o_1_iv_11[16]}), .prdata_o_1_iv_9({prdata_o_1_iv_9[16]})
        , .prdata_o_1_iv_0_11_0(prdata_o_1_iv_0_11_0), 
        .prdata_o_1_iv_0_11_2(prdata_o_1_iv_0_11_2), 
        .prdata_o_1_iv_0_11_3(prdata_o_1_iv_0_11_3), 
        .prdata_o_1_iv_0_12_0(prdata_o_1_iv_0_12_0), 
        .prdata_o_1_iv_0_12_2(prdata_o_1_iv_0_12_2), 
        .prdata_o_1_iv_0_10({prdata_o_1_iv_0_10[15], 
        prdata_o_1_iv_0_10[14]}), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15), 
        .prdata_m2_e_5_6(prdata_m2_e_5_6), .prdata_m2_e_5_11(
        prdata_m2_e_5_11), .prdata_m2_e_5_1(prdata_m2_e_5_1), 
        .prdata_N_5_mux_i_3_a0_7_1(prdata_N_5_mux_i_3_a0_7_1), 
        .prdata_o263(prdata_o263), .prdata_o274(prdata_o274), 
        .prdata_m2_e_5_4(prdata_m2_e_5_4), 
        .MC_System_0_AMBA_SLAVE_0_PSELx(MC_System_0_AMBA_SLAVE_0_PSELx)
        , .prdata_m2_e_5_10(prdata_m2_e_5_10), 
        .prdata_N_5_mux_i_3_a0_11(prdata_N_5_mux_i_3_a0_11), 
        .prdata_N_5_mux_i_3_a0_10(prdata_N_5_mux_i_3_a0_10), 
        .prdata_N_5_mux_i_3_a0_4(prdata_N_5_mux_i_3_a0_4), 
        .prdata_N_5_mux_i_3_a0_0(prdata_N_5_mux_i_3_a0_0), 
        .prdata_N_5_mux_i_3_a0_12(prdata_N_5_mux_i_3_a0_12), 
        .prdata_N_5_mux_i_2_a0_11(prdata_N_5_mux_i_2_a0_11), 
        .prdata_N_5_mux_i_2_a0_10(prdata_N_5_mux_i_2_a0_10), 
        .prdata_N_5_mux_i_2_a0_4(prdata_N_5_mux_i_2_a0_4), 
        .prdata_N_5_mux_i_2_a0_0(prdata_N_5_mux_i_2_a0_0), 
        .prdata_N_5_mux_i_2_a0_12(prdata_N_5_mux_i_2_a0_12), 
        .prdata_m2_0_a2_1_0(prdata_m2_0_a2_1_0), .prdata_m2_0_a2_17_0(
        prdata_m2_0_a2_17_0), .N_358(N_358), .prdata_m2_e_5_6_1(
        prdata_m2_e_5_6_1), .prdata_N_5_mux_i_1_a0_13(
        prdata_N_5_mux_i_1_a0_13), .prdata_N_5_mux_i_1_a0_12(
        prdata_N_5_mux_i_1_a0_12), .prdata_o277(prdata_o277), 
        .prdata_o267(prdata_o267), .N_296(N_296), .prdata_o259(
        prdata_o259), .N_225(N_225), .prdata_o270(prdata_o270), .N_283(
        N_283), .N_286(N_286), .prdata_o260(prdata_o260), 
        .prdata_m2_e_0_9(prdata_m2_e_0_9), .prdata_m2_e_0_10(
        prdata_m2_e_0_10), .prdata_m2_e_0_8(prdata_m2_e_0_8), 
        .prdata_m2_e_27_11(prdata_m2_e_27_11), .prdata_m2_e_27_12(
        prdata_m2_e_27_12), .prdata_m2_e_27_10(prdata_m2_e_27_10), 
        .prdata_N_5_mux_i_4_a0_12(prdata_N_5_mux_i_4_a0_12), 
        .prdata_N_5_mux_i_4_a0_13(prdata_N_5_mux_i_4_a0_13), 
        .prdata_N_5_mux_i_4_a0_11(prdata_N_5_mux_i_4_a0_11), .m7_i_2(
        m7_i_2), .N_435_4(N_435_4), .N_157(N_157));
    VCC VCC_Z (.Y(VCC));
    CFG2 #( .INIT(4'h1) )  \iPSELS_raw_0_a2_1[0]  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[14]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[13]), .Y(iPSELS_raw_0_a2_1[0]));
    GND GND_Z (.Y(GND));
    
endmodule


module MC_System_sb_CCC_0_FCCC(
       MC_System_0_FIC_0_LOCK,
       MC_System_0_FIC_0_CLK,
       FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
    );
output MC_System_0_FIC_0_LOCK;
output MC_System_0_FIC_0_CLK;
input  FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;

    wire [7:0] PRDATA;
    wire LOCK, GL0_net, Y0, Y1, Y2, Y3, BUSY, VCC, GND, GL1_net_i, GL2, 
        GL3;
    
    VCC VCC_Z (.Y(VCC));
    CLKINT GL0_INST (.A(GL0_net), .Y(MC_System_0_FIC_0_CLK));
    CCC #( .INIT(210'h0000007FB8000044D64000318C6307C1F18C61EC0404040400301)
        , .VCOFREQUENCY(800.000000) )  CCC_INST (.Y0(Y0), .Y1(Y1), .Y2(
        Y2), .Y3(Y3), .PRDATA({PRDATA[7], PRDATA[6], PRDATA[5], 
        PRDATA[4], PRDATA[3], PRDATA[2], PRDATA[1], PRDATA[0]}), .LOCK(
        LOCK), .BUSY(BUSY), .CLK0(VCC), .CLK1(VCC), .CLK2(VCC), .CLK3(
        VCC), .NGMUX0_SEL(GND), .NGMUX1_SEL(GND), .NGMUX2_SEL(GND), 
        .NGMUX3_SEL(GND), .NGMUX0_HOLD_N(VCC), .NGMUX1_HOLD_N(VCC), 
        .NGMUX2_HOLD_N(VCC), .NGMUX3_HOLD_N(VCC), .NGMUX0_ARST_N(VCC), 
        .NGMUX1_ARST_N(VCC), .NGMUX2_ARST_N(VCC), .NGMUX3_ARST_N(VCC), 
        .PLL_BYPASS_N(VCC), .PLL_ARST_N(VCC), .PLL_POWERDOWN_N(VCC), 
        .GPD0_ARST_N(VCC), .GPD1_ARST_N(VCC), .GPD2_ARST_N(VCC), 
        .GPD3_ARST_N(VCC), .PRESET_N(GND), .PCLK(VCC), .PSEL(VCC), 
        .PENABLE(VCC), .PWRITE(VCC), .PADDR({VCC, VCC, VCC, VCC, VCC, 
        VCC}), .PWDATA({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}), 
        .CLK0_PAD(GND), .CLK1_PAD(GND), .CLK2_PAD(GND), .CLK3_PAD(GND), 
        .GL0(GL0_net), .GL1(GL1_net_i), .GL2(GL2), .GL3(GL3), 
        .RCOSC_25_50MHZ(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC), 
        .RCOSC_1MHZ(GND), .XTLOSC(GND));
    GND GND_Z (.Y(GND));
    CLKINT CCC_INST_RNI2QPF (.A(LOCK), .Y(MC_System_0_FIC_0_LOCK));
    
endmodule


module MC_System_sb_MSS(
       USB_ULPI_DATA,
       MC_System_0_AMBA_SLAVE_0_PADDR_0,
       MC_System_0_AMBA_SLAVE_0_PADDR_1,
       MC_System_0_AMBA_SLAVE_0_PADDR_2,
       MC_System_0_AMBA_SLAVE_0_PADDR_3,
       MC_System_0_AMBA_SLAVE_0_PADDR_4,
       MC_System_0_AMBA_SLAVE_0_PADDR_5,
       MC_System_0_AMBA_SLAVE_0_PADDR_6,
       MC_System_0_AMBA_SLAVE_0_PADDR_7,
       MC_System_0_AMBA_SLAVE_0_PADDR_8,
       MC_System_0_AMBA_SLAVE_0_PADDR_9,
       MC_System_0_AMBA_SLAVE_0_PADDR_10,
       MC_System_0_AMBA_SLAVE_0_PADDR_11,
       MC_System_0_AMBA_SLAVE_0_PADDR_12,
       MC_System_0_AMBA_SLAVE_0_PADDR_13,
       MC_System_0_AMBA_SLAVE_0_PADDR_14,
       MC_System_0_AMBA_SLAVE_0_PADDR_15,
       MC_System_0_AMBA_SLAVE_0_PWDATA_0,
       MC_System_0_AMBA_SLAVE_0_PWDATA_1,
       MC_System_0_AMBA_SLAVE_0_PWDATA_2,
       MC_System_0_AMBA_SLAVE_0_PWDATA_3,
       MC_System_0_AMBA_SLAVE_0_PWDATA_4,
       MC_System_0_AMBA_SLAVE_0_PWDATA_5,
       MC_System_0_AMBA_SLAVE_0_PWDATA_6,
       MC_System_0_AMBA_SLAVE_0_PWDATA_7,
       MC_System_0_AMBA_SLAVE_0_PWDATA_8,
       MC_System_0_AMBA_SLAVE_0_PWDATA_9,
       MC_System_0_AMBA_SLAVE_0_PWDATA_10,
       MC_System_0_AMBA_SLAVE_0_PWDATA_11,
       MC_System_0_AMBA_SLAVE_0_PWDATA_12,
       MC_System_0_AMBA_SLAVE_0_PWDATA_13,
       MC_System_0_AMBA_SLAVE_0_PWDATA_14,
       MC_System_0_AMBA_SLAVE_0_PWDATA_15,
       MC_System_0_AMBA_SLAVE_0_PWDATA_16,
       MC_System_0_AMBA_SLAVE_0_PWDATA_17,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31,
       USB_ULPI_XCLK,
       USB_ULPI_STP,
       USB_ULPI_NXT,
       USB_ULPI_DIR,
       MC_System_0_AMBA_SLAVE_0_PENABLE,
       MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx,
       MC_System_0_AMBA_SLAVE_0_PWRITE,
       GPIO_0_M2F_c,
       MC_System_0_FIC_0_LOCK,
       MC_System_0_FIC_0_CLK
    );
inout  [7:0] USB_ULPI_DATA;
output MC_System_0_AMBA_SLAVE_0_PADDR_0;
output MC_System_0_AMBA_SLAVE_0_PADDR_1;
output MC_System_0_AMBA_SLAVE_0_PADDR_2;
output MC_System_0_AMBA_SLAVE_0_PADDR_3;
output MC_System_0_AMBA_SLAVE_0_PADDR_4;
output MC_System_0_AMBA_SLAVE_0_PADDR_5;
output MC_System_0_AMBA_SLAVE_0_PADDR_6;
output MC_System_0_AMBA_SLAVE_0_PADDR_7;
output MC_System_0_AMBA_SLAVE_0_PADDR_8;
output MC_System_0_AMBA_SLAVE_0_PADDR_9;
output MC_System_0_AMBA_SLAVE_0_PADDR_10;
output MC_System_0_AMBA_SLAVE_0_PADDR_11;
output MC_System_0_AMBA_SLAVE_0_PADDR_12;
output MC_System_0_AMBA_SLAVE_0_PADDR_13;
output MC_System_0_AMBA_SLAVE_0_PADDR_14;
output MC_System_0_AMBA_SLAVE_0_PADDR_15;
output MC_System_0_AMBA_SLAVE_0_PWDATA_0;
output MC_System_0_AMBA_SLAVE_0_PWDATA_1;
output MC_System_0_AMBA_SLAVE_0_PWDATA_2;
output MC_System_0_AMBA_SLAVE_0_PWDATA_3;
output MC_System_0_AMBA_SLAVE_0_PWDATA_4;
output MC_System_0_AMBA_SLAVE_0_PWDATA_5;
output MC_System_0_AMBA_SLAVE_0_PWDATA_6;
output MC_System_0_AMBA_SLAVE_0_PWDATA_7;
output MC_System_0_AMBA_SLAVE_0_PWDATA_8;
output MC_System_0_AMBA_SLAVE_0_PWDATA_9;
output MC_System_0_AMBA_SLAVE_0_PWDATA_10;
output MC_System_0_AMBA_SLAVE_0_PWDATA_11;
output MC_System_0_AMBA_SLAVE_0_PWDATA_12;
output MC_System_0_AMBA_SLAVE_0_PWDATA_13;
output MC_System_0_AMBA_SLAVE_0_PWDATA_14;
output MC_System_0_AMBA_SLAVE_0_PWDATA_15;
output MC_System_0_AMBA_SLAVE_0_PWDATA_16;
output MC_System_0_AMBA_SLAVE_0_PWDATA_17;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17;
input  MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31;
input  USB_ULPI_XCLK;
output USB_ULPI_STP;
input  USB_ULPI_NXT;
input  USB_ULPI_DIR;
output MC_System_0_AMBA_SLAVE_0_PENABLE;
output MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx;
output MC_System_0_AMBA_SLAVE_0_PWRITE;
output GPIO_0_M2F_c;
input  MC_System_0_FIC_0_LOCK;
input  MC_System_0_FIC_0_CLK;

    wire [7:0] EDAC_ERROR;
    wire [31:0] F_FM0_RDATA;
    wire [31:16] MC_System_0_AMBA_SLAVE_0_PADDR;
    wire [1:0] F_HM0_SIZE;
    wire [31:18] MC_System_0_AMBA_SLAVE_0_PWDATA;
    wire [1:0] FAB_OPMODE;
    wire [3:0] FAB_VCONTROL;
    wire [1:0] FAB_XCVRSEL;
    wire [7:0] FAB_XDATAOUT;
    wire [1:0] FIC32_0_MASTER;
    wire [1:0] FIC32_1_MASTER;
    wire [15:0] H2F_INTERRUPT;
    wire [15:2] PER2_FABRIC_PADDR;
    wire [31:0] PER2_FABRIC_PWDATA;
    wire [9:0] TCGF;
    wire [3:0] TRACEDATA;
    wire [3:0] TXD_RIF;
    wire [7:0] TXDF;
    wire [3:0] F_BID;
    wire [1:0] F_BRESP_HRESP0;
    wire [63:0] F_RDATA_HRDATA01;
    wire [3:0] F_RID;
    wire [1:0] F_RRESP_HRESP1;
    wire [15:0] MDDR_FABRIC_PRDATA;
    wire [15:0] DRAM_ADDR;
    wire [2:0] DRAM_BA;
    wire [2:0] DRAM_DM_RDQS_OUT;
    wire [17:0] DRAM_DQ_OUT;
    wire [2:0] DRAM_DQS_OUT;
    wire [1:0] DRAM_FIFO_WE_OUT;
    wire [2:0] DM_OE;
    wire [17:0] DRAM_DQ_OE;
    wire [2:0] DRAM_DQS_OE;
    wire USB_ULPI_XCLK_PAD_Y, 
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OUT, 
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OE, 
        USB_ULPI_NXT_PAD_Y, USB_ULPI_DIR_PAD_Y, USB_ULPI_DATA_7_PAD_Y, 
        MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT, 
        MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE, 
        USB_ULPI_DATA_6_PAD_Y, 
        MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OUT, 
        MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OE, USB_ULPI_DATA_5_PAD_Y, 
        MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OUT, 
        MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OE, USB_ULPI_DATA_4_PAD_Y, 
        MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OUT, 
        MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OE, USB_ULPI_DATA_3_PAD_Y, 
        MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT, 
        MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE, 
        USB_ULPI_DATA_2_PAD_Y, 
        MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT, 
        MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE, 
        USB_ULPI_DATA_1_PAD_Y, 
        MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT, 
        MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE, 
        USB_ULPI_DATA_0_PAD_Y, 
        MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT, 
        MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE, 
        CAN_RXBUS_MGPIO3A_H2F_A, CAN_RXBUS_MGPIO3A_H2F_B, 
        CAN_TX_EBL_MGPIO4A_H2F_A, CAN_TX_EBL_MGPIO4A_H2F_B, 
        CAN_TXBUS_MGPIO2A_H2F_A, CAN_TXBUS_MGPIO2A_H2F_B, 
        CLK_CONFIG_APB, COMMS_INT, 
        MC_System_sb_MSS_TMP_0_FIC_2_APB_M_PRESET_N, F_FM0_READYOUT, 
        F_FM0_RESP, F_HM0_TRANS1, FAB_CHRGVBUS, FAB_DISCHRGVBUS, 
        FAB_DMPULLDOWN, FAB_DPPULLDOWN, FAB_DRVVBUS, FAB_IDPULLUP, 
        FAB_SUSPENDM, FAB_TERMSEL, FAB_TXVALID, FAB_VCONTROLLOADM, 
        FACC_GLMUX_SEL, MC_System_sb_MSS_TMP_0_MSS_RESET_N_M2F, 
        GTX_CLK, H2F_NMI, H2FCALIB, I2C0_SCL_MGPIO31B_H2F_A, 
        I2C0_SCL_MGPIO31B_H2F_B, I2C0_SDA_MGPIO30B_H2F_A, 
        I2C0_SDA_MGPIO30B_H2F_B, I2C1_SCL_MGPIO1A_H2F_A, 
        I2C1_SCL_MGPIO1A_H2F_B, I2C1_SDA_MGPIO0A_H2F_A, MDCF, MDOENF, 
        MDOF, MMUART0_CTS_MGPIO19B_H2F_A, MMUART0_CTS_MGPIO19B_H2F_B, 
        MMUART0_DCD_MGPIO22B_H2F_A, MMUART0_DCD_MGPIO22B_H2F_B, 
        MMUART0_DSR_MGPIO20B_H2F_A, MMUART0_DSR_MGPIO20B_H2F_B, 
        MMUART0_DTR_MGPIO18B_H2F_A, MMUART0_DTR_MGPIO18B_H2F_B, 
        MMUART0_RI_MGPIO21B_H2F_A, MMUART0_RI_MGPIO21B_H2F_B, 
        MMUART0_RTS_MGPIO17B_H2F_A, MMUART0_RTS_MGPIO17B_H2F_B, 
        MMUART0_RXD_MGPIO28B_H2F_A, MMUART0_RXD_MGPIO28B_H2F_B, 
        MMUART0_SCK_MGPIO29B_H2F_A, MMUART0_SCK_MGPIO29B_H2F_B, 
        MMUART0_TXD_MGPIO27B_H2F_A, MMUART0_TXD_MGPIO27B_H2F_B, 
        MMUART1_DTR_MGPIO12B_H2F_A, MMUART1_RTS_MGPIO11B_H2F_A, 
        MMUART1_RTS_MGPIO11B_H2F_B, MMUART1_RXD_MGPIO26B_H2F_A, 
        MMUART1_RXD_MGPIO26B_H2F_B, MMUART1_SCK_MGPIO25B_H2F_A, 
        MMUART1_SCK_MGPIO25B_H2F_B, MMUART1_TXD_MGPIO24B_H2F_A, 
        MMUART1_TXD_MGPIO24B_H2F_B, MPLL_LOCK, PER2_FABRIC_PENABLE, 
        PER2_FABRIC_PSEL, PER2_FABRIC_PWRITE, RTC_MATCH, SLEEPDEEP, 
        SLEEPHOLDACK, SLEEPING, SMBALERT_NO0, SMBALERT_NO1, SMBSUS_NO0, 
        SMBSUS_NO1, SPI0_CLK_OUT, SPI0_SDI_MGPIO5A_H2F_A, 
        SPI0_SDI_MGPIO5A_H2F_B, SPI0_SDO_MGPIO6A_H2F_A, 
        SPI0_SDO_MGPIO6A_H2F_B, SPI0_SS0_MGPIO7A_H2F_A, 
        SPI0_SS0_MGPIO7A_H2F_B, SPI0_SS1_MGPIO8A_H2F_A, 
        SPI0_SS1_MGPIO8A_H2F_B, SPI0_SS2_MGPIO9A_H2F_A, 
        SPI0_SS2_MGPIO9A_H2F_B, SPI0_SS3_MGPIO10A_H2F_A, 
        SPI0_SS3_MGPIO10A_H2F_B, SPI0_SS4_MGPIO19A_H2F_A, 
        SPI0_SS5_MGPIO20A_H2F_A, SPI0_SS6_MGPIO21A_H2F_A, 
        SPI0_SS7_MGPIO22A_H2F_A, SPI1_CLK_OUT, SPI1_SDI_MGPIO11A_H2F_A, 
        SPI1_SDI_MGPIO11A_H2F_B, SPI1_SDO_MGPIO12A_H2F_A, 
        SPI1_SDO_MGPIO12A_H2F_B, SPI1_SS0_MGPIO13A_H2F_A, 
        SPI1_SS0_MGPIO13A_H2F_B, SPI1_SS1_MGPIO14A_H2F_A, 
        SPI1_SS1_MGPIO14A_H2F_B, SPI1_SS2_MGPIO15A_H2F_A, 
        SPI1_SS2_MGPIO15A_H2F_B, SPI1_SS3_MGPIO16A_H2F_A, 
        SPI1_SS3_MGPIO16A_H2F_B, SPI1_SS4_MGPIO17A_H2F_A, 
        SPI1_SS5_MGPIO18A_H2F_A, SPI1_SS6_MGPIO23A_H2F_A, 
        SPI1_SS7_MGPIO24A_H2F_A, TRACECLK, TX_CLK, TX_ENF, TX_ERRF, 
        TXCTL_EN_RIF, TXEV, WDOGTIMEOUT, F_ARREADY_HREADYOUT1, 
        F_AWREADY_HREADYOUT0, F_BVALID, F_RLAST, F_RVALID, F_WREADY, 
        MDDR_FABRIC_PREADY, MDDR_FABRIC_PSLVERR, VCC, GND, 
        CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT, 
        CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT, 
        CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT, DRAM_CASN, DRAM_CKE, 
        DRAM_CLK, DRAM_CSN, DRAM_ODT, DRAM_RASN, DRAM_RSTN, DRAM_WEN, 
        I2C0_SCL_USBC_DATA1_MGPIO31B_OUT, 
        I2C0_SDA_USBC_DATA0_MGPIO30B_OUT, 
        I2C1_SCL_USBA_DATA4_MGPIO1A_OUT, 
        I2C1_SDA_USBA_DATA3_MGPIO0A_OUT, 
        MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT, MMUART0_DCD_MGPIO22B_OUT, 
        MMUART0_DSR_MGPIO20B_OUT, MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT, 
        MMUART0_RI_MGPIO21B_OUT, MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT, 
        MMUART0_RXD_USBC_STP_MGPIO28B_OUT, 
        MMUART0_SCK_USBC_NXT_MGPIO29B_OUT, 
        MMUART0_TXD_USBC_DIR_MGPIO27B_OUT, 
        MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT, 
        MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT, 
        MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT, 
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT, RGMII_MDC_RMII_MDC_OUT, 
        RGMII_RX_CLK_OUT, RGMII_TX_CLK_OUT, 
        RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT, 
        RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT, SPI0_SCK_USBA_XCLK_OUT, 
        SPI0_SDI_USBA_DIR_MGPIO5A_OUT, SPI0_SDO_USBA_STP_MGPIO6A_OUT, 
        SPI0_SS0_USBA_NXT_MGPIO7A_OUT, SPI0_SS1_USBA_DATA5_MGPIO8A_OUT, 
        SPI0_SS2_USBA_DATA6_MGPIO9A_OUT, 
        SPI0_SS3_USBA_DATA7_MGPIO10A_OUT, SPI1_SCK_OUT, 
        SPI1_SDI_MGPIO11A_OUT, SPI1_SDO_MGPIO12A_OUT, 
        SPI1_SS0_MGPIO13A_OUT, SPI1_SS1_MGPIO14A_OUT, 
        SPI1_SS2_MGPIO15A_OUT, SPI1_SS3_MGPIO16A_OUT, 
        SPI1_SS4_MGPIO17A_OUT, SPI1_SS5_MGPIO18A_OUT, 
        SPI1_SS6_MGPIO23A_OUT, SPI1_SS7_MGPIO24A_OUT, USBC_XCLK_OUT, 
        CAN_RXBUS_USBA_DATA1_MGPIO3A_OE, 
        CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE, 
        CAN_TXBUS_USBA_DATA0_MGPIO2A_OE, 
        I2C0_SCL_USBC_DATA1_MGPIO31B_OE, 
        I2C0_SDA_USBC_DATA0_MGPIO30B_OE, 
        I2C1_SCL_USBA_DATA4_MGPIO1A_OE, I2C1_SDA_USBA_DATA3_MGPIO0A_OE, 
        MMUART0_CTS_USBC_DATA7_MGPIO19B_OE, MMUART0_DCD_MGPIO22B_OE, 
        MMUART0_DSR_MGPIO20B_OE, MMUART0_DTR_USBC_DATA6_MGPIO18B_OE, 
        MMUART0_RI_MGPIO21B_OE, MMUART0_RTS_USBC_DATA5_MGPIO17B_OE, 
        MMUART0_RXD_USBC_STP_MGPIO28B_OE, 
        MMUART0_SCK_USBC_NXT_MGPIO29B_OE, 
        MMUART0_TXD_USBC_DIR_MGPIO27B_OE, 
        MMUART1_RXD_USBC_DATA3_MGPIO26B_OE, 
        MMUART1_SCK_USBC_DATA4_MGPIO25B_OE, 
        MMUART1_TXD_USBC_DATA2_MGPIO24B_OE, 
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE, RGMII_MDC_RMII_MDC_OE, 
        RGMII_RX_CLK_OE, RGMII_TX_CLK_OE, 
        RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE, 
        RGMII_TXD0_RMII_TXD0_USBB_DIR_OE, SPI0_SCK_USBA_XCLK_OE, 
        SPI0_SDI_USBA_DIR_MGPIO5A_OE, SPI0_SDO_USBA_STP_MGPIO6A_OE, 
        SPI0_SS0_USBA_NXT_MGPIO7A_OE, SPI0_SS1_USBA_DATA5_MGPIO8A_OE, 
        SPI0_SS2_USBA_DATA6_MGPIO9A_OE, 
        SPI0_SS3_USBA_DATA7_MGPIO10A_OE, SPI1_SCK_OE, 
        SPI1_SDI_MGPIO11A_OE, SPI1_SDO_MGPIO12A_OE, 
        SPI1_SS0_MGPIO13A_OE, SPI1_SS1_MGPIO14A_OE, 
        SPI1_SS2_MGPIO15A_OE, SPI1_SS3_MGPIO16A_OE, 
        SPI1_SS4_MGPIO17A_OE, SPI1_SS5_MGPIO18A_OE, 
        SPI1_SS6_MGPIO23A_OE, SPI1_SS7_MGPIO24A_OE, USBC_XCLK_OE;
    
    BIBUF #( .IOSTD("") )  USB_ULPI_DATA_5_PAD (.PAD(USB_ULPI_DATA[5]), 
        .D(MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OUT), .E(
        MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OE), .Y(
        USB_ULPI_DATA_5_PAD_Y));
    BIBUF #( .IOSTD("") )  USB_ULPI_DATA_4_PAD (.PAD(USB_ULPI_DATA[4]), 
        .D(MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OUT), .E(
        MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OE), .Y(
        USB_ULPI_DATA_4_PAD_Y));
    BIBUF #( .IOSTD("") )  USB_ULPI_DATA_7_PAD (.PAD(USB_ULPI_DATA[7]), 
        .D(MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT), .E(
        MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE), .Y(
        USB_ULPI_DATA_7_PAD_Y));
    BIBUF #( .IOSTD("") )  USB_ULPI_DATA_3_PAD (.PAD(USB_ULPI_DATA[3]), 
        .D(MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT), .E(
        MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE), .Y(
        USB_ULPI_DATA_3_PAD_Y));
    INBUF #( .IOSTD("") )  USB_ULPI_NXT_PAD (.PAD(USB_ULPI_NXT), .Y(
        USB_ULPI_NXT_PAD_Y));
    GND GND_Z (.Y(GND));
    INBUF #( .IOSTD("") )  USB_ULPI_XCLK_PAD (.PAD(USB_ULPI_XCLK), .Y(
        USB_ULPI_XCLK_PAD_Y));
    BIBUF #( .IOSTD("") )  USB_ULPI_DATA_6_PAD (.PAD(USB_ULPI_DATA[6]), 
        .D(MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OUT), .E(
        MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OE), .Y(
        USB_ULPI_DATA_6_PAD_Y));
    BIBUF #( .IOSTD("") )  USB_ULPI_DATA_2_PAD (.PAD(USB_ULPI_DATA[2]), 
        .D(MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT), .E(
        MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE), .Y(
        USB_ULPI_DATA_2_PAD_Y));
    INBUF #( .IOSTD("") )  USB_ULPI_DIR_PAD (.PAD(USB_ULPI_DIR), .Y(
        USB_ULPI_DIR_PAD_Y));
    MSS_010 #( .INIT(1438'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000120481204812048120D8120D8120E00000000F000000000000000000000000000000007FFFFFFFB000001007C33C000000006092C0104003FFFFE4000000000001100000000F0F01C00000182CFFC010842108421000001FE34001FF8000000400000000020091007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
        , .ACT_UBITS(56'b11111111111111111111111111111111111111111111111111111111)
        , .MEMORYFILE("ENVM_init.mem"), .RTC_MAIN_XTL_FREQ(0.000000), .RTC_MAIN_XTL_MODE("")
        , .DDR_CLK_FREQ(0.000000) )  MSS_ADLIB_INST (
        .CAN_RXBUS_MGPIO3A_H2F_A(CAN_RXBUS_MGPIO3A_H2F_A), 
        .CAN_RXBUS_MGPIO3A_H2F_B(CAN_RXBUS_MGPIO3A_H2F_B), 
        .CAN_TX_EBL_MGPIO4A_H2F_A(CAN_TX_EBL_MGPIO4A_H2F_A), 
        .CAN_TX_EBL_MGPIO4A_H2F_B(CAN_TX_EBL_MGPIO4A_H2F_B), 
        .CAN_TXBUS_MGPIO2A_H2F_A(CAN_TXBUS_MGPIO2A_H2F_A), 
        .CAN_TXBUS_MGPIO2A_H2F_B(CAN_TXBUS_MGPIO2A_H2F_B), 
        .CLK_CONFIG_APB(CLK_CONFIG_APB), .COMMS_INT(COMMS_INT), 
        .CONFIG_PRESET_N(MC_System_sb_MSS_TMP_0_FIC_2_APB_M_PRESET_N), 
        .EDAC_ERROR({EDAC_ERROR[7], EDAC_ERROR[6], EDAC_ERROR[5], 
        EDAC_ERROR[4], EDAC_ERROR[3], EDAC_ERROR[2], EDAC_ERROR[1], 
        EDAC_ERROR[0]}), .F_FM0_RDATA({F_FM0_RDATA[31], 
        F_FM0_RDATA[30], F_FM0_RDATA[29], F_FM0_RDATA[28], 
        F_FM0_RDATA[27], F_FM0_RDATA[26], F_FM0_RDATA[25], 
        F_FM0_RDATA[24], F_FM0_RDATA[23], F_FM0_RDATA[22], 
        F_FM0_RDATA[21], F_FM0_RDATA[20], F_FM0_RDATA[19], 
        F_FM0_RDATA[18], F_FM0_RDATA[17], F_FM0_RDATA[16], 
        F_FM0_RDATA[15], F_FM0_RDATA[14], F_FM0_RDATA[13], 
        F_FM0_RDATA[12], F_FM0_RDATA[11], F_FM0_RDATA[10], 
        F_FM0_RDATA[9], F_FM0_RDATA[8], F_FM0_RDATA[7], F_FM0_RDATA[6], 
        F_FM0_RDATA[5], F_FM0_RDATA[4], F_FM0_RDATA[3], F_FM0_RDATA[2], 
        F_FM0_RDATA[1], F_FM0_RDATA[0]}), .F_FM0_READYOUT(
        F_FM0_READYOUT), .F_FM0_RESP(F_FM0_RESP), .F_HM0_ADDR({
        MC_System_0_AMBA_SLAVE_0_PADDR[31], 
        MC_System_0_AMBA_SLAVE_0_PADDR[30], 
        MC_System_0_AMBA_SLAVE_0_PADDR[29], 
        MC_System_0_AMBA_SLAVE_0_PADDR[28], 
        MC_System_0_AMBA_SLAVE_0_PADDR[27], 
        MC_System_0_AMBA_SLAVE_0_PADDR[26], 
        MC_System_0_AMBA_SLAVE_0_PADDR[25], 
        MC_System_0_AMBA_SLAVE_0_PADDR[24], 
        MC_System_0_AMBA_SLAVE_0_PADDR[23], 
        MC_System_0_AMBA_SLAVE_0_PADDR[22], 
        MC_System_0_AMBA_SLAVE_0_PADDR[21], 
        MC_System_0_AMBA_SLAVE_0_PADDR[20], 
        MC_System_0_AMBA_SLAVE_0_PADDR[19], 
        MC_System_0_AMBA_SLAVE_0_PADDR[18], 
        MC_System_0_AMBA_SLAVE_0_PADDR[17], 
        MC_System_0_AMBA_SLAVE_0_PADDR[16], 
        MC_System_0_AMBA_SLAVE_0_PADDR_15, 
        MC_System_0_AMBA_SLAVE_0_PADDR_14, 
        MC_System_0_AMBA_SLAVE_0_PADDR_13, 
        MC_System_0_AMBA_SLAVE_0_PADDR_12, 
        MC_System_0_AMBA_SLAVE_0_PADDR_11, 
        MC_System_0_AMBA_SLAVE_0_PADDR_10, 
        MC_System_0_AMBA_SLAVE_0_PADDR_9, 
        MC_System_0_AMBA_SLAVE_0_PADDR_8, 
        MC_System_0_AMBA_SLAVE_0_PADDR_7, 
        MC_System_0_AMBA_SLAVE_0_PADDR_6, 
        MC_System_0_AMBA_SLAVE_0_PADDR_5, 
        MC_System_0_AMBA_SLAVE_0_PADDR_4, 
        MC_System_0_AMBA_SLAVE_0_PADDR_3, 
        MC_System_0_AMBA_SLAVE_0_PADDR_2, 
        MC_System_0_AMBA_SLAVE_0_PADDR_1, 
        MC_System_0_AMBA_SLAVE_0_PADDR_0}), .F_HM0_ENABLE(
        MC_System_0_AMBA_SLAVE_0_PENABLE), .F_HM0_SEL(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx), .F_HM0_SIZE({
        F_HM0_SIZE[1], F_HM0_SIZE[0]}), .F_HM0_TRANS1(F_HM0_TRANS1), 
        .F_HM0_WDATA({MC_System_0_AMBA_SLAVE_0_PWDATA[31], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[30], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[29], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[28], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[27], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[26], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[25], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[24], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[23], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[22], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[21], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[20], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[19], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[18], 
        MC_System_0_AMBA_SLAVE_0_PWDATA_17, 
        MC_System_0_AMBA_SLAVE_0_PWDATA_16, 
        MC_System_0_AMBA_SLAVE_0_PWDATA_15, 
        MC_System_0_AMBA_SLAVE_0_PWDATA_14, 
        MC_System_0_AMBA_SLAVE_0_PWDATA_13, 
        MC_System_0_AMBA_SLAVE_0_PWDATA_12, 
        MC_System_0_AMBA_SLAVE_0_PWDATA_11, 
        MC_System_0_AMBA_SLAVE_0_PWDATA_10, 
        MC_System_0_AMBA_SLAVE_0_PWDATA_9, 
        MC_System_0_AMBA_SLAVE_0_PWDATA_8, 
        MC_System_0_AMBA_SLAVE_0_PWDATA_7, 
        MC_System_0_AMBA_SLAVE_0_PWDATA_6, 
        MC_System_0_AMBA_SLAVE_0_PWDATA_5, 
        MC_System_0_AMBA_SLAVE_0_PWDATA_4, 
        MC_System_0_AMBA_SLAVE_0_PWDATA_3, 
        MC_System_0_AMBA_SLAVE_0_PWDATA_2, 
        MC_System_0_AMBA_SLAVE_0_PWDATA_1, 
        MC_System_0_AMBA_SLAVE_0_PWDATA_0}), .F_HM0_WRITE(
        MC_System_0_AMBA_SLAVE_0_PWRITE), .FAB_CHRGVBUS(FAB_CHRGVBUS), 
        .FAB_DISCHRGVBUS(FAB_DISCHRGVBUS), .FAB_DMPULLDOWN(
        FAB_DMPULLDOWN), .FAB_DPPULLDOWN(FAB_DPPULLDOWN), .FAB_DRVVBUS(
        FAB_DRVVBUS), .FAB_IDPULLUP(FAB_IDPULLUP), .FAB_OPMODE({
        FAB_OPMODE[1], FAB_OPMODE[0]}), .FAB_SUSPENDM(FAB_SUSPENDM), 
        .FAB_TERMSEL(FAB_TERMSEL), .FAB_TXVALID(FAB_TXVALID), 
        .FAB_VCONTROL({FAB_VCONTROL[3], FAB_VCONTROL[2], 
        FAB_VCONTROL[1], FAB_VCONTROL[0]}), .FAB_VCONTROLLOADM(
        FAB_VCONTROLLOADM), .FAB_XCVRSEL({FAB_XCVRSEL[1], 
        FAB_XCVRSEL[0]}), .FAB_XDATAOUT({FAB_XDATAOUT[7], 
        FAB_XDATAOUT[6], FAB_XDATAOUT[5], FAB_XDATAOUT[4], 
        FAB_XDATAOUT[3], FAB_XDATAOUT[2], FAB_XDATAOUT[1], 
        FAB_XDATAOUT[0]}), .FACC_GLMUX_SEL(FACC_GLMUX_SEL), 
        .FIC32_0_MASTER({FIC32_0_MASTER[1], FIC32_0_MASTER[0]}), 
        .FIC32_1_MASTER({FIC32_1_MASTER[1], FIC32_1_MASTER[0]}), 
        .FPGA_RESET_N(MC_System_sb_MSS_TMP_0_MSS_RESET_N_M2F), 
        .GTX_CLK(GTX_CLK), .H2F_INTERRUPT({H2F_INTERRUPT[15], 
        H2F_INTERRUPT[14], H2F_INTERRUPT[13], H2F_INTERRUPT[12], 
        H2F_INTERRUPT[11], H2F_INTERRUPT[10], H2F_INTERRUPT[9], 
        H2F_INTERRUPT[8], H2F_INTERRUPT[7], H2F_INTERRUPT[6], 
        H2F_INTERRUPT[5], H2F_INTERRUPT[4], H2F_INTERRUPT[3], 
        H2F_INTERRUPT[2], H2F_INTERRUPT[1], H2F_INTERRUPT[0]}), 
        .H2F_NMI(H2F_NMI), .H2FCALIB(H2FCALIB), 
        .I2C0_SCL_MGPIO31B_H2F_A(I2C0_SCL_MGPIO31B_H2F_A), 
        .I2C0_SCL_MGPIO31B_H2F_B(I2C0_SCL_MGPIO31B_H2F_B), 
        .I2C0_SDA_MGPIO30B_H2F_A(I2C0_SDA_MGPIO30B_H2F_A), 
        .I2C0_SDA_MGPIO30B_H2F_B(I2C0_SDA_MGPIO30B_H2F_B), 
        .I2C1_SCL_MGPIO1A_H2F_A(I2C1_SCL_MGPIO1A_H2F_A), 
        .I2C1_SCL_MGPIO1A_H2F_B(I2C1_SCL_MGPIO1A_H2F_B), 
        .I2C1_SDA_MGPIO0A_H2F_A(I2C1_SDA_MGPIO0A_H2F_A), 
        .I2C1_SDA_MGPIO0A_H2F_B(GPIO_0_M2F_c), .MDCF(MDCF), .MDOENF(
        MDOENF), .MDOF(MDOF), .MMUART0_CTS_MGPIO19B_H2F_A(
        MMUART0_CTS_MGPIO19B_H2F_A), .MMUART0_CTS_MGPIO19B_H2F_B(
        MMUART0_CTS_MGPIO19B_H2F_B), .MMUART0_DCD_MGPIO22B_H2F_A(
        MMUART0_DCD_MGPIO22B_H2F_A), .MMUART0_DCD_MGPIO22B_H2F_B(
        MMUART0_DCD_MGPIO22B_H2F_B), .MMUART0_DSR_MGPIO20B_H2F_A(
        MMUART0_DSR_MGPIO20B_H2F_A), .MMUART0_DSR_MGPIO20B_H2F_B(
        MMUART0_DSR_MGPIO20B_H2F_B), .MMUART0_DTR_MGPIO18B_H2F_A(
        MMUART0_DTR_MGPIO18B_H2F_A), .MMUART0_DTR_MGPIO18B_H2F_B(
        MMUART0_DTR_MGPIO18B_H2F_B), .MMUART0_RI_MGPIO21B_H2F_A(
        MMUART0_RI_MGPIO21B_H2F_A), .MMUART0_RI_MGPIO21B_H2F_B(
        MMUART0_RI_MGPIO21B_H2F_B), .MMUART0_RTS_MGPIO17B_H2F_A(
        MMUART0_RTS_MGPIO17B_H2F_A), .MMUART0_RTS_MGPIO17B_H2F_B(
        MMUART0_RTS_MGPIO17B_H2F_B), .MMUART0_RXD_MGPIO28B_H2F_A(
        MMUART0_RXD_MGPIO28B_H2F_A), .MMUART0_RXD_MGPIO28B_H2F_B(
        MMUART0_RXD_MGPIO28B_H2F_B), .MMUART0_SCK_MGPIO29B_H2F_A(
        MMUART0_SCK_MGPIO29B_H2F_A), .MMUART0_SCK_MGPIO29B_H2F_B(
        MMUART0_SCK_MGPIO29B_H2F_B), .MMUART0_TXD_MGPIO27B_H2F_A(
        MMUART0_TXD_MGPIO27B_H2F_A), .MMUART0_TXD_MGPIO27B_H2F_B(
        MMUART0_TXD_MGPIO27B_H2F_B), .MMUART1_DTR_MGPIO12B_H2F_A(
        MMUART1_DTR_MGPIO12B_H2F_A), .MMUART1_RTS_MGPIO11B_H2F_A(
        MMUART1_RTS_MGPIO11B_H2F_A), .MMUART1_RTS_MGPIO11B_H2F_B(
        MMUART1_RTS_MGPIO11B_H2F_B), .MMUART1_RXD_MGPIO26B_H2F_A(
        MMUART1_RXD_MGPIO26B_H2F_A), .MMUART1_RXD_MGPIO26B_H2F_B(
        MMUART1_RXD_MGPIO26B_H2F_B), .MMUART1_SCK_MGPIO25B_H2F_A(
        MMUART1_SCK_MGPIO25B_H2F_A), .MMUART1_SCK_MGPIO25B_H2F_B(
        MMUART1_SCK_MGPIO25B_H2F_B), .MMUART1_TXD_MGPIO24B_H2F_A(
        MMUART1_TXD_MGPIO24B_H2F_A), .MMUART1_TXD_MGPIO24B_H2F_B(
        MMUART1_TXD_MGPIO24B_H2F_B), .MPLL_LOCK(MPLL_LOCK), 
        .PER2_FABRIC_PADDR({PER2_FABRIC_PADDR[15], 
        PER2_FABRIC_PADDR[14], PER2_FABRIC_PADDR[13], 
        PER2_FABRIC_PADDR[12], PER2_FABRIC_PADDR[11], 
        PER2_FABRIC_PADDR[10], PER2_FABRIC_PADDR[9], 
        PER2_FABRIC_PADDR[8], PER2_FABRIC_PADDR[7], 
        PER2_FABRIC_PADDR[6], PER2_FABRIC_PADDR[5], 
        PER2_FABRIC_PADDR[4], PER2_FABRIC_PADDR[3], 
        PER2_FABRIC_PADDR[2]}), .PER2_FABRIC_PENABLE(
        PER2_FABRIC_PENABLE), .PER2_FABRIC_PSEL(PER2_FABRIC_PSEL), 
        .PER2_FABRIC_PWDATA({PER2_FABRIC_PWDATA[31], 
        PER2_FABRIC_PWDATA[30], PER2_FABRIC_PWDATA[29], 
        PER2_FABRIC_PWDATA[28], PER2_FABRIC_PWDATA[27], 
        PER2_FABRIC_PWDATA[26], PER2_FABRIC_PWDATA[25], 
        PER2_FABRIC_PWDATA[24], PER2_FABRIC_PWDATA[23], 
        PER2_FABRIC_PWDATA[22], PER2_FABRIC_PWDATA[21], 
        PER2_FABRIC_PWDATA[20], PER2_FABRIC_PWDATA[19], 
        PER2_FABRIC_PWDATA[18], PER2_FABRIC_PWDATA[17], 
        PER2_FABRIC_PWDATA[16], PER2_FABRIC_PWDATA[15], 
        PER2_FABRIC_PWDATA[14], PER2_FABRIC_PWDATA[13], 
        PER2_FABRIC_PWDATA[12], PER2_FABRIC_PWDATA[11], 
        PER2_FABRIC_PWDATA[10], PER2_FABRIC_PWDATA[9], 
        PER2_FABRIC_PWDATA[8], PER2_FABRIC_PWDATA[7], 
        PER2_FABRIC_PWDATA[6], PER2_FABRIC_PWDATA[5], 
        PER2_FABRIC_PWDATA[4], PER2_FABRIC_PWDATA[3], 
        PER2_FABRIC_PWDATA[2], PER2_FABRIC_PWDATA[1], 
        PER2_FABRIC_PWDATA[0]}), .PER2_FABRIC_PWRITE(
        PER2_FABRIC_PWRITE), .RTC_MATCH(RTC_MATCH), .SLEEPDEEP(
        SLEEPDEEP), .SLEEPHOLDACK(SLEEPHOLDACK), .SLEEPING(SLEEPING), 
        .SMBALERT_NO0(SMBALERT_NO0), .SMBALERT_NO1(SMBALERT_NO1), 
        .SMBSUS_NO0(SMBSUS_NO0), .SMBSUS_NO1(SMBSUS_NO1), 
        .SPI0_CLK_OUT(SPI0_CLK_OUT), .SPI0_SDI_MGPIO5A_H2F_A(
        SPI0_SDI_MGPIO5A_H2F_A), .SPI0_SDI_MGPIO5A_H2F_B(
        SPI0_SDI_MGPIO5A_H2F_B), .SPI0_SDO_MGPIO6A_H2F_A(
        SPI0_SDO_MGPIO6A_H2F_A), .SPI0_SDO_MGPIO6A_H2F_B(
        SPI0_SDO_MGPIO6A_H2F_B), .SPI0_SS0_MGPIO7A_H2F_A(
        SPI0_SS0_MGPIO7A_H2F_A), .SPI0_SS0_MGPIO7A_H2F_B(
        SPI0_SS0_MGPIO7A_H2F_B), .SPI0_SS1_MGPIO8A_H2F_A(
        SPI0_SS1_MGPIO8A_H2F_A), .SPI0_SS1_MGPIO8A_H2F_B(
        SPI0_SS1_MGPIO8A_H2F_B), .SPI0_SS2_MGPIO9A_H2F_A(
        SPI0_SS2_MGPIO9A_H2F_A), .SPI0_SS2_MGPIO9A_H2F_B(
        SPI0_SS2_MGPIO9A_H2F_B), .SPI0_SS3_MGPIO10A_H2F_A(
        SPI0_SS3_MGPIO10A_H2F_A), .SPI0_SS3_MGPIO10A_H2F_B(
        SPI0_SS3_MGPIO10A_H2F_B), .SPI0_SS4_MGPIO19A_H2F_A(
        SPI0_SS4_MGPIO19A_H2F_A), .SPI0_SS5_MGPIO20A_H2F_A(
        SPI0_SS5_MGPIO20A_H2F_A), .SPI0_SS6_MGPIO21A_H2F_A(
        SPI0_SS6_MGPIO21A_H2F_A), .SPI0_SS7_MGPIO22A_H2F_A(
        SPI0_SS7_MGPIO22A_H2F_A), .SPI1_CLK_OUT(SPI1_CLK_OUT), 
        .SPI1_SDI_MGPIO11A_H2F_A(SPI1_SDI_MGPIO11A_H2F_A), 
        .SPI1_SDI_MGPIO11A_H2F_B(SPI1_SDI_MGPIO11A_H2F_B), 
        .SPI1_SDO_MGPIO12A_H2F_A(SPI1_SDO_MGPIO12A_H2F_A), 
        .SPI1_SDO_MGPIO12A_H2F_B(SPI1_SDO_MGPIO12A_H2F_B), 
        .SPI1_SS0_MGPIO13A_H2F_A(SPI1_SS0_MGPIO13A_H2F_A), 
        .SPI1_SS0_MGPIO13A_H2F_B(SPI1_SS0_MGPIO13A_H2F_B), 
        .SPI1_SS1_MGPIO14A_H2F_A(SPI1_SS1_MGPIO14A_H2F_A), 
        .SPI1_SS1_MGPIO14A_H2F_B(SPI1_SS1_MGPIO14A_H2F_B), 
        .SPI1_SS2_MGPIO15A_H2F_A(SPI1_SS2_MGPIO15A_H2F_A), 
        .SPI1_SS2_MGPIO15A_H2F_B(SPI1_SS2_MGPIO15A_H2F_B), 
        .SPI1_SS3_MGPIO16A_H2F_A(SPI1_SS3_MGPIO16A_H2F_A), 
        .SPI1_SS3_MGPIO16A_H2F_B(SPI1_SS3_MGPIO16A_H2F_B), 
        .SPI1_SS4_MGPIO17A_H2F_A(SPI1_SS4_MGPIO17A_H2F_A), 
        .SPI1_SS5_MGPIO18A_H2F_A(SPI1_SS5_MGPIO18A_H2F_A), 
        .SPI1_SS6_MGPIO23A_H2F_A(SPI1_SS6_MGPIO23A_H2F_A), 
        .SPI1_SS7_MGPIO24A_H2F_A(SPI1_SS7_MGPIO24A_H2F_A), .TCGF({
        TCGF[9], TCGF[8], TCGF[7], TCGF[6], TCGF[5], TCGF[4], TCGF[3], 
        TCGF[2], TCGF[1], TCGF[0]}), .TRACECLK(TRACECLK), .TRACEDATA({
        TRACEDATA[3], TRACEDATA[2], TRACEDATA[1], TRACEDATA[0]}), 
        .TX_CLK(TX_CLK), .TX_ENF(TX_ENF), .TX_ERRF(TX_ERRF), 
        .TXCTL_EN_RIF(TXCTL_EN_RIF), .TXD_RIF({TXD_RIF[3], TXD_RIF[2], 
        TXD_RIF[1], TXD_RIF[0]}), .TXDF({TXDF[7], TXDF[6], TXDF[5], 
        TXDF[4], TXDF[3], TXDF[2], TXDF[1], TXDF[0]}), .TXEV(TXEV), 
        .WDOGTIMEOUT(WDOGTIMEOUT), .F_ARREADY_HREADYOUT1(
        F_ARREADY_HREADYOUT1), .F_AWREADY_HREADYOUT0(
        F_AWREADY_HREADYOUT0), .F_BID({F_BID[3], F_BID[2], F_BID[1], 
        F_BID[0]}), .F_BRESP_HRESP0({F_BRESP_HRESP0[1], 
        F_BRESP_HRESP0[0]}), .F_BVALID(F_BVALID), .F_RDATA_HRDATA01({
        F_RDATA_HRDATA01[63], F_RDATA_HRDATA01[62], 
        F_RDATA_HRDATA01[61], F_RDATA_HRDATA01[60], 
        F_RDATA_HRDATA01[59], F_RDATA_HRDATA01[58], 
        F_RDATA_HRDATA01[57], F_RDATA_HRDATA01[56], 
        F_RDATA_HRDATA01[55], F_RDATA_HRDATA01[54], 
        F_RDATA_HRDATA01[53], F_RDATA_HRDATA01[52], 
        F_RDATA_HRDATA01[51], F_RDATA_HRDATA01[50], 
        F_RDATA_HRDATA01[49], F_RDATA_HRDATA01[48], 
        F_RDATA_HRDATA01[47], F_RDATA_HRDATA01[46], 
        F_RDATA_HRDATA01[45], F_RDATA_HRDATA01[44], 
        F_RDATA_HRDATA01[43], F_RDATA_HRDATA01[42], 
        F_RDATA_HRDATA01[41], F_RDATA_HRDATA01[40], 
        F_RDATA_HRDATA01[39], F_RDATA_HRDATA01[38], 
        F_RDATA_HRDATA01[37], F_RDATA_HRDATA01[36], 
        F_RDATA_HRDATA01[35], F_RDATA_HRDATA01[34], 
        F_RDATA_HRDATA01[33], F_RDATA_HRDATA01[32], 
        F_RDATA_HRDATA01[31], F_RDATA_HRDATA01[30], 
        F_RDATA_HRDATA01[29], F_RDATA_HRDATA01[28], 
        F_RDATA_HRDATA01[27], F_RDATA_HRDATA01[26], 
        F_RDATA_HRDATA01[25], F_RDATA_HRDATA01[24], 
        F_RDATA_HRDATA01[23], F_RDATA_HRDATA01[22], 
        F_RDATA_HRDATA01[21], F_RDATA_HRDATA01[20], 
        F_RDATA_HRDATA01[19], F_RDATA_HRDATA01[18], 
        F_RDATA_HRDATA01[17], F_RDATA_HRDATA01[16], 
        F_RDATA_HRDATA01[15], F_RDATA_HRDATA01[14], 
        F_RDATA_HRDATA01[13], F_RDATA_HRDATA01[12], 
        F_RDATA_HRDATA01[11], F_RDATA_HRDATA01[10], 
        F_RDATA_HRDATA01[9], F_RDATA_HRDATA01[8], F_RDATA_HRDATA01[7], 
        F_RDATA_HRDATA01[6], F_RDATA_HRDATA01[5], F_RDATA_HRDATA01[4], 
        F_RDATA_HRDATA01[3], F_RDATA_HRDATA01[2], F_RDATA_HRDATA01[1], 
        F_RDATA_HRDATA01[0]}), .F_RID({F_RID[3], F_RID[2], F_RID[1], 
        F_RID[0]}), .F_RLAST(F_RLAST), .F_RRESP_HRESP1({
        F_RRESP_HRESP1[1], F_RRESP_HRESP1[0]}), .F_RVALID(F_RVALID), 
        .F_WREADY(F_WREADY), .MDDR_FABRIC_PRDATA({
        MDDR_FABRIC_PRDATA[15], MDDR_FABRIC_PRDATA[14], 
        MDDR_FABRIC_PRDATA[13], MDDR_FABRIC_PRDATA[12], 
        MDDR_FABRIC_PRDATA[11], MDDR_FABRIC_PRDATA[10], 
        MDDR_FABRIC_PRDATA[9], MDDR_FABRIC_PRDATA[8], 
        MDDR_FABRIC_PRDATA[7], MDDR_FABRIC_PRDATA[6], 
        MDDR_FABRIC_PRDATA[5], MDDR_FABRIC_PRDATA[4], 
        MDDR_FABRIC_PRDATA[3], MDDR_FABRIC_PRDATA[2], 
        MDDR_FABRIC_PRDATA[1], MDDR_FABRIC_PRDATA[0]}), 
        .MDDR_FABRIC_PREADY(MDDR_FABRIC_PREADY), .MDDR_FABRIC_PSLVERR(
        MDDR_FABRIC_PSLVERR), .CAN_RXBUS_F2H_SCP(VCC), 
        .CAN_TX_EBL_F2H_SCP(VCC), .CAN_TXBUS_F2H_SCP(VCC), .COLF(VCC), 
        .CRSF(VCC), .F2_DMAREADY({VCC, VCC}), .F2H_INTERRUPT({GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND}), .F2HCALIB(VCC), .F_DMAREADY({VCC, VCC}), 
        .F_FM0_ADDR({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}), 
        .F_FM0_ENABLE(GND), .F_FM0_MASTLOCK(GND), .F_FM0_READY(VCC), 
        .F_FM0_SEL(GND), .F_FM0_SIZE({GND, GND}), .F_FM0_TRANS1(GND), 
        .F_FM0_WDATA({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}), 
        .F_FM0_WRITE(GND), .F_HM0_RDATA({
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0}), 
        .F_HM0_READY(VCC), .F_HM0_RESP(GND), .FAB_AVALID(VCC), 
        .FAB_HOSTDISCON(VCC), .FAB_IDDIG(VCC), .FAB_LINESTATE({VCC, 
        VCC}), .FAB_M3_RESET_N(VCC), .FAB_PLL_LOCK(
        MC_System_0_FIC_0_LOCK), .FAB_RXACTIVE(VCC), .FAB_RXERROR(VCC), 
        .FAB_RXVALID(VCC), .FAB_RXVALIDH(GND), .FAB_SESSEND(VCC), 
        .FAB_TXREADY(VCC), .FAB_VBUSVALID(VCC), .FAB_VSTATUS({VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC}), .FAB_XDATAIN({VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC}), .GTX_CLKPF(VCC), .I2C0_BCLK(VCC), 
        .I2C0_SCL_F2H_SCP(VCC), .I2C0_SDA_F2H_SCP(VCC), .I2C1_BCLK(VCC)
        , .I2C1_SCL_F2H_SCP(VCC), .I2C1_SDA_F2H_SCP(VCC), .MDIF(VCC), 
        .MGPIO0A_F2H_GPIN(VCC), .MGPIO10A_F2H_GPIN(VCC), 
        .MGPIO11A_F2H_GPIN(VCC), .MGPIO11B_F2H_GPIN(VCC), 
        .MGPIO12A_F2H_GPIN(VCC), .MGPIO13A_F2H_GPIN(VCC), 
        .MGPIO14A_F2H_GPIN(VCC), .MGPIO15A_F2H_GPIN(VCC), 
        .MGPIO16A_F2H_GPIN(VCC), .MGPIO17B_F2H_GPIN(VCC), 
        .MGPIO18B_F2H_GPIN(VCC), .MGPIO19B_F2H_GPIN(VCC), 
        .MGPIO1A_F2H_GPIN(VCC), .MGPIO20B_F2H_GPIN(VCC), 
        .MGPIO21B_F2H_GPIN(VCC), .MGPIO22B_F2H_GPIN(VCC), 
        .MGPIO24B_F2H_GPIN(VCC), .MGPIO25B_F2H_GPIN(VCC), 
        .MGPIO26B_F2H_GPIN(VCC), .MGPIO27B_F2H_GPIN(VCC), 
        .MGPIO28B_F2H_GPIN(VCC), .MGPIO29B_F2H_GPIN(VCC), 
        .MGPIO2A_F2H_GPIN(VCC), .MGPIO30B_F2H_GPIN(VCC), 
        .MGPIO31B_F2H_GPIN(VCC), .MGPIO3A_F2H_GPIN(VCC), 
        .MGPIO4A_F2H_GPIN(VCC), .MGPIO5A_F2H_GPIN(VCC), 
        .MGPIO6A_F2H_GPIN(VCC), .MGPIO7A_F2H_GPIN(VCC), 
        .MGPIO8A_F2H_GPIN(VCC), .MGPIO9A_F2H_GPIN(VCC), 
        .MMUART0_CTS_F2H_SCP(VCC), .MMUART0_DCD_F2H_SCP(VCC), 
        .MMUART0_DSR_F2H_SCP(VCC), .MMUART0_DTR_F2H_SCP(VCC), 
        .MMUART0_RI_F2H_SCP(VCC), .MMUART0_RTS_F2H_SCP(VCC), 
        .MMUART0_RXD_F2H_SCP(VCC), .MMUART0_SCK_F2H_SCP(VCC), 
        .MMUART0_TXD_F2H_SCP(VCC), .MMUART1_CTS_F2H_SCP(VCC), 
        .MMUART1_DCD_F2H_SCP(VCC), .MMUART1_DSR_F2H_SCP(VCC), 
        .MMUART1_RI_F2H_SCP(VCC), .MMUART1_RTS_F2H_SCP(VCC), 
        .MMUART1_RXD_F2H_SCP(VCC), .MMUART1_SCK_F2H_SCP(VCC), 
        .MMUART1_TXD_F2H_SCP(VCC), .PER2_FABRIC_PRDATA({GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND}), .PER2_FABRIC_PREADY(VCC), 
        .PER2_FABRIC_PSLVERR(GND), .RCGF({VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC}), .RX_CLKPF(VCC), .RX_DVF(VCC), .RX_ERRF(
        VCC), .RX_EV(VCC), .RXDF({VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC}), .SLEEPHOLDREQ(GND), .SMBALERT_NI0(VCC), .SMBALERT_NI1(
        VCC), .SMBSUS_NI0(VCC), .SMBSUS_NI1(VCC), .SPI0_CLK_IN(VCC), 
        .SPI0_SDI_F2H_SCP(VCC), .SPI0_SDO_F2H_SCP(VCC), 
        .SPI0_SS0_F2H_SCP(VCC), .SPI0_SS1_F2H_SCP(VCC), 
        .SPI0_SS2_F2H_SCP(VCC), .SPI0_SS3_F2H_SCP(VCC), .SPI1_CLK_IN(
        VCC), .SPI1_SDI_F2H_SCP(VCC), .SPI1_SDO_F2H_SCP(VCC), 
        .SPI1_SS0_F2H_SCP(VCC), .SPI1_SS1_F2H_SCP(VCC), 
        .SPI1_SS2_F2H_SCP(VCC), .SPI1_SS3_F2H_SCP(VCC), .TX_CLKPF(VCC), 
        .USER_MSS_GPIO_RESET_N(VCC), .USER_MSS_RESET_N(VCC), .XCLK_FAB(
        VCC), .CLK_BASE(MC_System_0_FIC_0_CLK), .CLK_MDDR_APB(VCC), 
        .F_ARADDR_HADDR1({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}), 
        .F_ARBURST_HTRANS1({GND, GND}), .F_ARID_HSEL1({GND, GND, GND, 
        GND}), .F_ARLEN_HBURST1({GND, GND, GND, GND}), 
        .F_ARLOCK_HMASTLOCK1({GND, GND}), .F_ARSIZE_HSIZE1({GND, GND}), 
        .F_ARVALID_HWRITE1(GND), .F_AWADDR_HADDR0({VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC}), .F_AWBURST_HTRANS0({GND, GND}), 
        .F_AWID_HSEL0({GND, GND, GND, GND}), .F_AWLEN_HBURST0({GND, 
        GND, GND, GND}), .F_AWLOCK_HMASTLOCK0({GND, GND}), 
        .F_AWSIZE_HSIZE0({GND, GND}), .F_AWVALID_HWRITE0(GND), 
        .F_BREADY(GND), .F_RMW_AXI(GND), .F_RREADY(GND), 
        .F_WDATA_HWDATA01({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC, VCC}), .F_WID_HREADY01({GND, GND, 
        GND, GND}), .F_WLAST(GND), .F_WSTRB({GND, GND, GND, GND, GND, 
        GND, GND, GND}), .F_WVALID(GND), .FPGA_MDDR_ARESET_N(VCC), 
        .MDDR_FABRIC_PADDR({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC}), .MDDR_FABRIC_PENABLE(VCC), .MDDR_FABRIC_PSEL(VCC), 
        .MDDR_FABRIC_PWDATA({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}), .MDDR_FABRIC_PWRITE(
        VCC), .PRESET_N(GND), .CAN_RXBUS_USBA_DATA1_MGPIO3A_IN(GND), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN(GND), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_IN(GND), .DM_IN({GND, GND, GND}), 
        .DRAM_DQ_IN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND}), .DRAM_DQS_IN({GND, 
        GND, GND}), .DRAM_FIFO_WE_IN({GND, GND}), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_IN(GND), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_IN(GND), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_IN(GND), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_IN(GND), 
        .MMUART0_CTS_USBC_DATA7_MGPIO19B_IN(GND), 
        .MMUART0_DCD_MGPIO22B_IN(GND), .MMUART0_DSR_MGPIO20B_IN(GND), 
        .MMUART0_DTR_USBC_DATA6_MGPIO18B_IN(GND), 
        .MMUART0_RI_MGPIO21B_IN(GND), 
        .MMUART0_RTS_USBC_DATA5_MGPIO17B_IN(GND), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_IN(GND), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_IN(GND), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_IN(GND), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_IN(GND), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_IN(GND), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_IN(GND), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN(USB_ULPI_XCLK_PAD_Y), 
        .RGMII_MDC_RMII_MDC_IN(GND), 
        .RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN(USB_ULPI_DATA_7_PAD_Y), 
        .RGMII_RX_CLK_IN(GND), .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN(
        USB_ULPI_DATA_2_PAD_Y), .RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN(
        USB_ULPI_DATA_0_PAD_Y), .RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN(
        USB_ULPI_DATA_1_PAD_Y), .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN(
        USB_ULPI_DATA_3_PAD_Y), .RGMII_RXD3_USBB_DATA4_IN(
        USB_ULPI_DATA_4_PAD_Y), .RGMII_TX_CLK_IN(GND), 
        .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN(USB_ULPI_NXT_PAD_Y), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_IN(USB_ULPI_DIR_PAD_Y), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_IN(GND), 
        .RGMII_TXD2_USBB_DATA5_IN(USB_ULPI_DATA_5_PAD_Y), 
        .RGMII_TXD3_USBB_DATA6_IN(USB_ULPI_DATA_6_PAD_Y), 
        .SPI0_SCK_USBA_XCLK_IN(GND), .SPI0_SDI_USBA_DIR_MGPIO5A_IN(GND)
        , .SPI0_SDO_USBA_STP_MGPIO6A_IN(GND), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_IN(GND), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_IN(GND), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_IN(GND), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_IN(GND), .SPI1_SCK_IN(GND), 
        .SPI1_SDI_MGPIO11A_IN(GND), .SPI1_SDO_MGPIO12A_IN(GND), 
        .SPI1_SS0_MGPIO13A_IN(GND), .SPI1_SS1_MGPIO14A_IN(GND), 
        .SPI1_SS2_MGPIO15A_IN(GND), .SPI1_SS3_MGPIO16A_IN(GND), 
        .SPI1_SS4_MGPIO17A_IN(GND), .SPI1_SS5_MGPIO18A_IN(GND), 
        .SPI1_SS6_MGPIO23A_IN(GND), .SPI1_SS7_MGPIO24A_IN(GND), 
        .USBC_XCLK_IN(GND), .CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT(
        CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT(
        CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT(
        CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT), .DRAM_ADDR({DRAM_ADDR[15], 
        DRAM_ADDR[14], DRAM_ADDR[13], DRAM_ADDR[12], DRAM_ADDR[11], 
        DRAM_ADDR[10], DRAM_ADDR[9], DRAM_ADDR[8], DRAM_ADDR[7], 
        DRAM_ADDR[6], DRAM_ADDR[5], DRAM_ADDR[4], DRAM_ADDR[3], 
        DRAM_ADDR[2], DRAM_ADDR[1], DRAM_ADDR[0]}), .DRAM_BA({
        DRAM_BA[2], DRAM_BA[1], DRAM_BA[0]}), .DRAM_CASN(DRAM_CASN), 
        .DRAM_CKE(DRAM_CKE), .DRAM_CLK(DRAM_CLK), .DRAM_CSN(DRAM_CSN), 
        .DRAM_DM_RDQS_OUT({DRAM_DM_RDQS_OUT[2], DRAM_DM_RDQS_OUT[1], 
        DRAM_DM_RDQS_OUT[0]}), .DRAM_DQ_OUT({DRAM_DQ_OUT[17], 
        DRAM_DQ_OUT[16], DRAM_DQ_OUT[15], DRAM_DQ_OUT[14], 
        DRAM_DQ_OUT[13], DRAM_DQ_OUT[12], DRAM_DQ_OUT[11], 
        DRAM_DQ_OUT[10], DRAM_DQ_OUT[9], DRAM_DQ_OUT[8], 
        DRAM_DQ_OUT[7], DRAM_DQ_OUT[6], DRAM_DQ_OUT[5], DRAM_DQ_OUT[4], 
        DRAM_DQ_OUT[3], DRAM_DQ_OUT[2], DRAM_DQ_OUT[1], DRAM_DQ_OUT[0]})
        , .DRAM_DQS_OUT({DRAM_DQS_OUT[2], DRAM_DQS_OUT[1], 
        DRAM_DQS_OUT[0]}), .DRAM_FIFO_WE_OUT({DRAM_FIFO_WE_OUT[1], 
        DRAM_FIFO_WE_OUT[0]}), .DRAM_ODT(DRAM_ODT), .DRAM_RASN(
        DRAM_RASN), .DRAM_RSTN(DRAM_RSTN), .DRAM_WEN(DRAM_WEN), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_OUT(
        I2C0_SCL_USBC_DATA1_MGPIO31B_OUT), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_OUT(
        I2C0_SDA_USBC_DATA0_MGPIO30B_OUT), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_OUT(
        I2C1_SCL_USBA_DATA4_MGPIO1A_OUT), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_OUT(
        I2C1_SDA_USBA_DATA3_MGPIO0A_OUT), 
        .MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT(
        MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT), 
        .MMUART0_DCD_MGPIO22B_OUT(MMUART0_DCD_MGPIO22B_OUT), 
        .MMUART0_DSR_MGPIO20B_OUT(MMUART0_DSR_MGPIO20B_OUT), 
        .MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT(
        MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT), .MMUART0_RI_MGPIO21B_OUT(
        MMUART0_RI_MGPIO21B_OUT), .MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT(
        MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_OUT(
        MMUART0_RXD_USBC_STP_MGPIO28B_OUT), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_OUT(
        MMUART0_SCK_USBC_NXT_MGPIO29B_OUT), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_OUT(
        MMUART0_TXD_USBC_DIR_MGPIO27B_OUT), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT(
        MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT(
        MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT(
        MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT(
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT), .RGMII_MDC_RMII_MDC_OUT(
        RGMII_MDC_RMII_MDC_OUT), .RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT(
        MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT), 
        .RGMII_RX_CLK_OUT(RGMII_RX_CLK_OUT), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT(
        MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT(
        MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT(
        MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT(
        MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT), 
        .RGMII_RXD3_USBB_DATA4_OUT(
        MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OUT), .RGMII_TX_CLK_OUT(
        RGMII_TX_CLK_OUT), .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT(
        RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT(
        RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_OUT(
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OUT), 
        .RGMII_TXD2_USBB_DATA5_OUT(
        MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OUT), 
        .RGMII_TXD3_USBB_DATA6_OUT(
        MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OUT), 
        .SPI0_SCK_USBA_XCLK_OUT(SPI0_SCK_USBA_XCLK_OUT), 
        .SPI0_SDI_USBA_DIR_MGPIO5A_OUT(SPI0_SDI_USBA_DIR_MGPIO5A_OUT), 
        .SPI0_SDO_USBA_STP_MGPIO6A_OUT(SPI0_SDO_USBA_STP_MGPIO6A_OUT), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_OUT(SPI0_SS0_USBA_NXT_MGPIO7A_OUT), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_OUT(
        SPI0_SS1_USBA_DATA5_MGPIO8A_OUT), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_OUT(
        SPI0_SS2_USBA_DATA6_MGPIO9A_OUT), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_OUT(
        SPI0_SS3_USBA_DATA7_MGPIO10A_OUT), .SPI1_SCK_OUT(SPI1_SCK_OUT), 
        .SPI1_SDI_MGPIO11A_OUT(SPI1_SDI_MGPIO11A_OUT), 
        .SPI1_SDO_MGPIO12A_OUT(SPI1_SDO_MGPIO12A_OUT), 
        .SPI1_SS0_MGPIO13A_OUT(SPI1_SS0_MGPIO13A_OUT), 
        .SPI1_SS1_MGPIO14A_OUT(SPI1_SS1_MGPIO14A_OUT), 
        .SPI1_SS2_MGPIO15A_OUT(SPI1_SS2_MGPIO15A_OUT), 
        .SPI1_SS3_MGPIO16A_OUT(SPI1_SS3_MGPIO16A_OUT), 
        .SPI1_SS4_MGPIO17A_OUT(SPI1_SS4_MGPIO17A_OUT), 
        .SPI1_SS5_MGPIO18A_OUT(SPI1_SS5_MGPIO18A_OUT), 
        .SPI1_SS6_MGPIO23A_OUT(SPI1_SS6_MGPIO23A_OUT), 
        .SPI1_SS7_MGPIO24A_OUT(SPI1_SS7_MGPIO24A_OUT), .USBC_XCLK_OUT(
        USBC_XCLK_OUT), .CAN_RXBUS_USBA_DATA1_MGPIO3A_OE(
        CAN_RXBUS_USBA_DATA1_MGPIO3A_OE), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE(
        CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_OE(
        CAN_TXBUS_USBA_DATA0_MGPIO2A_OE), .DM_OE({DM_OE[2], DM_OE[1], 
        DM_OE[0]}), .DRAM_DQ_OE({DRAM_DQ_OE[17], DRAM_DQ_OE[16], 
        DRAM_DQ_OE[15], DRAM_DQ_OE[14], DRAM_DQ_OE[13], DRAM_DQ_OE[12], 
        DRAM_DQ_OE[11], DRAM_DQ_OE[10], DRAM_DQ_OE[9], DRAM_DQ_OE[8], 
        DRAM_DQ_OE[7], DRAM_DQ_OE[6], DRAM_DQ_OE[5], DRAM_DQ_OE[4], 
        DRAM_DQ_OE[3], DRAM_DQ_OE[2], DRAM_DQ_OE[1], DRAM_DQ_OE[0]}), 
        .DRAM_DQS_OE({DRAM_DQS_OE[2], DRAM_DQS_OE[1], DRAM_DQS_OE[0]}), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_OE(
        I2C0_SCL_USBC_DATA1_MGPIO31B_OE), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_OE(
        I2C0_SDA_USBC_DATA0_MGPIO30B_OE), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_OE(I2C1_SCL_USBA_DATA4_MGPIO1A_OE)
        , .I2C1_SDA_USBA_DATA3_MGPIO0A_OE(
        I2C1_SDA_USBA_DATA3_MGPIO0A_OE), 
        .MMUART0_CTS_USBC_DATA7_MGPIO19B_OE(
        MMUART0_CTS_USBC_DATA7_MGPIO19B_OE), .MMUART0_DCD_MGPIO22B_OE(
        MMUART0_DCD_MGPIO22B_OE), .MMUART0_DSR_MGPIO20B_OE(
        MMUART0_DSR_MGPIO20B_OE), .MMUART0_DTR_USBC_DATA6_MGPIO18B_OE(
        MMUART0_DTR_USBC_DATA6_MGPIO18B_OE), .MMUART0_RI_MGPIO21B_OE(
        MMUART0_RI_MGPIO21B_OE), .MMUART0_RTS_USBC_DATA5_MGPIO17B_OE(
        MMUART0_RTS_USBC_DATA5_MGPIO17B_OE), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_OE(
        MMUART0_RXD_USBC_STP_MGPIO28B_OE), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_OE(
        MMUART0_SCK_USBC_NXT_MGPIO29B_OE), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_OE(
        MMUART0_TXD_USBC_DIR_MGPIO27B_OE), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_OE(
        MMUART1_RXD_USBC_DATA3_MGPIO26B_OE), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_OE(
        MMUART1_SCK_USBC_DATA4_MGPIO25B_OE), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_OE(
        MMUART1_TXD_USBC_DATA2_MGPIO24B_OE), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE(
        RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE), .RGMII_MDC_RMII_MDC_OE(
        RGMII_MDC_RMII_MDC_OE), .RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE(
        MSS_ADLIB_INST_RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE), 
        .RGMII_RX_CLK_OE(RGMII_RX_CLK_OE), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE(
        MSS_ADLIB_INST_RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE(
        MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE(
        MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE(
        MSS_ADLIB_INST_RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE), 
        .RGMII_RXD3_USBB_DATA4_OE(
        MSS_ADLIB_INST_RGMII_RXD3_USBB_DATA4_OE), .RGMII_TX_CLK_OE(
        RGMII_TX_CLK_OE), .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE(
        RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_OE(
        RGMII_TXD0_RMII_TXD0_USBB_DIR_OE), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_OE(
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OE), 
        .RGMII_TXD2_USBB_DATA5_OE(
        MSS_ADLIB_INST_RGMII_TXD2_USBB_DATA5_OE), 
        .RGMII_TXD3_USBB_DATA6_OE(
        MSS_ADLIB_INST_RGMII_TXD3_USBB_DATA6_OE), 
        .SPI0_SCK_USBA_XCLK_OE(SPI0_SCK_USBA_XCLK_OE), 
        .SPI0_SDI_USBA_DIR_MGPIO5A_OE(SPI0_SDI_USBA_DIR_MGPIO5A_OE), 
        .SPI0_SDO_USBA_STP_MGPIO6A_OE(SPI0_SDO_USBA_STP_MGPIO6A_OE), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_OE(SPI0_SS0_USBA_NXT_MGPIO7A_OE), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_OE(SPI0_SS1_USBA_DATA5_MGPIO8A_OE)
        , .SPI0_SS2_USBA_DATA6_MGPIO9A_OE(
        SPI0_SS2_USBA_DATA6_MGPIO9A_OE), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_OE(
        SPI0_SS3_USBA_DATA7_MGPIO10A_OE), .SPI1_SCK_OE(SPI1_SCK_OE), 
        .SPI1_SDI_MGPIO11A_OE(SPI1_SDI_MGPIO11A_OE), 
        .SPI1_SDO_MGPIO12A_OE(SPI1_SDO_MGPIO12A_OE), 
        .SPI1_SS0_MGPIO13A_OE(SPI1_SS0_MGPIO13A_OE), 
        .SPI1_SS1_MGPIO14A_OE(SPI1_SS1_MGPIO14A_OE), 
        .SPI1_SS2_MGPIO15A_OE(SPI1_SS2_MGPIO15A_OE), 
        .SPI1_SS3_MGPIO16A_OE(SPI1_SS3_MGPIO16A_OE), 
        .SPI1_SS4_MGPIO17A_OE(SPI1_SS4_MGPIO17A_OE), 
        .SPI1_SS5_MGPIO18A_OE(SPI1_SS5_MGPIO18A_OE), 
        .SPI1_SS6_MGPIO23A_OE(SPI1_SS6_MGPIO23A_OE), 
        .SPI1_SS7_MGPIO24A_OE(SPI1_SS7_MGPIO24A_OE), .USBC_XCLK_OE(
        USBC_XCLK_OE));
    VCC VCC_Z (.Y(VCC));
    BIBUF #( .IOSTD("") )  USB_ULPI_DATA_0_PAD (.PAD(USB_ULPI_DATA[0]), 
        .D(MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT), .E(
        MSS_ADLIB_INST_RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE), .Y(
        USB_ULPI_DATA_0_PAD_Y));
    BIBUF #( .IOSTD("") )  USB_ULPI_DATA_1_PAD (.PAD(USB_ULPI_DATA[1]), 
        .D(MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT), .E(
        MSS_ADLIB_INST_RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE), .Y(
        USB_ULPI_DATA_1_PAD_Y));
    TRIBUFF #( .IOSTD("") )  USB_ULPI_STP_PAD (.D(
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OUT), .E(
        MSS_ADLIB_INST_RGMII_TXD1_RMII_TXD1_USBB_STP_OE), .PAD(
        USB_ULPI_STP));
    
endmodule


module MC_System_sb(
       FOC_TRANSFORMS_0_valpha_o,
       FOC_TRANSFORMS_0_valpha_o_m_0,
       FOC_TRANSFORMS_0_valpha_o_m_5,
       FOC_TRANSFORMS_0_ialpha_o_m,
       SPEED_ID_IQ_PI_0_iq_pi_output_o,
       adc_interface_0_result_ch3_o_m,
       MC_System_0_AMBA_SLAVE_0_PRDATA,
       SPEED_ID_IQ_PI_0_id_pi_output_o,
       HALL_INTERFACE_1_omega_out_o,
       FOC_TRANSFORMS_0_ialpha_o,
       adc_interface_0_result_ch1_o_2,
       adc_interface_0_result_ch1_o_0,
       SEQ_CONTROLLER_0_state_o_2,
       SEQ_CONTROLLER_0_state_o_0,
       adc_interface_0_result_ch0_o,
       FOC_TRANSFORMS_0_ibeta_o,
       prdata_o_1_0_iv_0_14,
       prdata_o_1_0_iv_0_15,
       prdata_o_1_0_iv_0_13,
       prdata_o_1_iv_10_0,
       FOC_TRANSFORMS_0_id_o_m,
       prdata_o_1_iv_13,
       prdata_o_1_iv_14_0,
       prdata_o_1_iv_14_2,
       prdata_o_1_iv_12,
       prdata_o_1_iv_10_12,
       prdata_o_1_iv_10_13,
       prdata_o_1_iv_10_11,
       prdata_o_1_iv_0_7,
       prdata_o_1_iv_0_6,
       prdata_o_1_iv_0_8,
       prdata_o_1_iv_0_7_0,
       prdata_o_1_iv_0_9,
       prdata_o_1_iv_10,
       prdata_o_1_iv_11,
       prdata_o_1_iv_9,
       prdata_o_1_iv_0_11_0,
       prdata_o_1_iv_0_11_2,
       prdata_o_1_iv_0_11_3,
       prdata_o_1_iv_0_12_0,
       prdata_o_1_iv_0_12_2,
       prdata_o_1_iv_0_10,
       USB_ULPI_DATA,
       MC_System_0_AMBA_SLAVE_0_PADDR_0,
       MC_System_0_AMBA_SLAVE_0_PADDR_1,
       MC_System_0_AMBA_SLAVE_0_PADDR_2,
       MC_System_0_AMBA_SLAVE_0_PADDR_3,
       MC_System_0_AMBA_SLAVE_0_PADDR_4,
       MC_System_0_AMBA_SLAVE_0_PADDR_5,
       MC_System_0_AMBA_SLAVE_0_PADDR_6,
       MC_System_0_AMBA_SLAVE_0_PADDR_7,
       MC_System_0_AMBA_SLAVE_0_PADDR_8,
       MC_System_0_AMBA_SLAVE_0_PADDR_9,
       MC_System_0_AMBA_SLAVE_0_PADDR_10,
       MC_System_0_AMBA_SLAVE_0_PADDR_11,
       MC_System_0_AMBA_SLAVE_0_PWDATA,
       MC_System_0_FIC_0_LOCK,
       MC_System_0_FIC_0_CLK,
       MC_System_0_AMBA_SLAVE_0_PSELx,
       prdata_m2_e_5_6,
       prdata_m2_e_5_11,
       prdata_m2_e_5_1,
       prdata_N_5_mux_i_3_a0_7_1,
       prdata_o263,
       prdata_o274,
       prdata_m2_e_5_4,
       prdata_m2_e_5_10,
       prdata_N_5_mux_i_3_a0_11,
       prdata_N_5_mux_i_3_a0_10,
       prdata_N_5_mux_i_3_a0_4,
       prdata_N_5_mux_i_3_a0_0,
       prdata_N_5_mux_i_3_a0_12,
       prdata_N_5_mux_i_2_a0_11,
       prdata_N_5_mux_i_2_a0_10,
       prdata_N_5_mux_i_2_a0_4,
       prdata_N_5_mux_i_2_a0_0,
       prdata_N_5_mux_i_2_a0_12,
       prdata_m2_0_a2_1_0,
       prdata_m2_0_a2_17_0,
       N_358,
       prdata_m2_e_5_6_1,
       prdata_N_5_mux_i_1_a0_13,
       prdata_N_5_mux_i_1_a0_12,
       prdata_o277,
       prdata_o267,
       N_296,
       prdata_o259,
       N_225,
       prdata_o270,
       N_283,
       N_286,
       prdata_o260,
       prdata_m2_e_0_9,
       prdata_m2_e_0_10,
       prdata_m2_e_0_8,
       prdata_m2_e_27_11,
       prdata_m2_e_27_12,
       prdata_m2_e_27_10,
       prdata_N_5_mux_i_4_a0_12,
       prdata_N_5_mux_i_4_a0_13,
       prdata_N_5_mux_i_4_a0_11,
       m7_i_2,
       N_435_4,
       N_157,
       USB_ULPI_XCLK,
       USB_ULPI_STP,
       USB_ULPI_NXT,
       USB_ULPI_DIR,
       MC_System_0_AMBA_SLAVE_0_PENABLE,
       MC_System_0_AMBA_SLAVE_0_PWRITE,
       GPIO_0_M2F_c
    );
input  [2:2] FOC_TRANSFORMS_0_valpha_o;
input  FOC_TRANSFORMS_0_valpha_o_m_0;
input  FOC_TRANSFORMS_0_valpha_o_m_5;
input  [9:9] FOC_TRANSFORMS_0_ialpha_o_m;
input  [9:9] SPEED_ID_IQ_PI_0_iq_pi_output_o;
input  [9:9] adc_interface_0_result_ch3_o_m;
input  [19:19] MC_System_0_AMBA_SLAVE_0_PRDATA;
input  [0:0] SPEED_ID_IQ_PI_0_id_pi_output_o;
input  [0:0] HALL_INTERFACE_1_omega_out_o;
input  [0:0] FOC_TRANSFORMS_0_ialpha_o;
input  adc_interface_0_result_ch1_o_2;
input  adc_interface_0_result_ch1_o_0;
input  SEQ_CONTROLLER_0_state_o_2;
input  SEQ_CONTROLLER_0_state_o_0;
input  [0:0] adc_interface_0_result_ch0_o;
input  [0:0] FOC_TRANSFORMS_0_ibeta_o;
input  [1:1] prdata_o_1_0_iv_0_14;
input  [1:0] prdata_o_1_0_iv_0_15;
input  [1:1] prdata_o_1_0_iv_0_13;
input  [5:5] prdata_o_1_iv_10_0;
input  [5:5] FOC_TRANSFORMS_0_id_o_m;
input  [7:7] prdata_o_1_iv_13;
input  prdata_o_1_iv_14_0;
input  prdata_o_1_iv_14_2;
input  [7:7] prdata_o_1_iv_12;
input  [10:10] prdata_o_1_iv_10_12;
input  [10:10] prdata_o_1_iv_10_13;
input  [10:10] prdata_o_1_iv_10_11;
input  [12:12] prdata_o_1_iv_0_7;
input  [12:12] prdata_o_1_iv_0_6;
input  [13:13] prdata_o_1_iv_0_8;
input  [13:13] prdata_o_1_iv_0_7_0;
input  [14:14] prdata_o_1_iv_0_9;
input  [16:16] prdata_o_1_iv_10;
input  [16:16] prdata_o_1_iv_11;
input  [16:16] prdata_o_1_iv_9;
input  prdata_o_1_iv_0_11_0;
input  prdata_o_1_iv_0_11_2;
input  prdata_o_1_iv_0_11_3;
input  prdata_o_1_iv_0_12_0;
input  prdata_o_1_iv_0_12_2;
input  [15:14] prdata_o_1_iv_0_10;
inout  [7:0] USB_ULPI_DATA;
output MC_System_0_AMBA_SLAVE_0_PADDR_0;
output MC_System_0_AMBA_SLAVE_0_PADDR_1;
output MC_System_0_AMBA_SLAVE_0_PADDR_2;
output MC_System_0_AMBA_SLAVE_0_PADDR_3;
output MC_System_0_AMBA_SLAVE_0_PADDR_4;
output MC_System_0_AMBA_SLAVE_0_PADDR_5;
output MC_System_0_AMBA_SLAVE_0_PADDR_6;
output MC_System_0_AMBA_SLAVE_0_PADDR_7;
output MC_System_0_AMBA_SLAVE_0_PADDR_8;
output MC_System_0_AMBA_SLAVE_0_PADDR_9;
output MC_System_0_AMBA_SLAVE_0_PADDR_10;
output MC_System_0_AMBA_SLAVE_0_PADDR_11;
output [17:0] MC_System_0_AMBA_SLAVE_0_PWDATA;
output MC_System_0_FIC_0_LOCK;
output MC_System_0_FIC_0_CLK;
output MC_System_0_AMBA_SLAVE_0_PSELx;
input  prdata_m2_e_5_6;
input  prdata_m2_e_5_11;
input  prdata_m2_e_5_1;
input  prdata_N_5_mux_i_3_a0_7_1;
input  prdata_o263;
input  prdata_o274;
input  prdata_m2_e_5_4;
input  prdata_m2_e_5_10;
input  prdata_N_5_mux_i_3_a0_11;
input  prdata_N_5_mux_i_3_a0_10;
input  prdata_N_5_mux_i_3_a0_4;
input  prdata_N_5_mux_i_3_a0_0;
input  prdata_N_5_mux_i_3_a0_12;
input  prdata_N_5_mux_i_2_a0_11;
input  prdata_N_5_mux_i_2_a0_10;
input  prdata_N_5_mux_i_2_a0_4;
input  prdata_N_5_mux_i_2_a0_0;
input  prdata_N_5_mux_i_2_a0_12;
input  prdata_m2_0_a2_1_0;
input  prdata_m2_0_a2_17_0;
input  N_358;
input  prdata_m2_e_5_6_1;
input  prdata_N_5_mux_i_1_a0_13;
input  prdata_N_5_mux_i_1_a0_12;
input  prdata_o277;
input  prdata_o267;
input  N_296;
input  prdata_o259;
input  N_225;
input  prdata_o270;
input  N_283;
input  N_286;
input  prdata_o260;
input  prdata_m2_e_0_9;
input  prdata_m2_e_0_10;
input  prdata_m2_e_0_8;
input  prdata_m2_e_27_11;
input  prdata_m2_e_27_12;
input  prdata_m2_e_27_10;
input  prdata_N_5_mux_i_4_a0_12;
input  prdata_N_5_mux_i_4_a0_13;
input  prdata_N_5_mux_i_4_a0_11;
input  m7_i_2;
input  N_435_4;
input  N_157;
input  USB_ULPI_XCLK;
output USB_ULPI_STP;
input  USB_ULPI_NXT;
input  USB_ULPI_DIR;
output MC_System_0_AMBA_SLAVE_0_PENABLE;
output MC_System_0_AMBA_SLAVE_0_PWRITE;
output GPIO_0_M2F_c;

    wire [15:12] MC_System_0_AMBA_SLAVE_0_PADDR;
    wire [31:0] MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA;
    wire FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC, 
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx, GND, VCC;
    
    MC_System_sb_FABOSC_0_OSC FABOSC_0 (
        .FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    
        CoreAPB3_32_0_1_1_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_16_3_19 
        CoreAPB3_0 (.MC_System_0_AMBA_SLAVE_0_PADDR({
        MC_System_0_AMBA_SLAVE_0_PADDR[15], 
        MC_System_0_AMBA_SLAVE_0_PADDR[14], 
        MC_System_0_AMBA_SLAVE_0_PADDR[13], 
        MC_System_0_AMBA_SLAVE_0_PADDR[12]}), 
        .FOC_TRANSFORMS_0_valpha_o({FOC_TRANSFORMS_0_valpha_o[2]}), 
        .FOC_TRANSFORMS_0_valpha_o_m_0(FOC_TRANSFORMS_0_valpha_o_m_0), 
        .FOC_TRANSFORMS_0_valpha_o_m_5(FOC_TRANSFORMS_0_valpha_o_m_5), 
        .FOC_TRANSFORMS_0_ialpha_o_m({FOC_TRANSFORMS_0_ialpha_o_m[9]}), 
        .SPEED_ID_IQ_PI_0_iq_pi_output_o({
        SPEED_ID_IQ_PI_0_iq_pi_output_o[9]}), 
        .adc_interface_0_result_ch3_o_m({
        adc_interface_0_result_ch3_o_m[9]}), 
        .MC_System_0_AMBA_SLAVE_0_PRDATA({
        MC_System_0_AMBA_SLAVE_0_PRDATA[19]}), 
        .SPEED_ID_IQ_PI_0_id_pi_output_o({
        SPEED_ID_IQ_PI_0_id_pi_output_o[0]}), 
        .HALL_INTERFACE_1_omega_out_o({HALL_INTERFACE_1_omega_out_o[0]})
        , .FOC_TRANSFORMS_0_ialpha_o({FOC_TRANSFORMS_0_ialpha_o[0]}), 
        .adc_interface_0_result_ch1_o_2(adc_interface_0_result_ch1_o_2)
        , .adc_interface_0_result_ch1_o_0(
        adc_interface_0_result_ch1_o_0), .SEQ_CONTROLLER_0_state_o_2(
        SEQ_CONTROLLER_0_state_o_2), .SEQ_CONTROLLER_0_state_o_0(
        SEQ_CONTROLLER_0_state_o_0), .adc_interface_0_result_ch0_o({
        adc_interface_0_result_ch0_o[0]}), .FOC_TRANSFORMS_0_ibeta_o({
        FOC_TRANSFORMS_0_ibeta_o[0]}), .prdata_o_1_0_iv_0_14({
        prdata_o_1_0_iv_0_14[1]}), .prdata_o_1_0_iv_0_15({
        prdata_o_1_0_iv_0_15[1], prdata_o_1_0_iv_0_15[0]}), 
        .prdata_o_1_0_iv_0_13({prdata_o_1_0_iv_0_13[1]}), 
        .prdata_o_1_iv_10_0({prdata_o_1_iv_10_0[5]}), 
        .FOC_TRANSFORMS_0_id_o_m({FOC_TRANSFORMS_0_id_o_m[5]}), 
        .prdata_o_1_iv_13({prdata_o_1_iv_13[7]}), .prdata_o_1_iv_14_0(
        prdata_o_1_iv_14_0), .prdata_o_1_iv_14_2(prdata_o_1_iv_14_2), 
        .prdata_o_1_iv_12({prdata_o_1_iv_12[7]}), .prdata_o_1_iv_10_12({
        prdata_o_1_iv_10_12[10]}), .prdata_o_1_iv_10_13({
        prdata_o_1_iv_10_13[10]}), .prdata_o_1_iv_10_11({
        prdata_o_1_iv_10_11[10]}), .prdata_o_1_iv_0_7({
        prdata_o_1_iv_0_7[12]}), .prdata_o_1_iv_0_6({
        prdata_o_1_iv_0_6[12]}), .prdata_o_1_iv_0_8({
        prdata_o_1_iv_0_8[13]}), .prdata_o_1_iv_0_7_0({
        prdata_o_1_iv_0_7_0[13]}), .prdata_o_1_iv_0_9({
        prdata_o_1_iv_0_9[14]}), .prdata_o_1_iv_10({
        prdata_o_1_iv_10[16]}), .prdata_o_1_iv_11({
        prdata_o_1_iv_11[16]}), .prdata_o_1_iv_9({prdata_o_1_iv_9[16]})
        , .prdata_o_1_iv_0_11_0(prdata_o_1_iv_0_11_0), 
        .prdata_o_1_iv_0_11_2(prdata_o_1_iv_0_11_2), 
        .prdata_o_1_iv_0_11_3(prdata_o_1_iv_0_11_3), 
        .prdata_o_1_iv_0_12_0(prdata_o_1_iv_0_12_0), 
        .prdata_o_1_iv_0_12_2(prdata_o_1_iv_0_12_2), 
        .prdata_o_1_iv_0_10({prdata_o_1_iv_0_10[15], 
        prdata_o_1_iv_0_10[14]}), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[2]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[6]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[11]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[9]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[31]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[0]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[1]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[5]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[7]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[8]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[10]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[12]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[13]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[14]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[16]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[17]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[15]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx), 
        .MC_System_0_AMBA_SLAVE_0_PSELx(MC_System_0_AMBA_SLAVE_0_PSELx)
        , .prdata_m2_e_5_6(prdata_m2_e_5_6), .prdata_m2_e_5_11(
        prdata_m2_e_5_11), .prdata_m2_e_5_1(prdata_m2_e_5_1), 
        .prdata_N_5_mux_i_3_a0_7_1(prdata_N_5_mux_i_3_a0_7_1), 
        .prdata_o263(prdata_o263), .prdata_o274(prdata_o274), 
        .prdata_m2_e_5_4(prdata_m2_e_5_4), .prdata_m2_e_5_10(
        prdata_m2_e_5_10), .prdata_N_5_mux_i_3_a0_11(
        prdata_N_5_mux_i_3_a0_11), .prdata_N_5_mux_i_3_a0_10(
        prdata_N_5_mux_i_3_a0_10), .prdata_N_5_mux_i_3_a0_4(
        prdata_N_5_mux_i_3_a0_4), .prdata_N_5_mux_i_3_a0_0(
        prdata_N_5_mux_i_3_a0_0), .prdata_N_5_mux_i_3_a0_12(
        prdata_N_5_mux_i_3_a0_12), .prdata_N_5_mux_i_2_a0_11(
        prdata_N_5_mux_i_2_a0_11), .prdata_N_5_mux_i_2_a0_10(
        prdata_N_5_mux_i_2_a0_10), .prdata_N_5_mux_i_2_a0_4(
        prdata_N_5_mux_i_2_a0_4), .prdata_N_5_mux_i_2_a0_0(
        prdata_N_5_mux_i_2_a0_0), .prdata_N_5_mux_i_2_a0_12(
        prdata_N_5_mux_i_2_a0_12), .prdata_m2_0_a2_1_0(
        prdata_m2_0_a2_1_0), .prdata_m2_0_a2_17_0(prdata_m2_0_a2_17_0), 
        .N_358(N_358), .prdata_m2_e_5_6_1(prdata_m2_e_5_6_1), 
        .prdata_N_5_mux_i_1_a0_13(prdata_N_5_mux_i_1_a0_13), 
        .prdata_N_5_mux_i_1_a0_12(prdata_N_5_mux_i_1_a0_12), 
        .prdata_o277(prdata_o277), .prdata_o267(prdata_o267), .N_296(
        N_296), .prdata_o259(prdata_o259), .N_225(N_225), .prdata_o270(
        prdata_o270), .N_283(N_283), .N_286(N_286), .prdata_o260(
        prdata_o260), .prdata_m2_e_0_9(prdata_m2_e_0_9), 
        .prdata_m2_e_0_10(prdata_m2_e_0_10), .prdata_m2_e_0_8(
        prdata_m2_e_0_8), .prdata_m2_e_27_11(prdata_m2_e_27_11), 
        .prdata_m2_e_27_12(prdata_m2_e_27_12), .prdata_m2_e_27_10(
        prdata_m2_e_27_10), .prdata_N_5_mux_i_4_a0_12(
        prdata_N_5_mux_i_4_a0_12), .prdata_N_5_mux_i_4_a0_13(
        prdata_N_5_mux_i_4_a0_13), .prdata_N_5_mux_i_4_a0_11(
        prdata_N_5_mux_i_4_a0_11), .m7_i_2(m7_i_2), .N_435_4(N_435_4), 
        .N_157(N_157));
    MC_System_sb_CCC_0_FCCC CCC_0 (.MC_System_0_FIC_0_LOCK(
        MC_System_0_FIC_0_LOCK), .MC_System_0_FIC_0_CLK(
        MC_System_0_FIC_0_CLK), 
        .FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    VCC VCC_Z (.Y(VCC));
    MC_System_sb_MSS MC_System_sb_MSS_0 (.USB_ULPI_DATA({
        USB_ULPI_DATA[7], USB_ULPI_DATA[6], USB_ULPI_DATA[5], 
        USB_ULPI_DATA[4], USB_ULPI_DATA[3], USB_ULPI_DATA[2], 
        USB_ULPI_DATA[1], USB_ULPI_DATA[0]}), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_0(
        MC_System_0_AMBA_SLAVE_0_PADDR_0), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_1(
        MC_System_0_AMBA_SLAVE_0_PADDR_1), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_2(
        MC_System_0_AMBA_SLAVE_0_PADDR_2), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_3(
        MC_System_0_AMBA_SLAVE_0_PADDR_3), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_4(
        MC_System_0_AMBA_SLAVE_0_PADDR_4), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_5(
        MC_System_0_AMBA_SLAVE_0_PADDR_5), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_6(
        MC_System_0_AMBA_SLAVE_0_PADDR_6), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_7(
        MC_System_0_AMBA_SLAVE_0_PADDR_7), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_8(
        MC_System_0_AMBA_SLAVE_0_PADDR_8), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_9(
        MC_System_0_AMBA_SLAVE_0_PADDR_9), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_10(
        MC_System_0_AMBA_SLAVE_0_PADDR_10), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_11(
        MC_System_0_AMBA_SLAVE_0_PADDR_11), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_12(
        MC_System_0_AMBA_SLAVE_0_PADDR[12]), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_13(
        MC_System_0_AMBA_SLAVE_0_PADDR[13]), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_14(
        MC_System_0_AMBA_SLAVE_0_PADDR[14]), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_15(
        MC_System_0_AMBA_SLAVE_0_PADDR[15]), 
        .MC_System_0_AMBA_SLAVE_0_PWDATA_0(
        MC_System_0_AMBA_SLAVE_0_PWDATA[0]), 
        .MC_System_0_AMBA_SLAVE_0_PWDATA_1(
        MC_System_0_AMBA_SLAVE_0_PWDATA[1]), 
        .MC_System_0_AMBA_SLAVE_0_PWDATA_2(
        MC_System_0_AMBA_SLAVE_0_PWDATA[2]), 
        .MC_System_0_AMBA_SLAVE_0_PWDATA_3(
        MC_System_0_AMBA_SLAVE_0_PWDATA[3]), 
        .MC_System_0_AMBA_SLAVE_0_PWDATA_4(
        MC_System_0_AMBA_SLAVE_0_PWDATA[4]), 
        .MC_System_0_AMBA_SLAVE_0_PWDATA_5(
        MC_System_0_AMBA_SLAVE_0_PWDATA[5]), 
        .MC_System_0_AMBA_SLAVE_0_PWDATA_6(
        MC_System_0_AMBA_SLAVE_0_PWDATA[6]), 
        .MC_System_0_AMBA_SLAVE_0_PWDATA_7(
        MC_System_0_AMBA_SLAVE_0_PWDATA[7]), 
        .MC_System_0_AMBA_SLAVE_0_PWDATA_8(
        MC_System_0_AMBA_SLAVE_0_PWDATA[8]), 
        .MC_System_0_AMBA_SLAVE_0_PWDATA_9(
        MC_System_0_AMBA_SLAVE_0_PWDATA[9]), 
        .MC_System_0_AMBA_SLAVE_0_PWDATA_10(
        MC_System_0_AMBA_SLAVE_0_PWDATA[10]), 
        .MC_System_0_AMBA_SLAVE_0_PWDATA_11(
        MC_System_0_AMBA_SLAVE_0_PWDATA[11]), 
        .MC_System_0_AMBA_SLAVE_0_PWDATA_12(
        MC_System_0_AMBA_SLAVE_0_PWDATA[12]), 
        .MC_System_0_AMBA_SLAVE_0_PWDATA_13(
        MC_System_0_AMBA_SLAVE_0_PWDATA[13]), 
        .MC_System_0_AMBA_SLAVE_0_PWDATA_14(
        MC_System_0_AMBA_SLAVE_0_PWDATA[14]), 
        .MC_System_0_AMBA_SLAVE_0_PWDATA_15(
        MC_System_0_AMBA_SLAVE_0_PWDATA[15]), 
        .MC_System_0_AMBA_SLAVE_0_PWDATA_16(
        MC_System_0_AMBA_SLAVE_0_PWDATA[16]), 
        .MC_System_0_AMBA_SLAVE_0_PWDATA_17(
        MC_System_0_AMBA_SLAVE_0_PWDATA[17]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_0(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[0]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_1(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[1]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_2(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[2]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_3(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_4(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_5(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[5]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_6(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[6]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_7(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[7]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_8(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[8]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_9(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[9]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_10(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[10]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_11(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[11]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_12(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[12]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_13(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[13]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_14(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[14]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_15(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[15]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_16(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[16]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_17(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[17]), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA_31(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[31]), 
        .USB_ULPI_XCLK(USB_ULPI_XCLK), .USB_ULPI_STP(USB_ULPI_STP), 
        .USB_ULPI_NXT(USB_ULPI_NXT), .USB_ULPI_DIR(USB_ULPI_DIR), 
        .MC_System_0_AMBA_SLAVE_0_PENABLE(
        MC_System_0_AMBA_SLAVE_0_PENABLE), 
        .MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx(
        MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx), 
        .MC_System_0_AMBA_SLAVE_0_PWRITE(
        MC_System_0_AMBA_SLAVE_0_PWRITE), .GPIO_0_M2F_c(GPIO_0_M2F_c), 
        .MC_System_0_FIC_0_LOCK(MC_System_0_FIC_0_LOCK), 
        .MC_System_0_FIC_0_CLK(MC_System_0_FIC_0_CLK));
    GND GND_Z (.Y(GND));
    
endmodule


module MC_System(
       FOC_TRANSFORMS_0_valpha_o,
       FOC_TRANSFORMS_0_valpha_o_m_0,
       FOC_TRANSFORMS_0_valpha_o_m_5,
       FOC_TRANSFORMS_0_ialpha_o_m,
       SPEED_ID_IQ_PI_0_iq_pi_output_o,
       adc_interface_0_result_ch3_o_m,
       MC_System_0_AMBA_SLAVE_0_PRDATA,
       SPEED_ID_IQ_PI_0_id_pi_output_o,
       HALL_INTERFACE_1_omega_out_o,
       FOC_TRANSFORMS_0_ialpha_o,
       adc_interface_0_result_ch1_o_2,
       adc_interface_0_result_ch1_o_0,
       SEQ_CONTROLLER_0_state_o_2,
       SEQ_CONTROLLER_0_state_o_0,
       adc_interface_0_result_ch0_o,
       FOC_TRANSFORMS_0_ibeta_o,
       prdata_o_1_0_iv_0_14,
       prdata_o_1_0_iv_0_15,
       prdata_o_1_0_iv_0_13,
       prdata_o_1_iv_10_0,
       FOC_TRANSFORMS_0_id_o_m,
       prdata_o_1_iv_13,
       prdata_o_1_iv_14_0,
       prdata_o_1_iv_14_2,
       prdata_o_1_iv_12,
       prdata_o_1_iv_10_12,
       prdata_o_1_iv_10_13,
       prdata_o_1_iv_10_11,
       prdata_o_1_iv_0_7,
       prdata_o_1_iv_0_6,
       prdata_o_1_iv_0_8,
       prdata_o_1_iv_0_7_0,
       prdata_o_1_iv_0_9,
       prdata_o_1_iv_10,
       prdata_o_1_iv_11,
       prdata_o_1_iv_9,
       prdata_o_1_iv_0_11_0,
       prdata_o_1_iv_0_11_2,
       prdata_o_1_iv_0_11_3,
       prdata_o_1_iv_0_12_0,
       prdata_o_1_iv_0_12_2,
       prdata_o_1_iv_0_10,
       USB_ULPI_DATA,
       MC_System_0_AMBA_SLAVE_0_PADDR,
       MC_System_0_AMBA_SLAVE_0_PWDATA,
       MC_System_0_FIC_0_LOCK,
       MC_System_0_FIC_0_CLK,
       MC_System_0_AMBA_SLAVE_0_PSELx,
       prdata_m2_e_5_6,
       prdata_m2_e_5_11,
       prdata_m2_e_5_1,
       prdata_N_5_mux_i_3_a0_7_1,
       prdata_o263,
       prdata_o274,
       prdata_m2_e_5_4,
       prdata_m2_e_5_10,
       prdata_N_5_mux_i_3_a0_11,
       prdata_N_5_mux_i_3_a0_10,
       prdata_N_5_mux_i_3_a0_4,
       prdata_N_5_mux_i_3_a0_0,
       prdata_N_5_mux_i_3_a0_12,
       prdata_N_5_mux_i_2_a0_11,
       prdata_N_5_mux_i_2_a0_10,
       prdata_N_5_mux_i_2_a0_4,
       prdata_N_5_mux_i_2_a0_0,
       prdata_N_5_mux_i_2_a0_12,
       prdata_m2_0_a2_1_0,
       prdata_m2_0_a2_17_0,
       N_358,
       prdata_m2_e_5_6_1,
       prdata_N_5_mux_i_1_a0_13,
       prdata_N_5_mux_i_1_a0_12,
       prdata_o277,
       prdata_o267,
       N_296,
       prdata_o259,
       N_225,
       prdata_o270,
       N_283,
       N_286,
       prdata_o260,
       prdata_m2_e_0_9,
       prdata_m2_e_0_10,
       prdata_m2_e_0_8,
       prdata_m2_e_27_11,
       prdata_m2_e_27_12,
       prdata_m2_e_27_10,
       prdata_N_5_mux_i_4_a0_12,
       prdata_N_5_mux_i_4_a0_13,
       prdata_N_5_mux_i_4_a0_11,
       m7_i_2,
       N_435_4,
       N_157,
       USB_ULPI_XCLK,
       USB_ULPI_STP,
       USB_ULPI_NXT,
       USB_ULPI_DIR,
       MC_System_0_AMBA_SLAVE_0_PENABLE,
       MC_System_0_AMBA_SLAVE_0_PWRITE,
       GPIO_0_M2F_c
    );
input  [2:2] FOC_TRANSFORMS_0_valpha_o;
input  FOC_TRANSFORMS_0_valpha_o_m_0;
input  FOC_TRANSFORMS_0_valpha_o_m_5;
input  [9:9] FOC_TRANSFORMS_0_ialpha_o_m;
input  [9:9] SPEED_ID_IQ_PI_0_iq_pi_output_o;
input  [9:9] adc_interface_0_result_ch3_o_m;
input  [19:19] MC_System_0_AMBA_SLAVE_0_PRDATA;
input  [0:0] SPEED_ID_IQ_PI_0_id_pi_output_o;
input  [0:0] HALL_INTERFACE_1_omega_out_o;
input  [0:0] FOC_TRANSFORMS_0_ialpha_o;
input  adc_interface_0_result_ch1_o_2;
input  adc_interface_0_result_ch1_o_0;
input  SEQ_CONTROLLER_0_state_o_2;
input  SEQ_CONTROLLER_0_state_o_0;
input  [0:0] adc_interface_0_result_ch0_o;
input  [0:0] FOC_TRANSFORMS_0_ibeta_o;
input  [1:1] prdata_o_1_0_iv_0_14;
input  [1:0] prdata_o_1_0_iv_0_15;
input  [1:1] prdata_o_1_0_iv_0_13;
input  [5:5] prdata_o_1_iv_10_0;
input  [5:5] FOC_TRANSFORMS_0_id_o_m;
input  [7:7] prdata_o_1_iv_13;
input  prdata_o_1_iv_14_0;
input  prdata_o_1_iv_14_2;
input  [7:7] prdata_o_1_iv_12;
input  [10:10] prdata_o_1_iv_10_12;
input  [10:10] prdata_o_1_iv_10_13;
input  [10:10] prdata_o_1_iv_10_11;
input  [12:12] prdata_o_1_iv_0_7;
input  [12:12] prdata_o_1_iv_0_6;
input  [13:13] prdata_o_1_iv_0_8;
input  [13:13] prdata_o_1_iv_0_7_0;
input  [14:14] prdata_o_1_iv_0_9;
input  [16:16] prdata_o_1_iv_10;
input  [16:16] prdata_o_1_iv_11;
input  [16:16] prdata_o_1_iv_9;
input  prdata_o_1_iv_0_11_0;
input  prdata_o_1_iv_0_11_2;
input  prdata_o_1_iv_0_11_3;
input  prdata_o_1_iv_0_12_0;
input  prdata_o_1_iv_0_12_2;
input  [15:14] prdata_o_1_iv_0_10;
inout  [7:0] USB_ULPI_DATA;
output [11:0] MC_System_0_AMBA_SLAVE_0_PADDR;
output [17:0] MC_System_0_AMBA_SLAVE_0_PWDATA;
output MC_System_0_FIC_0_LOCK;
output MC_System_0_FIC_0_CLK;
output MC_System_0_AMBA_SLAVE_0_PSELx;
input  prdata_m2_e_5_6;
input  prdata_m2_e_5_11;
input  prdata_m2_e_5_1;
input  prdata_N_5_mux_i_3_a0_7_1;
input  prdata_o263;
input  prdata_o274;
input  prdata_m2_e_5_4;
input  prdata_m2_e_5_10;
input  prdata_N_5_mux_i_3_a0_11;
input  prdata_N_5_mux_i_3_a0_10;
input  prdata_N_5_mux_i_3_a0_4;
input  prdata_N_5_mux_i_3_a0_0;
input  prdata_N_5_mux_i_3_a0_12;
input  prdata_N_5_mux_i_2_a0_11;
input  prdata_N_5_mux_i_2_a0_10;
input  prdata_N_5_mux_i_2_a0_4;
input  prdata_N_5_mux_i_2_a0_0;
input  prdata_N_5_mux_i_2_a0_12;
input  prdata_m2_0_a2_1_0;
input  prdata_m2_0_a2_17_0;
input  N_358;
input  prdata_m2_e_5_6_1;
input  prdata_N_5_mux_i_1_a0_13;
input  prdata_N_5_mux_i_1_a0_12;
input  prdata_o277;
input  prdata_o267;
input  N_296;
input  prdata_o259;
input  N_225;
input  prdata_o270;
input  N_283;
input  N_286;
input  prdata_o260;
input  prdata_m2_e_0_9;
input  prdata_m2_e_0_10;
input  prdata_m2_e_0_8;
input  prdata_m2_e_27_11;
input  prdata_m2_e_27_12;
input  prdata_m2_e_27_10;
input  prdata_N_5_mux_i_4_a0_12;
input  prdata_N_5_mux_i_4_a0_13;
input  prdata_N_5_mux_i_4_a0_11;
input  m7_i_2;
input  N_435_4;
input  N_157;
input  USB_ULPI_XCLK;
output USB_ULPI_STP;
input  USB_ULPI_NXT;
input  USB_ULPI_DIR;
output MC_System_0_AMBA_SLAVE_0_PENABLE;
output MC_System_0_AMBA_SLAVE_0_PWRITE;
output GPIO_0_M2F_c;

    wire GND, VCC;
    
    VCC VCC_Z (.Y(VCC));
    MC_System_sb MC_System_sb_0 (.FOC_TRANSFORMS_0_valpha_o({
        FOC_TRANSFORMS_0_valpha_o[2]}), .FOC_TRANSFORMS_0_valpha_o_m_0(
        FOC_TRANSFORMS_0_valpha_o_m_0), .FOC_TRANSFORMS_0_valpha_o_m_5(
        FOC_TRANSFORMS_0_valpha_o_m_5), .FOC_TRANSFORMS_0_ialpha_o_m({
        FOC_TRANSFORMS_0_ialpha_o_m[9]}), 
        .SPEED_ID_IQ_PI_0_iq_pi_output_o({
        SPEED_ID_IQ_PI_0_iq_pi_output_o[9]}), 
        .adc_interface_0_result_ch3_o_m({
        adc_interface_0_result_ch3_o_m[9]}), 
        .MC_System_0_AMBA_SLAVE_0_PRDATA({
        MC_System_0_AMBA_SLAVE_0_PRDATA[19]}), 
        .SPEED_ID_IQ_PI_0_id_pi_output_o({
        SPEED_ID_IQ_PI_0_id_pi_output_o[0]}), 
        .HALL_INTERFACE_1_omega_out_o({HALL_INTERFACE_1_omega_out_o[0]})
        , .FOC_TRANSFORMS_0_ialpha_o({FOC_TRANSFORMS_0_ialpha_o[0]}), 
        .adc_interface_0_result_ch1_o_2(adc_interface_0_result_ch1_o_2)
        , .adc_interface_0_result_ch1_o_0(
        adc_interface_0_result_ch1_o_0), .SEQ_CONTROLLER_0_state_o_2(
        SEQ_CONTROLLER_0_state_o_2), .SEQ_CONTROLLER_0_state_o_0(
        SEQ_CONTROLLER_0_state_o_0), .adc_interface_0_result_ch0_o({
        adc_interface_0_result_ch0_o[0]}), .FOC_TRANSFORMS_0_ibeta_o({
        FOC_TRANSFORMS_0_ibeta_o[0]}), .prdata_o_1_0_iv_0_14({
        prdata_o_1_0_iv_0_14[1]}), .prdata_o_1_0_iv_0_15({
        prdata_o_1_0_iv_0_15[1], prdata_o_1_0_iv_0_15[0]}), 
        .prdata_o_1_0_iv_0_13({prdata_o_1_0_iv_0_13[1]}), 
        .prdata_o_1_iv_10_0({prdata_o_1_iv_10_0[5]}), 
        .FOC_TRANSFORMS_0_id_o_m({FOC_TRANSFORMS_0_id_o_m[5]}), 
        .prdata_o_1_iv_13({prdata_o_1_iv_13[7]}), .prdata_o_1_iv_14_0(
        prdata_o_1_iv_14_0), .prdata_o_1_iv_14_2(prdata_o_1_iv_14_2), 
        .prdata_o_1_iv_12({prdata_o_1_iv_12[7]}), .prdata_o_1_iv_10_12({
        prdata_o_1_iv_10_12[10]}), .prdata_o_1_iv_10_13({
        prdata_o_1_iv_10_13[10]}), .prdata_o_1_iv_10_11({
        prdata_o_1_iv_10_11[10]}), .prdata_o_1_iv_0_7({
        prdata_o_1_iv_0_7[12]}), .prdata_o_1_iv_0_6({
        prdata_o_1_iv_0_6[12]}), .prdata_o_1_iv_0_8({
        prdata_o_1_iv_0_8[13]}), .prdata_o_1_iv_0_7_0({
        prdata_o_1_iv_0_7_0[13]}), .prdata_o_1_iv_0_9({
        prdata_o_1_iv_0_9[14]}), .prdata_o_1_iv_10({
        prdata_o_1_iv_10[16]}), .prdata_o_1_iv_11({
        prdata_o_1_iv_11[16]}), .prdata_o_1_iv_9({prdata_o_1_iv_9[16]})
        , .prdata_o_1_iv_0_11_0(prdata_o_1_iv_0_11_0), 
        .prdata_o_1_iv_0_11_2(prdata_o_1_iv_0_11_2), 
        .prdata_o_1_iv_0_11_3(prdata_o_1_iv_0_11_3), 
        .prdata_o_1_iv_0_12_0(prdata_o_1_iv_0_12_0), 
        .prdata_o_1_iv_0_12_2(prdata_o_1_iv_0_12_2), 
        .prdata_o_1_iv_0_10({prdata_o_1_iv_0_10[15], 
        prdata_o_1_iv_0_10[14]}), .USB_ULPI_DATA({USB_ULPI_DATA[7], 
        USB_ULPI_DATA[6], USB_ULPI_DATA[5], USB_ULPI_DATA[4], 
        USB_ULPI_DATA[3], USB_ULPI_DATA[2], USB_ULPI_DATA[1], 
        USB_ULPI_DATA[0]}), .MC_System_0_AMBA_SLAVE_0_PADDR_0(
        MC_System_0_AMBA_SLAVE_0_PADDR[0]), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_1(
        MC_System_0_AMBA_SLAVE_0_PADDR[1]), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_2(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_3(
        MC_System_0_AMBA_SLAVE_0_PADDR[3]), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_4(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_5(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_6(
        MC_System_0_AMBA_SLAVE_0_PADDR[6]), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_7(
        MC_System_0_AMBA_SLAVE_0_PADDR[7]), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_8(
        MC_System_0_AMBA_SLAVE_0_PADDR[8]), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_9(
        MC_System_0_AMBA_SLAVE_0_PADDR[9]), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_10(
        MC_System_0_AMBA_SLAVE_0_PADDR[10]), 
        .MC_System_0_AMBA_SLAVE_0_PADDR_11(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), 
        .MC_System_0_AMBA_SLAVE_0_PWDATA({
        MC_System_0_AMBA_SLAVE_0_PWDATA[17], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[16], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[15], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[14], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[13], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[12], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[11], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[10], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[9], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[8], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[7], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[6], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[5], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[4], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[3], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[2], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[1], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[0]}), .MC_System_0_FIC_0_LOCK(
        MC_System_0_FIC_0_LOCK), .MC_System_0_FIC_0_CLK(
        MC_System_0_FIC_0_CLK), .MC_System_0_AMBA_SLAVE_0_PSELx(
        MC_System_0_AMBA_SLAVE_0_PSELx), .prdata_m2_e_5_6(
        prdata_m2_e_5_6), .prdata_m2_e_5_11(prdata_m2_e_5_11), 
        .prdata_m2_e_5_1(prdata_m2_e_5_1), .prdata_N_5_mux_i_3_a0_7_1(
        prdata_N_5_mux_i_3_a0_7_1), .prdata_o263(prdata_o263), 
        .prdata_o274(prdata_o274), .prdata_m2_e_5_4(prdata_m2_e_5_4), 
        .prdata_m2_e_5_10(prdata_m2_e_5_10), .prdata_N_5_mux_i_3_a0_11(
        prdata_N_5_mux_i_3_a0_11), .prdata_N_5_mux_i_3_a0_10(
        prdata_N_5_mux_i_3_a0_10), .prdata_N_5_mux_i_3_a0_4(
        prdata_N_5_mux_i_3_a0_4), .prdata_N_5_mux_i_3_a0_0(
        prdata_N_5_mux_i_3_a0_0), .prdata_N_5_mux_i_3_a0_12(
        prdata_N_5_mux_i_3_a0_12), .prdata_N_5_mux_i_2_a0_11(
        prdata_N_5_mux_i_2_a0_11), .prdata_N_5_mux_i_2_a0_10(
        prdata_N_5_mux_i_2_a0_10), .prdata_N_5_mux_i_2_a0_4(
        prdata_N_5_mux_i_2_a0_4), .prdata_N_5_mux_i_2_a0_0(
        prdata_N_5_mux_i_2_a0_0), .prdata_N_5_mux_i_2_a0_12(
        prdata_N_5_mux_i_2_a0_12), .prdata_m2_0_a2_1_0(
        prdata_m2_0_a2_1_0), .prdata_m2_0_a2_17_0(prdata_m2_0_a2_17_0), 
        .N_358(N_358), .prdata_m2_e_5_6_1(prdata_m2_e_5_6_1), 
        .prdata_N_5_mux_i_1_a0_13(prdata_N_5_mux_i_1_a0_13), 
        .prdata_N_5_mux_i_1_a0_12(prdata_N_5_mux_i_1_a0_12), 
        .prdata_o277(prdata_o277), .prdata_o267(prdata_o267), .N_296(
        N_296), .prdata_o259(prdata_o259), .N_225(N_225), .prdata_o270(
        prdata_o270), .N_283(N_283), .N_286(N_286), .prdata_o260(
        prdata_o260), .prdata_m2_e_0_9(prdata_m2_e_0_9), 
        .prdata_m2_e_0_10(prdata_m2_e_0_10), .prdata_m2_e_0_8(
        prdata_m2_e_0_8), .prdata_m2_e_27_11(prdata_m2_e_27_11), 
        .prdata_m2_e_27_12(prdata_m2_e_27_12), .prdata_m2_e_27_10(
        prdata_m2_e_27_10), .prdata_N_5_mux_i_4_a0_12(
        prdata_N_5_mux_i_4_a0_12), .prdata_N_5_mux_i_4_a0_13(
        prdata_N_5_mux_i_4_a0_13), .prdata_N_5_mux_i_4_a0_11(
        prdata_N_5_mux_i_4_a0_11), .m7_i_2(m7_i_2), .N_435_4(N_435_4), 
        .N_157(N_157), .USB_ULPI_XCLK(USB_ULPI_XCLK), .USB_ULPI_STP(
        USB_ULPI_STP), .USB_ULPI_NXT(USB_ULPI_NXT), .USB_ULPI_DIR(
        USB_ULPI_DIR), .MC_System_0_AMBA_SLAVE_0_PENABLE(
        MC_System_0_AMBA_SLAVE_0_PENABLE), 
        .MC_System_0_AMBA_SLAVE_0_PWRITE(
        MC_System_0_AMBA_SLAVE_0_PWRITE), .GPIO_0_M2F_c(GPIO_0_M2F_c));
    GND GND_Z (.Y(GND));
    
endmodule


module PWM3PH(
       reset_i,
       sys_clk_i,
       en_pwm_i,
       en_dual_trig_i,
       va_i,
       vb_i,
       vc_i,
       pwm_period_i,
       dead_time_i,
       delay_time_i,
       midmatch_o,
       PWM_AH_o,
       PWM_BH_o,
       PWM_CH_o,
       PWM_AL_o,
       PWM_BL_o,
       PWM_CL_o
    );
input  reset_i;
input  sys_clk_i;
input  en_pwm_i;
input  en_dual_trig_i;
input  [17:0] va_i;
input  [17:0] vb_i;
input  [17:0] vc_i;
input  [17:0] pwm_period_i;
input  [17:0] dead_time_i;
input  [17:0] delay_time_i;
output midmatch_o;
output PWM_AH_o;
output PWM_BH_o;
output PWM_CH_o;
output PWM_AL_o;
output PWM_BL_o;
output PWM_CL_o;

    wire MSC_net_116;
    wire [17:0] s_pwm_counter;
    wire [17:0] s_delay_counter;
    wire [17:1] \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4 ;
    wire [8:0] \PWM_MIDMATCH_GEN_PROC.s_midmatch5_0_data_tmp ;
    wire [16:0] s_pwm_counter_cry;
    wire [17:0] s_pwm_counter_s;
    wire [17:0] s_delay_counter_s;
    wire [16:1] s_delay_counter_cry;
    wire [16:1] s_delay_counter_cry_Y;
    wire [17:17] s_delay_counter_s_FCO;
    wire [17:17] s_delay_counter_s_Y;
    wire [16:0] s_pwm_counter_cry_Y;
    wire [17:17] s_pwm_counter_s_FCO;
    wire [17:17] s_pwm_counter_s_Y;
    wire MSC_net_285, MSC_net_286, MSC_net_287, MSC_net_288, 
        MSC_net_289, MSC_net_290, MSC_net_291, MSC_net_292, 
        MSC_net_293, MSC_net_294, MSC_net_295, MSC_net_296, 
        MSC_net_297, MSC_net_298, MSC_net_299, MSC_net_300, 
        MSC_net_301, MSC_net_302, MSC_net_303, MSC_net_304, 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5 , 
        \PWM_OUTPUT_GEN.un1_va_i , \PWM_OUTPUT_GEN.un1_vb_i , 
        \PWM_OUTPUT_GEN.un1_vc_i , MSC_net_309, 
        \PWM_OUTPUT_GEN.PWM_AH_o6 , \PWM_OUTPUT_GEN.PWM_BH_o6 , 
        \PWM_OUTPUT_GEN.PWM_CH_o6 , MSC_net_313, MSC_net_314, 
        MSC_net_315, MSC_net_316, \PWM_OUTPUT_GEN.PWM_AH_o6_cry_0_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_1_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_2_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_3_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_4_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_5_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_6_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_7_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_8_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_9_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_10_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_11_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_12_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_13_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_14_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_15_Z , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_16_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_0_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_1_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_2_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_3_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_4_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_5_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_6_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_7_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_8_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_9_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_10_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_11_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_12_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_13_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_14_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_15_Z , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_16_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_0_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_1_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_2_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_3_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_4_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_5_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_6_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_7_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_8_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_9_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_10_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_11_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_12_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_13_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_14_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_15_Z , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_16_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_0_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_1_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_2_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_3_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_4_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_5_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_6_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_7_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_8_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_9_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_10_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_11_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_12_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_13_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_14_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_15_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_16_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_0_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_1_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_2_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_3_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_4_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_5_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_6_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_7_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_8_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_9_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_10_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_11_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_12_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_13_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_14_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_15_Z , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_16_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_0_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_1_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_2_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_3_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_4_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_5_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_6_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_7_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_8_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_9_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_10_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_11_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_12_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_13_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_14_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_15_Z , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_16_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_0_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_1_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_2_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_3_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_4_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_5_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_6_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_7_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_8_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_9_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_10_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_11_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_12_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_13_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_14_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_15_Z , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_16_Z , MSC_net_436, MSC_net_437, 
        MSC_net_438, MSC_net_439, MSC_net_440, MSC_net_441, 
        MSC_net_442, MSC_net_443, MSC_net_444, MSC_net_445, 
        MSC_net_446, MSC_net_447, MSC_net_448, MSC_net_449, 
        MSC_net_450, MSC_net_451, MSC_net_452, MSC_net_453, 
        MSC_net_454, MSC_net_455, MSC_net_456, 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_0_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_1_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_2_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_3_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_4_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_5_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_6_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_7_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_8_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_9_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_10_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_11_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_12_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_13_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_14_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_15_Z , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_16_Z , MSC_net_474, 
        \PWM_MIDMATCH_GEN_PROC.un1_s_pwm_counter_3_Z , 
        \PWM_MIDMATCH_GEN_PROC.un1_s_pwm_counter_9_Z , 
        \PWM_MIDMATCH_GEN_PROC.un1_s_pwm_counter_11_Z , 
        \PWM_MIDMATCH_GEN_PROC.un1_s_pwm_counter_12_Z , 
        \PWM_MIDMATCH_GEN_PROC.un1_s_pwm_counter_14_Z , 
        \PWM_MIDMATCH_GEN_PROC.un1_s_pwm_counter_15_Z , MSC_net_481, 
        MSC_net_482, MSC_net_483, MSC_net_484, MSC_net_485, 
        MSC_net_486, MSC_net_487, MSC_net_488, 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_16_RNIOO6E5_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_16_RNIOO6E5_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_14_RNIPKUS4_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_14_RNIPKUS4_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_12_RNI7T6E4_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_12_RNI7T6E4_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_10_RNIT9FV3_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_10_RNIT9FV3_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_8_RNIRQNG3_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_8_RNIRQNG3_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_6_RNIT8VP2_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_6_RNIT8VP2_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_4_RNI7R632_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_4_RNI7R632_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_2_RNIPHEC1_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_2_RNIPHEC1_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_1_RNIJCML_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_1_RNIJCML_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_17_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_17_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_16_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_16_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_15_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_15_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_14_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_14_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_13_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_13_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_12_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_12_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_11_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_11_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_10_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_10_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_9_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_9_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_8_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_8_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_7_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_7_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_6_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_6_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_5_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_5_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_4_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_4_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_3_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_3_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_2_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_2_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_1_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_1_Y , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_0_S , 
        \PWM_OUTPUT_GEN.PWM_AH_o6_cry_0_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_17_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_17_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_16_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_16_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_15_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_15_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_14_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_14_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_13_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_13_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_12_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_12_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_11_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_11_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_10_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_10_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_9_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_9_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_8_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_8_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_7_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_7_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_6_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_6_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_5_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_5_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_4_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_4_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_3_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_3_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_2_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_2_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_1_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_1_Y , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_0_S , 
        \PWM_OUTPUT_GEN.PWM_BH_o6_cry_0_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_17_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_17_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_16_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_16_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_15_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_15_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_14_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_14_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_13_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_13_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_12_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_12_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_11_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_11_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_10_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_10_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_9_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_9_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_8_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_8_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_7_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_7_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_6_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_6_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_5_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_5_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_4_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_4_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_3_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_3_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_2_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_2_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_1_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_1_Y , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_0_S , 
        \PWM_OUTPUT_GEN.PWM_CH_o6_cry_0_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_17_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_17_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_16_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_16_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_15_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_15_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_14_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_14_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_13_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_13_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_12_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_12_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_11_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_11_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_10_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_10_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_9_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_9_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_8_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_8_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_7_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_7_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_6_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_6_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_5_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_5_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_4_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_4_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_3_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_3_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_2_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_2_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_1_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_1_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_0_S , 
        \PWM_MIDMATCH_GEN_PROC.s_delay_counter5_cry_0_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_17_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_17_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_16_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_16_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_15_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_15_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_14_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_14_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_13_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_13_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_12_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_12_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_11_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_11_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_10_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_10_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_9_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_9_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_8_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_8_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_7_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_7_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_6_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_6_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_5_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_5_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_4_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_4_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_3_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_3_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_2_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_2_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_1_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_1_Y , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_0_S , 
        \PWM_OUTPUT_GEN.un1_va_i_cry_0_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_17_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_17_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_16_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_16_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_15_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_15_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_14_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_14_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_13_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_13_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_12_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_12_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_11_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_11_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_10_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_10_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_9_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_9_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_8_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_8_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_7_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_7_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_6_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_6_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_5_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_5_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_4_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_4_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_3_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_3_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_2_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_2_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_1_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_1_Y , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_0_S , 
        \PWM_OUTPUT_GEN.un1_vb_i_cry_0_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_17_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_17_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_16_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_16_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_15_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_15_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_14_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_14_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_13_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_13_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_12_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_12_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_11_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_11_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_10_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_10_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_9_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_9_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_8_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_8_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_7_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_7_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_6_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_6_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_5_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_5_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_4_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_4_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_3_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_3_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_2_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_2_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_1_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_1_Y , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_0_S , 
        \PWM_OUTPUT_GEN.un1_vc_i_cry_0_Y , MSC_net_759, MSC_net_760, 
        MSC_net_761, MSC_net_762, MSC_net_763, MSC_net_764, 
        MSC_net_765, MSC_net_766, MSC_net_767, MSC_net_768, 
        MSC_net_769, MSC_net_770, MSC_net_771, MSC_net_772, 
        MSC_net_773, MSC_net_774, MSC_net_775, MSC_net_776, 
        MSC_net_777, MSC_net_778, 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_16_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_s_17_FCO , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_s_17_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_15_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_14_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_13_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_12_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_11_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_10_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_9_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_8_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_7_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_6_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_5_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_4_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_3_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_2_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_1_Y , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_0_S , 
        \PWM_MIDMATCH_GEN_PROC.s_midmatch5_a_4_cry_0_Y , MSC_net_799, 
        MSC_net_800, MSC_net_801, MSC_net_802;
    assign PWM_AL_o = MSC_net_116;
    assign PWM_BL_o = MSC_net_116;
    assign PWM_CL_o = MSC_net_116;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
lk3frI469ll+VheoC4/q3QVUkPTsQDZk50nP+SaHROpftBXGzNDk912wqNpBiKHA
dE5mQVyNEBKwUrN+jFj38syaLzXJN0ZGRW7FWDyvxYW61jnLSS+n6b58F/uQ0ye/
oaxv8287PAPeFouO7mGj71d9dfcmF/3xiO8+DdZfop4=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=115570)
`pragma protect data_block
[encoded data, 113792 characters]

`pragma protect end_protected

endmodule


module SVM(
       reset_i,
       sys_clk_i,
       start_i,
       va_i,
       vb_i,
       vc_i,
       va3h_o,
       vb3h_o,
       vc3h_o,
       done_o
    );
input  reset_i;
input  sys_clk_i;
input  start_i;
input  [17:0] va_i;
input  [17:0] vb_i;
input  [17:0] vc_i;
output [17:0] va3h_o;
output [17:0] vb3h_o;
output [17:0] vc3h_o;
output done_o;

    wire [17:1] s_v3h;
    wire [17:1] s_min_value;
    wire [17:0] s_max_value;
    wire [1:0] s_state;
    wire [0:0] s_state_ns;
    wire [17:0] \SVM_FSM_PROC.s_max_value_8 ;
    wire [17:0] \SVM_FSM_PROC.s_min_value_8 ;
    wire [17:0] \SVM_FSM_PROC.s_min_value_8_am ;
    wire [17:0] \SVM_FSM_PROC.s_min_value_8_bm ;
    wire [17:0] \SVM_FSM_PROC.s_max_value_8_am ;
    wire [17:0] \SVM_FSM_PROC.s_max_value_8_bm ;
    wire MSC_net_275, MSC_net_276, MSC_net_277, MSC_net_278, 
        MSC_net_279, MSC_net_280, MSC_net_281, MSC_net_282, 
        MSC_net_283, MSC_net_284, MSC_net_285, MSC_net_286, 
        MSC_net_287, MSC_net_288, MSC_net_289, MSC_net_290, 
        MSC_net_291, MSC_net_292, MSC_net_293, MSC_net_294, 
        MSC_net_295, MSC_net_296, MSC_net_297, MSC_net_298, 
        MSC_net_299, MSC_net_300, MSC_net_301, MSC_net_302, 
        MSC_net_303, MSC_net_304, MSC_net_305, MSC_net_306, 
        MSC_net_307, MSC_net_308, MSC_net_309, MSC_net_310, 
        MSC_net_311, MSC_net_312, MSC_net_313, MSC_net_314, 
        MSC_net_315, MSC_net_316, MSC_net_317, MSC_net_318, 
        MSC_net_319, MSC_net_320, MSC_net_321, MSC_net_322, 
        MSC_net_323, MSC_net_324, MSC_net_325, MSC_net_326, 
        MSC_net_327, MSC_net_328, MSC_net_329, MSC_net_330, 
        MSC_net_331, MSC_net_332, MSC_net_333, MSC_net_334, 
        \SVM_FSM_PROC.s_min_value_8_sn_N_5 , 
        \SVM_FSM_PROC.s_max_value_8_sn_N_5 , MSC_net_337, MSC_net_338, 
        MSC_net_339, MSC_net_340, MSC_net_341, MSC_net_342, 
        MSC_net_343, MSC_net_344, MSC_net_345, MSC_net_346, 
        MSC_net_347, MSC_net_348, MSC_net_349, MSC_net_350, 
        MSC_net_351, MSC_net_352, MSC_net_353, MSC_net_354, 
        MSC_net_355, MSC_net_356, MSC_net_357, MSC_net_358, 
        MSC_net_359, MSC_net_360, MSC_net_361, MSC_net_362, 
        MSC_net_363, MSC_net_364, MSC_net_365, MSC_net_366, 
        MSC_net_367, MSC_net_368, MSC_net_369, MSC_net_370, 
        MSC_net_371, MSC_net_372, MSC_net_373, MSC_net_374, 
        MSC_net_375, MSC_net_376, MSC_net_377, MSC_net_378, 
        MSC_net_379, MSC_net_380, MSC_net_381, MSC_net_382, 
        MSC_net_383, MSC_net_384, MSC_net_385, MSC_net_386, 
        MSC_net_387, MSC_net_388, MSC_net_389, MSC_net_390, 
        MSC_net_391, MSC_net_392, MSC_net_393, MSC_net_394, 
        MSC_net_395, MSC_net_396, MSC_net_397, MSC_net_398, 
        MSC_net_399, MSC_net_400, MSC_net_401, MSC_net_402, 
        MSC_net_403, MSC_net_404, MSC_net_405, MSC_net_406, 
        MSC_net_407, MSC_net_408, MSC_net_409, MSC_net_410, 
        MSC_net_411, MSC_net_412, MSC_net_413, MSC_net_414, 
        MSC_net_415, MSC_net_416, MSC_net_417, MSC_net_418, 
        MSC_net_419, MSC_net_420, MSC_net_421, MSC_net_422, 
        MSC_net_423, MSC_net_424, MSC_net_425, MSC_net_426, 
        MSC_net_427, MSC_net_428, MSC_net_429, MSC_net_430, 
        MSC_net_431, MSC_net_432, MSC_net_433, MSC_net_434, 
        MSC_net_435, MSC_net_436, MSC_net_437, MSC_net_438, 
        MSC_net_439, MSC_net_440, MSC_net_441, MSC_net_442, 
        MSC_net_443, MSC_net_444, MSC_net_445, MSC_net_446, 
        MSC_net_447, MSC_net_448, MSC_net_449, MSC_net_450, 
        MSC_net_451, MSC_net_452, MSC_net_453, MSC_net_454, 
        MSC_net_455, MSC_net_456, MSC_net_457, MSC_net_458, 
        MSC_net_459, MSC_net_460, MSC_net_461, MSC_net_462, 
        MSC_net_463, MSC_net_464, MSC_net_465, MSC_net_466, 
        MSC_net_467, MSC_net_468, MSC_net_469, MSC_net_470, 
        MSC_net_471, MSC_net_472, MSC_net_473, MSC_net_474, 
        MSC_net_475, MSC_net_476, MSC_net_477, MSC_net_478, 
        MSC_net_479, MSC_net_480, MSC_net_481, MSC_net_482, 
        MSC_net_483, MSC_net_484, MSC_net_485, MSC_net_486, 
        MSC_net_487, MSC_net_488, MSC_net_489, MSC_net_490, 
        MSC_net_491, MSC_net_492, MSC_net_493, MSC_net_494, 
        MSC_net_495, MSC_net_496, MSC_net_497, MSC_net_498, 
        MSC_net_499, MSC_net_500, MSC_net_501, MSC_net_502, 
        MSC_net_503, MSC_net_504, MSC_net_505, MSC_net_506, 
        MSC_net_507, MSC_net_508, MSC_net_509, MSC_net_510, 
        MSC_net_511, MSC_net_512, MSC_net_513, MSC_net_514, 
        MSC_net_515, MSC_net_516, MSC_net_517, MSC_net_518, 
        MSC_net_519, MSC_net_520, MSC_net_521, MSC_net_522, 
        MSC_net_523, MSC_net_524, MSC_net_525, MSC_net_526, 
        MSC_net_527, MSC_net_528, MSC_net_529, MSC_net_530, 
        MSC_net_531, MSC_net_532, MSC_net_533, MSC_net_534, 
        MSC_net_535, MSC_net_536, MSC_net_537, MSC_net_538, 
        MSC_net_539, MSC_net_540, MSC_net_541, MSC_net_542, 
        MSC_net_543, MSC_net_544, MSC_net_545, MSC_net_546, 
        MSC_net_547, MSC_net_548, MSC_net_549, MSC_net_550, 
        MSC_net_551, MSC_net_552, MSC_net_553, MSC_net_554, 
        MSC_net_555, MSC_net_556, MSC_net_557, MSC_net_558, 
        MSC_net_559, MSC_net_560, MSC_net_561, MSC_net_562, 
        MSC_net_563, MSC_net_564, MSC_net_565, MSC_net_566, 
        MSC_net_567, MSC_net_568, MSC_net_569, MSC_net_570, 
        MSC_net_571, MSC_net_572, MSC_net_573, MSC_net_574, 
        MSC_net_575, MSC_net_576, MSC_net_577, MSC_net_578, 
        MSC_net_579, MSC_net_580, MSC_net_581, MSC_net_582, 
        MSC_net_583, MSC_net_584, MSC_net_585, MSC_net_586, 
        MSC_net_587, MSC_net_588, MSC_net_589, MSC_net_590, 
        MSC_net_591, MSC_net_592, MSC_net_593, MSC_net_594, 
        MSC_net_595, MSC_net_596, MSC_net_597, MSC_net_598, 
        MSC_net_599, MSC_net_600, MSC_net_601, MSC_net_602, 
        MSC_net_603, MSC_net_604, MSC_net_605, MSC_net_606, 
        MSC_net_607, MSC_net_608, MSC_net_609, MSC_net_610, 
        MSC_net_611, MSC_net_612, MSC_net_613, MSC_net_614, 
        MSC_net_615, MSC_net_616, MSC_net_617, MSC_net_618, 
        MSC_net_619, MSC_net_620, MSC_net_621, MSC_net_622, 
        MSC_net_623, MSC_net_624, MSC_net_625, MSC_net_626, 
        MSC_net_627, MSC_net_628, MSC_net_629, MSC_net_630, 
        MSC_net_631, MSC_net_632, MSC_net_633, MSC_net_634, 
        MSC_net_635, MSC_net_636, MSC_net_637, MSC_net_638, 
        MSC_net_639, MSC_net_640, MSC_net_641, MSC_net_642, 
        MSC_net_643, MSC_net_644, MSC_net_645, MSC_net_646;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
JS4ANfut9yefw9cHVJcaCjhW1vdDqbvpFlhZk9AY9cMhtyJ/X2v8lJ7u9tVyoMc/
oO+4bRMFJczOSbqeP5ZaY7qQ8JE0ODHpCJJS5C25ePs3peik/nz96kyhm5Ru1E1K
PFUBycxIMFJC+X2GmFPKhb4OisdZjuZuD2ZTGYa0Eb0=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=92650)
`pragma protect data_block
[encoded data, 91200 characters]
O9yepv1Cz89gx24Hxa1OTQ==

`pragma protect end_protected

endmodule


module mas_adc_scl_44s_18s_2s(
       s_product,
       adc_scale_val_i,
       s_mas_done,
       reset_i,
       sys_clk_i,
       s_mas_en,
       un1_s_mul1_1_axb_0_i_0,
       un1_s_mul1_1_cry_1_S,
       un1_s_mul1_1_cry_2_S,
       un1_s_mul1_1_cry_3_S,
       un1_s_mul1_1_cry_4_S,
       un1_s_mul1_1_cry_5_S,
       un1_s_mul1_1_cry_6_S,
       un1_s_mul1_1_cry_7_S,
       un1_s_mul1_1_cry_8_S,
       un1_s_mul1_1_cry_9_S,
       un1_s_mul1_1_cry_10_S,
       un1_s_mul1_1_cry_11_S,
       un1_s_mul1_1_cry_12_S,
       un1_s_mul1_1_cry_13_S,
       un1_s_mul1_1_cry_14_S,
       un1_s_mul1_1_cry_15_S,
       un1_s_mul1_1_cry_16_S,
       un1_s_mul1_1_s_17_S,
       un1_s_ia_0_sqmuxa_0
    );
output [25:8] s_product;
input  [17:0] adc_scale_val_i;
output s_mas_done;
input  reset_i;
input  sys_clk_i;
input  s_mas_en;
input  un1_s_mul1_1_axb_0_i_0;
input  un1_s_mul1_1_cry_1_S;
input  un1_s_mul1_1_cry_2_S;
input  un1_s_mul1_1_cry_3_S;
input  un1_s_mul1_1_cry_4_S;
input  un1_s_mul1_1_cry_5_S;
input  un1_s_mul1_1_cry_6_S;
input  un1_s_mul1_1_cry_7_S;
input  un1_s_mul1_1_cry_8_S;
input  un1_s_mul1_1_cry_9_S;
input  un1_s_mul1_1_cry_10_S;
input  un1_s_mul1_1_cry_11_S;
input  un1_s_mul1_1_cry_12_S;
input  un1_s_mul1_1_cry_13_S;
input  un1_s_mul1_1_cry_14_S;
input  un1_s_mul1_1_cry_15_S;
input  un1_s_mul1_1_cry_16_S;
input  un1_s_mul1_1_s_17_S;
input  un1_s_ia_0_sqmuxa_0;

    wire [0:0] mas_done_sync;
    wire [43:0] product_o_NC;
    wire [35:0] product_o;
    wire [43:36] product_o_ONC;
    wire MSC_net_148, MSC_net_149, MSC_net_150, MSC_net_151, 
        MSC_net_152, MSC_net_153, MSC_net_154, MSC_net_155, 
        MSC_net_156, MSC_net_157, MSC_net_158, MSC_net_159, 
        MSC_net_160, MSC_net_161, MSC_net_162, MSC_net_163, 
        MSC_net_164, MSC_net_165, MSC_net_166, MSC_net_167, 
        MSC_net_168, MSC_net_169, MSC_net_170, MSC_net_171, 
        MSC_net_172, MSC_net_173, MSC_net_174, MSC_net_175, 
        MSC_net_176, MSC_net_177, MSC_net_178, MSC_net_179, 
        MSC_net_180, MSC_net_181, MSC_net_182, MSC_net_183, 
        MSC_net_184, MSC_net_185, MSC_net_186, MSC_net_187, 
        MSC_net_188, MSC_net_189, MSC_net_190, MSC_net_191, 
        MSC_net_192, MSC_net_193, MSC_net_194;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
FBFLdk2NB8WR7DvCNX8ekcTVZ4dtGPN3G37kaKLa1qgiNGDZxh3NTmEggVKSQS/A
VNq0qDia3GkDIcQXXofz5agD6ZhtAeCkSQHDWtKr1gYp02EV8dyfNCRl1ptXUduV
oKIFCkPQ2bdS6yfK/8yZG1a2vOj6NUK1ChB3a3Q1aHo=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=8540)
`pragma protect data_block
[encoded data, 8384 characters]
EAxl46EljNpGIivYu0zZkw==

`pragma protect end_protected

endmodule


module ADC_SCALING_0s_12s_2s_8192_5_44s_0_1_2_3(
       reset_i,
       sys_clk_i,
       adc_results_rdy_i,
       adc_scale_val_i,
       adc_result_ch0_i,
       adc_result_ch1_i,
       fault_threshold_i,
       done_o,
       calib_done_o,
       over_current_fault_o,
       ia_adc_o,
       ib_adc_o
    );
input  reset_i;
input  sys_clk_i;
input  adc_results_rdy_i;
input  [17:0] adc_scale_val_i;
input  [11:0] adc_result_ch0_i;
input  [11:0] adc_result_ch1_i;
input  [17:0] fault_threshold_i;
output done_o;
output calib_done_o;
output over_current_fault_o;
output [17:0] ia_adc_o;
output [17:0] ib_adc_o;

    wire [11:1] un1_s_mul1_1_m;
    wire [25:8] s_product;
    wire [30:0] s_adc_ch0_offset;
    wire [30:0] s_adc_ch1_offset;
    wire [1:0] s_state;
    wire [1:0] s_state_ns;
    wire [17:0] inf_abs1;
    wire [17:0] inf_abs0;
    wire [13:0] s_calib_cnt;
    wire [12:0] s_calib_cnt_cry;
    wire [13:0] s_calib_cnt_s;
    wire [11:1] un1_s_mul1_0;
    wire [12:0] s_calib_cnt_cry_Y;
    wire [13:13] s_calib_cnt_s_FCO;
    wire [13:13] s_calib_cnt_s_Y;
    wire [0:0] s_calib_cnt_cry_cy_S;
    wire [0:0] s_calib_cnt_cry_cy_Y;
    wire MSC_net_302, MSC_net_303, MSC_net_304, MSC_net_305, 
        MSC_net_306, MSC_net_307, MSC_net_308, MSC_net_309, 
        MSC_net_310, MSC_net_311, MSC_net_312, MSC_net_313, 
        MSC_net_314, MSC_net_315, MSC_net_316, MSC_net_317, 
        MSC_net_318, MSC_net_319, MSC_net_320, MSC_net_321, 
        MSC_net_322, MSC_net_323, MSC_net_324, MSC_net_325, 
        MSC_net_326, MSC_net_327, MSC_net_328, MSC_net_329, 
        MSC_net_330, MSC_net_331, MSC_net_332, MSC_net_333, 
        MSC_net_334, MSC_net_335, MSC_net_336, MSC_net_337, 
        MSC_net_338, MSC_net_339, MSC_net_340, MSC_net_341, 
        MSC_net_342, MSC_net_343, MSC_net_344, MSC_net_345, 
        MSC_net_346, MSC_net_347, MSC_net_348, MSC_net_349, 
        MSC_net_350, MSC_net_351, MSC_net_352, MSC_net_353, 
        MSC_net_354, MSC_net_355, MSC_net_356, MSC_net_357, 
        MSC_net_358, MSC_net_359, MSC_net_360, MSC_net_361, 
        MSC_net_362, MSC_net_363, MSC_net_364, MSC_net_365, 
        MSC_net_366, MSC_net_367, MSC_net_368, MSC_net_369, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1 , 
        \OVER_CURRENT_FAULT_DET_PROC.over_current_fault_o5 , 
        MSC_net_373, MSC_net_374, MSC_net_375, MSC_net_376, 
        MSC_net_377, MSC_net_378, MSC_net_379, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_0_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_1_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_2_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_3_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_4_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_5_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_6_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_7_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_8_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_9_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_10_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_11_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_12_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_13_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_14_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_15_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_16_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_0_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_1_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_2_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_3_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_4_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_5_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_6_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_7_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_8_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_9_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_10_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_11_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_12_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_13_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_14_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_15_Z , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_16_Z , 
        MSC_net_414, MSC_net_415, MSC_net_416, MSC_net_417, 
        MSC_net_418, MSC_net_419, MSC_net_420, MSC_net_421, 
        MSC_net_422, MSC_net_423, MSC_net_424, MSC_net_425, 
        MSC_net_426, MSC_net_427, MSC_net_428, MSC_net_429, 
        MSC_net_430, MSC_net_431, MSC_net_432, MSC_net_433, 
        MSC_net_434, MSC_net_435, MSC_net_436, MSC_net_437, 
        MSC_net_438, MSC_net_439, MSC_net_440, MSC_net_441, 
        MSC_net_442, MSC_net_443, MSC_net_444, MSC_net_445, 
        MSC_net_446, MSC_net_447, MSC_net_448, MSC_net_449, 
        MSC_net_450, MSC_net_451, MSC_net_452, MSC_net_453, 
        MSC_net_454, MSC_net_455, MSC_net_456, MSC_net_457, 
        MSC_net_458, MSC_net_459, MSC_net_460, MSC_net_461, 
        MSC_net_462, MSC_net_463, MSC_net_464, MSC_net_465, 
        MSC_net_466, MSC_net_467, MSC_net_468, MSC_net_469, 
        MSC_net_470, MSC_net_471, MSC_net_472, MSC_net_473, 
        MSC_net_474, MSC_net_475, MSC_net_476, MSC_net_477, 
        MSC_net_478, MSC_net_479, MSC_net_480, MSC_net_481, 
        MSC_net_482, MSC_net_483, MSC_net_484, MSC_net_485, 
        MSC_net_486, MSC_net_487, MSC_net_488, MSC_net_489, 
        MSC_net_490, MSC_net_491, MSC_net_492, MSC_net_493, 
        MSC_net_494, MSC_net_495, MSC_net_496, MSC_net_497, 
        MSC_net_498, MSC_net_499, MSC_net_500, MSC_net_501, 
        MSC_net_502, MSC_net_503, MSC_net_504, MSC_net_505, 
        MSC_net_506, MSC_net_507, MSC_net_508, MSC_net_509, 
        MSC_net_510, MSC_net_511, MSC_net_512, MSC_net_513, 
        MSC_net_514, MSC_net_515, MSC_net_516, MSC_net_517, 
        MSC_net_518, MSC_net_519, MSC_net_520, MSC_net_521, 
        MSC_net_522, MSC_net_523, MSC_net_524, MSC_net_525, 
        MSC_net_526, MSC_net_527, MSC_net_528, MSC_net_529, 
        MSC_net_530, MSC_net_531, MSC_net_532, MSC_net_533, 
        MSC_net_534, MSC_net_535, MSC_net_536, MSC_net_537, 
        MSC_net_538, MSC_net_539, MSC_net_540, MSC_net_541, 
        MSC_net_542, MSC_net_543, MSC_net_544, MSC_net_545, 
        MSC_net_546, MSC_net_547, MSC_net_548, MSC_net_549, 
        MSC_net_550, MSC_net_551, MSC_net_552, MSC_net_553, 
        MSC_net_554, MSC_net_555, MSC_net_556, MSC_net_557, 
        \OVER_CURRENT_FAULT_DET_PROC.over_current_fault_o5_0_a3_RNO_S , 
        \OVER_CURRENT_FAULT_DET_PROC.over_current_fault_o5_0_a3_RNO_Y , 
        MSC_net_560, MSC_net_561, MSC_net_562, MSC_net_563, 
        MSC_net_564, MSC_net_565, MSC_net_566, MSC_net_567, 
        MSC_net_568, MSC_net_569, MSC_net_570, MSC_net_571, 
        MSC_net_572, MSC_net_573, MSC_net_574, MSC_net_575, 
        MSC_net_576, MSC_net_577, MSC_net_578, 
        \OVER_CURRENT_FAULT_DET_PROC.over_current_fault_o5_0_a3_RNO_0_S , 
        \OVER_CURRENT_FAULT_DET_PROC.over_current_fault_o5_0_a3_RNO_0_Y , 
        MSC_net_581, MSC_net_582, MSC_net_583, MSC_net_584, 
        MSC_net_585, MSC_net_586, MSC_net_587, MSC_net_588, 
        MSC_net_589, MSC_net_590, MSC_net_591, MSC_net_592, 
        MSC_net_593, MSC_net_594, MSC_net_595, MSC_net_596, 
        MSC_net_597, MSC_net_598, MSC_net_599, 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_16_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_16_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_15_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_15_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_14_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_14_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_13_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_13_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_12_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_12_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_11_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_11_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_10_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_10_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_9_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_9_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_8_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_8_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_7_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_7_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_6_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_6_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_5_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_5_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_4_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_4_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_3_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_3_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_2_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_2_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_1_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_1_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_0_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_cry_0_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_16_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_16_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_15_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_15_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_14_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_14_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_13_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_13_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_12_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_12_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_11_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_11_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_10_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_10_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_9_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_9_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_8_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_8_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_7_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_7_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_6_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_6_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_5_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_5_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_4_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_4_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_3_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_3_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_2_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_2_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_1_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_1_Y , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_0_S , 
        \OVER_CURRENT_FAULT_DET_PROC.un1_fault_threshold_i_1_cry_0_Y , 
        MSC_net_668, MSC_net_669, MSC_net_670, MSC_net_671, 
        MSC_net_672, MSC_net_673, MSC_net_674, MSC_net_675, 
        MSC_net_676, MSC_net_677, MSC_net_678, MSC_net_679, 
        MSC_net_680, MSC_net_681, MSC_net_682, MSC_net_683, 
        MSC_net_684, MSC_net_685, MSC_net_686, MSC_net_687, 
        MSC_net_688, MSC_net_689, MSC_net_690, MSC_net_691, 
        MSC_net_692, MSC_net_693, MSC_net_694, MSC_net_695, 
        MSC_net_696, MSC_net_697, MSC_net_698, MSC_net_699, 
        MSC_net_700, MSC_net_701, MSC_net_702, MSC_net_703, 
        MSC_net_704, MSC_net_705, MSC_net_706, MSC_net_707, 
        MSC_net_708, MSC_net_709, MSC_net_710, MSC_net_711, 
        MSC_net_712, MSC_net_713, MSC_net_714, MSC_net_715, 
        MSC_net_716, MSC_net_717, MSC_net_718, MSC_net_719, 
        MSC_net_720, MSC_net_721, MSC_net_722, MSC_net_723, 
        MSC_net_724, MSC_net_725, MSC_net_726, MSC_net_727, 
        MSC_net_728, MSC_net_729, MSC_net_730, MSC_net_731, 
        MSC_net_732, MSC_net_733, MSC_net_734, MSC_net_735, 
        MSC_net_736, MSC_net_737, MSC_net_738, MSC_net_739, 
        MSC_net_740, MSC_net_741, MSC_net_742, MSC_net_743, 
        MSC_net_744, MSC_net_745, MSC_net_746, MSC_net_747, 
        MSC_net_748, MSC_net_749, MSC_net_750, MSC_net_751, 
        MSC_net_752, MSC_net_753, MSC_net_754;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
Q3z12Oi9rlZmLyQHS6Pj/g3jfAm0c42YWPx12Ckhf65KYAo3XInJIiKb6/cZ0Ol7
guu2UQ3wlfRXyw/wmrkpYtMmGsSQYN4KJFLqdmRP0YTEx6APLOEg7u89U/69Q/mw
kz1igZ4LuN5XYc5DMqHP5jBLc1rS8cZyhFqeNAkcTwU=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=115660)
`pragma protect data_block
[encoded data, 113856 characters]
hPrRBbyOOPT5LqF2TSNTrQ==

`pragma protect end_protected

endmodule


module accumulator_olmng_18s(
       s_theta_buff,
       s_theta,
       reset_i,
       sys_clk_i,
       clear_buffer_i,
       s_olmng_done
    );
output [17:0] s_theta_buff;
input  [17:0] s_theta;
input  reset_i;
input  sys_clk_i;
input  clear_buffer_i;
input  s_olmng_done;

    wire [17:0] theta_scl_buff_o_3;
    wire MSC_net_58, MSC_net_59, MSC_net_60;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
LwYxXCKeh0ewrDjahn0mmHjuGanyGCJxa7rNTcHi5LrMBCLwkcHGuZfYVfXOWHGa
pr+lL+0F1JU4a0bFlICzHIihRYGSn5z5tljwSu2rRYrrkQrhpu7Rsdh+bEG5hw/I
BZejiFmSSKmRyikT4mZ3BHHArplkU2NTGp1bJgsJyBk=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=9210)
`pragma protect data_block
[encoded data, 9024 characters]
ji7v1pW7lBlrEqPi2sQyj0SqPRD/lTSP8k/UiRNP/m8=

`pragma protect end_protected

endmodule


module mas_olmng_44s_18s_2s(
       s_product,
       speed_ref_i,
       theta_factor_i,
       s_addc_input,
       s_mas_done,
       reset_i,
       sys_clk_i,
       s_mas_en,
       s_init_iqpi,
       s_state_88_d
    );
output [30:13] s_product;
input  [17:1] speed_ref_i;
input  [17:0] theta_factor_i;
input  [30:13] s_addc_input;
output s_mas_done;
input  reset_i;
input  sys_clk_i;
input  s_mas_en;
input  s_init_iqpi;
input  s_state_88_d;

    wire [0:0] mas_done_sync;
    wire [43:0] product_o_NC;
    wire [43:0] product_o;
    wire MSC_net_166, MSC_net_167, MSC_net_168;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
RrBo/CW5U/h5/nMsfZwfQhAzQry9BNzP15rpetiE3wnyIrZYyX9KW0CnXLD89KaE
Vtn4Kx/9NVApayBNSfXQYotJCm2Gp6M/vD4FPIZfFmK/pUcRoXR6UuPxpEkGeO7W
4JXTD0HfaeqNBOen1lInYoYAGPRhIs8RhwM/urSkSSo=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=8385)
`pragma protect data_block
[encoded data, 8256 characters]

`pragma protect end_protected

endmodule


module OLMNG_2s_13s_44s_0_2_3(
       reset_i,
       sys_clk_i,
       start_i,
       clear_buffer_i,
       direction_config_i,
       cl_status_i,
       theta_factor_i,
       speed_ref_i,
       dv_i,
       theta_cl_i,
       iq_ref_in_i,
       done_o,
       theta_o,
       init_speedpi_o,
       init_iqpi_o
    );
input  reset_i;
input  sys_clk_i;
input  start_i;
input  clear_buffer_i;
input  direction_config_i;
input  cl_status_i;
input  [17:0] theta_factor_i;
input  [17:0] speed_ref_i;
input  [17:0] dv_i;
input  [17:0] theta_cl_i;
input  [17:0] iq_ref_in_i;
output done_o;
output [17:0] theta_o;
output [17:0] init_speedpi_o;
output [17:0] init_iqpi_o;

    wire [30:13] s_addc_input;
    wire [17:0] s_theta_buff;
    wire [17:0] \THETA_SEL_PROC.s_theta_4 ;
    wire [17:0] s_theta_ol;
    wire [17:1] s_init_iqpi;
    wire [30:13] \inst.s_product ;
    wire [1:0] s_state;
    wire [0:0] s_state_ns;
    wire [17:1] init_speedpi_o_7;
    wire MSC_net_278, MSC_net_279, MSC_net_280, MSC_net_281, 
        MSC_net_282, MSC_net_283, MSC_net_284, MSC_net_285, 
        MSC_net_286, MSC_net_287, MSC_net_288, MSC_net_289, 
        MSC_net_290, MSC_net_291, MSC_net_292, MSC_net_293, 
        MSC_net_294, MSC_net_295, MSC_net_296, MSC_net_297, 
        MSC_net_298, MSC_net_299, MSC_net_300, MSC_net_301, 
        MSC_net_302, MSC_net_303, MSC_net_304, MSC_net_305, 
        MSC_net_306, MSC_net_307, MSC_net_308, MSC_net_309, 
        MSC_net_310, MSC_net_311, MSC_net_312, MSC_net_313, 
        MSC_net_314, MSC_net_315, MSC_net_316, MSC_net_317, 
        MSC_net_318, MSC_net_319, MSC_net_320, MSC_net_321, 
        MSC_net_322, MSC_net_323, MSC_net_324, MSC_net_325, 
        MSC_net_326, MSC_net_327, MSC_net_328, MSC_net_329, 
        MSC_net_330, MSC_net_331, MSC_net_332, MSC_net_333, 
        MSC_net_334, MSC_net_335, MSC_net_336, MSC_net_337, 
        MSC_net_338, MSC_net_339, MSC_net_340, MSC_net_341, 
        MSC_net_342, MSC_net_343, MSC_net_344, MSC_net_345, 
        MSC_net_346, MSC_net_347, MSC_net_348, MSC_net_349, 
        MSC_net_350, MSC_net_351, MSC_net_352, MSC_net_353, 
        MSC_net_354, MSC_net_355, MSC_net_356, MSC_net_357, 
        MSC_net_358, MSC_net_359, MSC_net_360, MSC_net_361, 
        MSC_net_362, MSC_net_363, MSC_net_364, MSC_net_365, 
        MSC_net_366, MSC_net_367, MSC_net_368, MSC_net_369, 
        MSC_net_370;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
SoyXzzqA3grZUd6F0A9bstfmiMiMAUfs4T2+ivUDydxczHT8boI0kEmFJvrM4+vJ
Up3Re4UBzMKxztMJVVfwy13Mf61UTJkGGbH2kYgebYrrfkgqldf4YfBvQxe2thZD
hvuTvbP83xEalnVOmVuKAKO2svqLv8QBxs7nskKUDLw=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=47255)
`pragma protect data_block
[encoded data, 46528 characters]

`pragma protect end_protected

endmodule


module accumulator_rl_18s(
       s_ref_val_buf,
       s_ramp_out,
       reset_i,
       sys_clk_i,
       N_680_i,
       reset_rl_i,
       s_rl_done
    );
output [16:0] s_ref_val_buf;
input  [17:0] s_ramp_out;
input  reset_i;
input  sys_clk_i;
output N_680_i;
input  reset_rl_i;
input  s_rl_done;

    wire [17:0] rl_out_prev_o_3;
    wire MSC_net_58, MSC_net_59, MSC_net_60;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
AlQUGjFM0YM2KJ9Fo1NMpvuDIoIAx2akTAHi4A5gylhMINdVBmGBvVFAVZ44iEir
3ScDAgWR9OTtY2HvUdgG+wpeN25TyEUoDVPGW+z4fHxETDNzMsQfPuhLRd9Al3Jn
xAgWrdh3HBu+aWulZy6AXgYtjIn0OIFVyHLeoXnr038=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=8885)
`pragma protect data_block
[encoded data, 8704 characters]
RJFJdDPjZMe13V25ZbQmmMAGIAYKZqeR9R/7qnIQjoQ=

`pragma protect end_protected

endmodule


module RATE_LIMITER(
       reset_i,
       sys_clk_i,
       start_i,
       soft_stop_i,
       reset_rl_i,
       direction_i,
       slew_count_i,
       rate_count_i,
       rl_in_i,
       rl_out_o,
       rl_done_o
    );
input  reset_i;
input  sys_clk_i;
input  start_i;
input  soft_stop_i;
input  reset_rl_i;
input  direction_i;
input  [17:0] slew_count_i;
input  [17:0] rate_count_i;
input  [17:0] rl_in_i;
output [17:0] rl_out_o;
output rl_done_o;

    wire [16:0] s_ref_val_buf;
    wire [17:1] s_set_ref;
    wire [18:0] s_count;
    wire [1:0] s_ramp_present_state;
    wire [1:1] s_ramp_present_state_ns;
    wire [17:0] s_ramp_out_8;
    wire [17:0] un2_s_rate_count_minus;
    wire [17:0] s_set_ref_5;
    wire [17:1] s_rl_in;
    wire [18:1] s_diff_Z;
    wire [18:1] s_rate_count_minus;
    wire [17:0] s_count_cry;
    wire [18:0] s_count_s;
    wire [0:0] s_ramp_present_state_i_0;
    wire [0:0] rate_count_i_i;
    wire [0:0] s_count_i;
    wire [16:16] un2_s_rate_count_minus_RNI4LS8I_Y;
    wire [17:17] s_ramp_out_8_RNO_FCO;
    wire [17:17] s_ramp_out_8_RNO_Y;
    wire [15:15] un2_s_rate_count_minus_RNIFGJAH_Y;
    wire [14:14] un2_s_rate_count_minus_RNITEACG_Y;
    wire [13:13] un2_s_rate_count_minus_RNIEG1EF_Y;
    wire [12:12] un2_s_rate_count_minus_RNI2LOFE_Y;
    wire [11:11] un2_s_rate_count_minus_RNIPSFHD_Y;
    wire [10:10] un2_s_rate_count_minus_RNIJ77JC_Y;
    wire [9:9] un2_s_rate_count_minus_RNIGLUKB_Y;
    wire [8:8] un2_s_rate_count_minus_RNI5D5HA_Y;
    wire [7:7] un2_s_rate_count_minus_RNIT7CD9_Y;
    wire [6:6] un2_s_rate_count_minus_RNIO5J98_Y;
    wire [5:5] un2_s_rate_count_minus_RNIM6Q57_Y;
    wire [4:4] un2_s_rate_count_minus_RNINA126_Y;
    wire [3:3] un2_s_rate_count_minus_RNIRH8U4_Y;
    wire [2:2] un2_s_rate_count_minus_RNI2SFQ3_Y;
    wire [1:1] un2_s_rate_count_minus_RNIC9NM2_Y;
    wire [0:0] un2_s_rate_count_minus_RNIPPUI1_Y;
    wire [17:17] s_count_RNIT51DM_Y;
    wire [18:18] s_count_RNO_FCO;
    wire [18:18] s_count_RNO_Y;
    wire [16:16] s_count_RNIGI45L_Y;
    wire [15:15] s_count_RNI408TJ_Y;
    wire [14:14] s_count_RNIPEBLI_Y;
    wire [13:13] s_count_RNIFUEDH_Y;
    wire [12:12] s_count_RNI6FI5G_Y;
    wire [11:11] s_count_RNIU0MTE_Y;
    wire [10:10] s_count_RNINJPLD_Y;
    wire [9:9] s_count_RNIH7TDC_Y;
    wire [8:8] s_count_RNIJBK8B_Y;
    wire [7:7] s_count_RNIMGB3A_Y;
    wire [6:6] s_count_RNIQM2U8_Y;
    wire [5:5] s_count_RNIVTPO7_Y;
    wire [4:4] s_count_RNI56HJ6_Y;
    wire [3:3] s_count_RNICF8E5_Y;
    wire [2:2] s_count_RNIKPV84_Y;
    wire [1:1] s_count_RNIT4N33_Y;
    wire [0:0] s_count_RNI7HEU1_Y;
    wire \FSM_RATE_LIM_PROC.un1_s_count_1 , 
        \FSM_RATE_LIM_PROC.un1_s_count_2 , 
        \FSM_RATE_LIM_PROC.un1_s_count_3 , 
        \FSM_RATE_LIM_PROC.un1_s_count_4 , 
        \FSM_RATE_LIM_PROC.un1_s_count_5 , 
        \FSM_RATE_LIM_PROC.un1_s_count_6 , 
        \FSM_RATE_LIM_PROC.un1_s_count_7 , 
        \FSM_RATE_LIM_PROC.un1_s_count_8 , 
        \FSM_RATE_LIM_PROC.un1_s_count_9 , 
        \FSM_RATE_LIM_PROC.un1_s_count_10 , 
        \FSM_RATE_LIM_PROC.un1_s_count_11 , 
        \FSM_RATE_LIM_PROC.un1_s_count_12 , 
        \FSM_RATE_LIM_PROC.un1_s_count_13 , 
        \FSM_RATE_LIM_PROC.un1_s_count_14 , 
        \FSM_RATE_LIM_PROC.un1_s_count_15 , 
        \FSM_RATE_LIM_PROC.un1_s_count_16 , 
        \FSM_RATE_LIM_PROC.un1_s_count_17 , MSC_net_338, MSC_net_339, 
        MSC_net_340, MSC_net_341, \FSM_RATE_LIM_PROC.s_ramp_out11 , 
        \FSM_RATE_LIM_PROC.un1_s_diff , 
        \FSM_RATE_LIM_PROC.un1_s_count , MSC_net_345, MSC_net_346, 
        MSC_net_347, MSC_net_348, MSC_net_349, 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_0_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_1_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_2_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_3_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_4_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_5_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_6_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_7_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_8_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_9_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_10_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_11_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_12_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_13_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_14_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_15_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_16_Z , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_17_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_0_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_1_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_2_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_3_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_4_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_5_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_6_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_7_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_8_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_9_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_10_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_11_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_12_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_13_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_14_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_15_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_16_Z , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_17_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_0_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_1_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_2_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_3_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_4_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_5_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_6_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_7_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_8_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_9_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_10_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_11_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_12_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_13_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_14_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_15_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_16_Z , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_17_Z , MSC_net_404, 
        MSC_net_405, MSC_net_406, MSC_net_407, MSC_net_408, 
        MSC_net_409, MSC_net_410, MSC_net_411, MSC_net_412, 
        MSC_net_413, MSC_net_414, MSC_net_415, MSC_net_416, 
        MSC_net_417, MSC_net_418, MSC_net_419, MSC_net_420, 
        MSC_net_421, MSC_net_422, MSC_net_423, MSC_net_424, 
        MSC_net_425, MSC_net_426, MSC_net_427, MSC_net_428, 
        MSC_net_429, MSC_net_430, MSC_net_431, MSC_net_432, 
        MSC_net_433, MSC_net_434, MSC_net_435, MSC_net_436, 
        MSC_net_437, MSC_net_438, MSC_net_439, MSC_net_440, 
        MSC_net_441, MSC_net_442, MSC_net_443, MSC_net_444, 
        MSC_net_445, MSC_net_446, MSC_net_447, MSC_net_448, 
        MSC_net_449, MSC_net_450, MSC_net_451, MSC_net_452, 
        MSC_net_453, MSC_net_454, MSC_net_455, MSC_net_456, 
        MSC_net_457, MSC_net_458, MSC_net_459, MSC_net_460, 
        MSC_net_461, MSC_net_462, MSC_net_463, MSC_net_464, 
        MSC_net_465, MSC_net_466, MSC_net_467, MSC_net_468, 
        MSC_net_469, MSC_net_470, MSC_net_471, MSC_net_472, 
        MSC_net_473, MSC_net_474, MSC_net_475, MSC_net_476, 
        MSC_net_477, MSC_net_478, MSC_net_479, MSC_net_480, 
        MSC_net_481, MSC_net_482, MSC_net_483, MSC_net_484, 
        MSC_net_485, MSC_net_486, MSC_net_487, MSC_net_488, 
        MSC_net_489, MSC_net_490, MSC_net_491, MSC_net_492, 
        MSC_net_493, MSC_net_494, MSC_net_495, MSC_net_496, 
        MSC_net_497, MSC_net_498, MSC_net_499, MSC_net_500, 
        MSC_net_501, MSC_net_502, MSC_net_503, MSC_net_504, 
        MSC_net_505, MSC_net_506, MSC_net_507, MSC_net_508, 
        MSC_net_509, MSC_net_510, MSC_net_511, MSC_net_512, 
        MSC_net_513, MSC_net_514, MSC_net_515, MSC_net_516, 
        MSC_net_517, \FSM_RATE_LIM_PROC.s_ramp_out11_cry_18_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_18_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_17_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_17_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_16_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_16_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_15_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_15_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_14_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_14_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_13_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_13_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_12_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_12_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_11_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_11_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_10_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_10_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_9_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_9_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_8_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_8_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_7_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_7_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_6_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_6_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_5_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_5_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_4_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_4_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_3_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_3_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_2_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_2_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_1_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_1_Y , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_0_S , 
        \FSM_RATE_LIM_PROC.s_ramp_out11_cry_0_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_18_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_18_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_17_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_17_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_16_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_16_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_15_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_15_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_14_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_14_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_13_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_13_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_12_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_12_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_11_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_11_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_10_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_10_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_9_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_9_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_8_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_8_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_7_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_7_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_6_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_6_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_5_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_5_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_4_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_4_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_3_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_3_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_2_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_2_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_1_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_1_Y , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_0_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_0_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_18_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_18_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_17_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_17_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_16_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_16_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_15_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_15_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_14_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_14_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_13_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_13_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_12_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_12_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_11_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_11_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_10_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_10_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_9_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_9_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_8_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_8_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_7_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_7_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_6_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_6_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_5_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_5_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_4_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_4_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_3_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_3_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_2_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_2_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_1_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_1_Y , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_0_S , 
        \FSM_RATE_LIM_PROC.un1_s_count_cry_0_Y , MSC_net_632, 
        MSC_net_633, MSC_net_634, MSC_net_635, MSC_net_636, 
        MSC_net_637, MSC_net_638, MSC_net_639, MSC_net_640, 
        MSC_net_641, MSC_net_642, MSC_net_643, MSC_net_644, 
        MSC_net_645, MSC_net_646, MSC_net_647, MSC_net_648, 
        MSC_net_649, MSC_net_650, MSC_net_651, MSC_net_652, 
        MSC_net_653, MSC_net_654, MSC_net_655, MSC_net_656, 
        MSC_net_657, MSC_net_658, MSC_net_659, MSC_net_660, 
        MSC_net_661, MSC_net_662, MSC_net_663, MSC_net_664, 
        MSC_net_665, MSC_net_666, MSC_net_667, MSC_net_668, 
        MSC_net_669, MSC_net_670, MSC_net_671, MSC_net_672, 
        MSC_net_673, MSC_net_674, MSC_net_675, MSC_net_676, 
        MSC_net_677, MSC_net_678, MSC_net_679, MSC_net_680, 
        MSC_net_681, MSC_net_682, MSC_net_683, MSC_net_684, 
        MSC_net_685, MSC_net_686, MSC_net_687, MSC_net_688, 
        MSC_net_689, MSC_net_690, MSC_net_691, MSC_net_692, 
        MSC_net_693, MSC_net_694, 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_18_RNI9D6F_S , 
        \FSM_RATE_LIM_PROC.un1_s_diff_cry_18_RNI9D6F_Y , MSC_net_697, 
        MSC_net_698, MSC_net_699, MSC_net_700, MSC_net_701, 
        MSC_net_702, MSC_net_703, MSC_net_704, MSC_net_705, 
        MSC_net_706, MSC_net_707, MSC_net_708, MSC_net_709, 
        MSC_net_710, MSC_net_711, MSC_net_712, MSC_net_713, 
        MSC_net_714, MSC_net_715, MSC_net_716, MSC_net_717, 
        MSC_net_718, MSC_net_719;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
ZjDPCY6EKgs2Npi6kd6XTBs4Tx63U2iC1URZKp1y3japeIE+D/WrZ4YXEQ3c4zyq
9HYdU8rKefr8etN7xxvF5lXrgHXvY12pkgPhQ5XK6tD8T95wpjMt/KnC0JdefkiV
cnLb5/xD982QotpSj2Lpw6mLJ4k6OiOI8+6b1qmfIwo=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=98000)
`pragma protect data_block
[encoded data, 96448 characters]
oDomAqyWj4urlStVuMmoKMFoDM9sja7GOSFRYLNIo/U=

`pragma protect end_protected

endmodule


module mas_pi_spi_44s_18s_2s(
       s_state,
       s_product,
       s_error,
       s_mult1_input_6,
       s_add_cin_5,
       s_mas_done,
       reset_i,
       sys_clk_i,
       s_mas_en,
       N_77_i_0,
       s_error_axb_0_i_0,
       un1_s_acc_in_0_sqmuxa_0
    );
input  [2:2] s_state;
output [43:0] s_product;
input  [17:1] s_error;
input  [17:0] s_mult1_input_6;
input  [43:0] s_add_cin_5;
output s_mas_done;
input  reset_i;
input  sys_clk_i;
input  s_mas_en;
output N_77_i_0;
input  s_error_axb_0_i_0;
input  un1_s_acc_in_0_sqmuxa_0;

    wire [0:0] mas_done_sync;
    wire [43:0] product_o_NC;
    wire MSC_net_176, MSC_net_177, MSC_net_178;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
kQS2HBa/2N1ujxvgGrHTdQV6PsKC+YCpyWz+SwpXsHTgtPpJQmzQwqfQzSCpSZ13
XC8M6T9Lq6WTABkDkWM7lMA4bJfRv/HxVdXSq8CGpF7d5qCJAugiFsI6cmquTQkb
neNW8ZSEOvxqhHyQS/A61gDRNBWNzDX+NMrOf+nKwEg=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=8690)
`pragma protect data_block
[encoded data, 8512 characters]
70QtKOgdNcUrbVo6HZR2pacJ5tk1rhzhH5k9Itf5hnQ=

`pragma protect end_protected

endmodule


module pi_controller_spi_18s_44s_2s_10s_16s_0_1_2_3_4(
       s_acc_in_0,
       s_acc_out,
       s_output_y,
       id_pi_act_input_i,
       s_pi_sel_i_0,
       s_pi_sel,
       iq_pi_ref_input_i,
       speed_pi_ref_input_i,
       speed_pi_kp_i,
       iq_pi_kp_i,
       speed_pi_ki_i,
       iq_pi_ki_i,
       s_act_input,
       reset_i,
       sys_clk_i,
       s_done,
       N_1498,
       N_1516,
       N_1499,
       N_1517,
       N_1500,
       N_1518,
       N_1501,
       N_1519,
       N_1502,
       N_1520,
       N_1503,
       N_1521,
       N_1504,
       N_1522,
       N_1505,
       N_1523,
       N_1506,
       N_1524,
       N_1507,
       N_1525,
       N_1508,
       N_1526,
       N_1509,
       N_1527,
       N_1510,
       N_1528,
       N_1511,
       N_1529,
       N_1512,
       N_1530,
       N_1513,
       N_1531,
       N_1533,
       N_1514,
       N_1532,
       N_1480,
       N_1481,
       N_1482,
       N_1483,
       N_1484,
       N_1485,
       N_1486,
       N_1487,
       N_1488,
       N_1489,
       N_1490,
       N_1491,
       N_1492,
       N_1493,
       N_1494,
       N_1495,
       N_1497,
       N_1496,
       s_en,
       output_y_o6_0,
       s_start
    );
input  [43:0] s_acc_in_0;
output [43:0] s_acc_out;
output [17:0] s_output_y;
input  [17:0] id_pi_act_input_i;
input  [1:1] s_pi_sel_i_0;
input  [1:0] s_pi_sel;
input  [17:17] iq_pi_ref_input_i;
input  [17:17] speed_pi_ref_input_i;
input  [17:0] speed_pi_kp_i;
input  [17:0] iq_pi_kp_i;
input  [17:0] speed_pi_ki_i;
input  [17:0] iq_pi_ki_i;
input  [0:0] s_act_input;
input  reset_i;
input  sys_clk_i;
output s_done;
input  N_1498;
input  N_1516;
input  N_1499;
input  N_1517;
input  N_1500;
input  N_1518;
input  N_1501;
input  N_1519;
input  N_1502;
input  N_1520;
input  N_1503;
input  N_1521;
input  N_1504;
input  N_1522;
input  N_1505;
input  N_1523;
input  N_1506;
input  N_1524;
input  N_1507;
input  N_1525;
input  N_1508;
input  N_1526;
input  N_1509;
input  N_1527;
input  N_1510;
input  N_1528;
input  N_1511;
input  N_1529;
input  N_1512;
input  N_1530;
input  N_1513;
input  N_1531;
input  N_1533;
input  N_1514;
input  N_1532;
input  N_1480;
input  N_1481;
input  N_1482;
input  N_1483;
input  N_1484;
input  N_1485;
input  N_1486;
input  N_1487;
input  N_1488;
input  N_1489;
input  N_1490;
input  N_1491;
input  N_1492;
input  N_1493;
input  N_1494;
input  N_1495;
input  N_1497;
input  N_1496;
input  s_en;
input  output_y_o6_0;
input  s_start;

    wire [15:0] s_piout;
    wire [16:0] s_piout_i;
    wire [43:0] s_acc_in;
    wire [43:0] s_inew;
    wire [43:0] s_product;
    wire [43:11] s_pout;
    wire [17:0] s_i_init_ds;
    wire [4:0] s_state;
    wire [43:0] acc_out_o_5;
    wire [17:1] output_y_o_5;
    wire [1:1] s_state_ns;
    wire [16:16] s_inew_RNIRGJE_S;
    wire [16:16] s_inew_RNIRGJE_Y;
    wire [11:11] s_pout_RNIO37T_S;
    wire [11:11] s_pout_RNIO37T_Y;
    wire [12:12] s_pout_RNINOQB1_S;
    wire [12:12] s_pout_RNINOQB1_Y;
    wire [13:13] s_pout_RNIOFEQ1_S;
    wire [13:13] s_pout_RNIOFEQ1_Y;
    wire [14:14] s_pout_RNII0392_S;
    wire [14:14] s_pout_RNII0392_Y;
    wire [15:15] s_pout_RNIEJNN2_S;
    wire [15:15] s_pout_RNIEJNN2_Y;
    wire [16:16] s_pout_RNIC8C63_S;
    wire [16:16] s_pout_RNIC8C63_Y;
    wire [17:17] s_pout_RNICV0L3_S;
    wire [17:17] s_pout_RNICV0L3_Y;
    wire [18:18] s_pout_RNIEOL34_S;
    wire [18:18] s_pout_RNIEOL34_Y;
    wire [19:19] s_pout_RNIIJAI4_S;
    wire [19:19] s_pout_RNIIJAI4_Y;
    wire [20:20] s_pout_RNIF8015_S;
    wire [20:20] s_pout_RNIF8015_Y;
    wire [21:21] s_pout_RNIEVLF5_S;
    wire [21:21] s_pout_RNIEVLF5_Y;
    wire [22:22] s_pout_RNIFOBU5_S;
    wire [22:22] s_pout_RNIFOBU5_Y;
    wire [23:23] s_pout_RNIIJ1D6_S;
    wire [23:23] s_pout_RNIIJ1D6_Y;
    wire [24:24] s_pout_RNIE8OR6_S;
    wire [24:24] s_pout_RNIE8OR6_Y;
    wire [25:25] s_pout_RNICVEA7_S;
    wire [25:25] s_pout_RNICVEA7_Y;
    wire [26:26] s_pout_RNICO5P7_S;
    wire [26:26] s_pout_RNICO5P7_Y;
    wire [27:27] s_pout_RNIEJS78_S;
    wire [27:27] s_pout_RNIEJS78_Y;
    wire [28:28] s_pout_RNIIGJM8_S;
    wire [28:28] s_pout_RNIIGJM8_Y;
    wire [29:29] s_pout_RNIOFA59_S;
    wire [29:29] s_pout_RNIOFA59_Y;
    wire [30:30] s_pout_RNIN82K9_S;
    wire [30:30] s_pout_RNIN82K9_Y;
    wire [31:31] s_pout_RNIO3Q2A_S;
    wire [31:31] s_pout_RNIO3Q2A_Y;
    wire [32:32] s_pout_RNIR0IHA_S;
    wire [32:32] s_pout_RNIR0IHA_Y;
    wire [33:33] s_pout_RNI00A0B_S;
    wire [33:33] s_pout_RNI00A0B_Y;
    wire [34:34] s_pout_RNIUO2FB_S;
    wire [34:34] s_pout_RNIUO2FB_Y;
    wire [35:35] s_pout_RNIUJRTB_S;
    wire [35:35] s_pout_RNIUJRTB_Y;
    wire [36:36] s_pout_RNI0HKCC_S;
    wire [36:36] s_pout_RNI0HKCC_Y;
    wire [37:37] s_pout_RNI4GDRC_S;
    wire [37:37] s_pout_RNI4GDRC_Y;
    wire [38:38] s_pout_RNI9G6AD_S;
    wire [38:38] s_pout_RNI9G6AD_Y;
    wire [39:39] s_pout_RNIFHVOD_S;
    wire [39:39] s_pout_RNIFHVOD_Y;
    wire [40:40] s_pout_RNIDBP7E_S;
    wire [40:40] s_pout_RNIDBP7E_Y;
    wire [41:41] s_pout_RNIC6JME_S;
    wire [41:41] s_pout_RNIC6JME_Y;
    wire [42:42] s_pout_RNIC2D5F_S;
    wire [42:42] s_pout_RNIC2D5F_Y;
    wire [43:43] s_pout_RNIES03G_FCO;
    wire [43:43] s_pout_RNIES03G_S;
    wire [43:43] s_pout_RNIES03G_Y;
    wire [43:43] s_pout_RNIDV6KF_S;
    wire [43:43] s_pout_RNIDV6KF_Y;
    wire [17:1] s_error;
    wire [15:0] s_piout_0_Z;
    wire [34:34] s_piout_i_0_0;
    wire [34:34] s_piout_i_0;
    wire [17:0] s_mult1_input_6_1_1;
    wire [17:0] s_mult1_input_6;
    wire [43:0] s_add_cin_5;
    wire [42:0] s_iout;
    wire [43:43] acc_out_o_5_b_A;
    wire MSC_net_774, MSC_net_775, MSC_net_776, MSC_net_777, 
        MSC_net_778, MSC_net_779, MSC_net_780, MSC_net_781, 
        MSC_net_782, MSC_net_783, MSC_net_784, MSC_net_785, 
        MSC_net_786, MSC_net_787, MSC_net_788, MSC_net_789, 
        MSC_net_790, MSC_net_791, MSC_net_792, MSC_net_793, 
        MSC_net_794, MSC_net_795, MSC_net_796, MSC_net_797, 
        MSC_net_798, MSC_net_799, MSC_net_800, MSC_net_801, 
        MSC_net_802, MSC_net_803, MSC_net_804, MSC_net_805, 
        MSC_net_806, MSC_net_807, MSC_net_808, MSC_net_809, 
        MSC_net_810, MSC_net_811, MSC_net_812, MSC_net_813, 
        MSC_net_814, MSC_net_815, MSC_net_816, MSC_net_817, 
        MSC_net_818, MSC_net_819, MSC_net_820, MSC_net_821, 
        MSC_net_822, MSC_net_823, MSC_net_824, MSC_net_825, 
        MSC_net_826, MSC_net_827, MSC_net_828, MSC_net_829, 
        MSC_net_830, MSC_net_831, MSC_net_832, MSC_net_833, 
        MSC_net_834, MSC_net_835, MSC_net_836, MSC_net_837, 
        MSC_net_838, MSC_net_839, MSC_net_840, MSC_net_841, 
        MSC_net_842, MSC_net_843, MSC_net_844, MSC_net_845, 
        MSC_net_846, MSC_net_847, MSC_net_848, MSC_net_849, 
        MSC_net_850, MSC_net_851, MSC_net_852, MSC_net_853, 
        MSC_net_854, MSC_net_855, MSC_net_856, MSC_net_857, 
        MSC_net_858, MSC_net_859, MSC_net_860, MSC_net_861, 
        MSC_net_862, MSC_net_863, MSC_net_864, MSC_net_865, 
        MSC_net_866, MSC_net_867, MSC_net_868, MSC_net_869, 
        MSC_net_870, MSC_net_871, MSC_net_872, MSC_net_873, 
        MSC_net_874, MSC_net_875, MSC_net_876, MSC_net_877, 
        MSC_net_878, MSC_net_879, MSC_net_880, MSC_net_881, 
        MSC_net_882, MSC_net_883, MSC_net_884, MSC_net_885, 
        MSC_net_886, MSC_net_887, MSC_net_888, MSC_net_889, 
        MSC_net_890, MSC_net_891, MSC_net_892, MSC_net_893, 
        MSC_net_894, MSC_net_895, MSC_net_896, MSC_net_897, 
        MSC_net_898, MSC_net_899, MSC_net_900, MSC_net_901, 
        MSC_net_902, MSC_net_903, MSC_net_904, MSC_net_905, 
        MSC_net_906, MSC_net_907, MSC_net_908, MSC_net_909, 
        MSC_net_910, MSC_net_911, MSC_net_912, MSC_net_913, 
        MSC_net_914, MSC_net_915, MSC_net_916, MSC_net_917, 
        MSC_net_918, MSC_net_919, MSC_net_920, MSC_net_921, 
        MSC_net_922, MSC_net_923, MSC_net_924, MSC_net_925, 
        MSC_net_926, MSC_net_927, MSC_net_928, MSC_net_929, 
        MSC_net_930, MSC_net_931, MSC_net_932, MSC_net_933, 
        MSC_net_934, MSC_net_935, MSC_net_936, MSC_net_937, 
        MSC_net_938, MSC_net_939, MSC_net_940, MSC_net_941, 
        MSC_net_942, MSC_net_943, MSC_net_944, MSC_net_945, 
        MSC_net_946, MSC_net_947, MSC_net_948, MSC_net_949, 
        MSC_net_950, MSC_net_951, MSC_net_952, MSC_net_953, 
        MSC_net_954, MSC_net_955, MSC_net_956, MSC_net_957, 
        MSC_net_958, MSC_net_959, MSC_net_960, MSC_net_961, 
        MSC_net_962, MSC_net_963, MSC_net_964, MSC_net_965, 
        MSC_net_966, MSC_net_967, MSC_net_968, MSC_net_969, 
        MSC_net_970, MSC_net_971, MSC_net_972, MSC_net_973, 
        MSC_net_974, MSC_net_975, MSC_net_976, MSC_net_977, 
        MSC_net_978, MSC_net_979, MSC_net_980, MSC_net_981, 
        MSC_net_982, MSC_net_983, MSC_net_984, MSC_net_985, 
        MSC_net_986, MSC_net_987, MSC_net_988, MSC_net_989, 
        MSC_net_990, MSC_net_991, MSC_net_992, MSC_net_993, 
        MSC_net_994, MSC_net_995, MSC_net_996, MSC_net_997, 
        MSC_net_998, MSC_net_999, MSC_net_1000, MSC_net_1001, 
        MSC_net_1002, MSC_net_1003, MSC_net_1004, MSC_net_1005, 
        MSC_net_1006, MSC_net_1007, MSC_net_1008, MSC_net_1009, 
        MSC_net_1010, MSC_net_1011, MSC_net_1012, MSC_net_1013, 
        MSC_net_1014, MSC_net_1015, MSC_net_1016, MSC_net_1017, 
        MSC_net_1018, MSC_net_1019, MSC_net_1020, MSC_net_1021, 
        MSC_net_1022, MSC_net_1023, MSC_net_1024, MSC_net_1025, 
        MSC_net_1026, MSC_net_1027, MSC_net_1028, MSC_net_1029, 
        MSC_net_1030, MSC_net_1031, MSC_net_1032, MSC_net_1033, 
        MSC_net_1034, MSC_net_1035, MSC_net_1036, MSC_net_1037, 
        MSC_net_1038, MSC_net_1039, MSC_net_1040, MSC_net_1041, 
        MSC_net_1042, MSC_net_1043, MSC_net_1044, MSC_net_1045, 
        MSC_net_1046, MSC_net_1047, MSC_net_1048, MSC_net_1049, 
        MSC_net_1050, MSC_net_1051, MSC_net_1052, MSC_net_1053, 
        MSC_net_1054, MSC_net_1055, MSC_net_1056, MSC_net_1057, 
        MSC_net_1058, MSC_net_1059, MSC_net_1060, MSC_net_1061, 
        MSC_net_1062, MSC_net_1063, MSC_net_1064, MSC_net_1065, 
        MSC_net_1066, MSC_net_1067, MSC_net_1068, MSC_net_1069, 
        MSC_net_1070, MSC_net_1071, MSC_net_1072, MSC_net_1073, 
        MSC_net_1074, MSC_net_1075, MSC_net_1076, MSC_net_1077, 
        MSC_net_1078, MSC_net_1079, MSC_net_1080, MSC_net_1081, 
        MSC_net_1082, MSC_net_1083, MSC_net_1084, MSC_net_1085, 
        MSC_net_1086, MSC_net_1087, MSC_net_1088, MSC_net_1089, 
        MSC_net_1090, MSC_net_1091, MSC_net_1092, MSC_net_1093, 
        MSC_net_1094, MSC_net_1095, MSC_net_1096, MSC_net_1097, 
        MSC_net_1098, MSC_net_1099, MSC_net_1100, MSC_net_1101, 
        MSC_net_1102, MSC_net_1103, MSC_net_1104, MSC_net_1105, 
        MSC_net_1106, MSC_net_1107, MSC_net_1108, MSC_net_1109, 
        MSC_net_1110, MSC_net_1111, MSC_net_1112, MSC_net_1113, 
        MSC_net_1114, MSC_net_1115, MSC_net_1116, MSC_net_1117, 
        MSC_net_1118, MSC_net_1119, MSC_net_1120, MSC_net_1121, 
        MSC_net_1122, MSC_net_1123, MSC_net_1124, MSC_net_1125, 
        MSC_net_1126, MSC_net_1127, MSC_net_1128, MSC_net_1129, 
        MSC_net_1130, MSC_net_1131, MSC_net_1132, MSC_net_1133, 
        MSC_net_1134, MSC_net_1135, MSC_net_1136, MSC_net_1137, 
        MSC_net_1138, MSC_net_1139, MSC_net_1140, MSC_net_1141, 
        MSC_net_1142, MSC_net_1143, MSC_net_1144, MSC_net_1145, 
        MSC_net_1146, MSC_net_1147, MSC_net_1148, MSC_net_1149, 
        MSC_net_1150, MSC_net_1151, MSC_net_1152, MSC_net_1153, 
        MSC_net_1154, MSC_net_1155, MSC_net_1156, MSC_net_1157, 
        MSC_net_1158, MSC_net_1159, MSC_net_1160, MSC_net_1161, 
        MSC_net_1162, MSC_net_1163, MSC_net_1164;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
NMiBU8cZEjGxGFlMrIITs6ISAeVp4fRLlAKuaTb2zn6qJInATKF0zYCQdr+2hDAT
940XfZP+kI4d+KxmnXXMVJxMBT+63oqBDZF8X8DeYLlDeFXJulGzFZi/p4NIW+4u
FGxnVBpWd9mzDiaXeq6DEW2XoB29cPVnTy08hrgowtg=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=159165)
`pragma protect data_block
[encoded data, 156672 characters]
9XbVcbE+43TC7/92zVaq6wNdRihRpvPE1lTdQeiiqxs=

`pragma protect end_protected

endmodule


module pi_scheduler_spi_18s_44s(
       s_pi_sel_i_0,
       s_pi_sel,
       speed_pi_output_o,
       iq_pi_output_o,
       id_pi_output_o,
       s_output_y,
       s_acc_out,
       speed_init_i,
       iq_init_i,
       iq_pi_ref_input_i,
       speed_pi_ref_input_i,
       iq_pi_act_input_i,
       speed_pi_act_input_i,
       s_acc_in,
       id_pi_act_input_i,
       s_act_input,
       reset_i,
       sys_clk_i,
       id_pi_done_o,
       s_done,
       iq_pi_done_o,
       s_start,
       idq_en_i,
       speed_en_i,
       s_en,
       clear_buffer_i,
       output_y_o6_0,
       speed_pi_start_i,
       iq_pi_start_i,
       N_1480,
       N_1481,
       N_1482,
       N_1483,
       N_1484,
       N_1485,
       N_1486,
       N_1487,
       N_1488,
       N_1489,
       N_1490,
       N_1491,
       N_1492,
       N_1493,
       N_1494,
       N_1495,
       N_1496,
       N_1497,
       N_1498,
       N_1499,
       N_1500,
       N_1501,
       N_1502,
       N_1503,
       N_1504,
       N_1505,
       N_1506,
       N_1507,
       N_1508,
       N_1509,
       N_1510,
       N_1511,
       N_1512,
       N_1513,
       N_1514,
       N_1516,
       N_1517,
       N_1518,
       N_1519,
       N_1520,
       N_1521,
       N_1522,
       N_1523,
       N_1524,
       N_1525,
       N_1526,
       N_1527,
       N_1528,
       N_1529,
       N_1530,
       N_1531,
       N_1532,
       N_1533,
       id_pi_start_i
    );
output [1:1] s_pi_sel_i_0;
output [1:0] s_pi_sel;
output [17:0] speed_pi_output_o;
output [17:0] iq_pi_output_o;
output [17:0] id_pi_output_o;
input  [17:0] s_output_y;
input  [43:0] s_acc_out;
input  [17:0] speed_init_i;
input  [17:0] iq_init_i;
input  [16:0] iq_pi_ref_input_i;
input  [16:0] speed_pi_ref_input_i;
input  [17:0] iq_pi_act_input_i;
input  [17:0] speed_pi_act_input_i;
output [43:0] s_acc_in;
input  [0:0] id_pi_act_input_i;
output [0:0] s_act_input;
input  reset_i;
input  sys_clk_i;
output id_pi_done_o;
input  s_done;
output iq_pi_done_o;
output s_start;
input  idq_en_i;
input  speed_en_i;
output s_en;
input  clear_buffer_i;
output output_y_o6_0;
input  speed_pi_start_i;
input  iq_pi_start_i;
output N_1480;
output N_1481;
output N_1482;
output N_1483;
output N_1484;
output N_1485;
output N_1486;
output N_1487;
output N_1488;
output N_1489;
output N_1490;
output N_1491;
output N_1492;
output N_1493;
output N_1494;
output N_1495;
output N_1496;
output N_1497;
output N_1498;
output N_1499;
output N_1500;
output N_1501;
output N_1502;
output N_1503;
output N_1504;
output N_1505;
output N_1506;
output N_1507;
output N_1508;
output N_1509;
output N_1510;
output N_1511;
output N_1512;
output N_1513;
output N_1514;
output N_1516;
output N_1517;
output N_1518;
output N_1519;
output N_1520;
output N_1521;
output N_1522;
output N_1523;
output N_1524;
output N_1525;
output N_1526;
output N_1527;
output N_1528;
output N_1529;
output N_1530;
output N_1531;
output N_1532;
output N_1533;
input  id_pi_start_i;

    wire [43:0] s_speed_pi_acc_in;
    wire [43:0] s_speed_pi_acc_in_4;
    wire [1:0] s_pi_sel_dly;
    wire [43:0] s_iq_acc_in;
    wire [43:0] s_id_acc_in;
    wire [17:0] speed_pi_output_y_o_5;
    wire MSC_net_534, MSC_net_535, MSC_net_536, MSC_net_537, 
        MSC_net_538, MSC_net_539, MSC_net_540, MSC_net_541, 
        MSC_net_542, MSC_net_543, MSC_net_544, MSC_net_545, 
        MSC_net_546, MSC_net_547, MSC_net_548, MSC_net_549, 
        MSC_net_550, MSC_net_551, MSC_net_552, MSC_net_553, 
        MSC_net_554, MSC_net_555, MSC_net_556, MSC_net_557, 
        MSC_net_558, MSC_net_559, MSC_net_560, MSC_net_561, 
        MSC_net_562, MSC_net_563, MSC_net_564, MSC_net_565, 
        MSC_net_566, MSC_net_567, MSC_net_568, MSC_net_569, 
        MSC_net_570, MSC_net_571, MSC_net_572, MSC_net_573, 
        MSC_net_574, MSC_net_575, MSC_net_576, MSC_net_577, 
        MSC_net_578, MSC_net_579, MSC_net_580, MSC_net_581, 
        MSC_net_582, MSC_net_583, MSC_net_584, MSC_net_585, 
        MSC_net_586, MSC_net_587, MSC_net_588, MSC_net_589, 
        MSC_net_590, MSC_net_591, MSC_net_592;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
pMehGibosZPZuQQ3IFbNoFYPliFjHdQo1rFQwPnBsDJBuYiaFMrUXujU6A7AY2J+
i2A43VJDgk1TOhSbniQ3/h6Eas0hmiGGLmC9Nq4YovKBIatHg+fZBspN1/IsJYah
zU/6uNSZehiXcBGLQb87AgDopRcQX1XHG2aDpj8kczw=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=104480)
`pragma protect data_block
[encoded data, 102848 characters]
A+PF8BsdIru+qbvmxH2C9A==

`pragma protect end_protected

endmodule


module SPEED_ID_IQ_PI_2s_44s(
       reset_i,
       sys_clk_i,
       clear_buffer_i,
       speed_en_i,
       idq_en_i,
       speed_pi_start_i,
       id_pi_start_i,
       iq_pi_start_i,
       speed_init_i,
       id_init_i,
       iq_init_i,
       speed_pi_ref_input_i,
       speed_pi_act_input_i,
       speed_pi_kp_i,
       speed_pi_ki_i,
       speed_pi_ymax_i,
       speed_pi_ymin_i,
       id_pi_ref_input_i,
       id_pi_act_input_i,
       id_pi_kp_i,
       id_pi_ki_i,
       idq_pi_ymax_i,
       idq_pi_ymin_i,
       iq_pi_ref_input_i,
       iq_pi_act_input_i,
       iq_pi_kp_i,
       iq_pi_ki_i,
       speed_pi_done_o,
       id_pi_done_o,
       iq_pi_done_o,
       speed_pi_output_o,
       id_pi_output_o,
       iq_pi_output_o
    );
input  reset_i;
input  sys_clk_i;
input  clear_buffer_i;
input  speed_en_i;
input  idq_en_i;
input  speed_pi_start_i;
input  id_pi_start_i;
input  iq_pi_start_i;
input  [17:0] speed_init_i;
input  [17:0] id_init_i;
input  [17:0] iq_init_i;
input  [17:0] speed_pi_ref_input_i;
input  [17:0] speed_pi_act_input_i;
input  [17:0] speed_pi_kp_i;
input  [17:0] speed_pi_ki_i;
input  [17:0] speed_pi_ymax_i;
input  [17:0] speed_pi_ymin_i;
input  [17:0] id_pi_ref_input_i;
input  [17:0] id_pi_act_input_i;
input  [17:0] id_pi_kp_i;
input  [17:0] id_pi_ki_i;
input  [17:0] idq_pi_ymax_i;
input  [17:0] idq_pi_ymin_i;
input  [17:0] iq_pi_ref_input_i;
input  [17:0] iq_pi_act_input_i;
input  [17:0] iq_pi_kp_i;
input  [17:0] iq_pi_ki_i;
output speed_pi_done_o;
output id_pi_done_o;
output iq_pi_done_o;
output [17:0] speed_pi_output_o;
output [17:0] id_pi_output_o;
output [17:0] iq_pi_output_o;

    wire [43:0] s_acc_out;
    wire [17:0] s_output_y;
    wire [1:0] \pi_scheduler_spi_inst.s_pi_sel ;
    wire [0:0] s_act_input;
    wire [43:0] s_acc_in;
    wire [1:1] \pi_scheduler_spi_inst.s_pi_sel_i_0 ;
    wire MSC_net_517, MSC_net_518, MSC_net_519, MSC_net_520, 
        \pi_controller_spi_inst.PI_CONT_FSM_PROC.output_y_o6_0 , 
        MSC_net_522, MSC_net_523, MSC_net_524, MSC_net_525, 
        MSC_net_526, MSC_net_527, MSC_net_528, MSC_net_529, 
        MSC_net_530, MSC_net_531, MSC_net_532, MSC_net_533, 
        MSC_net_534, MSC_net_535, MSC_net_536, MSC_net_537, 
        MSC_net_538, MSC_net_539, MSC_net_540, MSC_net_541, 
        MSC_net_542, MSC_net_543, MSC_net_544, MSC_net_545, 
        MSC_net_546, MSC_net_547, MSC_net_548, MSC_net_549, 
        MSC_net_550, MSC_net_551, MSC_net_552, MSC_net_553, 
        MSC_net_554, MSC_net_555, MSC_net_556, MSC_net_557, 
        MSC_net_558, MSC_net_559, MSC_net_560, MSC_net_561, 
        MSC_net_562, MSC_net_563, MSC_net_564, MSC_net_565, 
        MSC_net_566, MSC_net_567, MSC_net_568, MSC_net_569, 
        MSC_net_570, MSC_net_571, MSC_net_572, MSC_net_573, 
        MSC_net_574;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
nJEAB0r12iAvzkJIrGr6Le4uoZBUMuSWFySR1vx3qTSbW3ZdJYJfLCxVBAEIcJk+
lYh4nt7tQdHYdG6Mo+6LF4jTv+6KxOWrX9NcjtPnLbC0wbkSw7Ijk6rkTg6DWl3c
Dr+5RFYI3lHfAbKENtuGs7wV8xd13rIy4lqHi7/3ovc=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=18960)
`pragma protect data_block
[encoded data, 18624 characters]
vD+iaOB3aK8spg87Nt5GqgDEtxdCJs9s6u5+jAQ9RYU=

`pragma protect end_protected

endmodule


module SEQ_CONTROLLER_Z1_layer1(
       reset_i,
       sys_clk_i,
       fault_i,
       start_motor_i,
       stop_motor_i,
       fault_clear_i,
       speed_ref_i,
       speed_cl_i,
       vq_i,
       max_ar_i,
       calib_done_i,
       pwm_midmatch_i,
       foc_done_i,
       config_reg_i,
       adc_start_o,
       cl_status_o,
       en_idq_pi_o,
       en_pwm_o,
       motor_stopped_o,
       reset_rl_o,
       soft_stop_o,
       sensor_reset_o,
       state_o
    );
input  reset_i;
input  sys_clk_i;
input  fault_i;
input  start_motor_i;
input  stop_motor_i;
input  fault_clear_i;
input  [17:0] speed_ref_i;
input  [17:0] speed_cl_i;
input  [17:0] vq_i;
input  [3:0] max_ar_i;
input  calib_done_i;
input  pwm_midmatch_i;
input  foc_done_i;
input  [3:0] config_reg_i;
output adc_start_o;
output cl_status_o;
output en_idq_pi_o;
output en_pwm_o;
output motor_stopped_o;
output reset_rl_o;
output soft_stop_o;
output sensor_reset_o;
output [3:0] state_o;

    wire [8:0] s_state;
    wire [3:0] s_restart_count;
    wire [12:0] s_adctrig_count;
    wire [8:0] s_state_ns;
    wire [16:0] inf_abs1;
    wire [17:0] inf_abs0;
    wire [4:4] s_state_ns_i_m3_s;
    wire [3:3] s_state_ns_i_a2_3_0;
    wire [1:1] s_state_ns_i_o2_5_0_o2_1_1;
    wire [3:3] s_state_ns_i_a2_8_0_a1_0;
    wire [3:3] s_state_ns_i_a2_8_0_a0_3;
    wire [1:1] s_state_ns_i_o2_5_0_o2_a0_1_0;
    wire [4:4] s_state_ns_i_o3_0;
    wire [4:4] s_state_ns_i_a3_13_0;
    wire [11:0] s_adctrig_count_cry;
    wire [12:0] s_adctrig_count_s;
    wire [13:0] s_sensor_calib_count;
    wire [12:0] s_sensor_calib_count_cry;
    wire [13:0] s_sensor_calib_count_s;
    wire [0:0] s_state_ns_0_a2_4_1;
    wire [0:0] s_state_ns_0_a2_0;
    wire [0:0] s_state_ns_0_a2_2;
    wire [1:1] s_state_ns_i_o2_5_0_o2_a0_1_0_0;
    wire [6:6] s_state_ns_i_o3_2_i_o2_0_0;
    wire [3:3] s_state_ns_i_o3_3_0;
    wire [6:6] s_state_ns_i_o2_4_1_i_a2_0;
    wire [4:4] s_state_ns_i_o3_16_1;
    wire [3:3] s_state_ns_i_o3_20_1;
    wire [3:3] s_state_ns_i_3_7_a0_2;
    wire [0:0] s_state_ns_0_a2_0_3;
    wire [0:0] s_state_ns_0_a2_0_4;
    wire [5:5] s_state_ns_i_i_a2_i_8_1;
    wire [5:5] s_state_ns_i_i_a2_i_8_2;
    wire [5:5] s_state_ns_i_i_a2_i_8_3;
    wire [0:0] s_state_ns_0_0;
    wire [0:0] s_state_ns_0_1;
    wire [4:4] s_state_ns_i_a3_9_0;
    wire [2:2] s_state_ns_i_i_a2_i_0;
    wire [2:2] s_state_ns_i_i_a2_i_1;
    wire [2:2] s_state_ns_i_i_a2_i_2;
    wire [2:2] s_state_ns_i_i_a2_i_3;
    wire [4:4] s_state_ns_i_a2_6_0;
    wire [1:1] s_state_ns_i_0_2;
    wire [1:1] s_state_ns_i_0_5;
    wire [3:3] s_state_ns_i_3_2;
    wire [3:3] s_state_ns_i_3_3;
    wire [3:3] s_state_ns_i_3_5;
    wire [3:3] s_state_ns_i_3_8;
    wire [1:1] s_state_ns_i_0_5_1;
    wire [0:0] s_state_ns_0_1_0;
    wire [3:3] s_state_ns_i_3_2_1;
    wire [6:6] s_state_ns_i_m3_i_a2_1;
    wire [4:4] s_state_ns_i_o2_8_1;
    wire [3:3] s_state_ns_i_3_5_1;
    wire [4:4] s_state_ns_i_a2_6_1;
    wire [4:4] s_state_ns_i_o2_8_0_1;
    wire [3:3] s_state_ns_i_o3_19_2_d_0_1_1;
    wire [4:4] s_state_ns_i_o3_8cf0;
    wire [4:4] s_state_ns_i_o3_8cf1;
    wire [3:3] s_state_RNO_28;
    wire [3:3] s_state_RNO_23;
    wire [3:3] s_state_RNO_22;
    wire [3:3] s_state_RNO_16;
    wire [4:3] s_state_RNO_13;
    wire [4:4] s_state_ns_i_o2_8_0_1_1;
    wire [3:3] s_state_RNO_19;
    wire [4:4] s_state_ns_i_o3_8cf1_1_0;
    wire [4:4] s_state_ns_i_o3_8cf0_1_0;
    wire [4:4] s_state_RNO_11;
    wire [4:4] s_state_RNO_8;
    wire [3:3] s_state_ns_i_a2_3_RNO_0;
    wire [4:4] s_state_RNO_10;
    wire [4:4] s_state_RNO_6;
    wire [4:4] s_state_RNO_7;
    wire [12:12] s_sensor_calib_count_RNI8HE93_Y;
    wire [13:13] s_sensor_calib_count_RNO_FCO;
    wire [13:13] s_sensor_calib_count_RNO_Y;
    wire [11:11] s_sensor_calib_count_RNIVKI33_Y;
    wire [10:10] s_sensor_calib_count_RNINPMT2_Y;
    wire [9:9] s_sensor_calib_count_RNIGVQN2_Y;
    wire [8:8] s_sensor_calib_count_RNIH8CG2_Y;
    wire [7:7] s_sensor_calib_count_RNIJIT82_Y;
    wire [6:6] s_sensor_calib_count_RNIMTE12_Y;
    wire [5:5] s_sensor_calib_count_RNIQ90Q1_Y;
    wire [4:4] s_sensor_calib_count_RNIVMHI1_Y;
    wire [3:3] s_sensor_calib_count_RNI553B1_Y;
    wire [2:2] s_sensor_calib_count_RNICKK31_Y;
    wire [1:1] s_sensor_calib_count_RNIK46S_Y;
    wire [0:0] s_sensor_calib_count_RNITLNK_Y;
    wire [13:13] s_sensor_calib_count_RNI789D_S;
    wire [13:13] s_sensor_calib_count_RNI789D_Y;
    wire [11:11] s_adctrig_count_RNI4KHQB_Y;
    wire [12:12] s_adctrig_count_RNO_FCO;
    wire [12:12] s_adctrig_count_RNO_Y;
    wire [10:10] s_adctrig_count_RNIEF9JA_Y;
    wire [9:9] s_adctrig_count_RNIPB1C9_Y;
    wire [8:8] s_adctrig_count_RNICLBG8_Y;
    wire [7:7] s_adctrig_count_RNI00MK7_Y;
    wire [6:6] s_adctrig_count_RNILB0P6_Y;
    wire [5:5] s_adctrig_count_RNIBOAT5_Y;
    wire [4:4] s_adctrig_count_RNI26L15_Y;
    wire [3:3] s_adctrig_count_RNIQKV54_Y;
    wire [2:2] s_adctrig_count_RNIJ4AA3_Y;
    wire [1:1] s_adctrig_count_RNIDLKE2_Y;
    wire [0:0] s_adctrig_count_RNI87VI1_Y;
    wire [1:1] s_state_RNI4Q9N_S;
    wire [1:1] s_state_RNI4Q9N_Y;
    wire MSC_net_316, MSC_net_317, MSC_net_318, MSC_net_319, 
        MSC_net_320, \ADC_START_PROC.adc_start_o_4 , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2 , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1 , 
        \EN_SPEED_PI_PROC.cl_status_o5_Z , MSC_net_326, MSC_net_327, 
        MSC_net_328, MSC_net_329, MSC_net_330, MSC_net_331, 
        MSC_net_332, MSC_net_333, MSC_net_334, 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_0_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_1_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_2_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_3_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_4_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_5_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_6_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_7_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_8_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_9_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_10_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_11_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_12_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_13_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_14_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_15_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_16_Z , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_0_Z , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_1_Z , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_2_Z , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_3_Z , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_4_Z , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_5_Z , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_6_Z , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_7_Z , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_8_Z , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_9_Z , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_10_Z , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_11_Z , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_12_Z , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_13_Z , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_14_Z , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_15_Z , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_16_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_0_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_1_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_2_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_3_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_4_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_5_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_6_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_7_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_8_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_9_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_10_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_11_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_12_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_13_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_14 , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_15 , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_16 , MSC_net_386, 
        MSC_net_387, MSC_net_388, MSC_net_389, MSC_net_390, 
        MSC_net_391, MSC_net_392, MSC_net_393, MSC_net_394, 
        \FSM_SEQ_CONTROLLER_PROC.un1_s_sensor_calib_count_inv_Z , 
        MSC_net_396, MSC_net_397, MSC_net_398, MSC_net_399, 
        MSC_net_400, MSC_net_401, MSC_net_402, MSC_net_403, 
        MSC_net_404, MSC_net_405, 
        \FSM_SEQ_CONTROLLER_PROC.un1_config_reg_i , MSC_net_407, 
        MSC_net_408, MSC_net_409, MSC_net_410, MSC_net_411, 
        MSC_net_412, MSC_net_413, MSC_net_414, MSC_net_415, 
        MSC_net_416, MSC_net_417, MSC_net_418, MSC_net_419, 
        MSC_net_420, MSC_net_421, MSC_net_422, MSC_net_423, 
        \FSM_SEQ_CONTROLLER_PROC.un1_max_ar_i_NE , MSC_net_425, 
        MSC_net_426, \FSM_SEQ_CONTROLLER_PROC.s_state73 , MSC_net_428, 
        MSC_net_429, MSC_net_430, MSC_net_431, MSC_net_432, 
        MSC_net_433, MSC_net_434, MSC_net_435, MSC_net_436, 
        MSC_net_437, MSC_net_438, MSC_net_439, MSC_net_440, 
        MSC_net_441, MSC_net_442, \ADC_START_PROC.adc_start_o5_Z , 
        MSC_net_444, MSC_net_445, MSC_net_446, MSC_net_447, 
        MSC_net_448, MSC_net_449, MSC_net_450, MSC_net_451, 
        MSC_net_452, MSC_net_453, MSC_net_454, MSC_net_455, 
        MSC_net_456, MSC_net_457, MSC_net_458, MSC_net_459, 
        MSC_net_460, MSC_net_461, MSC_net_462, MSC_net_463, 
        MSC_net_464, MSC_net_465, MSC_net_466, MSC_net_467, 
        MSC_net_468, MSC_net_469, MSC_net_470, MSC_net_471, 
        MSC_net_472, MSC_net_473, MSC_net_474, MSC_net_475, 
        MSC_net_476, \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_1_9_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_1_12_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_1_14 , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_1_15_Z , MSC_net_481, 
        MSC_net_482, MSC_net_483, MSC_net_484, MSC_net_485, 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_1_14_4_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_1_14_5_Z , MSC_net_488, 
        \FSM_SEQ_CONTROLLER_PROC.un1_max_ar_i_NE_0_Z , MSC_net_490, 
        \FSM_SEQ_CONTROLLER_PROC.un1_s_sensor_calib_count_inv_6_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_s_sensor_calib_count_inv_7_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_s_sensor_calib_count_inv_8_Z , 
        \FSM_SEQ_CONTROLLER_PROC.un1_s_sensor_calib_count_inv_9_Z , 
        \ADC_START_PROC.adc_start_o5_7_Z , 
        \ADC_START_PROC.adc_start_o5_8_Z , MSC_net_497, 
        \FSM_SEQ_CONTROLLER_PROC.s_state75_0_o3_i_i2_0_o2_m3_e_1 , 
        MSC_net_499, MSC_net_500, MSC_net_501, MSC_net_502, 
        MSC_net_503, MSC_net_504, MSC_net_505, MSC_net_506, 
        MSC_net_507, MSC_net_508, MSC_net_509, MSC_net_510, 
        MSC_net_511, MSC_net_512, MSC_net_513, MSC_net_514, 
        MSC_net_515, MSC_net_516, MSC_net_517, MSC_net_518, 
        MSC_net_519, \ADC_START_PROC.adc_start_o5_1_Z , MSC_net_521, 
        MSC_net_522, MSC_net_523, MSC_net_524, MSC_net_525, 
        MSC_net_526, MSC_net_527, MSC_net_528, MSC_net_529, 
        MSC_net_530, MSC_net_531, MSC_net_532, MSC_net_533, 
        MSC_net_534, MSC_net_535, MSC_net_536, MSC_net_537, 
        MSC_net_538, MSC_net_539, MSC_net_540, MSC_net_541, 
        MSC_net_542, MSC_net_543, MSC_net_544, MSC_net_545, 
        MSC_net_546, MSC_net_547, MSC_net_548, MSC_net_549, 
        MSC_net_550, MSC_net_551, MSC_net_552, MSC_net_553, 
        MSC_net_554, MSC_net_555, MSC_net_556, MSC_net_557, 
        MSC_net_558, MSC_net_559, MSC_net_560, MSC_net_561, 
        MSC_net_562, MSC_net_563, MSC_net_564, MSC_net_565, 
        MSC_net_566, MSC_net_567, MSC_net_568, MSC_net_569, 
        MSC_net_570, MSC_net_571, MSC_net_572, MSC_net_573, 
        MSC_net_574, MSC_net_575, MSC_net_576, MSC_net_577, 
        MSC_net_578, MSC_net_579, MSC_net_580, MSC_net_581, 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_1_14_5_RNIC6S21_Z , 
        MSC_net_583, MSC_net_584, MSC_net_585, MSC_net_586, 
        MSC_net_587, MSC_net_588, MSC_net_589, MSC_net_590, 
        MSC_net_591, MSC_net_592, MSC_net_593, MSC_net_594, 
        MSC_net_595, MSC_net_596, MSC_net_597, MSC_net_598, 
        MSC_net_599, MSC_net_600, MSC_net_601, MSC_net_602, 
        MSC_net_603, MSC_net_604, MSC_net_605, MSC_net_606, 
        MSC_net_607, MSC_net_608, MSC_net_609, MSC_net_610, 
        MSC_net_611, MSC_net_612, MSC_net_613, MSC_net_614, 
        MSC_net_615, MSC_net_616, MSC_net_617, MSC_net_618, 
        MSC_net_619, MSC_net_620, MSC_net_621, MSC_net_622, 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_13_RNI1TAL_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_13_RNI1TAL_Y , 
        MSC_net_625, MSC_net_626, MSC_net_627, MSC_net_628, 
        MSC_net_629, MSC_net_630, MSC_net_631, MSC_net_632, 
        MSC_net_633, MSC_net_634, MSC_net_635, MSC_net_636, 
        MSC_net_637, MSC_net_638, MSC_net_639, MSC_net_640, 
        MSC_net_641, MSC_net_642, MSC_net_643, 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_17_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_17_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_16_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_16_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_15_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_15_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_14_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_14_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_13_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_13_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_12_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_12_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_11_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_11_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_10_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_10_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_9_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_9_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_8_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_8_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_7_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_7_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_6_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_6_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_5_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_5_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_4_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_4_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_3_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_3_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_2_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_2_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_1_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_1_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_0_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs0_2_cry_0_Y , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_17_S , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_17_Y , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_16_S , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_16_Y , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_15_S , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_15_Y , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_14_S , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_14_Y , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_13_S , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_13_Y , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_12_S , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_12_Y , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_11_S , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_11_Y , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_10_S , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_10_Y , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_9_S , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_9_Y , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_8_S , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_8_Y , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_7_S , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_7_Y , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_6_S , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_6_Y , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_5_S , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_5_Y , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_4_S , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_4_Y , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_3_S , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_3_Y , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_2_S , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_2_Y , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_1_S , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_1_Y , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_0_S , 
        \EN_SPEED_PI_PROC.un1_speed_cl_i_cry_0_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_13_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_13_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_12_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_12_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_11_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_11_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_10_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_10_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_9_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_9_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_8_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_8_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_7_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_7_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_6_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_6_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_5_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_5_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_4_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_4_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_3_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_3_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_2_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_2_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_1_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_1_Y , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_0_S , 
        \FSM_SEQ_CONTROLLER_PROC.un1_inf_abs1_cry_0_Y ;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
d31HWM4phqoYTc+NHHWftSY8HEYTI0faUSpJipQ5vDAre0ACCRn9qmYL2b4dnRa9
r8TMpfG/ZNplwcvN1a+q/G+LOhM2yNUcud/1yKpUl4Xgpc0sRQeEcOY3R1oTmVw/
jf+SSC6CbomWsMjrAdOkx7XRp+IjgpmsbDcRV3SAry0=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=131000)
`pragma protect data_block
[encoded data, 128960 characters]
ayAtW46T4jEuzprOj7RAZA==

`pragma protect end_protected

endmodule


module cordic_scale_18s_44s_0_1_2(
       s_xo_scale,
       s_product_from_mas,
       s_yo_scale,
       s_mul_a_from_cordic,
       s_yo,
       s_xo,
       reset_i,
       sys_clk_i,
       s_done_o,
       s_mas_en_from_cordic,
       s_mas_done_to_cordic,
       s_cordic_done
    );
output [17:0] s_xo_scale;
input  [26:9] s_product_from_mas;
output [17:0] s_yo_scale;
output [17:0] s_mul_a_from_cordic;
input  [17:0] s_yo;
input  [17:0] s_xo;
input  reset_i;
input  sys_clk_i;
output s_done_o;
output s_mas_en_from_cordic;
input  s_mas_done_to_cordic;
input  s_cordic_done;

    wire [1:0] s_state;
    wire MSC_net_116, MSC_net_117, MSC_net_118, MSC_net_119, 
        MSC_net_120, MSC_net_121, MSC_net_122, MSC_net_123, 
        MSC_net_124, MSC_net_125, MSC_net_126, MSC_net_127, 
        MSC_net_128, MSC_net_129, MSC_net_130, MSC_net_131, 
        MSC_net_132, MSC_net_133, MSC_net_134, MSC_net_135, 
        MSC_net_136, MSC_net_137, MSC_net_138, MSC_net_139, 
        MSC_net_140, MSC_net_141, MSC_net_142, MSC_net_143, 
        MSC_net_144;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
e8cfTtfyLzwXE7yYgCh2U1j2Hd6jhNLls82KgpVMSOpgsy9KHeC7dQDYv7ScFuz6
fivTMQ+xCHFQp/MEu37H72GT4EIMiDSXlUBrYaPxJmNnbJO82/InhIW3fOJVUs7+
OipZMa/Ud6U6Bf1fxwy7L8ltlZF8ovNX7v05ut5nDzE=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=22320)
`pragma protect data_block
[encoded data, 21952 characters]
KGSos4MZP7QNIZjrsVNRkg==

`pragma protect end_protected

endmodule


module cordic_rot_foc_18s_15s_0_1(
       s_theta,
       s_xo,
       s_yo,
       s_yi,
       s_xi,
       reset_i,
       sys_clk_i,
       s_cordic_done,
       start_ipark_i,
       start_park_i
    );
input  [17:0] s_theta;
output [17:0] s_xo;
output [17:0] s_yo;
input  [16:0] s_yi;
input  [16:0] s_xi;
input  reset_i;
input  sys_clk_i;
output s_cordic_done;
input  start_ipark_i;
input  start_park_i;

    wire [3:0] s_index;
    wire [3:1] s_index_5_iv_i_0;
    wire [17:1] s_yi_rot;
    wire [17:0] s_yi_rot_6;
    wire [0:0] s_index_5;
    wire [17:0] s_theta_i;
    wire [17:0] x_o_6;
    wire [17:0] y_o_6;
    wire [17:0] s_theta_c;
    wire [17:0] s_theta_c_9;
    wire [17:0] s_xi_rot;
    wire [17:0] s_xi_rot_6;
    wire [0:0] s_state;
    wire [17:0] un1_s_sum2;
    wire [17:0] un1_s_diff2;
    wire [15:12] un1_s_diff_theta_ns;
    wire [17:1] x_o_3;
    wire [17:17] s_theta_i_RNINO69_FCO;
    wire [17:17] s_theta_i_RNINO69_S;
    wire [17:17] s_theta_i_RNINO69_Y;
    wire [0:0] s_xi_rot_RNI4IUL_Y;
    wire [1:1] s_xi_rot_RNIICM21_Y;
    wire [2:2] s_xi_rot_RNI18EF1_Y;
    wire [3:3] s_xi_rot_RNIH46S1_Y;
    wire [4:4] s_xi_rot_RNI22U82_Y;
    wire [5:5] s_xi_rot_RNIK0ML2_Y;
    wire [6:6] s_xi_rot_RNI70E23_Y;
    wire [7:7] s_xi_rot_RNIR06F3_Y;
    wire [8:8] s_xi_rot_RNIG2UR3_Y;
    wire [9:9] s_xi_rot_RNI65M84_Y;
    wire [10:10] s_xi_rot_RNI4BEM4_Y;
    wire [11:11] s_xi_rot_RNI3I645_Y;
    wire [12:12] s_xi_rot_RNI3QUH5_Y;
    wire [13:13] s_xi_rot_RNI43NV5_Y;
    wire [14:14] s_xi_rot_RNI6DFD6_Y;
    wire [15:15] s_xi_rot_RNI9O7R6_Y;
    wire [17:17] s_xi_rot_RNIIHOM7_FCO;
    wire [17:17] s_xi_rot_RNIIHOM7_Y;
    wire [16:16] s_xi_rot_RNID4097_Y;
    wire [15:12] un1_s_diff_theta_bm;
    wire [15:12] un1_s_diff_theta_am;
    wire MSC_net_350, MSC_net_351, MSC_net_352, MSC_net_353, 
        MSC_net_354, MSC_net_355, MSC_net_356, MSC_net_357, 
        MSC_net_358, MSC_net_359, MSC_net_360, MSC_net_361, 
        MSC_net_362, MSC_net_363, MSC_net_364, MSC_net_365, 
        MSC_net_366, MSC_net_367, MSC_net_368, MSC_net_369, 
        MSC_net_370, MSC_net_371, MSC_net_372, MSC_net_373, 
        MSC_net_374, MSC_net_375, MSC_net_376, MSC_net_377, 
        MSC_net_378, MSC_net_379, MSC_net_380, MSC_net_381, 
        MSC_net_382, MSC_net_383, MSC_net_384, MSC_net_385, 
        MSC_net_386, MSC_net_387, MSC_net_388, MSC_net_389, 
        MSC_net_390, MSC_net_391, MSC_net_392, MSC_net_393, 
        MSC_net_394, MSC_net_395, MSC_net_396, MSC_net_397, 
        MSC_net_398, MSC_net_399, MSC_net_400, MSC_net_401, 
        MSC_net_402, MSC_net_403, MSC_net_404, MSC_net_405, 
        MSC_net_406, MSC_net_407, MSC_net_408, MSC_net_409, 
        MSC_net_410, MSC_net_411, MSC_net_412, MSC_net_413, 
        MSC_net_414, MSC_net_415, MSC_net_416, MSC_net_417, 
        MSC_net_418, MSC_net_419, MSC_net_420, MSC_net_421, 
        MSC_net_422, MSC_net_423, MSC_net_424, MSC_net_425, 
        MSC_net_426, MSC_net_427, MSC_net_428, MSC_net_429, 
        MSC_net_430, MSC_net_431, MSC_net_432, MSC_net_433, 
        MSC_net_434, MSC_net_435, MSC_net_436, MSC_net_437, 
        MSC_net_438, MSC_net_439, MSC_net_440, MSC_net_441, 
        MSC_net_442, MSC_net_443, MSC_net_444, MSC_net_445, 
        MSC_net_446, MSC_net_447, MSC_net_448, MSC_net_449, 
        MSC_net_450, MSC_net_451, MSC_net_452, MSC_net_453, 
        MSC_net_454, MSC_net_455, MSC_net_456, MSC_net_457, 
        MSC_net_458, MSC_net_459, MSC_net_460, MSC_net_461, 
        MSC_net_462, MSC_net_463, MSC_net_464, MSC_net_465, 
        MSC_net_466, MSC_net_467, MSC_net_468, MSC_net_469, 
        MSC_net_470, MSC_net_471, MSC_net_472, MSC_net_473, 
        MSC_net_474, MSC_net_475, MSC_net_476, MSC_net_477, 
        MSC_net_478, MSC_net_479, MSC_net_480, MSC_net_481, 
        MSC_net_482, MSC_net_483, MSC_net_484, MSC_net_485, 
        MSC_net_486, MSC_net_487, MSC_net_488, MSC_net_489, 
        MSC_net_490, MSC_net_491, MSC_net_492, MSC_net_493, 
        MSC_net_494, MSC_net_495, MSC_net_496, MSC_net_497, 
        MSC_net_498, MSC_net_499, MSC_net_500, MSC_net_501, 
        MSC_net_502, MSC_net_503, MSC_net_504, MSC_net_505, 
        MSC_net_506, MSC_net_507, MSC_net_508, MSC_net_509, 
        MSC_net_510, MSC_net_511, MSC_net_512, MSC_net_513, 
        MSC_net_514, MSC_net_515, MSC_net_516, MSC_net_517, 
        MSC_net_518, MSC_net_519, MSC_net_520, MSC_net_521, 
        MSC_net_522, MSC_net_523, MSC_net_524, MSC_net_525, 
        MSC_net_526, MSC_net_527, MSC_net_528, MSC_net_529, 
        MSC_net_530, MSC_net_531, MSC_net_532, MSC_net_533, 
        MSC_net_534, MSC_net_535, MSC_net_536, MSC_net_537, 
        MSC_net_538, MSC_net_539, MSC_net_540, MSC_net_541, 
        MSC_net_542, MSC_net_543, MSC_net_544, MSC_net_545, 
        MSC_net_546, MSC_net_547, MSC_net_548, MSC_net_549, 
        MSC_net_550, MSC_net_551, MSC_net_552, MSC_net_553, 
        MSC_net_554, MSC_net_555, MSC_net_556, MSC_net_557, 
        MSC_net_558, MSC_net_559, MSC_net_560, MSC_net_561, 
        MSC_net_562, MSC_net_563, MSC_net_564, MSC_net_565, 
        MSC_net_566, MSC_net_567, MSC_net_568, MSC_net_569, 
        MSC_net_570, MSC_net_571, MSC_net_572, MSC_net_573, 
        MSC_net_574, MSC_net_575, MSC_net_576, MSC_net_577, 
        MSC_net_578, MSC_net_579, MSC_net_580, MSC_net_581, 
        MSC_net_582, MSC_net_583, MSC_net_584, MSC_net_585, 
        MSC_net_586, MSC_net_587, MSC_net_588, MSC_net_589, 
        MSC_net_590, MSC_net_591, MSC_net_592, MSC_net_593, 
        MSC_net_594, MSC_net_595, MSC_net_596, MSC_net_597, 
        MSC_net_598, MSC_net_599, MSC_net_600, MSC_net_601, 
        MSC_net_602, MSC_net_603, MSC_net_604, MSC_net_605, 
        MSC_net_606, MSC_net_607, MSC_net_608, MSC_net_609, 
        MSC_net_610, MSC_net_611, MSC_net_612, MSC_net_613, 
        MSC_net_614, MSC_net_615, MSC_net_616, MSC_net_617, 
        MSC_net_618, MSC_net_619, MSC_net_620, MSC_net_621, 
        MSC_net_622, MSC_net_623, MSC_net_624, MSC_net_625, 
        MSC_net_626, MSC_net_627, MSC_net_628, MSC_net_629, 
        MSC_net_630, MSC_net_631, MSC_net_632, MSC_net_633, 
        MSC_net_634, MSC_net_635, MSC_net_636, MSC_net_637, 
        MSC_net_638, MSC_net_639, MSC_net_640, MSC_net_641, 
        MSC_net_642, MSC_net_643, MSC_net_644, MSC_net_645, 
        MSC_net_646, MSC_net_647, MSC_net_648, MSC_net_649, 
        MSC_net_650, MSC_net_651, MSC_net_652, MSC_net_653, 
        MSC_net_654, MSC_net_655, MSC_net_656, MSC_net_657, 
        MSC_net_658, MSC_net_659, MSC_net_660, MSC_net_661, 
        MSC_net_662, MSC_net_663, MSC_net_664, MSC_net_665, 
        MSC_net_666, MSC_net_667, MSC_net_668, MSC_net_669, 
        MSC_net_670, MSC_net_671, MSC_net_672, MSC_net_673, 
        MSC_net_674, MSC_net_675, MSC_net_676, MSC_net_677, 
        MSC_net_678, MSC_net_679, MSC_net_680, MSC_net_681, 
        MSC_net_682, MSC_net_683, MSC_net_684, MSC_net_685, 
        MSC_net_686, MSC_net_687, MSC_net_688, MSC_net_689, 
        MSC_net_690, MSC_net_691, MSC_net_692, MSC_net_693, 
        MSC_net_694, MSC_net_695, MSC_net_696, MSC_net_697, 
        MSC_net_698, MSC_net_699, MSC_net_700, MSC_net_701, 
        MSC_net_702, MSC_net_703, MSC_net_704, MSC_net_705, 
        MSC_net_706, MSC_net_707, MSC_net_708, MSC_net_709, 
        MSC_net_710, MSC_net_711, MSC_net_712, MSC_net_713, 
        MSC_net_714, MSC_net_715, MSC_net_716, MSC_net_717, 
        MSC_net_718, MSC_net_719, MSC_net_720, MSC_net_721, 
        MSC_net_722, MSC_net_723, MSC_net_724, MSC_net_725, 
        MSC_net_726, MSC_net_727, MSC_net_728, MSC_net_729, 
        MSC_net_730, MSC_net_731, MSC_net_732, MSC_net_733, 
        MSC_net_734, MSC_net_735, MSC_net_736, MSC_net_737, 
        MSC_net_738, MSC_net_739, MSC_net_740, MSC_net_741, 
        MSC_net_742, MSC_net_743, MSC_net_744, MSC_net_745, 
        MSC_net_746, MSC_net_747, MSC_net_748, MSC_net_749, 
        MSC_net_750, MSC_net_751, MSC_net_752, MSC_net_753, 
        MSC_net_754, MSC_net_755, MSC_net_756, MSC_net_757, 
        MSC_net_758, MSC_net_759, MSC_net_760, MSC_net_761, 
        MSC_net_762, MSC_net_763, MSC_net_764, MSC_net_765, 
        MSC_net_766, MSC_net_767, MSC_net_768, MSC_net_769, 
        MSC_net_770, MSC_net_771, MSC_net_772, MSC_net_773, 
        MSC_net_774, MSC_net_775, MSC_net_776, MSC_net_777, 
        MSC_net_778, MSC_net_779, MSC_net_780, MSC_net_781, 
        MSC_net_782, MSC_net_783, MSC_net_784, MSC_net_785, 
        MSC_net_786, MSC_net_787, MSC_net_788, MSC_net_789, 
        MSC_net_790, MSC_net_791, MSC_net_792, MSC_net_793, 
        MSC_net_794, MSC_net_795, MSC_net_796, MSC_net_797, 
        MSC_net_798, MSC_net_799, MSC_net_800, MSC_net_801, 
        MSC_net_802, MSC_net_803, MSC_net_804, MSC_net_805, 
        MSC_net_806, MSC_net_807, MSC_net_808, MSC_net_809, 
        MSC_net_810;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
pOqAuouER/HSS5SyTSN2NyZp4zqBMJUca8w3941/Fm5URfV4yTl+xb+qKk1rAVuB
FX9O1hXppwzbk5V0plpE46UJzInEoZS5l2mpv/sNRNyqDlg+QXNyRc85nTAoAMFD
yRG0r0HytDtIyMaNut+q2k+rj4TIkK21mKFRl7XmGEg=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=124215)
`pragma protect data_block
[encoded data, 122304 characters]

`pragma protect end_protected

endmodule


module cordic_scheduler_foc_18s_15s_44s(
       valpha_o,
       vbeta_o,
       id_o,
       iq_o,
       vd_i,
       ialpha_i,
       ibeta_i,
       vq_i,
       theta_i,
       s_product_from_mas,
       s_mul_a_from_cordic,
       start_park_i,
       reset_i,
       sys_clk_i,
       ipark_done_o,
       park_done_o,
       start_ipark_i,
       s_mas_en_from_cordic,
       s_mas_done_to_cordic
    );
output [17:0] valpha_o;
output [17:0] vbeta_o;
output [17:0] id_o;
output [17:0] iq_o;
input  [17:1] vd_i;
input  [17:1] ialpha_i;
input  [17:1] ibeta_i;
input  [17:1] vq_i;
input  [17:0] theta_i;
input  [26:9] s_product_from_mas;
output [17:0] s_mul_a_from_cordic;
input  start_park_i;
input  reset_i;
input  sys_clk_i;
output ipark_done_o;
output park_done_o;
input  start_ipark_i;
output s_mas_en_from_cordic;
input  s_mas_done_to_cordic;

    wire [17:0] s_xo_scale;
    wire [17:0] s_yo_scale;
    wire [16:0] s_xi;
    wire [16:0] s_yi;
    wire [17:0] s_theta;
    wire [17:0] s_xo;
    wire [17:0] s_yo;
    wire MSC_net_326, MSC_net_327, MSC_net_328, MSC_net_329, 
        MSC_net_330, MSC_net_331, MSC_net_332, MSC_net_333, 
        MSC_net_334;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
OlKc3VDhldZ5rDsaTGD0xiJ31a/cgksequP+yuyjmI+vuQdn/6SXg5OEKIs7UpBp
lja5My9FZ7Lf7Y6/tXnO9qB+ZuWAbyzp8hsOrOhNzOGSwQkXh6NT4jm0hiX0g8yt
qdqq+1Uq+hfnwIRJ9XZ1lUiBueW49dF7QnP8SUSdDNE=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=36120)
`pragma protect data_block
[encoded data, 35520 characters]
Oex+Y/Qu6uFmjIyMg4rDWmEGKoXgTzE1rZGlPNJrxJs=

`pragma protect end_protected

endmodule


module mas_scheduler_foc_18s_44s(
       s_mas_sel,
       s_mul_b_from_clarke,
       s_mul_b_from_iclarke,
       s_mul_b_to_mas_4,
       s_mul_b_to_mas_0,
       s_mul_a_from_cordic,
       s_mul_a_from_clarke,
       va_o,
       s_add_c_to_mas_33,
       s_add_c_to_mas_16,
       s_add_c_to_mas_15,
       s_add_c_to_mas_14,
       s_add_c_to_mas_13,
       s_add_c_to_mas_12,
       s_add_c_to_mas_11,
       s_add_c_to_mas_10,
       s_add_c_to_mas_9,
       s_add_c_to_mas_8,
       s_add_c_to_mas_7,
       s_add_c_to_mas_6,
       s_add_c_to_mas_5,
       s_add_c_to_mas_4,
       s_add_c_to_mas_3,
       s_add_c_to_mas_2,
       s_add_c_to_mas_1,
       s_add_c_to_mas_0,
       s_mul_a_from_iclarke,
       s_mul_a_to_mas,
       reset_i,
       sys_clk_i,
       start_iclarke_i,
       start_clarke_i,
       start_ipark_i,
       start_park_i,
       s_mas_en_from_cordic,
       s_mas_en_from_clarke,
       s_mas_done_from_mas,
       s_mas_done_to_cordic,
       s_mas_en_from_iclarke,
       s_mas_en_to_mas
    );
output [1:0] s_mas_sel;
input  [1:1] s_mul_b_from_clarke;
input  [2:2] s_mul_b_from_iclarke;
output s_mul_b_to_mas_4;
output s_mul_b_to_mas_0;
input  [17:0] s_mul_a_from_cordic;
input  [17:0] s_mul_a_from_clarke;
input  [17:0] va_o;
output s_add_c_to_mas_33;
output s_add_c_to_mas_16;
output s_add_c_to_mas_15;
output s_add_c_to_mas_14;
output s_add_c_to_mas_13;
output s_add_c_to_mas_12;
output s_add_c_to_mas_11;
output s_add_c_to_mas_10;
output s_add_c_to_mas_9;
output s_add_c_to_mas_8;
output s_add_c_to_mas_7;
output s_add_c_to_mas_6;
output s_add_c_to_mas_5;
output s_add_c_to_mas_4;
output s_add_c_to_mas_3;
output s_add_c_to_mas_2;
output s_add_c_to_mas_1;
output s_add_c_to_mas_0;
input  [17:0] s_mul_a_from_iclarke;
output [17:0] s_mul_a_to_mas;
input  reset_i;
input  sys_clk_i;
input  start_iclarke_i;
input  start_clarke_i;
input  start_ipark_i;
input  start_park_i;
input  s_mas_en_from_cordic;
input  s_mas_en_from_clarke;
input  s_mas_done_from_mas;
output s_mas_done_to_cordic;
input  s_mas_en_from_iclarke;
output s_mas_en_to_mas;

    wire MSC_net_126, MSC_net_127, MSC_net_128, MSC_net_129, 
        MSC_net_130, MSC_net_131, MSC_net_132, MSC_net_133, 
        MSC_net_134, MSC_net_135, MSC_net_136, MSC_net_137, 
        MSC_net_138, MSC_net_139, MSC_net_140, MSC_net_141, 
        MSC_net_142, MSC_net_143, MSC_net_144, MSC_net_145, 
        MSC_net_146, MSC_net_147, MSC_net_148, MSC_net_149;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
gRgvWXYp0rMP4vYMV9+iUdWVOd37QTme84H38jjbdC9Ahb25TwzbieTy65Z9XN6A
Zy+uBjxJ+gZdquocybRoGX0Tj2Dsp9tS1IiOfhtkxv/jFqV4GSuhzB1tqEKMPaNe
bHondWNcLJGbnf3JszXFZ5nih2WJsAeTsrC+sAw7PDI=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=13975)
`pragma protect data_block
[encoded data, 13760 characters]

`pragma protect end_protected

endmodule


module inverse_clarke_foc_18s_44s_1774_0_1(
       s_mul_a_from_iclarke,
       vbeta_i,
       s_product_from_mas,
       va_o,
       valpha_i,
       s_mul_b_from_iclarke,
       vc_o,
       vb_o,
       s_mas_sel,
       reset_i,
       sys_clk_i,
       iclarke_done_o,
       s_mas_en_from_iclarke,
       s_vca_axb_0_i_0,
       start_iclarke_i,
       s_mas_done_from_mas
    );
output [17:0] s_mul_a_from_iclarke;
input  [17:0] vbeta_i;
input  [28:11] s_product_from_mas;
output [17:0] va_o;
input  [17:0] valpha_i;
output [2:2] s_mul_b_from_iclarke;
output [17:0] vc_o;
output [17:1] vb_o;
input  [1:0] s_mas_sel;
input  reset_i;
input  sys_clk_i;
output iclarke_done_o;
output s_mas_en_from_iclarke;
output s_vca_axb_0_i_0;
input  start_iclarke_i;
input  s_mas_done_from_mas;

    wire [17:1] s_vc;
    wire [0:0] s_state;
    wire MSC_net_153, MSC_net_154, MSC_net_155, MSC_net_156, 
        MSC_net_157, MSC_net_158, MSC_net_159, MSC_net_160, 
        MSC_net_161, MSC_net_162, MSC_net_163, MSC_net_164, 
        MSC_net_165, MSC_net_166, MSC_net_167, MSC_net_168, 
        MSC_net_169, MSC_net_170, MSC_net_171, MSC_net_172, 
        MSC_net_173, MSC_net_174, MSC_net_175, MSC_net_176, 
        MSC_net_177, MSC_net_178, MSC_net_179, MSC_net_180, 
        MSC_net_181, MSC_net_182, MSC_net_183, MSC_net_184, 
        MSC_net_185, MSC_net_186, MSC_net_187, MSC_net_188, 
        MSC_net_189, MSC_net_190, MSC_net_191, MSC_net_192, 
        MSC_net_193, MSC_net_194, MSC_net_195, MSC_net_196, 
        MSC_net_197, MSC_net_198, MSC_net_199, MSC_net_200, 
        MSC_net_201, MSC_net_202, MSC_net_203, MSC_net_204, 
        MSC_net_205, MSC_net_206, MSC_net_207, MSC_net_208, 
        MSC_net_209, MSC_net_210, MSC_net_211, MSC_net_212, 
        MSC_net_213, MSC_net_214, MSC_net_215, MSC_net_216, 
        MSC_net_217, MSC_net_218, MSC_net_219, MSC_net_220, 
        MSC_net_221, MSC_net_222, MSC_net_223, MSC_net_224, 
        MSC_net_225, MSC_net_226, MSC_net_227, MSC_net_228, 
        MSC_net_229, MSC_net_230, MSC_net_231, MSC_net_232, 
        MSC_net_233, MSC_net_234;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
ADfkKfAq8yvuKESwAh7mqnwwJhmhoXRPx27ft1sGdtUrM+R0KL5KJXGrUpdZTKju
belEIGsVruoP0j85XAZbzO640qju/72i2Ex100QNfZSJaiotVFYduy7bHXfbPUEm
XxdTZnZFrbKhzo9r7RCvUy7Kfcf0rrjnRO29gKOvbwg=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=27715)
`pragma protect data_block
[encoded data, 27264 characters]
vh28Ev6l3YtFC13TTkbnyg==

`pragma protect end_protected

endmodule


module clarke_foc_18s_44s_591_0_1(
       ialpha_o,
       ia_i,
       ibeta_o,
       s_product_from_mas,
       s_mul_a_from_clarke,
       s_mul_b_from_clarke,
       ib_i,
       s_mas_sel,
       s_mul_b_from_iclarke,
       s_mul_b_to_mas_7,
       s_mul_b_to_mas_0,
       reset_i,
       sys_clk_i,
       s_mas_en_from_clarke,
       clarke_done_o,
       start_clarke_i,
       s_mas_done_from_mas
    );
output [17:0] ialpha_o;
input  [17:0] ia_i;
output [17:0] ibeta_o;
input  [26:9] s_product_from_mas;
output [17:0] s_mul_a_from_clarke;
output [1:1] s_mul_b_from_clarke;
input  [17:0] ib_i;
input  [1:0] s_mas_sel;
input  [2:2] s_mul_b_from_iclarke;
output s_mul_b_to_mas_7;
output s_mul_b_to_mas_0;
input  reset_i;
input  sys_clk_i;
output s_mas_en_from_clarke;
output clarke_done_o;
input  start_clarke_i;
input  s_mas_done_from_mas;

    wire [0:0] s_state;
    wire MSC_net_121, MSC_net_122, MSC_net_123, MSC_net_124, 
        MSC_net_125, MSC_net_126, MSC_net_127, MSC_net_128, 
        MSC_net_129, MSC_net_130, MSC_net_131, MSC_net_132, 
        MSC_net_133, MSC_net_134, MSC_net_135, MSC_net_136, 
        MSC_net_137, MSC_net_138, MSC_net_139, MSC_net_140, 
        MSC_net_141, MSC_net_142, MSC_net_143, MSC_net_144, 
        MSC_net_145, MSC_net_146, MSC_net_147, MSC_net_148, 
        MSC_net_149, MSC_net_150, MSC_net_151, MSC_net_152, 
        MSC_net_153, MSC_net_154, MSC_net_155, MSC_net_156, 
        MSC_net_157, MSC_net_158, MSC_net_159, MSC_net_160, 
        MSC_net_161, MSC_net_162, MSC_net_163, MSC_net_164, 
        MSC_net_165, MSC_net_166, MSC_net_167, MSC_net_168, 
        MSC_net_169, MSC_net_170, MSC_net_171, MSC_net_172, 
        MSC_net_173, MSC_net_174, MSC_net_175, MSC_net_176, 
        MSC_net_177, MSC_net_178, MSC_net_179, MSC_net_180, 
        MSC_net_181, MSC_net_182;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
MALO+3XMa1ZxI46B8UOQmx5TAyW9IrNJTUgX0ExxwLTuFC0/H8iRezdPcGMsN+hC
+cyUaUihGcSUBdHSPJp+RaOwkJoSLi1jKRSADTmzwNLwidkI3y5VYZdddBZhgY/g
jF+eQ73xEpyUSOX5XEkukq7V3kL4HsayTeFQNjN0/C4=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=23140)
`pragma protect data_block
[encoded data, 22784 characters]

`pragma protect end_protected

endmodule


module mas_foc_44s_18s_2s(
       s_product_from_mas,
       s_mul_a_to_mas,
       s_mul_b_to_mas_0,
       s_mul_b_to_mas_9,
       s_mul_b_to_mas_5,
       s_mul_b_to_mas_7,
       s_add_c_to_mas_0,
       s_add_c_to_mas_1,
       s_add_c_to_mas_2,
       s_add_c_to_mas_3,
       s_add_c_to_mas_4,
       s_add_c_to_mas_5,
       s_add_c_to_mas_6,
       s_add_c_to_mas_7,
       s_add_c_to_mas_8,
       s_add_c_to_mas_9,
       s_add_c_to_mas_10,
       s_add_c_to_mas_11,
       s_add_c_to_mas_12,
       s_add_c_to_mas_13,
       s_add_c_to_mas_14,
       s_add_c_to_mas_15,
       s_add_c_to_mas_16,
       s_add_c_to_mas_33,
       s_mas_done_from_mas,
       reset_i,
       sys_clk_i,
       s_mas_en_to_mas
    );
output [28:9] s_product_from_mas;
input  [17:0] s_mul_a_to_mas;
input  s_mul_b_to_mas_0;
input  s_mul_b_to_mas_9;
input  s_mul_b_to_mas_5;
input  s_mul_b_to_mas_7;
input  s_add_c_to_mas_0;
input  s_add_c_to_mas_1;
input  s_add_c_to_mas_2;
input  s_add_c_to_mas_3;
input  s_add_c_to_mas_4;
input  s_add_c_to_mas_5;
input  s_add_c_to_mas_6;
input  s_add_c_to_mas_7;
input  s_add_c_to_mas_8;
input  s_add_c_to_mas_9;
input  s_add_c_to_mas_10;
input  s_add_c_to_mas_11;
input  s_add_c_to_mas_12;
input  s_add_c_to_mas_13;
input  s_add_c_to_mas_14;
input  s_add_c_to_mas_15;
input  s_add_c_to_mas_16;
input  s_add_c_to_mas_33;
output s_mas_done_from_mas;
input  reset_i;
input  sys_clk_i;
input  s_mas_en_to_mas;

    wire [0:0] mas_done_sync;
    wire [43:0] product_o_NC;
    wire [43:0] product_o;
    wire MSC_net_153, MSC_net_154, MSC_net_155;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
iou0kmcuHQ1zzDJNWfKWWGowQGujitQZDnBQEADtTA9uN0kLFbUbWRnLH2iZI+dX
Y3O6mxOBll6jBBPS+/7TbmGIEILUBnduvIPufILJxp/P42O3hekXCT1/AlTZDiQh
FsqZvzg3GMSEPPwqavVyaxbIeAwcEaGlKYlB0gvMlEk=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=8885)
`pragma protect data_block
[encoded data, 8704 characters]
iAoBKmQf+Dlu0tn3lYQEZAoVrKcEuqTetaEIG/ahf0Y=

`pragma protect end_protected

endmodule


module FOC_TRANSFORMS_2s_44s(
       reset_i,
       sys_clk_i,
       start_clarke_i,
       start_park_i,
       start_ipark_i,
       start_iclarke_i,
       ia_i,
       ib_i,
       ialpha_i,
       ibeta_i,
       vd_i,
       vq_i,
       valpha_i,
       vbeta_i,
       theta_i,
       clarke_done_o,
       park_done_o,
       ipark_done_o,
       iclarke_done_o,
       ialpha_o,
       ibeta_o,
       id_o,
       iq_o,
       valpha_o,
       vbeta_o,
       va_o,
       vb_o,
       vc_o
    );
input  reset_i;
input  sys_clk_i;
input  start_clarke_i;
input  start_park_i;
input  start_ipark_i;
input  start_iclarke_i;
input  [17:0] ia_i;
input  [17:0] ib_i;
input  [17:0] ialpha_i;
input  [17:0] ibeta_i;
input  [17:0] vd_i;
input  [17:0] vq_i;
input  [17:0] valpha_i;
input  [17:0] vbeta_i;
input  [17:0] theta_i;
output clarke_done_o;
output park_done_o;
output ipark_done_o;
output iclarke_done_o;
output [17:0] ialpha_o;
output [17:0] ibeta_o;
output [17:0] id_o;
output [17:0] iq_o;
output [17:0] valpha_o;
output [17:0] vbeta_o;
output [17:0] va_o;
output [17:0] vb_o;
output [17:0] vc_o;

    wire [17:0] s_mul_a_from_clarke;
    wire [1:1] s_mul_b_from_clarke;
    wire [17:0] s_mul_a_from_cordic;
    wire [17:0] s_mul_a_from_iclarke;
    wire [2:2] s_mul_b_from_iclarke;
    wire [17:0] s_mul_a_to_mas;
    wire [9:0] s_mul_b_to_mas;
    wire [43:10] s_add_c_to_mas;
    wire [28:9] s_product_from_mas;
    wire [1:0] \MAS_SCHEDULER_INST.s_mas_sel ;
    wire MSC_net_474, MSC_net_475, MSC_net_476, MSC_net_477, 
        MSC_net_478, MSC_net_479, MSC_net_480, MSC_net_481;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
h00y3dYLgdvlAEW3JJuIaFdCexB8B2QKMyJgpzvFhwHMf6QfyKME6yY5X8wQ4qHM
mIVygQXbrEBIA8lYn5BLY3al1OOzgeiTbFKw5I6AWmOTbiKzCuRjfPcaJcE+9zpg
nIyUwwzzBVuEyIkiAa4TVMPxBLK9mtHt8LkuHyTWu8Q=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=20455)
`pragma protect data_block
[encoded data, 20096 characters]
SPz0LwmVMNjYXSCMlkjsTVB8mjJJ9Di2CeTx67V2yv8=

`pragma protect end_protected

endmodule


module 
        work_adc_interface_adc_interface_6_16_12_2_g_ADC_CONFIG_REG_WIDTHg_ADC_CONFIG_VAL_WIDTHg_ADC_RESULTS_WIDTH(
        
       apb3_en_if_1_adc_control_reg_val_o,
       adc_interface_0_result_ch0_o,
       adc_interface_0_result_ch1_o,
       adc_interface_0_result_ch2_o,
       adc_interface_0_result_ch3_o,
       apb3_en_if_1_adc_channel_ch2_o,
       apb3_en_if_1_adc_channel_ch0_o,
       apb3_en_if_1_adc_channel_ch1_o,
       apb3_en_if_1_adc_channel_ch3_o,
       MC_System_0_FIC_0_LOCK,
       MC_System_0_FIC_0_CLK,
       SEQ_CONTROLLER_1_adc_start_o,
       A0_ADC_SDI_I_c,
       A0_ADC_SDO_O_c,
       A0_ADC_CS_O_c,
       A0_ADC_SCK_O_c,
       adc_interface_0_results_rdy_o
    );
input  [5:0] apb3_en_if_1_adc_control_reg_val_o;
output [11:0] adc_interface_0_result_ch0_o;
output [11:0] adc_interface_0_result_ch1_o;
output [11:0] adc_interface_0_result_ch2_o;
output [11:0] adc_interface_0_result_ch3_o;
input  [15:0] apb3_en_if_1_adc_channel_ch2_o;
input  [15:0] apb3_en_if_1_adc_channel_ch0_o;
input  [15:0] apb3_en_if_1_adc_channel_ch1_o;
input  [15:0] apb3_en_if_1_adc_channel_ch3_o;
input  MC_System_0_FIC_0_LOCK;
input  MC_System_0_FIC_0_CLK;
input  SEQ_CONTROLLER_1_adc_start_o;
input  A0_ADC_SDI_I_c;
output A0_ADC_SDO_O_c;
output A0_ADC_CS_O_c;
output A0_ADC_SCK_O_c;
output adc_interface_0_results_rdy_o;

    wire [4:0] s_r_sck_count;
    wire [2:0] s_channel_cnt;
    wire [2:0] s_channel_cnt_5;
    wire [2:0] s_r_adc_chnls_4_samp;
    wire [2:0] s_r_sck_sel;
    wire [15:0] s_r_adc_data;
    wire [15:0] s_r_adc_data_4;
    wire [15:0] s_sdo;
    wire [15:0] s_sdo_14;
    wire [4:0] present_state;
    wire [4:4] next_state;
    wire [3:1] present_state_ns;
    wire [4:4] next_state_i_0;
    wire [3:3] s_r_sck_max_count;
    wire [7:0] s_r_clock_count;
    wire [7:0] s_r_clock_count_s;
    wire [6:0] s_r_clock_count_cry;
    wire [6:0] s_r_clock_count_cry_Y;
    wire [7:7] s_r_clock_count_s_FCO;
    wire [7:7] s_r_clock_count_s_Y;
    wire [15:0] s_sdo_14_bm;
    wire [15:0] s_sdo_14_am;
    wire [1:1] present_state_ns_a3_1;
    wire [15:1] s_sdo_14_m0;
    wire VCC, s_r_sck_count_n2_Z, s_r_sck_counte, GND, 
        s_r_sck_count_n3_Z, s_r_sck_count_n4_Z, N_1585_i_0, 
        s_r_sck_count_n1_Z, s_r_sck_count_0_sqmuxa_Z, 
        result_ch1_o_1_sqmuxa, result_ch0_o_0_sqmuxa, 
        result_ch2_o_1_sqmuxa, result_ch3_o_1_sqmuxa, 
        s_sdo_1_sqmuxa_3_i_0, s_start_sig_ext_Z, 
        un13_s_r_adc_results_ready, s_adc_sdi_Z, N_154_i_0, N_173_i_0, 
        s_r_sck_enable_Z, adc_sdo_dly_Z, s_slave_select_2, s_r_sck_Z, 
        s_r_sck_10, s_r_adc_results_ready_1_sqmuxa_1, 
        s_r_clock_count_s_130_FCO, s_r_clock_count_s_130_S, 
        s_r_clock_count_s_130_Y, s_channel_cnt_0_sqmuxa_Z, 
        un13_s_r_sck, s_r_sck_10_7_am_1_1, s_r_sck_10_7_am, 
        s_r_sck_10_7_bm_1_1, s_r_sck_10_7_bm, s_sdo_14_sm2, 
        s_sdo_0_sqmuxa_1_1_Z, un1_s_r_sck, 
        result_ch3_o_1_sqmuxa_0_a2_0_3_Z, 
        result_ch3_o_1_sqmuxa_0_a2_0_2_Z, un10_s_start_sig_ext_0_a3_1, 
        s_r_sck_count_c2_Z, N_188, un1_s_sdo_2_sqmuxa_tz_Z, 
        s_sdo_14_m0s2, s_sdo_3_sqmuxa_Z, N_1595, CO1, 
        un1_s_sdo_1_sqmuxa_1_Z, un22_s_r_sck, 
        s_r_adc_results_ready_0_sqmuxa_1, CO0, N_120, N_119, N_118, 
        N_117, N_116;
    
    SLE s_r_sck (.D(s_r_sck_10), .CLK(MC_System_0_FIC_0_CLK), .EN(VCC), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(s_r_sck_Z));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_ns[7]  (.A(
        s_sdo_14_bm[7]), .B(s_sdo_14_am[7]), .C(s_sdo_14_sm2), .Y(
        s_sdo_14[7]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_am[14]  (
        .A(apb3_en_if_1_adc_channel_ch1_o[14]), .B(
        apb3_en_if_1_adc_channel_ch3_o[14]), .C(un1_s_sdo_1_sqmuxa_1_Z)
        , .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_am[14]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_m0[14]  (.A(
        apb3_en_if_1_adc_channel_ch0_o[14]), .B(s_sdo[13]), .C(
        A0_ADC_CS_O_c), .Y(s_sdo_14_m0[14]));
    SLE s_r_sck_enable (.D(next_state_i_0[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_r_sck_enable_Z)
        );
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_ns[8]  (.A(
        s_sdo_14_bm[8]), .B(s_sdo_14_am[8]), .C(s_sdo_14_sm2), .Y(
        s_sdo_14[8]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_am[12]  (
        .A(apb3_en_if_1_adc_channel_ch1_o[12]), .B(
        apb3_en_if_1_adc_channel_ch3_o[12]), .C(un1_s_sdo_1_sqmuxa_1_Z)
        , .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_am[12]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[1]  (
        .A(A0_ADC_CS_O_c), .B(s_r_adc_data[0]), .Y(s_r_adc_data_4[1]));
    CFG4 #( .INIT(16'hB830) )  \DATA_TRANSMIT_PROC.s_sdo_14_bm[0]  (.A(
        A0_ADC_CS_O_c), .B(s_sdo_14_m0s2), .C(
        apb3_en_if_1_adc_channel_ch2_o[0]), .D(
        apb3_en_if_1_adc_channel_ch0_o[0]), .Y(s_sdo_14_bm[0]));
    SLE \s_r_adc_data[13]  (.D(s_r_adc_data_4[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[13]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_ns[15]  (.A(
        s_sdo_14_bm[15]), .B(s_sdo_14_am[15]), .C(s_sdo_14_sm2), .Y(
        s_sdo_14[15]));
    SLE \s_r_adc_data[4]  (.D(s_r_adc_data_4[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[4]));
    SLE s_slave_select (.D(s_slave_select_2), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(A0_ADC_CS_O_c));
    SLE \s_r_adc_chnls_4_samp[0]  (.D(
        apb3_en_if_1_adc_control_reg_val_o[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_r_adc_chnls_4_samp[0]));
    SLE \s_r_clock_count[4]  (.D(s_r_clock_count_s[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_r_clock_count[4]));
    CFG4 #( .INIT(16'h1444) )  \CHANNEL_CNT_PROC.s_channel_cnt_5[1]  (
        .A(present_state[4]), .B(s_channel_cnt[1]), .C(
        s_channel_cnt_0_sqmuxa_Z), .D(s_channel_cnt[0]), .Y(
        s_channel_cnt_5[1]));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_cry[1]  (.A(VCC), .B(
        s_r_clock_count[1]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_cry[0]), .S(s_r_clock_count_s[1]), .Y(
        s_r_clock_count_cry_Y[1]), .FCO(s_r_clock_count_cry[1]));
    CFG3 #( .INIT(8'hB8) )  \DATA_TRANSMIT_PROC.s_sdo_14_bm[10]  (.A(
        s_sdo_14_m0[10]), .B(s_sdo_14_m0s2), .C(
        apb3_en_if_1_adc_channel_ch2_o[10]), .Y(s_sdo_14_bm[10]));
    CFG4 #( .INIT(16'h3437) )  \SCK_GEN_PROC.s_r_sck_10_7_bm_1_1  (.A(
        s_r_clock_count[5]), .B(s_r_sck_sel[2]), .C(s_r_sck_sel[1]), 
        .D(s_r_clock_count[1]), .Y(s_r_sck_10_7_bm_1_1));
    SLE \s_sdo[2]  (.D(s_sdo_14[2]), .CLK(MC_System_0_FIC_0_CLK), .EN(
        s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), 
        .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[2]));
    CFG2 #( .INIT(4'hE) )  s_sdo_1_sqmuxa_3_i (.A(un1_s_r_sck), .B(
        A0_ADC_CS_O_c), .Y(s_sdo_1_sqmuxa_3_i_0));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_cry[4]  (.A(VCC), .B(
        s_r_clock_count[4]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_cry[3]), .S(s_r_clock_count_s[4]), .Y(
        s_r_clock_count_cry_Y[4]), .FCO(s_r_clock_count_cry[4]));
    SLE \result_ch0_o[4]  (.D(s_r_adc_data[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[4]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[12]  
        (.A(A0_ADC_CS_O_c), .B(s_r_adc_data[11]), .Y(
        s_r_adc_data_4[12]));
    ARI1 #( .INIT(20'h4AA00) )  s_r_clock_count_s_130 (.A(VCC), .B(
        s_r_sck_enable_Z), .C(GND), .D(GND), .FCI(VCC), .S(
        s_r_clock_count_s_130_S), .Y(s_r_clock_count_s_130_Y), .FCO(
        s_r_clock_count_s_130_FCO));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_cry[0]  (.A(VCC), .B(
        s_r_clock_count[0]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_s_130_FCO), .S(s_r_clock_count_s[0]), .Y(
        s_r_clock_count_cry_Y[0]), .FCO(s_r_clock_count_cry[0]));
    SLE \result_ch1_o[8]  (.D(s_r_adc_data[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[8]));
    CFG3 #( .INIT(8'hB8) )  \DATA_TRANSMIT_PROC.s_sdo_14_bm[9]  (.A(
        s_sdo_14_m0[9]), .B(s_sdo_14_m0s2), .C(
        apb3_en_if_1_adc_channel_ch2_o[9]), .Y(s_sdo_14_bm[9]));
    CFG4 #( .INIT(16'h5755) )  \SS_GEN_PROC.s_slave_select_2  (.A(
        s_start_sig_ext_Z), .B(s_r_sck_count[3]), .C(s_r_sck_count[1]), 
        .D(un10_s_start_sig_ext_0_a3_1), .Y(s_slave_select_2));
    SLE \s_sdo[5]  (.D(s_sdo_14[5]), .CLK(MC_System_0_FIC_0_CLK), .EN(
        s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), 
        .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[5]));
    CFG3 #( .INIT(8'hB8) )  \DATA_TRANSMIT_PROC.s_sdo_14_bm[5]  (.A(
        s_sdo_14_m0[5]), .B(s_sdo_14_m0s2), .C(
        apb3_en_if_1_adc_channel_ch2_o[5]), .Y(s_sdo_14_bm[5]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_am[7]  (.A(
        apb3_en_if_1_adc_channel_ch1_o[7]), .B(
        apb3_en_if_1_adc_channel_ch3_o[7]), .C(un1_s_sdo_1_sqmuxa_1_Z), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_am[7]));
    SLE \result_ch3_o[0]  (.D(s_r_adc_data[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch3_o[0]));
    SLE \s_r_sck_count[0]  (.D(N_1585_i_0), .CLK(MC_System_0_FIC_0_CLK)
        , .EN(s_r_sck_counte), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), 
        .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_r_sck_count[0]));
    SLE \s_sdo[0]  (.D(s_sdo_14[0]), .CLK(MC_System_0_FIC_0_CLK), .EN(
        s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), 
        .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[0]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_m0[5]  (.A(
        apb3_en_if_1_adc_channel_ch0_o[5]), .B(s_sdo[4]), .C(
        A0_ADC_CS_O_c), .Y(s_sdo_14_m0[5]));
    SLE s_start_sig_ext (.D(SEQ_CONTROLLER_1_adc_start_o), .CLK(
        MC_System_0_FIC_0_CLK), .EN(un13_s_r_adc_results_ready), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_start_sig_ext_Z));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_m0[15]  (.A(
        apb3_en_if_1_adc_channel_ch0_o[15]), .B(s_sdo[14]), .C(
        A0_ADC_CS_O_c), .Y(s_sdo_14_m0[15]));
    CFG4 #( .INIT(16'h6A00) )  s_r_sck_count_n2 (.A(s_r_sck_count[2]), 
        .B(s_r_sck_count[1]), .C(s_r_sck_count[0]), .D(
        present_state[1]), .Y(s_r_sck_count_n2_Z));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[3]  (
        .A(A0_ADC_CS_O_c), .B(s_r_adc_data[2]), .Y(s_r_adc_data_4[3]));
    SLE \result_ch2_o[3]  (.D(s_r_adc_data[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[3]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_ns[2]  (.A(
        s_sdo_14_bm[2]), .B(s_sdo_14_am[2]), .C(s_sdo_14_sm2), .Y(
        s_sdo_14[2]));
    SLE \s_r_adc_data[6]  (.D(s_r_adc_data_4[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[6]));
    SLE \result_ch1_o[6]  (.D(s_r_adc_data[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[6]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_ns[6]  (.A(
        s_sdo_14_bm[6]), .B(s_sdo_14_am[6]), .C(s_sdo_14_sm2), .Y(
        s_sdo_14[6]));
    SLE s_adc_sdi (.D(A0_ADC_SDI_I_c), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(N_154_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(
        VCC), .SD(GND), .LAT(GND), .Q(s_adc_sdi_Z));
    SLE \result_ch1_o[4]  (.D(s_r_adc_data[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[4]));
    CFG2 #( .INIT(4'hE) )  
        \START_SIG_PROC.un13_s_r_adc_results_ready_0  (.A(
        s_r_adc_results_ready_1_sqmuxa_1), .B(
        SEQ_CONTROLLER_1_adc_start_o), .Y(un13_s_r_adc_results_ready));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_ns[9]  (.A(
        s_sdo_14_bm[9]), .B(s_sdo_14_am[9]), .C(s_sdo_14_sm2), .Y(
        s_sdo_14[9]));
    CFG3 #( .INIT(8'h80) )  s_r_adc_results_ready_0_sqmuxa_1_0_a3 (.A(
        un22_s_r_sck), .B(present_state[0]), .C(un1_s_r_sck), .Y(
        s_r_adc_results_ready_0_sqmuxa_1));
    CFG2 #( .INIT(4'h8) )  s_adc_sdi_RNO (.A(un1_s_r_sck), .B(
        present_state[1]), .Y(N_154_i_0));
    SLE \s_sdo[1]  (.D(s_sdo_14[1]), .CLK(MC_System_0_FIC_0_CLK), .EN(
        s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), 
        .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[1]));
    SLE \present_state[2]  (.D(present_state_ns[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(present_state[2])
        );
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_am[4]  (.A(
        apb3_en_if_1_adc_channel_ch1_o[4]), .B(
        apb3_en_if_1_adc_channel_ch3_o[4]), .C(un1_s_sdo_1_sqmuxa_1_Z), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_am[4]));
    SLE \s_r_clock_count[5]  (.D(s_r_clock_count_s[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_r_clock_count[5]));
    SLE \result_ch3_o[3]  (.D(s_r_adc_data[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch3_o[3]));
    SLE \s_r_clock_count[2]  (.D(s_r_clock_count_s[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_r_clock_count[2]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_m0[6]  (.A(
        apb3_en_if_1_adc_channel_ch0_o[6]), .B(s_sdo[5]), .C(
        A0_ADC_CS_O_c), .Y(s_sdo_14_m0[6]));
    CFG4 #( .INIT(16'h28A0) )  s_r_sck_count_n4 (.A(present_state[1]), 
        .B(s_r_sck_count_c2_Z), .C(s_r_sck_count[4]), .D(
        s_r_sck_count[3]), .Y(s_r_sck_count_n4_Z));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_am[15]  (
        .A(apb3_en_if_1_adc_channel_ch1_o[15]), .B(
        apb3_en_if_1_adc_channel_ch3_o[15]), .C(un1_s_sdo_1_sqmuxa_1_Z)
        , .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_am[15]));
    SLE \s_sdo[15]  (.D(s_sdo_14[15]), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[15]));
    SLE \s_sdo[12]  (.D(s_sdo_14[12]), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[12]));
    SLE \s_r_clock_count[3]  (.D(s_r_clock_count_s[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_r_clock_count[3]));
    SLE \s_r_adc_data[14]  (.D(s_r_adc_data_4[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[14]));
    SLE results_rdy_o (.D(s_r_adc_results_ready_1_sqmuxa_1), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        adc_interface_0_results_rdy_o));
    SLE \result_ch2_o[2]  (.D(s_r_adc_data[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[2]));
    SLE \s_r_sck_count[4]  (.D(s_r_sck_count_n4_Z), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_sck_count[4]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_ns[12]  (.A(
        s_sdo_14_bm[12]), .B(s_sdo_14_am[12]), .C(s_sdo_14_sm2), .Y(
        s_sdo_14[12]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_m0[10]  (.A(
        apb3_en_if_1_adc_channel_ch0_o[10]), .B(s_sdo[9]), .C(
        A0_ADC_CS_O_c), .Y(s_sdo_14_m0[10]));
    SLE \result_ch1_o[10]  (.D(s_r_adc_data[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[10]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_m0[13]  (.A(
        apb3_en_if_1_adc_channel_ch0_o[13]), .B(s_sdo[12]), .C(
        A0_ADC_CS_O_c), .Y(s_sdo_14_m0[13]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_am[8]  (.A(
        apb3_en_if_1_adc_channel_ch1_o[8]), .B(
        apb3_en_if_1_adc_channel_ch3_o[8]), .C(un1_s_sdo_1_sqmuxa_1_Z), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_am[8]));
    SLE \s_r_adc_data[7]  (.D(s_r_adc_data_4[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[7]));
    SLE \result_ch0_o[2]  (.D(s_r_adc_data[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[2]));
    SLE \s_channel_cnt[0]  (.D(s_channel_cnt_5[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_channel_cnt[0])
        );
    CFG3 #( .INIT(8'h20) )  result_ch2_o_1_sqmuxa_0_a2 (.A(
        s_r_adc_data[13]), .B(s_r_adc_data[12]), .C(N_1595), .Y(
        result_ch2_o_1_sqmuxa));
    SLE \result_ch1_o[5]  (.D(s_r_adc_data[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[5]));
    SLE \s_sdo[11]  (.D(s_sdo_14[11]), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[11]));
    SLE \s_r_sck_sel[0]  (.D(apb3_en_if_1_adc_control_reg_val_o[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_sck_sel[0]));
    CFG4 #( .INIT(16'h555D) )  \DATA_TRANSMIT_PROC.s_sdo_14_m0s2  (.A(
        A0_ADC_CS_O_c), .B(s_sdo_0_sqmuxa_1_1_Z), .C(
        s_r_adc_chnls_4_samp[2]), .D(s_channel_cnt[0]), .Y(
        s_sdo_14_m0s2));
    CFG3 #( .INIT(8'hB8) )  \DATA_TRANSMIT_PROC.s_sdo_14_bm[12]  (.A(
        s_sdo_14_m0[12]), .B(s_sdo_14_m0s2), .C(
        apb3_en_if_1_adc_channel_ch2_o[12]), .Y(s_sdo_14_bm[12]));
    SLE \s_r_adc_data[15]  (.D(s_r_adc_data_4[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[15]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_am[13]  (
        .A(apb3_en_if_1_adc_channel_ch1_o[13]), .B(
        apb3_en_if_1_adc_channel_ch3_o[13]), .C(un1_s_sdo_1_sqmuxa_1_Z)
        , .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_am[13]));
    CFG3 #( .INIT(8'hA4) )  \present_state_ns_i_m4[2]  (.A(
        present_state[3]), .B(present_state[2]), .C(un1_s_r_sck), .Y(
        present_state_ns[2]));
    CFG3 #( .INIT(8'hB8) )  \DATA_TRANSMIT_PROC.s_sdo_14_bm[7]  (.A(
        s_sdo_14_m0[7]), .B(s_sdo_14_m0s2), .C(
        apb3_en_if_1_adc_channel_ch2_o[7]), .Y(s_sdo_14_bm[7]));
    CFG3 #( .INIT(8'hDC) )  \next_state_0[4]  (.A(
        SEQ_CONTROLLER_1_adc_start_o), .B(
        s_r_adc_results_ready_1_sqmuxa_1), .C(present_state[4]), .Y(
        next_state[4]));
    SLE \s_r_adc_data[5]  (.D(s_r_adc_data_4[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[5]));
    SLE \s_r_adc_data[11]  (.D(s_r_adc_data_4[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[11]));
    SLE \s_r_adc_chnls_4_samp[1]  (.D(
        apb3_en_if_1_adc_control_reg_val_o[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_r_adc_chnls_4_samp[1]));
    SLE \s_sdo[9]  (.D(s_sdo_14[9]), .CLK(MC_System_0_FIC_0_CLK), .EN(
        s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), 
        .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[9]));
    SLE \result_ch0_o[1]  (.D(s_r_adc_data[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[1]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_m0[11]  (.A(
        apb3_en_if_1_adc_channel_ch0_o[11]), .B(s_sdo[10]), .C(
        A0_ADC_CS_O_c), .Y(s_sdo_14_m0[11]));
    CFG2 #( .INIT(4'h2) )  \s_r_sck_count_RNO[0]  (.A(present_state[1])
        , .B(s_r_sck_count[0]), .Y(N_1585_i_0));
    SLE \s_r_sck_max_count[3]  (.D(VCC), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), 
        .SD(GND), .LAT(GND), .Q(s_r_sck_max_count[3]));
    GND GND_Z (.Y(GND));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[4]  (
        .A(A0_ADC_CS_O_c), .B(s_r_adc_data[3]), .Y(s_r_adc_data_4[4]));
    SLE \s_sdo[4]  (.D(s_sdo_14[4]), .CLK(MC_System_0_FIC_0_CLK), .EN(
        s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), 
        .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[4]));
    CFG4 #( .INIT(16'h006A) )  \CHANNEL_CNT_PROC.s_channel_cnt_5[2]  (
        .A(s_channel_cnt[2]), .B(s_channel_cnt[1]), .C(CO0), .D(
        present_state[4]), .Y(s_channel_cnt_5[2]));
    CFG4 #( .INIT(16'h0401) )  result_ch3_o_1_sqmuxa_0_a2_0_2 (.A(
        s_r_adc_data[15]), .B(s_r_sck_max_count[3]), .C(
        s_r_adc_data[14]), .D(s_r_sck_count[4]), .Y(
        result_ch3_o_1_sqmuxa_0_a2_0_2_Z));
    VCC VCC_Z (.Y(VCC));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_am[2]  (.A(
        apb3_en_if_1_adc_channel_ch1_o[2]), .B(
        apb3_en_if_1_adc_channel_ch3_o[2]), .C(un1_s_sdo_1_sqmuxa_1_Z), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_am[2]));
    CFG4 #( .INIT(16'h0800) )  s_channel_cnt_0_sqmuxa (.A(
        present_state[0]), .B(s_r_sck_Z), .C(A0_ADC_SCK_O_c), .D(
        un22_s_r_sck), .Y(s_channel_cnt_0_sqmuxa_Z));
    SLE \s_r_sck_sel[2]  (.D(apb3_en_if_1_adc_control_reg_val_o[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_sck_sel[2]));
    SLE \s_r_adc_data[10]  (.D(s_r_adc_data_4[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[10]));
    SLE \result_ch0_o[8]  (.D(s_r_adc_data[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[8]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[15]  
        (.A(A0_ADC_CS_O_c), .B(s_r_adc_data[14]), .Y(
        s_r_adc_data_4[15]));
    SLE \result_ch2_o[5]  (.D(s_r_adc_data[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[5]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_ns[5]  (.A(
        s_sdo_14_bm[5]), .B(s_sdo_14_am[5]), .C(s_sdo_14_sm2), .Y(
        s_sdo_14[5]));
    SLE \result_ch2_o[10]  (.D(s_r_adc_data[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[10]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[10]  
        (.A(A0_ADC_CS_O_c), .B(s_r_adc_data[9]), .Y(s_r_adc_data_4[10])
        );
    SLE \result_ch3_o[4]  (.D(s_r_adc_data[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch3_o[4]));
    CFG3 #( .INIT(8'h40) )  result_ch1_o_1_sqmuxa_0_a2 (.A(
        s_r_adc_data[13]), .B(s_r_adc_data[12]), .C(N_1595), .Y(
        result_ch1_o_1_sqmuxa));
    SLE \result_ch0_o[9]  (.D(s_r_adc_data[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[9]));
    SLE \result_ch3_o[6]  (.D(s_r_adc_data[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch3_o[6]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_am[6]  (.A(
        apb3_en_if_1_adc_channel_ch1_o[6]), .B(
        apb3_en_if_1_adc_channel_ch3_o[6]), .C(un1_s_sdo_1_sqmuxa_1_Z), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_am[6]));
    SLE sdo_o (.D(adc_sdo_dly_Z), .CLK(MC_System_0_FIC_0_CLK), .EN(VCC)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(A0_ADC_SDO_O_c));
    CFG3 #( .INIT(8'hB8) )  \DATA_TRANSMIT_PROC.s_sdo_14_bm[4]  (.A(
        s_sdo_14_m0[4]), .B(s_sdo_14_m0s2), .C(
        apb3_en_if_1_adc_channel_ch2_o[4]), .Y(s_sdo_14_bm[4]));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_s[7]  (.A(VCC), .B(
        s_r_clock_count[7]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_cry[6]), .S(s_r_clock_count_s[7]), .Y(
        s_r_clock_count_s_Y[7]), .FCO(s_r_clock_count_s_FCO[7]));
    SLE \result_ch1_o[11]  (.D(s_r_adc_data[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[11]));
    SLE \result_ch0_o[5]  (.D(s_r_adc_data[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[5]));
    SLE \result_ch0_o[0]  (.D(s_r_adc_data[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[0]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_am[11]  (
        .A(apb3_en_if_1_adc_channel_ch1_o[11]), .B(
        apb3_en_if_1_adc_channel_ch3_o[11]), .C(un1_s_sdo_1_sqmuxa_1_Z)
        , .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_am[11]));
    CFG4 #( .INIT(16'hEACC) )  \present_state_ns[3]  (.A(
        present_state[2]), .B(present_state[1]), .C(un13_s_r_sck), .D(
        un1_s_r_sck), .Y(present_state_ns[3]));
    CFG3 #( .INIT(8'hB8) )  \DATA_TRANSMIT_PROC.s_sdo_14_bm[13]  (.A(
        s_sdo_14_m0[13]), .B(s_sdo_14_m0s2), .C(
        apb3_en_if_1_adc_channel_ch2_o[13]), .Y(s_sdo_14_bm[13]));
    SLE \s_r_adc_data[8]  (.D(s_r_adc_data_4[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[8]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[0]  (
        .A(A0_ADC_CS_O_c), .B(s_adc_sdi_Z), .Y(s_r_adc_data_4[0]));
    SLE \s_r_clock_count[6]  (.D(s_r_clock_count_s[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_r_clock_count[6]));
    CFG3 #( .INIT(8'h80) )  result_ch3_o_1_sqmuxa_0_a2 (.A(
        s_r_adc_data[13]), .B(s_r_adc_data[12]), .C(N_1595), .Y(
        result_ch3_o_1_sqmuxa));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[2]  (
        .A(A0_ADC_CS_O_c), .B(s_r_adc_data[1]), .Y(s_r_adc_data_4[2]));
    SLE \present_state[0]  (.D(N_173_i_0), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), 
        .SD(GND), .LAT(GND), .Q(present_state[0]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_m0[7]  (.A(
        apb3_en_if_1_adc_channel_ch0_o[7]), .B(s_sdo[6]), .C(
        A0_ADC_CS_O_c), .Y(s_sdo_14_m0[7]));
    SLE \result_ch3_o[1]  (.D(s_r_adc_data[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch3_o[1]));
    SLE \result_ch2_o[6]  (.D(s_r_adc_data[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[6]));
    SLE \s_r_sck_count[3]  (.D(s_r_sck_count_n3_Z), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_sck_count[3]));
    SLE \s_r_sck_count[1]  (.D(s_r_sck_count_n1_Z), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_sck_count[1]));
    SLE \present_state[3]  (.D(present_state_ns[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(present_state[3])
        );
    CFG3 #( .INIT(8'hB8) )  \DATA_TRANSMIT_PROC.s_sdo_14_bm[14]  (.A(
        s_sdo_14_m0[14]), .B(s_sdo_14_m0s2), .C(
        apb3_en_if_1_adc_channel_ch2_o[14]), .Y(s_sdo_14_bm[14]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[7]  (
        .A(A0_ADC_CS_O_c), .B(s_r_adc_data[6]), .Y(s_r_adc_data_4[7]));
    CFG3 #( .INIT(8'hB8) )  \DATA_TRANSMIT_PROC.s_sdo_14_bm[8]  (.A(
        s_sdo_14_m0[8]), .B(s_sdo_14_m0s2), .C(
        apb3_en_if_1_adc_channel_ch2_o[8]), .Y(s_sdo_14_bm[8]));
    CFG4 #( .INIT(16'h1075) )  \ADC_FSM_NS_PROC.un22_s_r_sck_1.CO1  (
        .A(s_r_adc_chnls_4_samp[1]), .B(s_channel_cnt[0]), .C(
        s_r_adc_chnls_4_samp[0]), .D(s_channel_cnt[1]), .Y(CO1));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_cry[6]  (.A(VCC), .B(
        s_r_clock_count[6]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_cry[5]), .S(s_r_clock_count_s[6]), .Y(
        s_r_clock_count_cry_Y[6]), .FCO(s_r_clock_count_cry[6]));
    SLE \s_channel_cnt[2]  (.D(s_channel_cnt_5[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_channel_cnt[2])
        );
    SLE \s_sdo[6]  (.D(s_sdo_14[6]), .CLK(MC_System_0_FIC_0_CLK), .EN(
        s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), 
        .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[6]));
    SLE \result_ch0_o[3]  (.D(s_r_adc_data[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[3]));
    CFG2 #( .INIT(4'h1) )  s_sdo_0_sqmuxa_1_1 (.A(s_channel_cnt[2]), 
        .B(s_channel_cnt[1]), .Y(s_sdo_0_sqmuxa_1_1_Z));
    CFG3 #( .INIT(8'hB8) )  \DATA_TRANSMIT_PROC.s_sdo_14_bm[11]  (.A(
        s_sdo_14_m0[11]), .B(s_sdo_14_m0s2), .C(
        apb3_en_if_1_adc_channel_ch2_o[11]), .Y(s_sdo_14_bm[11]));
    SLE \result_ch0_o[7]  (.D(s_r_adc_data[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[7]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_ns[1]  (.A(
        s_sdo_14_bm[1]), .B(s_sdo_14_am[1]), .C(s_sdo_14_sm2), .Y(
        s_sdo_14[1]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_am[1]  (.A(
        apb3_en_if_1_adc_channel_ch1_o[1]), .B(
        apb3_en_if_1_adc_channel_ch3_o[1]), .C(un1_s_sdo_1_sqmuxa_1_Z), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_am[1]));
    SLE \result_ch0_o[6]  (.D(s_r_adc_data[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[6]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_am[3]  (.A(
        apb3_en_if_1_adc_channel_ch1_o[3]), .B(
        apb3_en_if_1_adc_channel_ch3_o[3]), .C(un1_s_sdo_1_sqmuxa_1_Z), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_am[3]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[9]  (
        .A(A0_ADC_CS_O_c), .B(s_r_adc_data[8]), .Y(s_r_adc_data_4[9]));
    SLE \result_ch3_o[10]  (.D(s_r_adc_data[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch3_o[10]));
    SLE \present_state[1]  (.D(present_state_ns[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(present_state[1])
        );
    CFG3 #( .INIT(8'h40) )  \next_state_0_a3_0[4]  (.A(un22_s_r_sck), 
        .B(present_state[0]), .C(un1_s_r_sck), .Y(
        s_r_adc_results_ready_1_sqmuxa_1));
    SLE \result_ch3_o[5]  (.D(s_r_adc_data[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch3_o[5]));
    CFG4 #( .INIT(16'h7555) )  \present_state_ns_o4_RNINP6U[3]  (.A(
        present_state[1]), .B(s_r_sck_Z), .C(un13_s_r_sck), .D(
        A0_ADC_SCK_O_c), .Y(s_r_sck_counte));
    CFG4 #( .INIT(16'hFFF4) )  \present_state_ns[1]  (.A(un1_s_r_sck), 
        .B(present_state[3]), .C(s_r_adc_results_ready_0_sqmuxa_1), .D(
        N_188), .Y(present_state_ns[1]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_m0[2]  (.A(
        apb3_en_if_1_adc_channel_ch0_o[2]), .B(s_sdo[1]), .C(
        A0_ADC_CS_O_c), .Y(s_sdo_14_m0[2]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_ns[0]  (.A(
        s_sdo_14_bm[0]), .B(s_sdo_14_am[0]), .C(s_sdo_14_sm2), .Y(
        s_sdo_14[0]));
    CFG4 #( .INIT(16'h0400) )  s_sdo_3_sqmuxa (.A(
        s_r_adc_chnls_4_samp[2]), .B(s_r_adc_chnls_4_samp[0]), .C(
        s_channel_cnt[2]), .D(s_r_adc_chnls_4_samp[1]), .Y(
        s_sdo_3_sqmuxa_Z));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_ns[10]  (.A(
        s_sdo_14_bm[10]), .B(s_sdo_14_am[10]), .C(s_sdo_14_sm2), .Y(
        s_sdo_14[10]));
    SLE \result_ch2_o[4]  (.D(s_r_adc_data[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[4]));
    CFG3 #( .INIT(8'hE2) )  \SCK_GEN_PROC.s_r_sck_10_7_ns  (.A(
        s_r_sck_10_7_am), .B(s_r_sck_sel[0]), .C(s_r_sck_10_7_bm), .Y(
        s_r_sck_10));
    SLE \result_ch2_o[11]  (.D(s_r_adc_data[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[11]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_m0[4]  (.A(
        apb3_en_if_1_adc_channel_ch0_o[4]), .B(s_sdo[3]), .C(
        A0_ADC_CS_O_c), .Y(s_sdo_14_m0[4]));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_cry[5]  (.A(VCC), .B(
        s_r_clock_count[5]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_cry[4]), .S(s_r_clock_count_s[5]), .Y(
        s_r_clock_count_cry_Y[5]), .FCO(s_r_clock_count_cry[5]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_m0[12]  (.A(
        apb3_en_if_1_adc_channel_ch0_o[12]), .B(s_sdo[11]), .C(
        A0_ADC_CS_O_c), .Y(s_sdo_14_m0[12]));
    SLE \s_sdo[13]  (.D(s_sdo_14[13]), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[13]));
    CFG3 #( .INIT(8'h80) )  s_r_sck_count_c2 (.A(s_r_sck_count[2]), .B(
        s_r_sck_count[1]), .C(s_r_sck_count[0]), .Y(s_r_sck_count_c2_Z)
        );
    CFG3 #( .INIT(8'hB8) )  \DATA_TRANSMIT_PROC.s_sdo_14_bm[2]  (.A(
        s_sdo_14_m0[2]), .B(s_sdo_14_m0s2), .C(
        apb3_en_if_1_adc_channel_ch2_o[2]), .Y(s_sdo_14_bm[2]));
    SLE \result_ch2_o[0]  (.D(s_r_adc_data[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[0]));
    CFG4 #( .INIT(16'h0004) )  \present_state_ns_a3[1]  (.A(
        present_state[1]), .B(present_state_ns_a3_1[1]), .C(
        present_state[3]), .D(present_state[2]), .Y(N_188));
    SLE \s_sdo[7]  (.D(s_sdo_14[7]), .CLK(MC_System_0_FIC_0_CLK), .EN(
        s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), 
        .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[7]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_ns[14]  (.A(
        s_sdo_14_bm[14]), .B(s_sdo_14_am[14]), .C(s_sdo_14_sm2), .Y(
        s_sdo_14[14]));
    CFG3 #( .INIT(8'h28) )  s_r_sck_count_n3 (.A(present_state[1]), .B(
        s_r_sck_count_c2_Z), .C(s_r_sck_count[3]), .Y(
        s_r_sck_count_n3_Z));
    SLE \result_ch3_o[2]  (.D(s_r_adc_data[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch3_o[2]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[11]  
        (.A(A0_ADC_CS_O_c), .B(s_r_adc_data[10]), .Y(
        s_r_adc_data_4[11]));
    CFG3 #( .INIT(8'h18) )  result_ch3_o_1_sqmuxa_0_a2_0_3 (.A(
        s_r_sck_max_count[3]), .B(s_r_sck_count[1]), .C(
        s_r_sck_count[0]), .Y(result_ch3_o_1_sqmuxa_0_a2_0_3_Z));
    SLE \result_ch3_o[7]  (.D(s_r_adc_data[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch3_o[7]));
    SLE \result_ch1_o[1]  (.D(s_r_adc_data[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[1]));
    CFG2 #( .INIT(4'h2) )  \present_state_ns_a3_1[1]  (.A(
        SEQ_CONTROLLER_1_adc_start_o), .B(present_state[0]), .Y(
        present_state_ns_a3_1[1]));
    CFG4 #( .INIT(16'h3437) )  \SCK_GEN_PROC.s_r_sck_10_7_am_1_1  (.A(
        s_r_clock_count[4]), .B(s_r_sck_sel[2]), .C(s_r_sck_sel[1]), 
        .D(s_r_clock_count[0]), .Y(s_r_sck_10_7_am_1_1));
    SLE \result_ch1_o[9]  (.D(s_r_adc_data[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[9]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[14]  
        (.A(A0_ADC_CS_O_c), .B(s_r_adc_data[13]), .Y(
        s_r_adc_data_4[14]));
    CFG3 #( .INIT(8'h01) )  \SS_GEN_PROC.un10_s_start_sig_ext_0_a3_1  
        (.A(s_r_sck_count[4]), .B(s_r_sck_count[2]), .C(
        s_r_sck_count[0]), .Y(un10_s_start_sig_ext_0_a3_1));
    CFG4 #( .INIT(16'h04AC) )  \present_state_RNO[0]  (.A(
        present_state[1]), .B(present_state[0]), .C(un1_s_r_sck), .D(
        un13_s_r_sck), .Y(N_173_i_0));
    SLE \result_ch3_o[9]  (.D(s_r_adc_data[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch3_o[9]));
    CFG3 #( .INIT(8'hB8) )  \DATA_TRANSMIT_PROC.s_sdo_14_bm[6]  (.A(
        s_sdo_14_m0[6]), .B(s_sdo_14_m0s2), .C(
        apb3_en_if_1_adc_channel_ch2_o[6]), .Y(s_sdo_14_bm[6]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_am[0]  (.A(
        apb3_en_if_1_adc_channel_ch1_o[0]), .B(
        apb3_en_if_1_adc_channel_ch3_o[0]), .C(un1_s_sdo_1_sqmuxa_1_Z), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_am[0]));
    SLE \present_state[4]  (.D(next_state[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(GND), .SLn(VCC), .SD(GND), .LAT(GND), .Q(present_state[4])
        );
    SLE \result_ch0_o[10]  (.D(s_r_adc_data[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[10]));
    CFG3 #( .INIT(8'h60) )  s_r_sck_count_n1 (.A(s_r_sck_count[1]), .B(
        s_r_sck_count[0]), .C(present_state[1]), .Y(s_r_sck_count_n1_Z)
        );
    SLE \s_r_adc_data[2]  (.D(s_r_adc_data_4[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[2]));
    CFG2 #( .INIT(4'h2) )  un1_s_sdo_2_sqmuxa_tz (.A(
        s_r_adc_chnls_4_samp[1]), .B(s_r_adc_chnls_4_samp[2]), .Y(
        un1_s_sdo_2_sqmuxa_tz_Z));
    CFG4 #( .INIT(16'h6F06) )  \ADC_FSM_NS_PROC.un22_s_r_sck_1.CO2  (
        .A(s_r_adc_chnls_4_samp[2]), .B(s_r_adc_chnls_4_samp[1]), .C(
        s_channel_cnt[2]), .D(CO1), .Y(un22_s_r_sck));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_cry[2]  (.A(VCC), .B(
        s_r_clock_count[2]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_cry[1]), .S(s_r_clock_count_s[2]), .Y(
        s_r_clock_count_cry_Y[2]), .FCO(s_r_clock_count_cry[2]));
    SLE \s_r_adc_data[12]  (.D(s_r_adc_data_4[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[12]));
    SLE \s_r_adc_data[1]  (.D(s_r_adc_data_4[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[1]));
    CFG4 #( .INIT(16'hB931) )  \SCK_GEN_PROC.s_r_sck_10_7_am  (.A(
        s_r_sck_sel[1]), .B(s_r_sck_10_7_am_1_1), .C(
        s_r_clock_count[6]), .D(s_r_clock_count[2]), .Y(
        s_r_sck_10_7_am));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_m0[9]  (.A(
        apb3_en_if_1_adc_channel_ch0_o[9]), .B(s_sdo[8]), .C(
        A0_ADC_CS_O_c), .Y(s_sdo_14_m0[9]));
    SLE \s_sdo[10]  (.D(s_sdo_14[10]), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[10]));
    CFG3 #( .INIT(8'h10) )  result_ch0_o_0_sqmuxa_0_a2 (.A(
        s_r_adc_data[13]), .B(s_r_adc_data[12]), .C(N_1595), .Y(
        result_ch0_o_0_sqmuxa));
    CFG4 #( .INIT(16'h3200) )  un1_s_sdo_1_sqmuxa_1 (.A(
        s_r_adc_chnls_4_samp[0]), .B(s_r_adc_chnls_4_samp[2]), .C(
        s_r_adc_chnls_4_samp[1]), .D(s_sdo_0_sqmuxa_1_1_Z), .Y(
        un1_s_sdo_1_sqmuxa_1_Z));
    SLE \result_ch2_o[8]  (.D(s_r_adc_data[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[8]));
    CFG2 #( .INIT(4'h2) )  \ADC_FSM_NS_PROC.un1_s_r_sck  (.A(
        A0_ADC_SCK_O_c), .B(s_r_sck_Z), .Y(un1_s_r_sck));
    ARI1 #( .INIT(20'h48800) )  \s_r_clock_count_cry[3]  (.A(VCC), .B(
        s_r_clock_count[3]), .C(s_r_sck_enable_Z), .D(GND), .FCI(
        s_r_clock_count_cry[2]), .S(s_r_clock_count_s[3]), .Y(
        s_r_clock_count_cry_Y[3]), .FCO(s_r_clock_count_cry[3]));
    SLE \result_ch3_o[11]  (.D(s_r_adc_data[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch3_o[11]));
    CFG4 #( .INIT(16'hF1F0) )  \DATA_TRANSMIT_PROC.s_sdo_14s2  (.A(
        s_channel_cnt[0]), .B(s_channel_cnt[2]), .C(s_sdo_14_m0s2), .D(
        un1_s_sdo_2_sqmuxa_tz_Z), .Y(s_sdo_14_sm2));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_m0[3]  (.A(
        apb3_en_if_1_adc_channel_ch0_o[3]), .B(s_sdo[2]), .C(
        A0_ADC_CS_O_c), .Y(s_sdo_14_m0[3]));
    SLE \s_r_adc_chnls_4_samp[2]  (.D(
        apb3_en_if_1_adc_control_reg_val_o[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_r_adc_chnls_4_samp[2]));
    SLE \s_sdo[8]  (.D(s_sdo_14[8]), .CLK(MC_System_0_FIC_0_CLK), .EN(
        s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), 
        .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[8]));
    SLE \result_ch1_o[3]  (.D(s_r_adc_data[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[3]));
    CFG3 #( .INIT(8'h23) )  \next_state_0_i[4]  (.A(
        SEQ_CONTROLLER_1_adc_start_o), .B(
        s_r_adc_results_ready_1_sqmuxa_1), .C(present_state[4]), .Y(
        next_state_i_0[4]));
    CFG3 #( .INIT(8'h14) )  \CHANNEL_CNT_PROC.s_channel_cnt_5[0]  (.A(
        present_state[4]), .B(s_channel_cnt[0]), .C(
        s_channel_cnt_0_sqmuxa_Z), .Y(s_channel_cnt_5[0]));
    SLE \result_ch2_o[9]  (.D(s_r_adc_data[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[9]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_m0[1]  (.A(
        apb3_en_if_1_adc_channel_ch0_o[1]), .B(s_sdo[0]), .C(
        A0_ADC_CS_O_c), .Y(s_sdo_14_m0[1]));
    SLE \result_ch1_o[7]  (.D(s_r_adc_data[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[7]));
    CFG4 #( .INIT(16'h5557) )  \present_state_ns_o4[3]  (.A(
        s_r_sck_count[4]), .B(s_r_sck_count[3]), .C(s_r_sck_count[2]), 
        .D(s_r_sck_count[1]), .Y(un13_s_r_sck));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_am[9]  (.A(
        apb3_en_if_1_adc_channel_ch1_o[9]), .B(
        apb3_en_if_1_adc_channel_ch3_o[9]), .C(un1_s_sdo_1_sqmuxa_1_Z), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_am[9]));
    CFG4 #( .INIT(16'h1000) )  result_ch3_o_1_sqmuxa_0_a2_0 (.A(
        s_r_sck_count[3]), .B(s_r_sck_count[2]), .C(
        result_ch3_o_1_sqmuxa_0_a2_0_3_Z), .D(
        result_ch3_o_1_sqmuxa_0_a2_0_2_Z), .Y(N_1595));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[13]  
        (.A(A0_ADC_CS_O_c), .B(s_r_adc_data[12]), .Y(
        s_r_adc_data_4[13]));
    CFG3 #( .INIT(8'hB8) )  \DATA_TRANSMIT_PROC.s_sdo_14_bm[1]  (.A(
        s_sdo_14_m0[1]), .B(s_sdo_14_m0s2), .C(
        apb3_en_if_1_adc_channel_ch2_o[1]), .Y(s_sdo_14_bm[1]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_am[5]  (.A(
        apb3_en_if_1_adc_channel_ch1_o[5]), .B(
        apb3_en_if_1_adc_channel_ch3_o[5]), .C(un1_s_sdo_1_sqmuxa_1_Z), 
        .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_am[5]));
    SLE \s_r_adc_data[3]  (.D(s_r_adc_data_4[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[3]));
    CFG3 #( .INIT(8'hB8) )  \DATA_TRANSMIT_PROC.s_sdo_14_bm[3]  (.A(
        s_sdo_14_m0[3]), .B(s_sdo_14_m0s2), .C(
        apb3_en_if_1_adc_channel_ch2_o[3]), .Y(s_sdo_14_bm[3]));
    CFG4 #( .INIT(16'hB931) )  \SCK_GEN_PROC.s_r_sck_10_7_bm  (.A(
        s_r_sck_sel[1]), .B(s_r_sck_10_7_bm_1_1), .C(
        s_r_clock_count[7]), .D(s_r_clock_count[3]), .Y(
        s_r_sck_10_7_bm));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_ns[3]  (.A(
        s_sdo_14_bm[3]), .B(s_sdo_14_am[3]), .C(s_sdo_14_sm2), .Y(
        s_sdo_14[3]));
    SLE \s_sdo[14]  (.D(s_sdo_14[14]), .CLK(MC_System_0_FIC_0_CLK), 
        .EN(s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(
        VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[14]));
    SLE \result_ch2_o[7]  (.D(s_r_adc_data[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[7]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[6]  (
        .A(A0_ADC_CS_O_c), .B(s_r_adc_data[5]), .Y(s_r_adc_data_4[6]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_ns[11]  (.A(
        s_sdo_14_bm[11]), .B(s_sdo_14_am[11]), .C(s_sdo_14_sm2), .Y(
        s_sdo_14[11]));
    SLE \result_ch1_o[0]  (.D(s_r_adc_data[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[0]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[5]  (
        .A(A0_ADC_CS_O_c), .B(s_r_adc_data[4]), .Y(s_r_adc_data_4[5]));
    SLE \s_r_sck_sel[1]  (.D(apb3_en_if_1_adc_control_reg_val_o[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_sck_sel[1]));
    SLE \s_r_adc_data[0]  (.D(s_r_adc_data_4[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[0]));
    SLE \result_ch3_o[8]  (.D(s_r_adc_data[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch3_o[8]));
    CFG4 #( .INIT(16'hACA0) )  \DATA_TRANSMIT_PROC.s_sdo_14_am[10]  (
        .A(apb3_en_if_1_adc_channel_ch1_o[10]), .B(
        apb3_en_if_1_adc_channel_ch3_o[10]), .C(un1_s_sdo_1_sqmuxa_1_Z)
        , .D(s_sdo_3_sqmuxa_Z), .Y(s_sdo_14_am[10]));
    CFG2 #( .INIT(4'h8) )  \CHANNEL_CNT_PROC.s_channel_cnt_5_RNO[2]  (
        .A(s_channel_cnt_0_sqmuxa_Z), .B(s_channel_cnt[0]), .Y(CO0));
    CFG4 #( .INIT(16'h4000) )  s_r_sck_count_0_sqmuxa (.A(s_r_sck_Z), 
        .B(present_state[1]), .C(A0_ADC_SCK_O_c), .D(un13_s_r_sck), .Y(
        s_r_sck_count_0_sqmuxa_Z));
    SLE \s_r_clock_count[1]  (.D(s_r_clock_count_s[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_r_clock_count[1]));
    SLE \s_r_clock_count[0]  (.D(s_r_clock_count_s[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_r_clock_count[0]));
    CFG3 #( .INIT(8'hB8) )  \DATA_TRANSMIT_PROC.s_sdo_14_bm[15]  (.A(
        s_sdo_14_m0[15]), .B(s_sdo_14_m0s2), .C(
        apb3_en_if_1_adc_channel_ch2_o[15]), .Y(s_sdo_14_bm[15]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_ns[13]  (.A(
        s_sdo_14_bm[13]), .B(s_sdo_14_am[13]), .C(s_sdo_14_sm2), .Y(
        s_sdo_14[13]));
    SLE adc_sdo_dly (.D(s_sdo[15]), .CLK(MC_System_0_FIC_0_CLK), .EN(
        VCC), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(
        GND), .LAT(GND), .Q(adc_sdo_dly_Z));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_ns[4]  (.A(
        s_sdo_14_bm[4]), .B(s_sdo_14_am[4]), .C(s_sdo_14_sm2), .Y(
        s_sdo_14[4]));
    SLE \s_sdo[3]  (.D(s_sdo_14[3]), .CLK(MC_System_0_FIC_0_CLK), .EN(
        s_sdo_1_sqmuxa_3_i_0), .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), 
        .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_sdo[3]));
    CFG2 #( .INIT(4'h4) )  \DATA_CLOLLECTION_PROC.s_r_adc_data_4[8]  (
        .A(A0_ADC_CS_O_c), .B(s_r_adc_data[7]), .Y(s_r_adc_data_4[8]));
    CFG3 #( .INIT(8'hAC) )  \DATA_TRANSMIT_PROC.s_sdo_14_m0[8]  (.A(
        apb3_en_if_1_adc_channel_ch0_o[8]), .B(s_sdo[7]), .C(
        A0_ADC_CS_O_c), .Y(s_sdo_14_m0[8]));
    SLE \s_r_sck_count[2]  (.D(s_r_sck_count_n2_Z), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_counte), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_sck_count[2]));
    SLE \result_ch2_o[1]  (.D(s_r_adc_data[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch2_o[1]));
    SLE \s_r_adc_data[9]  (.D(s_r_adc_data_4[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(s_r_sck_count_0_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(s_r_adc_data[9]));
    SLE \result_ch1_o[2]  (.D(s_r_adc_data[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch1_o[2]));
    SLE \s_channel_cnt[1]  (.D(s_channel_cnt_5[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(s_channel_cnt[1])
        );
    SLE \result_ch0_o[11]  (.D(s_r_adc_data[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(result_ch0_o_0_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(adc_interface_0_result_ch0_o[11]));
    SLE \s_r_clock_count[7]  (.D(s_r_clock_count_s[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(VCC), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        s_r_clock_count[7]));
    SLE sck_o (.D(s_r_sck_Z), .CLK(MC_System_0_FIC_0_CLK), .EN(VCC), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(A0_ADC_SCK_O_c));
    
endmodule


module mas_pwm_scl_44s_18s_2s(
       s_product,
       s_mult_in0_5,
       pwm_gain_i,
       pwm_period_i,
       s_mas_done,
       reset_i,
       sys_clk_i,
       s_mas_en
    );
output [33:16] s_product;
input  [17:0] s_mult_in0_5;
input  [17:1] pwm_gain_i;
input  [17:0] pwm_period_i;
output s_mas_done;
input  reset_i;
input  sys_clk_i;
input  s_mas_en;

    wire [0:0] mas_done_sync;
    wire [43:0] product_o_NC;
    wire [43:0] product_o;
    wire MSC_net_164, MSC_net_165, MSC_net_166;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
N7nF2ZuXxjZAtPuBZfBSJilkZnU9JMX00KxITGiMprfmu634axOuHsPjbBV9pDgz
B4KKcKCApIc3kPJL6G8d1gPeAqoTPHuLAbEGY22bwBfUoEePArkLTIdBWu8SMyZJ
IxOoZCNJbjVRKssg5jy2FCrmlT4voYiTa8MLHIbbBko=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=8280)
`pragma protect data_block
[encoded data, 8128 characters]
2FK2uz8RZB/evTXdW9CWLQ==

`pragma protect end_protected

endmodule


module PWM_SCALING_2s_44s_15s_0_1_2_3_4(
       reset_i,
       sys_clk_i,
       start_i,
       va_i,
       vb_i,
       vc_i,
       pwm_period_i,
       pwm_gain_i,
       Va_o,
       Vb_o,
       Vc_o,
       done_o
    );
input  reset_i;
input  sys_clk_i;
input  start_i;
input  [17:0] va_i;
input  [17:0] vb_i;
input  [17:0] vc_i;
input  [17:0] pwm_period_i;
input  [17:0] pwm_gain_i;
output [17:0] Va_o;
output [17:0] Vb_o;
output [17:0] Vc_o;
output done_o;

    wire [33:16] s_product;
    wire [4:0] s_state;
    wire [17:0] \MUL_INP_GEN_PROC.s_mult_in0_5 ;
    wire [1:1] s_state_ns;
    wire [17:0] \MUL_INP_GEN_PROC.s_mult_in0_5_iv_0 ;
    wire MSC_net_208, MSC_net_209, MSC_net_210, MSC_net_211, 
        MSC_net_212, MSC_net_213, MSC_net_214, MSC_net_215, 
        MSC_net_216, MSC_net_217, MSC_net_218, MSC_net_219, 
        MSC_net_220, MSC_net_221, MSC_net_222, MSC_net_223, 
        MSC_net_224;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
ei7HKQrh/QTouTHnT6o+q2PFS/uY4ISEBsZA3IJMu+s99/JW4QfelpYTIOTA8Rgy
kquu2fye8oNGqc73qayKthdHSJbIJ27TIh7HM4Y0b8VAzn2jHUc8Le9v6jq9rp/s
uhTdKIjYp/8m39UpwdlFkENkcm0UT4nrOs4f/M8XhFk=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=30965)
`pragma protect data_block
[encoded data, 30464 characters]
zJ8UqnpwD0Z+ZF5yw5XVvg==

`pragma protect end_protected

endmodule


module hall_filter_34s_18s_16s_0_1(
       s_filter_out,
       s_filter_val_prev,
       s_spd_result,
       filter_factor_i,
       reset_i,
       sys_clk_i,
       fil_trig_i
    );
output [33:0] s_filter_out;
input  [33:0] s_filter_val_prev;
input  [25:8] s_spd_result;
input  [3:0] filter_factor_i;
input  reset_i;
input  sys_clk_i;
input  fil_trig_i;

    wire [32:0] s_filter_incr;
    wire [0:0] s_state_ns;
    wire [0:0] s_state;
    wire MSC_net_128, MSC_net_129, MSC_net_130, MSC_net_131, 
        MSC_net_132, MSC_net_133, MSC_net_134, MSC_net_135, 
        MSC_net_136, MSC_net_137, MSC_net_138, MSC_net_139, 
        MSC_net_140, MSC_net_141, MSC_net_142, MSC_net_143, 
        MSC_net_144, MSC_net_145, MSC_net_146, MSC_net_147, 
        MSC_net_148, MSC_net_149, MSC_net_150, MSC_net_151, 
        MSC_net_152, MSC_net_153, MSC_net_154, MSC_net_155, 
        MSC_net_156, MSC_net_157, MSC_net_158, MSC_net_159, 
        MSC_net_160, MSC_net_161, MSC_net_162, MSC_net_163, 
        MSC_net_164, MSC_net_165, MSC_net_166, MSC_net_167, 
        MSC_net_168, MSC_net_169, MSC_net_170, MSC_net_171, 
        MSC_net_172, MSC_net_173, MSC_net_174, MSC_net_175, 
        MSC_net_176, MSC_net_177, MSC_net_178, MSC_net_179, 
        MSC_net_180, MSC_net_181, MSC_net_182, MSC_net_183, 
        MSC_net_184, MSC_net_185, MSC_net_186, MSC_net_187, 
        MSC_net_188, MSC_net_189, MSC_net_190, MSC_net_191, 
        MSC_net_192, MSC_net_193, MSC_net_194, MSC_net_195, 
        MSC_net_196, MSC_net_197, MSC_net_198, MSC_net_199, 
        MSC_net_200, MSC_net_201, MSC_net_202, MSC_net_203, 
        MSC_net_204, MSC_net_205, MSC_net_206, MSC_net_207, 
        MSC_net_208, MSC_net_209, MSC_net_210, MSC_net_211, 
        MSC_net_212, MSC_net_213, MSC_net_214, MSC_net_215, 
        MSC_net_216, MSC_net_217, MSC_net_218, MSC_net_219, 
        MSC_net_220, MSC_net_221, MSC_net_222, MSC_net_223, 
        MSC_net_224, MSC_net_225, MSC_net_226, MSC_net_227, 
        MSC_net_228, MSC_net_229, MSC_net_230, MSC_net_231, 
        MSC_net_232, MSC_net_233, MSC_net_234, MSC_net_235, 
        MSC_net_236, MSC_net_237, MSC_net_238, MSC_net_239, 
        MSC_net_240, MSC_net_241, MSC_net_242, MSC_net_243, 
        MSC_net_244, MSC_net_245, MSC_net_246, MSC_net_247, 
        MSC_net_248, MSC_net_249, MSC_net_250, MSC_net_251, 
        MSC_net_252, MSC_net_253, MSC_net_254, MSC_net_255, 
        MSC_net_256, MSC_net_257, MSC_net_258, MSC_net_259, 
        MSC_net_260, MSC_net_261, MSC_net_262, MSC_net_263, 
        MSC_net_264, MSC_net_265, MSC_net_266, MSC_net_267, 
        MSC_net_268, MSC_net_269, MSC_net_270, MSC_net_271, 
        MSC_net_272, MSC_net_273, MSC_net_274, MSC_net_275, 
        MSC_net_276, MSC_net_277, MSC_net_278, MSC_net_279, 
        MSC_net_280, MSC_net_281, MSC_net_282, MSC_net_283, 
        MSC_net_284, MSC_net_285, MSC_net_286, MSC_net_287, 
        MSC_net_288, MSC_net_289, MSC_net_290, MSC_net_291, 
        MSC_net_292, MSC_net_293, MSC_net_294, MSC_net_295, 
        MSC_net_296, MSC_net_297, MSC_net_298, MSC_net_299, 
        MSC_net_300, MSC_net_301, MSC_net_302, MSC_net_303, 
        MSC_net_304, MSC_net_305, MSC_net_306, MSC_net_307, 
        MSC_net_308, MSC_net_309, MSC_net_310, MSC_net_311, 
        MSC_net_312, MSC_net_313, MSC_net_314, MSC_net_315, 
        MSC_net_316, MSC_net_317, MSC_net_318, MSC_net_319, 
        MSC_net_320, MSC_net_321, MSC_net_322, MSC_net_323, 
        MSC_net_324, MSC_net_325, MSC_net_326, MSC_net_327, 
        MSC_net_328, MSC_net_329, MSC_net_330, MSC_net_331, 
        MSC_net_332, MSC_net_333, MSC_net_334, MSC_net_335, 
        MSC_net_336, MSC_net_337, MSC_net_338, MSC_net_339, 
        MSC_net_340, MSC_net_341, MSC_net_342, MSC_net_343, 
        MSC_net_344, MSC_net_345, MSC_net_346, MSC_net_347, 
        MSC_net_348, MSC_net_349, MSC_net_350, MSC_net_351, 
        MSC_net_352, MSC_net_353, MSC_net_354, MSC_net_355, 
        MSC_net_356, MSC_net_357, MSC_net_358, MSC_net_359, 
        MSC_net_360, MSC_net_361, MSC_net_362, MSC_net_363, 
        MSC_net_364, MSC_net_365, MSC_net_366, MSC_net_367, 
        MSC_net_368, MSC_net_369, MSC_net_370, MSC_net_371, 
        MSC_net_372, MSC_net_373, MSC_net_374, MSC_net_375, 
        MSC_net_376, MSC_net_377, MSC_net_378, MSC_net_379, 
        MSC_net_380, MSC_net_381, MSC_net_382, MSC_net_383, 
        MSC_net_384, MSC_net_385, MSC_net_386, MSC_net_387, 
        MSC_net_388, MSC_net_389, MSC_net_390, MSC_net_391, 
        MSC_net_392, MSC_net_393, MSC_net_394, MSC_net_395, 
        MSC_net_396, MSC_net_397, MSC_net_398, MSC_net_399, 
        MSC_net_400, MSC_net_401, MSC_net_402, MSC_net_403, 
        MSC_net_404, MSC_net_405, MSC_net_406, MSC_net_407, 
        MSC_net_408, MSC_net_409, MSC_net_410, MSC_net_411, 
        MSC_net_412, MSC_net_413, MSC_net_414, MSC_net_415, 
        MSC_net_416, MSC_net_417, MSC_net_418, MSC_net_419, 
        MSC_net_420, MSC_net_421, MSC_net_422, MSC_net_423, 
        MSC_net_424, MSC_net_425, MSC_net_426, MSC_net_427, 
        MSC_net_428, MSC_net_429, MSC_net_430, MSC_net_431, 
        MSC_net_432, MSC_net_433, MSC_net_434, MSC_net_435, 
        MSC_net_436, MSC_net_437, MSC_net_438, MSC_net_439, 
        MSC_net_440, MSC_net_441, MSC_net_442, MSC_net_443, 
        MSC_net_444, MSC_net_445, MSC_net_446, MSC_net_447, 
        MSC_net_448, MSC_net_449, MSC_net_450, MSC_net_451, 
        MSC_net_452, MSC_net_453, MSC_net_454, MSC_net_455, 
        MSC_net_456, MSC_net_457, MSC_net_458, MSC_net_459, 
        MSC_net_460, MSC_net_461;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
m+62AbMctsCN6iHW4do3BU2RmgvvwmGklq84G7OW3C3mqweKZNfMXyiqgKxghMH8
hKtQW3Kd4GuDpB9X2p3aNkb4dIQoxzZO2BhPUmQQS0eGwEBKaTd0c530UHK4q1zW
nCV+nPdGnqe2Eo51RzVJBqE9REOApI8AJbSXN4dxHgw=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=69290)
`pragma protect data_block
[encoded data, 68224 characters]

`pragma protect end_protected

endmodule


module hall_mas_44s_18s_2s_0(
       s_omega_out_7,
       s_omega_out_8,
       s_omega_out_9,
       s_omega_out_10,
       s_omega_out_17,
       s_omega_out_0,
       s_omega_out_1,
       s_omega_out_2,
       s_omega_out_3,
       s_omega_out_4,
       s_omega_out_5,
       s_omega_out_6,
       s_speed_count,
       reset_i,
       sys_clk_i,
       s_hall_edge_det
    );
output s_omega_out_7;
output s_omega_out_8;
output s_omega_out_9;
output s_omega_out_10;
output s_omega_out_17;
output s_omega_out_0;
output s_omega_out_1;
output s_omega_out_2;
output s_omega_out_3;
output s_omega_out_4;
output s_omega_out_5;
output s_omega_out_6;
input  [17:0] s_speed_count;
input  reset_i;
input  sys_clk_i;
input  s_hall_edge_det;

    wire [23:12] P;
    wire [43:0] un1_mul_a_i_NC;
    wire [15:4] un1_mul_a_i;
    wire [43:24] un1_mul_a_i_ONC;
    wire MSC_net_121, MSC_net_122, MSC_net_123, MSC_net_124, 
        MSC_net_125, MSC_net_126, MSC_net_127, MSC_net_128, 
        MSC_net_129, MSC_net_130, MSC_net_131, MSC_net_132, 
        MSC_net_133, MSC_net_134, MSC_net_135, MSC_net_136, 
        MSC_net_137, MSC_net_138, MSC_net_139, MSC_net_140, 
        MSC_net_141, MSC_net_142, MSC_net_143, MSC_net_144, 
        MSC_net_145, MSC_net_146, MSC_net_147, MSC_net_148, 
        MSC_net_149, MSC_net_150, MSC_net_151;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
nlXD/VqBdaUHO8zybA7GROWk+CyAF1JA+wF8mbpStZ8Kk5eEZCTu51D9H3+lb7Cv
stDNjq+sIocTgV8OMMM5VsWFwTw37HD29uKGxdPjsQlR/UelvXpXD+Ifss53lgFK
2fjuoRasiCOcmlLZ7qx6sTNccgjhTNsJ/VC5LhAliVc=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=11160)
`pragma protect data_block
[encoded data, 10944 characters]
6jNOqxrTDhflCe9jzbcppdMp3sZZY7ozsgYnp+1pyXs=

`pragma protect end_protected

endmodule


module hall_mas_44s_18s_2s_1(
       s_spd_result,
       speed_factor_i,
       s_speed_raw_sig,
       reset_i,
       sys_clk_i,
       s_spd_window_calc_done_dly
    );
output [25:8] s_spd_result;
input  [17:0] speed_factor_i;
input  [16:0] s_speed_raw_sig;
input  reset_i;
input  sys_clk_i;
input  s_spd_window_calc_done_dly;

    wire [34:0] un1_mul_a_i;
    wire [43:0] un1_mul_a_i_NC;
    wire [43:43] product_o_4;
    wire [43:36] un1_mul_a_i_ONC;
    wire MSC_net_144, MSC_net_145, MSC_net_146, MSC_net_147, 
        MSC_net_148, MSC_net_149, MSC_net_150, MSC_net_151, 
        MSC_net_152, MSC_net_153, MSC_net_154, MSC_net_155, 
        MSC_net_156, MSC_net_157, MSC_net_158, MSC_net_159, 
        MSC_net_160, MSC_net_161, MSC_net_162, MSC_net_163, 
        MSC_net_164, MSC_net_165, MSC_net_166, MSC_net_167, 
        MSC_net_168, MSC_net_169, MSC_net_170, MSC_net_171, 
        MSC_net_172, MSC_net_173, MSC_net_174, MSC_net_175, 
        MSC_net_176, MSC_net_177, MSC_net_178, MSC_net_179, 
        MSC_net_180, MSC_net_181, MSC_net_182, MSC_net_183, 
        MSC_net_184, MSC_net_185, MSC_net_186, MSC_net_187, 
        MSC_net_188, MSC_net_189, MSC_net_190, MSC_net_191, 
        MSC_net_192, MSC_net_193, MSC_net_194, MSC_net_195, 
        MSC_net_196, MSC_net_197, MSC_net_198, MSC_net_199, 
        MSC_net_200, MSC_net_201, MSC_net_202, MSC_net_203, 
        MSC_net_204, MSC_net_205, MSC_net_206, MSC_net_207, 
        MSC_net_208, MSC_net_209, MSC_net_210, MSC_net_211, 
        MSC_net_212, MSC_net_213, MSC_net_214, MSC_net_215, 
        MSC_net_216, MSC_net_217, MSC_net_218, MSC_net_219, 
        MSC_net_220, MSC_net_221, MSC_net_222, MSC_net_223, 
        MSC_net_224, MSC_net_225, MSC_net_226;
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
BEhvLZ0nWniwdUAyr8B4o0yJg7QMNeEHeNUB97qTVS8EBbQJ3KL/XIv6UqqQEsc+
pu1q0y/M9atgFifSCbTiKkKiTPhapOlwAK5mA7i46KFQoJ6fEuGwtYNiiThYRPSy
7nQRYDHujZYVAHNTKW/sUraC81oBfbXILJ4jahnCwmE=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=13870)
`pragma protect data_block
[encoded data, 13632 characters]
IRdRnxKnpm+6siUqzx5Dxg==

`pragma protect end_protected

endmodule


module HALL_INTERFACE(
       reset_i,
       sys_clk_i,
       ha_i,
       hb_i,
       hc_i,
       clear_buffer_i,
       fil_trig_i,
       filter_factor_i,
       hall_sensor_pol_i,
       speed_factor_i,
       omega_done_o,
       omega_out_o,
       angle_out_raw_o,
       theta_output_o
    );
input  reset_i;
input  sys_clk_i;
input  ha_i;
input  hb_i;
input  hc_i;
input  clear_buffer_i;
input  fil_trig_i;
input  [3:0] filter_factor_i;
input  hall_sensor_pol_i;
input  [17:0] speed_factor_i;
output omega_done_o;
output [17:0] omega_out_o;
output [17:0] angle_out_raw_o;
output [17:0] theta_output_o;

    wire [17:0] angle_out_raw_o_net_1;
    wire [33:0] s_filter_out;
    wire [12:4] un1_s_ha_dly_0_iv;
    wire [25:8] s_spd_result;
    wire [33:0] s_filter_val_prev;
    wire [16:0] s_speed_raw_sig;
    wire [17:0] s_speed_count;
    wire [33:16] s_omega_out;
    wire [12:0] s_theta_incr;
    wire [12:0] s_theta_buff;
    wire [4:0] s_spd_window;
    wire [12:0] s_theta_output_buff;
    wire [17:0] s_hall_count_buff;
    wire [17:0] s_count_output;
    wire [4:0] s_spd_window_dly;
    wire [4:0] s_spd_window_dly1;
    wire [15:0] \FILTER_ACC_PROC.s_filter_val_prev_3 ;
    wire [15:0] \ANGLE_CNT_INCR_SIGNAL_DLY_GEN.s_speed_raw_sig_9 ;
    wire [12:0] s_speed_raw;
    wire [6:0] s_count_1us;
    wire [10:0] s_count_terminal;
    wire [7:0] s_limit_angle;
    wire [6:2] s_count_1us_3;
    wire [10:0] s_count_in_spd_win_3;
    wire [7:0] \THETA_SMOOTHEN_PROC.s_limit_angle_5 ;
    wire [12:1] \THETA_INCR_ROLL_PROC.s_speed_raw_4 ;
    wire [12:12] s_angle_out_raw;
    wire [8:3] s_count_terminal_2;
    wire [11:3] un1_s_sum_2_1_m;
    wire [8:0] \COUNT_TERM_PROC.s_count_in_spd_win7_0_data_tmp ;
    wire [3:3] s_speed_raw_m;
    wire [11:11] s_speed_raw_m_1;
    wire [12:0] inf_abs0;
    wire [12:1] s_diff_1;
    wire [17:1] s_hall_count_buff_p1;
    wire [0:0] s_count_in_spd_win_RNID0RI1_S;
    wire [1:1] s_count_in_spd_win_RNIQJ6P1_S;
    wire [2:2] s_count_in_spd_win_RNI88IV1_S;
    wire [3:3] s_count_in_spd_win_RNINTT52_S;
    wire [4:4] s_count_in_spd_win_RNI7K9C2_S;
    wire [5:5] s_count_in_spd_win_RNIOBLI2_S;
    wire [6:6] s_count_in_spd_win_RNIA41P2_S;
    wire [7:7] s_count_in_spd_win_RNITTCV2_S;
    wire [8:8] s_count_in_spd_win_RNIHOO53_S;
    wire [9:9] s_count_in_spd_win_RNI6K4C3_S;
    wire [10:10] s_count_in_spd_win_RNI392E3_S;
    wire [11:11] s_count_in_spd_win_RNI1VVF3_S;
    wire [12:12] s_count_in_spd_win_RNI0MTH3_S;
    wire [13:13] s_count_in_spd_win_RNI0ERJ3_S;
    wire [14:14] s_count_in_spd_win_RNI17PL3_S;
    wire [15:15] s_count_in_spd_win_RNI31NN3_S;
    wire [16:16] s_count_in_spd_win_RNI6SKP3_S;
    wire [17:17] s_count_in_spd_win_RNO_S;
    wire [17:0] s_count_in_spd_win;
    wire [16:0] s_speed_count_cry;
    wire [17:0] s_speed_count_s;
    wire [14:2] 
        \ANGLE_CNT_INCR_SIGNAL_DLY_GEN.s_speed_raw_sig_9_0_iv_0 ;
    wire [12:3] \ANGLE_CNT_INCR_SIGNAL_DLY_GEN.s_speed_raw_sig_9_iv_0 ;
    wire [12:4] \ANGLE_CNT_INCR_SIGNAL_DLY_GEN.s_speed_raw_sig_9_iv_1 ;
    wire [8:8] \COUNT_TERM_PROC.s_count_in_spd_win7_0_data_tmp_i_0 ;
    wire [4:0] s_spd_window_i_0;
    wire [0:0] s_count_1us_i_0;
    wire [4:4] un1_s_ha_dly_0_iv_0;
    wire [4:4] un1_s_ha_dly_0_iv_1;
    wire [4:4] un1_s_ha_dly_0_iv_2;
    wire [4:4] un1_s_ha_dly_0_iv_3;
    wire [16:0] s_speed_count_cry_Y;
    wire [17:17] s_speed_count_s_FCO;
    wire [17:17] s_speed_count_s_Y;
    wire [0:0] s_speed_count_cry_cy_S;
    wire [0:0] s_speed_count_cry_cy_Y;
    wire [16:16] s_count_in_spd_win_RNI6SKP3_Y;
    wire [17:17] s_count_in_spd_win_RNO_FCO;
    wire [17:17] s_count_in_spd_win_RNO_Y;
    wire [15:15] s_count_in_spd_win_RNI31NN3_Y;
    wire [14:14] s_count_in_spd_win_RNI17PL3_Y;
    wire [13:13] s_count_in_spd_win_RNI0ERJ3_Y;
    wire [12:12] s_count_in_spd_win_RNI0MTH3_Y;
    wire [11:11] s_count_in_spd_win_RNI1VVF3_Y;
    wire [10:10] s_count_in_spd_win_RNI392E3_Y;
    wire [9:9] s_count_in_spd_win_RNI6K4C3_Y;
    wire [8:8] s_count_in_spd_win_RNIHOO53_Y;
    wire [7:7] s_count_in_spd_win_RNITTCV2_Y;
    wire [6:6] s_count_in_spd_win_RNIA41P2_Y;
    wire [5:5] s_count_in_spd_win_RNIOBLI2_Y;
    wire [4:4] s_count_in_spd_win_RNI7K9C2_Y;
    wire [3:3] s_count_in_spd_win_RNINTT52_Y;
    wire [2:2] s_count_in_spd_win_RNI88IV1_Y;
    wire [1:1] s_count_in_spd_win_RNIQJ6P1_Y;
    wire [0:0] s_count_in_spd_win_RNID0RI1_Y;
    wire MSC_net_635, MSC_net_636, MSC_net_637, MSC_net_638, 
        MSC_net_639, MSC_net_640, MSC_net_641, MSC_net_642, 
        MSC_net_643, MSC_net_644, MSC_net_645, MSC_net_646, 
        MSC_net_647, MSC_net_648, MSC_net_649, MSC_net_650, 
        MSC_net_651, MSC_net_652, MSC_net_653, MSC_net_654, 
        MSC_net_655, MSC_net_656, MSC_net_657, MSC_net_658, 
        MSC_net_659, MSC_net_660, \THETA_INCR_PROC.s_theta_incr6_Z , 
        \THETA_INCR_ROLL_PROC.s_theta_roll_calc_done5_Z , MSC_net_663, 
        \SPD_WIN_PROC.s_spd_window_calc_done5_Z , MSC_net_665, 
        \ANGLE_CNT_INCR_SIGNAL_DLY_GEN.s_spd_window_dly14_Z , 
        MSC_net_667, \EDGE_DETECT_PROC.s_hall_edge_det_2_Z , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff , 
        \THETA_SMOOTHEN_PROC.s_theta_output19_Z , 
        \COUNT_TERM_PROC.un1_s_count_1us8_Z , 
        \DIR_DETECT_PROC.un1_s_dir4_Z , MSC_net_673, MSC_net_674, 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_0_Z , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_1_Z , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_2_Z , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_3_Z , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_4_Z , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_5_Z , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_6_Z , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_7_Z , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_8_Z , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_9_Z , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_10_Z , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_11_Z , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_12_Z , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_13_Z , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_14_Z , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_15_Z , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_16_Z , 
        \THETA_SMOOTHEN_PROC.s_count_output_5_iv_16_226_Z , 
        \THETA_SMOOTHEN_PROC.s_count_output_5_iv_15_234_Z , 
        \THETA_SMOOTHEN_PROC.s_count_output_5_iv_14_242_Z , 
        \THETA_SMOOTHEN_PROC.s_count_output_5_iv_13_250_Z , 
        \THETA_SMOOTHEN_PROC.s_count_output_5_iv_12_258_Z , 
        \THETA_SMOOTHEN_PROC.s_count_output_5_iv_11_266_Z , 
        \THETA_SMOOTHEN_PROC.s_count_output_5_iv_10_274_Z , 
        \THETA_SMOOTHEN_PROC.s_count_output_5_iv_9_282_Z , 
        \THETA_SMOOTHEN_PROC.s_count_output_5_iv_8_290_Z , 
        \THETA_SMOOTHEN_PROC.s_count_output_5_iv_7_298_Z , 
        \THETA_SMOOTHEN_PROC.s_count_output_5_iv_6_306_Z , 
        \THETA_SMOOTHEN_PROC.s_count_output_5_iv_5_314_Z , 
        \THETA_SMOOTHEN_PROC.s_count_output_5_iv_4_322_Z , 
        \THETA_SMOOTHEN_PROC.s_count_output_5_iv_3_330_Z , 
        \THETA_SMOOTHEN_PROC.s_count_output_5_iv_2_338_Z , 
        \THETA_SMOOTHEN_PROC.s_count_output_5_iv_1_346_Z , 
        \THETA_SMOOTHEN_PROC.s_count_output_5_iv_362_Z , 
        \THETA_SMOOTHEN_PROC.un1_s_omega_out_1_Z , MSC_net_710, 
        MSC_net_711, MSC_net_712, MSC_net_713, MSC_net_714, 
        MSC_net_715, MSC_net_716, \SPD_WIN_PROC.s_spd_window8 , 
        \COUNT_1MS_PROC.s_count_1us8lt4 , MSC_net_719, 
        \COUNT_1MS_PROC.s_count_1us8lt6 , MSC_net_721, 
        \THETA_SMOOTHEN_PROC.s_theta_output20_Z , 
        \THETA_SMOOTHEN_PROC.un1_s_count_1us8_Z , MSC_net_724, 
        \THETA_SMOOTHEN_PROC.s_count_output6lt4 , 
        \THETA_SMOOTHEN_PROC.s_count_output6lt7 , 
        \EDGE_DETECT_PROC.s_hall_edge_det_2_4_Z , MSC_net_728, 
        MSC_net_729, MSC_net_730, MSC_net_731, MSC_net_732, 
        MSC_net_733, MSC_net_734, MSC_net_735, MSC_net_736, 
        MSC_net_737, MSC_net_738, MSC_net_739, MSC_net_740, 
        MSC_net_741, MSC_net_742, MSC_net_743, MSC_net_744, 
        MSC_net_745, MSC_net_746, MSC_net_747, MSC_net_748, 
        MSC_net_749, MSC_net_750, MSC_net_751, MSC_net_752, 
        MSC_net_753, MSC_net_754, MSC_net_755, MSC_net_756, 
        MSC_net_757, MSC_net_758, MSC_net_759, MSC_net_760, 
        MSC_net_761, MSC_net_762, MSC_net_763, MSC_net_764, 
        MSC_net_765, MSC_net_766, MSC_net_767, MSC_net_768, 
        MSC_net_769, MSC_net_770, MSC_net_771, MSC_net_772, 
        MSC_net_773, MSC_net_774, MSC_net_775, MSC_net_776, 
        MSC_net_777, MSC_net_778, MSC_net_779, MSC_net_780, 
        MSC_net_781, MSC_net_782, MSC_net_783, MSC_net_784, 
        MSC_net_785, MSC_net_786, MSC_net_787, MSC_net_788, 
        MSC_net_789, MSC_net_790, MSC_net_791, MSC_net_792, 
        MSC_net_793, MSC_net_794, MSC_net_795, MSC_net_796, 
        MSC_net_797, MSC_net_798, MSC_net_799, MSC_net_800, 
        MSC_net_801, MSC_net_802, MSC_net_803, 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_0_Z , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_1_Z , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_2_Z , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_3_Z , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_4_Z , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_5_Z , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_6_Z , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_7_Z , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_8_Z , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_9_Z , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_10_Z , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_11_Z , MSC_net_816, 
        MSC_net_817, MSC_net_818, MSC_net_819, MSC_net_820, 
        MSC_net_821, MSC_net_822, MSC_net_823, MSC_net_824, 
        MSC_net_825, MSC_net_826, MSC_net_827, MSC_net_828, 
        MSC_net_829, MSC_net_830, MSC_net_831, MSC_net_832, 
        MSC_net_833, MSC_net_834, MSC_net_835, MSC_net_836, 
        MSC_net_837, MSC_net_838, MSC_net_839, MSC_net_840, 
        MSC_net_841, MSC_net_842, MSC_net_843, MSC_net_844, 
        \SPD_WIN_PROC.s_spd_window12lto17_0_202_0_a4_0_Z , 
        \THETA_SMOOTHEN_PROC.un1_s_omega_out_1_6_Z , 
        \THETA_SMOOTHEN_PROC.un1_s_omega_out_1_7_Z , 
        \THETA_SMOOTHEN_PROC.un1_s_omega_out_1_8_Z , 
        \SPD_WIN_PROC.un1_s_spd_window8_5_i_a4_2_1_Z , 
        \SPD_WIN_PROC.s_spd_window11_i_a2_0_Z , 
        \SPD_WIN_PROC.un1_s_spd_window8_5_i_a4_3_6_Z , 
        \SPD_WIN_PROC.un1_s_spd_window8_5_i_a4_3_7_Z , 
        \SPD_WIN_PROC.un1_s_spd_window8_5_i_a4_3_8_Z , 
        \SPD_WIN_PROC.un1_s_spd_window8_5_i_a4_3_9_Z , 
        \SPD_WIN_PROC.un1_s_spd_window8_5_i_a4_3_12_Z , 
        \SPD_WIN_PROC.un1_s_spd_window8_5_i_a4_1 , 
        \SPD_WIN_PROC.un1_s_spd_window8_5_i_a4_1_1_Z , 
        \THETA_INCR_ROLL_PROC.s_speed_raw6lto12_0_Z , 
        \THETA_INCR_ROLL_PROC.s_speed_raw6lto12_7_Z , 
        \THETA_INCR_ROLL_PROC.s_speed_raw6lto12_8_Z , 
        \THETA_INCR_ROLL_PROC.s_speed_raw6lto12_9_Z , MSC_net_862, 
        MSC_net_863, MSC_net_864, MSC_net_865, MSC_net_866, 
        MSC_net_867, MSC_net_868, MSC_net_869, MSC_net_870, 
        MSC_net_871, MSC_net_872, MSC_net_873, MSC_net_874, 
        MSC_net_875, MSC_net_876, MSC_net_877, MSC_net_878, 
        MSC_net_879, MSC_net_880, MSC_net_881, MSC_net_882, 
        MSC_net_883, MSC_net_884, MSC_net_885, MSC_net_886, 
        MSC_net_887, MSC_net_888, MSC_net_889, MSC_net_890, 
        MSC_net_891, MSC_net_892, MSC_net_893, MSC_net_894, 
        MSC_net_895, MSC_net_896, MSC_net_897, MSC_net_898, 
        MSC_net_899, MSC_net_900, MSC_net_901, MSC_net_902, 
        MSC_net_903, MSC_net_904, MSC_net_905, MSC_net_906, 
        MSC_net_907, MSC_net_908, MSC_net_909, MSC_net_910, 
        MSC_net_911, MSC_net_912, MSC_net_913, MSC_net_914, 
        MSC_net_915, MSC_net_916, MSC_net_917, MSC_net_918, 
        MSC_net_919, MSC_net_920, MSC_net_921, MSC_net_922, 
        MSC_net_923, MSC_net_924, MSC_net_925, MSC_net_926, 
        MSC_net_927, MSC_net_928, MSC_net_929, MSC_net_930, 
        MSC_net_931, MSC_net_932, MSC_net_933, MSC_net_934, 
        MSC_net_935, MSC_net_936, MSC_net_937, MSC_net_938, 
        MSC_net_939, MSC_net_940, MSC_net_941, MSC_net_942, 
        MSC_net_943, MSC_net_944, MSC_net_945, MSC_net_946, 
        MSC_net_947, MSC_net_948, MSC_net_949, MSC_net_950, 
        MSC_net_951, MSC_net_952, MSC_net_953, MSC_net_954, 
        MSC_net_955, MSC_net_956, MSC_net_957, MSC_net_958, 
        MSC_net_959, MSC_net_960, MSC_net_961, MSC_net_962, 
        MSC_net_963, \COUNT_TERM_PROC.s_count_in_spd_win7_0_I_51_S , 
        \COUNT_TERM_PROC.s_count_in_spd_win7_0_I_51_Y , 
        \COUNT_TERM_PROC.s_count_in_spd_win7_0_I_45_S , 
        \COUNT_TERM_PROC.s_count_in_spd_win7_0_I_45_Y , 
        \COUNT_TERM_PROC.s_count_in_spd_win7_0_I_39_S , 
        \COUNT_TERM_PROC.s_count_in_spd_win7_0_I_39_Y , 
        \COUNT_TERM_PROC.s_count_in_spd_win7_0_I_33_S , 
        \COUNT_TERM_PROC.s_count_in_spd_win7_0_I_33_Y , 
        \COUNT_TERM_PROC.s_count_in_spd_win7_0_I_27_S , 
        \COUNT_TERM_PROC.s_count_in_spd_win7_0_I_27_Y , 
        \COUNT_TERM_PROC.s_count_in_spd_win7_0_I_21_S , 
        \COUNT_TERM_PROC.s_count_in_spd_win7_0_I_21_Y , 
        \COUNT_TERM_PROC.s_count_in_spd_win7_0_I_15_S , 
        \COUNT_TERM_PROC.s_count_in_spd_win7_0_I_15_Y , 
        \COUNT_TERM_PROC.s_count_in_spd_win7_0_I_9_S , 
        \COUNT_TERM_PROC.s_count_in_spd_win7_0_I_9_Y , 
        \COUNT_TERM_PROC.s_count_in_spd_win7_0_I_1_S , 
        \COUNT_TERM_PROC.s_count_in_spd_win7_0_I_1_Y , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_17_S , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_17_Y , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_16_S , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_16_Y , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_15_S , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_15_Y , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_14_S , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_14_Y , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_13_S , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_13_Y , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_12_S , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_12_Y , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_11_S , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_11_Y , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_10_S , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_10_Y , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_9_S , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_9_Y , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_8_S , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_8_Y , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_7_S , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_7_Y , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_6_S , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_6_Y , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_5_S , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_5_Y , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_4_S , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_4_Y , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_3_S , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_3_Y , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_2_S , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_2_Y , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_1_S , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_1_Y , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_0_S , 
        \THETA_SMOOTHEN_PROC.un1_s_hall_count_buff_cry_0_Y , 
        MSC_net_1018, MSC_net_1019, MSC_net_1020, MSC_net_1021, 
        MSC_net_1022, MSC_net_1023, MSC_net_1024, MSC_net_1025, 
        MSC_net_1026, MSC_net_1027, MSC_net_1028, MSC_net_1029, 
        MSC_net_1030, MSC_net_1031, MSC_net_1032, 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_11_Y , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_s_12_FCO , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_s_12_Y , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_10_Y , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_9_Y , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_8_Y , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_7_Y , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_6_Y , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_5_Y , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_4_Y , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_3_Y , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_2_Y , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_1_Y , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_0_S , 
        \THETA_INCR_ROLL_PROC.s_speed_raw_4_cry_0_Y , MSC_net_1048, 
        MSC_net_1049, MSC_net_1050, MSC_net_1051, MSC_net_1052, 
        MSC_net_1053, MSC_net_1054, MSC_net_1055, MSC_net_1056, 
        MSC_net_1057, MSC_net_1058, MSC_net_1059, MSC_net_1060, 
        MSC_net_1061, MSC_net_1062, MSC_net_1063, 
        \COUNT_1MS_PROC.s_count_1us8lto4_RNI1EFC1_S , 
        \COUNT_1MS_PROC.s_count_1us8lto4_RNI1EFC1_Y ;
    assign omega_done_o = angle_out_raw_o_net_1[0];
    assign angle_out_raw_o[15] = angle_out_raw_o_net_1[15];
    assign angle_out_raw_o[14] = angle_out_raw_o_net_1[14];
    assign angle_out_raw_o[13] = angle_out_raw_o_net_1[15];
    assign angle_out_raw_o[12] = angle_out_raw_o_net_1[14];
    assign angle_out_raw_o[11] = angle_out_raw_o_net_1[15];
    assign angle_out_raw_o[10] = angle_out_raw_o_net_1[14];
    assign angle_out_raw_o[9] = angle_out_raw_o_net_1[15];
    assign angle_out_raw_o[8] = angle_out_raw_o_net_1[14];
    assign angle_out_raw_o[7] = angle_out_raw_o_net_1[15];
    assign angle_out_raw_o[6] = angle_out_raw_o_net_1[14];
    assign angle_out_raw_o[4] = angle_out_raw_o_net_1[0];
    assign angle_out_raw_o[3] = angle_out_raw_o_net_1[0];
    assign angle_out_raw_o[2] = angle_out_raw_o_net_1[0];
    assign angle_out_raw_o[1] = angle_out_raw_o_net_1[0];
    assign angle_out_raw_o[0] = angle_out_raw_o_net_1[0];
    assign theta_output_o[4] = angle_out_raw_o_net_1[0];
    assign theta_output_o[3] = angle_out_raw_o_net_1[0];
    assign theta_output_o[2] = angle_out_raw_o_net_1[0];
    assign theta_output_o[1] = angle_out_raw_o_net_1[0];
    assign theta_output_o[0] = angle_out_raw_o_net_1[0];
    
    
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="author-a", author_info="author-a-details"

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=128)
`pragma protect key_block
a10vhjRJTQQlR5y8dxOaVDUPUNOV81eioLK+ncVkVxUVxtkxKj9cfsjj65MIGIe1
nNQUAlFs6C1REdVQm6ch7/8jUtHx6/Xa4mL+8KsVAYay8rIZFOtospRjD5mmq0El
UBCRmQG/p0pjWuzlmk4gEdGwerrWtPu7BohYj6saDUE=

`pragma protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip", data_method="aes128-cbc"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=230840)
`pragma protect data_block
[encoded data, 227264 characters]
WqLIkOu+oo5nOXz6AA0ffg==

`pragma protect end_protected

endmodule


module 
        work_apb3_hall_if_apb3_hall_if_32_12_12_6_18_2_g_APB3_IF_DATA_WIDTHg_CONST_WIDTHg_ADC_OUT_WIDTHg_ADC_CONFIG_REG_WIDTHg_STD_IO_WIDTH(
        
       apb3_en_if_1_idq_pi_ki_o,
       MC_System_0_AMBA_SLAVE_0_PWDATA,
       apb3_en_if_1_idq_pi_kp_o,
       apb3_en_if_1_olmng_dv_o,
       apb3_en_if_1_olmng_iq_ref_in_o,
       apb3_en_if_1_olmng_theta_factor_o,
       apb3_en_if_1_pwm_dead_time_val_o,
       apb3_en_if_1_pwm_delay_time_val_o,
       apb3_en_if_1_pwm_gain_val_o,
       apb3_en_if_1_pwm_period_val_o,
       apb3_en_if_1_rate_limit_rate_cnt_o,
       apb3_en_if_1_rate_limit_ref_in_o,
       apb3_en_if_1_rate_limit_slew_cnt_o,
       apb3_en_if_1_seq_cntl_cl_omega_o,
       apb3_en_if_1_speed_pi_ki_o,
       apb3_en_if_1_speed_pi_kp_o,
       apb3_en_if_1_seq_cntl_config_o,
       apb3_hall_if_0_hall_filter_factor_o,
       apb3_en_if_1_auto_restart_no_o,
       apb3_en_if_1_adc_control_reg_val_o,
       apb3_en_if_1_adc_channel_ch0_o,
       apb3_en_if_1_adc_channel_ch1_o,
       apb3_en_if_1_adc_channel_ch2_o,
       apb3_en_if_1_adc_channel_ch3_o,
       apb3_en_if_1_adc_oc_thresh_o,
       apb3_en_if_1_adc_scale_val_o,
       apb3_hall_if_0_hall_speed_factor_o,
       MC_System_0_AMBA_SLAVE_0_PRDATA,
       prdata_o_1_iv_10_13,
       prdata_o_1_iv_9,
       prdata_o_1_0_iv_0_13,
       prdata_o_1_iv_10_11,
       MC_System_0_AMBA_SLAVE_0_PADDR,
       FOC_TRANSFORMS_0_ialpha_o_m_6,
       FOC_TRANSFORMS_0_valpha_o_m_0,
       FOC_TRANSFORMS_0_valpha_o_m_5,
       SEQ_CONTROLLER_0_state_o_0,
       SEQ_CONTROLLER_0_state_o_2,
       HALL_INTERFACE_1_angle_out_raw_o,
       HALL_INTERFACE_1_theta_output_o,
       adc_interface_0_result_ch3_o_m_4,
       FOC_TRANSFORMS_0_ialpha_o,
       SPEED_ID_IQ_PI_0_id_pi_output_o,
       adc_interface_0_result_ch0_o,
       FOC_TRANSFORMS_0_vbeta_o,
       adc_interface_0_result_ch1_o_5,
       adc_interface_0_result_ch1_o_6,
       adc_interface_0_result_ch1_o_4,
       adc_interface_0_result_ch1_o_2,
       adc_interface_0_result_ch1_o_9,
       adc_interface_0_result_ch1_o_0,
       adc_interface_0_result_ch1_o_3,
       adc_interface_0_result_ch1_o_7,
       adc_interface_0_result_ch1_o_8,
       adc_interface_0_result_ch1_o_10,
       FOC_TRANSFORMS_0_id_o_m_0,
       FOC_TRANSFORMS_0_iq_o,
       SPEED_ID_IQ_PI_0_speed_pi_output_o,
       ADC_SCALING_0_ib_adc_o,
       prdata_o_1_iv_0_6_0,
       prdata_o_1_iv_0_10,
       prdata_o_1_0_iv_0_14,
       prdata_o_1_iv_10,
       FOC_TRANSFORMS_0_valpha_o_4,
       FOC_TRANSFORMS_0_valpha_o_9,
       FOC_TRANSFORMS_0_valpha_o_3,
       FOC_TRANSFORMS_0_valpha_o_6,
       FOC_TRANSFORMS_0_valpha_o_11,
       FOC_TRANSFORMS_0_valpha_o_0,
       FOC_TRANSFORMS_0_valpha_o_7,
       FOC_TRANSFORMS_0_valpha_o_5,
       FOC_TRANSFORMS_0_valpha_o_14,
       FOC_TRANSFORMS_0_valpha_o_15,
       FOC_TRANSFORMS_0_valpha_o_1,
       FOC_TRANSFORMS_0_valpha_o_16,
       FOC_TRANSFORMS_0_valpha_o_17,
       FOC_TRANSFORMS_0_valpha_o_12,
       FOC_TRANSFORMS_0_valpha_o_10,
       FOC_TRANSFORMS_0_valpha_o_8,
       FOC_TRANSFORMS_0_valpha_o_13,
       prdata_o_1_iv_0_7_0,
       SPEED_ID_IQ_PI_0_iq_pi_output_o_11,
       SPEED_ID_IQ_PI_0_iq_pi_output_o_8,
       SPEED_ID_IQ_PI_0_iq_pi_output_o_1,
       SPEED_ID_IQ_PI_0_iq_pi_output_o_10,
       SPEED_ID_IQ_PI_0_iq_pi_output_o_15,
       SPEED_ID_IQ_PI_0_iq_pi_output_o_14,
       SPEED_ID_IQ_PI_0_iq_pi_output_o_16,
       SPEED_ID_IQ_PI_0_iq_pi_output_o_6,
       SPEED_ID_IQ_PI_0_iq_pi_output_o_17,
       SPEED_ID_IQ_PI_0_iq_pi_output_o_2,
       SPEED_ID_IQ_PI_0_iq_pi_output_o_5,
       SPEED_ID_IQ_PI_0_iq_pi_output_o_3,
       SPEED_ID_IQ_PI_0_iq_pi_output_o_4,
       SPEED_ID_IQ_PI_0_iq_pi_output_o_0,
       SPEED_ID_IQ_PI_0_iq_pi_output_o_7,
       SPEED_ID_IQ_PI_0_iq_pi_output_o_12,
       SPEED_ID_IQ_PI_0_iq_pi_output_o_13,
       HALL_INTERFACE_1_omega_out_o,
       RATE_LIMITER_0_rl_out_o,
       prdata_o_1_iv_13,
       prdata_o_1_iv_12,
       prdata_o_1_iv_10_0_0,
       OLMNG_0_theta_o,
       prdata_o_1_iv_0_9,
       prdata_o_1_iv_0_7,
       adc_interface_0_result_ch2_o,
       prdata_o_1_iv_10_12,
       ADC_SCALING_0_ia_adc_o,
       prdata_o_1_0_iv_0_15,
       prdata_o_1_iv_0_12_2,
       prdata_o_1_iv_0_12_0,
       prdata_o_1_iv_0_8,
       adc_interface_0_result_ch3_o,
       prdata_o_1_iv_14_2,
       prdata_o_1_iv_14_0,
       FOC_TRANSFORMS_0_id_o,
       prdata_o_1_iv_0_11_0,
       prdata_o_1_iv_0_11_2,
       prdata_o_1_iv_0_11_3,
       FOC_TRANSFORMS_0_ibeta_o,
       prdata_o_1_iv_11,
       MC_System_0_FIC_0_LOCK,
       MC_System_0_FIC_0_CLK,
       apb3_en_if_1_stop_motor_o,
       apb3_en_if_1_start_motor_o,
       apb3_hall_if_0_hall_sensor_polarity_o,
       apb3_en_if_1_fault_clr_o,
       apb3_en_if_0_direction_config_o,
       N_358,
       prdata_o277,
       prdata_o267,
       prdata_N_5_mux_i_3_a0_7_1,
       prdata_N_5_mux_i_3_a0_10,
       prdata_o263,
       prdata_N_5_mux_i_1_a0_13,
       N_435_4,
       prdata_N_5_mux_i_2_a0_11,
       prdata_o259,
       prdata_m2_e_5_6_1,
       prdata_N_5_mux_i_4_a0_11,
       prdata_o274,
       prdata_m2_e_27_10,
       prdata_m2_0_a2_1_0,
       prdata_m2_0_a2_17_0,
       prdata_o270,
       MC_System_0_AMBA_SLAVE_0_PSELx,
       MC_System_0_AMBA_SLAVE_0_PWRITE,
       MC_System_0_AMBA_SLAVE_0_PENABLE,
       N_296,
       prdata_o260,
       N_225,
       prdata_m2_e_5_1,
       prdata_N_5_mux_i_3_a0_4,
       prdata_N_5_mux_i_3_a0_0,
       prdata_N_5_mux_i_2_a0_4,
       prdata_N_5_mux_i_2_a0_0,
       N_286,
       N_283,
       prdata_m2_e_5_11,
       prdata_m2_e_5_6,
       prdata_m2_e_5_4,
       prdata_m2_e_27_11,
       prdata_m2_e_0_9,
       prdata_N_5_mux_i_4_a0_12,
       prdata_N_5_mux_i_3_a0_12,
       prdata_N_5_mux_i_1_a0_12,
       prdata_N_5_mux_i_2_a0_12,
       m7_i_2,
       prdata_m2_e_0_8,
       prdata_N_5_mux_i_2_a0_10,
       N_157,
       prdata_m2_e_5_10,
       prdata_m2_e_27_12,
       prdata_m2_e_0_10,
       prdata_N_5_mux_i_4_a0_13,
       prdata_N_5_mux_i_3_a0_11
    );
output [17:0] apb3_en_if_1_idq_pi_ki_o;
input  [17:0] MC_System_0_AMBA_SLAVE_0_PWDATA;
output [17:0] apb3_en_if_1_idq_pi_kp_o;
output [17:0] apb3_en_if_1_olmng_dv_o;
output [17:0] apb3_en_if_1_olmng_iq_ref_in_o;
output [17:0] apb3_en_if_1_olmng_theta_factor_o;
output [17:0] apb3_en_if_1_pwm_dead_time_val_o;
output [17:0] apb3_en_if_1_pwm_delay_time_val_o;
output [17:1] apb3_en_if_1_pwm_gain_val_o;
output [17:0] apb3_en_if_1_pwm_period_val_o;
output [17:0] apb3_en_if_1_rate_limit_rate_cnt_o;
output [17:0] apb3_en_if_1_rate_limit_ref_in_o;
output [17:0] apb3_en_if_1_rate_limit_slew_cnt_o;
output [17:0] apb3_en_if_1_seq_cntl_cl_omega_o;
output [17:0] apb3_en_if_1_speed_pi_ki_o;
output [17:0] apb3_en_if_1_speed_pi_kp_o;
output [3:0] apb3_en_if_1_seq_cntl_config_o;
output [3:0] apb3_hall_if_0_hall_filter_factor_o;
output [3:0] apb3_en_if_1_auto_restart_no_o;
output [5:0] apb3_en_if_1_adc_control_reg_val_o;
output [15:0] apb3_en_if_1_adc_channel_ch0_o;
output [15:0] apb3_en_if_1_adc_channel_ch1_o;
output [15:0] apb3_en_if_1_adc_channel_ch2_o;
output [15:0] apb3_en_if_1_adc_channel_ch3_o;
output [17:0] apb3_en_if_1_adc_oc_thresh_o;
output [17:0] apb3_en_if_1_adc_scale_val_o;
output [17:0] apb3_hall_if_0_hall_speed_factor_o;
output [19:19] MC_System_0_AMBA_SLAVE_0_PRDATA;
output [10:10] prdata_o_1_iv_10_13;
output [16:16] prdata_o_1_iv_9;
output [1:1] prdata_o_1_0_iv_0_13;
output [10:10] prdata_o_1_iv_10_11;
input  [11:0] MC_System_0_AMBA_SLAVE_0_PADDR;
output FOC_TRANSFORMS_0_ialpha_o_m_6;
output FOC_TRANSFORMS_0_valpha_o_m_0;
output FOC_TRANSFORMS_0_valpha_o_m_5;
input  SEQ_CONTROLLER_0_state_o_0;
input  SEQ_CONTROLLER_0_state_o_2;
input  [17:5] HALL_INTERFACE_1_angle_out_raw_o;
input  [17:5] HALL_INTERFACE_1_theta_output_o;
output adc_interface_0_result_ch3_o_m_4;
input  [17:1] FOC_TRANSFORMS_0_ialpha_o;
input  [17:1] SPEED_ID_IQ_PI_0_id_pi_output_o;
input  [11:1] adc_interface_0_result_ch0_o;
input  [17:0] FOC_TRANSFORMS_0_vbeta_o;
input  adc_interface_0_result_ch1_o_5;
input  adc_interface_0_result_ch1_o_6;
input  adc_interface_0_result_ch1_o_4;
input  adc_interface_0_result_ch1_o_2;
input  adc_interface_0_result_ch1_o_9;
input  adc_interface_0_result_ch1_o_0;
input  adc_interface_0_result_ch1_o_3;
input  adc_interface_0_result_ch1_o_7;
input  adc_interface_0_result_ch1_o_8;
input  adc_interface_0_result_ch1_o_10;
output FOC_TRANSFORMS_0_id_o_m_0;
input  [17:0] FOC_TRANSFORMS_0_iq_o;
input  [17:0] SPEED_ID_IQ_PI_0_speed_pi_output_o;
input  [17:0] ADC_SCALING_0_ib_adc_o;
output prdata_o_1_iv_0_6_0;
output [15:14] prdata_o_1_iv_0_10;
output [1:1] prdata_o_1_0_iv_0_14;
output [16:16] prdata_o_1_iv_10;
input  FOC_TRANSFORMS_0_valpha_o_4;
input  FOC_TRANSFORMS_0_valpha_o_9;
input  FOC_TRANSFORMS_0_valpha_o_3;
input  FOC_TRANSFORMS_0_valpha_o_6;
input  FOC_TRANSFORMS_0_valpha_o_11;
input  FOC_TRANSFORMS_0_valpha_o_0;
input  FOC_TRANSFORMS_0_valpha_o_7;
input  FOC_TRANSFORMS_0_valpha_o_5;
input  FOC_TRANSFORMS_0_valpha_o_14;
input  FOC_TRANSFORMS_0_valpha_o_15;
input  FOC_TRANSFORMS_0_valpha_o_1;
input  FOC_TRANSFORMS_0_valpha_o_16;
input  FOC_TRANSFORMS_0_valpha_o_17;
input  FOC_TRANSFORMS_0_valpha_o_12;
input  FOC_TRANSFORMS_0_valpha_o_10;
input  FOC_TRANSFORMS_0_valpha_o_8;
input  FOC_TRANSFORMS_0_valpha_o_13;
output [13:13] prdata_o_1_iv_0_7_0;
input  SPEED_ID_IQ_PI_0_iq_pi_output_o_11;
input  SPEED_ID_IQ_PI_0_iq_pi_output_o_8;
input  SPEED_ID_IQ_PI_0_iq_pi_output_o_1;
input  SPEED_ID_IQ_PI_0_iq_pi_output_o_10;
input  SPEED_ID_IQ_PI_0_iq_pi_output_o_15;
input  SPEED_ID_IQ_PI_0_iq_pi_output_o_14;
input  SPEED_ID_IQ_PI_0_iq_pi_output_o_16;
input  SPEED_ID_IQ_PI_0_iq_pi_output_o_6;
input  SPEED_ID_IQ_PI_0_iq_pi_output_o_17;
input  SPEED_ID_IQ_PI_0_iq_pi_output_o_2;
input  SPEED_ID_IQ_PI_0_iq_pi_output_o_5;
input  SPEED_ID_IQ_PI_0_iq_pi_output_o_3;
input  SPEED_ID_IQ_PI_0_iq_pi_output_o_4;
input  SPEED_ID_IQ_PI_0_iq_pi_output_o_0;
input  SPEED_ID_IQ_PI_0_iq_pi_output_o_7;
input  SPEED_ID_IQ_PI_0_iq_pi_output_o_12;
input  SPEED_ID_IQ_PI_0_iq_pi_output_o_13;
input  [17:1] HALL_INTERFACE_1_omega_out_o;
input  [17:0] RATE_LIMITER_0_rl_out_o;
output [7:7] prdata_o_1_iv_13;
output [7:7] prdata_o_1_iv_12;
output prdata_o_1_iv_10_0_0;
input  [17:0] OLMNG_0_theta_o;
output [14:14] prdata_o_1_iv_0_9;
output [12:12] prdata_o_1_iv_0_7;
input  [11:0] adc_interface_0_result_ch2_o;
output [10:10] prdata_o_1_iv_10_12;
input  [17:0] ADC_SCALING_0_ia_adc_o;
output [1:0] prdata_o_1_0_iv_0_15;
output prdata_o_1_iv_0_12_2;
output prdata_o_1_iv_0_12_0;
output [13:13] prdata_o_1_iv_0_8;
input  [11:0] adc_interface_0_result_ch3_o;
output prdata_o_1_iv_14_2;
output prdata_o_1_iv_14_0;
input  [17:0] FOC_TRANSFORMS_0_id_o;
output prdata_o_1_iv_0_11_0;
output prdata_o_1_iv_0_11_2;
output prdata_o_1_iv_0_11_3;
input  [17:1] FOC_TRANSFORMS_0_ibeta_o;
output [16:16] prdata_o_1_iv_11;
input  MC_System_0_FIC_0_LOCK;
input  MC_System_0_FIC_0_CLK;
output apb3_en_if_1_stop_motor_o;
output apb3_en_if_1_start_motor_o;
output apb3_hall_if_0_hall_sensor_polarity_o;
output apb3_en_if_1_fault_clr_o;
output apb3_en_if_0_direction_config_o;
output N_358;
output prdata_o277;
output prdata_o267;
output prdata_N_5_mux_i_3_a0_7_1;
output prdata_N_5_mux_i_3_a0_10;
output prdata_o263;
output prdata_N_5_mux_i_1_a0_13;
output N_435_4;
output prdata_N_5_mux_i_2_a0_11;
output prdata_o259;
output prdata_m2_e_5_6_1;
output prdata_N_5_mux_i_4_a0_11;
output prdata_o274;
output prdata_m2_e_27_10;
output prdata_m2_0_a2_1_0;
output prdata_m2_0_a2_17_0;
output prdata_o270;
input  MC_System_0_AMBA_SLAVE_0_PSELx;
input  MC_System_0_AMBA_SLAVE_0_PWRITE;
input  MC_System_0_AMBA_SLAVE_0_PENABLE;
output N_296;
output prdata_o260;
output N_225;
output prdata_m2_e_5_1;
output prdata_N_5_mux_i_3_a0_4;
output prdata_N_5_mux_i_3_a0_0;
output prdata_N_5_mux_i_2_a0_4;
output prdata_N_5_mux_i_2_a0_0;
output N_286;
output N_283;
output prdata_m2_e_5_11;
output prdata_m2_e_5_6;
output prdata_m2_e_5_4;
output prdata_m2_e_27_11;
output prdata_m2_e_0_9;
output prdata_N_5_mux_i_4_a0_12;
output prdata_N_5_mux_i_3_a0_12;
output prdata_N_5_mux_i_1_a0_12;
output prdata_N_5_mux_i_2_a0_12;
output m7_i_2;
output prdata_m2_e_0_8;
output prdata_N_5_mux_i_2_a0_10;
output N_157;
output prdata_m2_e_5_10;
output prdata_m2_e_27_12;
output prdata_m2_e_0_10;
output prdata_N_5_mux_i_4_a0_13;
output prdata_N_5_mux_i_3_a0_11;

    wire [18:18] prdata_o_1_RNO;
    wire [15:14] prdata_o_1_iv_0_5_1;
    wire [15:13] prdata_o_1_iv_0_5;
    wire [15:15] prdata_o_1_iv_0_12_1;
    wire [15:15] prdata_o_1_iv_0_6_0_Z;
    wire [15:15] prdata_o_1_iv_0_1_1;
    wire [10:10] prdata_o_1_iv_10_7;
    wire [10:10] prdata_o_1_iv_10_13_1;
    wire [10:10] prdata_o_1_iv_10_2;
    wire [16:16] prdata_o_1_iv_5_1;
    wire [0:0] prdata_o_1_0_iv_0_15_3_1;
    wire [16:16] prdata_o_1_iv_9_1;
    wire [16:16] prdata_o_1_iv_4;
    wire [9:5] HALL_INTERFACE_1_omega_out_o_m;
    wire [0:0] prdata_o_1_0_iv_0_15_1;
    wire [0:0] prdata_o_1_0_iv_0_15_3;
    wire [0:0] prdata_o_1_0_iv_0_15_0;
    wire [0:0] prdata_o_1_0_iv_0_2_0_1;
    wire [1:1] prdata_o_1_0_iv_0_0;
    wire [1:1] prdata_o_1_0_iv_0_12_1;
    wire [10:10] prdata_o_1_iv_10_0;
    wire [10:10] prdata_o_1_iv_10_11_1;
    wire [16:3] FOC_TRANSFORMS_0_vbeta_o_m;
    wire [16:5] prdata_o_1_iv_1;
    wire [7:5] prdata_o_1_iv_5;
    wire [5:5] prdata_o_1_iv_9_0;
    wire [12:12] prdata_o_1_iv_0_13_tz_RNO_0;
    wire [16:16] prdata_o_1_iv_1_RNO_0;
    wire [13:13] prdata_o_1_iv_0_2_RNO_0;
    wire [14:14] prdata_o_1_iv_0_6_a0_0;
    wire [16:16] prdata_o_1_iv_6_a0_0;
    wire [3:3] prdata_o_1_0_iv_1_a0_1;
    wire [3:3] prdata_o_1_0_iv_1_a1_3_0;
    wire [10:5] FOC_TRANSFORMS_0_ibeta_o_m_0;
    wire [1:1] prdata_o_1_0_iv_0_a2_3_0;
    wire [5:5] prdata_o_1_iv_18_1;
    wire [2:2] prdata_o_1_0_iv_0_a5_0_0;
    wire [3:3] prdata_o_1_0_iv_1_a1_1;
    wire [3:3] prdata_o_1_0_iv_1_a0_2_0;
    wire [10:5] prdata_o_1_iv_9_tz;
    wire [1:1] prdata_o_1_0_iv_0_9_tz;
    wire [1:1] prdata_o_1_0_iv_0_8_tz;
    wire [14:14] prdata_o_1_iv_0_7_tz;
    wire [0:0] prdata_o_1_0_iv_0_15_2_tz;
    wire [12:12] prdata_o_1_iv_0_13_0_tz;
    wire [13:13] prdata_o_1_iv_0_1_a1;
    wire [13:13] prdata_o_1_iv_0_1_a0;
    wire [8:8] SPEED_ID_IQ_PI_0_id_pi_output_o_m;
    wire [3:3] prdata_o_1_0_iv_1_a1;
    wire [3:3] prdata_o_1_0_iv_1_a0;
    wire [13:12] prdata_o_1_iv_0_0;
    wire [16:16] prdata_o_1_iv_6_a0;
    wire [14:14] prdata_o_1_iv_0_6_a0;
    wire [7:7] FOC_TRANSFORMS_0_ibeta_o_m;
    wire [14:14] prdata_o_1_iv_0_13_a1;
    wire [16:16] prdata_o_1_iv_13_a1;
    wire [5:5] prdata_o_1_iv_17_a2;
    wire [3:3] FOC_TRANSFORMS_0_ialpha_o_m;
    wire [7:7] adc_interface_0_result_ch0_o_m;
    wire [7:5] prdata_o_1_iv_3;
    wire [7:5] prdata_o_1_iv_0;
    wire [5:5] prdata_o_1_iv_2;
    wire [15:14] prdata_o_1_iv_0_4;
    wire [14:13] prdata_o_1_iv_0_1;
    wire [12:12] prdata_o_1_iv_0_3;
    wire [10:10] prdata_o_1_iv_10_5;
    wire [10:10] prdata_o_1_iv_10_1;
    wire [1:1] prdata_o_1_0_iv_0_4;
    wire [1:1] prdata_o_1_0_iv_0_3;
    wire [1:1] prdata_o_1_0_iv_0_1;
    wire [13:12] prdata_o_1_iv_0_2;
    wire [7:5] adc_interface_0_result_ch2_o_m;
    wire [7:5] adc_interface_0_result_ch3_o_m;
    wire [6:6] SPEED_ID_IQ_PI_0_iq_pi_output_o_m;
    wire [16:7] prdata_o_1_iv_6;
    wire [5:5] prdata_o_1_iv_8;
    wire [10:10] prdata_o_1_iv_10_4;
    wire [1:1] prdata_o_1_0_iv_0_6;
    wire [1:1] prdata_o_1_0_iv_0_5;
    wire [16:16] FOC_TRANSFORMS_0_id_o_m;
    wire [7:7] FOC_TRANSFORMS_0_iq_o_m;
    wire [7:7] SPEED_ID_IQ_PI_0_speed_pi_output_o_m;
    wire [7:7] prdata_o_1_iv_7;
    wire [14:13] prdata_o_1_iv_0_6;
    wire VCC, idq_pi_ki_o_1_sqmuxa, GND, idq_pi_kp_o_1_sqmuxa_Z, 
        olmng_dv_o_1_sqmuxa_Z, olmng_iq_ref_in_o_1_sqmuxa, 
        olmng_theta_factor_o_1_sqmuxa, pwm_dead_time_val_o_1_sqmuxa, 
        pwm_delay_time_val_o_1_sqmuxa, pwm_gain_val_o_1_sqmuxa, 
        pwm_period_val_o_1_sqmuxa, rate_limit_rate_cnt_o_1_sqmuxa, 
        rate_limit_ref_in_o_1_sqmuxa, rate_limit_slew_cnt_o_1_sqmuxa, 
        seq_cntl_cl_omega_o_1_sqmuxa, speed_pi_ki_o_1_sqmuxa, 
        speed_pi_kp_o_0_sqmuxa_Z, auto_restart_no_o_1_sqmuxa, 
        adc_control_reg_val_o_1_sqmuxa, seq_cntl_config_o_1_sqmuxa, 
        hall_filter_factor_o_1_sqmuxa_Z, adc_channel_ch0_o_1_sqmuxa, 
        adc_channel_ch1_o_1_sqmuxa, adc_channel_ch2_o_1_sqmuxa, 
        adc_channel_ch3_o_1_sqmuxa, adc_oc_thresh_o_1_sqmuxa, 
        adc_scale_val_o_1_sqmuxa, hall_speed_factor_o_1_sqmuxa, 
        stop_motor_o_1_sqmuxa, start_motor_o_1_sqmuxa, 
        hall_sensor_polarity_o_1_sqmuxa, fault_clr_o_1_sqmuxa, 
        direction_config_o_1_sqmuxa_Z, prdata_o276, N_308, N_220, 
        prdata_o275, N_303, N_307, N_301, prdata_o261, 
        prdata_m1_0_a2_4_1, prdata_o264, prdata_o277_RNI7HP94, 
        prdata_N_5_mux_i_3_a0_2, READ_m2_e_3_1_Z, N_118, 
        READ_m2_e_3_1_0_Z, N_353, prdata_o275_0_a2_N_2L1, N_101, N_391, 
        N_371, SPEED_m1_0_a2_1, prdata_m2_e_0_1_1_Z, prdata_m2_e_0_3_1, 
        prdata_m2_e_0_3, prdata_o276_2_0_RNI202U, READ_m2_e_N_2L1_Z, 
        N_355, prdata_N_5_mux_i_1_a0_2, prdata_N_5_mux_i_1_a0_4, 
        prdata_N_5_mux_i_1_a0_7, prdata_N_5_mux_i_1_a0_13_1, 
        hall_speed_factor_o_1_sqmuxa_0_a2_RNIN18V1_Z, 
        prdata_o267_1_RNIT66V, prdata_N_5_mux_i_1_a0_9_N_2L1_Z, N_364, 
        pwm_period_val_o_1_sqmuxa_8, 
        pwm_period_val_o_1_sqmuxa_8_0_a5_RNISD05_Z, prdata_o267_1, 
        N_360, m5_N_6_mux_i_0, m5_i_o2_3_1_0_1_Z, m5_i_o2_3_1_0, 
        m5_m2_Z, N_403, m5_i_o2_3_2, prdata_N_5_mux_i_2_a0_1, 
        prdata_o273, prdata_N_5_mux_i_2_a0_11_1, 
        prdata_N_5_mux_i_4_a0_1, prdata_N_5_mux_i_4_a0_11_1, 
        prdata_o272, prdata_m2_e_27_2, prdata_m2_e_27_7, 
        prdata_m2_e_27_10_1, prdata_m2_e_17_1_Z, FOC_m1_0_a2_1, N_359, 
        READ_m2_e_1_Z, prdata_N_5_mux_i_3_a0_3_1, 
        prdata_N_5_mux_i_3_a0_3, prdata_m2_0_a2_7_0_0, 
        prdata_m2_0_a2_31_0_Z, prdata_N_5_mux_i_4_a0_1_1_Z, 
        prdata_m2_6_Z, prdata_o275_0_a2_0, prdata_m2_i_a3_2_0_Z, 
        prdata_m2_i_a3_1_0_Z, prdata_m2_i_a3_0_0_Z, 
        speed_pi_kp_o_0_sqmuxa_0_Z, hall_filter_factor_o_1_sqmuxa_1_Z, 
        prdata_m4_0, m5_m2_0_a2_0_Z, READ_m3_e_0_Z, N_369, N_370, 
        N_373, N_367, prdata_o260_6, prdata_o267_5, N_1608, 
        olmng_dv_o_1_sqmuxa_3, olmng_dv_o_1_sqmuxa_4, 
        olmng_dv_o_1_sqmuxa_5, N_363, prdata_m2_19_Z, prdata_m2_5_Z, 
        prdata_m2_3_Z, prdata_m2_2_Z, prdata_m2_1_Z, prdata_m2_0_Z, 
        olmng_dv_o_1_sqmuxa_0_Z, idq_pi_kp_o_1_sqmuxa_1_Z, 
        direction_config_o_1_sqmuxa_1_Z, prdata_m1_0_a2_11_1_Z, 
        m7_m1_0_a2_1_Z, FOC_m1_0_a2_1_1_Z, FOC_m1_0_a2_2_1_Z, 
        FOC_m1_0_a2_0_1_Z, prdata_m1_0_a2_1_1, prdata_o276_1, 
        m7_m2_e_1_Z, prdata_o270_0_a2_0, prdata_o277_2_1, 
        prdata_o267_1_0, SPEED_N_5_mux_2, prdata_N_5_mux_28, 
        prdata_N_5_mux_24, ADC_N_5_mux, prdata_N_5_mux_17, 
        SPEED_N_5_mux_1, prdata_N_5_mux_13, OLMNG_N_5_mux_2, 
        OLMNG_N_5_mux_1, OLMNG_N_5_mux_0, m7_N_5_mux, 
        prdata_o260_0_a2_1, olmng_dv_o_1_sqmuxa_9, 
        speed_pi_kp_o_0_sqmuxa_9, prdata_o277_2_0, prdata_o259_1, 
        prdata_o259_2, prdata_o277_1_0, N_390, N_406, N_352, 
        prdata_m3_13_0_Z, prdata_m1_0_a2_0_0, prdata_m3_i_0, 
        prdata_m3_i_0_0, prdata_m2_0_a2_11_0, prdata_m2_0_a2_3_0_Z, 
        prdata_m2_0_a2_29_0_Z, prdata_m2_0_a2_21_0, 
        prdata_m2_0_a2_23_0, prdata_m2_0_a2_5_0_Z, 
        prdata_m2_0_a2_35_0_Z, prdata_m2_0_a2_13_0, prdata_m2_0_a2_0_Z, 
        prdata_m2_0_a2_27_0, prdata_m2_0_a2_25_0, prdata_m2_0_a2_0_16, 
        speed_pi_kp_o_0_sqmuxa_1_Z, hall_filter_factor_o_1_sqmuxa_2_Z, 
        prdata_o275_0_a2_2, FOC_m3_e_2, READ_m2_e_2_1, N_376, 
        prdata_o264_0_a2_1, prdata_m2_e_4_9_tz, prdata_m2_e_0_13_tz_Z, 
        adc_scale_val_o_1_sqmuxa_0_a2_0_0_Z, prdata_o259_2_RNI6SNT, 
        N_381, N_375, un3_psel_i, N_425, N_321, N_243, 
        olmng_dv_o_1_sqmuxa_7, N_404, 
        hall_speed_factor_o_1_sqmuxa_0_a2_RNIFHKE5_Z, 
        hall_speed_factor_o_1_sqmuxa_0_a2_RNIBDKE5_Z, 
        hall_speed_factor_o_1_sqmuxa_0_a2_RNI3AHL5_Z, N_365, N_361, 
        N_348, N_347, N_338, prdata_m2_e_5_0, prdata_m2_e_27_6, 
        prdata_m2_e_27_3, m7_i_0, prdata_m2_e_0_0, 
        prdata_N_5_mux_i_4_a0_4, prdata_N_5_mux_i_4_a0_2, 
        prdata_N_5_mux_i_2_a0_2, prdata_m2_e_5_9, 
        prdata_o260_0_a2_1_RNI3FNN, N_398, prdata_o257, prdata_o265, 
        N_145, N_409, prdata_m2_e_5_2, prdata_m2_e_0_6, 
        prdata_m2_e_0_5, prdata_m2_e_0_4, prdata_N_5_mux_i_4_a0_7, 
        prdata_N_5_mux_i_4_a0_6, prdata_N_5_mux_i_4_a0_5, 
        prdata_N_5_mux_i_2_a0_7, N_343, N_342, N_339, N_337, N_330, 
        N_329, N_326, N_324, N_313, N_982;
    
    CFG2 #( .INIT(4'h4) )  prdata_m2_i_a3_1_0 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(
        FOC_TRANSFORMS_0_id_o[6]), .Y(prdata_m2_i_a3_1_0_Z));
    SLE \idq_pi_ki_o[6]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_ki_o[6]));
    SLE \rate_limit_rate_cnt_o[16]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[16]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_rate_cnt_o[16]));
    CFG3 #( .INIT(8'h80) )  \WRITE_DECODE_PROC.un3_psel_i  (.A(
        MC_System_0_AMBA_SLAVE_0_PSELx), .B(
        MC_System_0_AMBA_SLAVE_0_PWRITE), .C(
        MC_System_0_AMBA_SLAVE_0_PENABLE), .Y(un3_psel_i));
    SLE \adc_channel_ch2_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch2_o[14]));
    SLE \adc_oc_thresh_o[13]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[13]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_oc_thresh_o[13]));
    CFG4 #( .INIT(16'h5F13) )  
        \READ_DECODE_PROC.prdata_o275_0_a2_RNIHJUK  (.A(
        HALL_INTERFACE_1_angle_out_raw_o[6]), .B(
        HALL_INTERFACE_1_theta_output_o[6]), .C(prdata_o275), .D(
        prdata_o276), .Y(prdata_N_5_mux_i_3_a0_4));
    SLE \rate_limit_slew_cnt_o[8]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_slew_cnt_o[8]));
    SLE \hall_speed_factor_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(hall_speed_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_hall_if_0_hall_speed_factor_o[14]));
    CFG4 #( .INIT(16'h0010) )  READ_m2_e_1 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[9]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[3]), .C(READ_m3_e_0_Z), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[8]), .Y(READ_m2_e_1_Z));
    CFG3 #( .INIT(8'h1D) )  \prdata_o_1_iv_0_13_tz_RNO_0[12]  (.A(
        ADC_SCALING_0_ib_adc_o[12]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        FOC_TRANSFORMS_0_iq_o[12]), .Y(prdata_o_1_iv_0_13_tz_RNO_0[12])
        );
    SLE \olmng_theta_factor_o[4]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_theta_factor_o[4]));
    CFG4 #( .INIT(16'hFFEC) )  \prdata_o_1_iv_0_6[13]  (.A(
        SPEED_ID_IQ_PI_0_iq_pi_output_o_13), .B(prdata_o_1_iv_0_0[13]), 
        .C(prdata_m2_e_5_6_1), .D(prdata_o_1_iv_0_1[13]), .Y(
        prdata_o_1_iv_0_6[13]));
    CFG3 #( .INIT(8'h10) )  \prdata_o_1_iv_0_2_RNO[13]  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .B(
        prdata_o_1_iv_0_2_RNO_0[13]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .Y(prdata_m2_0_a2_25_0));
    SLE \adc_channel_ch3_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch3_o[15]));
    CFG4 #( .INIT(16'hEAAA) )  \prdata_o_1_0_iv_0_8_tz[1]  (.A(
        prdata_N_5_mux_17), .B(N_359), .C(ADC_SCALING_0_ib_adc_o[1]), 
        .D(MC_System_0_AMBA_SLAVE_0_PADDR[2]), .Y(
        prdata_o_1_0_iv_0_8_tz[1]));
    CFG2 #( .INIT(4'hE) )  \prdata_o_1_iv_0_0[13]  (.A(
        prdata_o_1_iv_0_1_a0[13]), .B(prdata_o_1_iv_0_1_a1[13]), .Y(
        prdata_o_1_iv_0_0[13]));
    SLE \speed_pi_kp_o[3]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_0_sqmuxa_Z), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_speed_pi_kp_o[3]));
    CFG4 #( .INIT(16'h0100) )  \READ_DECODE_PROC.prdata_o275_0_a2_2  (
        .A(MC_System_0_AMBA_SLAVE_0_PADDR[10]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[6]), .C(N_101), .D(
        prdata_o275_0_a2_0), .Y(prdata_o275_0_a2_2));
    SLE \idq_pi_kp_o[14]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[14]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_kp_o[14]));
    CFG4 #( .INIT(16'hFFFE) )  \prdata_o_1_iv_0_12[13]  (.A(N_326), .B(
        N_324), .C(N_330), .D(N_329), .Y(prdata_o_1_iv_0_12_0));
    SLE \speed_pi_ki_o[3]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_speed_pi_ki_o[3]));
    SLE \olmng_iq_ref_in_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_iq_ref_in_o[11]));
    CFG4 #( .INIT(16'h0080) )  
        \READ_DECODE_PROC.prdata_o276_2_0_1_RNI2FF13  (.A(
        READ_m2_e_N_2L1_Z), .B(N_355), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .D(N_101), .Y(N_358));
    CFG2 #( .INIT(4'h7) )  \READ_DECODE_PROC.prdata_o275_6_i  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[9]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .Y(N_1608));
    CFG4 #( .INIT(16'h153F) )  \prdata_o_1_0_iv_0_2_0_1[0]  (.A(
        ADC_SCALING_0_ib_adc_o[0]), .B(FOC_TRANSFORMS_0_iq_o[0]), .C(
        N_364), .D(N_359), .Y(prdata_o_1_0_iv_0_2_0_1[0]));
    CFG4 #( .INIT(16'h153F) )  
        \READ_DECODE_PROC.prdata_o274_0_a2_RNIPFTC1  (.A(
        SEQ_CONTROLLER_0_state_o_2), .B(
        HALL_INTERFACE_1_omega_out_o[3]), .C(prdata_o277), .D(
        prdata_o274), .Y(prdata_m2_e_27_6));
    SLE \idq_pi_kp_o[12]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[12]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_kp_o[12]));
    CFG2 #( .INIT(4'h8) )  \prdata_o_1_iv_7_RNO[7]  (.A(prdata_o270), 
        .B(adc_interface_0_result_ch0_o[7]), .Y(
        adc_interface_0_result_ch0_o_m[7]));
    CFG4 #( .INIT(16'h0800) )  pwm_dead_time_val_o_1_sqmuxa_0_a5 (.A(
        adc_scale_val_o_1_sqmuxa_0_a2_0_0_Z), .B(un3_psel_i), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .D(N_390), .Y(
        pwm_dead_time_val_o_1_sqmuxa));
    SLE \adc_channel_ch0_o[3]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch0_o[3]));
    CFG4 #( .INIT(16'h2000) )  
        \READ_DECODE_PROC.prdata_o264_5_i_o5_RNISQ473  (.A(
        READ_m2_e_3_1_Z), .B(N_118), .C(READ_m2_e_3_1_0_Z), .D(N_353), 
        .Y(prdata_o264));
    SLE \adc_channel_ch0_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch0_o[15]));
    CFG3 #( .INIT(8'hF8) )  \prdata_o_1_iv_3[5]  (.A(
        adc_interface_0_result_ch0_o[5]), .B(prdata_o270), .C(
        prdata_o_1_iv_0[5]), .Y(prdata_o_1_iv_3[5]));
    CFG4 #( .INIT(16'h0100) )  \READ_DECODE_PROC.prdata_o270_0_a2_0  (
        .A(MC_System_0_AMBA_SLAVE_0_PADDR[9]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[8]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[7]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .Y(prdata_o270_0_a2_0));
    CFG3 #( .INIT(8'h35) )  prdata_m2_6 (.A(ADC_SCALING_0_ia_adc_o[8]), 
        .B(RATE_LIMITER_0_rl_out_o[8]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(prdata_m2_6_Z));
    SLE \speed_pi_ki_o[6]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[6]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_speed_pi_ki_o[6]));
    SLE \pwm_period_val_o[10]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[10])
        , .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_period_val_o[10]));
    SLE \rate_limit_ref_in_o[7]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_ref_in_o[7]));
    SLE \pwm_period_val_o[6]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[6]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_period_val_o[6]));
    CFG3 #( .INIT(8'hEF) )  
        \READ_DECODE_PROC.prdata_o276_2_0_1_RNIEC1T4  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(prdata_m3_13_0_Z), .C(
        N_358), .Y(prdata_m2_e_5_9));
    SLE \idq_pi_kp_o[13]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[13]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_kp_o[13]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_0_a2_13[0]  (.A(N_353), 
        .B(prdata_o264_0_a2_1), .C(FOC_TRANSFORMS_0_vbeta_o[0]), .D(
        READ_m2_e_3_1_0_Z), .Y(N_296));
    CFG4 #( .INIT(16'h8000) )  olmng_iq_ref_in_o_1_sqmuxa_0_a5 (.A(
        N_370), .B(N_360), .C(N_376), .D(N_365), .Y(
        olmng_iq_ref_in_o_1_sqmuxa));
    SLE \hall_speed_factor_o[6]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(hall_speed_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_hall_if_0_hall_speed_factor_o[6]));
    CFG4 #( .INIT(16'h0010) )  hall_filter_factor_o_1_sqmuxa_2 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[9]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .C(
        hall_filter_factor_o_1_sqmuxa_1_Z), .D(N_118), .Y(
        hall_filter_factor_o_1_sqmuxa_2_Z));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_0_a2_9[12]  (.A(N_353), 
        .B(prdata_o264_0_a2_1), .C(FOC_TRANSFORMS_0_vbeta_o[12]), .D(
        READ_m2_e_3_1_0_Z), .Y(N_347));
    SLE \rate_limit_rate_cnt_o[17]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[17]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_rate_cnt_o[17]));
    SLE \adc_channel_ch2_o[9]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[9]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch2_o[9]));
    CFG4 #( .INIT(16'hFFF8) )  \READ_DECODE_PROC.prdata_o277_RNIFUJG2  
        (.A(prdata_o277), .B(HALL_INTERFACE_1_omega_out_o[17]), .C(
        N_145), .D(m7_i_0), .Y(m7_i_2));
    SLE \pwm_delay_time_val_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_delay_time_val_o[1]));
    SLE \idq_pi_ki_o[15]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[15]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_ki_o[15]));
    SLE \speed_pi_kp_o[15]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[15]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_0_sqmuxa_Z), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_speed_pi_kp_o[15]));
    CFG3 #( .INIT(8'h10) )  prdata_m2_0_a2_35_0 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .B(prdata_m2_19_Z), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .Y(prdata_m2_0_a2_35_0_Z));
    CFG3 #( .INIT(8'h40) )  olmng_dv_o_1_sqmuxa_9_0_a5 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .C(olmng_dv_o_1_sqmuxa_5), 
        .Y(olmng_dv_o_1_sqmuxa_9));
    SLE \idq_pi_kp_o[9]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_kp_o[9]));
    SLE \idq_pi_kp_o[8]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_kp_o[8]));
    SLE \pwm_dead_time_val_o[9]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_dead_time_val_o[9]));
    CFG4 #( .INIT(16'h5F13) )  
        \READ_DECODE_PROC.prdata_o275_0_a2_RNINPUK  (.A(
        HALL_INTERFACE_1_angle_out_raw_o[9]), .B(
        HALL_INTERFACE_1_theta_output_o[9]), .C(prdata_o275), .D(
        prdata_o276), .Y(prdata_N_5_mux_i_1_a0_4));
    SLE \olmng_iq_ref_in_o[0]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_iq_ref_in_o[0]));
    SLE \rate_limit_slew_cnt_o[5]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_slew_cnt_o[5]));
    SLE \hall_speed_factor_o[9]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(hall_speed_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_hall_if_0_hall_speed_factor_o[9]));
    CFG4 #( .INIT(16'h8000) )  auto_restart_no_o_1_sqmuxa_0_a5 (.A(
        N_370), .B(N_363), .C(N_365), .D(N_376), .Y(
        auto_restart_no_o_1_sqmuxa));
    CFG4 #( .INIT(16'hAC00) )  prdata_m2_0_a2_17_0_c (.A(
        SPEED_ID_IQ_PI_0_speed_pi_output_o[9]), .B(
        ADC_SCALING_0_ib_adc_o[9]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .D(m5_m2_0_a2_0_Z), .Y(
        prdata_m2_0_a2_17_0));
    CFG4 #( .INIT(16'h8000) )  speed_pi_ki_o_1_sqmuxa_0_a5 (.A(N_364), 
        .B(N_370), .C(N_398), .D(N_369), .Y(speed_pi_ki_o_1_sqmuxa));
    CFG2 #( .INIT(4'h8) )  olmng_dv_o_1_sqmuxa_0 (.A(
        olmng_dv_o_1_sqmuxa_3), .B(MC_System_0_AMBA_SLAVE_0_PADDR[7]), 
        .Y(olmng_dv_o_1_sqmuxa_0_Z));
    CFG4 #( .INIT(16'h0080) )  \prdata_o_1_iv_0_6_a0[14]  (.A(N_355), 
        .B(READ_m2_e_2_1), .C(prdata_o_1_iv_0_6_a0_0[14]), .D(N_101), 
        .Y(prdata_o_1_iv_0_6_a0[14]));
    SLE direction_config_o (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(direction_config_o_1_sqmuxa_Z)
        , .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_0_direction_config_o));
    CFG4 #( .INIT(16'h0040) )  \prdata_o_1_0_iv_0_a5_0_0[2]  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[7]), .B(
        SPEED_ID_IQ_PI_0_id_pi_output_o[2]), .C(olmng_dv_o_1_sqmuxa_4), 
        .D(MC_System_0_AMBA_SLAVE_0_PADDR[9]), .Y(
        prdata_o_1_0_iv_0_a5_0_0[2]));
    SLE \idq_pi_kp_o[11]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[11]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_kp_o[11]));
    CFG4 #( .INIT(16'h8000) )  hall_filter_factor_o_1_sqmuxa (.A(N_391)
        , .B(N_352), .C(hall_filter_factor_o_1_sqmuxa_2_Z), .D(
        un3_psel_i), .Y(hall_filter_factor_o_1_sqmuxa_Z));
    CFG4 #( .INIT(16'h1333) )  
        \READ_DECODE_PROC.prdata_o267_1_RNIOHUO5  (.A(prdata_o267_1), 
        .B(hall_speed_factor_o_1_sqmuxa_0_a2_RNI3AHL5_Z), .C(
        SPEED_ID_IQ_PI_0_id_pi_output_o[11]), .D(
        pwm_period_val_o_1_sqmuxa_8), .Y(prdata_N_5_mux_i_2_a0_0));
    CFG4 #( .INIT(16'hA0EC) )  \prdata_o_1_iv_1[7]  (.A(prdata_o275), 
        .B(N_358), .C(HALL_INTERFACE_1_angle_out_raw_o[7]), .D(
        prdata_m3_i_0_0), .Y(prdata_o_1_iv_1[7]));
    CFG4 #( .INIT(16'hFFFE) )  \prdata_o_1_iv_0_11[12]  (.A(N_339), .B(
        N_337), .C(N_343), .D(N_342), .Y(prdata_o_1_iv_0_11_0));
    CFG4 #( .INIT(16'hC0EA) )  \prdata_o_1_iv_0[5]  (.A(
        HALL_INTERFACE_1_theta_output_o[5]), .B(prdata_o264_0_a2_1), 
        .C(FOC_m3_e_2), .D(prdata_o276), .Y(prdata_o_1_iv_0[5]));
    SLE \hall_speed_factor_o[5]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(hall_speed_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_hall_if_0_hall_speed_factor_o[5]));
    SLE \adc_channel_ch3_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch3_o[13]));
    CFG4 #( .INIT(16'h153F) )  \prdata_o_1_0_iv_0_12_1[1]  (.A(
        SPEED_ID_IQ_PI_0_iq_pi_output_o_1), .B(
        SEQ_CONTROLLER_0_state_o_0), .C(prdata_o274), .D(
        prdata_m2_e_5_6_1), .Y(prdata_o_1_0_iv_0_12_1[1]));
    SLE \pwm_delay_time_val_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_delay_time_val_o[13]));
    CFG3 #( .INIT(8'h80) )  \READ_DECODE_PROC.prdata_o267  (.A(
        prdata_o267_1_0), .B(prdata_o277_1_0), .C(
        pwm_period_val_o_1_sqmuxa_8), .Y(prdata_o267));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_iv_10_2[10]  (.A(
        adc_interface_0_result_ch0_o[10]), .B(
        HALL_INTERFACE_1_angle_out_raw_o[10]), .C(prdata_o270), .D(
        prdata_o275), .Y(prdata_o_1_iv_10_2[10]));
    CFG4 #( .INIT(16'h2000) )  prdata_m1_0_a2_11_1 (.A(
        SPEED_ID_IQ_PI_0_speed_pi_output_o[2]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(prdata_m1_0_a2_11_1_Z));
    SLE \olmng_dv_o[6]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_dv_o[6]));
    CFG2 #( .INIT(4'h2) )  hall_filter_factor_o_1_sqmuxa_1 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[10]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[6]), .Y(
        hall_filter_factor_o_1_sqmuxa_1_Z));
    CFG3 #( .INIT(8'h53) )  prdata_m2_0 (.A(OLMNG_0_theta_o[4]), .B(
        RATE_LIMITER_0_rl_out_o[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .Y(prdata_m2_0_Z));
    SLE \speed_pi_ki_o[15]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[15]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_speed_pi_ki_o[15]));
    CFG4 #( .INIT(16'h153F) )  \prdata_o_1_0_iv_0_a5_0_0_RNINJOU4[2]  
        (.A(prdata_o_1_0_iv_0_a5_0_0[2]), .B(prdata_m1_0_a2_11_1_Z), 
        .C(N_358), .D(prdata_o267_1), .Y(prdata_m2_e_5_0));
    CFG4 #( .INIT(16'h135F) )  
        \READ_DECODE_PROC.prdata_o270_0_a2_RNI3E726  (.A(
        prdata_m2_0_a2_35_0_Z), .B(adc_interface_0_result_ch0_o[2]), 
        .C(N_358), .D(prdata_o270), .Y(prdata_m2_e_5_1));
    CFG3 #( .INIT(8'h80) )  \prdata_o_1_iv_12_RNO[7]  (.A(N_381), .B(
        FOC_TRANSFORMS_0_ibeta_o[7]), .C(prdata_o260_0_a2_1), .Y(
        FOC_TRANSFORMS_0_ibeta_o_m[7]));
    CFG3 #( .INIT(8'h40) )  READ_m2_e_3_1 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .Y(READ_m2_e_3_1_Z));
    CFG4 #( .INIT(16'h0020) )  \prdata_o_1_0_iv_1_a1_3_0[3]  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(
        prdata_o_1_0_iv_1_a1_3_0[3]));
    SLE \adc_control_reg_val_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_control_reg_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_control_reg_val_o[3]));
    CFG3 #( .INIT(8'hC8) )  \prdata_o_1_0_iv_0_0[1]  (.A(
        prdata_o_1_0_iv_0_9_tz[1]), .B(N_358), .C(prdata_m2_0_a2_13_0), 
        .Y(prdata_o_1_0_iv_0_0[1]));
    SLE \prdata_o_1[18]  (.D(prdata_o_1_RNO[18]), .CLK(prdata_o276), 
        .EN(VCC), .ALn(VCC), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(VCC), 
        .Q(MC_System_0_AMBA_SLAVE_0_PRDATA[19]));
    SLE \adc_channel_ch1_o[7]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[7]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch1_o[7]));
    CFG4 #( .INIT(16'h4440) )  
        \READ_DECODE_PROC.prdata_o276_2_0_1_RNIAR7N4  (.A(N_101), .B(
        N_355), .C(prdata_m2_0_a2_7_0_0), .D(prdata_m2_0_a2_31_0_Z), 
        .Y(prdata_N_5_mux_i_3_a0_3_1));
    CFG4 #( .INIT(16'h8000) )  
        \READ_DECODE_PROC.prdata_o267_1_0_RNIQJET  (.A(
        SPEED_ID_IQ_PI_0_id_pi_output_o[8]), .B(prdata_o267_1_0), .C(
        prdata_o277_1_0), .D(pwm_period_val_o_1_sqmuxa_8), .Y(
        SPEED_ID_IQ_PI_0_id_pi_output_o_m[8]));
    SLE \adc_channel_ch0_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch0_o[13]));
    CFG4 #( .INIT(16'h8000) )  rate_limit_slew_cnt_o_1_sqmuxa_0_a5 (.A(
        N_363), .B(N_370), .C(N_369), .D(N_398), .Y(
        rate_limit_slew_cnt_o_1_sqmuxa));
    SLE \pwm_gain_val_o[8]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[8]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_gain_val_o[8]));
    SLE \rate_limit_rate_cnt_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_rate_cnt_o[11]));
    SLE \pwm_gain_val_o[17]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[17]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_gain_val_o[17]));
    SLE \pwm_delay_time_val_o[7]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_delay_time_val_o[7]));
    CFG4 #( .INIT(16'h7000) )  \READ_DECODE_PROC.prdata_o277_RNIL57V9  
        (.A(HALL_INTERFACE_1_omega_out_o[11]), .B(prdata_o277), .C(
        prdata_N_5_mux_i_2_a0_2), .D(prdata_N_5_mux_i_2_a0_7), .Y(
        prdata_N_5_mux_i_2_a0_10));
    SLE \seq_cntl_cl_omega_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_seq_cntl_cl_omega_o[0]));
    SLE \adc_scale_val_o[5]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_scale_val_o[5]));
    CFG4 #( .INIT(16'h8000) )  
        \READ_DECODE_PROC.prdata_o275_0_a2_RNIM9O9H  (.A(
        prdata_N_5_mux_i_1_a0_2), .B(prdata_N_5_mux_i_1_a0_4), .C(
        prdata_N_5_mux_i_1_a0_7), .D(prdata_N_5_mux_i_1_a0_13_1), .Y(
        prdata_N_5_mux_i_1_a0_13));
    CFG4 #( .INIT(16'h0222) )  
        \READ_DECODE_PROC.prdata_o270_0_a2_RNIG1FJB  (.A(
        prdata_m2_e_0_0), .B(N_243), .C(
        adc_interface_0_result_ch0_o[4]), .D(prdata_o270), .Y(
        prdata_m2_e_0_4));
    SLE \rate_limit_rate_cnt_o[8]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_rate_cnt_o[8]));
    SLE \adc_channel_ch2_o[5]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch2_o[5]));
    SLE \rate_limit_slew_cnt_o[17]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[17]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_slew_cnt_o[17]));
    SLE \olmng_theta_factor_o[16]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[16]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_theta_factor_o[16]));
    CFG4 #( .INIT(16'h8000) )  
        \READ_DECODE_PROC.prdata_o259_2_RNIQKBJ  (.A(prdata_o259_1), 
        .B(FOC_TRANSFORMS_0_ialpha_o[17]), .C(prdata_o259_2), .D(
        prdata_o277_1_0), .Y(N_425));
    SLE \speed_pi_kp_o[17]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[17]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_0_sqmuxa_Z), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_speed_pi_kp_o[17]));
    CFG3 #( .INIT(8'h80) )  \prdata_o_1_iv_0_a2_8[15]  (.A(N_381), .B(
        FOC_TRANSFORMS_0_ibeta_o[15]), .C(prdata_o260_0_a2_1), .Y(
        N_307));
    SLE \pwm_period_val_o[15]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[15])
        , .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_period_val_o[15]));
    SLE \pwm_delay_time_val_o[8]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_delay_time_val_o[8]));
    CFG4 #( .INIT(16'h0800) )  pwm_gain_val_o_1_sqmuxa_0_a2 (.A(
        MC_System_0_AMBA_SLAVE_0_PENABLE), .B(
        MC_System_0_AMBA_SLAVE_0_PSELx), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .D(
        MC_System_0_AMBA_SLAVE_0_PWRITE), .Y(N_365));
    CFG4 #( .INIT(16'h0800) )  OLMNG_m2_0_a2_1 (.A(OLMNG_0_theta_o[11])
        , .B(MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(OLMNG_N_5_mux_0));
    SLE \adc_oc_thresh_o[2]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_oc_thresh_o[2]));
    CFG4 #( .INIT(16'h2000) )  \prdata_o_1_0_iv_0_a2_3_0[1]  (.A(
        adc_interface_0_result_ch3_o[1]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[3]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .Y(
        prdata_o_1_0_iv_0_a2_3_0[1]));
    SLE \adc_channel_ch3_o[7]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[7]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch3_o[7]));
    CFG3 #( .INIT(8'h40) )  \READ_DECODE_PROC.prdata_o274_0_a2  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .B(N_406), .C(N_376), .Y(
        prdata_o274));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_17_a2[5]  (.A(
        SPEED_ID_IQ_PI_0_id_pi_output_o[5]), .B(prdata_o267_1_0), .C(
        prdata_o277_1_0), .D(pwm_period_val_o_1_sqmuxa_8), .Y(
        prdata_o_1_iv_17_a2[5]));
    SLE \adc_channel_ch3_o[5]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch3_o[5]));
    SLE \pwm_delay_time_val_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_delay_time_val_o[11]));
    SLE \hall_speed_factor_o[4]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(hall_speed_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_hall_if_0_hall_speed_factor_o[4]));
    CFG4 #( .INIT(16'h7000) )  
        \READ_DECODE_PROC.prdata_o271_0_a2_RNIPHJCA  (.A(
        adc_interface_0_result_ch1_o_5), .B(prdata_N_5_mux_i_3_a0_7_1), 
        .C(prdata_N_5_mux_i_3_a0_2), .D(prdata_o277_RNI7HP94), .Y(
        prdata_N_5_mux_i_3_a0_10));
    SLE \seq_cntl_cl_omega_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_seq_cntl_cl_omega_o[10]));
    SLE \pwm_delay_time_val_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_delay_time_val_o[10]));
    CFG4 #( .INIT(16'h2000) )  
        \READ_DECODE_PROC.prdata_o264_0_a2_1_RNI9QM0H  (.A(
        prdata_m2_e_27_2), .B(FOC_TRANSFORMS_0_vbeta_o_m[3]), .C(
        prdata_m2_e_27_7), .D(prdata_m2_e_27_10_1), .Y(
        prdata_m2_e_27_10));
    SLE \pwm_delay_time_val_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_delay_time_val_o[15]));
    SLE \speed_pi_ki_o[7]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[7]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_speed_pi_ki_o[7]));
    CFG4 #( .INIT(16'hFF80) )  \prdata_o_1_iv_0_13_0_tz[12]  (.A(
        SPEED_ID_IQ_PI_0_speed_pi_output_o[12]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .C(N_360), .D(
        prdata_m2_0_a2_0_16), .Y(prdata_o_1_iv_0_13_0_tz[12]));
    CFG4 #( .INIT(16'h030D) )  
        hall_speed_factor_o_1_sqmuxa_0_a2_RNI24JN5 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .C(m5_N_6_mux_i_0), .D(
        m5_i_o2_3_1_0_1_Z), .Y(m5_i_o2_3_1_0));
    SLE \pwm_gain_val_o[2]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_gain_val_o[2]));
    SLE \adc_oc_thresh_o[12]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[12]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_oc_thresh_o[12]));
    SLE \rate_limit_ref_in_o[9]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_ref_in_o[9]));
    CFG3 #( .INIT(8'h02) )  olmng_dv_o_1_sqmuxa_7_0_a5 (.A(un3_psel_i), 
        .B(MC_System_0_AMBA_SLAVE_0_PADDR[2]), .C(N_101), .Y(
        olmng_dv_o_1_sqmuxa_7));
    SLE \olmng_iq_ref_in_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_iq_ref_in_o[10]));
    SLE \speed_pi_kp_o[10]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[10]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_0_sqmuxa_Z), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_speed_pi_kp_o[10]));
    SLE \rate_limit_rate_cnt_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_rate_cnt_o[3]));
    VCC VCC_Z (.Y(VCC));
    CFG4 #( .INIT(16'hFFEC) )  \prdata_o_1_iv_10_12_cZ[10]  (.A(
        prdata_o272), .B(prdata_o_1_iv_10_4[10]), .C(
        adc_interface_0_result_ch2_o[10]), .D(prdata_o_1_iv_10_5[10]), 
        .Y(prdata_o_1_iv_10_12[10]));
    SLE \olmng_iq_ref_in_o[6]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[6]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_iq_ref_in_o[6]));
    CFG3 #( .INIT(8'h1D) )  \prdata_o_1_iv_0_2_RNO_0[13]  (.A(
        ADC_SCALING_0_ib_adc_o[13]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        FOC_TRANSFORMS_0_iq_o[13]), .Y(prdata_o_1_iv_0_2_RNO_0[13]));
    CFG4 #( .INIT(16'h0001) )  \prdata_o_1_0_iv_1_a0_1[3]  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[9]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[7]), .Y(
        prdata_o_1_0_iv_1_a0_1[3]));
    CFG4 #( .INIT(16'h135F) )  \prdata_o_1_iv_10_11_1[10]  (.A(
        FOC_TRANSFORMS_0_ialpha_o[10]), .B(
        SPEED_ID_IQ_PI_0_iq_pi_output_o_10), .C(prdata_o259), .D(
        prdata_m2_e_5_6_1), .Y(prdata_o_1_iv_10_11_1[10]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0_iv_0_6[1]  (.A(
        FOC_TRANSFORMS_0_vbeta_o[1]), .B(
        adc_interface_0_result_ch1_o_0), .C(prdata_N_5_mux_i_3_a0_7_1), 
        .D(prdata_o264), .Y(prdata_o_1_0_iv_0_6[1]));
    SLE \idq_pi_ki_o[14]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[14]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_ki_o[14]));
    CFG4 #( .INIT(16'hFFFE) )  \prdata_o_1_iv_10[5]  (.A(
        prdata_o_1_iv_2[5]), .B(prdata_o_1_iv_3[5]), .C(
        HALL_INTERFACE_1_omega_out_o_m[5]), .D(prdata_o_1_iv_17_a2[5]), 
        .Y(prdata_o_1_iv_10_0_0));
    SLE \speed_pi_ki_o[17]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[17]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_speed_pi_ki_o[17]));
    SLE \pwm_gain_val_o[15]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[15]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_gain_val_o[15]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_iv_8[5]  (.A(
        SPEED_ID_IQ_PI_0_iq_pi_output_o_5), .B(
        adc_interface_0_result_ch1_o_4), .C(prdata_m2_e_5_6_1), .D(
        prdata_N_5_mux_i_3_a0_7_1), .Y(prdata_o_1_iv_8[5]));
    CFG4 #( .INIT(16'hE0F0) )  \READ_DECODE_PROC.prdata_o263_RNIEGRT6  
        (.A(prdata_m2_e_0_1_1_Z), .B(MC_System_0_AMBA_SLAVE_0_PADDR[5])
        , .C(prdata_m2_e_0_3_1), .D(N_358), .Y(prdata_m2_e_0_3));
    SLE \seq_cntl_cl_omega_o[7]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_seq_cntl_cl_omega_o[7]));
    CFG4 #( .INIT(16'hEFFF) )  \prdata_o_1_iv_0_12[15]  (.A(N_303), .B(
        N_307), .C(prdata_o_1_iv_0_12_1[15]), .D(
        prdata_o_1_iv_0_6_0_Z[15]), .Y(prdata_o_1_iv_0_12_2));
    CFG4 #( .INIT(16'hAE0C) )  
        \READ_DECODE_PROC.prdata_o275_0_a2_RNIL7RK  (.A(
        HALL_INTERFACE_1_angle_out_raw_o[17]), .B(
        HALL_INTERFACE_1_theta_output_o[17]), .C(prdata_o276), .D(
        prdata_o275), .Y(m7_i_0));
    SLE \idq_pi_ki_o[12]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[12]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_ki_o[12]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_0_iv_0_3[1]  (.A(
        prdata_o259), .B(N_375), .C(FOC_TRANSFORMS_0_ialpha_o[1]), .D(
        prdata_o_1_0_iv_0_a2_3_0[1]), .Y(prdata_o_1_0_iv_0_3[1]));
    SLE \pwm_dead_time_val_o[5]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_dead_time_val_o[5]));
    CFG2 #( .INIT(4'h4) )  \prdata_o_1_iv_0_a2_10[12]  (.A(prdata_o276)
        , .B(HALL_INTERFACE_1_theta_output_o[12]), .Y(N_348));
    CFG4 #( .INIT(16'h2000) )  fault_clr_o_1_sqmuxa_0_a5 (.A(N_390), 
        .B(MC_System_0_AMBA_SLAVE_0_PADDR[11]), .C(un3_psel_i), .D(
        N_376), .Y(fault_clr_o_1_sqmuxa));
    CFG3 #( .INIT(8'h10) )  \prdata_o_1_iv_1_RNO[16]  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .B(
        prdata_o_1_iv_1_RNO_0[16]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .Y(prdata_m2_0_a2_27_0));
    SLE \rate_limit_rate_cnt_o[7]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_rate_cnt_o[7]));
    CFG4 #( .INIT(16'h8000) )  \READ_DECODE_PROC.prdata_o259  (.A(
        olmng_dv_o_1_sqmuxa_4), .B(prdata_o277_1_0), .C(prdata_o259_1), 
        .D(olmng_dv_o_1_sqmuxa_5), .Y(prdata_o259));
    CFG3 #( .INIT(8'h35) )  prdata_m2_2 (.A(ADC_SCALING_0_ia_adc_o[9]), 
        .B(RATE_LIMITER_0_rl_out_o[9]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(prdata_m2_2_Z));
    SLE \olmng_dv_o[2]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_dv_o[2]));
    SLE \idq_pi_ki_o[13]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[13]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_ki_o[13]));
    SLE \rate_limit_rate_cnt_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_rate_cnt_o[0]));
    SLE \olmng_dv_o[16]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[16]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_dv_o[16]));
    SLE \rate_limit_ref_in_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_ref_in_o[15]));
    SLE \rate_limit_ref_in_o[5]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_ref_in_o[5]));
    CFG3 #( .INIT(8'h80) )  \prdata_o_1_0_iv_0_a2_0[0]  (.A(N_375), .B(
        adc_interface_0_result_ch2_o[0]), .C(N_371), .Y(N_283));
    SLE \pwm_delay_time_val_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_delay_time_val_o[12]));
    CFG3 #( .INIT(8'h40) )  speed_pi_kp_o_0_sqmuxa_9_0_a5 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .B(olmng_dv_o_1_sqmuxa_5), 
        .C(MC_System_0_AMBA_SLAVE_0_PADDR[4]), .Y(
        speed_pi_kp_o_0_sqmuxa_9));
    SLE \seq_cntl_cl_omega_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_seq_cntl_cl_omega_o[12]));
    CFG4 #( .INIT(16'h8000) )  adc_control_reg_val_o_1_sqmuxa_0_a5 (.A(
        N_367), .B(N_359), .C(adc_scale_val_o_1_sqmuxa_0_a2_0_0_Z), .D(
        N_365), .Y(adc_control_reg_val_o_1_sqmuxa));
    SLE \rate_limit_rate_cnt_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_rate_cnt_o[13]));
    SLE \rate_limit_ref_in_o[4]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_ref_in_o[4]));
    SLE \speed_pi_ki_o[10]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[10]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_speed_pi_ki_o[10]));
    SLE \idq_pi_ki_o[9]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_ki_o[9]));
    CFG4 #( .INIT(16'h1000) )  hall_speed_factor_o_1_sqmuxa_0_a2_0 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[7]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .C(N_353), .D(un3_psel_i), 
        .Y(N_398));
    CFG4 #( .INIT(16'hAC00) )  prdata_m2_0_a2_29_0 (.A(
        SPEED_ID_IQ_PI_0_speed_pi_output_o[11]), .B(
        ADC_SCALING_0_ib_adc_o[11]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .D(m5_m2_0_a2_0_Z), .Y(
        prdata_m2_0_a2_29_0_Z));
    SLE \adc_scale_val_o[4]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_scale_val_o[4]));
    SLE \adc_channel_ch0_o[2]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch0_o[2]));
    SLE \pwm_period_val_o[7]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[7]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_period_val_o[7]));
    CFG3 #( .INIT(8'h80) )  \prdata_o_1_iv_12_RNO_0[7]  (.A(N_375), .B(
        adc_interface_0_result_ch2_o[7]), .C(N_371), .Y(
        adc_interface_0_result_ch2_o_m[7]));
    SLE \olmng_theta_factor_o[6]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_theta_factor_o[6]));
    SLE \hall_speed_factor_o[7]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(hall_speed_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_hall_if_0_hall_speed_factor_o[7]));
    CFG3 #( .INIT(8'h1D) )  prdata_m2_19 (.A(ADC_SCALING_0_ib_adc_o[2])
        , .B(MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        FOC_TRANSFORMS_0_iq_o[2]), .Y(prdata_m2_19_Z));
    SLE \adc_channel_ch2_o[0]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch2_o[0]));
    SLE \rate_limit_ref_in_o[8]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_ref_in_o[8]));
    SLE \rate_limit_ref_in_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_ref_in_o[13]));
    SLE \idq_pi_ki_o[5]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_ki_o[5]));
    SLE \seq_cntl_cl_omega_o[5]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_seq_cntl_cl_omega_o[5]));
    CFG4 #( .INIT(16'h0008) )  \READ_DECODE_PROC.prdata_o264_0_a2_1  (
        .A(MC_System_0_AMBA_SLAVE_0_PADDR[11]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(N_118), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(prdata_o264_0_a2_1));
    SLE \pwm_dead_time_val_o[8]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_dead_time_val_o[8]));
    SLE \rate_limit_ref_in_o[16]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[16]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_ref_in_o[16]));
    SLE \adc_channel_ch3_o[4]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch3_o[4]));
    CFG4 #( .INIT(16'hFFEC) )  \prdata_o_1_iv_0_11[15]  (.A(
        FOC_TRANSFORMS_0_id_o[15]), .B(prdata_o_1_iv_0_4[15]), .C(
        prdata_o261), .D(prdata_o_1_iv_0_5[15]), .Y(
        prdata_o_1_iv_0_11_3));
    SLE \olmng_dv_o[5]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_dv_o[5]));
    CFG4 #( .INIT(16'hC0A0) )  \prdata_o_1_iv_0_RNO[7]  (.A(
        RATE_LIMITER_0_rl_out_o[7]), .B(OLMNG_0_theta_o[7]), .C(
        prdata_m4_0), .D(MC_System_0_AMBA_SLAVE_0_PADDR[4]), .Y(
        prdata_m2_0_a2_23_0));
    SLE \adc_oc_thresh_o[7]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[7]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_oc_thresh_o[7]));
    SLE \olmng_iq_ref_in_o[3]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_iq_ref_in_o[3]));
    SLE \rate_limit_slew_cnt_o[7]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_slew_cnt_o[7]));
    CFG4 #( .INIT(16'h3F15) )  
        \READ_DECODE_PROC.prdata_o267_1_RNIT66V  (.A(prdata_o267_1), 
        .B(prdata_o263), .C(FOC_TRANSFORMS_0_valpha_o_9), .D(
        pwm_period_val_o_1_sqmuxa_8_0_a5_RNISD05_Z), .Y(
        prdata_o267_1_RNIT66V));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_0_a2_0[12]  (.A(
        HALL_INTERFACE_1_angle_out_raw_o[12]), .B(N_391), .C(N_371), 
        .D(prdata_o275_0_a2_2), .Y(N_338));
    SLE \adc_channel_ch2_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch2_o[12]));
    SLE \auto_restart_no_o[2]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(auto_restart_no_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_auto_restart_no_o[2]));
    CFG4 #( .INIT(16'h2000) )  \prdata_o_1_iv_9_tz_RNO[10]  (.A(
        SPEED_ID_IQ_PI_0_speed_pi_output_o[10]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(SPEED_N_5_mux_2));
    SLE fault_clr_o (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(fault_clr_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_fault_clr_o));
    CFG4 #( .INIT(16'h0007) )  \prdata_o_1_0_iv_1_a0_RNIR9T11[3]  (.A(
        prdata_o270), .B(adc_interface_0_result_ch0_o[3]), .C(
        prdata_o_1_0_iv_1_a0[3]), .D(prdata_o_1_0_iv_1_a1[3]), .Y(
        prdata_m2_e_27_3));
    SLE \idq_pi_ki_o[11]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[11]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_ki_o[11]));
    SLE \pwm_dead_time_val_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_dead_time_val_o[2]));
    CFG3 #( .INIT(8'h1D) )  prdata_m2_1 (.A(ADC_SCALING_0_ia_adc_o[4]), 
        .B(MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        FOC_TRANSFORMS_0_id_o[4]), .Y(prdata_m2_1_Z));
    CFG3 #( .INIT(8'h07) )  \READ_DECODE_PROC.prdata_o263_RNIELHL1  (
        .A(prdata_o263), .B(FOC_TRANSFORMS_0_valpha_o_4), .C(
        prdata_o276_2_0_RNI202U), .Y(prdata_m2_e_0_3_1));
    CFG4 #( .INIT(16'h0400) )  \READ_DECODE_PROC.prdata_o259_1  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[7]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[3]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .Y(prdata_o259_1));
    SLE \adc_channel_ch2_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch2_o[11]));
    SLE \adc_channel_ch2_o[7]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[7]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch2_o[7]));
    SLE \rate_limit_slew_cnt_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_slew_cnt_o[3]));
    SLE \adc_channel_ch1_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch1_o[14]));
    SLE \rate_limit_slew_cnt_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_slew_cnt_o[0]));
    SLE \adc_channel_ch3_o[8]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[8]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch3_o[8]));
    SLE \rate_limit_slew_cnt_o[16]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[16]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_slew_cnt_o[16]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0_iv_0_15_3[0]  (.A(
        OLMNG_0_theta_o[0]), .B(RATE_LIMITER_0_rl_out_o[0]), .C(
        prdata_o265), .D(prdata_o_1_0_iv_0_15_3_1[0]), .Y(
        prdata_o_1_0_iv_0_15_3[0]));
    SLE \pwm_dead_time_val_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_dead_time_val_o[1]));
    SLE \seq_cntl_cl_omega_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_seq_cntl_cl_omega_o[11]));
    CFG4 #( .INIT(16'h8000) )  direction_config_o_1_sqmuxa (.A(
        olmng_dv_o_1_sqmuxa_4), .B(direction_config_o_1_sqmuxa_1_Z), 
        .C(olmng_dv_o_1_sqmuxa_7), .D(speed_pi_kp_o_0_sqmuxa_9), .Y(
        direction_config_o_1_sqmuxa_Z));
    SLE \hall_speed_factor_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(hall_speed_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_hall_if_0_hall_speed_factor_o[3]));
    CFG4 #( .INIT(16'h2000) )  \READ_DECODE_PROC.prdata_o267_1_0  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[10]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[3]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .Y(prdata_o267_1_0));
    CFG4 #( .INIT(16'h0001) )  \READ_DECODE_PROC.prdata_o274_0_a2_2  (
        .A(MC_System_0_AMBA_SLAVE_0_PADDR[1]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[0]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[9]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[8]), .Y(N_353));
    SLE \adc_channel_ch3_o[3]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch3_o[3]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_0_1_a1[13]  (.A(
        prdata_o277_1_0), .B(HALL_INTERFACE_1_omega_out_o[13]), .C(
        prdata_o277_2_0), .D(prdata_o277_2_1), .Y(
        prdata_o_1_iv_0_1_a1[13]));
    SLE \adc_scale_val_o[1]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_scale_val_o[1]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_iv_5[5]  (.A(
        FOC_TRANSFORMS_0_ibeta_o_m_0[5]), .B(
        FOC_TRANSFORMS_0_valpha_o_5), .C(N_381), .D(prdata_o263), .Y(
        prdata_o_1_iv_5[5]));
    CFG4 #( .INIT(16'h135F) )  
        \READ_DECODE_PROC.prdata_o271_0_a2_RNI9NP51  (.A(
        SPEED_ID_IQ_PI_0_iq_pi_output_o_3), .B(
        adc_interface_0_result_ch1_o_2), .C(prdata_m2_e_5_6_1), .D(
        prdata_N_5_mux_i_3_a0_7_1), .Y(prdata_m2_e_27_7));
    CFG4 #( .INIT(16'hFF80) )  \prdata_o_1_0_iv_0_9_tz[1]  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(
        SPEED_ID_IQ_PI_0_speed_pi_output_o[1]), .C(N_360), .D(
        prdata_N_5_mux_13), .Y(prdata_o_1_0_iv_0_9_tz[1]));
    CFG4 #( .INIT(16'h8000) )  hall_speed_factor_o_1_sqmuxa_0_a5 (.A(
        N_367), .B(hall_filter_factor_o_1_sqmuxa_1_Z), .C(N_364), .D(
        N_398), .Y(hall_speed_factor_o_1_sqmuxa));
    CFG4 #( .INIT(16'h153F) )  
        \READ_DECODE_PROC.prdata_o271_0_a2_RNINHH24  (.A(
        FOC_TRANSFORMS_0_vbeta_o[9]), .B(
        adc_interface_0_result_ch1_o_8), .C(prdata_N_5_mux_i_3_a0_7_1), 
        .D(prdata_o264), .Y(prdata_N_5_mux_i_1_a0_7));
    CFG4 #( .INIT(16'h8000) )  
        \READ_DECODE_PROC.prdata_o264_0_a2_1_RNI0QG62  (.A(N_353), .B(
        prdata_o264_0_a2_1), .C(FOC_TRANSFORMS_0_vbeta_o[17]), .D(
        READ_m2_e_3_1_0_Z), .Y(N_403));
    SLE \pwm_gain_val_o[14]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[14]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_gain_val_o[14]));
    CFG2 #( .INIT(4'h1) )  \READ_DECODE_PROC.prdata_o258_5_0_a2  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[10]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[9]), .Y(olmng_dv_o_1_sqmuxa_5));
    CFG4 #( .INIT(16'h4000) )  pwm_gain_val_o_1_sqmuxa_0_a2_0 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[7]), .B(N_359), .C(N_369), .D(
        N_353), .Y(N_375));
    CFG4 #( .INIT(16'h135F) )  \READ_DECODE_PROC.prdata_o259_RNI8TRP7  
        (.A(FOC_TRANSFORMS_0_ialpha_o[6]), .B(READ_m2_e_1_Z), .C(
        prdata_o259), .D(prdata_N_5_mux_i_3_a0_3_1), .Y(
        prdata_N_5_mux_i_3_a0_3));
    SLE \pwm_delay_time_val_o[4]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_delay_time_val_o[4]));
    SLE \adc_control_reg_val_o[4]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_control_reg_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_control_reg_val_o[4]));
    SLE \speed_pi_kp_o[6]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[6]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_0_sqmuxa_Z), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_speed_pi_kp_o[6]));
    CFG3 #( .INIT(8'h13) )  \prdata_o_1_iv_0_5_1[15]  (.A(
        HALL_INTERFACE_1_angle_out_raw_o[15]), .B(N_220), .C(
        prdata_o275), .Y(prdata_o_1_iv_0_5_1[15]));
    CFG3 #( .INIT(8'h10) )  direction_config_o_1_sqmuxa_1 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[3]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[7]), .Y(
        direction_config_o_1_sqmuxa_1_Z));
    CFG4 #( .INIT(16'h2000) )  \prdata_o_1_iv_0_5_RNO[14]  (.A(
        SPEED_ID_IQ_PI_0_speed_pi_output_o[14]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(prdata_m1_0_a2_4_1));
    CFG2 #( .INIT(4'h4) )  pwm_gain_val_o_1_sqmuxa_0_a2_2 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[10]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[6]), .Y(N_369));
    SLE \pwm_gain_val_o[11]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[11]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_gain_val_o[11]));
    CFG3 #( .INIT(8'hF8) )  \prdata_o_1_0_iv_0_5[1]  (.A(
        HALL_INTERFACE_1_omega_out_o[1]), .B(prdata_o277), .C(
        prdata_o_1_0_iv_0_1[1]), .Y(prdata_o_1_0_iv_0_5[1]));
    SLE \rate_limit_ref_in_o[17]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[17]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_ref_in_o[17]));
    SLE \adc_scale_val_o[13]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[13]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_scale_val_o[13]));
    SLE \rate_limit_slew_cnt_o[6]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_slew_cnt_o[6]));
    CFG4 #( .INIT(16'h8000) )  
        \READ_DECODE_PROC.prdata_o259_2_RNI6SNT  (.A(prdata_o259_1), 
        .B(FOC_TRANSFORMS_0_ialpha_o[4]), .C(prdata_o259_2), .D(
        prdata_o277_1_0), .Y(prdata_o259_2_RNI6SNT));
    SLE \rate_limit_slew_cnt_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_slew_cnt_o[15]));
    CFG4 #( .INIT(16'h8000) )  idq_pi_ki_o_1_sqmuxa_0_a5 (.A(N_360), 
        .B(N_370), .C(N_398), .D(N_369), .Y(idq_pi_ki_o_1_sqmuxa));
    SLE \hall_filter_factor_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(hall_filter_factor_o_1_sqmuxa_Z), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_hall_if_0_hall_filter_factor_o[0]));
    SLE \seq_cntl_cl_omega_o[8]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_seq_cntl_cl_omega_o[8]));
    SLE \adc_oc_thresh_o[4]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_oc_thresh_o[4]));
    SLE \rate_limit_ref_in_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_ref_in_o[1]));
    CFG4 #( .INIT(16'h0001) )  \READ_DECODE_PROC.prdata_o259_1_0  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[1]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[0]), .Y(prdata_o277_1_0));
    SLE \adc_channel_ch2_o[6]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[6]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch2_o[6]));
    CFG4 #( .INIT(16'h135F) )  \READ_DECODE_PROC.prdata_o259_RNI08O01  
        (.A(FOC_TRANSFORMS_0_ialpha_o[11]), .B(
        SPEED_ID_IQ_PI_0_iq_pi_output_o_11), .C(prdata_o259), .D(
        prdata_m2_e_5_6_1), .Y(prdata_N_5_mux_i_2_a0_11_1));
    SLE \adc_channel_ch1_o[6]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[6]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch1_o[6]));
    CFG4 #( .INIT(16'h8000) )  
        \READ_DECODE_PROC.prdata_o260_0_a2_1_RNI7FPB2  (.A(m7_m2_e_1_Z)
        , .B(N_359), .C(prdata_o260_0_a2_1), .D(N_353), .Y(N_404));
    SLE \adc_channel_ch0_o[7]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[7]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch0_o[7]));
    SLE \rate_limit_ref_in_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_ref_in_o[11]));
    SLE \rate_limit_rate_cnt_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_rate_cnt_o[10]));
    CFG2 #( .INIT(4'h2) )  READ_m3_e_0 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[7]), .Y(READ_m3_e_0_Z));
    SLE \speed_pi_ki_o[4]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_speed_pi_ki_o[4]));
    CFG4 #( .INIT(16'h2000) )  pwm_delay_time_val_o_1_sqmuxa_0_a5 (.A(
        N_363), .B(N_118), .C(N_365), .D(
        adc_scale_val_o_1_sqmuxa_0_a2_0_0_Z), .Y(
        pwm_delay_time_val_o_1_sqmuxa));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_0_iv_0_4[1]  (.A(
        SPEED_ID_IQ_PI_0_id_pi_output_o[1]), .B(
        FOC_TRANSFORMS_0_valpha_o_1), .C(prdata_o267), .D(prdata_o263), 
        .Y(prdata_o_1_0_iv_0_4[1]));
    CFG2 #( .INIT(4'h4) )  prdata_m2_i_a3_2_0 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(
        FOC_TRANSFORMS_0_id_o[8]), .Y(prdata_m2_i_a3_2_0_Z));
    CFG4 #( .INIT(16'h5F13) )  
        \READ_DECODE_PROC.prdata_o275_0_a2_RNILNUK  (.A(
        HALL_INTERFACE_1_angle_out_raw_o[8]), .B(
        HALL_INTERFACE_1_theta_output_o[8]), .C(prdata_o275), .D(
        prdata_o276), .Y(prdata_N_5_mux_i_4_a0_4));
    CFG4 #( .INIT(16'hFFF4) )  \prdata_o_1_0_iv_0_15_cZ[0]  (.A(
        prdata_o_1_0_iv_0_15_1[0]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .C(
        prdata_o_1_0_iv_0_15_3[0]), .D(prdata_o_1_0_iv_0_15_0[0]), .Y(
        prdata_o_1_0_iv_0_15[0]));
    SLE \auto_restart_no_o[1]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(auto_restart_no_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_auto_restart_no_o[1]));
    CFG4 #( .INIT(16'hC0A0) )  \prdata_o_1_0_iv_0_0_RNO[1]  (.A(
        RATE_LIMITER_0_rl_out_o[1]), .B(OLMNG_0_theta_o[1]), .C(
        prdata_m4_0), .D(MC_System_0_AMBA_SLAVE_0_PADDR[4]), .Y(
        prdata_m2_0_a2_13_0));
    SLE \adc_channel_ch2_o[1]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch2_o[1]));
    CFG4 #( .INIT(16'h0020) )  ADC_m2_e (.A(ADC_SCALING_0_ib_adc_o[8]), 
        .B(MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(ADC_N_5_mux));
    CFG3 #( .INIT(8'h80) )  rate_limit_rate_cnt_o_1_sqmuxa_0_a5 (.A(
        N_369), .B(N_398), .C(N_390), .Y(
        rate_limit_rate_cnt_o_1_sqmuxa));
    SLE \adc_scale_val_o[16]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[16]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_scale_val_o[16]));
    CFG3 #( .INIT(8'h51) )  \READ_DECODE_PROC.prdata_o259_2_RNILMHL6  
        (.A(prdata_o259_2_RNI6SNT), .B(N_358), .C(
        prdata_m2_e_0_13_tz_Z), .Y(prdata_m2_e_0_0));
    SLE \idq_pi_kp_o[1]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_kp_o[1]));
    SLE stop_motor_o (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(stop_motor_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_stop_motor_o));
    CFG4 #( .INIT(16'h0800) )  \READ_DECODE_PROC.prdata_o270_0_a2  (.A(
        N_390), .B(prdata_o270_0_a2_0), .C(N_101), .D(N_355), .Y(
        prdata_o270));
    SLE \rate_limit_ref_in_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_ref_in_o[2]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_iv_0_10_cZ[15]  (.A(
        OLMNG_0_theta_o[15]), .B(ADC_SCALING_0_ia_adc_o[15]), .C(
        prdata_o_1_0_iv_0_15_3_1[0]), .D(prdata_o257), .Y(
        prdata_o_1_iv_0_10[15]));
    SLE \adc_channel_ch0_o[8]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[8]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch0_o[8]));
    CFG4 #( .INIT(16'h0200) )  m7_m2_0_a2 (.A(
        RATE_LIMITER_0_rl_out_o[17]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(m7_N_5_mux));
    SLE \hall_filter_factor_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(hall_filter_factor_o_1_sqmuxa_Z), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_hall_if_0_hall_filter_factor_o[3]));
    CFG4 #( .INIT(16'hF8FF) )  \prdata_o_1_iv_10_13_cZ[10]  (.A(
        FOC_TRANSFORMS_0_id_o[10]), .B(prdata_o261), .C(
        prdata_o_1_iv_10_7[10]), .D(prdata_o_1_iv_10_13_1[10]), .Y(
        prdata_o_1_iv_10_13[10]));
    CFG3 #( .INIT(8'h01) )  prdata_m2_0_a2_7_0 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .C(prdata_m2_5_Z), .Y(
        prdata_m2_0_a2_7_0_0));
    CFG4 #( .INIT(16'h153F) )  
        \READ_DECODE_PROC.prdata_o268_0_a2_RNI2Q6B4  (.A(
        FOC_TRANSFORMS_0_vbeta_o[4]), .B(
        SPEED_ID_IQ_PI_0_iq_pi_output_o_4), .C(prdata_m2_e_5_6_1), .D(
        prdata_o264), .Y(prdata_m2_e_0_6));
    CFG4 #( .INIT(16'h8000) )  
        \READ_DECODE_PROC.prdata_o259_2_RNIB1OT  (.A(prdata_o259_1), 
        .B(FOC_TRANSFORMS_0_ialpha_o[9]), .C(prdata_o259_2), .D(
        prdata_o277_1_0), .Y(FOC_TRANSFORMS_0_ialpha_o_m_6));
    SLE \adc_channel_ch1_o[3]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch1_o[3]));
    SLE \olmng_iq_ref_in_o[8]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[8]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_iq_ref_in_o[8]));
    SLE \seq_cntl_config_o[3]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(seq_cntl_config_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_seq_cntl_config_o[3]));
    CFG4 #( .INIT(16'h8000) )  \READ_DECODE_PROC.prdata_o277  (.A(
        speed_pi_kp_o_0_sqmuxa_0_Z), .B(prdata_o277_1_0), .C(
        prdata_o277_2_1), .D(N_355), .Y(prdata_o277));
    CFG4 #( .INIT(16'h135F) )  
        \READ_DECODE_PROC.prdata_o270_0_a2_RNI5R7K5  (.A(prdata_o270), 
        .B(N_358), .C(adc_interface_0_result_ch0_o[6]), .D(
        FOC_m1_0_a2_2_1_Z), .Y(prdata_N_5_mux_i_3_a0_2));
    CFG4 #( .INIT(16'h8000) )  adc_channel_ch1_o_1_sqmuxa_0_a5 (.A(
        N_373), .B(N_359), .C(adc_scale_val_o_1_sqmuxa_0_a2_0_0_Z), .D(
        N_365), .Y(adc_channel_ch1_o_1_sqmuxa));
    SLE \pwm_delay_time_val_o[17]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[17]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_delay_time_val_o[17]));
    SLE \adc_oc_thresh_o[1]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_oc_thresh_o[1]));
    CFG2 #( .INIT(4'h8) )  \READ_DECODE_PROC.prdata_o263_RNIENFN  (.A(
        prdata_o263), .B(FOC_TRANSFORMS_0_valpha_o_6), .Y(
        FOC_TRANSFORMS_0_valpha_o_m_0));
    SLE \adc_channel_ch2_o[2]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch2_o[2]));
    SLE \seq_cntl_cl_omega_o[16]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[16]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_seq_cntl_cl_omega_o[16]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_iv_0_2[13]  (.A(prdata_o275)
        , .B(N_358), .C(HALL_INTERFACE_1_angle_out_raw_o[13]), .D(
        prdata_m2_0_a2_25_0), .Y(prdata_o_1_iv_0_2[13]));
    CFG4 #( .INIT(16'h0080) )  \prdata_o_1_iv_10_5_RNO[10]  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(
        FOC_TRANSFORMS_0_ibeta_o[10]), .C(prdata_o260_6), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[10]), .Y(
        FOC_TRANSFORMS_0_ibeta_o_m_0[10]));
    SLE \adc_oc_thresh_o[5]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_oc_thresh_o[5]));
    CFG4 #( .INIT(16'hECFF) )  \prdata_o_1_0_iv_0_12[1]  (.A(
        adc_interface_0_result_ch2_o[1]), .B(prdata_o_1_0_iv_0_0[1]), 
        .C(prdata_o272), .D(prdata_o_1_0_iv_0_12_1[1]), .Y(
        prdata_o_1_0_iv_0_13[1]));
    SLE \adc_channel_ch1_o[8]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[8]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch1_o[8]));
    SLE \adc_channel_ch0_o[5]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch0_o[5]));
    CFG3 #( .INIT(8'h37) )  
        \READ_DECODE_PROC.prdata_o276_2_0_1_RNII68N6  (.A(
        prdata_m2_0_a2_29_0_Z), .B(N_358), .C(prdata_m2_0_a2_3_0_Z), 
        .Y(prdata_N_5_mux_i_2_a0_1));
    SLE \olmng_theta_factor_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_theta_factor_o[10]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_0_a2_9[15]  (.A(N_353), 
        .B(prdata_o264_0_a2_1), .C(FOC_TRANSFORMS_0_vbeta_o[15]), .D(
        READ_m2_e_3_1_0_Z), .Y(N_308));
    CFG4 #( .INIT(16'h8000) )  
        seq_cntl_cl_omega_o_1_sqmuxa_0_a2_RNIIHV34 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(
        SPEED_ID_IQ_PI_0_speed_pi_output_o[4]), .C(N_358), .D(N_360), 
        .Y(N_243));
    CFG4 #( .INIT(16'h5F13) )  
        \READ_DECODE_PROC.prdata_o275_0_a2_RNI9RQK  (.A(
        HALL_INTERFACE_1_angle_out_raw_o[11]), .B(
        HALL_INTERFACE_1_theta_output_o[11]), .C(prdata_o275), .D(
        prdata_o276), .Y(prdata_N_5_mux_i_2_a0_4));
    CFG4 #( .INIT(16'h153F) )  
        \READ_DECODE_PROC.prdata_o268_0_a2_RNIUL6B4  (.A(
        FOC_TRANSFORMS_0_vbeta_o[2]), .B(
        SPEED_ID_IQ_PI_0_iq_pi_output_o_2), .C(prdata_m2_e_5_6_1), .D(
        prdata_o264), .Y(prdata_m2_e_5_6));
    SLE \olmng_theta_factor_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_theta_factor_o[15]));
    CFG4 #( .INIT(16'h0080) )  FOC_m1_0_a2_1_1 (.A(
        FOC_TRANSFORMS_0_iq_o[11]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(FOC_m1_0_a2_1_1_Z));
    SLE \olmng_dv_o[8]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_dv_o[8]));
    SLE \idq_pi_ki_o[1]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_ki_o[1]));
    CFG3 #( .INIT(8'hB3) )  \prdata_o_1_iv_0_5[14]  (.A(N_358), .B(
        prdata_o_1_iv_0_5_1[14]), .C(prdata_m1_0_a2_4_1), .Y(
        prdata_o_1_iv_0_5[14]));
    SLE \pwm_dead_time_val_o[4]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_dead_time_val_o[4]));
    CFG4 #( .INIT(16'hB3FF) )  \prdata_o_1_iv_9_cZ[16]  (.A(
        OLMNG_0_theta_o[16]), .B(prdata_o_1_iv_5_1[16]), .C(
        prdata_o_1_0_iv_0_15_3_1[0]), .D(prdata_o_1_iv_9_1[16]), .Y(
        prdata_o_1_iv_9[16]));
    SLE \adc_scale_val_o[14]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[14]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_scale_val_o[14]));
    SLE \adc_control_reg_val_o[5]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_control_reg_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_control_reg_val_o[5]));
    CFG4 #( .INIT(16'h00D5) )  
        hall_speed_factor_o_1_sqmuxa_0_a2_RNIN18V1 (.A(
        prdata_N_5_mux_i_1_a0_9_N_2L1_Z), .B(N_364), .C(
        FOC_TRANSFORMS_0_id_o[9]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .Y(
        hall_speed_factor_o_1_sqmuxa_0_a2_RNIN18V1_Z));
    SLE \adc_scale_val_o[0]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_scale_val_o[0]));
    CFG2 #( .INIT(4'h4) )  hall_speed_factor_o_1_sqmuxa_0_a2 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .Y(N_364));
    CFG4 #( .INIT(16'h0400) )  \READ_DECODE_PROC.prdata_o276_1  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[0]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[8]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[1]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .Y(prdata_o276_1));
    SLE \hall_speed_factor_o[17]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[17]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(hall_speed_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_hall_if_0_hall_speed_factor_o[17]));
    CFG4 #( .INIT(16'h4C00) )  
        \READ_DECODE_PROC.prdata_o273_0_a2_RNIF6AD8  (.A(
        adc_interface_0_result_ch3_o[11]), .B(prdata_N_5_mux_i_2_a0_1), 
        .C(prdata_o273), .D(prdata_N_5_mux_i_2_a0_11_1), .Y(
        prdata_N_5_mux_i_2_a0_11));
    SLE \pwm_period_val_o[17]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[17])
        , .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_period_val_o[17]));
    CFG4 #( .INIT(16'h0080) )  \prdata_o_1_iv_5_RNO[5]  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(
        FOC_TRANSFORMS_0_ibeta_o[5]), .C(prdata_o260_6), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[10]), .Y(
        FOC_TRANSFORMS_0_ibeta_o_m_0[5]));
    CFG4 #( .INIT(16'h0013) )  \READ_DECODE_PROC.prdata_o263_RNIPUI37  
        (.A(FOC_TRANSFORMS_0_valpha_o_8), .B(
        SPEED_ID_IQ_PI_0_id_pi_output_o_m[8]), .C(prdata_o263), .D(
        hall_speed_factor_o_1_sqmuxa_0_a2_RNIFHKE5_Z), .Y(
        prdata_N_5_mux_i_4_a0_5));
    CFG4 #( .INIT(16'h8000) )  olmng_dv_o_1_sqmuxa (.A(
        olmng_dv_o_1_sqmuxa_4), .B(olmng_dv_o_1_sqmuxa_0_Z), .C(
        olmng_dv_o_1_sqmuxa_9), .D(olmng_dv_o_1_sqmuxa_7), .Y(
        olmng_dv_o_1_sqmuxa_Z));
    SLE \olmng_iq_ref_in_o[9]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[9]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_iq_ref_in_o[9]));
    SLE \hall_filter_factor_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(hall_filter_factor_o_1_sqmuxa_Z), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_hall_if_0_hall_filter_factor_o[2]));
    CFG4 #( .INIT(16'h6FFF) )  
        \READ_DECODE_PROC.prdata_o276_2_0_1_RNIV9376  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .C(
        prdata_N_5_mux_i_4_a0_1_1_Z), .D(N_358), .Y(
        prdata_N_5_mux_i_4_a0_1));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_13_a1[16]  (.A(
        prdata_o277_1_0), .B(HALL_INTERFACE_1_omega_out_o[16]), .C(
        prdata_o277_2_0), .D(prdata_o277_2_1), .Y(
        prdata_o_1_iv_13_a1[16]));
    CFG4 #( .INIT(16'hFEFA) )  \prdata_o_1_iv_0_6[12]  (.A(N_347), .B(
        SPEED_ID_IQ_PI_0_iq_pi_output_o_12), .C(prdata_o_1_iv_0_3[12]), 
        .D(prdata_m2_e_5_6_1), .Y(prdata_o_1_iv_0_6_0));
    CFG4 #( .INIT(16'hDC50) )  \prdata_o_1_iv_0[7]  (.A(prdata_o276), 
        .B(N_358), .C(HALL_INTERFACE_1_theta_output_o[7]), .D(
        prdata_m2_0_a2_23_0), .Y(prdata_o_1_iv_0[7]));
    SLE \speed_pi_ki_o[9]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[9]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_speed_pi_ki_o[9]));
    SLE \idq_pi_ki_o[3]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_ki_o[3]));
    CFG2 #( .INIT(4'h4) )  prdata_m2_i_a3_0_0 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(
        FOC_TRANSFORMS_0_id_o[11]), .Y(prdata_m2_i_a3_0_0_Z));
    CFG3 #( .INIT(8'h1D) )  m5_m2 (.A(ADC_SCALING_0_ib_adc_o[17]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .C(
        SPEED_ID_IQ_PI_0_speed_pi_output_o[17]), .Y(m5_m2_Z));
    SLE \adc_oc_thresh_o[0]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_oc_thresh_o[0]));
    SLE \pwm_dead_time_val_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_dead_time_val_o[0]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_iv_0_0[12]  (.A(prdata_o259)
        , .B(N_358), .C(FOC_TRANSFORMS_0_ialpha_o[12]), .D(
        prdata_o_1_iv_0_13_0_tz[12]), .Y(prdata_o_1_iv_0_0[12]));
    CFG4 #( .INIT(16'h0080) )  m7_m1_0_a2_1 (.A(
        FOC_TRANSFORMS_0_iq_o[17]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(m7_m1_0_a2_1_Z));
    SLE \adc_scale_val_o[11]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[11]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_scale_val_o[11]));
    SLE \olmng_iq_ref_in_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_iq_ref_in_o[13]));
    CFG4 #( .INIT(16'h0800) )  OLMNG_m2_0_a2_5 (.A(OLMNG_0_theta_o[8]), 
        .B(MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(OLMNG_N_5_mux_2));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_1_a0_2[3]  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .B(olmng_dv_o_1_sqmuxa_4), 
        .C(SPEED_ID_IQ_PI_0_id_pi_output_o[3]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .Y(
        prdata_o_1_0_iv_1_a0_2_0[3]));
    CFG4 #( .INIT(16'hECFF) )  \prdata_o_1_iv_10_11_cZ[10]  (.A(
        adc_interface_0_result_ch3_o[10]), .B(prdata_o_1_iv_10_0[10]), 
        .C(prdata_o273), .D(prdata_o_1_iv_10_11_1[10]), .Y(
        prdata_o_1_iv_10_11[10]));
    CFG3 #( .INIT(8'h07) )  \prdata_o_1_iv_10_13_1[10]  (.A(
        HALL_INTERFACE_1_omega_out_o[10]), .B(prdata_o277), .C(
        prdata_o_1_iv_10_2[10]), .Y(prdata_o_1_iv_10_13_1[10]));
    SLE \idq_pi_kp_o[6]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_kp_o[6]));
    SLE \olmng_theta_factor_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_theta_factor_o[11]));
    SLE \pwm_dead_time_val_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_dead_time_val_o[10]));
    SLE \olmng_theta_factor_o[7]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_theta_factor_o[7]));
    CFG4 #( .INIT(16'hEC00) )  
        hall_speed_factor_o_1_sqmuxa_0_a2_RNI3AHL5 (.A(
        prdata_m2_i_a3_0_0_Z), .B(OLMNG_N_5_mux_0), .C(N_364), .D(
        N_358), .Y(hall_speed_factor_o_1_sqmuxa_0_a2_RNI3AHL5_Z));
    SLE \idq_pi_kp_o[7]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_kp_o[7]));
    CFG4 #( .INIT(16'h0008) )  \prdata_o_1_0_iv_0_9_tz_RNO[1]  (.A(
        FOC_TRANSFORMS_0_id_o[1]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(prdata_N_5_mux_13));
    SLE \pwm_dead_time_val_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_dead_time_val_o[13]));
    CFG4 #( .INIT(16'hFFF8) )  \prdata_o_1_0_iv_0_14_cZ[1]  (.A(
        prdata_o257), .B(ADC_SCALING_0_ia_adc_o[1]), .C(
        prdata_o_1_0_iv_0_5[1]), .D(prdata_o_1_0_iv_0_6[1]), .Y(
        prdata_o_1_0_iv_0_15[1]));
    SLE \adc_channel_ch1_o[4]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch1_o[4]));
    CFG4 #( .INIT(16'h1333) )  
        \READ_DECODE_PROC.prdata_o267_1_RNIKMAM5  (.A(prdata_o267_1), 
        .B(hall_speed_factor_o_1_sqmuxa_0_a2_RNIBDKE5_Z), .C(
        SPEED_ID_IQ_PI_0_id_pi_output_o[6]), .D(
        pwm_period_val_o_1_sqmuxa_8), .Y(prdata_N_5_mux_i_3_a0_0));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_0_iv_0_1[1]  (.A(
        prdata_o_1_0_iv_0_8_tz[1]), .B(adc_interface_0_result_ch0_o[1])
        , .C(N_358), .D(prdata_o270), .Y(prdata_o_1_0_iv_0_1[1]));
    SLE \olmng_dv_o[4]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_dv_o[4]));
    SLE \adc_channel_ch1_o[5]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch1_o[5]));
    SLE \seq_cntl_cl_omega_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_seq_cntl_cl_omega_o[2]));
    CFG4 #( .INIT(16'h153F) )  
        \READ_DECODE_PROC.prdata_o271_0_a2_RNI9RQ54  (.A(
        FOC_TRANSFORMS_0_vbeta_o[11]), .B(
        adc_interface_0_result_ch1_o_10), .C(prdata_N_5_mux_i_3_a0_7_1)
        , .D(prdata_o264), .Y(prdata_N_5_mux_i_2_a0_7));
    CFG4 #( .INIT(16'hFFEC) )  \prdata_o_1_iv_13_cZ[7]  (.A(
        FOC_TRANSFORMS_0_id_o[7]), .B(prdata_o_1_iv_5[7]), .C(
        prdata_o261), .D(prdata_o_1_iv_6[7]), .Y(prdata_o_1_iv_13[7]));
    SLE \adc_oc_thresh_o[15]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[15]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_oc_thresh_o[15]));
    SLE \idq_pi_ki_o[7]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_ki_o[7]));
    SLE \seq_cntl_config_o[1]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(seq_cntl_config_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_seq_cntl_config_o[1]));
    SLE \pwm_gain_val_o[16]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[16]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_gain_val_o[16]));
    SLE \olmng_iq_ref_in_o[16]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[16]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_iq_ref_in_o[16]));
    SLE \pwm_delay_time_val_o[6]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_delay_time_val_o[6]));
    SLE \hall_speed_factor_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(hall_speed_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_hall_if_0_hall_speed_factor_o[13]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_iv_0_10_cZ[14]  (.A(
        RATE_LIMITER_0_rl_out_o[14]), .B(ADC_SCALING_0_ia_adc_o[14]), 
        .C(prdata_o257), .D(prdata_o265), .Y(prdata_o_1_iv_0_10[14]));
    CFG3 #( .INIT(8'h20) )  \prdata_o_1_iv_0_6_a0_0[14]  (.A(
        SPEED_ID_IQ_PI_0_iq_pi_output_o_14), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(
        prdata_o_1_iv_0_6_a0_0[14]));
    SLE \olmng_iq_ref_in_o[5]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_iq_ref_in_o[5]));
    CFG4 #( .INIT(16'h3BBB) )  \prdata_o_1_0_iv_0_15_1[0]  (.A(
        prdata_o_1_0_iv_0_2_0_1[0]), .B(N_358), .C(
        SPEED_ID_IQ_PI_0_speed_pi_output_o[0]), .D(N_360), .Y(
        prdata_o_1_0_iv_0_15_1[0]));
    CFG4 #( .INIT(16'h1000) )  
        \READ_DECODE_PROC.prdata_o259_2_RNIS3A44  (.A(
        FOC_TRANSFORMS_0_ialpha_o_m[3]), .B(prdata_o260_0_a2_1_RNI3FNN)
        , .C(prdata_m2_e_27_3), .D(prdata_m2_e_27_6), .Y(
        prdata_m2_e_27_12));
    SLE \speed_pi_kp_o[9]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[9]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_0_sqmuxa_Z), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_speed_pi_kp_o[9]));
    SLE \speed_pi_ki_o[0]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_speed_pi_ki_o[0]));
    CFG4 #( .INIT(16'hF3F5) )  prdata_m3_13_0 (.A(
        ADC_SCALING_0_ia_adc_o[2]), .B(FOC_TRANSFORMS_0_id_o[2]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .Y(prdata_m3_13_0_Z));
    SLE \idq_pi_kp_o[16]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[16]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_kp_o[16]));
    CFG4 #( .INIT(16'h8000) )  olmng_theta_factor_o_1_sqmuxa_0_a5 (.A(
        N_373), .B(N_364), .C(N_376), .D(N_365), .Y(
        olmng_theta_factor_o_1_sqmuxa));
    CFG4 #( .INIT(16'hDC50) )  \prdata_o_1_iv_1[16]  (.A(prdata_o276), 
        .B(N_358), .C(HALL_INTERFACE_1_theta_output_o[16]), .D(
        prdata_m2_0_a2_27_0), .Y(prdata_o_1_iv_1[16]));
    SLE \olmng_dv_o[9]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_dv_o[9]));
    CFG3 #( .INIT(8'h04) )  \READ_DECODE_PROC.prdata_o272_0_a2_0  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[3]), .Y(N_371));
    SLE \speed_pi_kp_o[8]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[8]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_0_sqmuxa_Z), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_speed_pi_kp_o[8]));
    SLE \seq_cntl_cl_omega_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_seq_cntl_cl_omega_o[3]));
    SLE \olmng_iq_ref_in_o[17]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[17]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_iq_ref_in_o[17]));
    SLE \idq_pi_kp_o[17]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[17]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_kp_o[17]));
    CFG4 #( .INIT(16'h4000) )  \READ_DECODE_PROC.prdata_o268_0_a2  (.A(
        N_101), .B(N_360), .C(N_355), .D(READ_m2_e_2_1), .Y(
        prdata_m2_e_5_6_1));
    SLE \speed_pi_ki_o[1]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_speed_pi_ki_o[1]));
    CFG4 #( .INIT(16'hF7FF) )  \READ_DECODE_PROC.prdata_o276  (.A(
        prdata_o276_1), .B(prdata_o277_2_0), .C(N_1608), .D(
        olmng_dv_o_1_sqmuxa_3), .Y(prdata_o276));
    SLE \adc_channel_ch3_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch3_o[14]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_14_RNO[7]  (.A(N_364), 
        .B(N_358), .C(FOC_TRANSFORMS_0_iq_o[7]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .Y(
        FOC_TRANSFORMS_0_iq_o_m[7]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_iv_0_5[13]  (.A(
        SPEED_ID_IQ_PI_0_id_pi_output_o[13]), .B(
        FOC_TRANSFORMS_0_vbeta_o[13]), .C(prdata_o267), .D(prdata_o264)
        , .Y(prdata_o_1_iv_0_5[13]));
    SLE \rate_limit_rate_cnt_o[4]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_rate_cnt_o[4]));
    SLE \pwm_period_val_o[1]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_period_val_o[1]));
    SLE \pwm_dead_time_val_o[6]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_dead_time_val_o[6]));
    CFG4 #( .INIT(16'h0080) )  FOC_m1_0_a2_0_1 (.A(
        FOC_TRANSFORMS_0_iq_o[9]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(FOC_m1_0_a2_0_1_Z));
    CFG3 #( .INIT(8'h80) )  
        \READ_DECODE_PROC.prdata_o260_0_a2_1_RNI3FNN  (.A(N_381), .B(
        FOC_TRANSFORMS_0_ibeta_o[3]), .C(prdata_o260_0_a2_1), .Y(
        prdata_o260_0_a2_1_RNI3FNN));
    CFG2 #( .INIT(4'h8) )  \READ_DECODE_PROC.prdata_o260_0_a2  (.A(
        N_381), .B(prdata_o260_0_a2_1), .Y(prdata_o260));
    CFG4 #( .INIT(16'h8000) )  speed_pi_kp_o_0_sqmuxa (.A(
        speed_pi_kp_o_0_sqmuxa_1_Z), .B(N_352), .C(
        speed_pi_kp_o_0_sqmuxa_9), .D(un3_psel_i), .Y(
        speed_pi_kp_o_0_sqmuxa_Z));
    SLE \seq_cntl_cl_omega_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_seq_cntl_cl_omega_o[15]));
    CFG4 #( .INIT(16'h058D) )  prdata_N_5_mux_i_4_a0_1_1 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(
        FOC_TRANSFORMS_0_iq_o[8]), .C(prdata_m2_6_Z), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(
        prdata_N_5_mux_i_4_a0_1_1_Z));
    SLE \adc_channel_ch1_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch1_o[12]));
    SLE \seq_cntl_cl_omega_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_seq_cntl_cl_omega_o[13]));
    SLE \adc_channel_ch0_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch0_o[14]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_14_RNO_0[7]  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(
        SPEED_ID_IQ_PI_0_speed_pi_output_o[7]), .C(N_358), .D(N_360), 
        .Y(SPEED_ID_IQ_PI_0_speed_pi_output_o_m[7]));
    SLE \adc_channel_ch2_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch2_o[10]));
    CFG4 #( .INIT(16'h153F) )  
        \READ_DECODE_PROC.prdata_o269_0_a2_0_RNI2L872  (.A(N_361), .B(
        prdata_o277), .C(HALL_INTERFACE_1_omega_out_o[2]), .D(
        prdata_m1_0_a2_0_0), .Y(prdata_m2_e_5_4));
    CFG4 #( .INIT(16'h4000) )  \READ_DECODE_PROC.prdata_o275_0_a2  (.A(
        N_101), .B(prdata_o275_0_a2_N_2L1), .C(N_391), .D(N_371), .Y(
        prdata_o275));
    SLE \pwm_gain_val_o[1]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_gain_val_o[1]));
    CFG4 #( .INIT(16'h4000) )  \prdata_o_1_iv_0_a2_5[12]  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(OLMNG_0_theta_o[12]), 
        .C(N_358), .D(N_363), .Y(N_343));
    CFG2 #( .INIT(4'h2) )  prdata_m2_0_a2_0 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .Y(prdata_m4_0));
    CFG4 #( .INIT(16'h1050) )  
        \READ_DECODE_PROC.prdata_o267_1_RNITSVT6  (.A(
        HALL_INTERFACE_1_omega_out_o_m[9]), .B(
        hall_speed_factor_o_1_sqmuxa_0_a2_RNIN18V1_Z), .C(
        prdata_o267_1_RNIT66V), .D(N_358), .Y(
        prdata_N_5_mux_i_1_a0_13_1));
    SLE \adc_channel_ch1_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch1_o[11]));
    CFG2 #( .INIT(4'h8) )  \READ_DECODE_PROC.prdata_o275_0_a2_0  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[8]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[9]), .Y(prdata_o275_0_a2_0));
    CFG4 #( .INIT(16'h2000) )  \prdata_o_1_iv_5_1_RNO[16]  (.A(
        SPEED_ID_IQ_PI_0_speed_pi_output_o[16]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(SPEED_m1_0_a2_1));
    CFG4 #( .INIT(16'h135F) )  
        \READ_DECODE_PROC.prdata_o273_0_a2_RNIS41R  (.A(
        adc_interface_0_result_ch3_o[4]), .B(
        adc_interface_0_result_ch2_o[4]), .C(prdata_o273), .D(
        prdata_o272), .Y(prdata_m2_e_0_9));
    SLE \idq_pi_kp_o[5]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_kp_o[5]));
    SLE \pwm_gain_val_o[7]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[7]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_gain_val_o[7]));
    SLE \adc_channel_ch0_o[1]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch0_o[1]));
    SLE \olmng_iq_ref_in_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_iq_ref_in_o[15]));
    CFG2 #( .INIT(4'h8) )  \READ_DECODE_PROC.prdata_o268_0_a2_RNI2O7N  
        (.A(prdata_m2_e_5_6_1), .B(SPEED_ID_IQ_PI_0_iq_pi_output_o_6), 
        .Y(SPEED_ID_IQ_PI_0_iq_pi_output_o_m[6]));
    SLE \speed_pi_ki_o[2]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_speed_pi_ki_o[2]));
    SLE \rate_limit_rate_cnt_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_rate_cnt_o[14]));
    CFG4 #( .INIT(16'h0080) )  \READ_DECODE_PROC.prdata_o260_0_a2_1  (
        .A(MC_System_0_AMBA_SLAVE_0_PADDR[3]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[10]), .Y(prdata_o260_0_a2_1));
    CFG4 #( .INIT(16'h0080) )  \prdata_o_1_0_iv_1_a1[3]  (.A(
        prdata_o267_5), .B(prdata_o_1_0_iv_1_a1_1[3]), .C(
        prdata_o_1_0_iv_1_a1_3_0[3]), .D(N_101), .Y(
        prdata_o_1_0_iv_1_a1[3]));
    CFG4 #( .INIT(16'h0001) )  pwm_period_val_o_1_sqmuxa_8_0_a5 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[7]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[9]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[6]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[8]), .Y(
        pwm_period_val_o_1_sqmuxa_8));
    SLE \adc_channel_ch2_o[8]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[8]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch2_o[8]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_iv_0_4[14]  (.A(
        FOC_TRANSFORMS_0_ialpha_o[14]), .B(
        FOC_TRANSFORMS_0_valpha_o_14), .C(prdata_o259), .D(prdata_o263)
        , .Y(prdata_o_1_iv_0_4[14]));
    CFG3 #( .INIT(8'h01) )  prdata_m2_0_a2_3_0 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .C(prdata_m2_3_Z), .Y(
        prdata_m2_0_a2_3_0_Z));
    CFG4 #( .INIT(16'h8000) )  pwm_gain_val_o_1_sqmuxa_0_a2_0_RNIN43K1 
        (.A(adc_interface_0_result_ch3_o[9]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .C(N_370), .D(N_375), .Y(
        adc_interface_0_result_ch3_o_m_4));
    CFG4 #( .INIT(16'h8000) )  hall_sensor_polarity_o_1_sqmuxa_0_a5 (
        .A(MC_System_0_AMBA_SLAVE_0_PADDR[10]), .B(N_373), .C(N_381), 
        .D(N_365), .Y(hall_sensor_polarity_o_1_sqmuxa));
    SLE \adc_scale_val_o[17]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[17]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_scale_val_o[17]));
    SLE \speed_pi_kp_o[7]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[7]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_0_sqmuxa_Z), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_speed_pi_kp_o[7]));
    SLE \pwm_gain_val_o[9]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[9]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_gain_val_o[9]));
    SLE \olmng_theta_factor_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_theta_factor_o[0]));
    CFG4 #( .INIT(16'h153F) )  
        \READ_DECODE_PROC.prdata_o272_0_a2_RNIAQ8N  (.A(
        FOC_TRANSFORMS_0_ibeta_o[9]), .B(
        adc_interface_0_result_ch2_o[9]), .C(prdata_o272), .D(
        prdata_o260), .Y(prdata_N_5_mux_i_1_a0_12));
    SLE \idq_pi_kp_o[3]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_kp_o[3]));
    SLE \pwm_gain_val_o[3]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_gain_val_o[3]));
    SLE \pwm_dead_time_val_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_dead_time_val_o[15]));
    SLE \adc_control_reg_val_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_control_reg_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_control_reg_val_o[1]));
    SLE \adc_oc_thresh_o[9]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[9]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_oc_thresh_o[9]));
    SLE \adc_control_reg_val_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_control_reg_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_control_reg_val_o[2]));
    CFG4 #( .INIT(16'h4000) )  \READ_DECODE_PROC.prdata_o263  (.A(
        N_101), .B(prdata_o_1_0_iv_1_a1_3_0[3]), .C(
        pwm_period_val_o_1_sqmuxa_8), .D(prdata_o267_5), .Y(
        prdata_o263));
    SLE \rate_limit_slew_cnt_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_slew_cnt_o[13]));
    CFG4 #( .INIT(16'h4C00) )  
        \READ_DECODE_PROC.prdata_o273_0_a2_RNIUL8J8  (.A(
        adc_interface_0_result_ch3_o[8]), .B(prdata_N_5_mux_i_4_a0_1), 
        .C(prdata_o273), .D(prdata_N_5_mux_i_4_a0_11_1), .Y(
        prdata_N_5_mux_i_4_a0_11));
    SLE \adc_scale_val_o[7]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[7]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_scale_val_o[7]));
    CFG4 #( .INIT(16'h8000) )  adc_channel_ch0_o_1_sqmuxa_0_a5 (.A(
        N_370), .B(N_359), .C(adc_scale_val_o_1_sqmuxa_0_a2_0_0_Z), .D(
        N_365), .Y(adc_channel_ch0_o_1_sqmuxa));
    SLE \rate_limit_rate_cnt_o[5]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_rate_cnt_o[5]));
    SLE \adc_channel_ch2_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch2_o[15]));
    CFG4 #( .INIT(16'h0001) )  \READ_DECODE_PROC.prdata_o276_2_0  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[7]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[10]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[6]), .Y(prdata_o277_2_0));
    SLE \rate_limit_rate_cnt_o[6]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_rate_cnt_o[6]));
    CFG2 #( .INIT(4'h1) )  auto_restart_no_o_1_sqmuxa_3_0_a2 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[8]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[6]), .Y(olmng_dv_o_1_sqmuxa_4));
    CFG4 #( .INIT(16'h2000) )  \prdata_o_1_iv_9_tz_RNO[5]  (.A(
        SPEED_ID_IQ_PI_0_speed_pi_output_o[5]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(SPEED_N_5_mux_1));
    SLE \idq_pi_kp_o[10]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[10]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_kp_o[10]));
    SLE \pwm_period_val_o[16]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[16])
        , .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_period_val_o[16]));
    SLE \olmng_dv_o[12]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[12]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_dv_o[12]));
    CFG4 #( .INIT(16'h4000) )  \prdata_o_1_iv_0_a2_4[12]  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(
        RATE_LIMITER_0_rl_out_o[12]), .C(N_358), .D(N_360), .Y(N_342));
    CFG3 #( .INIT(8'h40) )  \READ_DECODE_PROC.prdata_o269_0_a2  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(N_363), .C(N_358), .Y(
        prdata_o_1_0_iv_0_15_3_1[0]));
    CFG4 #( .INIT(16'h8000) )  idq_pi_kp_o_1_sqmuxa (.A(
        olmng_dv_o_1_sqmuxa_3), .B(idq_pi_kp_o_1_sqmuxa_1_Z), .C(
        olmng_dv_o_1_sqmuxa_9), .D(olmng_dv_o_1_sqmuxa_7), .Y(
        idq_pi_kp_o_1_sqmuxa_Z));
    CFG4 #( .INIT(16'h53FF) )  prdata_m2_e_0_1_1 (.A(
        FOC_TRANSFORMS_0_iq_o[4]), .B(ADC_SCALING_0_ib_adc_o[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .Y(prdata_m2_e_0_1_1_Z));
    SLE \olmng_theta_factor_o[8]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_theta_factor_o[8]));
    SLE \pwm_delay_time_val_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_delay_time_val_o[0]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_iv_10_5[10]  (.A(
        prdata_o267), .B(N_381), .C(
        SPEED_ID_IQ_PI_0_id_pi_output_o[10]), .D(
        FOC_TRANSFORMS_0_ibeta_o_m_0[10]), .Y(prdata_o_1_iv_10_5[10]));
    SLE \pwm_gain_val_o[4]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_gain_val_o[4]));
    CFG4 #( .INIT(16'hFFF8) )  \prdata_o_1_iv_14_RNO_1[5]  (.A(
        FOC_TRANSFORMS_0_ialpha_o[5]), .B(prdata_o259), .C(
        prdata_o_1_iv_1[5]), .D(prdata_o_1_iv_5[5]), .Y(
        prdata_o_1_iv_9_0[5]));
    SLE \olmng_theta_factor_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_theta_factor_o[12]));
    SLE \pwm_dead_time_val_o[7]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_dead_time_val_o[7]));
    CFG4 #( .INIT(16'hFFEC) )  \prdata_o_1_iv_0_7_cZ[12]  (.A(
        FOC_TRANSFORMS_0_ibeta_o[12]), .B(prdata_o_1_iv_0_0[12]), .C(
        prdata_o260), .D(prdata_o_1_iv_0_2[12]), .Y(
        prdata_o_1_iv_0_7[12]));
    CFG4 #( .INIT(16'h0577) )  m5_i_o2_3_1_0_1 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(m5_m2_Z), .C(
        OLMNG_0_theta_o[17]), .D(MC_System_0_AMBA_SLAVE_0_PADDR[4]), 
        .Y(m5_i_o2_3_1_0_1_Z));
    CFG4 #( .INIT(16'hFFF8) )  \prdata_o_1_iv_0_7[13]  (.A(
        FOC_TRANSFORMS_0_valpha_o_13), .B(prdata_o263), .C(
        prdata_o_1_iv_0_2[13]), .D(prdata_o_1_iv_0_5[13]), .Y(
        prdata_o_1_iv_0_7_0[13]));
    SLE \olmng_iq_ref_in_o[1]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_iq_ref_in_o[1]));
    CFG3 #( .INIT(8'h80) )  \prdata_o_1_iv_14_RNO[5]  (.A(N_375), .B(
        adc_interface_0_result_ch2_o[5]), .C(N_371), .Y(
        adc_interface_0_result_ch2_o_m[5]));
    CFG4 #( .INIT(16'h0800) )  OLMNG_m2_0_a2_3 (.A(OLMNG_0_theta_o[6]), 
        .B(MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(OLMNG_N_5_mux_1));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_iv_10_cZ[16]  (.A(
        RATE_LIMITER_0_rl_out_o[16]), .B(ADC_SCALING_0_ia_adc_o[16]), 
        .C(prdata_o257), .D(prdata_o265), .Y(prdata_o_1_iv_10[16]));
    CFG3 #( .INIT(8'hB0) )  \prdata_o_1_iv_10_1[10]  (.A(
        prdata_o_1_iv_9_tz[10]), .B(prdata_m3_i_0), .C(N_358), .Y(
        prdata_o_1_iv_10_1[10]));
    CFG3 #( .INIT(8'h70) )  \READ_DECODE_PROC.prdata_o259_RNIP3RR5  (
        .A(FOC_TRANSFORMS_0_ialpha_o[2]), .B(prdata_o259), .C(
        prdata_m2_e_5_0), .Y(prdata_m2_e_5_2));
    SLE \adc_channel_ch3_o[0]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch3_o[0]));
    SLE \seq_cntl_cl_omega_o[17]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[17]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_seq_cntl_cl_omega_o[17]));
    CFG3 #( .INIT(8'h01) )  READ_m2_e_3_1_0 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[6]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[10]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[7]), .Y(READ_m2_e_3_1_0_Z));
    SLE \pwm_delay_time_val_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_delay_time_val_o[2]));
    CFG4 #( .INIT(16'h0001) )  READ_m2_e_N_2L1 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[7]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[3]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[8]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[9]), .Y(READ_m2_e_N_2L1_Z));
    SLE \pwm_dead_time_val_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_dead_time_val_o[14]));
    CFG4 #( .INIT(16'h2000) )  stop_motor_o_1_sqmuxa_0_a5 (.A(N_360), 
        .B(N_118), .C(N_365), .D(N_376), .Y(stop_motor_o_1_sqmuxa));
    SLE start_motor_o (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(start_motor_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_start_motor_o));
    CFG4 #( .INIT(16'hAC00) )  prdata_m2_0_a2_31_0 (.A(
        SPEED_ID_IQ_PI_0_speed_pi_output_o[6]), .B(
        ADC_SCALING_0_ib_adc_o[6]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .D(m5_m2_0_a2_0_Z), .Y(
        prdata_m2_0_a2_31_0_Z));
    CFG4 #( .INIT(16'h4000) )  \prdata_o_1_iv_0_a2_5[13]  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(OLMNG_0_theta_o[13]), 
        .C(N_358), .D(N_363), .Y(N_330));
    SLE \olmng_theta_factor_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_theta_factor_o[14]));
    CFG4 #( .INIT(16'h0080) )  FOC_m1_0_a2_2_1 (.A(
        FOC_TRANSFORMS_0_iq_o[6]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(FOC_m1_0_a2_2_1_Z));
    CFG4 #( .INIT(16'h8000) )  
        \READ_DECODE_PROC.prdata_o275_0_a2_RNIVFI6J  (.A(
        prdata_N_5_mux_i_4_a0_6), .B(prdata_N_5_mux_i_4_a0_5), .C(
        prdata_N_5_mux_i_4_a0_4), .D(prdata_N_5_mux_i_4_a0_7), .Y(
        prdata_N_5_mux_i_4_a0_13));
    SLE \rate_limit_rate_cnt_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_rate_cnt_o[2]));
    SLE \olmng_theta_factor_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_theta_factor_o[1]));
    SLE \speed_pi_kp_o[14]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[14]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_0_sqmuxa_Z), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_speed_pi_kp_o[14]));
    SLE \idq_pi_ki_o[4]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_ki_o[4]));
    CFG4 #( .INIT(16'hC0A0) )  prdata_m2_0_a2_0_0 (.A(
        RATE_LIMITER_0_rl_out_o[3]), .B(OLMNG_0_theta_o[3]), .C(
        prdata_m4_0), .D(MC_System_0_AMBA_SLAVE_0_PADDR[4]), .Y(
        prdata_m2_0_a2_0_Z));
    SLE \idq_pi_ki_o[16]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[16]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_ki_o[16]));
    SLE \olmng_iq_ref_in_o[2]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_iq_ref_in_o[2]));
    CFG3 #( .INIT(8'h04) )  m7_m2_e_1 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[6]), .B(
        FOC_TRANSFORMS_0_ibeta_o[17]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[7]), .Y(m7_m2_e_1_Z));
    SLE \idq_pi_ki_o[17]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[17]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_ki_o[17]));
    SLE \pwm_period_val_o[4]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_period_val_o[4]));
    CFG4 #( .INIT(16'h135F) )  \prdata_o_1_iv_0_6_1[15]  (.A(
        FOC_TRANSFORMS_0_ialpha_o[15]), .B(
        SPEED_ID_IQ_PI_0_iq_pi_output_o_15), .C(prdata_o259), .D(
        prdata_m2_e_5_6_1), .Y(prdata_o_1_iv_0_6_0_Z[15]));
    CFG4 #( .INIT(16'h020A) )  
        \READ_DECODE_PROC.prdata_o273_0_a2_RNIREU89  (.A(
        prdata_N_5_mux_i_3_a0_3), .B(adc_interface_0_result_ch3_o[6]), 
        .C(SPEED_ID_IQ_PI_0_iq_pi_output_o_m[6]), .D(prdata_o273), .Y(
        prdata_N_5_mux_i_3_a0_11));
    CFG4 #( .INIT(16'hDC50) )  \prdata_o_1_iv_10_0[10]  (.A(
        prdata_o276), .B(N_358), .C(
        HALL_INTERFACE_1_theta_output_o[10]), .D(prdata_m2_0_a2_21_0), 
        .Y(prdata_o_1_iv_10_0[10]));
    CFG3 #( .INIT(8'h80) )  \READ_DECODE_PROC.prdata_o273_0_a2  (.A(
        N_375), .B(MC_System_0_AMBA_SLAVE_0_PADDR[11]), .C(N_370), .Y(
        prdata_o273));
    SLE \olmng_dv_o[15]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[15]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_dv_o[15]));
    CFG3 #( .INIT(8'h01) )  adc_channel_ch2_o_1_sqmuxa_1_0_0_a2 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[7]), .Y(N_391));
    SLE \pwm_gain_val_o[12]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[12]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_gain_val_o[12]));
    SLE \rate_limit_rate_cnt_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_rate_cnt_o[1]));
    CFG4 #( .INIT(16'h1000) )  hall_sensor_polarity_o_1_sqmuxa_0_a2 (
        .A(MC_System_0_AMBA_SLAVE_0_PADDR[7]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[6]), .C(N_359), .D(N_353), .Y(
        N_381));
    SLE \adc_scale_val_o[6]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[6]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_scale_val_o[6]));
    SLE \adc_scale_val_o[9]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[9]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_scale_val_o[9]));
    CFG4 #( .INIT(16'hAC00) )  \prdata_o_1_iv_18_1[5]  (.A(
        ADC_SCALING_0_ib_adc_o[5]), .B(ADC_SCALING_0_ia_adc_o[5]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(N_359), .Y(
        prdata_o_1_iv_18_1[5]));
    SLE \adc_channel_ch2_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch2_o[13]));
    CFG4 #( .INIT(16'h0080) )  \prdata_o_1_iv_6_a0[16]  (.A(N_355), .B(
        READ_m2_e_2_1), .C(prdata_o_1_iv_6_a0_0[16]), .D(N_101), .Y(
        prdata_o_1_iv_6_a0[16]));
    SLE \rate_limit_slew_cnt_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_slew_cnt_o[12]));
    CFG4 #( .INIT(16'h0EFF) )  
        \READ_DECODE_PROC.prdata_o276_2_0_1_RNI5SRL6  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(prdata_m2_e_17_1_Z), .C(
        FOC_m1_0_a2_1), .D(N_358), .Y(prdata_m2_e_27_10_1));
    SLE \hall_speed_factor_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(hall_speed_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_hall_if_0_hall_speed_factor_o[2]));
    CFG4 #( .INIT(16'h0AC0) )  \prdata_o_1_iv_0_1_1[15]  (.A(
        FOC_TRANSFORMS_0_iq_o[15]), .B(
        SPEED_ID_IQ_PI_0_speed_pi_output_o[15]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .Y(prdata_o_1_iv_0_1_1[15])
        );
    CFG4 #( .INIT(16'h0040) )  \prdata_o_1_0_iv_1_a1_1[3]  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[7]), .B(
        FOC_TRANSFORMS_0_valpha_o_3), .C(olmng_dv_o_1_sqmuxa_4), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[9]), .Y(
        prdata_o_1_0_iv_1_a1_1[3]));
    CFG4 #( .INIT(16'h0010) )  \READ_DECODE_PROC.prdata_o267_1  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(prdata_o267_1_0), .D(
        N_101), .Y(prdata_o267_1));
    CFG3 #( .INIT(8'h40) )  \READ_DECODE_PROC.prdata_o265_0_a2  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(N_360), .C(N_358), .Y(
        prdata_o265));
    SLE \rate_limit_ref_in_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_ref_in_o[12]));
    SLE \adc_channel_ch3_o[1]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch3_o[1]));
    SLE \rate_limit_slew_cnt_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_slew_cnt_o[10]));
    SLE \seq_cntl_cl_omega_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_seq_cntl_cl_omega_o[14]));
    CFG3 #( .INIT(8'h70) )  \READ_DECODE_PROC.prdata_o277_RNIS9FB7  (
        .A(HALL_INTERFACE_1_omega_out_o[8]), .B(prdata_o277), .C(
        prdata_N_5_mux_i_4_a0_2), .Y(prdata_N_5_mux_i_4_a0_6));
    SLE \pwm_dead_time_val_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_dead_time_val_o[11]));
    SLE \speed_pi_kp_o[1]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_0_sqmuxa_Z), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_speed_pi_kp_o[1]));
    CFG3 #( .INIT(8'h10) )  \prdata_o_1_iv_0_13_0_tz_RNO[12]  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .B(
        prdata_o_1_iv_0_13_tz_RNO_0[12]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .Y(prdata_m2_0_a2_0_16));
    SLE \adc_oc_thresh_o[16]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[16]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_oc_thresh_o[16]));
    CFG3 #( .INIT(8'h01) )  prdata_m2_0_a2_1_0_c (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .C(prdata_m2_2_Z), .Y(
        prdata_m2_0_a2_1_0));
    CFG4 #( .INIT(16'h8000) )  
        \READ_DECODE_PROC.prdata_o276_2_0_RNI202U  (.A(prdata_o277_1_0)
        , .B(HALL_INTERFACE_1_omega_out_o[4]), .C(prdata_o277_2_0), .D(
        prdata_o277_2_1), .Y(prdata_o276_2_0_RNI202U));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_iv_5[7]  (.A(
        SPEED_ID_IQ_PI_0_id_pi_output_o[7]), .B(
        HALL_INTERFACE_1_omega_out_o[7]), .C(prdata_o277), .D(
        prdata_o267), .Y(prdata_o_1_iv_5[7]));
    SLE \speed_pi_ki_o[14]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[14]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_speed_pi_ki_o[14]));
    CFG4 #( .INIT(16'h0001) )  \READ_DECODE_PROC.prdata_o259_2  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[6]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[9]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[10]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[8]), .Y(prdata_o259_2));
    SLE \speed_pi_kp_o[12]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[12]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_0_sqmuxa_Z), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_speed_pi_kp_o[12]));
    SLE \auto_restart_no_o[0]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(auto_restart_no_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_auto_restart_no_o[0]));
    CFG4 #( .INIT(16'h4000) )  \prdata_o_1_iv_0_a2_4[13]  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(
        RATE_LIMITER_0_rl_out_o[13]), .C(N_358), .D(N_360), .Y(N_329));
    SLE \seq_cntl_config_o[2]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(seq_cntl_config_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_seq_cntl_config_o[2]));
    SLE \pwm_delay_time_val_o[5]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_delay_time_val_o[5]));
    CFG4 #( .INIT(16'h0080) )  \prdata_o_1_iv_0_RNO[5]  (.A(N_355), .B(
        N_353), .C(FOC_TRANSFORMS_0_vbeta_o[5]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[7]), .Y(FOC_m3_e_2));
    CFG2 #( .INIT(4'h8) )  \prdata_o_1_0_iv_0_a5_1[0]  (.A(prdata_o263)
        , .B(FOC_TRANSFORMS_0_valpha_o_0), .Y(N_225));
    SLE \seq_cntl_cl_omega_o[4]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_seq_cntl_cl_omega_o[4]));
    CFG4 #( .INIT(16'h0008) )  \READ_DECODE_PROC.prdata_o269_0_a2_0  (
        .A(N_355), .B(READ_m2_e_1_Z), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(N_101), .Y(N_361));
    SLE \olmng_dv_o[13]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[13]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_dv_o[13]));
    SLE \adc_channel_ch1_o[1]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[1]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch1_o[1]));
    CFG4 #( .INIT(16'hECA0) )  \READ_DECODE_PROC.prdata_o267_RNI5OL81  
        (.A(SPEED_ID_IQ_PI_0_id_pi_output_o[17]), .B(
        FOC_TRANSFORMS_0_valpha_o_17), .C(prdata_o267), .D(prdata_o263)
        , .Y(N_145));
    SLE \rate_limit_rate_cnt_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_rate_cnt_o[15]));
    CFG2 #( .INIT(4'h1) )  \READ_DECODE_PROC.prdata_o258_2_0_a2  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[3]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .Y(olmng_dv_o_1_sqmuxa_3));
    CFG4 #( .INIT(16'h0800) )  pwm_gain_val_o_1_sqmuxa_0_a5 (.A(N_375), 
        .B(un3_psel_i), .C(MC_System_0_AMBA_SLAVE_0_PADDR[11]), .D(
        N_367), .Y(pwm_gain_val_o_1_sqmuxa));
    SLE \olmng_theta_factor_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_theta_factor_o[13]));
    SLE \idq_pi_ki_o[8]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_ki_o[8]));
    CFG4 #( .INIT(16'hFFFE) )  \prdata_o_1_iv_14[5]  (.A(
        adc_interface_0_result_ch2_o_m[5]), .B(
        adc_interface_0_result_ch3_o_m[5]), .C(prdata_o_1_iv_8[5]), .D(
        prdata_o_1_iv_9_0[5]), .Y(prdata_o_1_iv_14_0));
    SLE \adc_channel_ch0_o[4]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch0_o[4]));
    CFG2 #( .INIT(4'h4) )  \READ_DECODE_PROC.prdata_o263_5  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[10]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[3]), .Y(prdata_o267_5));
    CFG4 #( .INIT(16'hC0A0) )  \prdata_o_1_iv_10_0_RNO[10]  (.A(
        RATE_LIMITER_0_rl_out_o[10]), .B(OLMNG_0_theta_o[10]), .C(
        prdata_m4_0), .D(MC_System_0_AMBA_SLAVE_0_PADDR[4]), .Y(
        prdata_m2_0_a2_21_0));
    CFG4 #( .INIT(16'hFF80) )  
        \READ_DECODE_PROC.prdata_o269_0_a2_0_RNIHME71  (.A(
        ADC_SCALING_0_ia_adc_o[17]), .B(N_359), .C(N_361), .D(N_409), 
        .Y(N_157));
    CFG4 #( .INIT(16'hFFEC) )  \prdata_o_1_iv_7[7]  (.A(
        SPEED_ID_IQ_PI_0_iq_pi_output_o_7), .B(
        adc_interface_0_result_ch0_o_m[7]), .C(prdata_m2_e_5_6_1), .D(
        prdata_o_1_iv_0[7]), .Y(prdata_o_1_iv_7[7]));
    SLE \olmng_theta_factor_o[17]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[17]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_theta_factor_o[17]));
    CFG3 #( .INIT(8'h80) )  rate_limit_ref_in_o_1_sqmuxa_0_a5 (.A(
        N_398), .B(N_406), .C(N_369), .Y(rate_limit_ref_in_o_1_sqmuxa));
    CFG2 #( .INIT(4'h1) )  speed_pi_kp_o_0_sqmuxa_1_0_0_a2 (.A(N_101), 
        .B(MC_System_0_AMBA_SLAVE_0_PADDR[8]), .Y(N_352));
    CFG4 #( .INIT(16'h153F) )  
        \READ_DECODE_PROC.prdata_o272_0_a2_RNI8O8N  (.A(
        FOC_TRANSFORMS_0_ibeta_o[8]), .B(
        adc_interface_0_result_ch2_o[8]), .C(prdata_o272), .D(
        prdata_o260), .Y(prdata_N_5_mux_i_4_a0_12));
    SLE \olmng_theta_factor_o[5]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[5]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_theta_factor_o[5]));
    SLE \idq_pi_kp_o[4]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_kp_o[4]));
    SLE \adc_channel_ch2_o[4]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch2_o[4]));
    SLE \adc_channel_ch3_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch3_o[12]));
    SLE \hall_speed_factor_o[8]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[8]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(hall_speed_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_hall_if_0_hall_speed_factor_o[8]));
    SLE \speed_pi_ki_o[12]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[12]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_speed_pi_ki_o[12]));
    SLE \pwm_gain_val_o[10]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[10]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_gain_val_o[10]));
    SLE \speed_pi_kp_o[13]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[13]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_0_sqmuxa_Z), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_speed_pi_kp_o[13]));
    SLE \idq_pi_ki_o[10]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[10]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_ki_o[10]));
    SLE \adc_scale_val_o[8]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[8]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_scale_val_o[8]));
    SLE \olmng_iq_ref_in_o[4]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_iq_ref_in_o[4]));
    SLE \adc_channel_ch0_o[0]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch0_o[0]));
    SLE \adc_channel_ch0_o[6]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[6]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch0_o[6]));
    CFG4 #( .INIT(16'hFFF2) )  
        \READ_DECODE_PROC.prdata_o264_0_a2_1_RNIHI4CI  (.A(N_358), .B(
        m5_i_o2_3_1_0), .C(N_403), .D(m5_i_o2_3_2), .Y(N_435_4));
    CFG4 #( .INIT(16'hFFFE) )  \prdata_o_1_iv_12_cZ[7]  (.A(
        FOC_TRANSFORMS_0_ibeta_o_m[7]), .B(prdata_o_1_iv_1[7]), .C(
        adc_interface_0_result_ch2_o_m[7]), .D(prdata_o_1_iv_3[7]), .Y(
        prdata_o_1_iv_12[7]));
    CFG4 #( .INIT(16'h8000) )  adc_channel_ch3_o_1_sqmuxa_0_a5 (.A(
        N_367), .B(N_364), .C(adc_scale_val_o_1_sqmuxa_0_a2_0_0_Z), .D(
        N_365), .Y(adc_channel_ch3_o_1_sqmuxa));
    SLE \adc_channel_ch3_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch3_o[11]));
    SLE \rate_limit_ref_in_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_ref_in_o[0]));
    CFG4 #( .INIT(16'h8000) )  adc_scale_val_o_1_sqmuxa_0_a5 (.A(N_367)
        , .B(N_360), .C(adc_scale_val_o_1_sqmuxa_0_a2_0_0_Z), .D(N_365)
        , .Y(adc_scale_val_o_1_sqmuxa));
    CFG4 #( .INIT(16'hFFEC) )  \prdata_o_1_iv_0_11[14]  (.A(
        FOC_TRANSFORMS_0_ibeta_o[14]), .B(N_313), .C(prdata_o260), .D(
        prdata_o_1_iv_0_6[14]), .Y(prdata_o_1_iv_0_11_2));
    SLE hall_sensor_polarity_o (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(
        hall_sensor_polarity_o_1_sqmuxa), .ALn(MC_System_0_FIC_0_LOCK), 
        .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(GND), .Q(
        apb3_hall_if_0_hall_sensor_polarity_o));
    CFG4 #( .INIT(16'h0080) )  \prdata_o_1_iv_0_a2_1[14]  (.A(N_364), 
        .B(N_358), .C(FOC_TRANSFORMS_0_id_o[14]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .Y(N_313));
    SLE \seq_cntl_cl_omega_o[9]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_seq_cntl_cl_omega_o[9]));
    CFG4 #( .INIT(16'hFFEA) )  \prdata_o_1_0_iv_0_13_cZ[1]  (.A(
        prdata_o_1_0_iv_0_3[1]), .B(prdata_o260), .C(
        FOC_TRANSFORMS_0_ibeta_o[1]), .D(prdata_o_1_0_iv_0_4[1]), .Y(
        prdata_o_1_0_iv_0_14[1]));
    SLE \olmng_dv_o[0]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_dv_o[0]));
    SLE \adc_channel_ch0_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch0_o[12]));
    CFG4 #( .INIT(16'hAAEA) )  \prdata_o_1_0_iv_0_15_2_tz[0]  (.A(
        prdata_N_5_mux_28), .B(N_364), .C(FOC_TRANSFORMS_0_id_o[0]), 
        .D(MC_System_0_AMBA_SLAVE_0_PADDR[2]), .Y(
        prdata_o_1_0_iv_0_15_2_tz[0]));
    SLE \adc_channel_ch2_o[3]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch2_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch2_o[3]));
    SLE \pwm_dead_time_val_o[16]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[16]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_dead_time_val_o[16]));
    CFG2 #( .INIT(4'h1) )  speed_pi_kp_o_0_sqmuxa_0 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[7]), .Y(
        speed_pi_kp_o_0_sqmuxa_0_Z));
    CFG4 #( .INIT(16'h53FF) )  \prdata_o_1_iv_10_1_RNO[10]  (.A(
        ADC_SCALING_0_ib_adc_o[10]), .B(ADC_SCALING_0_ia_adc_o[10]), 
        .C(MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(N_359), .Y(
        prdata_m3_i_0));
    CFG2 #( .INIT(4'h8) )  \READ_DECODE_PROC.prdata_o259_6  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[3]), .Y(prdata_o260_6));
    CFG2 #( .INIT(4'hE) )  \READ_DECODE_PROC.prdata_o257_1_i_o5  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[0]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[1]), .Y(N_101));
    CFG4 #( .INIT(16'h2000) )  \prdata_o_1_iv_0_1_RNO[13]  (.A(
        SPEED_ID_IQ_PI_0_speed_pi_output_o[13]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(prdata_m1_0_a2_1_1));
    SLE \hall_speed_factor_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(hall_speed_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_hall_if_0_hall_speed_factor_o[1]));
    SLE \adc_channel_ch0_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch0_o[11]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_iv_10_7[10]  (.A(
        FOC_TRANSFORMS_0_vbeta_o[10]), .B(
        adc_interface_0_result_ch1_o_9), .C(prdata_N_5_mux_i_3_a0_7_1), 
        .D(prdata_o264), .Y(prdata_o_1_iv_10_7[10]));
    CFG4 #( .INIT(16'h135F) )  
        \READ_DECODE_PROC.prdata_o273_0_a2_RNIQ21R  (.A(
        adc_interface_0_result_ch3_o[3]), .B(
        adc_interface_0_result_ch2_o[3]), .C(prdata_o273), .D(
        prdata_o272), .Y(prdata_m2_e_27_11));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_iv_4[16]  (.A(
        FOC_TRANSFORMS_0_ialpha_o[16]), .B(
        FOC_TRANSFORMS_0_valpha_o_16), .C(prdata_o259), .D(prdata_o263)
        , .Y(prdata_o_1_iv_4[16]));
    CFG4 #( .INIT(16'hF2FF) )  \prdata_o_1_iv_0_5[15]  (.A(
        HALL_INTERFACE_1_theta_output_o[15]), .B(prdata_o276), .C(
        N_308), .D(prdata_o_1_iv_0_5_1[15]), .Y(prdata_o_1_iv_0_5[15]));
    SLE \auto_restart_no_o[3]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(auto_restart_no_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_auto_restart_no_o[3]));
    SLE \adc_channel_ch1_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch1_o[10]));
    CFG4 #( .INIT(16'h4000) )  pwm_dead_time_val_o_1_sqmuxa_0_a2 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[3]), .Y(N_390));
    CFG4 #( .INIT(16'hFEEE) )  \prdata_o_1_iv_0_2[12]  (.A(N_338), .B(
        N_348), .C(FOC_TRANSFORMS_0_valpha_o_12), .D(prdata_o263), .Y(
        prdata_o_1_iv_0_2[12]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_0_iv_0_15_0[0]  (.A(
        SPEED_ID_IQ_PI_0_iq_pi_output_o_0), .B(
        prdata_o_1_0_iv_0_15_2_tz[0]), .C(N_358), .D(prdata_m2_e_5_6_1)
        , .Y(prdata_o_1_0_iv_0_15_0[0]));
    SLE \seq_cntl_cl_omega_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_seq_cntl_cl_omega_o[1]));
    CFG4 #( .INIT(16'h153F) )  
        \READ_DECODE_PROC.prdata_o272_0_a2_RNISN1T  (.A(
        FOC_TRANSFORMS_0_ibeta_o[11]), .B(
        adc_interface_0_result_ch2_o[11]), .C(prdata_o272), .D(
        prdata_o260), .Y(prdata_N_5_mux_i_2_a0_12));
    SLE \rate_limit_slew_cnt_o[9]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_slew_cnt_o[9]));
    SLE \olmng_dv_o[7]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[7]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_dv_o[7]));
    CFG3 #( .INIT(8'h80) )  \READ_DECODE_PROC.prdata_o274_0_a2_0  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[7]), .B(N_355), .C(N_353), .Y(
        N_376));
    CFG3 #( .INIT(8'h37) )  
        \READ_DECODE_PROC.prdata_o276_2_0_1_RNIG9LO6  (.A(
        prdata_m2_0_a2_5_0_Z), .B(N_358), .C(prdata_m2_0_a2_0_Z), .Y(
        prdata_m2_e_27_2));
    SLE \adc_channel_ch3_o[2]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch3_o[2]));
    SLE \idq_pi_ki_o[2]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_ki_o[2]));
    CFG4 #( .INIT(16'h53FF) )  \prdata_o_1_iv_1_RNO[7]  (.A(
        ADC_SCALING_0_ib_adc_o[7]), .B(ADC_SCALING_0_ia_adc_o[7]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(N_359), .Y(
        prdata_m3_i_0_0));
    CFG2 #( .INIT(4'h8) )  pwm_delay_time_val_o_1_sqmuxa_0_a2 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .Y(N_363));
    SLE \adc_scale_val_o[2]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_scale_val_o[2]));
    GND GND_Z (.Y(GND));
    CFG4 #( .INIT(16'h135F) )  
        \READ_DECODE_PROC.prdata_o270_0_a2_RNITH965  (.A(prdata_o270), 
        .B(N_358), .C(adc_interface_0_result_ch0_o[11]), .D(
        FOC_m1_0_a2_1_1_Z), .Y(prdata_N_5_mux_i_2_a0_2));
    CFG4 #( .INIT(16'h0080) )  
        hall_speed_factor_o_1_sqmuxa_0_a2_RNIV0504 (.A(N_364), .B(
        N_358), .C(FOC_TRANSFORMS_0_id_o[5]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .Y(
        FOC_TRANSFORMS_0_id_o_m_0));
    SLE \adc_scale_val_o[3]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_scale_val_o[3]));
    SLE \speed_pi_ki_o[13]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[13]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_speed_pi_ki_o[13]));
    CFG4 #( .INIT(16'h0080) )  FOC_m1_0_a2_1_2 (.A(
        FOC_TRANSFORMS_0_iq_o[3]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(FOC_m1_0_a2_1));
    CFG4 #( .INIT(16'h2000) )  seq_cntl_config_o_1_sqmuxa_0_a5 (.A(
        N_364), .B(N_118), .C(N_365), .D(N_376), .Y(
        seq_cntl_config_o_1_sqmuxa));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_0_1_a0[13]  (.A(
        prdata_o259_1), .B(FOC_TRANSFORMS_0_ialpha_o[13]), .C(
        prdata_o259_2), .D(prdata_o277_1_0), .Y(
        prdata_o_1_iv_0_1_a0[13]));
    CFG4 #( .INIT(16'h0002) )  \prdata_o_1_0_iv_0_15_2_tz_RNO[0]  (.A(
        ADC_SCALING_0_ia_adc_o[0]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(prdata_N_5_mux_28));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_iv_0_3[12]  (.A(
        SPEED_ID_IQ_PI_0_id_pi_output_o[12]), .B(
        HALL_INTERFACE_1_omega_out_o[12]), .C(prdata_o277), .D(
        prdata_o267), .Y(prdata_o_1_iv_0_3[12]));
    SLE \adc_channel_ch1_o[0]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch1_o[0]));
    SLE \seq_cntl_cl_omega_o[6]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(seq_cntl_cl_omega_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_seq_cntl_cl_omega_o[6]));
    SLE \speed_pi_kp_o[16]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[16]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_0_sqmuxa_Z), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_speed_pi_kp_o[16]));
    CFG4 #( .INIT(16'h0010) )  
        \READ_DECODE_PROC.prdata_o264_5_i_o5_RNISAVR1  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[9]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[8]), .C(READ_m3_e_0_Z), .D(
        N_118), .Y(READ_m2_e_2_1));
    CFG3 #( .INIT(8'hC8) )  \prdata_o_1_iv_1[5]  (.A(
        prdata_o_1_iv_18_1[5]), .B(N_358), .C(prdata_m2_0_a2_11_0), .Y(
        prdata_o_1_iv_1[5]));
    CFG3 #( .INIT(8'hFE) )  \prdata_o_1_RNO[18]  (.A(N_157), .B(N_145), 
        .C(N_435_4), .Y(prdata_o_1_RNO[18]));
    SLE \olmng_dv_o[10]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[10]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_dv_o[10]));
    SLE \adc_oc_thresh_o[3]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_oc_thresh_o[3]));
    SLE \adc_oc_thresh_o[14]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[14]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_oc_thresh_o[14]));
    CFG4 #( .INIT(16'h8000) )  adc_oc_thresh_o_1_sqmuxa_0_a5 (.A(N_370)
        , .B(N_360), .C(adc_scale_val_o_1_sqmuxa_0_a2_0_0_Z), .D(N_365)
        , .Y(adc_oc_thresh_o_1_sqmuxa));
    SLE \olmng_iq_ref_in_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_iq_ref_in_o[14]));
    SLE \idq_pi_ki_o[0]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_ki_o[0]));
    CFG3 #( .INIT(8'hF8) )  \prdata_o_1_iv_0_8_cZ[13]  (.A(
        FOC_TRANSFORMS_0_ibeta_o[13]), .B(prdata_o260), .C(
        prdata_o_1_iv_0_6[13]), .Y(prdata_o_1_iv_0_8[13]));
    SLE \pwm_gain_val_o[6]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[6]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_gain_val_o[6]));
    SLE \rate_limit_slew_cnt_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_slew_cnt_o[2]));
    CFG4 #( .INIT(16'h153F) )  
        \READ_DECODE_PROC.prdata_o272_0_a2_RNISB8N  (.A(
        FOC_TRANSFORMS_0_ibeta_o[2]), .B(
        adc_interface_0_result_ch2_o[2]), .C(prdata_o272), .D(
        prdata_o260), .Y(prdata_m2_e_5_11));
    SLE \pwm_dead_time_val_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_dead_time_val_o[3]));
    SLE \rate_limit_slew_cnt_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_slew_cnt_o[1]));
    SLE \pwm_gain_val_o[5]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_gain_val_o[5]));
    CFG4 #( .INIT(16'h4000) )  \prdata_o_1_0_iv_1_a0[3]  (.A(N_101), 
        .B(prdata_o_1_0_iv_1_a0_1[3]), .C(prdata_o_1_0_iv_1_a0_2_0[3]), 
        .D(prdata_o267_5), .Y(prdata_o_1_0_iv_1_a0[3]));
    CFG4 #( .INIT(16'h135F) )  \READ_DECODE_PROC.prdata_o267_RNISPA11  
        (.A(SPEED_ID_IQ_PI_0_id_pi_output_o[4]), .B(
        adc_interface_0_result_ch1_o_3), .C(prdata_o267), .D(
        prdata_N_5_mux_i_3_a0_7_1), .Y(prdata_m2_e_0_5));
    CFG4 #( .INIT(16'hFDEC) )  prdata_m2_e_0_13_tz (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .C(prdata_m2_0_Z), .D(
        prdata_m2_1_Z), .Y(prdata_m2_e_0_13_tz_Z));
    SLE \olmng_theta_factor_o[9]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_theta_factor_o[9]));
    SLE \speed_pi_ki_o[5]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_speed_pi_ki_o[5]));
    SLE \rate_limit_ref_in_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_ref_in_o[10]));
    CFG4 #( .INIT(16'h007F) )  \prdata_o_1_iv_0_12_1[15]  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(prdata_o_1_iv_0_1_1[15])
        , .C(N_358), .D(N_301), .Y(prdata_o_1_iv_0_12_1[15]));
    CFG4 #( .INIT(16'hEAAA) )  \prdata_o_1_iv_0_7_tz[14]  (.A(
        prdata_N_5_mux_24), .B(N_364), .C(FOC_TRANSFORMS_0_iq_o[14]), 
        .D(MC_System_0_AMBA_SLAVE_0_PADDR[2]), .Y(
        prdata_o_1_iv_0_7_tz[14]));
    SLE \olmng_theta_factor_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_theta_factor_o[3]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_0_a5[15]  (.A(
        prdata_o277_1_0), .B(HALL_INTERFACE_1_omega_out_o[15]), .C(
        prdata_o277_2_0), .D(prdata_o277_2_1), .Y(N_220));
    CFG4 #( .INIT(16'h0020) )  \prdata_o_1_iv_0_7_tz_RNO[14]  (.A(
        ADC_SCALING_0_ib_adc_o[14]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(prdata_N_5_mux_24));
    CFG4 #( .INIT(16'hDC50) )  \prdata_o_1_iv_0_1[14]  (.A(prdata_o276)
        , .B(N_358), .C(HALL_INTERFACE_1_theta_output_o[14]), .D(
        prdata_o_1_iv_0_7_tz[14]), .Y(prdata_o_1_iv_0_1[14]));
    CFG4 #( .INIT(16'hEC00) )  
        hall_speed_factor_o_1_sqmuxa_0_a2_RNIBDKE5 (.A(
        prdata_m2_i_a3_1_0_Z), .B(OLMNG_N_5_mux_1), .C(N_364), .D(
        N_358), .Y(hall_speed_factor_o_1_sqmuxa_0_a2_RNIBDKE5_Z));
    CFG3 #( .INIT(8'h80) )  speed_pi_kp_o_0_sqmuxa_1 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[6]), .B(
        speed_pi_kp_o_0_sqmuxa_0_Z), .C(N_367), .Y(
        speed_pi_kp_o_0_sqmuxa_1_Z));
    SLE \idq_pi_kp_o[0]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_kp_o[0]));
    SLE \adc_channel_ch1_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch1_o[15]));
    CFG4 #( .INIT(16'hAAEA) )  
        hall_speed_factor_o_1_sqmuxa_0_a2_RNIGFII2 (.A(m7_N_5_mux), .B(
        N_364), .C(FOC_TRANSFORMS_0_id_o[17]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .Y(m5_N_6_mux_i_0));
    SLE \pwm_period_val_o[3]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[3]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_period_val_o[3]));
    SLE \speed_pi_kp_o[5]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_0_sqmuxa_Z), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_speed_pi_kp_o[5]));
    SLE \speed_pi_ki_o[8]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[8]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_speed_pi_ki_o[8]));
    SLE \olmng_dv_o[11]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[11]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_dv_o[11]));
    SLE \hall_speed_factor_o[16]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[16]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(hall_speed_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_hall_if_0_hall_speed_factor_o[16]));
    CFG2 #( .INIT(4'h7) )  pwm_period_val_o_1_sqmuxa_8_0_a5_RNISD05 (
        .A(pwm_period_val_o_1_sqmuxa_8), .B(
        SPEED_ID_IQ_PI_0_id_pi_output_o[9]), .Y(
        pwm_period_val_o_1_sqmuxa_8_0_a5_RNISD05_Z));
    SLE \pwm_delay_time_val_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_delay_time_val_o[3]));
    SLE \speed_pi_ki_o[16]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[16]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_speed_pi_ki_o[16]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_iv_2[5]  (.A(prdata_o275), 
        .B(N_358), .C(HALL_INTERFACE_1_angle_out_raw_o[5]), .D(
        prdata_o_1_iv_9_tz[5]), .Y(prdata_o_1_iv_2[5]));
    CFG4 #( .INIT(16'h0080) )  \prdata_o_1_0_iv_0_8_tz_RNO[1]  (.A(
        FOC_TRANSFORMS_0_iq_o[1]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(prdata_N_5_mux_17));
    SLE \pwm_delay_time_val_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_delay_time_val_o[14]));
    SLE \adc_oc_thresh_o[11]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[11]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_oc_thresh_o[11]));
    CFG4 #( .INIT(16'h4000) )  \READ_DECODE_PROC.prdata_o271_0_a2  (.A(
        N_101), .B(N_363), .C(READ_m2_e_2_1), .D(N_355), .Y(
        prdata_N_5_mux_i_3_a0_7_1));
    SLE \pwm_period_val_o[8]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[8]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_period_val_o[8]));
    CFG4 #( .INIT(16'h23AF) )  
        \READ_DECODE_PROC.prdata_o270_0_a2_RNINSKL6  (.A(
        prdata_m2_e_4_9_tz), .B(adc_interface_0_result_ch0_o[8]), .C(
        N_358), .D(prdata_o270), .Y(prdata_N_5_mux_i_4_a0_2));
    SLE \idq_pi_kp_o[2]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_kp_o[2]));
    CFG4 #( .INIT(16'hFEFC) )  
        \READ_DECODE_PROC.prdata_o259_2_RNID5HC7  (.A(m7_m1_0_a2_1_Z), 
        .B(N_425), .C(N_404), .D(N_358), .Y(m5_i_o2_3_2));
    SLE \olmng_dv_o[17]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[17]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_dv_o[17]));
    SLE \hall_speed_factor_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(hall_speed_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_hall_if_0_hall_speed_factor_o[10]));
    SLE \adc_oc_thresh_o[8]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[8]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_oc_thresh_o[8]));
    CFG3 #( .INIT(8'h40) )  adc_scale_val_o_1_sqmuxa_0_a2_0_0 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[7]), .B(N_355), .C(N_353), .Y(
        adc_scale_val_o_1_sqmuxa_0_a2_0_0_Z));
    SLE \pwm_period_val_o[12]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[12])
        , .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_period_val_o[12]));
    CFG4 #( .INIT(16'h153F) )  
        \READ_DECODE_PROC.prdata_o271_0_a2_RNILFH24  (.A(
        FOC_TRANSFORMS_0_vbeta_o[8]), .B(
        adc_interface_0_result_ch1_o_7), .C(prdata_N_5_mux_i_3_a0_7_1), 
        .D(prdata_o264), .Y(prdata_N_5_mux_i_4_a0_7));
    SLE \pwm_dead_time_val_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_dead_time_val_o[12]));
    SLE \pwm_period_val_o[2]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_period_val_o[2]));
    CFG3 #( .INIT(8'hF8) )  \prdata_o_1_iv_10_4[10]  (.A(
        FOC_TRANSFORMS_0_valpha_o_10), .B(prdata_o263), .C(
        prdata_o_1_iv_10_1[10]), .Y(prdata_o_1_iv_10_4[10]));
    SLE \rate_limit_slew_cnt_o[4]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[4]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_slew_cnt_o[4]));
    SLE \adc_channel_ch1_o[9]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[9]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch1_o[9]));
    CFG4 #( .INIT(16'hFFFE) )  \prdata_o_1_iv_14[7]  (.A(
        FOC_TRANSFORMS_0_iq_o_m[7]), .B(
        SPEED_ID_IQ_PI_0_speed_pi_output_o_m[7]), .C(
        adc_interface_0_result_ch3_o_m[7]), .D(prdata_o_1_iv_7[7]), .Y(
        prdata_o_1_iv_14_2));
    SLE \adc_oc_thresh_o[17]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[17]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_oc_thresh_o[17]));
    SLE \rate_limit_rate_cnt_o[9]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_rate_cnt_o[9]));
    SLE \seq_cntl_config_o[0]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(seq_cntl_config_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_seq_cntl_config_o[0]));
    CFG4 #( .INIT(16'hAC00) )  prdata_m2_0_a2_5_0 (.A(
        SPEED_ID_IQ_PI_0_speed_pi_output_o[3]), .B(
        ADC_SCALING_0_ib_adc_o[3]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .D(m5_m2_0_a2_0_Z), .Y(
        prdata_m2_0_a2_5_0_Z));
    CFG2 #( .INIT(4'h8) )  \READ_DECODE_PROC.prdata_o268_0_a2_RNIK92E  
        (.A(prdata_m2_e_5_6_1), .B(SPEED_ID_IQ_PI_0_iq_pi_output_o_17), 
        .Y(N_409));
    SLE \pwm_period_val_o[13]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[13])
        , .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_period_val_o[13]));
    SLE \adc_control_reg_val_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_control_reg_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_control_reg_val_o[0]));
    SLE \speed_pi_kp_o[11]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[11]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_0_sqmuxa_Z), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_speed_pi_kp_o[11]));
    CFG2 #( .INIT(4'h2) )  start_motor_o_1_sqmuxa_0_a2 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[3]), .Y(N_370));
    CFG4 #( .INIT(16'h0080) )  \prdata_o_1_iv_0_a2_1[12]  (.A(N_364), 
        .B(N_358), .C(FOC_TRANSFORMS_0_id_o[12]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .Y(N_339));
    SLE \adc_oc_thresh_o[10]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[10]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_oc_thresh_o[10]));
    CFG4 #( .INIT(16'h8000) )  seq_cntl_cl_omega_o_1_sqmuxa_0_a5 (.A(
        N_373), .B(N_360), .C(N_376), .D(N_365), .Y(
        seq_cntl_cl_omega_o_1_sqmuxa));
    CFG2 #( .INIT(4'h1) )  adc_scale_val_o_1_sqmuxa_0_a2 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[3]), .Y(N_367));
    SLE \olmng_iq_ref_in_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_iq_ref_in_o[12]));
    CFG4 #( .INIT(16'hEAAA) )  \prdata_o_1_iv_9_tz[5]  (.A(
        SPEED_N_5_mux_1), .B(N_364), .C(FOC_TRANSFORMS_0_iq_o[5]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .Y(prdata_o_1_iv_9_tz[5]));
    CFG4 #( .INIT(16'h4000) )  \prdata_o_1_iv_0_a2_4[15]  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(
        RATE_LIMITER_0_rl_out_o[15]), .C(N_358), .D(N_360), .Y(N_303));
    CFG3 #( .INIT(8'h07) )  \prdata_o_1_iv_9_1[16]  (.A(
        HALL_INTERFACE_1_angle_out_raw_o[16]), .B(prdata_o275), .C(
        prdata_o_1_iv_4[16]), .Y(prdata_o_1_iv_9_1[16]));
    CFG4 #( .INIT(16'hFFFE) )  \prdata_o_1_iv_6[16]  (.A(
        prdata_o_1_iv_6_a0[16]), .B(prdata_o_1_iv_1[16]), .C(
        prdata_o_1_iv_13_a1[16]), .D(FOC_TRANSFORMS_0_vbeta_o_m[16]), 
        .Y(prdata_o_1_iv_6[16]));
    CFG4 #( .INIT(16'h8000) )  
        \READ_DECODE_PROC.prdata_o259_2_RNI5RNT  (.A(prdata_o259_1), 
        .B(FOC_TRANSFORMS_0_ialpha_o[3]), .C(prdata_o259_2), .D(
        prdata_o277_1_0), .Y(FOC_TRANSFORMS_0_ialpha_o_m[3]));
    SLE \adc_channel_ch1_o[13]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[13]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch1_o[13]));
    CFG4 #( .INIT(16'hDC50) )  \prdata_o_1_iv_0_1[13]  (.A(prdata_o276)
        , .B(N_358), .C(HALL_INTERFACE_1_theta_output_o[13]), .D(
        prdata_m1_0_a2_1_1), .Y(prdata_o_1_iv_0_1[13]));
    CFG4 #( .INIT(16'hEC00) )  
        hall_speed_factor_o_1_sqmuxa_0_a2_RNIFHKE5 (.A(
        prdata_m2_i_a3_2_0_Z), .B(OLMNG_N_5_mux_2), .C(N_364), .D(
        N_358), .Y(hall_speed_factor_o_1_sqmuxa_0_a2_RNIFHKE5_Z));
    SLE \adc_oc_thresh_o[6]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[6]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_oc_thresh_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_oc_thresh_o[6]));
    CFG2 #( .INIT(4'h4) )  seq_cntl_cl_omega_o_1_sqmuxa_0_a2_0 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[3]), .Y(N_373));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_o_1_iv_6[7]  (.A(
        FOC_TRANSFORMS_0_vbeta_o[7]), .B(
        adc_interface_0_result_ch1_o_6), .C(prdata_N_5_mux_i_3_a0_7_1), 
        .D(prdata_o264), .Y(prdata_o_1_iv_6[7]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_14_RNO_0[5]  (.A(
        adc_interface_0_result_ch3_o[5]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .C(N_370), .D(N_375), .Y(
        adc_interface_0_result_ch3_o_m[5]));
    SLE \pwm_period_val_o[11]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[11])
        , .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_period_val_o[11]));
    SLE \speed_pi_kp_o[4]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[4]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_0_sqmuxa_Z), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_speed_pi_kp_o[4]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_iv_0_4[15]  (.A(
        SPEED_ID_IQ_PI_0_id_pi_output_o[15]), .B(
        FOC_TRANSFORMS_0_valpha_o_15), .C(prdata_o267), .D(prdata_o263)
        , .Y(prdata_o_1_iv_0_4[15]));
    SLE \rate_limit_ref_in_o[3]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_ref_in_o[3]));
    SLE \adc_channel_ch0_o[9]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[9]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch0_o[9]));
    SLE \speed_pi_kp_o[2]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_0_sqmuxa_Z), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_speed_pi_kp_o[2]));
    SLE \rate_limit_slew_cnt_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_slew_cnt_o[14]));
    SLE \adc_scale_val_o[10]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[10]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_scale_val_o[10]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_0_iv_0_a2_3[0]  (.A(
        adc_interface_0_result_ch3_o[0]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .C(N_370), .D(N_375), .Y(
        N_286));
    CFG4 #( .INIT(16'h8000) )  pwm_period_val_o_1_sqmuxa_0_a5 (.A(
        N_370), .B(N_363), .C(N_365), .D(
        adc_scale_val_o_1_sqmuxa_0_a2_0_0_Z), .Y(
        pwm_period_val_o_1_sqmuxa));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_6_RNO[16]  (.A(N_353), 
        .B(prdata_o264_0_a2_1), .C(FOC_TRANSFORMS_0_vbeta_o[16]), .D(
        READ_m2_e_3_1_0_Z), .Y(FOC_TRANSFORMS_0_vbeta_o_m[16]));
    SLE \pwm_dead_time_val_o[17]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[17]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_dead_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_dead_time_val_o[17]));
    CFG3 #( .INIT(8'h02) )  idq_pi_kp_o_1_sqmuxa_1 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[6]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[8]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[7]), .Y(
        idq_pi_kp_o_1_sqmuxa_1_Z));
    SLE \hall_filter_factor_o[1]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(hall_filter_factor_o_1_sqmuxa_Z), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_hall_if_0_hall_filter_factor_o[1]));
    SLE \speed_pi_ki_o[11]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[11]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_ki_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_speed_pi_ki_o[11]));
    CFG4 #( .INIT(16'h153F) )  \READ_DECODE_PROC.prdata_o277_RNI7HP94  
        (.A(HALL_INTERFACE_1_omega_out_o[6]), .B(
        FOC_TRANSFORMS_0_vbeta_o[6]), .C(prdata_o264), .D(prdata_o277), 
        .Y(prdata_o277_RNI7HP94));
    CFG4 #( .INIT(16'h0040) )  rate_limit_ref_in_o_1_sqmuxa_0_a2 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[3]), .Y(N_406));
    SLE \rate_limit_slew_cnt_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_slew_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_slew_cnt_o[11]));
    CFG4 #( .INIT(16'h0080) )  \prdata_o_1_iv_0_a2[12]  (.A(N_359), .B(
        N_358), .C(ADC_SCALING_0_ia_adc_o[12]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .Y(N_337));
    SLE \olmng_dv_o[1]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[1]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_dv_o[1]));
    CFG4 #( .INIT(16'hFFEC) )  \prdata_o_1_iv_0_9_cZ[14]  (.A(
        OLMNG_0_theta_o[14]), .B(prdata_o_1_iv_0_4[14]), .C(
        prdata_o_1_0_iv_0_15_3_1[0]), .D(prdata_o_1_iv_0_5[14]), .Y(
        prdata_o_1_iv_0_9[14]));
    CFG2 #( .INIT(4'h7) )  \READ_DECODE_PROC.prdata_o264_5_i_o5  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[3]), .Y(N_118));
    SLE \hall_speed_factor_o[15]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[15]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(hall_speed_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_hall_if_0_hall_speed_factor_o[15]));
    SLE \idq_pi_kp_o[15]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[15]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(idq_pi_kp_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_idq_pi_kp_o[15]));
    SLE \olmng_dv_o[14]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[14]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_dv_o[14]));
    CFG4 #( .INIT(16'h135F) )  
        \READ_DECODE_PROC.prdata_o270_0_a2_RNIB18K5  (.A(prdata_o270), 
        .B(N_358), .C(adc_interface_0_result_ch0_o[9]), .D(
        FOC_m1_0_a2_0_1_Z), .Y(prdata_N_5_mux_i_1_a0_2));
    CFG4 #( .INIT(16'h135F) )  \prdata_o_1_iv_0_5_1[14]  (.A(
        SPEED_ID_IQ_PI_0_id_pi_output_o[14]), .B(
        HALL_INTERFACE_1_angle_out_raw_o[14]), .C(prdata_o267), .D(
        prdata_o275), .Y(prdata_o_1_iv_0_5_1[14]));
    CFG4 #( .INIT(16'hF3F5) )  prdata_m2_e_17_1 (.A(
        ADC_SCALING_0_ia_adc_o[3]), .B(FOC_TRANSFORMS_0_id_o[3]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .Y(prdata_m2_e_17_1_Z));
    SLE \rate_limit_ref_in_o[6]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[6]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_ref_in_o[6]));
    SLE \pwm_delay_time_val_o[16]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[16]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_delay_time_val_o[16]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_0_a2_9[14]  (.A(N_353), 
        .B(prdata_o264_0_a2_1), .C(FOC_TRANSFORMS_0_vbeta_o[14]), .D(
        READ_m2_e_3_1_0_Z), .Y(N_321));
    CFG2 #( .INIT(4'h1) )  \READ_DECODE_PROC.prdata_o258_0_a2_0  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .Y(N_359));
    SLE \speed_pi_kp_o[0]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(speed_pi_kp_o_0_sqmuxa_Z), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_speed_pi_kp_o[0]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_0_a2_2[15]  (.A(N_359), 
        .B(N_358), .C(ADC_SCALING_0_ib_adc_o[15]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .Y(N_301));
    CFG4 #( .INIT(16'hECA0) )  \prdata_o_1_iv_3[7]  (.A(
        FOC_TRANSFORMS_0_ialpha_o[7]), .B(FOC_TRANSFORMS_0_valpha_o_7), 
        .C(prdata_o259), .D(prdata_o263), .Y(prdata_o_1_iv_3[7]));
    CFG4 #( .INIT(16'hFFFE) )  \prdata_o_1_iv_0_6[14]  (.A(
        prdata_o_1_iv_0_6_a0[14]), .B(prdata_o_1_iv_0_1[14]), .C(
        prdata_o_1_iv_0_13_a1[14]), .D(N_321), .Y(
        prdata_o_1_iv_0_6[14]));
    CFG4 #( .INIT(16'h135F) )  \prdata_o_1_iv_5_1[16]  (.A(
        SPEED_m1_0_a2_1), .B(SPEED_ID_IQ_PI_0_id_pi_output_o[16]), .C(
        N_358), .D(prdata_o267), .Y(prdata_o_1_iv_5_1[16]));
    SLE \hall_speed_factor_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(hall_speed_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_hall_if_0_hall_speed_factor_o[12]));
    CFG3 #( .INIT(8'h40) )  \READ_DECODE_PROC.prdata_o257_0_a2  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(N_359), .C(N_358), .Y(
        prdata_o257));
    CFG4 #( .INIT(16'hAC00) )  prdata_m1_0_a2_0_0_0 (.A(
        OLMNG_0_theta_o[2]), .B(RATE_LIMITER_0_rl_out_o[2]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(prdata_m1_0_a2_0_0));
    CFG2 #( .INIT(4'h2) )  m5_m2_0_a2_0 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .Y(m5_m2_0_a2_0_Z));
    CFG2 #( .INIT(4'h2) )  seq_cntl_cl_omega_o_1_sqmuxa_0_a2 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .Y(N_360));
    CFG4 #( .INIT(16'hC0A0) )  \prdata_o_1_iv_1_RNO[5]  (.A(
        RATE_LIMITER_0_rl_out_o[5]), .B(OLMNG_0_theta_o[5]), .C(
        prdata_m4_0), .D(MC_System_0_AMBA_SLAVE_0_PADDR[4]), .Y(
        prdata_m2_0_a2_11_0));
    CFG3 #( .INIT(8'h20) )  \prdata_o_1_iv_6_a0_0[16]  (.A(
        SPEED_ID_IQ_PI_0_iq_pi_output_o_16), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(
        prdata_o_1_iv_6_a0_0[16]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_0_13_a1[14]  (.A(
        prdata_o277_1_0), .B(HALL_INTERFACE_1_omega_out_o[14]), .C(
        prdata_o277_2_0), .D(prdata_o277_2_1), .Y(
        prdata_o_1_iv_0_13_a1[14]));
    CFG2 #( .INIT(4'h8) )  \READ_DECODE_PROC.prdata_o263_RNIQK5Q  (.A(
        prdata_o263), .B(FOC_TRANSFORMS_0_valpha_o_11), .Y(
        FOC_TRANSFORMS_0_valpha_o_m_5));
    SLE \hall_speed_factor_o[11]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[11]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(hall_speed_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_hall_if_0_hall_speed_factor_o[11]));
    SLE \pwm_period_val_o[14]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[14])
        , .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_period_val_o[14]));
    CFG4 #( .INIT(16'h8000) )  start_motor_o_1_sqmuxa_0_a5 (.A(N_370), 
        .B(N_364), .C(N_376), .D(N_365), .Y(start_motor_o_1_sqmuxa));
    SLE \pwm_delay_time_val_o[9]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[9]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(pwm_delay_time_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_delay_time_val_o[9]));
    SLE \adc_scale_val_o[12]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[12]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_scale_val_o[12]));
    CFG2 #( .INIT(4'h8) )  
        \READ_DECODE_PROC.prdata_o268_0_a2_RNIUJHC5  (.A(
        prdata_m2_e_0_6), .B(prdata_m2_e_0_5), .Y(prdata_m2_e_0_8));
    SLE \olmng_theta_factor_o[2]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[2]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_theta_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_theta_factor_o[2]));
    SLE \pwm_period_val_o[9]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[9]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_period_val_o[9]));
    CFG4 #( .INIT(16'h007F) )  
        seq_cntl_cl_omega_o_1_sqmuxa_0_a2_RNI8G7Q2 (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(
        SPEED_ID_IQ_PI_0_speed_pi_output_o[8]), .C(N_360), .D(
        ADC_N_5_mux), .Y(prdata_m2_e_4_9_tz));
    SLE \pwm_period_val_o[5]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[5]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_period_val_o[5]));
    CFG4 #( .INIT(16'hEAAA) )  \prdata_o_1_iv_9_tz[10]  (.A(
        SPEED_N_5_mux_2), .B(N_364), .C(FOC_TRANSFORMS_0_iq_o[10]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .Y(prdata_o_1_iv_9_tz[10]));
    CFG4 #( .INIT(16'h135F) )  \READ_DECODE_PROC.prdata_o259_RNICGAK1  
        (.A(FOC_TRANSFORMS_0_ialpha_o[8]), .B(
        SPEED_ID_IQ_PI_0_iq_pi_output_o_8), .C(prdata_o259), .D(
        prdata_m2_e_5_6_1), .Y(prdata_N_5_mux_i_4_a0_11_1));
    SLE \adc_channel_ch3_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch3_o[10]));
    CFG4 #( .INIT(16'h0080) )  \prdata_o_1_iv_11_RNO[16]  (.A(N_364), 
        .B(N_358), .C(FOC_TRANSFORMS_0_id_o[16]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .Y(
        FOC_TRANSFORMS_0_id_o_m[16]));
    SLE \hall_speed_factor_o[0]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[0]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(hall_speed_factor_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_hall_if_0_hall_speed_factor_o[0]));
    CFG4 #( .INIT(16'h0400) )  
        \READ_DECODE_PROC.prdata_o275_0_a2_N_2L1  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[6]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[9]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[10]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[8]), .Y(prdata_o275_0_a2_N_2L1));
    CFG4 #( .INIT(16'h0080) )  \prdata_o_1_iv_0_a2_1[13]  (.A(N_364), 
        .B(N_358), .C(FOC_TRANSFORMS_0_id_o[13]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .Y(N_326));
    CFG3 #( .INIT(8'h7F) )  prdata_N_5_mux_i_1_a0_9_N_2L1 (.A(
        OLMNG_0_theta_o[9]), .B(MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(
        prdata_N_5_mux_i_1_a0_9_N_2L1_Z));
    CFG3 #( .INIT(8'h40) )  \READ_DECODE_PROC.prdata_o261_0_a2  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .B(N_364), .C(N_358), .Y(
        prdata_o261));
    SLE \rate_limit_ref_in_o[14]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[14]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_ref_in_o[14]));
    CFG4 #( .INIT(16'h8000) )  \READ_DECODE_PROC.prdata_o277_2_1  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[9]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[8]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[3]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .Y(prdata_o277_2_1));
    CFG4 #( .INIT(16'h4C00) )  
        \READ_DECODE_PROC.prdata_o273_0_a2_RNIK5NGB  (.A(prdata_o273), 
        .B(prdata_m2_e_5_2), .C(adc_interface_0_result_ch3_o[2]), .D(
        prdata_m2_e_5_9), .Y(prdata_m2_e_5_10));
    CFG4 #( .INIT(16'h8000) )  
        \READ_DECODE_PROC.prdata_o264_0_a2_1_RNIBTBC2  (.A(N_353), .B(
        prdata_o264_0_a2_1), .C(FOC_TRANSFORMS_0_vbeta_o[3]), .D(
        READ_m2_e_3_1_0_Z), .Y(FOC_TRANSFORMS_0_vbeta_o_m[3]));
    SLE \adc_channel_ch3_o[9]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[9]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch3_o[9]));
    SLE \adc_scale_val_o[15]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[15]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_scale_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_scale_val_o[15]));
    SLE \adc_channel_ch0_o[10]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[10]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(adc_channel_ch0_o_1_sqmuxa), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_adc_channel_ch0_o[10]));
    CFG3 #( .INIT(8'h35) )  prdata_m2_5 (.A(ADC_SCALING_0_ia_adc_o[6]), 
        .B(RATE_LIMITER_0_rl_out_o[6]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(prdata_m2_5_Z));
    SLE \olmng_iq_ref_in_o[7]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[7]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(olmng_iq_ref_in_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_olmng_iq_ref_in_o[7]));
    CFG4 #( .INIT(16'hFFEC) )  \prdata_o_1_iv_11_cZ[16]  (.A(
        FOC_TRANSFORMS_0_ibeta_o[16]), .B(FOC_TRANSFORMS_0_id_o_m[16]), 
        .C(prdata_o260), .D(prdata_o_1_iv_6[16]), .Y(
        prdata_o_1_iv_11[16]));
    SLE \adc_channel_ch3_o[6]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[6]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch3_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch3_o[6]));
    CFG4 #( .INIT(16'h7000) )  
        \READ_DECODE_PROC.prdata_o260_0_a2_RNIHKC5J  (.A(
        FOC_TRANSFORMS_0_ibeta_o[4]), .B(prdata_o260), .C(
        prdata_m2_e_0_3), .D(prdata_m2_e_0_4), .Y(prdata_m2_e_0_10));
    CFG4 #( .INIT(16'h8000) )  
        \READ_DECODE_PROC.prdata_o276_2_0_RNI752U  (.A(prdata_o277_1_0)
        , .B(HALL_INTERFACE_1_omega_out_o[9]), .C(prdata_o277_2_0), .D(
        prdata_o277_2_1), .Y(HALL_INTERFACE_1_omega_out_o_m[9]));
    CFG2 #( .INIT(4'h8) )  \READ_DECODE_PROC.prdata_o272_0_a2  (.A(
        N_375), .B(N_371), .Y(prdata_o272));
    CFG4 #( .INIT(16'h153F) )  
        \READ_DECODE_PROC.prdata_o272_0_a2_RNI4K8N  (.A(
        FOC_TRANSFORMS_0_ibeta_o[6]), .B(
        adc_interface_0_result_ch2_o[6]), .C(prdata_o272), .D(
        prdata_o260), .Y(prdata_N_5_mux_i_3_a0_12));
    SLE \pwm_period_val_o[0]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[0]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_period_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_period_val_o[0]));
    SLE \pwm_gain_val_o[13]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[13]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(pwm_gain_val_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_pwm_gain_val_o[13]));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_14_RNO_1[7]  (.A(
        adc_interface_0_result_ch3_o[7]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[11]), .C(N_370), .D(N_375), .Y(
        adc_interface_0_result_ch3_o_m[7]));
    CFG4 #( .INIT(16'h0080) )  \prdata_o_1_iv_0_a2[13]  (.A(N_359), .B(
        N_358), .C(ADC_SCALING_0_ia_adc_o[13]), .D(
        MC_System_0_AMBA_SLAVE_0_PADDR[2]), .Y(N_324));
    CFG3 #( .INIT(8'h1D) )  \prdata_o_1_iv_1_RNO_0[16]  (.A(
        ADC_SCALING_0_ib_adc_o[16]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[4]), .C(
        FOC_TRANSFORMS_0_iq_o[16]), .Y(prdata_o_1_iv_1_RNO_0[16]));
    CFG2 #( .INIT(4'h1) )  \READ_DECODE_PROC.prdata_o276_2_0_1  (.A(
        MC_System_0_AMBA_SLAVE_0_PADDR[10]), .B(
        MC_System_0_AMBA_SLAVE_0_PADDR[6]), .Y(N_355));
    CFG4 #( .INIT(16'h8000) )  \prdata_o_1_iv_10_RNO[5]  (.A(
        prdata_o277_1_0), .B(HALL_INTERFACE_1_omega_out_o[5]), .C(
        prdata_o277_2_0), .D(prdata_o277_2_1), .Y(
        HALL_INTERFACE_1_omega_out_o_m[5]));
    CFG4 #( .INIT(16'h2000) )  adc_channel_ch2_o_1_sqmuxa_0_a5 (.A(
        N_359), .B(N_118), .C(N_365), .D(
        adc_scale_val_o_1_sqmuxa_0_a2_0_0_Z), .Y(
        adc_channel_ch2_o_1_sqmuxa));
    SLE \adc_channel_ch1_o[2]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[2]), 
        .CLK(MC_System_0_FIC_0_CLK), .EN(adc_channel_ch1_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_adc_channel_ch1_o[2]));
    SLE \olmng_dv_o[3]  (.D(MC_System_0_AMBA_SLAVE_0_PWDATA[3]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(olmng_dv_o_1_sqmuxa_Z), .ALn(
        MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), .LAT(
        GND), .Q(apb3_en_if_1_olmng_dv_o[3]));
    SLE \rate_limit_rate_cnt_o[12]  (.D(
        MC_System_0_AMBA_SLAVE_0_PWDATA[12]), .CLK(
        MC_System_0_FIC_0_CLK), .EN(rate_limit_rate_cnt_o_1_sqmuxa), 
        .ALn(MC_System_0_FIC_0_LOCK), .ADn(VCC), .SLn(VCC), .SD(GND), 
        .LAT(GND), .Q(apb3_en_if_1_rate_limit_rate_cnt_o[12]));
    CFG3 #( .INIT(8'h35) )  prdata_m2_3 (.A(ADC_SCALING_0_ia_adc_o[11])
        , .B(RATE_LIMITER_0_rl_out_o[11]), .C(
        MC_System_0_AMBA_SLAVE_0_PADDR[5]), .Y(prdata_m2_3_Z));
    
endmodule


module BLDC_HALL_Axis(
       HALL_INTERFACE_1_omega_out_o_0,
       SPEED_ID_IQ_PI_0_id_pi_output_o_0,
       SPEED_ID_IQ_PI_0_iq_pi_output_o_9,
       SEQ_CONTROLLER_0_state_o_0,
       SEQ_CONTROLLER_0_state_o_2,
       FOC_TRANSFORMS_0_valpha_o_2,
       FOC_TRANSFORMS_0_ialpha_o_0,
       FOC_TRANSFORMS_0_ibeta_o_0,
       adc_interface_0_result_ch0_o_0,
       adc_interface_0_result_ch1_o_0,
       adc_interface_0_result_ch1_o_2,
       MC_System_0_AMBA_SLAVE_0_PWDATA,
       MC_System_0_AMBA_SLAVE_0_PRDATA,
       prdata_o_1_iv_10_13,
       prdata_o_1_iv_9,
       prdata_o_1_0_iv_0_13,
       prdata_o_1_iv_10_11,
       MC_System_0_AMBA_SLAVE_0_PADDR,
       FOC_TRANSFORMS_0_ialpha_o_m,
       FOC_TRANSFORMS_0_valpha_o_m_0,
       FOC_TRANSFORMS_0_valpha_o_m_5,
       adc_interface_0_result_ch3_o_m,
       FOC_TRANSFORMS_0_id_o_m,
       prdata_o_1_iv_0_6,
       prdata_o_1_iv_0_10,
       prdata_o_1_0_iv_0_14,
       prdata_o_1_iv_10,
       prdata_o_1_iv_0_7_0,
       prdata_o_1_iv_13,
       prdata_o_1_iv_12,
       prdata_o_1_iv_10_0,
       prdata_o_1_iv_0_9,
       prdata_o_1_iv_0_7,
       prdata_o_1_iv_10_12,
       prdata_o_1_0_iv_0_15,
       prdata_o_1_iv_0_12_2,
       prdata_o_1_iv_0_12_0,
       prdata_o_1_iv_0_8,
       prdata_o_1_iv_14_2,
       prdata_o_1_iv_14_0,
       prdata_o_1_iv_0_11_0,
       prdata_o_1_iv_0_11_2,
       prdata_o_1_iv_0_11_3,
       prdata_o_1_iv_11,
       MC_System_0_FIC_0_LOCK,
       MC_System_0_FIC_0_CLK,
       A0_PWM_VL_O_c,
       A0_PWM_UH_O_c,
       A0_PWM_VH_O_c,
       A0_PWM_WH_O_c,
       HA_i_c,
       HB_i_c,
       HC_i_c,
       N_358,
       prdata_o277,
       prdata_o267,
       prdata_N_5_mux_i_3_a0_7_1,
       prdata_N_5_mux_i_3_a0_10,
       prdata_o263,
       prdata_N_5_mux_i_1_a0_13,
       N_435_4,
       prdata_N_5_mux_i_2_a0_11,
       prdata_o259,
       prdata_m2_e_5_6_1,
       prdata_N_5_mux_i_4_a0_11,
       prdata_o274,
       prdata_m2_e_27_10,
       prdata_m2_0_a2_1_0,
       prdata_m2_0_a2_17_0,
       prdata_o270,
       MC_System_0_AMBA_SLAVE_0_PSELx,
       MC_System_0_AMBA_SLAVE_0_PWRITE,
       MC_System_0_AMBA_SLAVE_0_PENABLE,
       N_296,
       prdata_o260,
       N_225,
       prdata_m2_e_5_1,
       prdata_N_5_mux_i_3_a0_4,
       prdata_N_5_mux_i_3_a0_0,
       prdata_N_5_mux_i_2_a0_4,
       prdata_N_5_mux_i_2_a0_0,
       N_286,
       N_283,
       prdata_m2_e_5_11,
       prdata_m2_e_5_6,
       prdata_m2_e_5_4,
       prdata_m2_e_27_11,
       prdata_m2_e_0_9,
       prdata_N_5_mux_i_4_a0_12,
       prdata_N_5_mux_i_3_a0_12,
       prdata_N_5_mux_i_1_a0_12,
       prdata_N_5_mux_i_2_a0_12,
       m7_i_2,
       prdata_m2_e_0_8,
       prdata_N_5_mux_i_2_a0_10,
       N_157,
       prdata_m2_e_5_10,
       prdata_m2_e_27_12,
       prdata_m2_e_0_10,
       prdata_N_5_mux_i_4_a0_13,
       prdata_N_5_mux_i_3_a0_11,
       A0_ADC_SDI_I_c,
       A0_ADC_SDO_O_c,
       A0_ADC_CS_O_c,
       A0_ADC_SCK_O_c
    );
output HALL_INTERFACE_1_omega_out_o_0;
output SPEED_ID_IQ_PI_0_id_pi_output_o_0;
output SPEED_ID_IQ_PI_0_iq_pi_output_o_9;
output SEQ_CONTROLLER_0_state_o_0;
output SEQ_CONTROLLER_0_state_o_2;
output FOC_TRANSFORMS_0_valpha_o_2;
output FOC_TRANSFORMS_0_ialpha_o_0;
output FOC_TRANSFORMS_0_ibeta_o_0;
output adc_interface_0_result_ch0_o_0;
output adc_interface_0_result_ch1_o_0;
output adc_interface_0_result_ch1_o_2;
input  [17:0] MC_System_0_AMBA_SLAVE_0_PWDATA;
output [19:19] MC_System_0_AMBA_SLAVE_0_PRDATA;
output [10:10] prdata_o_1_iv_10_13;
output [16:16] prdata_o_1_iv_9;
output [1:1] prdata_o_1_0_iv_0_13;
output [10:10] prdata_o_1_iv_10_11;
input  [11:0] MC_System_0_AMBA_SLAVE_0_PADDR;
output [9:9] FOC_TRANSFORMS_0_ialpha_o_m;
output FOC_TRANSFORMS_0_valpha_o_m_0;
output FOC_TRANSFORMS_0_valpha_o_m_5;
output [9:9] adc_interface_0_result_ch3_o_m;
output [5:5] FOC_TRANSFORMS_0_id_o_m;
output [12:12] prdata_o_1_iv_0_6;
output [15:14] prdata_o_1_iv_0_10;
output [1:1] prdata_o_1_0_iv_0_14;
output [16:16] prdata_o_1_iv_10;
output [13:13] prdata_o_1_iv_0_7_0;
output [7:7] prdata_o_1_iv_13;
output [7:7] prdata_o_1_iv_12;
output [5:5] prdata_o_1_iv_10_0;
output [14:14] prdata_o_1_iv_0_9;
output [12:12] prdata_o_1_iv_0_7;
output [10:10] prdata_o_1_iv_10_12;
output [1:0] prdata_o_1_0_iv_0_15;
output prdata_o_1_iv_0_12_2;
output prdata_o_1_iv_0_12_0;
output [13:13] prdata_o_1_iv_0_8;
output prdata_o_1_iv_14_2;
output prdata_o_1_iv_14_0;
output prdata_o_1_iv_0_11_0;
output prdata_o_1_iv_0_11_2;
output prdata_o_1_iv_0_11_3;
output [16:16] prdata_o_1_iv_11;
input  MC_System_0_FIC_0_LOCK;
input  MC_System_0_FIC_0_CLK;
output A0_PWM_VL_O_c;
output A0_PWM_UH_O_c;
output A0_PWM_VH_O_c;
output A0_PWM_WH_O_c;
input  HA_i_c;
input  HB_i_c;
input  HC_i_c;
output N_358;
output prdata_o277;
output prdata_o267;
output prdata_N_5_mux_i_3_a0_7_1;
output prdata_N_5_mux_i_3_a0_10;
output prdata_o263;
output prdata_N_5_mux_i_1_a0_13;
output N_435_4;
output prdata_N_5_mux_i_2_a0_11;
output prdata_o259;
output prdata_m2_e_5_6_1;
output prdata_N_5_mux_i_4_a0_11;
output prdata_o274;
output prdata_m2_e_27_10;
output prdata_m2_0_a2_1_0;
output prdata_m2_0_a2_17_0;
output prdata_o270;
input  MC_System_0_AMBA_SLAVE_0_PSELx;
input  MC_System_0_AMBA_SLAVE_0_PWRITE;
input  MC_System_0_AMBA_SLAVE_0_PENABLE;
output N_296;
output prdata_o260;
output N_225;
output prdata_m2_e_5_1;
output prdata_N_5_mux_i_3_a0_4;
output prdata_N_5_mux_i_3_a0_0;
output prdata_N_5_mux_i_2_a0_4;
output prdata_N_5_mux_i_2_a0_0;
output N_286;
output N_283;
output prdata_m2_e_5_11;
output prdata_m2_e_5_6;
output prdata_m2_e_5_4;
output prdata_m2_e_27_11;
output prdata_m2_e_0_9;
output prdata_N_5_mux_i_4_a0_12;
output prdata_N_5_mux_i_3_a0_12;
output prdata_N_5_mux_i_1_a0_12;
output prdata_N_5_mux_i_2_a0_12;
output m7_i_2;
output prdata_m2_e_0_8;
output prdata_N_5_mux_i_2_a0_10;
output N_157;
output prdata_m2_e_5_10;
output prdata_m2_e_27_12;
output prdata_m2_e_0_10;
output prdata_N_5_mux_i_4_a0_13;
output prdata_N_5_mux_i_3_a0_11;
input  A0_ADC_SDI_I_c;
output A0_ADC_SDO_O_c;
output A0_ADC_CS_O_c;
output A0_ADC_SCK_O_c;

    wire [17:0] FOC_TRANSFORMS_0_va_o;
    wire [17:0] FOC_TRANSFORMS_0_vb_o;
    wire [17:0] FOC_TRANSFORMS_0_vc_o;
    wire [17:0] SVM_0_va3h_o;
    wire [17:0] SVM_0_vb3h_o;
    wire [17:0] SVM_0_vc3h_o;
    wire [17:0] OLMNG_0_init_speedpi_o;
    wire [17:0] OLMNG_0_init_iqpi_o;
    wire [17:0] RATE_LIMITER_0_rl_out_o;
    wire [17:1] HALL_INTERFACE_1_omega_out_o;
    wire [17:0] apb3_en_if_1_speed_pi_kp_o;
    wire [17:0] apb3_en_if_1_speed_pi_ki_o;
    wire [17:0] FOC_TRANSFORMS_0_id_o;
    wire [17:0] apb3_en_if_1_idq_pi_kp_o;
    wire [17:0] apb3_en_if_1_idq_pi_ki_o;
    wire [17:0] SPEED_ID_IQ_PI_0_speed_pi_output_o;
    wire [17:0] FOC_TRANSFORMS_0_iq_o;
    wire [17:1] SPEED_ID_IQ_PI_0_id_pi_output_o;
    wire [17:0] SPEED_ID_IQ_PI_0_iq_pi_output_o;
    wire [17:0] apb3_en_if_1_seq_cntl_cl_omega_o;
    wire [3:0] apb3_en_if_1_auto_restart_no_o;
    wire [3:0] apb3_en_if_1_seq_cntl_config_o;
    wire [3:1] SEQ_CONTROLLER_0_state_o;
    wire [17:0] apb3_en_if_1_rate_limit_slew_cnt_o;
    wire [17:0] apb3_en_if_1_rate_limit_rate_cnt_o;
    wire [17:0] apb3_en_if_1_rate_limit_ref_in_o;
    wire [17:0] apb3_en_if_1_pwm_period_val_o;
    wire [17:1] apb3_en_if_1_pwm_gain_val_o;
    wire [17:0] PWM_SCALING_0_Va_o;
    wire [17:0] PWM_SCALING_0_Vb_o;
    wire [17:0] PWM_SCALING_0_Vc_o;
    wire [17:0] apb3_en_if_1_pwm_dead_time_val_o;
    wire [17:0] apb3_en_if_1_pwm_delay_time_val_o;
    wire [17:0] apb3_en_if_1_olmng_theta_factor_o;
    wire [17:0] apb3_en_if_1_olmng_dv_o;
    wire [17:5] HALL_INTERFACE_1_theta_output_o;
    wire [17:0] apb3_en_if_1_olmng_iq_ref_in_o;
    wire [17:0] OLMNG_0_theta_o;
    wire [3:0] apb3_hall_if_0_hall_filter_factor_o;
    wire [17:0] apb3_hall_if_0_hall_speed_factor_o;
    wire [4:0] angle_out_raw_o;
    wire [17:5] HALL_INTERFACE_1_angle_out_raw_o;
    wire [4:0] theta_output_o;
    wire [17:0] ADC_SCALING_0_ia_adc_o;
    wire [17:0] ADC_SCALING_0_ib_adc_o;
    wire [17:1] FOC_TRANSFORMS_0_ialpha_o;
    wire [17:1] FOC_TRANSFORMS_0_ibeta_o;
    wire [17:0] FOC_TRANSFORMS_0_valpha_o;
    wire [17:0] FOC_TRANSFORMS_0_vbeta_o;
    wire [17:0] apb3_en_if_1_adc_scale_val_o;
    wire [11:1] adc_interface_0_result_ch0_o;
    wire [11:1] adc_interface_0_result_ch1_o;
    wire [17:0] apb3_en_if_1_adc_oc_thresh_o;
    wire [5:0] apb3_en_if_1_adc_control_reg_val_o;
    wire [15:0] apb3_en_if_1_adc_channel_ch0_o;
    wire [15:0] apb3_en_if_1_adc_channel_ch1_o;
    wire [15:0] apb3_en_if_1_adc_channel_ch2_o;
    wire [15:0] apb3_en_if_1_adc_channel_ch3_o;
    wire [11:0] adc_interface_0_result_ch2_o;
    wire [11:0] adc_interface_0_result_ch3_o;
    wire FOC_TRANSFORMS_0_iclarke_done_o, SVM_0_done_o, 
        SEQ_CONTROLLER_0_motor_stopped_o, SEQ_CONTROLLER_0_cl_status_o, 
        SEQ_CONTROLLER_0_en_idq_pi_o, RATE_LIMITER_0_rl_done_o, 
        SPEED_ID_IQ_PI_1_iq_pi_done_o, FOC_TRANSFORMS_0_park_done_o, 
        GND, VCC, speed_pi_done_o, SPEED_ID_IQ_PI_1_id_pi_done_o, 
        ADC_SCALING_1_over_current_fault_o, apb3_en_if_1_start_motor_o, 
        apb3_en_if_1_stop_motor_o, apb3_en_if_1_fault_clr_o, 
        ADC_SCALING_0_calib_done_o, PWM3PH_0_midmatch_o, 
        PWM_SCALING_1_done_o, SEQ_CONTROLLER_1_adc_start_o, 
        SEQ_CONTROLLER_0_reset_rl_o, SEQ_CONTROLLER_0_soft_stop_o, 
        sensor_reset_o, ADC_SCALING_0_done_o, 
        apb3_en_if_0_direction_config_o, PWM_AL_o, PWM_BL_o, PWM_CL_o, 
        done_o, apb3_hall_if_0_hall_sensor_polarity_o, omega_done_o, 
        FOC_TRANSFORMS_1_clarke_done_o_0, 
        FOC_TRANSFORMS_0_ipark_done_o, adc_interface_0_results_rdy_o;
    
    PWM3PH MSC_i_27 (.reset_i(MC_System_0_FIC_0_LOCK), .sys_clk_i(
        MC_System_0_FIC_0_CLK), .en_pwm_i(A0_PWM_VL_O_c), 
        .en_dual_trig_i(GND), .va_i({PWM_SCALING_0_Va_o[17], 
        PWM_SCALING_0_Va_o[16], PWM_SCALING_0_Va_o[15], 
        PWM_SCALING_0_Va_o[14], PWM_SCALING_0_Va_o[13], 
        PWM_SCALING_0_Va_o[12], PWM_SCALING_0_Va_o[11], 
        PWM_SCALING_0_Va_o[10], PWM_SCALING_0_Va_o[9], 
        PWM_SCALING_0_Va_o[8], PWM_SCALING_0_Va_o[7], 
        PWM_SCALING_0_Va_o[6], PWM_SCALING_0_Va_o[5], 
        PWM_SCALING_0_Va_o[4], PWM_SCALING_0_Va_o[3], 
        PWM_SCALING_0_Va_o[2], PWM_SCALING_0_Va_o[1], 
        PWM_SCALING_0_Va_o[0]}), .vb_i({PWM_SCALING_0_Vb_o[17], 
        PWM_SCALING_0_Vb_o[16], PWM_SCALING_0_Vb_o[15], 
        PWM_SCALING_0_Vb_o[14], PWM_SCALING_0_Vb_o[13], 
        PWM_SCALING_0_Vb_o[12], PWM_SCALING_0_Vb_o[11], 
        PWM_SCALING_0_Vb_o[10], PWM_SCALING_0_Vb_o[9], 
        PWM_SCALING_0_Vb_o[8], PWM_SCALING_0_Vb_o[7], 
        PWM_SCALING_0_Vb_o[6], PWM_SCALING_0_Vb_o[5], 
        PWM_SCALING_0_Vb_o[4], PWM_SCALING_0_Vb_o[3], 
        PWM_SCALING_0_Vb_o[2], PWM_SCALING_0_Vb_o[1], 
        PWM_SCALING_0_Vb_o[0]}), .vc_i({PWM_SCALING_0_Vc_o[17], 
        PWM_SCALING_0_Vc_o[16], PWM_SCALING_0_Vc_o[15], 
        PWM_SCALING_0_Vc_o[14], PWM_SCALING_0_Vc_o[13], 
        PWM_SCALING_0_Vc_o[12], PWM_SCALING_0_Vc_o[11], 
        PWM_SCALING_0_Vc_o[10], PWM_SCALING_0_Vc_o[9], 
        PWM_SCALING_0_Vc_o[8], PWM_SCALING_0_Vc_o[7], 
        PWM_SCALING_0_Vc_o[6], PWM_SCALING_0_Vc_o[5], 
        PWM_SCALING_0_Vc_o[4], PWM_SCALING_0_Vc_o[3], 
        PWM_SCALING_0_Vc_o[2], PWM_SCALING_0_Vc_o[1], 
        PWM_SCALING_0_Vc_o[0]}), .pwm_period_i({
        apb3_en_if_1_pwm_period_val_o[17], 
        apb3_en_if_1_pwm_period_val_o[16], 
        apb3_en_if_1_pwm_period_val_o[15], 
        apb3_en_if_1_pwm_period_val_o[14], 
        apb3_en_if_1_pwm_period_val_o[13], 
        apb3_en_if_1_pwm_period_val_o[12], 
        apb3_en_if_1_pwm_period_val_o[11], 
        apb3_en_if_1_pwm_period_val_o[10], 
        apb3_en_if_1_pwm_period_val_o[9], 
        apb3_en_if_1_pwm_period_val_o[8], 
        apb3_en_if_1_pwm_period_val_o[7], 
        apb3_en_if_1_pwm_period_val_o[6], 
        apb3_en_if_1_pwm_period_val_o[5], 
        apb3_en_if_1_pwm_period_val_o[4], 
        apb3_en_if_1_pwm_period_val_o[3], 
        apb3_en_if_1_pwm_period_val_o[2], 
        apb3_en_if_1_pwm_period_val_o[1], 
        apb3_en_if_1_pwm_period_val_o[0]}), .dead_time_i({
        apb3_en_if_1_pwm_dead_time_val_o[17], 
        apb3_en_if_1_pwm_dead_time_val_o[16], 
        apb3_en_if_1_pwm_dead_time_val_o[15], 
        apb3_en_if_1_pwm_dead_time_val_o[14], 
        apb3_en_if_1_pwm_dead_time_val_o[13], 
        apb3_en_if_1_pwm_dead_time_val_o[12], 
        apb3_en_if_1_pwm_dead_time_val_o[11], 
        apb3_en_if_1_pwm_dead_time_val_o[10], 
        apb3_en_if_1_pwm_dead_time_val_o[9], 
        apb3_en_if_1_pwm_dead_time_val_o[8], 
        apb3_en_if_1_pwm_dead_time_val_o[7], 
        apb3_en_if_1_pwm_dead_time_val_o[6], 
        apb3_en_if_1_pwm_dead_time_val_o[5], 
        apb3_en_if_1_pwm_dead_time_val_o[4], 
        apb3_en_if_1_pwm_dead_time_val_o[3], 
        apb3_en_if_1_pwm_dead_time_val_o[2], 
        apb3_en_if_1_pwm_dead_time_val_o[1], 
        apb3_en_if_1_pwm_dead_time_val_o[0]}), .delay_time_i({
        apb3_en_if_1_pwm_delay_time_val_o[17], 
        apb3_en_if_1_pwm_delay_time_val_o[16], 
        apb3_en_if_1_pwm_delay_time_val_o[15], 
        apb3_en_if_1_pwm_delay_time_val_o[14], 
        apb3_en_if_1_pwm_delay_time_val_o[13], 
        apb3_en_if_1_pwm_delay_time_val_o[12], 
        apb3_en_if_1_pwm_delay_time_val_o[11], 
        apb3_en_if_1_pwm_delay_time_val_o[10], 
        apb3_en_if_1_pwm_delay_time_val_o[9], 
        apb3_en_if_1_pwm_delay_time_val_o[8], 
        apb3_en_if_1_pwm_delay_time_val_o[7], 
        apb3_en_if_1_pwm_delay_time_val_o[6], 
        apb3_en_if_1_pwm_delay_time_val_o[5], 
        apb3_en_if_1_pwm_delay_time_val_o[4], 
        apb3_en_if_1_pwm_delay_time_val_o[3], 
        apb3_en_if_1_pwm_delay_time_val_o[2], 
        apb3_en_if_1_pwm_delay_time_val_o[1], 
        apb3_en_if_1_pwm_delay_time_val_o[0]}), .midmatch_o(
        PWM3PH_0_midmatch_o), .PWM_AH_o(A0_PWM_UH_O_c), .PWM_BH_o(
        A0_PWM_VH_O_c), .PWM_CH_o(A0_PWM_WH_O_c), .PWM_AL_o(PWM_AL_o), 
        .PWM_BL_o(PWM_BL_o), .PWM_CL_o(PWM_CL_o));
    SVM MSC_i_0 (.reset_i(MC_System_0_FIC_0_LOCK), .sys_clk_i(
        MC_System_0_FIC_0_CLK), .start_i(
        FOC_TRANSFORMS_0_iclarke_done_o), .va_i({
        FOC_TRANSFORMS_0_va_o[17], FOC_TRANSFORMS_0_va_o[16], 
        FOC_TRANSFORMS_0_va_o[15], FOC_TRANSFORMS_0_va_o[14], 
        FOC_TRANSFORMS_0_va_o[13], FOC_TRANSFORMS_0_va_o[12], 
        FOC_TRANSFORMS_0_va_o[11], FOC_TRANSFORMS_0_va_o[10], 
        FOC_TRANSFORMS_0_va_o[9], FOC_TRANSFORMS_0_va_o[8], 
        FOC_TRANSFORMS_0_va_o[7], FOC_TRANSFORMS_0_va_o[6], 
        FOC_TRANSFORMS_0_va_o[5], FOC_TRANSFORMS_0_va_o[4], 
        FOC_TRANSFORMS_0_va_o[3], FOC_TRANSFORMS_0_va_o[2], 
        FOC_TRANSFORMS_0_va_o[1], FOC_TRANSFORMS_0_va_o[0]}), .vb_i({
        FOC_TRANSFORMS_0_vb_o[17], FOC_TRANSFORMS_0_vb_o[16], 
        FOC_TRANSFORMS_0_vb_o[15], FOC_TRANSFORMS_0_vb_o[14], 
        FOC_TRANSFORMS_0_vb_o[13], FOC_TRANSFORMS_0_vb_o[12], 
        FOC_TRANSFORMS_0_vb_o[11], FOC_TRANSFORMS_0_vb_o[10], 
        FOC_TRANSFORMS_0_vb_o[9], FOC_TRANSFORMS_0_vb_o[8], 
        FOC_TRANSFORMS_0_vb_o[7], FOC_TRANSFORMS_0_vb_o[6], 
        FOC_TRANSFORMS_0_vb_o[5], FOC_TRANSFORMS_0_vb_o[4], 
        FOC_TRANSFORMS_0_vb_o[3], FOC_TRANSFORMS_0_vb_o[2], 
        FOC_TRANSFORMS_0_vb_o[1], FOC_TRANSFORMS_0_vb_o[0]}), .vc_i({
        FOC_TRANSFORMS_0_vc_o[17], FOC_TRANSFORMS_0_vc_o[16], 
        FOC_TRANSFORMS_0_vc_o[15], FOC_TRANSFORMS_0_vc_o[14], 
        FOC_TRANSFORMS_0_vc_o[13], FOC_TRANSFORMS_0_vc_o[12], 
        FOC_TRANSFORMS_0_vc_o[11], FOC_TRANSFORMS_0_vc_o[10], 
        FOC_TRANSFORMS_0_vc_o[9], FOC_TRANSFORMS_0_vc_o[8], 
        FOC_TRANSFORMS_0_vc_o[7], FOC_TRANSFORMS_0_vc_o[6], 
        FOC_TRANSFORMS_0_vc_o[5], FOC_TRANSFORMS_0_vc_o[4], 
        FOC_TRANSFORMS_0_vc_o[3], FOC_TRANSFORMS_0_vc_o[2], 
        FOC_TRANSFORMS_0_vc_o[1], FOC_TRANSFORMS_0_vc_o[0]}), .va3h_o({
        SVM_0_va3h_o[17], SVM_0_va3h_o[16], SVM_0_va3h_o[15], 
        SVM_0_va3h_o[14], SVM_0_va3h_o[13], SVM_0_va3h_o[12], 
        SVM_0_va3h_o[11], SVM_0_va3h_o[10], SVM_0_va3h_o[9], 
        SVM_0_va3h_o[8], SVM_0_va3h_o[7], SVM_0_va3h_o[6], 
        SVM_0_va3h_o[5], SVM_0_va3h_o[4], SVM_0_va3h_o[3], 
        SVM_0_va3h_o[2], SVM_0_va3h_o[1], SVM_0_va3h_o[0]}), .vb3h_o({
        SVM_0_vb3h_o[17], SVM_0_vb3h_o[16], SVM_0_vb3h_o[15], 
        SVM_0_vb3h_o[14], SVM_0_vb3h_o[13], SVM_0_vb3h_o[12], 
        SVM_0_vb3h_o[11], SVM_0_vb3h_o[10], SVM_0_vb3h_o[9], 
        SVM_0_vb3h_o[8], SVM_0_vb3h_o[7], SVM_0_vb3h_o[6], 
        SVM_0_vb3h_o[5], SVM_0_vb3h_o[4], SVM_0_vb3h_o[3], 
        SVM_0_vb3h_o[2], SVM_0_vb3h_o[1], SVM_0_vb3h_o[0]}), .vc3h_o({
        SVM_0_vc3h_o[17], SVM_0_vc3h_o[16], SVM_0_vc3h_o[15], 
        SVM_0_vc3h_o[14], SVM_0_vc3h_o[13], SVM_0_vc3h_o[12], 
        SVM_0_vc3h_o[11], SVM_0_vc3h_o[10], SVM_0_vc3h_o[9], 
        SVM_0_vc3h_o[8], SVM_0_vc3h_o[7], SVM_0_vc3h_o[6], 
        SVM_0_vc3h_o[5], SVM_0_vc3h_o[4], SVM_0_vc3h_o[3], 
        SVM_0_vc3h_o[2], SVM_0_vc3h_o[1], SVM_0_vc3h_o[0]}), .done_o(
        SVM_0_done_o));
    GND GND_Z (.Y(GND));
    ADC_SCALING_0s_12s_2s_8192_5_44s_0_1_2_3 MSC_i_19 (.reset_i(
        MC_System_0_FIC_0_LOCK), .sys_clk_i(MC_System_0_FIC_0_CLK), 
        .adc_results_rdy_i(adc_interface_0_results_rdy_o), 
        .adc_scale_val_i({apb3_en_if_1_adc_scale_val_o[17], 
        apb3_en_if_1_adc_scale_val_o[16], 
        apb3_en_if_1_adc_scale_val_o[15], 
        apb3_en_if_1_adc_scale_val_o[14], 
        apb3_en_if_1_adc_scale_val_o[13], 
        apb3_en_if_1_adc_scale_val_o[12], 
        apb3_en_if_1_adc_scale_val_o[11], 
        apb3_en_if_1_adc_scale_val_o[10], 
        apb3_en_if_1_adc_scale_val_o[9], 
        apb3_en_if_1_adc_scale_val_o[8], 
        apb3_en_if_1_adc_scale_val_o[7], 
        apb3_en_if_1_adc_scale_val_o[6], 
        apb3_en_if_1_adc_scale_val_o[5], 
        apb3_en_if_1_adc_scale_val_o[4], 
        apb3_en_if_1_adc_scale_val_o[3], 
        apb3_en_if_1_adc_scale_val_o[2], 
        apb3_en_if_1_adc_scale_val_o[1], 
        apb3_en_if_1_adc_scale_val_o[0]}), .adc_result_ch0_i({
        adc_interface_0_result_ch0_o[11], 
        adc_interface_0_result_ch0_o[10], 
        adc_interface_0_result_ch0_o[9], 
        adc_interface_0_result_ch0_o[8], 
        adc_interface_0_result_ch0_o[7], 
        adc_interface_0_result_ch0_o[6], 
        adc_interface_0_result_ch0_o[5], 
        adc_interface_0_result_ch0_o[4], 
        adc_interface_0_result_ch0_o[3], 
        adc_interface_0_result_ch0_o[2], 
        adc_interface_0_result_ch0_o[1], 
        adc_interface_0_result_ch0_o_0}), .adc_result_ch1_i({
        adc_interface_0_result_ch1_o[11], 
        adc_interface_0_result_ch1_o[10], 
        adc_interface_0_result_ch1_o[9], 
        adc_interface_0_result_ch1_o[8], 
        adc_interface_0_result_ch1_o[7], 
        adc_interface_0_result_ch1_o[6], 
        adc_interface_0_result_ch1_o[5], 
        adc_interface_0_result_ch1_o[4], 
        adc_interface_0_result_ch1_o[3], 
        adc_interface_0_result_ch1_o_2, 
        adc_interface_0_result_ch1_o[1], 
        adc_interface_0_result_ch1_o_0}), .fault_threshold_i({
        apb3_en_if_1_adc_oc_thresh_o[17], 
        apb3_en_if_1_adc_oc_thresh_o[16], 
        apb3_en_if_1_adc_oc_thresh_o[15], 
        apb3_en_if_1_adc_oc_thresh_o[14], 
        apb3_en_if_1_adc_oc_thresh_o[13], 
        apb3_en_if_1_adc_oc_thresh_o[12], 
        apb3_en_if_1_adc_oc_thresh_o[11], 
        apb3_en_if_1_adc_oc_thresh_o[10], 
        apb3_en_if_1_adc_oc_thresh_o[9], 
        apb3_en_if_1_adc_oc_thresh_o[8], 
        apb3_en_if_1_adc_oc_thresh_o[7], 
        apb3_en_if_1_adc_oc_thresh_o[6], 
        apb3_en_if_1_adc_oc_thresh_o[5], 
        apb3_en_if_1_adc_oc_thresh_o[4], 
        apb3_en_if_1_adc_oc_thresh_o[3], 
        apb3_en_if_1_adc_oc_thresh_o[2], 
        apb3_en_if_1_adc_oc_thresh_o[1], 
        apb3_en_if_1_adc_oc_thresh_o[0]}), .done_o(
        ADC_SCALING_0_done_o), .calib_done_o(
        ADC_SCALING_0_calib_done_o), .over_current_fault_o(
        ADC_SCALING_1_over_current_fault_o), .ia_adc_o({
        ADC_SCALING_0_ia_adc_o[17], ADC_SCALING_0_ia_adc_o[16], 
        ADC_SCALING_0_ia_adc_o[15], ADC_SCALING_0_ia_adc_o[14], 
        ADC_SCALING_0_ia_adc_o[13], ADC_SCALING_0_ia_adc_o[12], 
        ADC_SCALING_0_ia_adc_o[11], ADC_SCALING_0_ia_adc_o[10], 
        ADC_SCALING_0_ia_adc_o[9], ADC_SCALING_0_ia_adc_o[8], 
        ADC_SCALING_0_ia_adc_o[7], ADC_SCALING_0_ia_adc_o[6], 
        ADC_SCALING_0_ia_adc_o[5], ADC_SCALING_0_ia_adc_o[4], 
        ADC_SCALING_0_ia_adc_o[3], ADC_SCALING_0_ia_adc_o[2], 
        ADC_SCALING_0_ia_adc_o[1], ADC_SCALING_0_ia_adc_o[0]}), 
        .ib_adc_o({ADC_SCALING_0_ib_adc_o[17], 
        ADC_SCALING_0_ib_adc_o[16], ADC_SCALING_0_ib_adc_o[15], 
        ADC_SCALING_0_ib_adc_o[14], ADC_SCALING_0_ib_adc_o[13], 
        ADC_SCALING_0_ib_adc_o[12], ADC_SCALING_0_ib_adc_o[11], 
        ADC_SCALING_0_ib_adc_o[10], ADC_SCALING_0_ib_adc_o[9], 
        ADC_SCALING_0_ib_adc_o[8], ADC_SCALING_0_ib_adc_o[7], 
        ADC_SCALING_0_ib_adc_o[6], ADC_SCALING_0_ib_adc_o[5], 
        ADC_SCALING_0_ib_adc_o[4], ADC_SCALING_0_ib_adc_o[3], 
        ADC_SCALING_0_ib_adc_o[2], ADC_SCALING_0_ib_adc_o[1], 
        ADC_SCALING_0_ib_adc_o[0]}));
    OLMNG_2s_13s_44s_0_2_3 MSC_i_12 (.reset_i(MC_System_0_FIC_0_LOCK), 
        .sys_clk_i(MC_System_0_FIC_0_CLK), .start_i(
        RATE_LIMITER_0_rl_done_o), .clear_buffer_i(
        SEQ_CONTROLLER_0_motor_stopped_o), .direction_config_i(
        apb3_en_if_0_direction_config_o), .cl_status_i(
        SEQ_CONTROLLER_0_cl_status_o), .theta_factor_i({
        apb3_en_if_1_olmng_theta_factor_o[17], 
        apb3_en_if_1_olmng_theta_factor_o[16], 
        apb3_en_if_1_olmng_theta_factor_o[15], 
        apb3_en_if_1_olmng_theta_factor_o[14], 
        apb3_en_if_1_olmng_theta_factor_o[13], 
        apb3_en_if_1_olmng_theta_factor_o[12], 
        apb3_en_if_1_olmng_theta_factor_o[11], 
        apb3_en_if_1_olmng_theta_factor_o[10], 
        apb3_en_if_1_olmng_theta_factor_o[9], 
        apb3_en_if_1_olmng_theta_factor_o[8], 
        apb3_en_if_1_olmng_theta_factor_o[7], 
        apb3_en_if_1_olmng_theta_factor_o[6], 
        apb3_en_if_1_olmng_theta_factor_o[5], 
        apb3_en_if_1_olmng_theta_factor_o[4], 
        apb3_en_if_1_olmng_theta_factor_o[3], 
        apb3_en_if_1_olmng_theta_factor_o[2], 
        apb3_en_if_1_olmng_theta_factor_o[1], 
        apb3_en_if_1_olmng_theta_factor_o[0]}), .speed_ref_i({
        RATE_LIMITER_0_rl_out_o[17], RATE_LIMITER_0_rl_out_o[16], 
        RATE_LIMITER_0_rl_out_o[15], RATE_LIMITER_0_rl_out_o[14], 
        RATE_LIMITER_0_rl_out_o[13], RATE_LIMITER_0_rl_out_o[12], 
        RATE_LIMITER_0_rl_out_o[11], RATE_LIMITER_0_rl_out_o[10], 
        RATE_LIMITER_0_rl_out_o[9], RATE_LIMITER_0_rl_out_o[8], 
        RATE_LIMITER_0_rl_out_o[7], RATE_LIMITER_0_rl_out_o[6], 
        RATE_LIMITER_0_rl_out_o[5], RATE_LIMITER_0_rl_out_o[4], 
        RATE_LIMITER_0_rl_out_o[3], RATE_LIMITER_0_rl_out_o[2], 
        RATE_LIMITER_0_rl_out_o[1], RATE_LIMITER_0_rl_out_o[0]}), 
        .dv_i({apb3_en_if_1_olmng_dv_o[17], 
        apb3_en_if_1_olmng_dv_o[16], apb3_en_if_1_olmng_dv_o[15], 
        apb3_en_if_1_olmng_dv_o[14], apb3_en_if_1_olmng_dv_o[13], 
        apb3_en_if_1_olmng_dv_o[12], apb3_en_if_1_olmng_dv_o[11], 
        apb3_en_if_1_olmng_dv_o[10], apb3_en_if_1_olmng_dv_o[9], 
        apb3_en_if_1_olmng_dv_o[8], apb3_en_if_1_olmng_dv_o[7], 
        apb3_en_if_1_olmng_dv_o[6], apb3_en_if_1_olmng_dv_o[5], 
        apb3_en_if_1_olmng_dv_o[4], apb3_en_if_1_olmng_dv_o[3], 
        apb3_en_if_1_olmng_dv_o[2], apb3_en_if_1_olmng_dv_o[1], 
        apb3_en_if_1_olmng_dv_o[0]}), .theta_cl_i({
        HALL_INTERFACE_1_theta_output_o[17], 
        HALL_INTERFACE_1_theta_output_o[16], 
        HALL_INTERFACE_1_theta_output_o[15], 
        HALL_INTERFACE_1_theta_output_o[14], 
        HALL_INTERFACE_1_theta_output_o[13], 
        HALL_INTERFACE_1_theta_output_o[12], 
        HALL_INTERFACE_1_theta_output_o[11], 
        HALL_INTERFACE_1_theta_output_o[10], 
        HALL_INTERFACE_1_theta_output_o[9], 
        HALL_INTERFACE_1_theta_output_o[8], 
        HALL_INTERFACE_1_theta_output_o[7], 
        HALL_INTERFACE_1_theta_output_o[6], 
        HALL_INTERFACE_1_theta_output_o[5], GND, GND, GND, GND, GND}), 
        .iq_ref_in_i({apb3_en_if_1_olmng_iq_ref_in_o[17], 
        apb3_en_if_1_olmng_iq_ref_in_o[16], 
        apb3_en_if_1_olmng_iq_ref_in_o[15], 
        apb3_en_if_1_olmng_iq_ref_in_o[14], 
        apb3_en_if_1_olmng_iq_ref_in_o[13], 
        apb3_en_if_1_olmng_iq_ref_in_o[12], 
        apb3_en_if_1_olmng_iq_ref_in_o[11], 
        apb3_en_if_1_olmng_iq_ref_in_o[10], 
        apb3_en_if_1_olmng_iq_ref_in_o[9], 
        apb3_en_if_1_olmng_iq_ref_in_o[8], 
        apb3_en_if_1_olmng_iq_ref_in_o[7], 
        apb3_en_if_1_olmng_iq_ref_in_o[6], 
        apb3_en_if_1_olmng_iq_ref_in_o[5], 
        apb3_en_if_1_olmng_iq_ref_in_o[4], 
        apb3_en_if_1_olmng_iq_ref_in_o[3], 
        apb3_en_if_1_olmng_iq_ref_in_o[2], 
        apb3_en_if_1_olmng_iq_ref_in_o[1], 
        apb3_en_if_1_olmng_iq_ref_in_o[0]}), .done_o(done_o), .theta_o({
        OLMNG_0_theta_o[17], OLMNG_0_theta_o[16], OLMNG_0_theta_o[15], 
        OLMNG_0_theta_o[14], OLMNG_0_theta_o[13], OLMNG_0_theta_o[12], 
        OLMNG_0_theta_o[11], OLMNG_0_theta_o[10], OLMNG_0_theta_o[9], 
        OLMNG_0_theta_o[8], OLMNG_0_theta_o[7], OLMNG_0_theta_o[6], 
        OLMNG_0_theta_o[5], OLMNG_0_theta_o[4], OLMNG_0_theta_o[3], 
        OLMNG_0_theta_o[2], OLMNG_0_theta_o[1], OLMNG_0_theta_o[0]}), 
        .init_speedpi_o({OLMNG_0_init_speedpi_o[17], 
        OLMNG_0_init_speedpi_o[16], OLMNG_0_init_speedpi_o[15], 
        OLMNG_0_init_speedpi_o[14], OLMNG_0_init_speedpi_o[13], 
        OLMNG_0_init_speedpi_o[12], OLMNG_0_init_speedpi_o[11], 
        OLMNG_0_init_speedpi_o[10], OLMNG_0_init_speedpi_o[9], 
        OLMNG_0_init_speedpi_o[8], OLMNG_0_init_speedpi_o[7], 
        OLMNG_0_init_speedpi_o[6], OLMNG_0_init_speedpi_o[5], 
        OLMNG_0_init_speedpi_o[4], OLMNG_0_init_speedpi_o[3], 
        OLMNG_0_init_speedpi_o[2], OLMNG_0_init_speedpi_o[1], 
        OLMNG_0_init_speedpi_o[0]}), .init_iqpi_o({
        OLMNG_0_init_iqpi_o[17], OLMNG_0_init_iqpi_o[16], 
        OLMNG_0_init_iqpi_o[15], OLMNG_0_init_iqpi_o[14], 
        OLMNG_0_init_iqpi_o[13], OLMNG_0_init_iqpi_o[12], 
        OLMNG_0_init_iqpi_o[11], OLMNG_0_init_iqpi_o[10], 
        OLMNG_0_init_iqpi_o[9], OLMNG_0_init_iqpi_o[8], 
        OLMNG_0_init_iqpi_o[7], OLMNG_0_init_iqpi_o[6], 
        OLMNG_0_init_iqpi_o[5], OLMNG_0_init_iqpi_o[4], 
        OLMNG_0_init_iqpi_o[3], OLMNG_0_init_iqpi_o[2], 
        OLMNG_0_init_iqpi_o[1], OLMNG_0_init_iqpi_o[0]}));
    RATE_LIMITER MSC_i_9 (.reset_i(MC_System_0_FIC_0_LOCK), .sys_clk_i(
        MC_System_0_FIC_0_CLK), .start_i(ADC_SCALING_0_done_o), 
        .soft_stop_i(SEQ_CONTROLLER_0_soft_stop_o), .reset_rl_i(
        SEQ_CONTROLLER_0_reset_rl_o), .direction_i(
        apb3_en_if_0_direction_config_o), .slew_count_i({
        apb3_en_if_1_rate_limit_slew_cnt_o[17], 
        apb3_en_if_1_rate_limit_slew_cnt_o[16], 
        apb3_en_if_1_rate_limit_slew_cnt_o[15], 
        apb3_en_if_1_rate_limit_slew_cnt_o[14], 
        apb3_en_if_1_rate_limit_slew_cnt_o[13], 
        apb3_en_if_1_rate_limit_slew_cnt_o[12], 
        apb3_en_if_1_rate_limit_slew_cnt_o[11], 
        apb3_en_if_1_rate_limit_slew_cnt_o[10], 
        apb3_en_if_1_rate_limit_slew_cnt_o[9], 
        apb3_en_if_1_rate_limit_slew_cnt_o[8], 
        apb3_en_if_1_rate_limit_slew_cnt_o[7], 
        apb3_en_if_1_rate_limit_slew_cnt_o[6], 
        apb3_en_if_1_rate_limit_slew_cnt_o[5], 
        apb3_en_if_1_rate_limit_slew_cnt_o[4], 
        apb3_en_if_1_rate_limit_slew_cnt_o[3], 
        apb3_en_if_1_rate_limit_slew_cnt_o[2], 
        apb3_en_if_1_rate_limit_slew_cnt_o[1], 
        apb3_en_if_1_rate_limit_slew_cnt_o[0]}), .rate_count_i({
        apb3_en_if_1_rate_limit_rate_cnt_o[17], 
        apb3_en_if_1_rate_limit_rate_cnt_o[16], 
        apb3_en_if_1_rate_limit_rate_cnt_o[15], 
        apb3_en_if_1_rate_limit_rate_cnt_o[14], 
        apb3_en_if_1_rate_limit_rate_cnt_o[13], 
        apb3_en_if_1_rate_limit_rate_cnt_o[12], 
        apb3_en_if_1_rate_limit_rate_cnt_o[11], 
        apb3_en_if_1_rate_limit_rate_cnt_o[10], 
        apb3_en_if_1_rate_limit_rate_cnt_o[9], 
        apb3_en_if_1_rate_limit_rate_cnt_o[8], 
        apb3_en_if_1_rate_limit_rate_cnt_o[7], 
        apb3_en_if_1_rate_limit_rate_cnt_o[6], 
        apb3_en_if_1_rate_limit_rate_cnt_o[5], 
        apb3_en_if_1_rate_limit_rate_cnt_o[4], 
        apb3_en_if_1_rate_limit_rate_cnt_o[3], 
        apb3_en_if_1_rate_limit_rate_cnt_o[2], 
        apb3_en_if_1_rate_limit_rate_cnt_o[1], 
        apb3_en_if_1_rate_limit_rate_cnt_o[0]}), .rl_in_i({
        apb3_en_if_1_rate_limit_ref_in_o[17], 
        apb3_en_if_1_rate_limit_ref_in_o[16], 
        apb3_en_if_1_rate_limit_ref_in_o[15], 
        apb3_en_if_1_rate_limit_ref_in_o[14], 
        apb3_en_if_1_rate_limit_ref_in_o[13], 
        apb3_en_if_1_rate_limit_ref_in_o[12], 
        apb3_en_if_1_rate_limit_ref_in_o[11], 
        apb3_en_if_1_rate_limit_ref_in_o[10], 
        apb3_en_if_1_rate_limit_ref_in_o[9], 
        apb3_en_if_1_rate_limit_ref_in_o[8], 
        apb3_en_if_1_rate_limit_ref_in_o[7], 
        apb3_en_if_1_rate_limit_ref_in_o[6], 
        apb3_en_if_1_rate_limit_ref_in_o[5], 
        apb3_en_if_1_rate_limit_ref_in_o[4], 
        apb3_en_if_1_rate_limit_ref_in_o[3], 
        apb3_en_if_1_rate_limit_ref_in_o[2], 
        apb3_en_if_1_rate_limit_ref_in_o[1], 
        apb3_en_if_1_rate_limit_ref_in_o[0]}), .rl_out_o({
        RATE_LIMITER_0_rl_out_o[17], RATE_LIMITER_0_rl_out_o[16], 
        RATE_LIMITER_0_rl_out_o[15], RATE_LIMITER_0_rl_out_o[14], 
        RATE_LIMITER_0_rl_out_o[13], RATE_LIMITER_0_rl_out_o[12], 
        RATE_LIMITER_0_rl_out_o[11], RATE_LIMITER_0_rl_out_o[10], 
        RATE_LIMITER_0_rl_out_o[9], RATE_LIMITER_0_rl_out_o[8], 
        RATE_LIMITER_0_rl_out_o[7], RATE_LIMITER_0_rl_out_o[6], 
        RATE_LIMITER_0_rl_out_o[5], RATE_LIMITER_0_rl_out_o[4], 
        RATE_LIMITER_0_rl_out_o[3], RATE_LIMITER_0_rl_out_o[2], 
        RATE_LIMITER_0_rl_out_o[1], RATE_LIMITER_0_rl_out_o[0]}), 
        .rl_done_o(RATE_LIMITER_0_rl_done_o));
    SPEED_ID_IQ_PI_2s_44s MSC_i_21 (.reset_i(MC_System_0_FIC_0_LOCK), 
        .sys_clk_i(MC_System_0_FIC_0_CLK), .clear_buffer_i(
        SEQ_CONTROLLER_0_motor_stopped_o), .speed_en_i(
        SEQ_CONTROLLER_0_cl_status_o), .idq_en_i(
        SEQ_CONTROLLER_0_en_idq_pi_o), .speed_pi_start_i(
        RATE_LIMITER_0_rl_done_o), .id_pi_start_i(
        SPEED_ID_IQ_PI_1_iq_pi_done_o), .iq_pi_start_i(
        FOC_TRANSFORMS_0_park_done_o), .speed_init_i({
        OLMNG_0_init_speedpi_o[17], OLMNG_0_init_speedpi_o[16], 
        OLMNG_0_init_speedpi_o[15], OLMNG_0_init_speedpi_o[14], 
        OLMNG_0_init_speedpi_o[13], OLMNG_0_init_speedpi_o[12], 
        OLMNG_0_init_speedpi_o[11], OLMNG_0_init_speedpi_o[10], 
        OLMNG_0_init_speedpi_o[9], OLMNG_0_init_speedpi_o[8], 
        OLMNG_0_init_speedpi_o[7], OLMNG_0_init_speedpi_o[6], 
        OLMNG_0_init_speedpi_o[5], OLMNG_0_init_speedpi_o[4], 
        OLMNG_0_init_speedpi_o[3], OLMNG_0_init_speedpi_o[2], 
        OLMNG_0_init_speedpi_o[1], OLMNG_0_init_speedpi_o[0]}), 
        .id_init_i({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND}), .iq_init_i({
        OLMNG_0_init_iqpi_o[17], OLMNG_0_init_iqpi_o[16], 
        OLMNG_0_init_iqpi_o[15], OLMNG_0_init_iqpi_o[14], 
        OLMNG_0_init_iqpi_o[13], OLMNG_0_init_iqpi_o[12], 
        OLMNG_0_init_iqpi_o[11], OLMNG_0_init_iqpi_o[10], 
        OLMNG_0_init_iqpi_o[9], OLMNG_0_init_iqpi_o[8], 
        OLMNG_0_init_iqpi_o[7], OLMNG_0_init_iqpi_o[6], 
        OLMNG_0_init_iqpi_o[5], OLMNG_0_init_iqpi_o[4], 
        OLMNG_0_init_iqpi_o[3], OLMNG_0_init_iqpi_o[2], 
        OLMNG_0_init_iqpi_o[1], OLMNG_0_init_iqpi_o[0]}), 
        .speed_pi_ref_input_i({RATE_LIMITER_0_rl_out_o[17], 
        RATE_LIMITER_0_rl_out_o[16], RATE_LIMITER_0_rl_out_o[15], 
        RATE_LIMITER_0_rl_out_o[14], RATE_LIMITER_0_rl_out_o[13], 
        RATE_LIMITER_0_rl_out_o[12], RATE_LIMITER_0_rl_out_o[11], 
        RATE_LIMITER_0_rl_out_o[10], RATE_LIMITER_0_rl_out_o[9], 
        RATE_LIMITER_0_rl_out_o[8], RATE_LIMITER_0_rl_out_o[7], 
        RATE_LIMITER_0_rl_out_o[6], RATE_LIMITER_0_rl_out_o[5], 
        RATE_LIMITER_0_rl_out_o[4], RATE_LIMITER_0_rl_out_o[3], 
        RATE_LIMITER_0_rl_out_o[2], RATE_LIMITER_0_rl_out_o[1], 
        RATE_LIMITER_0_rl_out_o[0]}), .speed_pi_act_input_i({
        HALL_INTERFACE_1_omega_out_o[17], 
        HALL_INTERFACE_1_omega_out_o[16], 
        HALL_INTERFACE_1_omega_out_o[15], 
        HALL_INTERFACE_1_omega_out_o[14], 
        HALL_INTERFACE_1_omega_out_o[13], 
        HALL_INTERFACE_1_omega_out_o[12], 
        HALL_INTERFACE_1_omega_out_o[11], 
        HALL_INTERFACE_1_omega_out_o[10], 
        HALL_INTERFACE_1_omega_out_o[9], 
        HALL_INTERFACE_1_omega_out_o[8], 
        HALL_INTERFACE_1_omega_out_o[7], 
        HALL_INTERFACE_1_omega_out_o[6], 
        HALL_INTERFACE_1_omega_out_o[5], 
        HALL_INTERFACE_1_omega_out_o[4], 
        HALL_INTERFACE_1_omega_out_o[3], 
        HALL_INTERFACE_1_omega_out_o[2], 
        HALL_INTERFACE_1_omega_out_o[1], 
        HALL_INTERFACE_1_omega_out_o_0}), .speed_pi_kp_i({
        apb3_en_if_1_speed_pi_kp_o[17], apb3_en_if_1_speed_pi_kp_o[16], 
        apb3_en_if_1_speed_pi_kp_o[15], apb3_en_if_1_speed_pi_kp_o[14], 
        apb3_en_if_1_speed_pi_kp_o[13], apb3_en_if_1_speed_pi_kp_o[12], 
        apb3_en_if_1_speed_pi_kp_o[11], apb3_en_if_1_speed_pi_kp_o[10], 
        apb3_en_if_1_speed_pi_kp_o[9], apb3_en_if_1_speed_pi_kp_o[8], 
        apb3_en_if_1_speed_pi_kp_o[7], apb3_en_if_1_speed_pi_kp_o[6], 
        apb3_en_if_1_speed_pi_kp_o[5], apb3_en_if_1_speed_pi_kp_o[4], 
        apb3_en_if_1_speed_pi_kp_o[3], apb3_en_if_1_speed_pi_kp_o[2], 
        apb3_en_if_1_speed_pi_kp_o[1], apb3_en_if_1_speed_pi_kp_o[0]}), 
        .speed_pi_ki_i({apb3_en_if_1_speed_pi_ki_o[17], 
        apb3_en_if_1_speed_pi_ki_o[16], apb3_en_if_1_speed_pi_ki_o[15], 
        apb3_en_if_1_speed_pi_ki_o[14], apb3_en_if_1_speed_pi_ki_o[13], 
        apb3_en_if_1_speed_pi_ki_o[12], apb3_en_if_1_speed_pi_ki_o[11], 
        apb3_en_if_1_speed_pi_ki_o[10], apb3_en_if_1_speed_pi_ki_o[9], 
        apb3_en_if_1_speed_pi_ki_o[8], apb3_en_if_1_speed_pi_ki_o[7], 
        apb3_en_if_1_speed_pi_ki_o[6], apb3_en_if_1_speed_pi_ki_o[5], 
        apb3_en_if_1_speed_pi_ki_o[4], apb3_en_if_1_speed_pi_ki_o[3], 
        apb3_en_if_1_speed_pi_ki_o[2], apb3_en_if_1_speed_pi_ki_o[1], 
        apb3_en_if_1_speed_pi_ki_o[0]}), .speed_pi_ymax_i({GND, VCC, 
        VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, 
        VCC, VCC, VCC, VCC}), .speed_pi_ymin_i({VCC, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, VCC}), .id_pi_ref_input_i({GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}), 
        .id_pi_act_input_i({FOC_TRANSFORMS_0_id_o[17], 
        FOC_TRANSFORMS_0_id_o[16], FOC_TRANSFORMS_0_id_o[15], 
        FOC_TRANSFORMS_0_id_o[14], FOC_TRANSFORMS_0_id_o[13], 
        FOC_TRANSFORMS_0_id_o[12], FOC_TRANSFORMS_0_id_o[11], 
        FOC_TRANSFORMS_0_id_o[10], FOC_TRANSFORMS_0_id_o[9], 
        FOC_TRANSFORMS_0_id_o[8], FOC_TRANSFORMS_0_id_o[7], 
        FOC_TRANSFORMS_0_id_o[6], FOC_TRANSFORMS_0_id_o[5], 
        FOC_TRANSFORMS_0_id_o[4], FOC_TRANSFORMS_0_id_o[3], 
        FOC_TRANSFORMS_0_id_o[2], FOC_TRANSFORMS_0_id_o[1], 
        FOC_TRANSFORMS_0_id_o[0]}), .id_pi_kp_i({
        apb3_en_if_1_idq_pi_kp_o[17], apb3_en_if_1_idq_pi_kp_o[16], 
        apb3_en_if_1_idq_pi_kp_o[15], apb3_en_if_1_idq_pi_kp_o[14], 
        apb3_en_if_1_idq_pi_kp_o[13], apb3_en_if_1_idq_pi_kp_o[12], 
        apb3_en_if_1_idq_pi_kp_o[11], apb3_en_if_1_idq_pi_kp_o[10], 
        apb3_en_if_1_idq_pi_kp_o[9], apb3_en_if_1_idq_pi_kp_o[8], 
        apb3_en_if_1_idq_pi_kp_o[7], apb3_en_if_1_idq_pi_kp_o[6], 
        apb3_en_if_1_idq_pi_kp_o[5], apb3_en_if_1_idq_pi_kp_o[4], 
        apb3_en_if_1_idq_pi_kp_o[3], apb3_en_if_1_idq_pi_kp_o[2], 
        apb3_en_if_1_idq_pi_kp_o[1], apb3_en_if_1_idq_pi_kp_o[0]}), 
        .id_pi_ki_i({apb3_en_if_1_idq_pi_ki_o[17], 
        apb3_en_if_1_idq_pi_ki_o[16], apb3_en_if_1_idq_pi_ki_o[15], 
        apb3_en_if_1_idq_pi_ki_o[14], apb3_en_if_1_idq_pi_ki_o[13], 
        apb3_en_if_1_idq_pi_ki_o[12], apb3_en_if_1_idq_pi_ki_o[11], 
        apb3_en_if_1_idq_pi_ki_o[10], apb3_en_if_1_idq_pi_ki_o[9], 
        apb3_en_if_1_idq_pi_ki_o[8], apb3_en_if_1_idq_pi_ki_o[7], 
        apb3_en_if_1_idq_pi_ki_o[6], apb3_en_if_1_idq_pi_ki_o[5], 
        apb3_en_if_1_idq_pi_ki_o[4], apb3_en_if_1_idq_pi_ki_o[3], 
        apb3_en_if_1_idq_pi_ki_o[2], apb3_en_if_1_idq_pi_ki_o[1], 
        apb3_en_if_1_idq_pi_ki_o[0]}), .idq_pi_ymax_i({GND, VCC, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND}), .idq_pi_ymin_i({VCC, VCC, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}), 
        .iq_pi_ref_input_i({SPEED_ID_IQ_PI_0_speed_pi_output_o[17], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[16], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[15], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[14], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[13], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[12], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[11], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[10], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[9], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[8], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[7], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[6], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[5], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[4], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[3], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[2], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[1], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[0]}), .iq_pi_act_input_i({
        FOC_TRANSFORMS_0_iq_o[17], FOC_TRANSFORMS_0_iq_o[16], 
        FOC_TRANSFORMS_0_iq_o[15], FOC_TRANSFORMS_0_iq_o[14], 
        FOC_TRANSFORMS_0_iq_o[13], FOC_TRANSFORMS_0_iq_o[12], 
        FOC_TRANSFORMS_0_iq_o[11], FOC_TRANSFORMS_0_iq_o[10], 
        FOC_TRANSFORMS_0_iq_o[9], FOC_TRANSFORMS_0_iq_o[8], 
        FOC_TRANSFORMS_0_iq_o[7], FOC_TRANSFORMS_0_iq_o[6], 
        FOC_TRANSFORMS_0_iq_o[5], FOC_TRANSFORMS_0_iq_o[4], 
        FOC_TRANSFORMS_0_iq_o[3], FOC_TRANSFORMS_0_iq_o[2], 
        FOC_TRANSFORMS_0_iq_o[1], FOC_TRANSFORMS_0_iq_o[0]}), 
        .iq_pi_kp_i({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND}), .iq_pi_ki_i({GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND}), .speed_pi_done_o(speed_pi_done_o), 
        .id_pi_done_o(SPEED_ID_IQ_PI_1_id_pi_done_o), .iq_pi_done_o(
        SPEED_ID_IQ_PI_1_iq_pi_done_o), .speed_pi_output_o({
        SPEED_ID_IQ_PI_0_speed_pi_output_o[17], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[16], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[15], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[14], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[13], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[12], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[11], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[10], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[9], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[8], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[7], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[6], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[5], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[4], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[3], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[2], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[1], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[0]}), .id_pi_output_o({
        SPEED_ID_IQ_PI_0_id_pi_output_o[17], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[16], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[15], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[14], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[13], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[12], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[11], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[10], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[9], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[8], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[7], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[6], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[5], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[4], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[3], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[2], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[1], 
        SPEED_ID_IQ_PI_0_id_pi_output_o_0}), .iq_pi_output_o({
        SPEED_ID_IQ_PI_0_iq_pi_output_o[17], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[16], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[15], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[14], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[13], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[12], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[11], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[10], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o_9, 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[8], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[7], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[6], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[5], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[4], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[3], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[2], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[1], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[0]}));
    SEQ_CONTROLLER_Z1_layer1 MSC_i_11 (.reset_i(MC_System_0_FIC_0_LOCK)
        , .sys_clk_i(MC_System_0_FIC_0_CLK), .fault_i(
        ADC_SCALING_1_over_current_fault_o), .start_motor_i(
        apb3_en_if_1_start_motor_o), .stop_motor_i(
        apb3_en_if_1_stop_motor_o), .fault_clear_i(
        apb3_en_if_1_fault_clr_o), .speed_ref_i({
        RATE_LIMITER_0_rl_out_o[17], RATE_LIMITER_0_rl_out_o[16], 
        RATE_LIMITER_0_rl_out_o[15], RATE_LIMITER_0_rl_out_o[14], 
        RATE_LIMITER_0_rl_out_o[13], RATE_LIMITER_0_rl_out_o[12], 
        RATE_LIMITER_0_rl_out_o[11], RATE_LIMITER_0_rl_out_o[10], 
        RATE_LIMITER_0_rl_out_o[9], RATE_LIMITER_0_rl_out_o[8], 
        RATE_LIMITER_0_rl_out_o[7], RATE_LIMITER_0_rl_out_o[6], 
        RATE_LIMITER_0_rl_out_o[5], RATE_LIMITER_0_rl_out_o[4], 
        RATE_LIMITER_0_rl_out_o[3], RATE_LIMITER_0_rl_out_o[2], 
        RATE_LIMITER_0_rl_out_o[1], RATE_LIMITER_0_rl_out_o[0]}), 
        .speed_cl_i({apb3_en_if_1_seq_cntl_cl_omega_o[17], 
        apb3_en_if_1_seq_cntl_cl_omega_o[16], 
        apb3_en_if_1_seq_cntl_cl_omega_o[15], 
        apb3_en_if_1_seq_cntl_cl_omega_o[14], 
        apb3_en_if_1_seq_cntl_cl_omega_o[13], 
        apb3_en_if_1_seq_cntl_cl_omega_o[12], 
        apb3_en_if_1_seq_cntl_cl_omega_o[11], 
        apb3_en_if_1_seq_cntl_cl_omega_o[10], 
        apb3_en_if_1_seq_cntl_cl_omega_o[9], 
        apb3_en_if_1_seq_cntl_cl_omega_o[8], 
        apb3_en_if_1_seq_cntl_cl_omega_o[7], 
        apb3_en_if_1_seq_cntl_cl_omega_o[6], 
        apb3_en_if_1_seq_cntl_cl_omega_o[5], 
        apb3_en_if_1_seq_cntl_cl_omega_o[4], 
        apb3_en_if_1_seq_cntl_cl_omega_o[3], 
        apb3_en_if_1_seq_cntl_cl_omega_o[2], 
        apb3_en_if_1_seq_cntl_cl_omega_o[1], 
        apb3_en_if_1_seq_cntl_cl_omega_o[0]}), .vq_i({
        SPEED_ID_IQ_PI_0_iq_pi_output_o[17], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[16], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[15], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[14], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[13], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[12], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[11], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[10], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o_9, 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[8], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[7], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[6], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[5], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[4], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[3], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[2], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[1], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[0]}), .max_ar_i({
        apb3_en_if_1_auto_restart_no_o[3], 
        apb3_en_if_1_auto_restart_no_o[2], 
        apb3_en_if_1_auto_restart_no_o[1], 
        apb3_en_if_1_auto_restart_no_o[0]}), .calib_done_i(
        ADC_SCALING_0_calib_done_o), .pwm_midmatch_i(
        PWM3PH_0_midmatch_o), .foc_done_i(PWM_SCALING_1_done_o), 
        .config_reg_i({apb3_en_if_1_seq_cntl_config_o[3], 
        apb3_en_if_1_seq_cntl_config_o[2], 
        apb3_en_if_1_seq_cntl_config_o[1], 
        apb3_en_if_1_seq_cntl_config_o[0]}), .adc_start_o(
        SEQ_CONTROLLER_1_adc_start_o), .cl_status_o(
        SEQ_CONTROLLER_0_cl_status_o), .en_idq_pi_o(
        SEQ_CONTROLLER_0_en_idq_pi_o), .en_pwm_o(A0_PWM_VL_O_c), 
        .motor_stopped_o(SEQ_CONTROLLER_0_motor_stopped_o), 
        .reset_rl_o(SEQ_CONTROLLER_0_reset_rl_o), .soft_stop_o(
        SEQ_CONTROLLER_0_soft_stop_o), .sensor_reset_o(sensor_reset_o), 
        .state_o({SEQ_CONTROLLER_0_state_o[3], 
        SEQ_CONTROLLER_0_state_o_2, SEQ_CONTROLLER_0_state_o[1], 
        SEQ_CONTROLLER_0_state_o_0}));
    VCC VCC_Z (.Y(VCC));
    FOC_TRANSFORMS_2s_44s MSC_i_1 (.reset_i(MC_System_0_FIC_0_LOCK), 
        .sys_clk_i(MC_System_0_FIC_0_CLK), .start_clarke_i(
        ADC_SCALING_0_done_o), .start_park_i(
        FOC_TRANSFORMS_1_clarke_done_o_0), .start_ipark_i(
        SPEED_ID_IQ_PI_1_id_pi_done_o), .start_iclarke_i(
        FOC_TRANSFORMS_0_ipark_done_o), .ia_i({
        ADC_SCALING_0_ia_adc_o[17], ADC_SCALING_0_ia_adc_o[16], 
        ADC_SCALING_0_ia_adc_o[15], ADC_SCALING_0_ia_adc_o[14], 
        ADC_SCALING_0_ia_adc_o[13], ADC_SCALING_0_ia_adc_o[12], 
        ADC_SCALING_0_ia_adc_o[11], ADC_SCALING_0_ia_adc_o[10], 
        ADC_SCALING_0_ia_adc_o[9], ADC_SCALING_0_ia_adc_o[8], 
        ADC_SCALING_0_ia_adc_o[7], ADC_SCALING_0_ia_adc_o[6], 
        ADC_SCALING_0_ia_adc_o[5], ADC_SCALING_0_ia_adc_o[4], 
        ADC_SCALING_0_ia_adc_o[3], ADC_SCALING_0_ia_adc_o[2], 
        ADC_SCALING_0_ia_adc_o[1], ADC_SCALING_0_ia_adc_o[0]}), .ib_i({
        ADC_SCALING_0_ib_adc_o[17], ADC_SCALING_0_ib_adc_o[16], 
        ADC_SCALING_0_ib_adc_o[15], ADC_SCALING_0_ib_adc_o[14], 
        ADC_SCALING_0_ib_adc_o[13], ADC_SCALING_0_ib_adc_o[12], 
        ADC_SCALING_0_ib_adc_o[11], ADC_SCALING_0_ib_adc_o[10], 
        ADC_SCALING_0_ib_adc_o[9], ADC_SCALING_0_ib_adc_o[8], 
        ADC_SCALING_0_ib_adc_o[7], ADC_SCALING_0_ib_adc_o[6], 
        ADC_SCALING_0_ib_adc_o[5], ADC_SCALING_0_ib_adc_o[4], 
        ADC_SCALING_0_ib_adc_o[3], ADC_SCALING_0_ib_adc_o[2], 
        ADC_SCALING_0_ib_adc_o[1], ADC_SCALING_0_ib_adc_o[0]}), 
        .ialpha_i({FOC_TRANSFORMS_0_ialpha_o[17], 
        FOC_TRANSFORMS_0_ialpha_o[16], FOC_TRANSFORMS_0_ialpha_o[15], 
        FOC_TRANSFORMS_0_ialpha_o[14], FOC_TRANSFORMS_0_ialpha_o[13], 
        FOC_TRANSFORMS_0_ialpha_o[12], FOC_TRANSFORMS_0_ialpha_o[11], 
        FOC_TRANSFORMS_0_ialpha_o[10], FOC_TRANSFORMS_0_ialpha_o[9], 
        FOC_TRANSFORMS_0_ialpha_o[8], FOC_TRANSFORMS_0_ialpha_o[7], 
        FOC_TRANSFORMS_0_ialpha_o[6], FOC_TRANSFORMS_0_ialpha_o[5], 
        FOC_TRANSFORMS_0_ialpha_o[4], FOC_TRANSFORMS_0_ialpha_o[3], 
        FOC_TRANSFORMS_0_ialpha_o[2], FOC_TRANSFORMS_0_ialpha_o[1], 
        GND}), .ibeta_i({FOC_TRANSFORMS_0_ibeta_o[17], 
        FOC_TRANSFORMS_0_ibeta_o[16], FOC_TRANSFORMS_0_ibeta_o[15], 
        FOC_TRANSFORMS_0_ibeta_o[14], FOC_TRANSFORMS_0_ibeta_o[13], 
        FOC_TRANSFORMS_0_ibeta_o[12], FOC_TRANSFORMS_0_ibeta_o[11], 
        FOC_TRANSFORMS_0_ibeta_o[10], FOC_TRANSFORMS_0_ibeta_o[9], 
        FOC_TRANSFORMS_0_ibeta_o[8], FOC_TRANSFORMS_0_ibeta_o[7], 
        FOC_TRANSFORMS_0_ibeta_o[6], FOC_TRANSFORMS_0_ibeta_o[5], 
        FOC_TRANSFORMS_0_ibeta_o[4], FOC_TRANSFORMS_0_ibeta_o[3], 
        FOC_TRANSFORMS_0_ibeta_o[2], FOC_TRANSFORMS_0_ibeta_o[1], GND})
        , .vd_i({SPEED_ID_IQ_PI_0_id_pi_output_o[17], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[16], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[15], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[14], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[13], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[12], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[11], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[10], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[9], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[8], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[7], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[6], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[5], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[4], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[3], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[2], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[1], GND}), .vq_i({
        SPEED_ID_IQ_PI_0_iq_pi_output_o[17], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[16], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[15], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[14], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[13], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[12], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[11], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[10], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o_9, 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[8], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[7], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[6], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[5], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[4], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[3], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[2], 
        SPEED_ID_IQ_PI_0_iq_pi_output_o[1], GND}), .valpha_i({
        FOC_TRANSFORMS_0_valpha_o[17], FOC_TRANSFORMS_0_valpha_o[16], 
        FOC_TRANSFORMS_0_valpha_o[15], FOC_TRANSFORMS_0_valpha_o[14], 
        FOC_TRANSFORMS_0_valpha_o[13], FOC_TRANSFORMS_0_valpha_o[12], 
        FOC_TRANSFORMS_0_valpha_o[11], FOC_TRANSFORMS_0_valpha_o[10], 
        FOC_TRANSFORMS_0_valpha_o[9], FOC_TRANSFORMS_0_valpha_o[8], 
        FOC_TRANSFORMS_0_valpha_o[7], FOC_TRANSFORMS_0_valpha_o[6], 
        FOC_TRANSFORMS_0_valpha_o[5], FOC_TRANSFORMS_0_valpha_o[4], 
        FOC_TRANSFORMS_0_valpha_o[3], FOC_TRANSFORMS_0_valpha_o_2, 
        FOC_TRANSFORMS_0_valpha_o[1], FOC_TRANSFORMS_0_valpha_o[0]}), 
        .vbeta_i({FOC_TRANSFORMS_0_vbeta_o[17], 
        FOC_TRANSFORMS_0_vbeta_o[16], FOC_TRANSFORMS_0_vbeta_o[15], 
        FOC_TRANSFORMS_0_vbeta_o[14], FOC_TRANSFORMS_0_vbeta_o[13], 
        FOC_TRANSFORMS_0_vbeta_o[12], FOC_TRANSFORMS_0_vbeta_o[11], 
        FOC_TRANSFORMS_0_vbeta_o[10], FOC_TRANSFORMS_0_vbeta_o[9], 
        FOC_TRANSFORMS_0_vbeta_o[8], FOC_TRANSFORMS_0_vbeta_o[7], 
        FOC_TRANSFORMS_0_vbeta_o[6], FOC_TRANSFORMS_0_vbeta_o[5], 
        FOC_TRANSFORMS_0_vbeta_o[4], FOC_TRANSFORMS_0_vbeta_o[3], 
        FOC_TRANSFORMS_0_vbeta_o[2], FOC_TRANSFORMS_0_vbeta_o[1], 
        FOC_TRANSFORMS_0_vbeta_o[0]}), .theta_i({OLMNG_0_theta_o[17], 
        OLMNG_0_theta_o[16], OLMNG_0_theta_o[15], OLMNG_0_theta_o[14], 
        OLMNG_0_theta_o[13], OLMNG_0_theta_o[12], OLMNG_0_theta_o[11], 
        OLMNG_0_theta_o[10], OLMNG_0_theta_o[9], OLMNG_0_theta_o[8], 
        OLMNG_0_theta_o[7], OLMNG_0_theta_o[6], OLMNG_0_theta_o[5], 
        OLMNG_0_theta_o[4], OLMNG_0_theta_o[3], OLMNG_0_theta_o[2], 
        OLMNG_0_theta_o[1], OLMNG_0_theta_o[0]}), .clarke_done_o(
        FOC_TRANSFORMS_1_clarke_done_o_0), .park_done_o(
        FOC_TRANSFORMS_0_park_done_o), .ipark_done_o(
        FOC_TRANSFORMS_0_ipark_done_o), .iclarke_done_o(
        FOC_TRANSFORMS_0_iclarke_done_o), .ialpha_o({
        FOC_TRANSFORMS_0_ialpha_o[17], FOC_TRANSFORMS_0_ialpha_o[16], 
        FOC_TRANSFORMS_0_ialpha_o[15], FOC_TRANSFORMS_0_ialpha_o[14], 
        FOC_TRANSFORMS_0_ialpha_o[13], FOC_TRANSFORMS_0_ialpha_o[12], 
        FOC_TRANSFORMS_0_ialpha_o[11], FOC_TRANSFORMS_0_ialpha_o[10], 
        FOC_TRANSFORMS_0_ialpha_o[9], FOC_TRANSFORMS_0_ialpha_o[8], 
        FOC_TRANSFORMS_0_ialpha_o[7], FOC_TRANSFORMS_0_ialpha_o[6], 
        FOC_TRANSFORMS_0_ialpha_o[5], FOC_TRANSFORMS_0_ialpha_o[4], 
        FOC_TRANSFORMS_0_ialpha_o[3], FOC_TRANSFORMS_0_ialpha_o[2], 
        FOC_TRANSFORMS_0_ialpha_o[1], FOC_TRANSFORMS_0_ialpha_o_0}), 
        .ibeta_o({FOC_TRANSFORMS_0_ibeta_o[17], 
        FOC_TRANSFORMS_0_ibeta_o[16], FOC_TRANSFORMS_0_ibeta_o[15], 
        FOC_TRANSFORMS_0_ibeta_o[14], FOC_TRANSFORMS_0_ibeta_o[13], 
        FOC_TRANSFORMS_0_ibeta_o[12], FOC_TRANSFORMS_0_ibeta_o[11], 
        FOC_TRANSFORMS_0_ibeta_o[10], FOC_TRANSFORMS_0_ibeta_o[9], 
        FOC_TRANSFORMS_0_ibeta_o[8], FOC_TRANSFORMS_0_ibeta_o[7], 
        FOC_TRANSFORMS_0_ibeta_o[6], FOC_TRANSFORMS_0_ibeta_o[5], 
        FOC_TRANSFORMS_0_ibeta_o[4], FOC_TRANSFORMS_0_ibeta_o[3], 
        FOC_TRANSFORMS_0_ibeta_o[2], FOC_TRANSFORMS_0_ibeta_o[1], 
        FOC_TRANSFORMS_0_ibeta_o_0}), .id_o({FOC_TRANSFORMS_0_id_o[17], 
        FOC_TRANSFORMS_0_id_o[16], FOC_TRANSFORMS_0_id_o[15], 
        FOC_TRANSFORMS_0_id_o[14], FOC_TRANSFORMS_0_id_o[13], 
        FOC_TRANSFORMS_0_id_o[12], FOC_TRANSFORMS_0_id_o[11], 
        FOC_TRANSFORMS_0_id_o[10], FOC_TRANSFORMS_0_id_o[9], 
        FOC_TRANSFORMS_0_id_o[8], FOC_TRANSFORMS_0_id_o[7], 
        FOC_TRANSFORMS_0_id_o[6], FOC_TRANSFORMS_0_id_o[5], 
        FOC_TRANSFORMS_0_id_o[4], FOC_TRANSFORMS_0_id_o[3], 
        FOC_TRANSFORMS_0_id_o[2], FOC_TRANSFORMS_0_id_o[1], 
        FOC_TRANSFORMS_0_id_o[0]}), .iq_o({FOC_TRANSFORMS_0_iq_o[17], 
        FOC_TRANSFORMS_0_iq_o[16], FOC_TRANSFORMS_0_iq_o[15], 
        FOC_TRANSFORMS_0_iq_o[14], FOC_TRANSFORMS_0_iq_o[13], 
        FOC_TRANSFORMS_0_iq_o[12], FOC_TRANSFORMS_0_iq_o[11], 
        FOC_TRANSFORMS_0_iq_o[10], FOC_TRANSFORMS_0_iq_o[9], 
        FOC_TRANSFORMS_0_iq_o[8], FOC_TRANSFORMS_0_iq_o[7], 
        FOC_TRANSFORMS_0_iq_o[6], FOC_TRANSFORMS_0_iq_o[5], 
        FOC_TRANSFORMS_0_iq_o[4], FOC_TRANSFORMS_0_iq_o[3], 
        FOC_TRANSFORMS_0_iq_o[2], FOC_TRANSFORMS_0_iq_o[1], 
        FOC_TRANSFORMS_0_iq_o[0]}), .valpha_o({
        FOC_TRANSFORMS_0_valpha_o[17], FOC_TRANSFORMS_0_valpha_o[16], 
        FOC_TRANSFORMS_0_valpha_o[15], FOC_TRANSFORMS_0_valpha_o[14], 
        FOC_TRANSFORMS_0_valpha_o[13], FOC_TRANSFORMS_0_valpha_o[12], 
        FOC_TRANSFORMS_0_valpha_o[11], FOC_TRANSFORMS_0_valpha_o[10], 
        FOC_TRANSFORMS_0_valpha_o[9], FOC_TRANSFORMS_0_valpha_o[8], 
        FOC_TRANSFORMS_0_valpha_o[7], FOC_TRANSFORMS_0_valpha_o[6], 
        FOC_TRANSFORMS_0_valpha_o[5], FOC_TRANSFORMS_0_valpha_o[4], 
        FOC_TRANSFORMS_0_valpha_o[3], FOC_TRANSFORMS_0_valpha_o_2, 
        FOC_TRANSFORMS_0_valpha_o[1], FOC_TRANSFORMS_0_valpha_o[0]}), 
        .vbeta_o({FOC_TRANSFORMS_0_vbeta_o[17], 
        FOC_TRANSFORMS_0_vbeta_o[16], FOC_TRANSFORMS_0_vbeta_o[15], 
        FOC_TRANSFORMS_0_vbeta_o[14], FOC_TRANSFORMS_0_vbeta_o[13], 
        FOC_TRANSFORMS_0_vbeta_o[12], FOC_TRANSFORMS_0_vbeta_o[11], 
        FOC_TRANSFORMS_0_vbeta_o[10], FOC_TRANSFORMS_0_vbeta_o[9], 
        FOC_TRANSFORMS_0_vbeta_o[8], FOC_TRANSFORMS_0_vbeta_o[7], 
        FOC_TRANSFORMS_0_vbeta_o[6], FOC_TRANSFORMS_0_vbeta_o[5], 
        FOC_TRANSFORMS_0_vbeta_o[4], FOC_TRANSFORMS_0_vbeta_o[3], 
        FOC_TRANSFORMS_0_vbeta_o[2], FOC_TRANSFORMS_0_vbeta_o[1], 
        FOC_TRANSFORMS_0_vbeta_o[0]}), .va_o({
        FOC_TRANSFORMS_0_va_o[17], FOC_TRANSFORMS_0_va_o[16], 
        FOC_TRANSFORMS_0_va_o[15], FOC_TRANSFORMS_0_va_o[14], 
        FOC_TRANSFORMS_0_va_o[13], FOC_TRANSFORMS_0_va_o[12], 
        FOC_TRANSFORMS_0_va_o[11], FOC_TRANSFORMS_0_va_o[10], 
        FOC_TRANSFORMS_0_va_o[9], FOC_TRANSFORMS_0_va_o[8], 
        FOC_TRANSFORMS_0_va_o[7], FOC_TRANSFORMS_0_va_o[6], 
        FOC_TRANSFORMS_0_va_o[5], FOC_TRANSFORMS_0_va_o[4], 
        FOC_TRANSFORMS_0_va_o[3], FOC_TRANSFORMS_0_va_o[2], 
        FOC_TRANSFORMS_0_va_o[1], FOC_TRANSFORMS_0_va_o[0]}), .vb_o({
        FOC_TRANSFORMS_0_vb_o[17], FOC_TRANSFORMS_0_vb_o[16], 
        FOC_TRANSFORMS_0_vb_o[15], FOC_TRANSFORMS_0_vb_o[14], 
        FOC_TRANSFORMS_0_vb_o[13], FOC_TRANSFORMS_0_vb_o[12], 
        FOC_TRANSFORMS_0_vb_o[11], FOC_TRANSFORMS_0_vb_o[10], 
        FOC_TRANSFORMS_0_vb_o[9], FOC_TRANSFORMS_0_vb_o[8], 
        FOC_TRANSFORMS_0_vb_o[7], FOC_TRANSFORMS_0_vb_o[6], 
        FOC_TRANSFORMS_0_vb_o[5], FOC_TRANSFORMS_0_vb_o[4], 
        FOC_TRANSFORMS_0_vb_o[3], FOC_TRANSFORMS_0_vb_o[2], 
        FOC_TRANSFORMS_0_vb_o[1], FOC_TRANSFORMS_0_vb_o[0]}), .vc_o({
        FOC_TRANSFORMS_0_vc_o[17], FOC_TRANSFORMS_0_vc_o[16], 
        FOC_TRANSFORMS_0_vc_o[15], FOC_TRANSFORMS_0_vc_o[14], 
        FOC_TRANSFORMS_0_vc_o[13], FOC_TRANSFORMS_0_vc_o[12], 
        FOC_TRANSFORMS_0_vc_o[11], FOC_TRANSFORMS_0_vc_o[10], 
        FOC_TRANSFORMS_0_vc_o[9], FOC_TRANSFORMS_0_vc_o[8], 
        FOC_TRANSFORMS_0_vc_o[7], FOC_TRANSFORMS_0_vc_o[6], 
        FOC_TRANSFORMS_0_vc_o[5], FOC_TRANSFORMS_0_vc_o[4], 
        FOC_TRANSFORMS_0_vc_o[3], FOC_TRANSFORMS_0_vc_o[2], 
        FOC_TRANSFORMS_0_vc_o[1], FOC_TRANSFORMS_0_vc_o[0]}));
    
        work_adc_interface_adc_interface_6_16_12_2_g_ADC_CONFIG_REG_WIDTHg_ADC_CONFIG_VAL_WIDTHg_ADC_RESULTS_WIDTH 
        adc_interface_0 (.apb3_en_if_1_adc_control_reg_val_o({
        apb3_en_if_1_adc_control_reg_val_o[5], 
        apb3_en_if_1_adc_control_reg_val_o[4], 
        apb3_en_if_1_adc_control_reg_val_o[3], 
        apb3_en_if_1_adc_control_reg_val_o[2], 
        apb3_en_if_1_adc_control_reg_val_o[1], 
        apb3_en_if_1_adc_control_reg_val_o[0]}), 
        .adc_interface_0_result_ch0_o({
        adc_interface_0_result_ch0_o[11], 
        adc_interface_0_result_ch0_o[10], 
        adc_interface_0_result_ch0_o[9], 
        adc_interface_0_result_ch0_o[8], 
        adc_interface_0_result_ch0_o[7], 
        adc_interface_0_result_ch0_o[6], 
        adc_interface_0_result_ch0_o[5], 
        adc_interface_0_result_ch0_o[4], 
        adc_interface_0_result_ch0_o[3], 
        adc_interface_0_result_ch0_o[2], 
        adc_interface_0_result_ch0_o[1], 
        adc_interface_0_result_ch0_o_0}), 
        .adc_interface_0_result_ch1_o({
        adc_interface_0_result_ch1_o[11], 
        adc_interface_0_result_ch1_o[10], 
        adc_interface_0_result_ch1_o[9], 
        adc_interface_0_result_ch1_o[8], 
        adc_interface_0_result_ch1_o[7], 
        adc_interface_0_result_ch1_o[6], 
        adc_interface_0_result_ch1_o[5], 
        adc_interface_0_result_ch1_o[4], 
        adc_interface_0_result_ch1_o[3], 
        adc_interface_0_result_ch1_o_2, 
        adc_interface_0_result_ch1_o[1], 
        adc_interface_0_result_ch1_o_0}), 
        .adc_interface_0_result_ch2_o({
        adc_interface_0_result_ch2_o[11], 
        adc_interface_0_result_ch2_o[10], 
        adc_interface_0_result_ch2_o[9], 
        adc_interface_0_result_ch2_o[8], 
        adc_interface_0_result_ch2_o[7], 
        adc_interface_0_result_ch2_o[6], 
        adc_interface_0_result_ch2_o[5], 
        adc_interface_0_result_ch2_o[4], 
        adc_interface_0_result_ch2_o[3], 
        adc_interface_0_result_ch2_o[2], 
        adc_interface_0_result_ch2_o[1], 
        adc_interface_0_result_ch2_o[0]}), 
        .adc_interface_0_result_ch3_o({
        adc_interface_0_result_ch3_o[11], 
        adc_interface_0_result_ch3_o[10], 
        adc_interface_0_result_ch3_o[9], 
        adc_interface_0_result_ch3_o[8], 
        adc_interface_0_result_ch3_o[7], 
        adc_interface_0_result_ch3_o[6], 
        adc_interface_0_result_ch3_o[5], 
        adc_interface_0_result_ch3_o[4], 
        adc_interface_0_result_ch3_o[3], 
        adc_interface_0_result_ch3_o[2], 
        adc_interface_0_result_ch3_o[1], 
        adc_interface_0_result_ch3_o[0]}), 
        .apb3_en_if_1_adc_channel_ch2_o({
        apb3_en_if_1_adc_channel_ch2_o[15], 
        apb3_en_if_1_adc_channel_ch2_o[14], 
        apb3_en_if_1_adc_channel_ch2_o[13], 
        apb3_en_if_1_adc_channel_ch2_o[12], 
        apb3_en_if_1_adc_channel_ch2_o[11], 
        apb3_en_if_1_adc_channel_ch2_o[10], 
        apb3_en_if_1_adc_channel_ch2_o[9], 
        apb3_en_if_1_adc_channel_ch2_o[8], 
        apb3_en_if_1_adc_channel_ch2_o[7], 
        apb3_en_if_1_adc_channel_ch2_o[6], 
        apb3_en_if_1_adc_channel_ch2_o[5], 
        apb3_en_if_1_adc_channel_ch2_o[4], 
        apb3_en_if_1_adc_channel_ch2_o[3], 
        apb3_en_if_1_adc_channel_ch2_o[2], 
        apb3_en_if_1_adc_channel_ch2_o[1], 
        apb3_en_if_1_adc_channel_ch2_o[0]}), 
        .apb3_en_if_1_adc_channel_ch0_o({
        apb3_en_if_1_adc_channel_ch0_o[15], 
        apb3_en_if_1_adc_channel_ch0_o[14], 
        apb3_en_if_1_adc_channel_ch0_o[13], 
        apb3_en_if_1_adc_channel_ch0_o[12], 
        apb3_en_if_1_adc_channel_ch0_o[11], 
        apb3_en_if_1_adc_channel_ch0_o[10], 
        apb3_en_if_1_adc_channel_ch0_o[9], 
        apb3_en_if_1_adc_channel_ch0_o[8], 
        apb3_en_if_1_adc_channel_ch0_o[7], 
        apb3_en_if_1_adc_channel_ch0_o[6], 
        apb3_en_if_1_adc_channel_ch0_o[5], 
        apb3_en_if_1_adc_channel_ch0_o[4], 
        apb3_en_if_1_adc_channel_ch0_o[3], 
        apb3_en_if_1_adc_channel_ch0_o[2], 
        apb3_en_if_1_adc_channel_ch0_o[1], 
        apb3_en_if_1_adc_channel_ch0_o[0]}), 
        .apb3_en_if_1_adc_channel_ch1_o({
        apb3_en_if_1_adc_channel_ch1_o[15], 
        apb3_en_if_1_adc_channel_ch1_o[14], 
        apb3_en_if_1_adc_channel_ch1_o[13], 
        apb3_en_if_1_adc_channel_ch1_o[12], 
        apb3_en_if_1_adc_channel_ch1_o[11], 
        apb3_en_if_1_adc_channel_ch1_o[10], 
        apb3_en_if_1_adc_channel_ch1_o[9], 
        apb3_en_if_1_adc_channel_ch1_o[8], 
        apb3_en_if_1_adc_channel_ch1_o[7], 
        apb3_en_if_1_adc_channel_ch1_o[6], 
        apb3_en_if_1_adc_channel_ch1_o[5], 
        apb3_en_if_1_adc_channel_ch1_o[4], 
        apb3_en_if_1_adc_channel_ch1_o[3], 
        apb3_en_if_1_adc_channel_ch1_o[2], 
        apb3_en_if_1_adc_channel_ch1_o[1], 
        apb3_en_if_1_adc_channel_ch1_o[0]}), 
        .apb3_en_if_1_adc_channel_ch3_o({
        apb3_en_if_1_adc_channel_ch3_o[15], 
        apb3_en_if_1_adc_channel_ch3_o[14], 
        apb3_en_if_1_adc_channel_ch3_o[13], 
        apb3_en_if_1_adc_channel_ch3_o[12], 
        apb3_en_if_1_adc_channel_ch3_o[11], 
        apb3_en_if_1_adc_channel_ch3_o[10], 
        apb3_en_if_1_adc_channel_ch3_o[9], 
        apb3_en_if_1_adc_channel_ch3_o[8], 
        apb3_en_if_1_adc_channel_ch3_o[7], 
        apb3_en_if_1_adc_channel_ch3_o[6], 
        apb3_en_if_1_adc_channel_ch3_o[5], 
        apb3_en_if_1_adc_channel_ch3_o[4], 
        apb3_en_if_1_adc_channel_ch3_o[3], 
        apb3_en_if_1_adc_channel_ch3_o[2], 
        apb3_en_if_1_adc_channel_ch3_o[1], 
        apb3_en_if_1_adc_channel_ch3_o[0]}), .MC_System_0_FIC_0_LOCK(
        MC_System_0_FIC_0_LOCK), .MC_System_0_FIC_0_CLK(
        MC_System_0_FIC_0_CLK), .SEQ_CONTROLLER_1_adc_start_o(
        SEQ_CONTROLLER_1_adc_start_o), .A0_ADC_SDI_I_c(A0_ADC_SDI_I_c), 
        .A0_ADC_SDO_O_c(A0_ADC_SDO_O_c), .A0_ADC_CS_O_c(A0_ADC_CS_O_c), 
        .A0_ADC_SCK_O_c(A0_ADC_SCK_O_c), 
        .adc_interface_0_results_rdy_o(adc_interface_0_results_rdy_o));
    PWM_SCALING_2s_44s_15s_0_1_2_3_4 MSC_i_25 (.reset_i(
        MC_System_0_FIC_0_LOCK), .sys_clk_i(MC_System_0_FIC_0_CLK), 
        .start_i(SVM_0_done_o), .va_i({SVM_0_va3h_o[17], 
        SVM_0_va3h_o[16], SVM_0_va3h_o[15], SVM_0_va3h_o[14], 
        SVM_0_va3h_o[13], SVM_0_va3h_o[12], SVM_0_va3h_o[11], 
        SVM_0_va3h_o[10], SVM_0_va3h_o[9], SVM_0_va3h_o[8], 
        SVM_0_va3h_o[7], SVM_0_va3h_o[6], SVM_0_va3h_o[5], 
        SVM_0_va3h_o[4], SVM_0_va3h_o[3], SVM_0_va3h_o[2], 
        SVM_0_va3h_o[1], SVM_0_va3h_o[0]}), .vb_i({SVM_0_vb3h_o[17], 
        SVM_0_vb3h_o[16], SVM_0_vb3h_o[15], SVM_0_vb3h_o[14], 
        SVM_0_vb3h_o[13], SVM_0_vb3h_o[12], SVM_0_vb3h_o[11], 
        SVM_0_vb3h_o[10], SVM_0_vb3h_o[9], SVM_0_vb3h_o[8], 
        SVM_0_vb3h_o[7], SVM_0_vb3h_o[6], SVM_0_vb3h_o[5], 
        SVM_0_vb3h_o[4], SVM_0_vb3h_o[3], SVM_0_vb3h_o[2], 
        SVM_0_vb3h_o[1], SVM_0_vb3h_o[0]}), .vc_i({SVM_0_vc3h_o[17], 
        SVM_0_vc3h_o[16], SVM_0_vc3h_o[15], SVM_0_vc3h_o[14], 
        SVM_0_vc3h_o[13], SVM_0_vc3h_o[12], SVM_0_vc3h_o[11], 
        SVM_0_vc3h_o[10], SVM_0_vc3h_o[9], SVM_0_vc3h_o[8], 
        SVM_0_vc3h_o[7], SVM_0_vc3h_o[6], SVM_0_vc3h_o[5], 
        SVM_0_vc3h_o[4], SVM_0_vc3h_o[3], SVM_0_vc3h_o[2], 
        SVM_0_vc3h_o[1], SVM_0_vc3h_o[0]}), .pwm_period_i({
        apb3_en_if_1_pwm_period_val_o[17], 
        apb3_en_if_1_pwm_period_val_o[16], 
        apb3_en_if_1_pwm_period_val_o[15], 
        apb3_en_if_1_pwm_period_val_o[14], 
        apb3_en_if_1_pwm_period_val_o[13], 
        apb3_en_if_1_pwm_period_val_o[12], 
        apb3_en_if_1_pwm_period_val_o[11], 
        apb3_en_if_1_pwm_period_val_o[10], 
        apb3_en_if_1_pwm_period_val_o[9], 
        apb3_en_if_1_pwm_period_val_o[8], 
        apb3_en_if_1_pwm_period_val_o[7], 
        apb3_en_if_1_pwm_period_val_o[6], 
        apb3_en_if_1_pwm_period_val_o[5], 
        apb3_en_if_1_pwm_period_val_o[4], 
        apb3_en_if_1_pwm_period_val_o[3], 
        apb3_en_if_1_pwm_period_val_o[2], 
        apb3_en_if_1_pwm_period_val_o[1], 
        apb3_en_if_1_pwm_period_val_o[0]}), .pwm_gain_i({
        apb3_en_if_1_pwm_gain_val_o[17], 
        apb3_en_if_1_pwm_gain_val_o[16], 
        apb3_en_if_1_pwm_gain_val_o[15], 
        apb3_en_if_1_pwm_gain_val_o[14], 
        apb3_en_if_1_pwm_gain_val_o[13], 
        apb3_en_if_1_pwm_gain_val_o[12], 
        apb3_en_if_1_pwm_gain_val_o[11], 
        apb3_en_if_1_pwm_gain_val_o[10], 
        apb3_en_if_1_pwm_gain_val_o[9], apb3_en_if_1_pwm_gain_val_o[8], 
        apb3_en_if_1_pwm_gain_val_o[7], apb3_en_if_1_pwm_gain_val_o[6], 
        apb3_en_if_1_pwm_gain_val_o[5], apb3_en_if_1_pwm_gain_val_o[4], 
        apb3_en_if_1_pwm_gain_val_o[3], apb3_en_if_1_pwm_gain_val_o[2], 
        apb3_en_if_1_pwm_gain_val_o[1], GND}), .Va_o({
        PWM_SCALING_0_Va_o[17], PWM_SCALING_0_Va_o[16], 
        PWM_SCALING_0_Va_o[15], PWM_SCALING_0_Va_o[14], 
        PWM_SCALING_0_Va_o[13], PWM_SCALING_0_Va_o[12], 
        PWM_SCALING_0_Va_o[11], PWM_SCALING_0_Va_o[10], 
        PWM_SCALING_0_Va_o[9], PWM_SCALING_0_Va_o[8], 
        PWM_SCALING_0_Va_o[7], PWM_SCALING_0_Va_o[6], 
        PWM_SCALING_0_Va_o[5], PWM_SCALING_0_Va_o[4], 
        PWM_SCALING_0_Va_o[3], PWM_SCALING_0_Va_o[2], 
        PWM_SCALING_0_Va_o[1], PWM_SCALING_0_Va_o[0]}), .Vb_o({
        PWM_SCALING_0_Vb_o[17], PWM_SCALING_0_Vb_o[16], 
        PWM_SCALING_0_Vb_o[15], PWM_SCALING_0_Vb_o[14], 
        PWM_SCALING_0_Vb_o[13], PWM_SCALING_0_Vb_o[12], 
        PWM_SCALING_0_Vb_o[11], PWM_SCALING_0_Vb_o[10], 
        PWM_SCALING_0_Vb_o[9], PWM_SCALING_0_Vb_o[8], 
        PWM_SCALING_0_Vb_o[7], PWM_SCALING_0_Vb_o[6], 
        PWM_SCALING_0_Vb_o[5], PWM_SCALING_0_Vb_o[4], 
        PWM_SCALING_0_Vb_o[3], PWM_SCALING_0_Vb_o[2], 
        PWM_SCALING_0_Vb_o[1], PWM_SCALING_0_Vb_o[0]}), .Vc_o({
        PWM_SCALING_0_Vc_o[17], PWM_SCALING_0_Vc_o[16], 
        PWM_SCALING_0_Vc_o[15], PWM_SCALING_0_Vc_o[14], 
        PWM_SCALING_0_Vc_o[13], PWM_SCALING_0_Vc_o[12], 
        PWM_SCALING_0_Vc_o[11], PWM_SCALING_0_Vc_o[10], 
        PWM_SCALING_0_Vc_o[9], PWM_SCALING_0_Vc_o[8], 
        PWM_SCALING_0_Vc_o[7], PWM_SCALING_0_Vc_o[6], 
        PWM_SCALING_0_Vc_o[5], PWM_SCALING_0_Vc_o[4], 
        PWM_SCALING_0_Vc_o[3], PWM_SCALING_0_Vc_o[2], 
        PWM_SCALING_0_Vc_o[1], PWM_SCALING_0_Vc_o[0]}), .done_o(
        PWM_SCALING_1_done_o));
    HALL_INTERFACE MSC_i_15 (.reset_i(MC_System_0_FIC_0_LOCK), 
        .sys_clk_i(MC_System_0_FIC_0_CLK), .ha_i(HA_i_c), .hb_i(HB_i_c)
        , .hc_i(HC_i_c), .clear_buffer_i(
        SEQ_CONTROLLER_0_motor_stopped_o), .fil_trig_i(
        PWM3PH_0_midmatch_o), .filter_factor_i({
        apb3_hall_if_0_hall_filter_factor_o[3], 
        apb3_hall_if_0_hall_filter_factor_o[2], 
        apb3_hall_if_0_hall_filter_factor_o[1], 
        apb3_hall_if_0_hall_filter_factor_o[0]}), .hall_sensor_pol_i(
        apb3_hall_if_0_hall_sensor_polarity_o), .speed_factor_i({
        apb3_hall_if_0_hall_speed_factor_o[17], 
        apb3_hall_if_0_hall_speed_factor_o[16], 
        apb3_hall_if_0_hall_speed_factor_o[15], 
        apb3_hall_if_0_hall_speed_factor_o[14], 
        apb3_hall_if_0_hall_speed_factor_o[13], 
        apb3_hall_if_0_hall_speed_factor_o[12], 
        apb3_hall_if_0_hall_speed_factor_o[11], 
        apb3_hall_if_0_hall_speed_factor_o[10], 
        apb3_hall_if_0_hall_speed_factor_o[9], 
        apb3_hall_if_0_hall_speed_factor_o[8], 
        apb3_hall_if_0_hall_speed_factor_o[7], 
        apb3_hall_if_0_hall_speed_factor_o[6], 
        apb3_hall_if_0_hall_speed_factor_o[5], 
        apb3_hall_if_0_hall_speed_factor_o[4], 
        apb3_hall_if_0_hall_speed_factor_o[3], 
        apb3_hall_if_0_hall_speed_factor_o[2], 
        apb3_hall_if_0_hall_speed_factor_o[1], 
        apb3_hall_if_0_hall_speed_factor_o[0]}), .omega_done_o(
        omega_done_o), .omega_out_o({HALL_INTERFACE_1_omega_out_o[17], 
        HALL_INTERFACE_1_omega_out_o[16], 
        HALL_INTERFACE_1_omega_out_o[15], 
        HALL_INTERFACE_1_omega_out_o[14], 
        HALL_INTERFACE_1_omega_out_o[13], 
        HALL_INTERFACE_1_omega_out_o[12], 
        HALL_INTERFACE_1_omega_out_o[11], 
        HALL_INTERFACE_1_omega_out_o[10], 
        HALL_INTERFACE_1_omega_out_o[9], 
        HALL_INTERFACE_1_omega_out_o[8], 
        HALL_INTERFACE_1_omega_out_o[7], 
        HALL_INTERFACE_1_omega_out_o[6], 
        HALL_INTERFACE_1_omega_out_o[5], 
        HALL_INTERFACE_1_omega_out_o[4], 
        HALL_INTERFACE_1_omega_out_o[3], 
        HALL_INTERFACE_1_omega_out_o[2], 
        HALL_INTERFACE_1_omega_out_o[1], 
        HALL_INTERFACE_1_omega_out_o_0}), .angle_out_raw_o({
        HALL_INTERFACE_1_angle_out_raw_o[17], 
        HALL_INTERFACE_1_angle_out_raw_o[16], 
        HALL_INTERFACE_1_angle_out_raw_o[15], 
        HALL_INTERFACE_1_angle_out_raw_o[14], 
        HALL_INTERFACE_1_angle_out_raw_o[13], 
        HALL_INTERFACE_1_angle_out_raw_o[12], 
        HALL_INTERFACE_1_angle_out_raw_o[11], 
        HALL_INTERFACE_1_angle_out_raw_o[10], 
        HALL_INTERFACE_1_angle_out_raw_o[9], 
        HALL_INTERFACE_1_angle_out_raw_o[8], 
        HALL_INTERFACE_1_angle_out_raw_o[7], 
        HALL_INTERFACE_1_angle_out_raw_o[6], 
        HALL_INTERFACE_1_angle_out_raw_o[5], angle_out_raw_o[4], 
        angle_out_raw_o[3], angle_out_raw_o[2], angle_out_raw_o[1], 
        angle_out_raw_o[0]}), .theta_output_o({
        HALL_INTERFACE_1_theta_output_o[17], 
        HALL_INTERFACE_1_theta_output_o[16], 
        HALL_INTERFACE_1_theta_output_o[15], 
        HALL_INTERFACE_1_theta_output_o[14], 
        HALL_INTERFACE_1_theta_output_o[13], 
        HALL_INTERFACE_1_theta_output_o[12], 
        HALL_INTERFACE_1_theta_output_o[11], 
        HALL_INTERFACE_1_theta_output_o[10], 
        HALL_INTERFACE_1_theta_output_o[9], 
        HALL_INTERFACE_1_theta_output_o[8], 
        HALL_INTERFACE_1_theta_output_o[7], 
        HALL_INTERFACE_1_theta_output_o[6], 
        HALL_INTERFACE_1_theta_output_o[5], theta_output_o[4], 
        theta_output_o[3], theta_output_o[2], theta_output_o[1], 
        theta_output_o[0]}));
    
        work_apb3_hall_if_apb3_hall_if_32_12_12_6_18_2_g_APB3_IF_DATA_WIDTHg_CONST_WIDTHg_ADC_OUT_WIDTHg_ADC_CONFIG_REG_WIDTHg_STD_IO_WIDTH 
        apb3_hall_if_0 (.apb3_en_if_1_idq_pi_ki_o({
        apb3_en_if_1_idq_pi_ki_o[17], apb3_en_if_1_idq_pi_ki_o[16], 
        apb3_en_if_1_idq_pi_ki_o[15], apb3_en_if_1_idq_pi_ki_o[14], 
        apb3_en_if_1_idq_pi_ki_o[13], apb3_en_if_1_idq_pi_ki_o[12], 
        apb3_en_if_1_idq_pi_ki_o[11], apb3_en_if_1_idq_pi_ki_o[10], 
        apb3_en_if_1_idq_pi_ki_o[9], apb3_en_if_1_idq_pi_ki_o[8], 
        apb3_en_if_1_idq_pi_ki_o[7], apb3_en_if_1_idq_pi_ki_o[6], 
        apb3_en_if_1_idq_pi_ki_o[5], apb3_en_if_1_idq_pi_ki_o[4], 
        apb3_en_if_1_idq_pi_ki_o[3], apb3_en_if_1_idq_pi_ki_o[2], 
        apb3_en_if_1_idq_pi_ki_o[1], apb3_en_if_1_idq_pi_ki_o[0]}), 
        .MC_System_0_AMBA_SLAVE_0_PWDATA({
        MC_System_0_AMBA_SLAVE_0_PWDATA[17], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[16], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[15], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[14], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[13], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[12], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[11], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[10], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[9], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[8], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[7], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[6], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[5], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[4], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[3], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[2], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[1], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[0]}), 
        .apb3_en_if_1_idq_pi_kp_o({apb3_en_if_1_idq_pi_kp_o[17], 
        apb3_en_if_1_idq_pi_kp_o[16], apb3_en_if_1_idq_pi_kp_o[15], 
        apb3_en_if_1_idq_pi_kp_o[14], apb3_en_if_1_idq_pi_kp_o[13], 
        apb3_en_if_1_idq_pi_kp_o[12], apb3_en_if_1_idq_pi_kp_o[11], 
        apb3_en_if_1_idq_pi_kp_o[10], apb3_en_if_1_idq_pi_kp_o[9], 
        apb3_en_if_1_idq_pi_kp_o[8], apb3_en_if_1_idq_pi_kp_o[7], 
        apb3_en_if_1_idq_pi_kp_o[6], apb3_en_if_1_idq_pi_kp_o[5], 
        apb3_en_if_1_idq_pi_kp_o[4], apb3_en_if_1_idq_pi_kp_o[3], 
        apb3_en_if_1_idq_pi_kp_o[2], apb3_en_if_1_idq_pi_kp_o[1], 
        apb3_en_if_1_idq_pi_kp_o[0]}), .apb3_en_if_1_olmng_dv_o({
        apb3_en_if_1_olmng_dv_o[17], apb3_en_if_1_olmng_dv_o[16], 
        apb3_en_if_1_olmng_dv_o[15], apb3_en_if_1_olmng_dv_o[14], 
        apb3_en_if_1_olmng_dv_o[13], apb3_en_if_1_olmng_dv_o[12], 
        apb3_en_if_1_olmng_dv_o[11], apb3_en_if_1_olmng_dv_o[10], 
        apb3_en_if_1_olmng_dv_o[9], apb3_en_if_1_olmng_dv_o[8], 
        apb3_en_if_1_olmng_dv_o[7], apb3_en_if_1_olmng_dv_o[6], 
        apb3_en_if_1_olmng_dv_o[5], apb3_en_if_1_olmng_dv_o[4], 
        apb3_en_if_1_olmng_dv_o[3], apb3_en_if_1_olmng_dv_o[2], 
        apb3_en_if_1_olmng_dv_o[1], apb3_en_if_1_olmng_dv_o[0]}), 
        .apb3_en_if_1_olmng_iq_ref_in_o({
        apb3_en_if_1_olmng_iq_ref_in_o[17], 
        apb3_en_if_1_olmng_iq_ref_in_o[16], 
        apb3_en_if_1_olmng_iq_ref_in_o[15], 
        apb3_en_if_1_olmng_iq_ref_in_o[14], 
        apb3_en_if_1_olmng_iq_ref_in_o[13], 
        apb3_en_if_1_olmng_iq_ref_in_o[12], 
        apb3_en_if_1_olmng_iq_ref_in_o[11], 
        apb3_en_if_1_olmng_iq_ref_in_o[10], 
        apb3_en_if_1_olmng_iq_ref_in_o[9], 
        apb3_en_if_1_olmng_iq_ref_in_o[8], 
        apb3_en_if_1_olmng_iq_ref_in_o[7], 
        apb3_en_if_1_olmng_iq_ref_in_o[6], 
        apb3_en_if_1_olmng_iq_ref_in_o[5], 
        apb3_en_if_1_olmng_iq_ref_in_o[4], 
        apb3_en_if_1_olmng_iq_ref_in_o[3], 
        apb3_en_if_1_olmng_iq_ref_in_o[2], 
        apb3_en_if_1_olmng_iq_ref_in_o[1], 
        apb3_en_if_1_olmng_iq_ref_in_o[0]}), 
        .apb3_en_if_1_olmng_theta_factor_o({
        apb3_en_if_1_olmng_theta_factor_o[17], 
        apb3_en_if_1_olmng_theta_factor_o[16], 
        apb3_en_if_1_olmng_theta_factor_o[15], 
        apb3_en_if_1_olmng_theta_factor_o[14], 
        apb3_en_if_1_olmng_theta_factor_o[13], 
        apb3_en_if_1_olmng_theta_factor_o[12], 
        apb3_en_if_1_olmng_theta_factor_o[11], 
        apb3_en_if_1_olmng_theta_factor_o[10], 
        apb3_en_if_1_olmng_theta_factor_o[9], 
        apb3_en_if_1_olmng_theta_factor_o[8], 
        apb3_en_if_1_olmng_theta_factor_o[7], 
        apb3_en_if_1_olmng_theta_factor_o[6], 
        apb3_en_if_1_olmng_theta_factor_o[5], 
        apb3_en_if_1_olmng_theta_factor_o[4], 
        apb3_en_if_1_olmng_theta_factor_o[3], 
        apb3_en_if_1_olmng_theta_factor_o[2], 
        apb3_en_if_1_olmng_theta_factor_o[1], 
        apb3_en_if_1_olmng_theta_factor_o[0]}), 
        .apb3_en_if_1_pwm_dead_time_val_o({
        apb3_en_if_1_pwm_dead_time_val_o[17], 
        apb3_en_if_1_pwm_dead_time_val_o[16], 
        apb3_en_if_1_pwm_dead_time_val_o[15], 
        apb3_en_if_1_pwm_dead_time_val_o[14], 
        apb3_en_if_1_pwm_dead_time_val_o[13], 
        apb3_en_if_1_pwm_dead_time_val_o[12], 
        apb3_en_if_1_pwm_dead_time_val_o[11], 
        apb3_en_if_1_pwm_dead_time_val_o[10], 
        apb3_en_if_1_pwm_dead_time_val_o[9], 
        apb3_en_if_1_pwm_dead_time_val_o[8], 
        apb3_en_if_1_pwm_dead_time_val_o[7], 
        apb3_en_if_1_pwm_dead_time_val_o[6], 
        apb3_en_if_1_pwm_dead_time_val_o[5], 
        apb3_en_if_1_pwm_dead_time_val_o[4], 
        apb3_en_if_1_pwm_dead_time_val_o[3], 
        apb3_en_if_1_pwm_dead_time_val_o[2], 
        apb3_en_if_1_pwm_dead_time_val_o[1], 
        apb3_en_if_1_pwm_dead_time_val_o[0]}), 
        .apb3_en_if_1_pwm_delay_time_val_o({
        apb3_en_if_1_pwm_delay_time_val_o[17], 
        apb3_en_if_1_pwm_delay_time_val_o[16], 
        apb3_en_if_1_pwm_delay_time_val_o[15], 
        apb3_en_if_1_pwm_delay_time_val_o[14], 
        apb3_en_if_1_pwm_delay_time_val_o[13], 
        apb3_en_if_1_pwm_delay_time_val_o[12], 
        apb3_en_if_1_pwm_delay_time_val_o[11], 
        apb3_en_if_1_pwm_delay_time_val_o[10], 
        apb3_en_if_1_pwm_delay_time_val_o[9], 
        apb3_en_if_1_pwm_delay_time_val_o[8], 
        apb3_en_if_1_pwm_delay_time_val_o[7], 
        apb3_en_if_1_pwm_delay_time_val_o[6], 
        apb3_en_if_1_pwm_delay_time_val_o[5], 
        apb3_en_if_1_pwm_delay_time_val_o[4], 
        apb3_en_if_1_pwm_delay_time_val_o[3], 
        apb3_en_if_1_pwm_delay_time_val_o[2], 
        apb3_en_if_1_pwm_delay_time_val_o[1], 
        apb3_en_if_1_pwm_delay_time_val_o[0]}), 
        .apb3_en_if_1_pwm_gain_val_o({apb3_en_if_1_pwm_gain_val_o[17], 
        apb3_en_if_1_pwm_gain_val_o[16], 
        apb3_en_if_1_pwm_gain_val_o[15], 
        apb3_en_if_1_pwm_gain_val_o[14], 
        apb3_en_if_1_pwm_gain_val_o[13], 
        apb3_en_if_1_pwm_gain_val_o[12], 
        apb3_en_if_1_pwm_gain_val_o[11], 
        apb3_en_if_1_pwm_gain_val_o[10], 
        apb3_en_if_1_pwm_gain_val_o[9], apb3_en_if_1_pwm_gain_val_o[8], 
        apb3_en_if_1_pwm_gain_val_o[7], apb3_en_if_1_pwm_gain_val_o[6], 
        apb3_en_if_1_pwm_gain_val_o[5], apb3_en_if_1_pwm_gain_val_o[4], 
        apb3_en_if_1_pwm_gain_val_o[3], apb3_en_if_1_pwm_gain_val_o[2], 
        apb3_en_if_1_pwm_gain_val_o[1]}), 
        .apb3_en_if_1_pwm_period_val_o({
        apb3_en_if_1_pwm_period_val_o[17], 
        apb3_en_if_1_pwm_period_val_o[16], 
        apb3_en_if_1_pwm_period_val_o[15], 
        apb3_en_if_1_pwm_period_val_o[14], 
        apb3_en_if_1_pwm_period_val_o[13], 
        apb3_en_if_1_pwm_period_val_o[12], 
        apb3_en_if_1_pwm_period_val_o[11], 
        apb3_en_if_1_pwm_period_val_o[10], 
        apb3_en_if_1_pwm_period_val_o[9], 
        apb3_en_if_1_pwm_period_val_o[8], 
        apb3_en_if_1_pwm_period_val_o[7], 
        apb3_en_if_1_pwm_period_val_o[6], 
        apb3_en_if_1_pwm_period_val_o[5], 
        apb3_en_if_1_pwm_period_val_o[4], 
        apb3_en_if_1_pwm_period_val_o[3], 
        apb3_en_if_1_pwm_period_val_o[2], 
        apb3_en_if_1_pwm_period_val_o[1], 
        apb3_en_if_1_pwm_period_val_o[0]}), 
        .apb3_en_if_1_rate_limit_rate_cnt_o({
        apb3_en_if_1_rate_limit_rate_cnt_o[17], 
        apb3_en_if_1_rate_limit_rate_cnt_o[16], 
        apb3_en_if_1_rate_limit_rate_cnt_o[15], 
        apb3_en_if_1_rate_limit_rate_cnt_o[14], 
        apb3_en_if_1_rate_limit_rate_cnt_o[13], 
        apb3_en_if_1_rate_limit_rate_cnt_o[12], 
        apb3_en_if_1_rate_limit_rate_cnt_o[11], 
        apb3_en_if_1_rate_limit_rate_cnt_o[10], 
        apb3_en_if_1_rate_limit_rate_cnt_o[9], 
        apb3_en_if_1_rate_limit_rate_cnt_o[8], 
        apb3_en_if_1_rate_limit_rate_cnt_o[7], 
        apb3_en_if_1_rate_limit_rate_cnt_o[6], 
        apb3_en_if_1_rate_limit_rate_cnt_o[5], 
        apb3_en_if_1_rate_limit_rate_cnt_o[4], 
        apb3_en_if_1_rate_limit_rate_cnt_o[3], 
        apb3_en_if_1_rate_limit_rate_cnt_o[2], 
        apb3_en_if_1_rate_limit_rate_cnt_o[1], 
        apb3_en_if_1_rate_limit_rate_cnt_o[0]}), 
        .apb3_en_if_1_rate_limit_ref_in_o({
        apb3_en_if_1_rate_limit_ref_in_o[17], 
        apb3_en_if_1_rate_limit_ref_in_o[16], 
        apb3_en_if_1_rate_limit_ref_in_o[15], 
        apb3_en_if_1_rate_limit_ref_in_o[14], 
        apb3_en_if_1_rate_limit_ref_in_o[13], 
        apb3_en_if_1_rate_limit_ref_in_o[12], 
        apb3_en_if_1_rate_limit_ref_in_o[11], 
        apb3_en_if_1_rate_limit_ref_in_o[10], 
        apb3_en_if_1_rate_limit_ref_in_o[9], 
        apb3_en_if_1_rate_limit_ref_in_o[8], 
        apb3_en_if_1_rate_limit_ref_in_o[7], 
        apb3_en_if_1_rate_limit_ref_in_o[6], 
        apb3_en_if_1_rate_limit_ref_in_o[5], 
        apb3_en_if_1_rate_limit_ref_in_o[4], 
        apb3_en_if_1_rate_limit_ref_in_o[3], 
        apb3_en_if_1_rate_limit_ref_in_o[2], 
        apb3_en_if_1_rate_limit_ref_in_o[1], 
        apb3_en_if_1_rate_limit_ref_in_o[0]}), 
        .apb3_en_if_1_rate_limit_slew_cnt_o({
        apb3_en_if_1_rate_limit_slew_cnt_o[17], 
        apb3_en_if_1_rate_limit_slew_cnt_o[16], 
        apb3_en_if_1_rate_limit_slew_cnt_o[15], 
        apb3_en_if_1_rate_limit_slew_cnt_o[14], 
        apb3_en_if_1_rate_limit_slew_cnt_o[13], 
        apb3_en_if_1_rate_limit_slew_cnt_o[12], 
        apb3_en_if_1_rate_limit_slew_cnt_o[11], 
        apb3_en_if_1_rate_limit_slew_cnt_o[10], 
        apb3_en_if_1_rate_limit_slew_cnt_o[9], 
        apb3_en_if_1_rate_limit_slew_cnt_o[8], 
        apb3_en_if_1_rate_limit_slew_cnt_o[7], 
        apb3_en_if_1_rate_limit_slew_cnt_o[6], 
        apb3_en_if_1_rate_limit_slew_cnt_o[5], 
        apb3_en_if_1_rate_limit_slew_cnt_o[4], 
        apb3_en_if_1_rate_limit_slew_cnt_o[3], 
        apb3_en_if_1_rate_limit_slew_cnt_o[2], 
        apb3_en_if_1_rate_limit_slew_cnt_o[1], 
        apb3_en_if_1_rate_limit_slew_cnt_o[0]}), 
        .apb3_en_if_1_seq_cntl_cl_omega_o({
        apb3_en_if_1_seq_cntl_cl_omega_o[17], 
        apb3_en_if_1_seq_cntl_cl_omega_o[16], 
        apb3_en_if_1_seq_cntl_cl_omega_o[15], 
        apb3_en_if_1_seq_cntl_cl_omega_o[14], 
        apb3_en_if_1_seq_cntl_cl_omega_o[13], 
        apb3_en_if_1_seq_cntl_cl_omega_o[12], 
        apb3_en_if_1_seq_cntl_cl_omega_o[11], 
        apb3_en_if_1_seq_cntl_cl_omega_o[10], 
        apb3_en_if_1_seq_cntl_cl_omega_o[9], 
        apb3_en_if_1_seq_cntl_cl_omega_o[8], 
        apb3_en_if_1_seq_cntl_cl_omega_o[7], 
        apb3_en_if_1_seq_cntl_cl_omega_o[6], 
        apb3_en_if_1_seq_cntl_cl_omega_o[5], 
        apb3_en_if_1_seq_cntl_cl_omega_o[4], 
        apb3_en_if_1_seq_cntl_cl_omega_o[3], 
        apb3_en_if_1_seq_cntl_cl_omega_o[2], 
        apb3_en_if_1_seq_cntl_cl_omega_o[1], 
        apb3_en_if_1_seq_cntl_cl_omega_o[0]}), 
        .apb3_en_if_1_speed_pi_ki_o({apb3_en_if_1_speed_pi_ki_o[17], 
        apb3_en_if_1_speed_pi_ki_o[16], apb3_en_if_1_speed_pi_ki_o[15], 
        apb3_en_if_1_speed_pi_ki_o[14], apb3_en_if_1_speed_pi_ki_o[13], 
        apb3_en_if_1_speed_pi_ki_o[12], apb3_en_if_1_speed_pi_ki_o[11], 
        apb3_en_if_1_speed_pi_ki_o[10], apb3_en_if_1_speed_pi_ki_o[9], 
        apb3_en_if_1_speed_pi_ki_o[8], apb3_en_if_1_speed_pi_ki_o[7], 
        apb3_en_if_1_speed_pi_ki_o[6], apb3_en_if_1_speed_pi_ki_o[5], 
        apb3_en_if_1_speed_pi_ki_o[4], apb3_en_if_1_speed_pi_ki_o[3], 
        apb3_en_if_1_speed_pi_ki_o[2], apb3_en_if_1_speed_pi_ki_o[1], 
        apb3_en_if_1_speed_pi_ki_o[0]}), .apb3_en_if_1_speed_pi_kp_o({
        apb3_en_if_1_speed_pi_kp_o[17], apb3_en_if_1_speed_pi_kp_o[16], 
        apb3_en_if_1_speed_pi_kp_o[15], apb3_en_if_1_speed_pi_kp_o[14], 
        apb3_en_if_1_speed_pi_kp_o[13], apb3_en_if_1_speed_pi_kp_o[12], 
        apb3_en_if_1_speed_pi_kp_o[11], apb3_en_if_1_speed_pi_kp_o[10], 
        apb3_en_if_1_speed_pi_kp_o[9], apb3_en_if_1_speed_pi_kp_o[8], 
        apb3_en_if_1_speed_pi_kp_o[7], apb3_en_if_1_speed_pi_kp_o[6], 
        apb3_en_if_1_speed_pi_kp_o[5], apb3_en_if_1_speed_pi_kp_o[4], 
        apb3_en_if_1_speed_pi_kp_o[3], apb3_en_if_1_speed_pi_kp_o[2], 
        apb3_en_if_1_speed_pi_kp_o[1], apb3_en_if_1_speed_pi_kp_o[0]}), 
        .apb3_en_if_1_seq_cntl_config_o({
        apb3_en_if_1_seq_cntl_config_o[3], 
        apb3_en_if_1_seq_cntl_config_o[2], 
        apb3_en_if_1_seq_cntl_config_o[1], 
        apb3_en_if_1_seq_cntl_config_o[0]}), 
        .apb3_hall_if_0_hall_filter_factor_o({
        apb3_hall_if_0_hall_filter_factor_o[3], 
        apb3_hall_if_0_hall_filter_factor_o[2], 
        apb3_hall_if_0_hall_filter_factor_o[1], 
        apb3_hall_if_0_hall_filter_factor_o[0]}), 
        .apb3_en_if_1_auto_restart_no_o({
        apb3_en_if_1_auto_restart_no_o[3], 
        apb3_en_if_1_auto_restart_no_o[2], 
        apb3_en_if_1_auto_restart_no_o[1], 
        apb3_en_if_1_auto_restart_no_o[0]}), 
        .apb3_en_if_1_adc_control_reg_val_o({
        apb3_en_if_1_adc_control_reg_val_o[5], 
        apb3_en_if_1_adc_control_reg_val_o[4], 
        apb3_en_if_1_adc_control_reg_val_o[3], 
        apb3_en_if_1_adc_control_reg_val_o[2], 
        apb3_en_if_1_adc_control_reg_val_o[1], 
        apb3_en_if_1_adc_control_reg_val_o[0]}), 
        .apb3_en_if_1_adc_channel_ch0_o({
        apb3_en_if_1_adc_channel_ch0_o[15], 
        apb3_en_if_1_adc_channel_ch0_o[14], 
        apb3_en_if_1_adc_channel_ch0_o[13], 
        apb3_en_if_1_adc_channel_ch0_o[12], 
        apb3_en_if_1_adc_channel_ch0_o[11], 
        apb3_en_if_1_adc_channel_ch0_o[10], 
        apb3_en_if_1_adc_channel_ch0_o[9], 
        apb3_en_if_1_adc_channel_ch0_o[8], 
        apb3_en_if_1_adc_channel_ch0_o[7], 
        apb3_en_if_1_adc_channel_ch0_o[6], 
        apb3_en_if_1_adc_channel_ch0_o[5], 
        apb3_en_if_1_adc_channel_ch0_o[4], 
        apb3_en_if_1_adc_channel_ch0_o[3], 
        apb3_en_if_1_adc_channel_ch0_o[2], 
        apb3_en_if_1_adc_channel_ch0_o[1], 
        apb3_en_if_1_adc_channel_ch0_o[0]}), 
        .apb3_en_if_1_adc_channel_ch1_o({
        apb3_en_if_1_adc_channel_ch1_o[15], 
        apb3_en_if_1_adc_channel_ch1_o[14], 
        apb3_en_if_1_adc_channel_ch1_o[13], 
        apb3_en_if_1_adc_channel_ch1_o[12], 
        apb3_en_if_1_adc_channel_ch1_o[11], 
        apb3_en_if_1_adc_channel_ch1_o[10], 
        apb3_en_if_1_adc_channel_ch1_o[9], 
        apb3_en_if_1_adc_channel_ch1_o[8], 
        apb3_en_if_1_adc_channel_ch1_o[7], 
        apb3_en_if_1_adc_channel_ch1_o[6], 
        apb3_en_if_1_adc_channel_ch1_o[5], 
        apb3_en_if_1_adc_channel_ch1_o[4], 
        apb3_en_if_1_adc_channel_ch1_o[3], 
        apb3_en_if_1_adc_channel_ch1_o[2], 
        apb3_en_if_1_adc_channel_ch1_o[1], 
        apb3_en_if_1_adc_channel_ch1_o[0]}), 
        .apb3_en_if_1_adc_channel_ch2_o({
        apb3_en_if_1_adc_channel_ch2_o[15], 
        apb3_en_if_1_adc_channel_ch2_o[14], 
        apb3_en_if_1_adc_channel_ch2_o[13], 
        apb3_en_if_1_adc_channel_ch2_o[12], 
        apb3_en_if_1_adc_channel_ch2_o[11], 
        apb3_en_if_1_adc_channel_ch2_o[10], 
        apb3_en_if_1_adc_channel_ch2_o[9], 
        apb3_en_if_1_adc_channel_ch2_o[8], 
        apb3_en_if_1_adc_channel_ch2_o[7], 
        apb3_en_if_1_adc_channel_ch2_o[6], 
        apb3_en_if_1_adc_channel_ch2_o[5], 
        apb3_en_if_1_adc_channel_ch2_o[4], 
        apb3_en_if_1_adc_channel_ch2_o[3], 
        apb3_en_if_1_adc_channel_ch2_o[2], 
        apb3_en_if_1_adc_channel_ch2_o[1], 
        apb3_en_if_1_adc_channel_ch2_o[0]}), 
        .apb3_en_if_1_adc_channel_ch3_o({
        apb3_en_if_1_adc_channel_ch3_o[15], 
        apb3_en_if_1_adc_channel_ch3_o[14], 
        apb3_en_if_1_adc_channel_ch3_o[13], 
        apb3_en_if_1_adc_channel_ch3_o[12], 
        apb3_en_if_1_adc_channel_ch3_o[11], 
        apb3_en_if_1_adc_channel_ch3_o[10], 
        apb3_en_if_1_adc_channel_ch3_o[9], 
        apb3_en_if_1_adc_channel_ch3_o[8], 
        apb3_en_if_1_adc_channel_ch3_o[7], 
        apb3_en_if_1_adc_channel_ch3_o[6], 
        apb3_en_if_1_adc_channel_ch3_o[5], 
        apb3_en_if_1_adc_channel_ch3_o[4], 
        apb3_en_if_1_adc_channel_ch3_o[3], 
        apb3_en_if_1_adc_channel_ch3_o[2], 
        apb3_en_if_1_adc_channel_ch3_o[1], 
        apb3_en_if_1_adc_channel_ch3_o[0]}), 
        .apb3_en_if_1_adc_oc_thresh_o({
        apb3_en_if_1_adc_oc_thresh_o[17], 
        apb3_en_if_1_adc_oc_thresh_o[16], 
        apb3_en_if_1_adc_oc_thresh_o[15], 
        apb3_en_if_1_adc_oc_thresh_o[14], 
        apb3_en_if_1_adc_oc_thresh_o[13], 
        apb3_en_if_1_adc_oc_thresh_o[12], 
        apb3_en_if_1_adc_oc_thresh_o[11], 
        apb3_en_if_1_adc_oc_thresh_o[10], 
        apb3_en_if_1_adc_oc_thresh_o[9], 
        apb3_en_if_1_adc_oc_thresh_o[8], 
        apb3_en_if_1_adc_oc_thresh_o[7], 
        apb3_en_if_1_adc_oc_thresh_o[6], 
        apb3_en_if_1_adc_oc_thresh_o[5], 
        apb3_en_if_1_adc_oc_thresh_o[4], 
        apb3_en_if_1_adc_oc_thresh_o[3], 
        apb3_en_if_1_adc_oc_thresh_o[2], 
        apb3_en_if_1_adc_oc_thresh_o[1], 
        apb3_en_if_1_adc_oc_thresh_o[0]}), 
        .apb3_en_if_1_adc_scale_val_o({
        apb3_en_if_1_adc_scale_val_o[17], 
        apb3_en_if_1_adc_scale_val_o[16], 
        apb3_en_if_1_adc_scale_val_o[15], 
        apb3_en_if_1_adc_scale_val_o[14], 
        apb3_en_if_1_adc_scale_val_o[13], 
        apb3_en_if_1_adc_scale_val_o[12], 
        apb3_en_if_1_adc_scale_val_o[11], 
        apb3_en_if_1_adc_scale_val_o[10], 
        apb3_en_if_1_adc_scale_val_o[9], 
        apb3_en_if_1_adc_scale_val_o[8], 
        apb3_en_if_1_adc_scale_val_o[7], 
        apb3_en_if_1_adc_scale_val_o[6], 
        apb3_en_if_1_adc_scale_val_o[5], 
        apb3_en_if_1_adc_scale_val_o[4], 
        apb3_en_if_1_adc_scale_val_o[3], 
        apb3_en_if_1_adc_scale_val_o[2], 
        apb3_en_if_1_adc_scale_val_o[1], 
        apb3_en_if_1_adc_scale_val_o[0]}), 
        .apb3_hall_if_0_hall_speed_factor_o({
        apb3_hall_if_0_hall_speed_factor_o[17], 
        apb3_hall_if_0_hall_speed_factor_o[16], 
        apb3_hall_if_0_hall_speed_factor_o[15], 
        apb3_hall_if_0_hall_speed_factor_o[14], 
        apb3_hall_if_0_hall_speed_factor_o[13], 
        apb3_hall_if_0_hall_speed_factor_o[12], 
        apb3_hall_if_0_hall_speed_factor_o[11], 
        apb3_hall_if_0_hall_speed_factor_o[10], 
        apb3_hall_if_0_hall_speed_factor_o[9], 
        apb3_hall_if_0_hall_speed_factor_o[8], 
        apb3_hall_if_0_hall_speed_factor_o[7], 
        apb3_hall_if_0_hall_speed_factor_o[6], 
        apb3_hall_if_0_hall_speed_factor_o[5], 
        apb3_hall_if_0_hall_speed_factor_o[4], 
        apb3_hall_if_0_hall_speed_factor_o[3], 
        apb3_hall_if_0_hall_speed_factor_o[2], 
        apb3_hall_if_0_hall_speed_factor_o[1], 
        apb3_hall_if_0_hall_speed_factor_o[0]}), 
        .MC_System_0_AMBA_SLAVE_0_PRDATA({
        MC_System_0_AMBA_SLAVE_0_PRDATA[19]}), .prdata_o_1_iv_10_13({
        prdata_o_1_iv_10_13[10]}), .prdata_o_1_iv_9({
        prdata_o_1_iv_9[16]}), .prdata_o_1_0_iv_0_13({
        prdata_o_1_0_iv_0_13[1]}), .prdata_o_1_iv_10_11({
        prdata_o_1_iv_10_11[10]}), .MC_System_0_AMBA_SLAVE_0_PADDR({
        MC_System_0_AMBA_SLAVE_0_PADDR[11], 
        MC_System_0_AMBA_SLAVE_0_PADDR[10], 
        MC_System_0_AMBA_SLAVE_0_PADDR[9], 
        MC_System_0_AMBA_SLAVE_0_PADDR[8], 
        MC_System_0_AMBA_SLAVE_0_PADDR[7], 
        MC_System_0_AMBA_SLAVE_0_PADDR[6], 
        MC_System_0_AMBA_SLAVE_0_PADDR[5], 
        MC_System_0_AMBA_SLAVE_0_PADDR[4], 
        MC_System_0_AMBA_SLAVE_0_PADDR[3], 
        MC_System_0_AMBA_SLAVE_0_PADDR[2], 
        MC_System_0_AMBA_SLAVE_0_PADDR[1], 
        MC_System_0_AMBA_SLAVE_0_PADDR[0]}), 
        .FOC_TRANSFORMS_0_ialpha_o_m_6(FOC_TRANSFORMS_0_ialpha_o_m[9]), 
        .FOC_TRANSFORMS_0_valpha_o_m_0(FOC_TRANSFORMS_0_valpha_o_m_0), 
        .FOC_TRANSFORMS_0_valpha_o_m_5(FOC_TRANSFORMS_0_valpha_o_m_5), 
        .SEQ_CONTROLLER_0_state_o_0(SEQ_CONTROLLER_0_state_o[1]), 
        .SEQ_CONTROLLER_0_state_o_2(SEQ_CONTROLLER_0_state_o[3]), 
        .HALL_INTERFACE_1_angle_out_raw_o({
        HALL_INTERFACE_1_angle_out_raw_o[17], 
        HALL_INTERFACE_1_angle_out_raw_o[16], 
        HALL_INTERFACE_1_angle_out_raw_o[15], 
        HALL_INTERFACE_1_angle_out_raw_o[14], 
        HALL_INTERFACE_1_angle_out_raw_o[13], 
        HALL_INTERFACE_1_angle_out_raw_o[12], 
        HALL_INTERFACE_1_angle_out_raw_o[11], 
        HALL_INTERFACE_1_angle_out_raw_o[10], 
        HALL_INTERFACE_1_angle_out_raw_o[9], 
        HALL_INTERFACE_1_angle_out_raw_o[8], 
        HALL_INTERFACE_1_angle_out_raw_o[7], 
        HALL_INTERFACE_1_angle_out_raw_o[6], 
        HALL_INTERFACE_1_angle_out_raw_o[5]}), 
        .HALL_INTERFACE_1_theta_output_o({
        HALL_INTERFACE_1_theta_output_o[17], 
        HALL_INTERFACE_1_theta_output_o[16], 
        HALL_INTERFACE_1_theta_output_o[15], 
        HALL_INTERFACE_1_theta_output_o[14], 
        HALL_INTERFACE_1_theta_output_o[13], 
        HALL_INTERFACE_1_theta_output_o[12], 
        HALL_INTERFACE_1_theta_output_o[11], 
        HALL_INTERFACE_1_theta_output_o[10], 
        HALL_INTERFACE_1_theta_output_o[9], 
        HALL_INTERFACE_1_theta_output_o[8], 
        HALL_INTERFACE_1_theta_output_o[7], 
        HALL_INTERFACE_1_theta_output_o[6], 
        HALL_INTERFACE_1_theta_output_o[5]}), 
        .adc_interface_0_result_ch3_o_m_4(
        adc_interface_0_result_ch3_o_m[9]), .FOC_TRANSFORMS_0_ialpha_o({
        FOC_TRANSFORMS_0_ialpha_o[17], FOC_TRANSFORMS_0_ialpha_o[16], 
        FOC_TRANSFORMS_0_ialpha_o[15], FOC_TRANSFORMS_0_ialpha_o[14], 
        FOC_TRANSFORMS_0_ialpha_o[13], FOC_TRANSFORMS_0_ialpha_o[12], 
        FOC_TRANSFORMS_0_ialpha_o[11], FOC_TRANSFORMS_0_ialpha_o[10], 
        FOC_TRANSFORMS_0_ialpha_o[9], FOC_TRANSFORMS_0_ialpha_o[8], 
        FOC_TRANSFORMS_0_ialpha_o[7], FOC_TRANSFORMS_0_ialpha_o[6], 
        FOC_TRANSFORMS_0_ialpha_o[5], FOC_TRANSFORMS_0_ialpha_o[4], 
        FOC_TRANSFORMS_0_ialpha_o[3], FOC_TRANSFORMS_0_ialpha_o[2], 
        FOC_TRANSFORMS_0_ialpha_o[1]}), 
        .SPEED_ID_IQ_PI_0_id_pi_output_o({
        SPEED_ID_IQ_PI_0_id_pi_output_o[17], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[16], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[15], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[14], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[13], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[12], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[11], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[10], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[9], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[8], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[7], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[6], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[5], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[4], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[3], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[2], 
        SPEED_ID_IQ_PI_0_id_pi_output_o[1]}), 
        .adc_interface_0_result_ch0_o({
        adc_interface_0_result_ch0_o[11], 
        adc_interface_0_result_ch0_o[10], 
        adc_interface_0_result_ch0_o[9], 
        adc_interface_0_result_ch0_o[8], 
        adc_interface_0_result_ch0_o[7], 
        adc_interface_0_result_ch0_o[6], 
        adc_interface_0_result_ch0_o[5], 
        adc_interface_0_result_ch0_o[4], 
        adc_interface_0_result_ch0_o[3], 
        adc_interface_0_result_ch0_o[2], 
        adc_interface_0_result_ch0_o[1]}), .FOC_TRANSFORMS_0_vbeta_o({
        FOC_TRANSFORMS_0_vbeta_o[17], FOC_TRANSFORMS_0_vbeta_o[16], 
        FOC_TRANSFORMS_0_vbeta_o[15], FOC_TRANSFORMS_0_vbeta_o[14], 
        FOC_TRANSFORMS_0_vbeta_o[13], FOC_TRANSFORMS_0_vbeta_o[12], 
        FOC_TRANSFORMS_0_vbeta_o[11], FOC_TRANSFORMS_0_vbeta_o[10], 
        FOC_TRANSFORMS_0_vbeta_o[9], FOC_TRANSFORMS_0_vbeta_o[8], 
        FOC_TRANSFORMS_0_vbeta_o[7], FOC_TRANSFORMS_0_vbeta_o[6], 
        FOC_TRANSFORMS_0_vbeta_o[5], FOC_TRANSFORMS_0_vbeta_o[4], 
        FOC_TRANSFORMS_0_vbeta_o[3], FOC_TRANSFORMS_0_vbeta_o[2], 
        FOC_TRANSFORMS_0_vbeta_o[1], FOC_TRANSFORMS_0_vbeta_o[0]}), 
        .adc_interface_0_result_ch1_o_5(
        adc_interface_0_result_ch1_o[6]), 
        .adc_interface_0_result_ch1_o_6(
        adc_interface_0_result_ch1_o[7]), 
        .adc_interface_0_result_ch1_o_4(
        adc_interface_0_result_ch1_o[5]), 
        .adc_interface_0_result_ch1_o_2(
        adc_interface_0_result_ch1_o[3]), 
        .adc_interface_0_result_ch1_o_9(
        adc_interface_0_result_ch1_o[10]), 
        .adc_interface_0_result_ch1_o_0(
        adc_interface_0_result_ch1_o[1]), 
        .adc_interface_0_result_ch1_o_3(
        adc_interface_0_result_ch1_o[4]), 
        .adc_interface_0_result_ch1_o_7(
        adc_interface_0_result_ch1_o[8]), 
        .adc_interface_0_result_ch1_o_8(
        adc_interface_0_result_ch1_o[9]), 
        .adc_interface_0_result_ch1_o_10(
        adc_interface_0_result_ch1_o[11]), .FOC_TRANSFORMS_0_id_o_m_0(
        FOC_TRANSFORMS_0_id_o_m[5]), .FOC_TRANSFORMS_0_iq_o({
        FOC_TRANSFORMS_0_iq_o[17], FOC_TRANSFORMS_0_iq_o[16], 
        FOC_TRANSFORMS_0_iq_o[15], FOC_TRANSFORMS_0_iq_o[14], 
        FOC_TRANSFORMS_0_iq_o[13], FOC_TRANSFORMS_0_iq_o[12], 
        FOC_TRANSFORMS_0_iq_o[11], FOC_TRANSFORMS_0_iq_o[10], 
        FOC_TRANSFORMS_0_iq_o[9], FOC_TRANSFORMS_0_iq_o[8], 
        FOC_TRANSFORMS_0_iq_o[7], FOC_TRANSFORMS_0_iq_o[6], 
        FOC_TRANSFORMS_0_iq_o[5], FOC_TRANSFORMS_0_iq_o[4], 
        FOC_TRANSFORMS_0_iq_o[3], FOC_TRANSFORMS_0_iq_o[2], 
        FOC_TRANSFORMS_0_iq_o[1], FOC_TRANSFORMS_0_iq_o[0]}), 
        .SPEED_ID_IQ_PI_0_speed_pi_output_o({
        SPEED_ID_IQ_PI_0_speed_pi_output_o[17], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[16], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[15], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[14], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[13], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[12], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[11], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[10], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[9], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[8], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[7], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[6], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[5], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[4], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[3], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[2], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[1], 
        SPEED_ID_IQ_PI_0_speed_pi_output_o[0]}), 
        .ADC_SCALING_0_ib_adc_o({ADC_SCALING_0_ib_adc_o[17], 
        ADC_SCALING_0_ib_adc_o[16], ADC_SCALING_0_ib_adc_o[15], 
        ADC_SCALING_0_ib_adc_o[14], ADC_SCALING_0_ib_adc_o[13], 
        ADC_SCALING_0_ib_adc_o[12], ADC_SCALING_0_ib_adc_o[11], 
        ADC_SCALING_0_ib_adc_o[10], ADC_SCALING_0_ib_adc_o[9], 
        ADC_SCALING_0_ib_adc_o[8], ADC_SCALING_0_ib_adc_o[7], 
        ADC_SCALING_0_ib_adc_o[6], ADC_SCALING_0_ib_adc_o[5], 
        ADC_SCALING_0_ib_adc_o[4], ADC_SCALING_0_ib_adc_o[3], 
        ADC_SCALING_0_ib_adc_o[2], ADC_SCALING_0_ib_adc_o[1], 
        ADC_SCALING_0_ib_adc_o[0]}), .prdata_o_1_iv_0_6_0(
        prdata_o_1_iv_0_6[12]), .prdata_o_1_iv_0_10({
        prdata_o_1_iv_0_10[15], prdata_o_1_iv_0_10[14]}), 
        .prdata_o_1_0_iv_0_14({prdata_o_1_0_iv_0_14[1]}), 
        .prdata_o_1_iv_10({prdata_o_1_iv_10[16]}), 
        .FOC_TRANSFORMS_0_valpha_o_4(FOC_TRANSFORMS_0_valpha_o[4]), 
        .FOC_TRANSFORMS_0_valpha_o_9(FOC_TRANSFORMS_0_valpha_o[9]), 
        .FOC_TRANSFORMS_0_valpha_o_3(FOC_TRANSFORMS_0_valpha_o[3]), 
        .FOC_TRANSFORMS_0_valpha_o_6(FOC_TRANSFORMS_0_valpha_o[6]), 
        .FOC_TRANSFORMS_0_valpha_o_11(FOC_TRANSFORMS_0_valpha_o[11]), 
        .FOC_TRANSFORMS_0_valpha_o_0(FOC_TRANSFORMS_0_valpha_o[0]), 
        .FOC_TRANSFORMS_0_valpha_o_7(FOC_TRANSFORMS_0_valpha_o[7]), 
        .FOC_TRANSFORMS_0_valpha_o_5(FOC_TRANSFORMS_0_valpha_o[5]), 
        .FOC_TRANSFORMS_0_valpha_o_14(FOC_TRANSFORMS_0_valpha_o[14]), 
        .FOC_TRANSFORMS_0_valpha_o_15(FOC_TRANSFORMS_0_valpha_o[15]), 
        .FOC_TRANSFORMS_0_valpha_o_1(FOC_TRANSFORMS_0_valpha_o[1]), 
        .FOC_TRANSFORMS_0_valpha_o_16(FOC_TRANSFORMS_0_valpha_o[16]), 
        .FOC_TRANSFORMS_0_valpha_o_17(FOC_TRANSFORMS_0_valpha_o[17]), 
        .FOC_TRANSFORMS_0_valpha_o_12(FOC_TRANSFORMS_0_valpha_o[12]), 
        .FOC_TRANSFORMS_0_valpha_o_10(FOC_TRANSFORMS_0_valpha_o[10]), 
        .FOC_TRANSFORMS_0_valpha_o_8(FOC_TRANSFORMS_0_valpha_o[8]), 
        .FOC_TRANSFORMS_0_valpha_o_13(FOC_TRANSFORMS_0_valpha_o[13]), 
        .prdata_o_1_iv_0_7_0({prdata_o_1_iv_0_7_0[13]}), 
        .SPEED_ID_IQ_PI_0_iq_pi_output_o_11(
        SPEED_ID_IQ_PI_0_iq_pi_output_o[11]), 
        .SPEED_ID_IQ_PI_0_iq_pi_output_o_8(
        SPEED_ID_IQ_PI_0_iq_pi_output_o[8]), 
        .SPEED_ID_IQ_PI_0_iq_pi_output_o_1(
        SPEED_ID_IQ_PI_0_iq_pi_output_o[1]), 
        .SPEED_ID_IQ_PI_0_iq_pi_output_o_10(
        SPEED_ID_IQ_PI_0_iq_pi_output_o[10]), 
        .SPEED_ID_IQ_PI_0_iq_pi_output_o_15(
        SPEED_ID_IQ_PI_0_iq_pi_output_o[15]), 
        .SPEED_ID_IQ_PI_0_iq_pi_output_o_14(
        SPEED_ID_IQ_PI_0_iq_pi_output_o[14]), 
        .SPEED_ID_IQ_PI_0_iq_pi_output_o_16(
        SPEED_ID_IQ_PI_0_iq_pi_output_o[16]), 
        .SPEED_ID_IQ_PI_0_iq_pi_output_o_6(
        SPEED_ID_IQ_PI_0_iq_pi_output_o[6]), 
        .SPEED_ID_IQ_PI_0_iq_pi_output_o_17(
        SPEED_ID_IQ_PI_0_iq_pi_output_o[17]), 
        .SPEED_ID_IQ_PI_0_iq_pi_output_o_2(
        SPEED_ID_IQ_PI_0_iq_pi_output_o[2]), 
        .SPEED_ID_IQ_PI_0_iq_pi_output_o_5(
        SPEED_ID_IQ_PI_0_iq_pi_output_o[5]), 
        .SPEED_ID_IQ_PI_0_iq_pi_output_o_3(
        SPEED_ID_IQ_PI_0_iq_pi_output_o[3]), 
        .SPEED_ID_IQ_PI_0_iq_pi_output_o_4(
        SPEED_ID_IQ_PI_0_iq_pi_output_o[4]), 
        .SPEED_ID_IQ_PI_0_iq_pi_output_o_0(
        SPEED_ID_IQ_PI_0_iq_pi_output_o[0]), 
        .SPEED_ID_IQ_PI_0_iq_pi_output_o_7(
        SPEED_ID_IQ_PI_0_iq_pi_output_o[7]), 
        .SPEED_ID_IQ_PI_0_iq_pi_output_o_12(
        SPEED_ID_IQ_PI_0_iq_pi_output_o[12]), 
        .SPEED_ID_IQ_PI_0_iq_pi_output_o_13(
        SPEED_ID_IQ_PI_0_iq_pi_output_o[13]), 
        .HALL_INTERFACE_1_omega_out_o({
        HALL_INTERFACE_1_omega_out_o[17], 
        HALL_INTERFACE_1_omega_out_o[16], 
        HALL_INTERFACE_1_omega_out_o[15], 
        HALL_INTERFACE_1_omega_out_o[14], 
        HALL_INTERFACE_1_omega_out_o[13], 
        HALL_INTERFACE_1_omega_out_o[12], 
        HALL_INTERFACE_1_omega_out_o[11], 
        HALL_INTERFACE_1_omega_out_o[10], 
        HALL_INTERFACE_1_omega_out_o[9], 
        HALL_INTERFACE_1_omega_out_o[8], 
        HALL_INTERFACE_1_omega_out_o[7], 
        HALL_INTERFACE_1_omega_out_o[6], 
        HALL_INTERFACE_1_omega_out_o[5], 
        HALL_INTERFACE_1_omega_out_o[4], 
        HALL_INTERFACE_1_omega_out_o[3], 
        HALL_INTERFACE_1_omega_out_o[2], 
        HALL_INTERFACE_1_omega_out_o[1]}), .RATE_LIMITER_0_rl_out_o({
        RATE_LIMITER_0_rl_out_o[17], RATE_LIMITER_0_rl_out_o[16], 
        RATE_LIMITER_0_rl_out_o[15], RATE_LIMITER_0_rl_out_o[14], 
        RATE_LIMITER_0_rl_out_o[13], RATE_LIMITER_0_rl_out_o[12], 
        RATE_LIMITER_0_rl_out_o[11], RATE_LIMITER_0_rl_out_o[10], 
        RATE_LIMITER_0_rl_out_o[9], RATE_LIMITER_0_rl_out_o[8], 
        RATE_LIMITER_0_rl_out_o[7], RATE_LIMITER_0_rl_out_o[6], 
        RATE_LIMITER_0_rl_out_o[5], RATE_LIMITER_0_rl_out_o[4], 
        RATE_LIMITER_0_rl_out_o[3], RATE_LIMITER_0_rl_out_o[2], 
        RATE_LIMITER_0_rl_out_o[1], RATE_LIMITER_0_rl_out_o[0]}), 
        .prdata_o_1_iv_13({prdata_o_1_iv_13[7]}), .prdata_o_1_iv_12({
        prdata_o_1_iv_12[7]}), .prdata_o_1_iv_10_0_0(
        prdata_o_1_iv_10_0[5]), .OLMNG_0_theta_o({OLMNG_0_theta_o[17], 
        OLMNG_0_theta_o[16], OLMNG_0_theta_o[15], OLMNG_0_theta_o[14], 
        OLMNG_0_theta_o[13], OLMNG_0_theta_o[12], OLMNG_0_theta_o[11], 
        OLMNG_0_theta_o[10], OLMNG_0_theta_o[9], OLMNG_0_theta_o[8], 
        OLMNG_0_theta_o[7], OLMNG_0_theta_o[6], OLMNG_0_theta_o[5], 
        OLMNG_0_theta_o[4], OLMNG_0_theta_o[3], OLMNG_0_theta_o[2], 
        OLMNG_0_theta_o[1], OLMNG_0_theta_o[0]}), .prdata_o_1_iv_0_9({
        prdata_o_1_iv_0_9[14]}), .prdata_o_1_iv_0_7({
        prdata_o_1_iv_0_7[12]}), .adc_interface_0_result_ch2_o({
        adc_interface_0_result_ch2_o[11], 
        adc_interface_0_result_ch2_o[10], 
        adc_interface_0_result_ch2_o[9], 
        adc_interface_0_result_ch2_o[8], 
        adc_interface_0_result_ch2_o[7], 
        adc_interface_0_result_ch2_o[6], 
        adc_interface_0_result_ch2_o[5], 
        adc_interface_0_result_ch2_o[4], 
        adc_interface_0_result_ch2_o[3], 
        adc_interface_0_result_ch2_o[2], 
        adc_interface_0_result_ch2_o[1], 
        adc_interface_0_result_ch2_o[0]}), .prdata_o_1_iv_10_12({
        prdata_o_1_iv_10_12[10]}), .ADC_SCALING_0_ia_adc_o({
        ADC_SCALING_0_ia_adc_o[17], ADC_SCALING_0_ia_adc_o[16], 
        ADC_SCALING_0_ia_adc_o[15], ADC_SCALING_0_ia_adc_o[14], 
        ADC_SCALING_0_ia_adc_o[13], ADC_SCALING_0_ia_adc_o[12], 
        ADC_SCALING_0_ia_adc_o[11], ADC_SCALING_0_ia_adc_o[10], 
        ADC_SCALING_0_ia_adc_o[9], ADC_SCALING_0_ia_adc_o[8], 
        ADC_SCALING_0_ia_adc_o[7], ADC_SCALING_0_ia_adc_o[6], 
        ADC_SCALING_0_ia_adc_o[5], ADC_SCALING_0_ia_adc_o[4], 
        ADC_SCALING_0_ia_adc_o[3], ADC_SCALING_0_ia_adc_o[2], 
        ADC_SCALING_0_ia_adc_o[1], ADC_SCALING_0_ia_adc_o[0]}), 
        .prdata_o_1_0_iv_0_15({prdata_o_1_0_iv_0_15[1], 
        prdata_o_1_0_iv_0_15[0]}), .prdata_o_1_iv_0_12_2(
        prdata_o_1_iv_0_12_2), .prdata_o_1_iv_0_12_0(
        prdata_o_1_iv_0_12_0), .prdata_o_1_iv_0_8({
        prdata_o_1_iv_0_8[13]}), .adc_interface_0_result_ch3_o({
        adc_interface_0_result_ch3_o[11], 
        adc_interface_0_result_ch3_o[10], 
        adc_interface_0_result_ch3_o[9], 
        adc_interface_0_result_ch3_o[8], 
        adc_interface_0_result_ch3_o[7], 
        adc_interface_0_result_ch3_o[6], 
        adc_interface_0_result_ch3_o[5], 
        adc_interface_0_result_ch3_o[4], 
        adc_interface_0_result_ch3_o[3], 
        adc_interface_0_result_ch3_o[2], 
        adc_interface_0_result_ch3_o[1], 
        adc_interface_0_result_ch3_o[0]}), .prdata_o_1_iv_14_2(
        prdata_o_1_iv_14_2), .prdata_o_1_iv_14_0(prdata_o_1_iv_14_0), 
        .FOC_TRANSFORMS_0_id_o({FOC_TRANSFORMS_0_id_o[17], 
        FOC_TRANSFORMS_0_id_o[16], FOC_TRANSFORMS_0_id_o[15], 
        FOC_TRANSFORMS_0_id_o[14], FOC_TRANSFORMS_0_id_o[13], 
        FOC_TRANSFORMS_0_id_o[12], FOC_TRANSFORMS_0_id_o[11], 
        FOC_TRANSFORMS_0_id_o[10], FOC_TRANSFORMS_0_id_o[9], 
        FOC_TRANSFORMS_0_id_o[8], FOC_TRANSFORMS_0_id_o[7], 
        FOC_TRANSFORMS_0_id_o[6], FOC_TRANSFORMS_0_id_o[5], 
        FOC_TRANSFORMS_0_id_o[4], FOC_TRANSFORMS_0_id_o[3], 
        FOC_TRANSFORMS_0_id_o[2], FOC_TRANSFORMS_0_id_o[1], 
        FOC_TRANSFORMS_0_id_o[0]}), .prdata_o_1_iv_0_11_0(
        prdata_o_1_iv_0_11_0), .prdata_o_1_iv_0_11_2(
        prdata_o_1_iv_0_11_2), .prdata_o_1_iv_0_11_3(
        prdata_o_1_iv_0_11_3), .FOC_TRANSFORMS_0_ibeta_o({
        FOC_TRANSFORMS_0_ibeta_o[17], FOC_TRANSFORMS_0_ibeta_o[16], 
        FOC_TRANSFORMS_0_ibeta_o[15], FOC_TRANSFORMS_0_ibeta_o[14], 
        FOC_TRANSFORMS_0_ibeta_o[13], FOC_TRANSFORMS_0_ibeta_o[12], 
        FOC_TRANSFORMS_0_ibeta_o[11], FOC_TRANSFORMS_0_ibeta_o[10], 
        FOC_TRANSFORMS_0_ibeta_o[9], FOC_TRANSFORMS_0_ibeta_o[8], 
        FOC_TRANSFORMS_0_ibeta_o[7], FOC_TRANSFORMS_0_ibeta_o[6], 
        FOC_TRANSFORMS_0_ibeta_o[5], FOC_TRANSFORMS_0_ibeta_o[4], 
        FOC_TRANSFORMS_0_ibeta_o[3], FOC_TRANSFORMS_0_ibeta_o[2], 
        FOC_TRANSFORMS_0_ibeta_o[1]}), .prdata_o_1_iv_11({
        prdata_o_1_iv_11[16]}), .MC_System_0_FIC_0_LOCK(
        MC_System_0_FIC_0_LOCK), .MC_System_0_FIC_0_CLK(
        MC_System_0_FIC_0_CLK), .apb3_en_if_1_stop_motor_o(
        apb3_en_if_1_stop_motor_o), .apb3_en_if_1_start_motor_o(
        apb3_en_if_1_start_motor_o), 
        .apb3_hall_if_0_hall_sensor_polarity_o(
        apb3_hall_if_0_hall_sensor_polarity_o), 
        .apb3_en_if_1_fault_clr_o(apb3_en_if_1_fault_clr_o), 
        .apb3_en_if_0_direction_config_o(
        apb3_en_if_0_direction_config_o), .N_358(N_358), .prdata_o277(
        prdata_o277), .prdata_o267(prdata_o267), 
        .prdata_N_5_mux_i_3_a0_7_1(prdata_N_5_mux_i_3_a0_7_1), 
        .prdata_N_5_mux_i_3_a0_10(prdata_N_5_mux_i_3_a0_10), 
        .prdata_o263(prdata_o263), .prdata_N_5_mux_i_1_a0_13(
        prdata_N_5_mux_i_1_a0_13), .N_435_4(N_435_4), 
        .prdata_N_5_mux_i_2_a0_11(prdata_N_5_mux_i_2_a0_11), 
        .prdata_o259(prdata_o259), .prdata_m2_e_5_6_1(
        prdata_m2_e_5_6_1), .prdata_N_5_mux_i_4_a0_11(
        prdata_N_5_mux_i_4_a0_11), .prdata_o274(prdata_o274), 
        .prdata_m2_e_27_10(prdata_m2_e_27_10), .prdata_m2_0_a2_1_0(
        prdata_m2_0_a2_1_0), .prdata_m2_0_a2_17_0(prdata_m2_0_a2_17_0), 
        .prdata_o270(prdata_o270), .MC_System_0_AMBA_SLAVE_0_PSELx(
        MC_System_0_AMBA_SLAVE_0_PSELx), 
        .MC_System_0_AMBA_SLAVE_0_PWRITE(
        MC_System_0_AMBA_SLAVE_0_PWRITE), 
        .MC_System_0_AMBA_SLAVE_0_PENABLE(
        MC_System_0_AMBA_SLAVE_0_PENABLE), .N_296(N_296), .prdata_o260(
        prdata_o260), .N_225(N_225), .prdata_m2_e_5_1(prdata_m2_e_5_1), 
        .prdata_N_5_mux_i_3_a0_4(prdata_N_5_mux_i_3_a0_4), 
        .prdata_N_5_mux_i_3_a0_0(prdata_N_5_mux_i_3_a0_0), 
        .prdata_N_5_mux_i_2_a0_4(prdata_N_5_mux_i_2_a0_4), 
        .prdata_N_5_mux_i_2_a0_0(prdata_N_5_mux_i_2_a0_0), .N_286(
        N_286), .N_283(N_283), .prdata_m2_e_5_11(prdata_m2_e_5_11), 
        .prdata_m2_e_5_6(prdata_m2_e_5_6), .prdata_m2_e_5_4(
        prdata_m2_e_5_4), .prdata_m2_e_27_11(prdata_m2_e_27_11), 
        .prdata_m2_e_0_9(prdata_m2_e_0_9), .prdata_N_5_mux_i_4_a0_12(
        prdata_N_5_mux_i_4_a0_12), .prdata_N_5_mux_i_3_a0_12(
        prdata_N_5_mux_i_3_a0_12), .prdata_N_5_mux_i_1_a0_12(
        prdata_N_5_mux_i_1_a0_12), .prdata_N_5_mux_i_2_a0_12(
        prdata_N_5_mux_i_2_a0_12), .m7_i_2(m7_i_2), .prdata_m2_e_0_8(
        prdata_m2_e_0_8), .prdata_N_5_mux_i_2_a0_10(
        prdata_N_5_mux_i_2_a0_10), .N_157(N_157), .prdata_m2_e_5_10(
        prdata_m2_e_5_10), .prdata_m2_e_27_12(prdata_m2_e_27_12), 
        .prdata_m2_e_0_10(prdata_m2_e_0_10), .prdata_N_5_mux_i_4_a0_13(
        prdata_N_5_mux_i_4_a0_13), .prdata_N_5_mux_i_3_a0_11(
        prdata_N_5_mux_i_3_a0_11));
    
endmodule


module MC_System_top(
       A0_ADC_SDI_I,
       DEVRST_N,
       HA_i,
       HB_i,
       HC_i,
       USB_ULPI_DIR,
       USB_ULPI_NXT,
       USB_ULPI_XCLK,
       A0_ADC_CS_O,
       A0_ADC_SCK_O,
       A0_ADC_SDO_O,
       A0_PWM_UH_O,
       A0_PWM_UL_O,
       A0_PWM_VH_O,
       A0_PWM_VL_O,
       A0_PWM_WH_O,
       A0_PWM_WL_O,
       A0_RUNNING_LED,
       GPIO_0_M2F,
       USB_ULPI_STP,
       USB_ULPI_DATA
    );
input  A0_ADC_SDI_I;
input  DEVRST_N;
input  HA_i;
input  HB_i;
input  HC_i;
input  USB_ULPI_DIR;
input  USB_ULPI_NXT;
input  USB_ULPI_XCLK;
output A0_ADC_CS_O;
output A0_ADC_SCK_O;
output A0_ADC_SDO_O;
output A0_PWM_UH_O;
output A0_PWM_UL_O;
output A0_PWM_VH_O;
output A0_PWM_VL_O;
output A0_PWM_WH_O;
output A0_PWM_WL_O;
output A0_RUNNING_LED;
output GPIO_0_M2F;
output USB_ULPI_STP;
inout  [7:0] USB_ULPI_DATA;

    wire [19:19] MC_System_0_AMBA_SLAVE_0_PRDATA;
    wire [11:0] MC_System_0_AMBA_SLAVE_0_PADDR;
    wire [17:0] MC_System_0_AMBA_SLAVE_0_PWDATA;
    wire [0:0] \BLDC_HALL_Axis_0.adc_interface_0_result_ch0_o ;
    wire [2:0] \BLDC_HALL_Axis_0.adc_interface_0_result_ch1_o ;
    wire [0:0] \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_ialpha_o ;
    wire [0:0] \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_ibeta_o ;
    wire [0:0] \BLDC_HALL_Axis_0.SPEED_ID_IQ_PI_0_id_pi_output_o ;
    wire [9:9] \BLDC_HALL_Axis_0.SPEED_ID_IQ_PI_0_iq_pi_output_o ;
    wire [2:2] \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_valpha_o ;
    wire [0:0] \BLDC_HALL_Axis_0.HALL_INTERFACE_1_omega_out_o ;
    wire [2:0] \BLDC_HALL_Axis_0.SEQ_CONTROLLER_0_state_o ;
    wire [11:6] \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_valpha_o_m ;
    wire [5:5] \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_id_o_m ;
    wire [9:9] \BLDC_HALL_Axis_0.adc_interface_0_result_ch3_o_m ;
    wire [9:9] \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_ialpha_o_m ;
    wire [1:0] \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_15 ;
    wire [13:13] \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_7_0 ;
    wire [13:13] \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_8 ;
    wire [15:13] \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_12 ;
    wire [16:16] \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_9 ;
    wire [16:16] \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_10 ;
    wire [16:16] \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_11 ;
    wire [1:1] \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_13 ;
    wire [1:1] \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_14 ;
    wire [15:14] \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_10 ;
    wire [15:12] \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_11 ;
    wire [10:10] \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_10_11 ;
    wire [10:10] \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_10_12 ;
    wire [10:10] \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_10_13 ;
    wire [12:12] \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_6 ;
    wire [12:12] \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_7 ;
    wire [14:14] \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_9 ;
    wire [5:5] \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_10_0 ;
    wire [7:5] \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_14 ;
    wire [7:7] \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_12 ;
    wire [7:7] \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_13 ;
    wire GND, MC_System_0_AMBA_SLAVE_0_PENABLE, 
        MC_System_0_AMBA_SLAVE_0_PWRITE, MC_System_0_FIC_0_CLK, VCC, 
        MC_System_0_FIC_0_LOCK, MC_System_0_AMBA_SLAVE_0_PSELx, 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o259 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o260 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o263 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o267 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_5_6_1 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o270 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_3_a0_7_1 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o274 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o277 , 
        \BLDC_HALL_Axis_0.N_157 , \BLDC_HALL_Axis_0.N_225 , 
        \BLDC_HALL_Axis_0.N_283 , \BLDC_HALL_Axis_0.N_286 , 
        \BLDC_HALL_Axis_0.N_296 , \BLDC_HALL_Axis_0.N_358 , 
        \BLDC_HALL_Axis_0.N_435_4 , A0_ADC_SDI_I_c, HA_i_c, HB_i_c, 
        HC_i_c, A0_ADC_CS_O_c, A0_ADC_SCK_O_c, A0_ADC_SDO_O_c, 
        A0_PWM_UH_O_c, A0_PWM_VH_O_c, A0_PWM_VL_O_c, A0_PWM_WH_O_c, 
        GPIO_0_M2F_c, 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_0_a2_17_0 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_0_a2_1_0 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_2_a0_0 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_2_a0_4 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_2_a0_10 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_2_a0_11 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_2_a0_12 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_1_a0_12 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_1_a0_13 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_3_a0_0 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_3_a0_4 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_3_a0_10 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_3_a0_11 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_3_a0_12 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_4_a0_11 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_4_a0_12 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_4_a0_13 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_0_8 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_0_9 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_0_10 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.m7_i_2 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_27_10 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_27_11 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_27_12 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_5_1 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_5_4 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_5_6 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_5_10 , 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_5_11 ;
    
    GND GND_Z (.Y(GND));
    OUTBUF #( .IOSTD("") )  A0_PWM_VH_O_obuf (.D(A0_PWM_VH_O_c), .PAD(
        A0_PWM_VH_O));
    OUTBUF #( .IOSTD("") )  A0_PWM_UH_O_obuf (.D(A0_PWM_UH_O_c), .PAD(
        A0_PWM_UH_O));
    INBUF #( .IOSTD("") )  HB_i_ibuf (.PAD(HB_i), .Y(HB_i_c));
    OUTBUF #( .IOSTD("") )  A0_PWM_WL_O_obuf (.D(A0_PWM_VL_O_c), .PAD(
        A0_PWM_WL_O));
    VCC VCC_Z (.Y(VCC));
    MC_System MC_System_0 (.FOC_TRANSFORMS_0_valpha_o({
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_valpha_o [2]}), 
        .FOC_TRANSFORMS_0_valpha_o_m_0(
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_valpha_o_m [6]), 
        .FOC_TRANSFORMS_0_valpha_o_m_5(
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_valpha_o_m [11]), 
        .FOC_TRANSFORMS_0_ialpha_o_m({
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_ialpha_o_m [9]}), 
        .SPEED_ID_IQ_PI_0_iq_pi_output_o({
        \BLDC_HALL_Axis_0.SPEED_ID_IQ_PI_0_iq_pi_output_o [9]}), 
        .adc_interface_0_result_ch3_o_m({
        \BLDC_HALL_Axis_0.adc_interface_0_result_ch3_o_m [9]}), 
        .MC_System_0_AMBA_SLAVE_0_PRDATA({
        MC_System_0_AMBA_SLAVE_0_PRDATA[19]}), 
        .SPEED_ID_IQ_PI_0_id_pi_output_o({
        \BLDC_HALL_Axis_0.SPEED_ID_IQ_PI_0_id_pi_output_o [0]}), 
        .HALL_INTERFACE_1_omega_out_o({
        \BLDC_HALL_Axis_0.HALL_INTERFACE_1_omega_out_o [0]}), 
        .FOC_TRANSFORMS_0_ialpha_o({
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_ialpha_o [0]}), 
        .adc_interface_0_result_ch1_o_2(
        \BLDC_HALL_Axis_0.adc_interface_0_result_ch1_o [2]), 
        .adc_interface_0_result_ch1_o_0(
        \BLDC_HALL_Axis_0.adc_interface_0_result_ch1_o [0]), 
        .SEQ_CONTROLLER_0_state_o_2(
        \BLDC_HALL_Axis_0.SEQ_CONTROLLER_0_state_o [2]), 
        .SEQ_CONTROLLER_0_state_o_0(
        \BLDC_HALL_Axis_0.SEQ_CONTROLLER_0_state_o [0]), 
        .adc_interface_0_result_ch0_o({
        \BLDC_HALL_Axis_0.adc_interface_0_result_ch0_o [0]}), 
        .FOC_TRANSFORMS_0_ibeta_o({
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_ibeta_o [0]}), 
        .prdata_o_1_0_iv_0_14({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_14 [1]}), 
        .prdata_o_1_0_iv_0_15({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_15 [1], 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_15 [0]}), 
        .prdata_o_1_0_iv_0_13({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_13 [1]}), 
        .prdata_o_1_iv_10_0({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_10_0 [5]}), 
        .FOC_TRANSFORMS_0_id_o_m({
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_id_o_m [5]}), 
        .prdata_o_1_iv_13({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_13 [7]}), 
        .prdata_o_1_iv_14_0(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_14 [5]), 
        .prdata_o_1_iv_14_2(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_14 [7]), 
        .prdata_o_1_iv_12({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_12 [7]}), 
        .prdata_o_1_iv_10_12({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_10_12 [10]}), 
        .prdata_o_1_iv_10_13({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_10_13 [10]}), 
        .prdata_o_1_iv_10_11({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_10_11 [10]}), 
        .prdata_o_1_iv_0_7({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_7 [12]}), 
        .prdata_o_1_iv_0_6({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_6 [12]}), 
        .prdata_o_1_iv_0_8({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_8 [13]}), 
        .prdata_o_1_iv_0_7_0({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_7_0 [13]}), 
        .prdata_o_1_iv_0_9({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_9 [14]}), 
        .prdata_o_1_iv_10({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_10 [16]}), 
        .prdata_o_1_iv_11({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_11 [16]}), 
        .prdata_o_1_iv_9({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_9 [16]}), 
        .prdata_o_1_iv_0_11_0(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_11 [12]), 
        .prdata_o_1_iv_0_11_2(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_11 [14]), 
        .prdata_o_1_iv_0_11_3(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_11 [15]), 
        .prdata_o_1_iv_0_12_0(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_12 [13]), 
        .prdata_o_1_iv_0_12_2(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_12 [15]), 
        .prdata_o_1_iv_0_10({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_10 [15], 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_10 [14]}), 
        .USB_ULPI_DATA({USB_ULPI_DATA[7], USB_ULPI_DATA[6], 
        USB_ULPI_DATA[5], USB_ULPI_DATA[4], USB_ULPI_DATA[3], 
        USB_ULPI_DATA[2], USB_ULPI_DATA[1], USB_ULPI_DATA[0]}), 
        .MC_System_0_AMBA_SLAVE_0_PADDR({
        MC_System_0_AMBA_SLAVE_0_PADDR[11], 
        MC_System_0_AMBA_SLAVE_0_PADDR[10], 
        MC_System_0_AMBA_SLAVE_0_PADDR[9], 
        MC_System_0_AMBA_SLAVE_0_PADDR[8], 
        MC_System_0_AMBA_SLAVE_0_PADDR[7], 
        MC_System_0_AMBA_SLAVE_0_PADDR[6], 
        MC_System_0_AMBA_SLAVE_0_PADDR[5], 
        MC_System_0_AMBA_SLAVE_0_PADDR[4], 
        MC_System_0_AMBA_SLAVE_0_PADDR[3], 
        MC_System_0_AMBA_SLAVE_0_PADDR[2], 
        MC_System_0_AMBA_SLAVE_0_PADDR[1], 
        MC_System_0_AMBA_SLAVE_0_PADDR[0]}), 
        .MC_System_0_AMBA_SLAVE_0_PWDATA({
        MC_System_0_AMBA_SLAVE_0_PWDATA[17], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[16], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[15], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[14], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[13], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[12], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[11], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[10], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[9], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[8], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[7], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[6], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[5], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[4], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[3], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[2], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[1], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[0]}), .MC_System_0_FIC_0_LOCK(
        MC_System_0_FIC_0_LOCK), .MC_System_0_FIC_0_CLK(
        MC_System_0_FIC_0_CLK), .MC_System_0_AMBA_SLAVE_0_PSELx(
        MC_System_0_AMBA_SLAVE_0_PSELx), .prdata_m2_e_5_6(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_5_6 ), 
        .prdata_m2_e_5_11(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_5_11 ), 
        .prdata_m2_e_5_1(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_5_1 ), 
        .prdata_N_5_mux_i_3_a0_7_1(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_3_a0_7_1 ), 
        .prdata_o263(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o263 )
        , .prdata_o274(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o274 )
        , .prdata_m2_e_5_4(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_5_4 ), 
        .prdata_m2_e_5_10(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_5_10 ), 
        .prdata_N_5_mux_i_3_a0_11(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_3_a0_11 ), 
        .prdata_N_5_mux_i_3_a0_10(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_3_a0_10 ), 
        .prdata_N_5_mux_i_3_a0_4(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_3_a0_4 ), 
        .prdata_N_5_mux_i_3_a0_0(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_3_a0_0 ), 
        .prdata_N_5_mux_i_3_a0_12(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_3_a0_12 ), 
        .prdata_N_5_mux_i_2_a0_11(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_2_a0_11 ), 
        .prdata_N_5_mux_i_2_a0_10(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_2_a0_10 ), 
        .prdata_N_5_mux_i_2_a0_4(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_2_a0_4 ), 
        .prdata_N_5_mux_i_2_a0_0(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_2_a0_0 ), 
        .prdata_N_5_mux_i_2_a0_12(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_2_a0_12 ), 
        .prdata_m2_0_a2_1_0(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_0_a2_1_0 ), 
        .prdata_m2_0_a2_17_0(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_0_a2_17_0 ), .N_358(
        \BLDC_HALL_Axis_0.N_358 ), .prdata_m2_e_5_6_1(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_5_6_1 ), 
        .prdata_N_5_mux_i_1_a0_13(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_1_a0_13 ), 
        .prdata_N_5_mux_i_1_a0_12(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_1_a0_12 ), 
        .prdata_o277(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o277 )
        , .prdata_o267(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o267 )
        , .N_296(\BLDC_HALL_Axis_0.N_296 ), .prdata_o259(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o259 )
        , .N_225(\BLDC_HALL_Axis_0.N_225 ), .prdata_o270(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o270 )
        , .N_283(\BLDC_HALL_Axis_0.N_283 ), .N_286(
        \BLDC_HALL_Axis_0.N_286 ), .prdata_o260(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o260 )
        , .prdata_m2_e_0_9(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_0_9 ), 
        .prdata_m2_e_0_10(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_0_10 ), 
        .prdata_m2_e_0_8(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_0_8 ), 
        .prdata_m2_e_27_11(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_27_11 ), 
        .prdata_m2_e_27_12(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_27_12 ), 
        .prdata_m2_e_27_10(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_27_10 ), 
        .prdata_N_5_mux_i_4_a0_12(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_4_a0_12 ), 
        .prdata_N_5_mux_i_4_a0_13(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_4_a0_13 ), 
        .prdata_N_5_mux_i_4_a0_11(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_4_a0_11 ), 
        .m7_i_2(\BLDC_HALL_Axis_0.apb3_hall_if_0.m7_i_2 ), .N_435_4(
        \BLDC_HALL_Axis_0.N_435_4 ), .N_157(\BLDC_HALL_Axis_0.N_157 ), 
        .USB_ULPI_XCLK(USB_ULPI_XCLK), .USB_ULPI_STP(USB_ULPI_STP), 
        .USB_ULPI_NXT(USB_ULPI_NXT), .USB_ULPI_DIR(USB_ULPI_DIR), 
        .MC_System_0_AMBA_SLAVE_0_PENABLE(
        MC_System_0_AMBA_SLAVE_0_PENABLE), 
        .MC_System_0_AMBA_SLAVE_0_PWRITE(
        MC_System_0_AMBA_SLAVE_0_PWRITE), .GPIO_0_M2F_c(GPIO_0_M2F_c));
    BLDC_HALL_Axis BLDC_HALL_Axis_0 (.HALL_INTERFACE_1_omega_out_o_0(
        \BLDC_HALL_Axis_0.HALL_INTERFACE_1_omega_out_o [0]), 
        .SPEED_ID_IQ_PI_0_id_pi_output_o_0(
        \BLDC_HALL_Axis_0.SPEED_ID_IQ_PI_0_id_pi_output_o [0]), 
        .SPEED_ID_IQ_PI_0_iq_pi_output_o_9(
        \BLDC_HALL_Axis_0.SPEED_ID_IQ_PI_0_iq_pi_output_o [9]), 
        .SEQ_CONTROLLER_0_state_o_0(
        \BLDC_HALL_Axis_0.SEQ_CONTROLLER_0_state_o [0]), 
        .SEQ_CONTROLLER_0_state_o_2(
        \BLDC_HALL_Axis_0.SEQ_CONTROLLER_0_state_o [2]), 
        .FOC_TRANSFORMS_0_valpha_o_2(
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_valpha_o [2]), 
        .FOC_TRANSFORMS_0_ialpha_o_0(
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_ialpha_o [0]), 
        .FOC_TRANSFORMS_0_ibeta_o_0(
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_ibeta_o [0]), 
        .adc_interface_0_result_ch0_o_0(
        \BLDC_HALL_Axis_0.adc_interface_0_result_ch0_o [0]), 
        .adc_interface_0_result_ch1_o_0(
        \BLDC_HALL_Axis_0.adc_interface_0_result_ch1_o [0]), 
        .adc_interface_0_result_ch1_o_2(
        \BLDC_HALL_Axis_0.adc_interface_0_result_ch1_o [2]), 
        .MC_System_0_AMBA_SLAVE_0_PWDATA({
        MC_System_0_AMBA_SLAVE_0_PWDATA[17], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[16], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[15], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[14], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[13], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[12], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[11], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[10], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[9], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[8], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[7], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[6], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[5], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[4], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[3], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[2], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[1], 
        MC_System_0_AMBA_SLAVE_0_PWDATA[0]}), 
        .MC_System_0_AMBA_SLAVE_0_PRDATA({
        MC_System_0_AMBA_SLAVE_0_PRDATA[19]}), .prdata_o_1_iv_10_13({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_10_13 [10]}), 
        .prdata_o_1_iv_9({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_9 [16]}), 
        .prdata_o_1_0_iv_0_13({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_13 [1]}), 
        .prdata_o_1_iv_10_11({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_10_11 [10]}), 
        .MC_System_0_AMBA_SLAVE_0_PADDR({
        MC_System_0_AMBA_SLAVE_0_PADDR[11], 
        MC_System_0_AMBA_SLAVE_0_PADDR[10], 
        MC_System_0_AMBA_SLAVE_0_PADDR[9], 
        MC_System_0_AMBA_SLAVE_0_PADDR[8], 
        MC_System_0_AMBA_SLAVE_0_PADDR[7], 
        MC_System_0_AMBA_SLAVE_0_PADDR[6], 
        MC_System_0_AMBA_SLAVE_0_PADDR[5], 
        MC_System_0_AMBA_SLAVE_0_PADDR[4], 
        MC_System_0_AMBA_SLAVE_0_PADDR[3], 
        MC_System_0_AMBA_SLAVE_0_PADDR[2], 
        MC_System_0_AMBA_SLAVE_0_PADDR[1], 
        MC_System_0_AMBA_SLAVE_0_PADDR[0]}), 
        .FOC_TRANSFORMS_0_ialpha_o_m({
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_ialpha_o_m [9]}), 
        .FOC_TRANSFORMS_0_valpha_o_m_0(
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_valpha_o_m [6]), 
        .FOC_TRANSFORMS_0_valpha_o_m_5(
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_valpha_o_m [11]), 
        .adc_interface_0_result_ch3_o_m({
        \BLDC_HALL_Axis_0.adc_interface_0_result_ch3_o_m [9]}), 
        .FOC_TRANSFORMS_0_id_o_m({
        \BLDC_HALL_Axis_0.FOC_TRANSFORMS_0_id_o_m [5]}), 
        .prdata_o_1_iv_0_6({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_6 [12]}), 
        .prdata_o_1_iv_0_10({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_10 [15], 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_10 [14]}), 
        .prdata_o_1_0_iv_0_14({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_14 [1]}), 
        .prdata_o_1_iv_10({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_10 [16]}), 
        .prdata_o_1_iv_0_7_0({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_7_0 [13]}), 
        .prdata_o_1_iv_13({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_13 [7]}), 
        .prdata_o_1_iv_12({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_12 [7]}), 
        .prdata_o_1_iv_10_0({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_10_0 [5]}), 
        .prdata_o_1_iv_0_9({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_9 [14]}), 
        .prdata_o_1_iv_0_7({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_7 [12]}), 
        .prdata_o_1_iv_10_12({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_10_12 [10]}), 
        .prdata_o_1_0_iv_0_15({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_15 [1], 
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_0_iv_0_15 [0]}), 
        .prdata_o_1_iv_0_12_2(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_12 [15]), 
        .prdata_o_1_iv_0_12_0(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_12 [13]), 
        .prdata_o_1_iv_0_8({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_8 [13]}), 
        .prdata_o_1_iv_14_2(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_14 [7]), 
        .prdata_o_1_iv_14_0(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_14 [5]), 
        .prdata_o_1_iv_0_11_0(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_11 [12]), 
        .prdata_o_1_iv_0_11_2(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_11 [14]), 
        .prdata_o_1_iv_0_11_3(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_0_11 [15]), 
        .prdata_o_1_iv_11({
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_iv_11 [16]}), 
        .MC_System_0_FIC_0_LOCK(MC_System_0_FIC_0_LOCK), 
        .MC_System_0_FIC_0_CLK(MC_System_0_FIC_0_CLK), .A0_PWM_VL_O_c(
        A0_PWM_VL_O_c), .A0_PWM_UH_O_c(A0_PWM_UH_O_c), .A0_PWM_VH_O_c(
        A0_PWM_VH_O_c), .A0_PWM_WH_O_c(A0_PWM_WH_O_c), .HA_i_c(HA_i_c), 
        .HB_i_c(HB_i_c), .HC_i_c(HC_i_c), .N_358(
        \BLDC_HALL_Axis_0.N_358 ), .prdata_o277(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o277 )
        , .prdata_o267(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o267 )
        , .prdata_N_5_mux_i_3_a0_7_1(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_3_a0_7_1 ), 
        .prdata_N_5_mux_i_3_a0_10(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_3_a0_10 ), 
        .prdata_o263(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o263 )
        , .prdata_N_5_mux_i_1_a0_13(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_1_a0_13 ), 
        .N_435_4(\BLDC_HALL_Axis_0.N_435_4 ), 
        .prdata_N_5_mux_i_2_a0_11(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_2_a0_11 ), 
        .prdata_o259(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o259 )
        , .prdata_m2_e_5_6_1(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_5_6_1 ), 
        .prdata_N_5_mux_i_4_a0_11(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_4_a0_11 ), 
        .prdata_o274(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o274 )
        , .prdata_m2_e_27_10(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_27_10 ), 
        .prdata_m2_0_a2_1_0(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_0_a2_1_0 ), 
        .prdata_m2_0_a2_17_0(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_0_a2_17_0 ), 
        .prdata_o270(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o270 )
        , .MC_System_0_AMBA_SLAVE_0_PSELx(
        MC_System_0_AMBA_SLAVE_0_PSELx), 
        .MC_System_0_AMBA_SLAVE_0_PWRITE(
        MC_System_0_AMBA_SLAVE_0_PWRITE), 
        .MC_System_0_AMBA_SLAVE_0_PENABLE(
        MC_System_0_AMBA_SLAVE_0_PENABLE), .N_296(
        \BLDC_HALL_Axis_0.N_296 ), .prdata_o260(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.READ_DECODE_PROC.prdata_o260 )
        , .N_225(\BLDC_HALL_Axis_0.N_225 ), .prdata_m2_e_5_1(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_5_1 ), 
        .prdata_N_5_mux_i_3_a0_4(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_3_a0_4 ), 
        .prdata_N_5_mux_i_3_a0_0(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_3_a0_0 ), 
        .prdata_N_5_mux_i_2_a0_4(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_2_a0_4 ), 
        .prdata_N_5_mux_i_2_a0_0(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_2_a0_0 ), 
        .N_286(\BLDC_HALL_Axis_0.N_286 ), .N_283(
        \BLDC_HALL_Axis_0.N_283 ), .prdata_m2_e_5_11(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_5_11 ), 
        .prdata_m2_e_5_6(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_5_6 ), 
        .prdata_m2_e_5_4(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_5_4 ), 
        .prdata_m2_e_27_11(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_27_11 ), 
        .prdata_m2_e_0_9(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_0_9 ), 
        .prdata_N_5_mux_i_4_a0_12(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_4_a0_12 ), 
        .prdata_N_5_mux_i_3_a0_12(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_3_a0_12 ), 
        .prdata_N_5_mux_i_1_a0_12(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_1_a0_12 ), 
        .prdata_N_5_mux_i_2_a0_12(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_2_a0_12 ), 
        .m7_i_2(\BLDC_HALL_Axis_0.apb3_hall_if_0.m7_i_2 ), 
        .prdata_m2_e_0_8(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_0_8 ), 
        .prdata_N_5_mux_i_2_a0_10(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_2_a0_10 ), 
        .N_157(\BLDC_HALL_Axis_0.N_157 ), .prdata_m2_e_5_10(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_5_10 ), 
        .prdata_m2_e_27_12(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_27_12 ), 
        .prdata_m2_e_0_10(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_m2_e_0_10 ), 
        .prdata_N_5_mux_i_4_a0_13(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_4_a0_13 ), 
        .prdata_N_5_mux_i_3_a0_11(
        \BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_N_5_mux_i_3_a0_11 ), 
        .A0_ADC_SDI_I_c(A0_ADC_SDI_I_c), .A0_ADC_SDO_O_c(
        A0_ADC_SDO_O_c), .A0_ADC_CS_O_c(A0_ADC_CS_O_c), 
        .A0_ADC_SCK_O_c(A0_ADC_SCK_O_c));
    INBUF #( .IOSTD("") )  HA_i_ibuf (.PAD(HA_i), .Y(HA_i_c));
    OUTBUF #( .IOSTD("") )  A0_ADC_SCK_O_obuf (.D(A0_ADC_SCK_O_c), 
        .PAD(A0_ADC_SCK_O));
    OUTBUF #( .IOSTD("") )  A0_PWM_WH_O_obuf (.D(A0_PWM_WH_O_c), .PAD(
        A0_PWM_WH_O));
    OUTBUF #( .IOSTD("") )  A0_PWM_VL_O_obuf (.D(A0_PWM_VL_O_c), .PAD(
        A0_PWM_VL_O));
    OUTBUF #( .IOSTD("") )  A0_PWM_UL_O_obuf (.D(A0_PWM_VL_O_c), .PAD(
        A0_PWM_UL_O));
    OUTBUF #( .IOSTD("") )  A0_ADC_SDO_O_obuf (.D(A0_ADC_SDO_O_c), 
        .PAD(A0_ADC_SDO_O));
    OUTBUF #( .IOSTD("") )  GPIO_0_M2F_obuf (.D(GPIO_0_M2F_c), .PAD(
        GPIO_0_M2F));
    OUTBUF #( .IOSTD("") )  A0_ADC_CS_O_obuf (.D(A0_ADC_CS_O_c), .PAD(
        A0_ADC_CS_O));
    INBUF #( .IOSTD("") )  HC_i_ibuf (.PAD(HC_i), .Y(HC_i_c));
    OUTBUF #( .IOSTD("") )  A0_RUNNING_LED_obuf (.D(A0_PWM_VL_O_c), 
        .PAD(A0_RUNNING_LED));
    INBUF #( .IOSTD("") )  A0_ADC_SDI_I_ibuf (.PAD(A0_ADC_SDI_I), .Y(
        A0_ADC_SDI_I_c));
    
endmodule
