#Build: Synplify Pro L-2016.09M-2, Build 065R, Nov 16 2016
#install: F:\Microsemi\Libero_SoC_v11.8\SynplifyPro
#OS: Windows 8 6.2
#Hostname: W1064L-ASHWINM

# Wed Nov 29 13:44:44 2017

#Implementation: synthesis

Synopsys HDL Compiler, version comp2016q3p1, Build 117R, built Nov 17 2016
@N|Running in 64-bit mode
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

Synopsys VHDL Compiler, version comp2016q3p1, Build 127R, built Nov 24 2016
@N|Running in 64-bit mode
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

@N: CD720 :"F:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vhd2008\std.vhd":146:18:146:21|Setting time resolution to ps
@N:"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\work\MC_System_top\MC_System_top.vhd":17:7:17:19|Top entity is set to MC_System_top.
VHDL syntax check successful!
@N: CD231 :"F:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vhd2008\std1164.vhd":890:16:890:17|Using onehot encoding for type mvl9plus. For example, enumeration 'U' is mapped to "1000000000".
@N: CD630 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\work\MC_System_top\MC_System_top.vhd":17:7:17:19|Synthesizing work.mc_system_top.rtl.
@N: CD630 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\work\MC_System\MC_System.vhd":17:7:17:15|Synthesizing work.mc_system.rtl.
@N: CD630 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\work\MC_System_sb\MC_System_sb.vhd":20:7:20:18|Synthesizing work.mc_system_sb.rtl.
@N: CD630 :"F:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.vhd":786:10:786:17|Synthesizing smartfusion2.sysreset.syn_black_box.
Post processing for smartfusion2.sysreset.syn_black_box
@N: CD630 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\work\MC_System_sb_MSS\MC_System_sb_MSS.vhd":17:7:17:22|Synthesizing work.mc_system_sb_mss.rtl.
@N: CD630 :"F:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.vhd":434:10:434:14|Synthesizing smartfusion2.bibuf.syn_black_box.
Post processing for smartfusion2.bibuf.syn_black_box
@N: CD630 :"F:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.vhd":403:10:403:14|Synthesizing smartfusion2.inbuf.syn_black_box.
Post processing for smartfusion2.inbuf.syn_black_box
@N: CD630 :"F:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.vhd":423:10:423:16|Synthesizing smartfusion2.tribuff.syn_black_box.
Post processing for smartfusion2.tribuff.syn_black_box
@N: CD630 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\work\MC_System_sb_MSS\MC_System_sb_MSS_syn.vhd":10:7:10:13|Synthesizing work.mss_010.def_arch.
Post processing for work.mss_010.def_arch
Post processing for work.mc_system_sb_mss.rtl
@N: CD630 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd":8:7:8:31|Synthesizing work.mc_system_sb_fabosc_0_osc.def_arch.
@N: CD630 :"F:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.vhd":562:10:562:15|Synthesizing smartfusion2.clkint.syn_black_box.
Post processing for smartfusion2.clkint.syn_black_box
@N: CD630 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\SgCore\OSC\1.0.103\osc_comps.vhd":19:7:19:20|Synthesizing work.rcosc_25_50mhz.def_arch.
Post processing for work.rcosc_25_50mhz.def_arch
@N: CD630 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\SgCore\OSC\1.0.103\osc_comps.vhd":79:7:79:24|Synthesizing work.rcosc_25_50mhz_fab.def_arch.
Post processing for work.rcosc_25_50mhz_fab.def_arch
Post processing for work.mc_system_sb_fabosc_0_osc.def_arch
@W: CL240 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd":16:10:16:19|Signal XTLOSC_O2F is floating; a simulation mismatch is possible.
@W: CL240 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd":15:10:15:19|Signal XTLOSC_CCC is floating; a simulation mismatch is possible.
@W: CL240 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd":14:10:14:23|Signal RCOSC_1MHZ_O2F is floating; a simulation mismatch is possible.
@W: CL240 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd":13:10:13:23|Signal RCOSC_1MHZ_CCC is floating; a simulation mismatch is possible.
@N: CD630 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":27:7:27:16|Synthesizing work.coreresetp.rtl.
@W: CD434 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":477:8:477:25|Signal soft_ext_reset_out in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":478:8:478:21|Signal soft_reset_f2m in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":479:8:479:20|Signal soft_m3_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":480:8:480:37|Signal soft_mddr_ddr_axi_s_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":481:8:481:27|Signal soft_fddr_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":482:8:482:27|Signal soft_sdif0_phy_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":483:8:483:28|Signal soft_sdif0_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":484:8:484:27|Signal soft_sdif1_phy_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":485:8:485:28|Signal soft_sdif1_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":486:8:486:27|Signal soft_sdif2_phy_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":487:8:487:28|Signal soft_sdif2_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":488:8:488:27|Signal soft_sdif3_phy_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":489:8:489:28|Signal soft_sdif3_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":490:8:490:30|Signal soft_sdif0_0_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":491:8:491:30|Signal soft_sdif0_1_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
Post processing for work.coreresetp.rtl
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1519:8:1519:9|Pruning unused register count_ddr_2(13 downto 0). Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1495:8:1495:9|Pruning unused register count_sdif3_1(12 downto 0). Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1471:8:1471:9|Pruning unused register count_sdif2_1(12 downto 0). Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1447:8:1447:9|Pruning unused register count_sdif1_1(12 downto 0). Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1423:8:1423:9|Pruning unused register count_sdif0_2(12 downto 0). Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning unused register count_ddr_enable_rcosc_2. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning unused register count_ddr_enable_q1_2. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning unused register count_sdif3_enable_rcosc_2. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning unused register count_sdif2_enable_rcosc_2. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning unused register count_sdif1_enable_rcosc_2. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning unused register count_sdif0_enable_rcosc_2. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning unused register count_sdif3_enable_q1_2. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning unused register count_sdif2_enable_q1_2. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning unused register count_sdif1_enable_q1_2. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1395:8:1395:9|Pruning unused register count_sdif0_enable_q1_2. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1311:8:1311:9|Pruning unused register count_sdif3_enable_3. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1252:8:1252:9|Pruning unused register count_sdif2_enable_3. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1193:8:1193:9|Pruning unused register count_sdif1_enable_3. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1134:8:1134:9|Pruning unused register count_sdif0_enable_3. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Pruning unused register count_ddr_enable_3. Make sure that there are no unused intermediate registers.
@W: CL177 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1331:8:1331:9|Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL190 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1376:8:1376:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1376:8:1376:9|Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1376:8:1376:9|Pruning unused register sm2_state(2 downto 0). Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":792:8:792:9|Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":792:8:792:9|Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers.
@N: CD630 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":34:7:34:14|Synthesizing coreapb3_lib.coreapb3.coreapb3_arch.
@N: CD604 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":665:16:665:29|OTHERS clause is not synthesized.
@W: CD434 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":1453:41:1453:46|Signal infill in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD638 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":616:7:616:15|Signal ia_prdata is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3_muxptob3.vhd":33:7:33:23|Synthesizing coreapb3_lib.coreapb3_muxptob3.coreapb3_muxptob3_arch.
Post processing for coreapb3_lib.coreapb3_muxptob3.coreapb3_muxptob3_arch
Post processing for coreapb3_lib.coreapb3.coreapb3_arch
@N: CD630 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\work\MC_System_sb\CCC_0\MC_System_sb_CCC_0_FCCC.vhd":8:7:8:29|Synthesizing work.mc_system_sb_ccc_0_fccc.def_arch.
@N: CD630 :"F:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.vhd":794:10:794:12|Synthesizing smartfusion2.ccc.syn_black_box.
Post processing for smartfusion2.ccc.syn_black_box
@N: CD630 :"F:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.vhd":576:10:576:12|Synthesizing smartfusion2.gnd.syn_black_box.
Post processing for smartfusion2.gnd.syn_black_box
@N: CD630 :"F:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.vhd":582:10:582:12|Synthesizing smartfusion2.vcc.syn_black_box.
Post processing for smartfusion2.vcc.syn_black_box
Post processing for work.mc_system_sb_ccc_0_fccc.def_arch
Post processing for work.mc_system_sb.rtl
Post processing for work.mc_system.rtl
@N: CD630 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\work\BLDC_HALL_Axis\BLDC_HALL_Axis.vhd":19:7:19:20|Synthesizing work.bldc_hall_axis.rtl.
Post processing for work.svm.svm
Post processing for work.mas_pi_spi.mas_pi_spi
Post processing for work.pi_controller_spi.pi_controller_spi
Post processing for work.pi_scheduler_spi.pi_scheduler_spi
Post processing for work.speed_id_iq_pi.speed_id_iq_pi
Post processing for work.seq_controller.seq_controller
Post processing for work.accumulator_rl.accumulator_rl
Post processing for work.rate_limiter.rate_limiter
Post processing for work.mas_pwm_scl.mas_pwm_scl
Post processing for work.pwm_scaling.pwm_scaling
Post processing for work.pwm3ph.pwm3ph
Post processing for work.accumulator_olmng.accumulator_olmng
Post processing for work.mas_olmng.mas_olmng
Post processing for work.olmng.olmng
Post processing for work.hall_mas.hall_mas
Post processing for work.hall_filter.hall_filter
Post processing for work.hall_interface.hall_interface
Post processing for work.mas_scheduler_foc.mas_scheduler_foc
Post processing for work.mas_foc.mas_foc
Post processing for work.inverse_clarke_foc.inverse_clarke_foc
Post processing for work.cordic_scale.cordic_scale
Post processing for work.cordic_rot_foc.cordic_rot_foc
Post processing for work.cordic_scheduler_foc.cordic_scheduler_foc
Post processing for work.clarke_foc.clarke_foc
Post processing for work.foc_transforms.foc_transforms
@N: CD630 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\hdl\apb3_hall_if.vhd":33:7:33:18|Synthesizing work.apb3_hall_if.apb3_hall_if.
Post processing for work.apb3_hall_if.apb3_hall_if
Post processing for adc_scaling_lib.mas_adc_scl.mas_adc_scl
Post processing for adc_scaling_lib.adc_scaling.adc_scaling
@N: CD630 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\hdl\adc_interface_795x.vhd":32:7:32:24|Synthesizing work.adc_interface_795x.adc_interface.
@N: CD231 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\hdl\adc_interface_795x.vhd":128:18:128:19|Using onehot encoding for type adc_op_state. For example, enumeration idle is mapped to "100000".
@N: CD604 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\hdl\adc_interface_795x.vhd":289:12:289:25|OTHERS clause is not synthesized.
@N: CD630 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\hdl\adc_interface_795x.vhd":434:7:434:16|Synthesizing work.spi_engine.spi_engine.
Post processing for work.spi_engine.spi_engine
@W: CL271 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\hdl\adc_interface_795x.vhd":539:8:539:9|Pruning unused bits 7 to 3 of s_sys_clk_count_4(7 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
Post processing for work.adc_interface_795x.adc_interface
@W: CL190 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\hdl\adc_interface_795x.vhd":197:4:197:5|Optimizing register bit s_spi_mosi(0) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\hdl\adc_interface_795x.vhd":197:4:197:5|Optimizing register bit s_spi_mosi(1) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\hdl\adc_interface_795x.vhd":197:4:197:5|Optimizing register bit s_spi_mosi(2) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\hdl\adc_interface_795x.vhd":197:4:197:5|Optimizing register bit s_spi_mosi(3) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\hdl\adc_interface_795x.vhd":197:4:197:5|Optimizing register bit s_spi_mosi(4) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\hdl\adc_interface_795x.vhd":197:4:197:5|Optimizing register bit s_spi_mosi(5) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\hdl\adc_interface_795x.vhd":197:4:197:5|Optimizing register bit s_spi_mosi(13) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\hdl\adc_interface_795x.vhd":197:4:197:5|Optimizing register bit s_spi_mosi(14) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\hdl\adc_interface_795x.vhd":197:4:197:5|Optimizing register bit s_spi_mosi(15) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\hdl\adc_interface_795x.vhd":197:4:197:5|Pruning register bits 15 to 13 of s_spi_mosi(15 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\hdl\adc_interface_795x.vhd":197:4:197:5|Pruning register bits 5 to 0 of s_spi_mosi(15 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
Post processing for work.bldc_hall_axis.rtl
Post processing for work.mc_system_top.rtl
@N: CL201 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\hdl\adc_interface_795x.vhd":197:4:197:5|Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 6 reachable states with original encodings of:
   000001
   000010
   000100
   001000
   010000
   100000
@W: CL279 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\hdl\adc_interface_795x.vhd":197:4:197:5|Pruning register bits 12 to 11 of s_spi_mosi(12 downto 6). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
Extracted state machine for register s_state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W: CL246 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\hdl\apb3_hall_if.vhd":62:4:62:10|Input port bits 31 to 12 of paddr_i(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\hdl\apb3_hall_if.vhd":64:4:64:11|Input port bits 31 to 18 of pwdata_i(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
Extracted state machine for register s_state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
Extracted state machine for register s_state
State machine has 3 reachable states with original encodings of:
   00
   10
   11
Extracted state machine for register s_state
State machine has 5 reachable states with original encodings of:
   00001
   00010
   00100
   01000
   10000
Extracted state machine for register s_ramp_present_state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
Extracted state machine for register s_state
State machine has 9 reachable states with original encodings of:
   000000001
   000000010
   000000100
   000001000
   000010000
   000100000
   001000000
   010000000
   100000000
Extracted state machine for register s_state
State machine has 5 reachable states with original encodings of:
   00001
   00010
   00100
   01000
   10000
Extracted state machine for register s_state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":75:0:75:4|Input IADDR is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":76:0:76:6|Input PRESETN is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":77:0:77:3|Input PCLK is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":109:0:109:7|Input PRDATAS2 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":110:0:110:7|Input PRDATAS3 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":111:0:111:7|Input PRDATAS4 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":112:0:112:7|Input PRDATAS5 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":113:0:113:7|Input PRDATAS6 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":114:0:114:7|Input PRDATAS7 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":115:0:115:7|Input PRDATAS8 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":116:0:116:7|Input PRDATAS9 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":117:0:117:8|Input PRDATAS10 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":118:0:118:8|Input PRDATAS11 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":119:0:119:8|Input PRDATAS12 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":120:0:120:8|Input PRDATAS13 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":121:0:121:8|Input PRDATAS14 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":122:0:122:8|Input PRDATAS15 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":126:0:126:7|Input PREADYS2 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":127:0:127:7|Input PREADYS3 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":128:0:128:7|Input PREADYS4 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":129:0:129:7|Input PREADYS5 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":130:0:130:7|Input PREADYS6 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":131:0:131:7|Input PREADYS7 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":132:0:132:7|Input PREADYS8 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":133:0:133:7|Input PREADYS9 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":134:0:134:8|Input PREADYS10 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":135:0:135:8|Input PREADYS11 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":136:0:136:8|Input PREADYS12 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":137:0:137:8|Input PREADYS13 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":138:0:138:8|Input PREADYS14 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":139:0:139:8|Input PREADYS15 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":143:0:143:8|Input PSLVERRS2 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":144:0:144:8|Input PSLVERRS3 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":145:0:145:8|Input PSLVERRS4 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":146:0:146:8|Input PSLVERRS5 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":147:0:147:8|Input PSLVERRS6 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":148:0:148:8|Input PSLVERRS7 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":149:0:149:8|Input PSLVERRS8 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":150:0:150:8|Input PSLVERRS9 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":151:0:151:9|Input PSLVERRS10 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":152:0:152:9|Input PSLVERRS11 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":153:0:153:9|Input PSLVERRS12 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":154:0:154:9|Input PSLVERRS13 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":155:0:155:9|Input PSLVERRS14 is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":156:0:156:9|Input PSLVERRS15 is unused.
@W: CL177 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@N: CL201 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1311:8:1311:9|Trying to extract state machine for register sdif3_state.
Extracted state machine for register sdif3_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1252:8:1252:9|Trying to extract state machine for register sdif2_state.
Extracted state machine for register sdif2_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1193:8:1193:9|Trying to extract state machine for register sdif1_state.
Extracted state machine for register sdif1_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1134:8:1134:9|Trying to extract state machine for register sdif0_state.
Extracted state machine for register sdif0_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Trying to extract state machine for register sm0_state.
Extracted state machine for register sm0_state
State machine has 7 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":96:4:96:12|Input CLK_LTSSM is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":123:4:123:12|Input FPLL_LOCK is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":126:4:126:18|Input SDIF0_SPLL_LOCK is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":135:4:135:18|Input SDIF1_SPLL_LOCK is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":139:4:139:18|Input SDIF2_SPLL_LOCK is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":143:4:143:18|Input SDIF3_SPLL_LOCK is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":157:4:157:13|Input SDIF0_PSEL is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":158:4:158:15|Input SDIF0_PWRITE is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":159:4:159:15|Input SDIF0_PRDATA is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":160:4:160:13|Input SDIF1_PSEL is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":161:4:161:15|Input SDIF1_PWRITE is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":162:4:162:15|Input SDIF1_PRDATA is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":163:4:163:13|Input SDIF2_PSEL is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":164:4:164:15|Input SDIF2_PWRITE is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":165:4:165:15|Input SDIF2_PRDATA is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":166:4:166:13|Input SDIF3_PSEL is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":167:4:167:15|Input SDIF3_PWRITE is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":168:4:168:15|Input SDIF3_PRDATA is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":174:4:174:21|Input SOFT_EXT_RESET_OUT is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":175:4:175:17|Input SOFT_RESET_F2M is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":176:4:176:16|Input SOFT_M3_RESET is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":177:4:177:33|Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":178:4:178:23|Input SOFT_FDDR_CORE_RESET is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":179:4:179:23|Input SOFT_SDIF0_PHY_RESET is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":180:4:180:24|Input SOFT_SDIF0_CORE_RESET is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":181:4:181:23|Input SOFT_SDIF1_PHY_RESET is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":182:4:182:24|Input SOFT_SDIF1_CORE_RESET is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":183:4:183:23|Input SOFT_SDIF2_PHY_RESET is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":184:4:184:24|Input SOFT_SDIF2_CORE_RESET is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":185:4:185:23|Input SOFT_SDIF3_PHY_RESET is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":186:4:186:24|Input SOFT_SDIF3_CORE_RESET is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":190:4:190:26|Input SOFT_SDIF0_0_CORE_RESET is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd":191:4:191:26|Input SOFT_SDIF0_1_CORE_RESET is unused.
@N: CL159 :"F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd":10:10:10:12|Input XTL is unused.

At c_vhdl Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 113MB peak: 120MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime

Process completed successfully.
# Wed Nov 29 13:44:48 2017

###########################################################]
Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016
@N|Running in 64-bit mode

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 78MB peak: 79MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Nov 29 13:44:48 2017

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:04s realtime, 0h:00m:04s cputime

Process completed successfully.
# Wed Nov 29 13:44:48 2017

###########################################################]
Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016
@N|Running in 64-bit mode

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 84MB peak: 85MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Nov 29 13:44:50 2017

###########################################################]
Pre-mapping Report

# Wed Nov 29 13:44:50 2017

Synopsys Generic Technology Pre-mapping, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.09M-2

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

Reading constraint file: F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\synthesis\MC_System_top.fdc
@L: F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\synthesis\MC_System_top_1_scck.rpt 
Printing clock  summary report in "F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\synthesis\MC_System_top_1_scck.rpt" file 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 129MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 129MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 129MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 129MB)

@W: BN132 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance MC_System_0.MC_System_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":703:8:703:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":719:8:719:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":735:8:735:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":751:8:751:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":781:8:781:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":703:8:703:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":719:8:719:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":735:8:735:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":751:8:751:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":781:8:781:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":703:8:703:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":719:8:719:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":735:8:735:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":751:8:751:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1331:8:1331:9|Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":303:8:303:9|Removing sequential instance result_ch4_o[11:0] (in view: work.adc_interface_795x(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":303:8:303:9|Removing sequential instance result_ch5_o[11:0] (in view: work.adc_interface_795x(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":303:8:303:9|Removing sequential instance result_ch6_o[11:0] (in view: work.adc_interface_795x(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":303:8:303:9|Removing sequential instance result_ch7_o[11:0] (in view: work.adc_interface_795x(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":303:8:303:9|Removing sequential instance result_ch8_o[11:0] (in view: work.adc_interface_795x(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":303:8:303:9|Removing sequential instance result_ch9_o[11:0] (in view: work.adc_interface_795x(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":303:8:303:9|Removing sequential instance result_ch10_o[11:0] (in view: work.adc_interface_795x(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":303:8:303:9|Removing sequential instance result_ch11_o[11:0] (in view: work.adc_interface_795x(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":303:8:303:9|Removing sequential instance result_ch12_o[11:0] (in view: work.adc_interface_795x(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":303:8:303:9|Removing sequential instance result_ch13_o[11:0] (in view: work.adc_interface_795x(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":303:8:303:9|Removing sequential instance result_ch14_o[11:0] (in view: work.adc_interface_795x(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":303:8:303:9|Removing sequential instance result_ch15_o[11:0] (in view: work.adc_interface_795x(adc_interface)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\apb3_hall_if.vhd":603:8:603:9|Removing sequential instance adc_control_reg_val_o[5:0] (in view: work.apb3_hall_if(apb3_hall_if)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\apb3_hall_if.vhd":603:8:603:9|Removing sequential instance adc_channel_ch0_o[15:0] (in view: work.apb3_hall_if(apb3_hall_if)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\apb3_hall_if.vhd":603:8:603:9|Removing sequential instance adc_channel_ch1_o[15:0] (in view: work.apb3_hall_if(apb3_hall_if)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\apb3_hall_if.vhd":603:8:603:9|Removing sequential instance adc_channel_ch2_o[15:0] (in view: work.apb3_hall_if(apb3_hall_if)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\apb3_hall_if.vhd":603:8:603:9|Removing sequential instance adc_channel_ch3_o[15:0] (in view: work.apb3_hall_if(apb3_hall_if)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Removing sequential instance DDR_READY_int (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Removing sequential instance SDIF_READY_int (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Removing sequential instance SDIF_RELEASED_int (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Removing sequential instance FDDR_CORE_RESET_N_int (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1134:8:1134:9|Removing sequential instance SDIF0_PHY_RESET_N_int (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1134:8:1134:9|Removing sequential instance SDIF0_CORE_RESET_N_0 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1193:8:1193:9|Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1193:8:1193:9|Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1252:8:1252:9|Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1252:8:1252:9|Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1311:8:1311:9|Removing sequential instance SDIF3_PHY_RESET_N_int (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1311:8:1311:9|Removing sequential instance SDIF3_CORE_RESET_N_0 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN115 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\work\mc_system_sb\mc_system_sb.vhd":530:0:530:11|Removing instance CORERESETP_0 (in view: work.MC_System_sb(rtl)) of type view:work.CoreResetP(rtl) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Removing sequential instance INIT_DONE_int (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1134:8:1134:9|Removing sequential instance sdif0_state[0:3] (in view: work.CoreResetP(rtl)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1193:8:1193:9|Removing sequential instance sdif1_state[0:3] (in view: work.CoreResetP(rtl)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1252:8:1252:9|Removing sequential instance sdif2_state[0:3] (in view: work.CoreResetP(rtl)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1311:8:1311:9|Removing sequential instance sdif3_state[0:3] (in view: work.CoreResetP(rtl)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1059:8:1059:9|Removing sequential instance sm0_state[0:6] (in view: work.CoreResetP(rtl)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":922:8:922:9|Removing sequential instance CONFIG2_DONE_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":803:8:803:9|Removing sequential instance sdif0_areset_n_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":814:8:814:9|Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":825:8:825:9|Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":836:8:836:9|Removing sequential instance sdif3_areset_n_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Removing sequential instance sdif3_spll_lock_q2 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":908:8:908:9|Removing sequential instance CONFIG1_DONE_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif3_core_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif2_core_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif1_core_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":922:8:922:9|Removing sequential instance CONFIG2_DONE_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":803:8:803:9|Removing sequential instance sdif0_areset_n_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":814:8:814:9|Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":825:8:825:9|Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":836:8:836:9|Removing sequential instance sdif3_areset_n_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":936:8:936:9|Removing sequential instance sdif3_spll_lock_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":908:8:908:9|Removing sequential instance CONFIG1_DONE_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif0_core_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance ddr_settled_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif3_core_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif2_core_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif1_core_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance release_sdif0_core_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1544:8:1544:9|Removing sequential instance ddr_settled_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1495:8:1495:9|Removing sequential instance release_sdif3_core (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1471:8:1471:9|Removing sequential instance release_sdif2_core (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1447:8:1447:9|Removing sequential instance release_sdif1_core (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1423:8:1423:9|Removing sequential instance release_sdif0_core (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":1519:8:1519:9|Removing sequential instance ddr_settled (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":770:8:770:9|Removing sequential instance sm0_areset_n_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":894:8:894:9|Removing sequential instance sdif3_areset_n_rcosc (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":883:8:883:9|Removing sequential instance sdif2_areset_n_rcosc (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":872:8:872:9|Removing sequential instance sdif1_areset_n_rcosc (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":861:8:861:9|Removing sequential instance sdif0_areset_n_rcosc (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":770:8:770:9|Removing sequential instance sm0_areset_n_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":850:8:850:9|Removing sequential instance sm0_areset_n_rcosc (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":894:8:894:9|Removing sequential instance sdif3_areset_n_rcosc_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":883:8:883:9|Removing sequential instance sdif2_areset_n_rcosc_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":872:8:872:9|Removing sequential instance sdif1_areset_n_rcosc_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":861:8:861:9|Removing sequential instance sdif0_areset_n_rcosc_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":850:8:850:9|Removing sequential instance sm0_areset_n_rcosc_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":608:8:608:9|Removing sequential instance MSS_HPMS_READY_int (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":593:8:593:9|Removing sequential instance mss_ready_select (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":593:8:593:9|Removing sequential instance mss_ready_state (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":577:8:577:9|Removing sequential instance FIC_2_APB_M_PRESET_N_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":565:8:565:9|Removing sequential instance RESET_N_M2F_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":577:8:577:9|Removing sequential instance FIC_2_APB_M_PRESET_N_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":565:8:565:9|Removing sequential instance RESET_N_M2F_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":553:8:553:9|Removing sequential instance POWER_ON_RESET_N_clk_base (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd":553:8:553:9|Removing sequential instance POWER_ON_RESET_N_q1 (in view: work.CoreResetP(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
syn_allowed_resources : blockrams=21,dsps=22  set on top level netlist MC_System_top

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 151MB peak: 152MB)



Clock Summary
*****************

Start      Requested     Requested     Clock        Clock                Clock
Clock      Frequency     Period        Type         Group                Load 
------------------------------------------------------------------------------
GL0        100.0 MHz     10.000        declared     default_clkgroup     2624 
GL1        100.0 MHz     10.000        declared     default_clkgroup     0    
System     100.0 MHz     10.000        system       system_clkgroup      0    
==============================================================================

Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\synthesis\MC_System_top_1.sap.

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 149MB peak: 152MB)

Encoding state machine state[0:5] (in view: work.adc_interface_795x(adc_interface))
original code -> new code
   000001 -> 000001
   000010 -> 000010
   000100 -> 000100
   001000 -> 001000
   010000 -> 010000
   100000 -> 100000
Encoding state machine s_state[0:3] (in view: adc_scaling_lib.ADC_SCALING(adc_scaling))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
Encoding state machine s_state[0:2] (in view: work.cordic_scale(cordic_scale))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine s_state[0:2] (in view: work.OLMNG(olmng))
original code -> new code
   00 -> 00
   10 -> 01
   11 -> 10
Encoding state machine s_state[0:4] (in view: work.PWM_SCALING(pwm_scaling))
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine s_ramp_present_state[0:2] (in view: work.RATE_LIMITER(rate_limiter))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine s_state[0:8] (in view: work.SEQ_CONTROLLER(seq_controller))
original code -> new code
   000000001 -> 000000001
   000000010 -> 000000010
   000000100 -> 000000100
   000001000 -> 000001000
   000010000 -> 000010000
   000100000 -> 000100000
   001000000 -> 001000000
   010000000 -> 010000000
   100000000 -> 100000000
Encoding state machine s_state[0:4] (in view: work.pi_controller_spi(pi_controller_spi))
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine s_state[0:2] (in view: work.SVM(svm))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\apb3_hall_if.vhd":603:8:603:9|Removing sequential instance pwm_gain_val_o[0] (in view: work.apb3_hall_if(apb3_hall_if)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
None
None
@W: MF511 |Found issues with constraints. Please check constraint checker report "F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\synthesis\MC_System_top_1_cck.rpt" .

Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 167MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 65MB peak: 167MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Nov 29 13:44:52 2017

###########################################################]
Map & Optimize Report

# Wed Nov 29 13:44:53 2017

Synopsys Generic Technology Mapper, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.09M-2

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)

@W: BN114 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\work\mc_system_sb\mc_system_sb.vhd":674:0:674:11|Removing instance SYSRESET_POR (in view: work.MC_System_sb(rtl)) of black box view:ACG4.SYSRESET(PRIM) because it does not drive other instances.

Available hyper_sources - for debug and ip models
	None Found

@W: FA239 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreapb3\4.1.100\rtl\vhdl\core\coreapb3.vhd":648:12:648:15|ROM CoreAPB3_0.iPSELS_raw_5[1:0] (in view: work.MC_System_sb(rtl)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreapb3\4.1.100\rtl\vhdl\core\coreapb3.vhd":648:12:648:15|ROM CoreAPB3_0.iPSELS_raw_5[1:0] (in view: work.MC_System_sb(rtl)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N: MO106 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\actel\directcore\coreapb3\4.1.100\rtl\vhdl\core\coreapb3.vhd":648:12:648:15|Found ROM .delname. (in view: work.MC_System_sb(rtl)) with 16 words by 2 bits.

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 147MB)

@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\apb3_hall_if.vhd":603:8:603:9|Removing sequential instance apb3_hall_if_0.pwm_gain_val_o[0] (in view: work.BLDC_HALL_Axis(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
Encoding state machine state[0:5] (in view: work.adc_interface_795x(adc_interface))
original code -> new code
   000001 -> 000001
   000010 -> 000010
   000100 -> 000100
   001000 -> 001000
   010000 -> 010000
   100000 -> 100000
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[15] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[14] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[13] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[12] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[11] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[10] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[9] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[8] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[7] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[6] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[5] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[4] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[3] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[2] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: BN132 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":368:8:368:9|Removing instance BLDC_HALL_Axis_0.adc_interface_795x_0.s_channel_sel[1] because it is equivalent to instance BLDC_HALL_Axis_0.adc_interface_795x_0.s_channel_sel[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":584:8:584:9|Register bit s_sdo_reg[0] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":584:8:584:9|Register bit s_sdo_reg[1] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":584:8:584:9|Register bit s_sdo_reg[2] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":584:8:584:9|Register bit s_sdo_reg[3] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":584:8:584:9|Register bit s_sdo_reg[4] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\hdl\adc_interface_795x.vhd":584:8:584:9|Register bit s_sdo_reg[5] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
Encoding state machine s_state[0:3] (in view: adc_scaling_lib.ADC_SCALING(adc_scaling))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
Encoding state machine s_state[0:2] (in view: work.cordic_scale(cordic_scale))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine s_state[0:2] (in view: work.OLMNG(olmng))
original code -> new code
   00 -> 00
   10 -> 01
   11 -> 10
Encoding state machine s_state[0:4] (in view: work.PWM_SCALING(pwm_scaling))
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine s_ramp_present_state[0:2] (in view: work.RATE_LIMITER(rate_limiter))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine s_state[0:8] (in view: work.SEQ_CONTROLLER(seq_controller))
original code -> new code
   000000001 -> 000000001
   000000010 -> 000000010
   000000100 -> 000000100
   000001000 -> 000001000
   000010000 -> 000010000
   000100000 -> 000100000
   001000000 -> 001000000
   010000000 -> 010000000
   100000000 -> 100000000
Encoding state machine s_state[0:4] (in view: work.pi_controller_spi(pi_controller_spi))
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine s_state[0:2] (in view: work.SVM(svm))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10

Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 156MB peak: 168MB)


Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 168MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 165MB peak: 169MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 164MB peak: 175MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 166MB peak: 175MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 170MB peak: 175MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 168MB peak: 175MB)


Finished preparing to map (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 170MB peak: 175MB)


Finished technology mapping (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 195MB peak: 243MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:09s		    -1.45ns		3942 /      2276
   2		0h:00m:10s		    -1.45ns		3426 /      2276
   3		0h:00m:10s		    -2.16ns		3426 /      2276
   4		0h:00m:10s		    -1.31ns		3426 /      2276

   5		0h:00m:10s		    -1.31ns		3426 /      2276


   6		0h:00m:11s		    -1.31ns		3426 /      2276
@N: FP130 |Promoting Net MC_System_0_FIC_0_LOCK on CLKINT  I_52 

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 203MB peak: 243MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:11s; Memory used current: 203MB peak: 243MB)



@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

Clock optimization not enabled
1 non-gated/non-generated clock tree(s) driving 2289 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

===================================================================== Non-Gated/Non-Generated Clocks ======================================================================
Clock Tree ID     Driving Element                                   Drive Element Type              Fanout     Sample Instance                                             
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@K:CKID0001       MC_System_0.MC_System_sb_0.CCC_0.GL0_net_keep     clock definition on keepbuf     2289       MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST
===========================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 161MB peak: 243MB)

Writing Analyst data base F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\synthesis\synwork\MC_System_top_1_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 196MB peak: 243MB)

Writing Verilog Simulation files
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 194MB peak: 243MB)


Start final timing analysis (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:15s; Memory used current: 194MB peak: 243MB)

@W: MT246 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablhl10\liberoproject\sk1ablhl10_5_1\component\work\mc_system_sb\ccc_0\mc_system_sb_ccc_0_fccc.vhd":110:4:110:11|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@N: MT615 |Found clock GL0 with period 10.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Wed Nov 29 13:45:09 2017
#


Top view:               MC_System_top
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLHL10\LiberoProject\SK1ABLHL10_5_1\synthesis\MC_System_top.fdc
                       
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: 0.637

                   Requested     Estimated      Requested     Estimated               Clock        Clock           
Starting Clock     Frequency     Frequency      Period        Period        Slack     Type         Group           
-------------------------------------------------------------------------------------------------------------------
GL0                100.0 MHz     106.8 MHz      10.000        9.363         0.637     declared     default_clkgroup
System             100.0 MHz     1029.4 MHz     10.000        0.971         9.029     system       system_clkgroup 
===================================================================================================================
@W: MT548 :"f:/svn/motorcontrol/release/webrelease/liberoprojects/sk1ablhl10/liberoproject/sk1ablhl10_5_1/synthesis/mc_system_top.fdc":19:0:19:0|Source for clock GL1 not found in netlist. Run the constraint checker to verify if constraints are applied correctly.





Clock Relationships
*******************

Clocks            |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
--------------------------------------------------------------------------------------------------------
Starting  Ending  |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
--------------------------------------------------------------------------------------------------------
System    System  |  10.000      9.029  |  No paths    -      |  No paths    -      |  No paths    -    
System    GL0     |  10.000      1.763  |  No paths    -      |  No paths    -      |  No paths    -    
GL0       GL0     |  10.000      0.637  |  No paths    -      |  No paths    -      |  No paths    -    
========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: GL0
====================================



Starting Points with Worst Slack
********************************

                                                                 Starting                                                                            Arrival          
Instance                                                         Reference     Type        Pin                Net                                    Time        Slack
                                                                 Clock                                                                                                
----------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_ADDR[10]     MC_System_0_AMBA_SLAVE_0_PADDR[10]     3.357       0.637
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_ADDR[1]      MC_System_0_AMBA_SLAVE_0_PADDR[1]      3.058       0.777
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_ADDR[8]      MC_System_0_AMBA_SLAVE_0_PADDR[8]      3.354       0.787
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_ADDR[5]      MC_System_0_AMBA_SLAVE_0_PADDR[5]      3.110       0.811
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_ADDR[2]      MC_System_0_AMBA_SLAVE_0_PADDR[2]      3.040       0.814
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_ADDR[6]      MC_System_0_AMBA_SLAVE_0_PADDR[6]      3.185       0.864
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_ADDR[7]      MC_System_0_AMBA_SLAVE_0_PADDR[7]      3.055       0.867
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_ADDR[0]      MC_System_0_AMBA_SLAVE_0_PADDR[0]      3.112       0.919
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_ADDR[3]      MC_System_0_AMBA_SLAVE_0_PADDR[3]      3.040       0.954
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_ADDR[4]      MC_System_0_AMBA_SLAVE_0_PADDR[4]      3.026       1.051
======================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                 Starting                                                                                             Required          
Instance                                                         Reference     Type        Pin                 Net                                                    Time         Slack
                                                                 Clock                                                                                                                  
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_RDATA[6]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[6]      9.651        0.637
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_RDATA[5]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[5]      9.672        0.658
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_RDATA[4]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]      9.539        0.785
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_RDATA[3]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]      9.483        0.789
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_RDATA[16]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[16]     9.647        0.820
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_RDATA[1]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[1]      9.684        0.824
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_RDATA[2]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[2]      9.706        0.846
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_RDATA[14]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[14]     9.688        0.861
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_RDATA[15]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[15]     9.695        0.868
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_RDATA[8]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[8]      9.668        0.890
========================================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.349
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.651

    - Propagation time:                      9.014
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     0.637

    Number of logic level(s):                5
    Starting point:                          MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[10]
    Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[6]
    The start point is clocked by            GL0 [rising] on pin CLK_BASE
    The end   point is clocked by            GL0 [rising] on pin CLK_BASE

Instance / Net                                                                               Pin                Pin               Arrival     No. of    
Name                                                                             Type        Name               Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST                     MSS_010     F_HM0_ADDR[10]     Out     3.357     3.357       -         
MC_System_0_AMBA_SLAVE_0_PADDR[10]                                               Net         -                  -       0.980     -           3         
BLDC_HALL_Axis_0.apb3_hall_if_0.pwm_period_val_o_1_sqmuxa_0_a2_1                 CFG4        B                  In      -         4.337       -         
BLDC_HALL_Axis_0.apb3_hall_if_0.pwm_period_val_o_1_sqmuxa_0_a2_1                 CFG4        Y                  Out     0.125     4.461       -         
N_1834                                                                           Net         -                  -       0.876     -           25        
BLDC_HALL_Axis_0.apb3_hall_if_0.seq_cntl_cl_omega_o_1_sqmuxa_0_a2_0_RNI69711     CFG4        D                  In      -         5.337       -         
BLDC_HALL_Axis_0.apb3_hall_if_0.seq_cntl_cl_omega_o_1_sqmuxa_0_a2_0_RNI69711     CFG4        Y                  Out     0.250     5.587       -         
N_1846                                                                           Net         -                  -       0.761     -           12        
BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_9_0[6]                                CFG4        D                  In      -         6.348       -         
BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_9_0[6]                                CFG4        Y                  Out     0.250     6.598       -         
prdata_o_1_9_0[6]                                                                Net         -                  -       0.483     -           1         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[6]                  CFG4        C                  In      -         7.082       -         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[6]                  CFG4        Y                  Out     0.194     7.276       -         
PRDATA_1[6]                                                                      Net         -                  -       0.483     -           1         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[6]                    CFG4        D                  In      -         7.759       -         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[6]                    CFG4        Y                  Out     0.284     8.043       -         
MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[6]                                Net         -                  -       0.971     -           1         
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST                     MSS_010     F_HM0_RDATA[6]     In      -         9.014       -         
========================================================================================================================================================
Total path delay (propagation time + setup) of 9.363 is 4.809(51.4%) logic and 4.554(48.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                         Starting                                                                                           Arrival          
Instance                                                 Reference     Type               Pin        Net                                                    Time        Slack
                                                         Clock                                                                                                               
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.CCC_0.CCC_INST                System        CCC                LOCK       LOCK                                                   0.000       1.763
MC_System_0.MC_System_sb_0.FABOSC_0.I_RCOSC_25_50MHZ     System        RCOSC_25_50MHZ     CLKOUT     FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     0.000       9.029
=============================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                 Starting                                                                                             Required          
Instance                                                         Reference     Type        Pin                 Net                                                    Time         Slack
                                                                 Clock                                                                                                                  
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[4]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]      9.539        1.763
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[3]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]      9.483        1.895
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[23]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[18]     9.604        2.125
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[17]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[17]     9.675        2.133
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[29]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[18]     9.625        2.146
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[30]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[18]     9.629        2.150
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[22]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[18]     9.652        2.173
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[21]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[18]     9.657        2.178
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[20]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[18]     9.677        2.198
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[24]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[18]     9.678        2.199
========================================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.461
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.539

    - Propagation time:                      7.776
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 1.763

    Number of logic level(s):                8
    Starting point:                          MC_System_0.MC_System_sb_0.CCC_0.CCC_INST / LOCK
    Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[4]
    The start point is clocked by            System [rising]
    The end   point is clocked by            GL0 [rising] on pin CLK_BASE

Instance / Net                                                                 Pin                Pin               Arrival     No. of    
Name                                                               Type        Name               Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.CCC_0.CCC_INST                          CCC         LOCK               Out     0.000     0.000       -         
LOCK                                                               Net         -                  -       0.971     -           1         
MC_System_0.MC_System_sb_0.CCC_0.CCC_INST_RNI2QPF                  CLKINT      A                  In      -         0.971       -         
MC_System_0.MC_System_sb_0.CCC_0.CCC_INST_RNI2QPF                  CLKINT      Y                  Out     0.337     1.308       -         
MC_System_0_FIC_0_LOCK                                             Net         -                  -       0.993     -           2307      
BLDC_HALL_Axis_0.OLMNG_0.s_theta_ol_RNIJB1M[4]                     CFG3        A                  In      -         2.301       -         
BLDC_HALL_Axis_0.OLMNG_0.s_theta_ol_RNIJB1M[4]                     CFG3        Y                  Out     0.067     2.368       -         
theta_o[4]                                                         Net         -                  -       0.590     -           3         
BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_13_i_m3_0_0_wmux[4]     ARI1        D                  In      -         2.958       -         
BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_13_i_m3_0_0_wmux[4]     ARI1        Y                  Out     0.284     3.242       -         
prdata_o_1_13_i_m3_0_0_y0[4]                                       Net         -                  -       0.324     -           1         
BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_13_i_m3_0_wmux_0[4]     ARI1        A                  In      -         3.566       -         
BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_13_i_m3_0_wmux_0[4]     ARI1        Y                  Out     0.087     3.653       -         
N_758                                                              Net         -                  -       0.971     -           1         
BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_9_0_RNO_0[4]            CFG4        D                  In      -         4.625       -         
BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_9_0_RNO_0[4]            CFG4        Y                  Out     0.276     4.900       -         
prdata_N_4_3                                                       Net         -                  -       0.483     -           1         
BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_9_0[4]                  CFG4        C                  In      -         5.384       -         
BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_9_0[4]                  CFG4        Y                  Out     0.196     5.580       -         
prdata_o_1_9_0[4]                                                  Net         -                  -       0.483     -           1         
BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_9_3[4]                  CFG4        C                  In      -         6.063       -         
BLDC_HALL_Axis_0.apb3_hall_if_0.prdata_o_1_9_3[4]                  CFG4        Y                  Out     0.182     6.245       -         
prdata_o_1_9_3[4]                                                  Net         -                  -       0.483     -           1         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[4]      CFG3        A                  In      -         6.729       -         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[4]      CFG3        Y                  Out     0.076     6.804       -         
MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]                  Net         -                  -       0.971     -           1         
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST       MSS_010     F_HM0_RDATA[4]     In      -         7.776       -         
==========================================================================================================================================
Total path delay (propagation time + setup) of 8.237 is 1.966(23.9%) logic and 6.271(76.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 194MB peak: 243MB)


Finished timing report (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 194MB peak: 243MB)

---------------------------------------
Resource Usage Report for MC_System_top 

Mapping to part: m2s010fbga484-1
Cell usage:
CCC             1 use
CLKINT          2 uses
MSS_010         1 use
RCOSC_25_50MHZ  1 use
CFG1           15 uses
CFG2           461 uses
CFG3           712 uses
CFG4           744 uses

Carry cells:
ARI1            1372 uses - used for arithmetic functions
ARI1            152 uses - used for Wide-Mux implementation
Total ARI1      1524 uses


Sequential Cells: 
SLE            2276 uses

DSP Blocks:    7 of 22 (31%)
 MACC:         3 Mults
 MACC:         4 MultAdds

I/O ports: 28
I/O primitives: 27
BIBUF          8 uses
INBUF          7 uses
OUTBUF         11 uses
TRIBUFF        1 use


Global Clock Buffers: 2 of 8 (25%)


Total LUTs:    3456

Extra resources required for RAM and MACC interface logic during P&R:

RAM64x18 Interface Logic : SLEs = 0; LUTs = 0;
RAM1K18  Interface Logic : SLEs = 0; LUTs = 0;
MACC     Interface Logic : SLEs = 252; LUTs = 252;

Total number of SLEs after P&R:  2276 + 0 + 0 + 252 = 2528;
Total number of LUTs after P&R:  3456 + 0 + 0 + 252 = 3708;

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 42MB peak: 243MB)

Process took 0h:00m:16s realtime, 0h:00m:16s cputime
# Wed Nov 29 13:45:09 2017

###########################################################]
