#Build: Synplify Pro I-2013.09M-SP1 , Build 034R, Jan 17 2014 #install: C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1 #OS: Windows 7 6.1 #Hostname: W764-PINNINTIA #Implementation: synthesis $ Start of Compile #Wed Oct 08 11:16:14 2014 Synopsys VHDL Compiler, version comp201309rcp1, Build 078R, built Jan 14 2014 @N: : | Running in 64-bit mode Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. @N:CD720 : std.vhd(146) | Setting time resolution to ns @N: : sqmng.vhd(29) | Top entity is set to SQMNG. Options changed - recompiling @W:CD134 : pi_controller.vhd(155) | No such identifier, output_y_o, of proper type in current declarative region @W:CD134 : pi_controller.vhd(156) | No such identifier, acc_out_o, of proper type in current declarative region VHDL syntax check successful! @N:CD231 : std1164.vhd(913) | Using onehot encoding for type mvl9plus ('U'="1000000000") @N:CD630 : sqmng.vhd(29) | Synthesizing work.sqmng.sqmng @N:CD233 : sqmng.vhd(91) | Using sequential encoding for type fsm_state @W:CG296 : sqmng.vhd(150) | Incomplete sensitivity list - assuming completeness @W:CG290 : sqmng.vhd(152) | Referenced variable s_reset_state is not in sensitivity list @W:CG296 : sqmng.vhd(172) | Incomplete sensitivity list - assuming completeness @W:CG290 : sqmng.vhd(174) | Referenced variable s_reset_state is not in sensitivity list @W:CG296 : sqmng.vhd(217) | Incomplete sensitivity list - assuming completeness @W:CG290 : sqmng.vhd(219) | Referenced variable s_reset_state is not in sensitivity list @W:CG296 : sqmng.vhd(265) | Incomplete sensitivity list - assuming completeness @W:CG290 : sqmng.vhd(267) | Referenced variable s_reset_state is not in sensitivity list @W:CG296 : sqmng.vhd(282) | Incomplete sensitivity list - assuming completeness @W:CG290 : sqmng.vhd(284) | Referenced variable s_reset_state is not in sensitivity list @W:CG296 : sqmng.vhd(308) | Incomplete sensitivity list - assuming completeness @W:CG290 : sqmng.vhd(310) | Referenced variable s_reset_state is not in sensitivity list @W:CG296 : sqmng.vhd(330) | Incomplete sensitivity list - assuming completeness @W:CG290 : sqmng.vhd(332) | Referenced variable s_reset_state is not in sensitivity list @W:CD434 : sqmng.vhd(376) | Signal speed_error_abs in the sensitivity list is not used in the process @W:CG296 : sqmng.vhd(401) | Incomplete sensitivity list - assuming completeness @W:CG290 : sqmng.vhd(406) | Referenced variable w_cl_abs is not in sensitivity list @W:CG296 : sqmng.vhd(469) | Incomplete sensitivity list - assuming completeness @W:CG290 : sqmng.vhd(471) | Referenced variable s_reset_state is not in sensitivity list @W:CG296 : sqmng.vhd(487) | Incomplete sensitivity list - assuming completeness @W:CG290 : sqmng.vhd(489) | Referenced variable s_reset_state is not in sensitivity list @W:CD638 : sqmng.vhd(97) | Signal s_r_angle is undriven @W:CD638 : sqmng.vhd(98) | Signal s_r_coef_a is undriven @W:CD638 : sqmng.vhd(99) | Signal s_r_coef_b is undriven @W:CD638 : sqmng.vhd(100) | Signal s_ca_mul_inp is undriven @W:CD638 : sqmng.vhd(101) | Signal s_cb_mul_out is undriven @W:CD638 : sqmng.vhd(102) | Signal s_ca_mul_ang is undriven @W:CD638 : sqmng.vhd(103) | Signal speed_o_sig is undriven @W:CD638 : sqmng.vhd(104) | Signal speed_prv is undriven @W:CD638 : sqmng.vhd(105) | Signal sub is undriven @W:CD638 : sqmng.vhd(107) | Signal s_mas_en_o is undriven @W:CD638 : sqmng.vhd(119) | Signal speed_act_i_abs is undriven @W:CD638 : sqmng.vhd(121) | Signal speed_ref_in_by_2 is undriven Post processing for work.sqmng.sqmng @W:CL169 : sqmng.vhd(152) | Pruning register s_start_d1_2 @W:CL111 : sqmng.vhd(219) | All reachable assignments to sub_o assign '0'; register removed by optimization @W:CL190 : sqmng.vhd(310) | Optimizing register bit theta_scale_val_limit(17) to a constant 0 @W:CL260 : sqmng.vhd(310) | Pruning register bit 17 of theta_scale_val_limit(17 downto 0) @W:CL260 : sqmng.vhd(284) | Pruning register bit 17 of theta_scale_val(17 downto 0) @N:CL201 : sqmng.vhd(174) | Trying to extract state machine for register state Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL279 : sqmng.vhd(267) | Pruning register bits 35 to 22 of s_omega_scl_reg(35 downto 0) @W:CL279 : sqmng.vhd(219) | Pruning register bits 35 to 22 of add_c_o(35 downto 0) @W:CL159 : sqmng.vhd(52) | Input speed_act_i is unused @END At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 88MB peak: 89MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Oct 08 11:16:14 2014 ###########################################################] Pre-mapping Report Synopsys Generic Technology Pre-mapping, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2013.09M-SP1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) Reading constraint file: C:\SK1ASTSL10_3_0_multi_axis\synthesis\MC_System_top_sdc.sdc Linked File: MC_System_top_scck.rpt Printing clock summary report in "C:\SK1ASTSL10_3_0_multi_axis\synthesis\MC_System_top_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) syn_allowed_resources : blockrams=21 set on top level netlist SQMNG Clock Summary ************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ----------------------------------------------------------------------------------------------------------------- MC_System_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 50.0 MHz 20.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_0 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_1 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_2 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_3 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_4 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_5 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_6 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_7 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_8 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_9 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_10 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_11 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_12 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_13 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_14 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_15 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_16 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_17 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_18 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_19 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_20 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_21 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_22 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_23 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_24 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_25 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_26 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_27 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_28 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_29 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_30 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_31 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_32 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_33 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_34 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_35 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_36 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_37 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_38 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_39 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_40 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_41 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_42 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_43 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_44 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_45 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_46 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_47 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_48 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_49 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_50 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_51 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_52 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_53 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_54 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_55 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_56 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_57 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_58 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_59 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_60 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_61 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_62 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_63 100.0 MHz 10.000 declared group_55_166 MC_System_CCC_0_FCCC|GL1_net_inferred_clock 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_0 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_1 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_2 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_3 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_4 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_5 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_6 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_7 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_8 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_9 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_10 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_11 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_12 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_13 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_14 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_15 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_16 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_17 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_18 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_19 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_20 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_21 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_22 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_23 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_24 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_25 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_26 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_27 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_28 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_29 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_30 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_31 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_32 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_33 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_34 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_35 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_36 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_37 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_38 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_39 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_40 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_41 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_42 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_43 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_44 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_45 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_46 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_47 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_48 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_49 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_50 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_51 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_52 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_53 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_54 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_55 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_56 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_57 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_58 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_59 100.0 MHz 10.000 virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_60 100.0 MHz 10.000 declared group_55_165 SQMNG|sys_clk_i 100.0 MHz 10.000 inferred Inferred_clkgroup_0 ================================================================================================================= @W:MT530 : sqmng.vhd(489) | Found inferred clock SQMNG|sys_clk_i which controls 140 sequential elements including init_theta_s. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\SK1ASTSL10_3_0_multi_axis\synthesis\MC_System_top.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 133MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Oct 08 11:16:16 2014 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2013.09M-SP1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 132MB) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 132MB) Encoding state machine state[0:2] (view:work.SQMNG(sqmng)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:FX404 : sqmng.vhd(399) | Found addmux in view:work.SQMNG(sqmng) inst inf_abs2[17:0] from inf_abs2_a_2[17:0] @N:FX404 : sqmng.vhd(361) | Found addmux in view:work.SQMNG(sqmng) inst inf_abs1[17:0] from inf_abs1_a_1[17:0] @N:FX404 : sqmng.vhd(360) | Found addmux in view:work.SQMNG(sqmng) inst inf_abs0[17:0] from inf_abs0_a_0[17:0] @N:FX404 : sqmng.vhd(435) | Found addmux in view:work.SQMNG(sqmng) inst init_speedpi_o_1[18:1] from un3_init_speedpi_o[17:0] @N:FX404 : sqmng.vhd(460) | Found addmux in view:work.SQMNG(sqmng) inst init_iqpi_o[17:0] from un4_init_iqpi_o[17:0] Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ ------------------------------------------------------------ @N:FP130 : | Promoting Net reset_i_c on CLKINT I_172 @N:FP130 : | Promoting Net sys_clk_i_c on CLKINT I_173 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 1 non-gated/non-generated clock tree(s) driving 139 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId0001 sys_clk_i port 139 s_start_d ======================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Writing Analyst data base C:\SK1ASTSL10_3_0_multi_axis\synthesis\MC_System_top.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) Writing EDIF Netlist and constraint files @W:MT558 : mc_system_top_sdc.sdc(5) | Unable to locate source for clock MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_60. Clock will not be forward annotated @W:MT558 : mc_system_top_sdc.sdc(6) | Unable to locate source for clock MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_63. Clock will not be forward annotated @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF @W:BW152 : mc_system_top_sdc.sdc(165) | Cannot forward annotate set_clock_groups command because clock MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_60 is not referenced @W:BW152 : mc_system_top_sdc.sdc(166) | Cannot forward annotate set_clock_groups command because clock MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_63 is not referenced I-2013.09M-SP1 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 135MB) @W:MT420 : | Found inferred clock SQMNG|sys_clk_i with period 10.00ns. Please declare a user-defined clock on object "p:sys_clk_i" ##### START OF TIMING REPORT #####[ # Timing Report written on Wed Oct 08 11:16:18 2014 # Top view: SQMNG Requested Frequency: 50.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): C:\SK1ASTSL10_3_0_multi_axis\synthesis\MC_System_top_sdc.sdc @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 7.033 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------------- MC_System_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 50.0 MHz NA 20.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_0 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_1 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_2 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_3 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_4 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_5 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_6 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_7 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_8 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_9 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_10 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_11 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_12 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_13 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_14 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_15 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_16 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_17 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_18 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_19 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_20 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_21 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_22 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_23 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_24 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_25 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_26 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_27 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_28 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_29 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_30 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_31 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_32 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_33 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_34 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_35 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_36 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_37 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_38 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_39 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_40 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_41 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_42 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_43 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_44 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_45 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_46 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_47 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_48 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_49 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_50 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_51 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_52 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_53 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_54 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_55 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_56 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_57 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_58 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_59 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_60 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_61 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_62 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_63 100.0 MHz NA 10.000 NA NA declared group_55_166 MC_System_CCC_0_FCCC|GL1_net_inferred_clock 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_0 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_1 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_2 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_3 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_4 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_5 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_6 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_7 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_8 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_9 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_10 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_11 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_12 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_13 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_14 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_15 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_16 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_17 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_18 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_19 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_20 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_21 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_22 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_23 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_24 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_25 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_26 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_27 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_28 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_29 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_30 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_31 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_32 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_33 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_34 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_35 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_36 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_37 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_38 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_39 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_40 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_41 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_42 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_43 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_44 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_45 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_46 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_47 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_48 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_49 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_50 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_51 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_52 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_53 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_54 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_55 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_56 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_57 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_58 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_59 100.0 MHz NA 10.000 NA NA virtual default_clkgroup MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_60 100.0 MHz NA 10.000 NA NA declared group_55_165 SQMNG|sys_clk_i 100.0 MHz 337.0 MHz 10.000 2.967 7.033 inferred Inferred_clkgroup_0 ======================================================================================================================================================= @W:MT548 : mc_system_top_sdc.sdc(5) | Source for clock MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_60 not found in netlist @W:MT548 : mc_system_top_sdc.sdc(6) | Source for clock MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_63 not found in netlist Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------ Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------ SQMNG|sys_clk_i SQMNG|sys_clk_i | 10.000 7.033 | No paths - | No paths - | No paths - ======================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: SQMNG|sys_clk_i ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------- state[0] SQMNG|sys_clk_i SLE Q state[0] 0.094 7.033 state[1] SQMNG|sys_clk_i SLE Q state[1] 0.094 7.524 s_start_d SQMNG|sys_clk_i SLE Q s_start_d 0.094 8.080 init_theta_s SQMNG|sys_clk_i SLE Q init_theta_s 0.094 8.141 theta_scale_val_limit[4] SQMNG|sys_clk_i SLE Q theta_scale_val_limit[4] 0.076 8.405 theta_scale_val_limit[5] SQMNG|sys_clk_i SLE Q theta_scale_val_limit[5] 0.076 8.405 theta_scale_val_limit[6] SQMNG|sys_clk_i SLE Q theta_scale_val_limit[6] 0.076 8.405 theta_scale_val_limit[7] SQMNG|sys_clk_i SLE Q theta_scale_val_limit[7] 0.076 8.405 theta_scale_val_limit[8] SQMNG|sys_clk_i SLE Q theta_scale_val_limit[8] 0.076 8.405 theta_scale_val_limit[9] SQMNG|sys_clk_i SLE Q theta_scale_val_limit[9] 0.076 8.405 ================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------- s_omega_scl_reg[0] SQMNG|sys_clk_i SLE EN mas_en_o_0_sqmuxa 9.707 7.033 s_omega_scl_reg[1] SQMNG|sys_clk_i SLE EN mas_en_o_0_sqmuxa 9.707 7.033 s_omega_scl_reg[2] SQMNG|sys_clk_i SLE EN mas_en_o_0_sqmuxa 9.707 7.033 s_omega_scl_reg[3] SQMNG|sys_clk_i SLE EN mas_en_o_0_sqmuxa 9.707 7.033 s_omega_scl_reg[4] SQMNG|sys_clk_i SLE EN mas_en_o_0_sqmuxa 9.707 7.033 s_omega_scl_reg[5] SQMNG|sys_clk_i SLE EN mas_en_o_0_sqmuxa 9.707 7.033 s_omega_scl_reg[6] SQMNG|sys_clk_i SLE EN mas_en_o_0_sqmuxa 9.707 7.033 s_omega_scl_reg[7] SQMNG|sys_clk_i SLE EN mas_en_o_0_sqmuxa 9.707 7.033 s_omega_scl_reg[8] SQMNG|sys_clk_i SLE EN mas_en_o_0_sqmuxa 9.707 7.033 s_omega_scl_reg[9] SQMNG|sys_clk_i SLE EN mas_en_o_0_sqmuxa 9.707 7.033 ==================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.293 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.707 - Propagation time: 2.674 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 7.033 Number of logic level(s): 1 Starting point: state[0] / Q Ending point: s_omega_scl_reg[0] / EN The start point is clocked by SQMNG|sys_clk_i [rising] on pin CLK The end point is clocked by SQMNG|sys_clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------- state[0] SLE Q Out 0.094 0.094 - state[0] Net - - 1.518 - 62 mas_en_o_0_sqmuxa_0_a3 CFG2 A In - 1.612 - mas_en_o_0_sqmuxa_0_a3 CFG2 Y Out 0.076 1.688 - mas_en_o_0_sqmuxa Net - - 0.986 - 22 s_omega_scl_reg[0] SLE EN In - 2.674 - ===================================================================================== Total path delay (propagation time + setup) of 2.967 is 0.463(15.6%) logic and 2.504(84.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report for SQMNG Mapping to part: m2s010fbga484-1 Cell usage: CLKINT 2 uses CFG2 32 uses CFG3 37 uses CFG4 43 uses Carry primitives used for arithmetic functions: ARI1 177 uses Sequential Cells: SLE 139 uses DSP Blocks: 0 I/O ports: 356 I/O primitives: 338 INBUF 187 uses OUTBUF 151 uses Global Clock Buffers: 2 Total LUTs: 289 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 50MB peak: 135MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Oct 08 11:16:18 2014 ###########################################################]