Synopsys VHDL Compiler, version comp201403sp1p1, Build 095R, built Oct  9 2014
@N|Running in 64-bit mode
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

@N: CD720 :"E:\Microsemi\Libero_v11.5\Synopsys\synplify_I201403MSP1\lib\vhd2008\std.vhd":146:18:146:21|Setting time resolution to ns
@N:"E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10_bup\SK2ABLSL10_5_0\component\work\MC_System_top\MC_System_top.vhd":17:7:17:19|Top entity is set to MC_System_top.
VHDL syntax check successful!
@END

At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 80MB peak: 81MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Jul 23 13:44:42 2015

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