# Synopsys Constraint Checker, version mapact, Build 1085R, built Oct 16 2013
# Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

# Written on Mon Jul 07 16:56:08 2014


##### DESIGN INFO #######################################################

Top View:                "MC_System_top"
Constraint File(s):      "D:\MS_MC_single_axis_Ver2\MS_MC_single_axis\synthesis\MC_System_top_syn.fdc"




##### SUMMARY ############################################################

Found 0 issues in 0 out of 2 constraints


##### DETAILS ############################################################



Clock Relationships
*******************

Starting                                       Ending                                         |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise                     
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                         System                                         |     1000.000         |     No paths         |     No paths         |     No paths                         
System                                         MC_System_0/CCC_0/CCC_INST/INST_CCC_IP:GL0     |     20.000           |     No paths         |     No paths         |     No paths                         
MC_System_0/CCC_0/CCC_INST/INST_CCC_IP:GL0     System                                         |     20.000           |     No paths         |     No paths         |     No paths                         
MC_System_0/CCC_0/CCC_INST/INST_CCC_IP:GL0     MC_System_0/CCC_0/CCC_INST/INST_CCC_IP:GL0     |     20.000           |     No paths         |     No paths         |     No paths                         
=========================================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.


Unconstrained Start/End Points
******************************

p:A0_ADC_BIP_O
p:A0_ADC_CONV_O
p:A0_ADC_SCK_O
p:A0_ADC_SDO_I
p:A0_ADC_U_I_SEL
p:A0_PWM_UH_O
p:A0_PWM_UL_O
p:A0_PWM_VH_O
p:A0_PWM_VL_O
p:A0_PWM_WH_O
p:A0_PWM_WL_O
p:A0_T603CLRERR_AF23_O
p:A0_T603ENABLE_AK11_O
p:GPIO_0_M2F
p:GPIO_8_M2F
p:GPIO_9_M2F
p:SPI_1_CLK_M2F
p:SPI_1_DO_M2F
p:SPI_1_SS0_M2F
p:USB_ULPI_DATA[0] (bidir end point)
p:USB_ULPI_DATA[0] (bidir start point)
p:USB_ULPI_DATA[1] (bidir end point)
p:USB_ULPI_DATA[1] (bidir start point)
p:USB_ULPI_DATA[2] (bidir end point)
p:USB_ULPI_DATA[2] (bidir start point)
p:USB_ULPI_DATA[3] (bidir end point)
p:USB_ULPI_DATA[3] (bidir start point)
p:USB_ULPI_DATA[4] (bidir end point)
p:USB_ULPI_DATA[4] (bidir start point)
p:USB_ULPI_DATA[5] (bidir end point)
p:USB_ULPI_DATA[5] (bidir start point)
p:USB_ULPI_DATA[6] (bidir end point)
p:USB_ULPI_DATA[6] (bidir start point)
p:USB_ULPI_DATA[7] (bidir end point)
p:USB_ULPI_DATA[7] (bidir start point)
p:USB_ULPI_DIR
p:USB_ULPI_NXT
p:USB_ULPI_STP
p:USB_ULPI_XCLK (bidir end point)
p:USB_ULPI_XCLK (bidir start point)


Inapplicable constraints
************************

(none)


Applicable constraints with issues
**********************************

(none)


Constraints with matching wildcard expressions
**********************************************

(none)


Library Report
**************


# End of Constraint Checker Report
