Synopsys Generic Technology Mapper, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
Product Version I-2013.09M-SP1 

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 132MB)


Available hyper_sources - for debug and ip models
	None Found


Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 132MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 132MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 132MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 132MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 132MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 132MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 132MB)


Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 132MB)


Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 132MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
------------------------------------------------------------


Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 132MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 132MB)



#### START OF CLOCK OPTIMIZATION REPORT #####[

Clock optimization not enabled
1 non-gated/non-generated clock tree(s) driving 4 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

====================================== Non-Gated/Non-Generated Clocks ======================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                     
------------------------------------------------------------------------------------------------------------
@K:CKID0001       sys_clk_i           port                   4          op_mult.un3_product_o_muladd_0[35:0]
============================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]

Writing Analyst data base D:\MS_MC_single_axis\synthesis\mas.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 132MB)

Writing EDIF Netlist and constraint files
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
I-2013.09M-SP1 

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

@W: MT246 :"d:\ms_mc_single_axis\hdl\mas.vhd":158:11:158:12|Blackbox MACC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock mas|sys_clk_i with period 10.00ns. Please declare a user-defined clock on object "p:sys_clk_i"



##### START OF TIMING REPORT #####[
# Timing Report written on Thu Aug 07 15:16:58 2014
#


Top view:               mas
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: 8.972

                   Requested     Estimated     Requested     Estimated               Clock        Clock              
Starting Clock     Frequency     Frequency     Period        Period        Slack     Type         Group              
---------------------------------------------------------------------------------------------------------------------
mas|sys_clk_i      100.0 MHz     972.8 MHz     10.000        1.028         8.972     inferred     Inferred_clkgroup_0
System             100.0 MHz     NA            10.000        NA            NA        system       system_clkgroup    
=====================================================================================================================





Clock Relationships
*******************

Clocks                        |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
--------------------------------------------------------------------------------------------------------------------
Starting       Ending         |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
--------------------------------------------------------------------------------------------------------------------
mas|sys_clk_i  mas|sys_clk_i  |  10.000      8.972  |  No paths    -      |  No paths    -      |  No paths    -    
====================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: mas|sys_clk_i
====================================



Starting Points with Worst Slack
********************************

                     Starting                                                Arrival          
Instance             Reference         Type     Pin     Net                  Time        Slack
                     Clock                                                                    
----------------------------------------------------------------------------------------------
mas_done_sync[0]     mas|sys_clk_i     SLE      Q       mas_done_sync[0]     0.087       8.972
==============================================================================================


Ending Points with Worst Slack
******************************

               Starting                                                Required          
Instance       Reference         Type     Pin     Net                  Time         Slack
               Clock                                                                     
-----------------------------------------------------------------------------------------
mas_done_o     mas|sys_clk_i     SLE      D       mas_done_sync[0]     9.745        8.972
=========================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.255
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.745

    - Propagation time:                      0.773
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     8.972

    Number of logic level(s):                0
    Starting point:                          mas_done_sync[0] / Q
    Ending point:                            mas_done_o / D
    The start point is clocked by            mas|sys_clk_i [rising] on pin CLK
    The end   point is clocked by            mas|sys_clk_i [rising] on pin CLK

Instance / Net                Pin      Pin               Arrival     No. of    
Name                 Type     Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------
mas_done_sync[0]     SLE      Q        Out     0.087     0.087       -         
mas_done_sync[0]     Net      -        -       0.685     -           1         
mas_done_o           SLE      D        In      -         0.773       -         
===============================================================================
Total path delay (propagation time + setup) of 1.028 is 0.343(33.3%) logic and 0.685(66.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report for mas 

Mapping to part: m2s050t_esfbga896std
Cell usage:


Sequential Cells: 
SLE            2 uses

DSP Blocks:    1
 MACC:         1 MultAddSub

Total LUTs:    0

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 47MB peak: 133MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Aug 07 15:16:59 2014

###########################################################]
