Synopsys Generic Technology Pre-mapping, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
Product Version I-2013.09M-SP1 

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@L: D:\MS_MC_single_axis\synthesis\mas_scck.rpt 
Printing clock  summary report in "D:\MS_MC_single_axis\synthesis\mas_scck.rpt" file 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB)

@N: BN133 |Ignoring syn_hier=hard property on top-level design.

Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

syn_allowed_resources : blockrams=69,dsps=72  set on top level netlist mas


Clock Summary
**************

Start             Requested     Requested     Clock        Clock              
Clock             Frequency     Period        Type         Group              
------------------------------------------------------------------------------
mas|sys_clk_i     100.0 MHz     10.000        inferred     Inferred_clkgroup_0
==============================================================================

@W: MT530 :"d:\ms_mc_single_axis\hdl\mas.vhd":154:9:154:10|Found inferred clock mas|sys_clk_i which controls 46 sequential elements including product_o[43:0]. This clock has no specified timing constraint which may adversely impact design performance. 

Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file D:\MS_MC_single_axis\synthesis\mas.sap.
Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 132MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Aug 07 15:16:57 2014

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