@N|Running in 64-bit mode
@N: CD720 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":58:7:58:26|Top entity is set to MSMC_Fab_Toplevel_st.
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":58:7:58:26|Synthesizing work.msmc_fab_toplevel_st.msmc_fab_toplevel_st 
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":32:7:32:29|Synthesizing work.edge_detection_logic_st.edge_detection_logic_st 
@N: CL177 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\edge_detection_logic_st.vhd":227:3:227:4|Sharing sequential element iq_pi_start_o.
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\accumulator_st.vhd":31:7:31:20|Synthesizing work.accumulator_st.accumulator_st 
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\mas.vhd":32:7:32:9|Synthesizing work.mas.mas 
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\cpipic.vhd":39:7:39:12|Synthesizing work.cpipic.cpipic 
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\mas_scheduler.vhd":37:7:37:19|Synthesizing work.mas_scheduler.mas_scheduler 
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\inverse_clarke.vhd":30:7:30:20|Synthesizing work.inverse_clarke.inverse_clarke 
@N: CD231 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\inverse_clarke.vhd":80:35:80:36|Using onehot encoding for type iclarke_trnsf_states (idle="100000")
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\inverse_park.vhd":30:7:30:18|Synthesizing work.inverse_park.inverse_park 
@N: CD231 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\inverse_park.vhd":82:33:82:34|Using onehot encoding for type ipark_trnsf_states (idle="100000")
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\park.vhd":31:7:31:10|Synthesizing work.park.park 
@N: CD231 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\park.vhd":73:27:73:28|Using onehot encoding for type park_trnsf_states (idle="100000")
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":30:7:30:12|Synthesizing work.clarke.clarke 
@N: CD233 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\clarke.vhd":79:34:79:35|Using sequential encoding for type clarke_trnsf_states
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":31:7:31:22|Synthesizing work.adc_measurements.adc_measurements 
@N: CD231 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":117:26:117:27|Using onehot encoding for type adc_op_state (idle="1000000000")
@N: CL177 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\adc_measurements.vhd":406:6:406:7|Sharing sequential element s_r_sck_sync.
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\core3phasepwm_st.vhd":29:7:29:22|Synthesizing work.core3phasepwm_st.core3phasepwm_st 
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\apb3_if_st.vhd":36:7:36:16|Synthesizing work.apb3_if_st.apb3_if_st 
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\sine_cos.vhd":53:7:53:14|Synthesizing work.sine_cos.sine_cos 
@N: CD231 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\sine_cos.vhd":2193:25:2193:26|Using onehot encoding for type sine_cos_states (idle="10000")
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\svpwm.vhd":35:7:35:11|Synthesizing work.svpwm.svpwm 
@N: CD231 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\svpwm.vhd":92:19:92:20|Using onehot encoding for type min_max_fsm (idle="10000000")
@N: CD231 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\svpwm.vhd":93:21:93:22|Using onehot encoding for type third_har_fsm (idle="100000000")
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\speed_id_iq_pi.vhd":31:7:31:20|Synthesizing work.speed_id_iq_pi.speed_id_iq_pi 
@N: CD630 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\pwm_count.vhd":32:7:32:15|Synthesizing work.pwm_count.pwm_count 

