Project Status Summary Page

Project Settings
Project Name | MC_System_top_syn | Implementation Name | synthesis
Top Module | work.MC_System_top | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 10000
Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0

Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 118 | 71 | 0 | - | 00m:04s | - | 29-11-2017 12:03:26
(premap) | Complete | 96 | 17 | 0 | 0m:02s | 0m:02s | 169MB | 29-11-2017 12:03:30
(fpga_mapper) | Complete | 16 | 26 | 0 | 0m:16s | 0m:17s | 246MB | 29-11-2017 12:03:48
Multi-srs Generator | Complete |  |  |  |  |  |  | 29-11-2017 12:03:28

Area Summary
Carry Cells | 1530 | Sequential Cells | 2543
DSP Blocks (MACC) (dsp_used) | 8 | I/O Cells | 26
Global Clock Buffers | 2 | LUTs (total_luts) | 3484

Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
GL0 | 100.0 MHz | 109.4 MHz | 0.860
System | 100.0 MHz | 1029.4 MHz | 9.029

Optimizations Summary
Combined Clock Conversion | 1 / 0 |  |