--=================================================================================================
-- File Name                           : svm.vhd

-- Description                         : This module implements Space vector modulation.

-- Targeted device                     : Microsemi-SoC
-- Author                              : India Solutions Team
--
-- SVN Revision Information            :
-- SVN $Revision                       :
-- SVN $Date                           :
--
-- COPYRIGHT 2016 BY MICROSEMI
-- THE INFORMATION CONTAINED IN THIS DOCUMENT IS SUBJECT TO LICENSING RESTRICTIONS FROM MICROSEMI
-- CORP. IF YOU ARE NOT IN POSSESSION OF WRITTEN AUTHORIZATION FROM MICROSEMI FOR USE OF THIS
-- FILE, THEN THE FILE SHOULD BE IMMEDIATELY DESTROYED AND NO BACK-UP OF THE FILE SHOULD BE MADE.
--
--=================================================================================================

--=================================================================================================
-- Libraries
--=================================================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

--=================================================================================================
-- svm entity declaration
--=================================================================================================
ENTITY SVM is
PORT (
-- Port list
    -- System reset
    reset_i                            : IN  STD_LOGIC;

    -- System clock
    sys_clk_i                          : IN  STD_LOGIC;    
    
    -- Control input specifies the start of SVM operation
    start_i                            : IN  STD_LOGIC;
    
    -- Data input specifies the input A-phase voltage
    va_i             		           : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);
    
    -- Data input specifies the input B-phase voltage
    vb_i                               : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);
    
    -- Data input specifies the input C-phase voltage
    vc_i                               : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);
    
    -- Data output specifies the output A-phase voltage with third harmonic component
    va3h_o                             : OUT STD_LOGIC_VECTOR(17  DOWNTO 0);
    
    -- Data output specifies the output B-phase voltage with third harmonic component
    vb3h_o                             : OUT STD_LOGIC_VECTOR(17  DOWNTO 0);
    
    -- Data output specifies the output C-phase voltage with third harmonic component
    vc3h_o                             : OUT STD_LOGIC_VECTOR(17  DOWNTO 0);
    
    -- Control output specifies the completion of SVM operation
    done_o                             : OUT STD_LOGIC
    );
END svm;
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