`

    #Build: Synplify Pro I-2014.03M-SP1, Build 097R, Oct  9 2014
    #install: C:\Microsemi\Libero_v11.5\Synopsys\synplify_I201403MSP1
    #OS: Windows 7 6.1
    #Hostname: W764-BATTUP

    #Implementation: synthesis

    Synopsys VHDL Compiler, version comp201403sp1p1, Build 095R, built Oct  9 2014
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

    @N:CD720 : std.vhd(146) | Setting time resolution to ns
    @N: : MC_System.vhd(17) | Top entity is set to MC_System.
    VHDL syntax check successful!
    @N:CD231 : std1164.vhd(913) | Using onehot encoding for type mvl9plus ('U'="1000000000")
    @N:CD630 : MC_System.vhd(17) | Synthesizing work.mc_system.rtl
    @N:CD630 : MC_System_sb.vhd(20) | Synthesizing work.mc_system_sb.rtl
    @N:CD630 : smartfusion2.vhd(779) | Synthesizing smartfusion2.sysreset.syn_black_box
    Post processing for smartfusion2.sysreset.syn_black_box
    @N:CD630 : MC_System_sb_MSS.vhd(17) | Synthesizing work.mc_system_sb_mss.rtl
    @N:CD630 : smartfusion2.vhd(434) | Synthesizing smartfusion2.bibuf.syn_black_box
    Post processing for smartfusion2.bibuf.syn_black_box
    @N:CD630 : smartfusion2.vhd(403) | Synthesizing smartfusion2.inbuf.syn_black_box
    Post processing for smartfusion2.inbuf.syn_black_box
    @N:CD630 : smartfusion2.vhd(423) | Synthesizing smartfusion2.tribuff.syn_black_box
    Post processing for smartfusion2.tribuff.syn_black_box
    @N:CD630 : MC_System_sb_MSS_syn.vhd(10) | Synthesizing work.mss_010.def_arch
    Post processing for work.mss_010.def_arch
    Post processing for work.mc_system_sb_mss.rtl
    @N:CD630 : MC_System_sb_FABOSC_0_OSC.vhd(8) | Synthesizing work.mc_system_sb_fabosc_0_osc.def_arch
    @N:CD630 : smartfusion2.vhd(562) | Synthesizing smartfusion2.clkint.syn_black_box
    Post processing for smartfusion2.clkint.syn_black_box
    @N:CD630 : osc_comps.vhd(19) | Synthesizing work.rcosc_25_50mhz.def_arch
    Post processing for work.rcosc_25_50mhz.def_arch
    @N:CD630 : osc_comps.vhd(79) | Synthesizing work.rcosc_25_50mhz_fab.def_arch
    Post processing for work.rcosc_25_50mhz_fab.def_arch
    Post processing for work.mc_system_sb_fabosc_0_osc.def_arch
    @W:CL240 : MC_System_sb_FABOSC_0_OSC.vhd(16) | XTLOSC_O2F is not assigned a value (floating) -- simulation mismatch possible.
    @W:CL240 : MC_System_sb_FABOSC_0_OSC.vhd(15) | XTLOSC_CCC is not assigned a value (floating) -- simulation mismatch possible.
    @W:CL240 : MC_System_sb_FABOSC_0_OSC.vhd(14) | RCOSC_1MHZ_O2F is not assigned a value (floating) -- simulation mismatch possible.
    @W:CL240 : MC_System_sb_FABOSC_0_OSC.vhd(13) | RCOSC_1MHZ_CCC is not assigned a value (floating) -- simulation mismatch possible.
    @N:CD630 : coreresetp.vhd(27) | Synthesizing work.coreresetp.rtl
    @W:CD434 : coreresetp.vhd(477) | Signal soft_ext_reset_out in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(478) | Signal soft_reset_f2m in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(479) | Signal soft_m3_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(480) | Signal soft_mddr_ddr_axi_s_core_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(481) | Signal soft_fddr_core_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(482) | Signal soft_sdif0_phy_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(483) | Signal soft_sdif0_core_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(484) | Signal soft_sdif1_phy_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(485) | Signal soft_sdif1_core_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(486) | Signal soft_sdif2_phy_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(487) | Signal soft_sdif2_core_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(488) | Signal soft_sdif3_phy_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(489) | Signal soft_sdif3_core_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(490) | Signal soft_sdif0_0_core_reset in the sensitivity list is not used in the process
    @W:CD434 : coreresetp.vhd(491) | Signal soft_sdif0_1_core_reset in the sensitivity list is not used in the process
    Post processing for work.coreresetp.rtl
    @W:CL169 : coreresetp.vhd(1519) | Pruning register count_ddr_2(13 downto 0)
    @W:CL169 : coreresetp.vhd(1495) | Pruning register count_sdif3_2(12 downto 0)
    @W:CL169 : coreresetp.vhd(1471) | Pruning register count_sdif2_2(12 downto 0)
    @W:CL169 : coreresetp.vhd(1447) | Pruning register count_sdif1_2(12 downto 0)
    @W:CL169 : coreresetp.vhd(1423) | Pruning register count_sdif0_2(12 downto 0)
    @W:CL169 : coreresetp.vhd(1395) | Pruning register count_ddr_enable_rcosc_2
    @W:CL169 : coreresetp.vhd(1395) | Pruning register count_ddr_enable_q1_2
    @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif3_enable_rcosc_2
    @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif2_enable_rcosc_2
    @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif1_enable_rcosc_2
    @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif0_enable_rcosc_2
    @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif3_enable_q1_2
    @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif2_enable_q1_2
    @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif1_enable_q1_2
    @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif0_enable_q1_2
    @W:CL169 : coreresetp.vhd(1311) | Pruning register count_sdif3_enable_3
    @W:CL169 : coreresetp.vhd(1252) | Pruning register count_sdif2_enable_3
    @W:CL169 : coreresetp.vhd(1193) | Pruning register count_sdif1_enable_3
    @W:CL169 : coreresetp.vhd(1134) | Pruning register count_sdif0_enable_3
    @W:CL169 : coreresetp.vhd(1059) | Pruning register count_ddr_enable_3
    @N:CL177 : coreresetp.vhd(1331) | Sharing sequential element M3_RESET_N_int.
    @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif2_spll_lock_q1.
    @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif1_spll_lock_q1.
    @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif0_spll_lock_q1.
    @N:CL177 : coreresetp.vhd(936) | Sharing sequential element fpll_lock_q1.
    @W:CL190 : coreresetp.vhd(1376) | Optimizing register bit EXT_RESET_OUT_int to a constant 0
    @W:CL169 : coreresetp.vhd(1059) | Pruning register release_ext_reset
    @W:CL169 : coreresetp.vhd(1376) | Pruning register EXT_RESET_OUT_int
    @W:CL169 : coreresetp.vhd(1376) | Pruning register sm2_state(2 downto 0)
    @W:CL169 : coreresetp.vhd(792) | Pruning register sm2_areset_n_q1
    @W:CL169 : coreresetp.vhd(792) | Pruning register sm2_areset_n_clk_base
    @N:CD630 : coreapb3.vhd(34) | Synthesizing coreapb3_lib.coreapb3.coreapb3_arch
    @W:CD604 : coreapb3.vhd(650) | OTHERS clause is not synthesized
    @W:CD434 : coreapb3.vhd(1438) | Signal infill in the sensitivity list is not used in the process
    @W:CD638 : coreapb3.vhd(601) | Signal ia_prdata is undriven
    @N:CD630 : coreapb3_muxptob3.vhd(33) | Synthesizing coreapb3_lib.coreapb3_muxptob3.coreapb3_muxptob3_arch
    Post processing for coreapb3_lib.coreapb3_muxptob3.coreapb3_muxptob3_arch
    Post processing for coreapb3_lib.coreapb3.coreapb3_arch
    @N:CD630 : MC_System_sb_CCC_0_FCCC.vhd(8) | Synthesizing work.mc_system_sb_ccc_0_fccc.def_arch
    @N:CD630 : smartfusion2.vhd(787) | Synthesizing smartfusion2.ccc.syn_black_box
    Post processing for smartfusion2.ccc.syn_black_box
    @N:CD630 : smartfusion2.vhd(569) | Synthesizing smartfusion2.gnd.syn_black_box
    Post processing for smartfusion2.gnd.syn_black_box
    @N:CD630 : smartfusion2.vhd(575) | Synthesizing smartfusion2.vcc.syn_black_box
    Post processing for smartfusion2.vcc.syn_black_box
    Post processing for work.mc_system_sb_ccc_0_fccc.def_arch
    Post processing for work.mc_system_sb.rtl
    Post processing for work.mc_system.rtl
    @W:CL159 : coreapb3.vhd(74) | Input IADDR is unused
    @W:CL159 : coreapb3.vhd(75) | Input PRESETN is unused
    @W:CL159 : coreapb3.vhd(76) | Input PCLK is unused
    @W:CL159 : coreapb3.vhd(108) | Input PRDATAS2 is unused
    @W:CL159 : coreapb3.vhd(109) | Input PRDATAS3 is unused
    @W:CL159 : coreapb3.vhd(110) | Input PRDATAS4 is unused
    @W:CL159 : coreapb3.vhd(111) | Input PRDATAS5 is unused
    @W:CL159 : coreapb3.vhd(112) | Input PRDATAS6 is unused
    @W:CL159 : coreapb3.vhd(113) | Input PRDATAS7 is unused
    @W:CL159 : coreapb3.vhd(114) | Input PRDATAS8 is unused
    @W:CL159 : coreapb3.vhd(115) | Input PRDATAS9 is unused
    @W:CL159 : coreapb3.vhd(116) | Input PRDATAS10 is unused
    @W:CL159 : coreapb3.vhd(117) | Input PRDATAS11 is unused
    @W:CL159 : coreapb3.vhd(118) | Input PRDATAS12 is unused
    @W:CL159 : coreapb3.vhd(119) | Input PRDATAS13 is unused
    @W:CL159 : coreapb3.vhd(120) | Input PRDATAS14 is unused
    @W:CL159 : coreapb3.vhd(121) | Input PRDATAS15 is unused
    @W:CL159 : coreapb3.vhd(125) | Input PREADYS2 is unused
    @W:CL159 : coreapb3.vhd(126) | Input PREADYS3 is unused
    @W:CL159 : coreapb3.vhd(127) | Input PREADYS4 is unused
    @W:CL159 : coreapb3.vhd(128) | Input PREADYS5 is unused
    @W:CL159 : coreapb3.vhd(129) | Input PREADYS6 is unused
    @W:CL159 : coreapb3.vhd(130) | Input PREADYS7 is unused
    @W:CL159 : coreapb3.vhd(131) | Input PREADYS8 is unused
    @W:CL159 : coreapb3.vhd(132) | Input PREADYS9 is unused
    @W:CL159 : coreapb3.vhd(133) | Input PREADYS10 is unused
    @W:CL159 : coreapb3.vhd(134) | Input PREADYS11 is unused
    @W:CL159 : coreapb3.vhd(135) | Input PREADYS12 is unused
    @W:CL159 : coreapb3.vhd(136) | Input PREADYS13 is unused
    @W:CL159 : coreapb3.vhd(137) | Input PREADYS14 is unused
    @W:CL159 : coreapb3.vhd(138) | Input PREADYS15 is unused
    @W:CL159 : coreapb3.vhd(142) | Input PSLVERRS2 is unused
    @W:CL159 : coreapb3.vhd(143) | Input PSLVERRS3 is unused
    @W:CL159 : coreapb3.vhd(144) | Input PSLVERRS4 is unused
    @W:CL159 : coreapb3.vhd(145) | Input PSLVERRS5 is unused
    @W:CL159 : coreapb3.vhd(146) | Input PSLVERRS6 is unused
    @W:CL159 : coreapb3.vhd(147) | Input PSLVERRS7 is unused
    @W:CL159 : coreapb3.vhd(148) | Input PSLVERRS8 is unused
    @W:CL159 : coreapb3.vhd(149) | Input PSLVERRS9 is unused
    @W:CL159 : coreapb3.vhd(150) | Input PSLVERRS10 is unused
    @W:CL159 : coreapb3.vhd(151) | Input PSLVERRS11 is unused
    @W:CL159 : coreapb3.vhd(152) | Input PSLVERRS12 is unused
    @W:CL159 : coreapb3.vhd(153) | Input PSLVERRS13 is unused
    @W:CL159 : coreapb3.vhd(154) | Input PSLVERRS14 is unused
    @W:CL159 : coreapb3.vhd(155) | Input PSLVERRS15 is unused
    @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif0_spll_lock_q2.
    @N:CL177 : coreresetp.vhd(936) | Sharing sequential element fpll_lock_q2.
    @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif1_spll_lock_q2.
    @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif2_spll_lock_q2.
    @N:CL201 : coreresetp.vhd(1311) | Trying to extract state machine for register sdif3_state
    Extracted state machine for register sdif3_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.vhd(1252) | Trying to extract state machine for register sdif2_state
    Extracted state machine for register sdif2_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.vhd(1193) | Trying to extract state machine for register sdif1_state
    Extracted state machine for register sdif1_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.vhd(1134) | Trying to extract state machine for register sdif0_state
    Extracted state machine for register sdif0_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.vhd(1059) | Trying to extract state machine for register sm0_state
    Extracted state machine for register sm0_state
    State machine has 7 reachable states with original encodings of:
       000
       001
       010
       011
       100
       101
       110
    @W:CL159 : coreresetp.vhd(96) | Input CLK_LTSSM is unused
    @W:CL159 : coreresetp.vhd(123) | Input FPLL_LOCK is unused
    @W:CL159 : coreresetp.vhd(126) | Input SDIF0_SPLL_LOCK is unused
    @W:CL159 : coreresetp.vhd(135) | Input SDIF1_SPLL_LOCK is unused
    @W:CL159 : coreresetp.vhd(139) | Input SDIF2_SPLL_LOCK is unused
    @W:CL159 : coreresetp.vhd(143) | Input SDIF3_SPLL_LOCK is unused
    @W:CL159 : coreresetp.vhd(157) | Input SDIF0_PSEL is unused
    @W:CL159 : coreresetp.vhd(158) | Input SDIF0_PWRITE is unused
    @W:CL159 : coreresetp.vhd(159) | Input SDIF0_PRDATA is unused
    @W:CL159 : coreresetp.vhd(160) | Input SDIF1_PSEL is unused
    @W:CL159 : coreresetp.vhd(161) | Input SDIF1_PWRITE is unused
    @W:CL159 : coreresetp.vhd(162) | Input SDIF1_PRDATA is unused
    @W:CL159 : coreresetp.vhd(163) | Input SDIF2_PSEL is unused
    @W:CL159 : coreresetp.vhd(164) | Input SDIF2_PWRITE is unused
    @W:CL159 : coreresetp.vhd(165) | Input SDIF2_PRDATA is unused
    @W:CL159 : coreresetp.vhd(166) | Input SDIF3_PSEL is unused
    @W:CL159 : coreresetp.vhd(167) | Input SDIF3_PWRITE is unused
    @W:CL159 : coreresetp.vhd(168) | Input SDIF3_PRDATA is unused
    @W:CL159 : coreresetp.vhd(174) | Input SOFT_EXT_RESET_OUT is unused
    @W:CL159 : coreresetp.vhd(175) | Input SOFT_RESET_F2M is unused
    @W:CL159 : coreresetp.vhd(176) | Input SOFT_M3_RESET is unused
    @W:CL159 : coreresetp.vhd(177) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused
    @W:CL159 : coreresetp.vhd(178) | Input SOFT_FDDR_CORE_RESET is unused
    @W:CL159 : coreresetp.vhd(179) | Input SOFT_SDIF0_PHY_RESET is unused
    @W:CL159 : coreresetp.vhd(180) | Input SOFT_SDIF0_CORE_RESET is unused
    @W:CL159 : coreresetp.vhd(181) | Input SOFT_SDIF1_PHY_RESET is unused
    @W:CL159 : coreresetp.vhd(182) | Input SOFT_SDIF1_CORE_RESET is unused
    @W:CL159 : coreresetp.vhd(183) | Input SOFT_SDIF2_PHY_RESET is unused
    @W:CL159 : coreresetp.vhd(184) | Input SOFT_SDIF2_CORE_RESET is unused
    @W:CL159 : coreresetp.vhd(185) | Input SOFT_SDIF3_PHY_RESET is unused
    @W:CL159 : coreresetp.vhd(186) | Input SOFT_SDIF3_CORE_RESET is unused
    @W:CL159 : coreresetp.vhd(190) | Input SOFT_SDIF0_0_CORE_RESET is unused
    @W:CL159 : coreresetp.vhd(191) | Input SOFT_SDIF0_1_CORE_RESET is unused
    @W:CL159 : MC_System_sb_FABOSC_0_OSC.vhd(10) | Input XTL is unused
    @END

    At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 88MB peak: 90MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Tue Mar 10 11:25:04 2015

    ###########################################################]
    Synopsys Netlist Linker, version comp201403sp1p1, Build 095R, built Oct  9 2014
    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Tue Mar 10 11:25:05 2015

    ###########################################################]
    Pre-mapping Report

    Synopsys Generic Technology Pre-mapping, Version mapact, Build 1350R, Built Oct 16 2014 10:02:37
    Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
    Product Version I-2014.03M-SP1

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Linked File: SVN
    Printing clock  summary report in "D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\synthesis\MC_System_scck.rpt" file
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 107MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 107MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 107MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 108MB)

    @W:BN132 : coreresetp.vhd(1059) | Removing sequential instance MC_System_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int,  because it is equivalent to instance MC_System_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance SDIF_RELEASED_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1134) | Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1134) | Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1193) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1193) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1252) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1252) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1311) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1311) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance INIT_DONE_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1134) | Removing sequential instance sdif0_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1193) | Removing sequential instance sdif1_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1252) | Removing sequential instance sdif2_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1311) | Removing sequential instance sdif3_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance sm0_state[0:6] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(922) | Removing sequential instance CONFIG2_DONE_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(803) | Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(814) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(836) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(936) | Removing sequential instance sdif3_spll_lock_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(908) | Removing sequential instance CONFIG1_DONE_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif3_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif2_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif1_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(922) | Removing sequential instance CONFIG2_DONE_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(803) | Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(814) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(836) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(936) | Removing sequential instance sdif3_spll_lock_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(908) | Removing sequential instance CONFIG1_DONE_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif0_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance ddr_settled_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif3_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif2_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif1_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance release_sdif0_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1544) | Removing sequential instance ddr_settled_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1495) | Removing sequential instance release_sdif3_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1471) | Removing sequential instance release_sdif2_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1447) | Removing sequential instance release_sdif1_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1423) | Removing sequential instance release_sdif0_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(1519) | Removing sequential instance ddr_settled of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(770) | Removing sequential instance sm0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(894) | Removing sequential instance sdif3_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(883) | Removing sequential instance sdif2_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(872) | Removing sequential instance sdif1_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(861) | Removing sequential instance sdif0_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(770) | Removing sequential instance sm0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(850) | Removing sequential instance sm0_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(894) | Removing sequential instance sdif3_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(883) | Removing sequential instance sdif2_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(872) | Removing sequential instance sdif1_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(861) | Removing sequential instance sdif0_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(850) | Removing sequential instance sm0_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(751) | Removing sequential instance SDIF3_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(735) | Removing sequential instance SDIF2_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(719) | Removing sequential instance SDIF1_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(703) | Removing sequential instance SDIF0_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(608) | Removing sequential instance MSS_HPMS_READY_int of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN114 : mc_system_sb_fabosc_0_osc.vhd(49) | Removing instance I_RCOSC_25_50MHZ_FAB of black_box view:work.RCOSC_25_50MHZ_FAB(def_arch) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(593) | Removing sequential instance mss_ready_select of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(751) | Removing sequential instance SDIF3_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(735) | Removing sequential instance SDIF2_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(719) | Removing sequential instance SDIF1_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(703) | Removing sequential instance SDIF0_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(751) | Removing sequential instance SDIF3_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(735) | Removing sequential instance SDIF2_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(719) | Removing sequential instance SDIF1_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(703) | Removing sequential instance SDIF0_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(593) | Removing sequential instance mss_ready_state of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(577) | Removing sequential instance FIC_2_APB_M_PRESET_N_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(751) | Removing sequential instance SDIF3_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(735) | Removing sequential instance SDIF2_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(719) | Removing sequential instance SDIF1_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(703) | Removing sequential instance SDIF0_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(565) | Removing sequential instance RESET_N_M2F_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(577) | Removing sequential instance FIC_2_APB_M_PRESET_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(565) | Removing sequential instance RESET_N_M2F_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(553) | Removing sequential instance POWER_ON_RESET_N_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    @N:BN362 : coreresetp.vhd(553) | Removing sequential instance POWER_ON_RESET_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs
    syn_allowed_resources : blockrams=21  set on top level netlist MC_System

    @S |Clock Summary
    ****************

    Start                                              Requested     Requested     Clock        Clock
    Clock                                              Frequency     Period        Type         Group
    ---------------------------------------------------------------------------------------------------------------
    MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_0
    System                                             1.0 MHz       1000.000      system       system_clkgroup
    ===============================================================================================================

    @W:MT530 : coreresetp.vhd(781) | Found inferred clock MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock which controls 3 sequential elements including MC_System_sb_0.CORERESETP_0.sm1_areset_n_clk_base. This clock has no specified timing constraint which may adversely impact design performance.

    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\synthesis\MC_System.sap.
    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 136MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Tue Mar 10 11:25:06 2015

    ###########################################################]
    Map & Optimize Report

    Synopsys Generic Technology Mapper, Version mapact, Build 1350R, Built Oct 16 2014 10:02:37
    Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
    Product Version I-2014.03M-SP1

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 135MB)

    @N:BN114 : mc_system_sb.vhd(687) | Removing instance SYSRESET_POR of black_box view:smartfusion2.SYSRESET(syn_black_box) because there are no references to its outputs

    Available hyper_sources - for debug and ip models
    	None Found

    @W:MO129 : coreresetp.vhd(781) | Sequential instance MC_System_sb_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation
    @N:FA239 : coreapb3.vhd(633) | ROM CoreAPB3_0.iPSELS_raw_5[1:0] mapped in logic.
    @N:FA239 : coreapb3.vhd(633) | ROM CoreAPB3_0.iPSELS_raw_5[1:0] mapped in logic.
    @N:MO106 : coreapb3.vhd(633) | Found ROM, 'CoreAPB3_0.iPSELS_raw_5[1:0]', 16 words by 2 bits
    @W:MO129 : coreresetp.vhd(781) | Sequential instance MC_System_sb_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation
    @W:MO129 : coreresetp.vhd(1331) | Sequential instance MC_System_sb_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB)

    Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

    Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

    Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    ------------------------------------------------------------

    Added 0 Buffers
    Added 0 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 0 Combinational Cells via replication

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

    Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

    #### START OF CLOCK OPTIMIZATION REPORT #####[

    Clock optimization not enabled
    1 non-gated/non-generated clock tree(s) driving 1 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =================================================== Non-Gated/Non-Generated Clocks ===================================================
    Clock Tree ID     Driving Element                   Drive Element Type     Fanout     Sample Instance
    --------------------------------------------------------------------------------------------------------------------------------------
    ClockId0001        MC_System_sb_0.CCC_0.GL0_INST     CLKINT                 1          MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST
    ======================================================================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######]

    Writing Analyst data base D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\synthesis\MC_System.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 135MB)

    Writing Analyst data base D:\SVN Solutions\Motor Control\Development\MCSK\SK2ABLSTSL10_4_1\synthesis\synwork\MC_System_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 135MB)

    Writing EDIF Netlist and constraint files
    @N:BW103 :  | Synopsys Constraint File time units using default value of 1ns
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF
    I-2014.03M-SP1

    Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 135MB)

    @W:MT246 : mc_system_sb_ccc_0_fccc.vhd(110) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT420 :  | Found inferred clock MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:MC_System_sb_0.CCC_0.GL0_net"

    @S |##### START OF TIMING REPORT #####[
    # Timing Report written on Tue Mar 10 11:25:07 2015
    #

    Top view:               MC_System
    Requested Frequency:    100.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing.

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.

    Performance Summary
    *******************

    Worst slack in design: 2.048

                                                       Requested     Estimated      Requested     Estimated               Clock        Clock
    Starting Clock                                     Frequency     Frequency      Period        Period        Slack     Type         Group
    ------------------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     125.7 MHz      10.000        7.952         2.048     inferred     Inferred_clkgroup_0
    System                                             100.0 MHz     1029.4 MHz     10.000        0.971         9.029     system       system_clkgroup
    ======================================================================================================================================================

    Clock Relationships
    *******************

    Clocks                                                                                          |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                                        Ending                                          |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    System                                          System                                          |  10.000      9.029  |  No paths    -      |  No paths    -      |  No paths    -
    MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock  |  10.000      2.048  |  No paths    -      |  No paths    -      |  No paths    -
    ======================================================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                         Starting                                                                                                                            Arrival
    Instance                                             Reference                                          Type        Pin                Net                                               Time        Slack
                                                         Clock
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[13]     AMBA_SLAVE_1_PADDRS_c[13]                         3.101       2.048
    MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[14]     AMBA_SLAVE_1_PADDRS_c[14]                         3.105       2.258
    MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[15]     AMBA_SLAVE_1_PADDRS_c[15]                         3.044       2.428
    MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_SEL          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx     2.965       2.460
    MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[12]     AMBA_SLAVE_1_PADDRS_c[12]                         3.126       3.136
    ==========================================================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                         Starting                                                                                                                                  Required
    Instance                                             Reference                                          Type        Pin                 Net                                                    Time         Slack
                                                         Clock
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_READY         N_39_i_0                                               8.643        2.048
    MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RESP          MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSLVERR        9.147        2.569
    MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[3]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]      9.483        2.905
    MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[4]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]      9.539        2.961
    MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[9]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[9]      9.594        3.016
    MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[23]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[23]     9.604        3.026
    MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[0]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[0]      9.617        3.039
    MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[29]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[29]     9.625        3.047
    MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[30]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[30]     9.629        3.051
    MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_RDATA[13]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[13]     9.640        3.062
    =================================================================================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            1.357
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         8.643

        - Propagation time:                      6.595
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     2.048

        Number of logic level(s):                2
        Starting point:                          MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[13]
        Ending point:                            MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_READY
        The start point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
        The end   point is clocked by            MC_System_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

    Instance / Net                                                   Pin                Pin               Arrival     No. of
    Name                                                 Type        Name               Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------------------------
    MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MSS_010     F_HM0_ADDR[13]     Out     3.101     3.101       -
    AMBA_SLAVE_1_PADDRS_c[13]                            Net         -                  -       0.980     -           3
    MC_System_sb_0.CoreAPB3_0.iPSELS_raw_0_a2_0[0]       CFG4        D                  In      -         4.080       -
    MC_System_sb_0.CoreAPB3_0.iPSELS_raw_0_a2_0[0]       CFG4        Y                  Out     0.411     4.491       -
    N_113                                                Net         -                  -       0.933     -           36
    MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.N_39_i       CFG4        C                  In      -         5.424       -
    MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.N_39_i       CFG4        Y                  Out     0.200     5.624       -
    N_39_i_0                                             Net         -                  -       0.971     -           1
    MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     MSS_010     F_HM0_READY        In      -         6.595       -
    ============================================================================================================================
    Total path delay (propagation time + setup) of 7.952 is 5.069(63.7%) logic and 2.884(36.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                 Starting                                                                                           Arrival
    Instance                                     Reference     Type               Pin        Net                                                    Time        Slack
                                                 Clock
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_sb_0.FABOSC_0.I_RCOSC_25_50MHZ     System        RCOSC_25_50MHZ     CLKOUT     FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     0.000       9.029
    =================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                      Starting                                                                                         Required
    Instance                          Reference     Type     Pin                Net                                                    Time         Slack
                                      Clock
    -----------------------------------------------------------------------------------------------------------------------------------------------------
    MC_System_sb_0.CCC_0.CCC_INST     System        CCC      RCOSC_25_50MHZ     FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     10.000       9.029
    =====================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         10.000

        - Propagation time:                      0.971
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 9.029

        Number of logic level(s):                0
        Starting point:                          MC_System_sb_0.FABOSC_0.I_RCOSC_25_50MHZ / CLKOUT
        Ending point:                            MC_System_sb_0.CCC_0.CCC_INST / RCOSC_25_50MHZ
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                                                            Pin                Pin               Arrival     No. of
    Name                                                   Type               Name               Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------------------------
    MC_System_sb_0.FABOSC_0.I_RCOSC_25_50MHZ               RCOSC_25_50MHZ     CLKOUT             Out     0.000     0.000       -
    FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     Net                -                  -       0.971     -           1
    MC_System_sb_0.CCC_0.CCC_INST                          CCC                RCOSC_25_50MHZ     In      -         0.971       -
    =====================================================================================================================================
    Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    ---------------------------------------
    Resource Usage Report for MC_System

    Mapping to part: m2s010fbga484-1
    Cell usage:
    CCC             1 use
    CLKINT          2 uses
    MSS_010         1 use
    RCOSC_25_50MHZ  1 use
    CFG2           2 uses
    CFG4           35 uses

    Sequential Cells:
    SLE            0 uses

    DSP Blocks:    0

    I/O ports: 220
    I/O primitives: 219
    BIBUF          8 uses
    INBUF          71 uses
    OUTBUF         139 uses
    TRIBUFF        1 use

    Global Clock Buffers: 2

    Total LUTs:    37

    Extra resources required for RAM and MACC interface logic during P&R:

    RAM64x18 Interface Logic : SLEs = 0; LUTs = 0;
    RAM1K18  Interface Logic : SLEs = 0; LUTs = 0;
    MACC     Interface Logic : SLEs = 0; LUTs = 0;

    Total number of SLEs after P&R:  0 + 0 + 0 + 0 = 0;
    Total number of LUTs after P&R:  37 + 0 + 0 + 0 = 37;

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 50MB peak: 135MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Tue Mar 10 11:25:08 2015

    ###########################################################]

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