Synopsys Generic Technology Pre-mapping, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
Product Version I-2013.09M-SP1 

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

Reading constraint file: C:\SK1ASTSL10_3_0_multi_axis\synthesis\MC_System_top_sdc.sdc
@L: C:\SK1ASTSL10_3_0_multi_axis\synthesis\MC_System_top_scck.rpt 
Printing clock  summary report in "C:\SK1ASTSL10_3_0_multi_axis\synthesis\MC_System_top_scck.rpt" file 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

syn_allowed_resources : blockrams=21  set on top level netlist SQMNG


Clock Summary
**************

Start                                                Requested     Requested     Clock        Clock              
Clock                                                Frequency     Period        Type         Group              
-----------------------------------------------------------------------------------------------------------------
MC_System_0/CCC_0/CCC_INST/INST_CCC_IP:GL0           50.0 MHz      20.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock          100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1        100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_0      100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_1      100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_2      100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_3      100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_4      100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_5      100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_6      100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_7      100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_8      100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_9      100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_10     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_11     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_12     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_13     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_14     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_15     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_16     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_17     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_18     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_19     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_20     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_21     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_22     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_23     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_24     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_25     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_26     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_27     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_28     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_29     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_30     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_31     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_32     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_33     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_34     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_35     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_36     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_37     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_38     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_39     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_40     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_41     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_42     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_43     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_44     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_45     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_46     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_47     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_48     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_49     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_50     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_51     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_52     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_53     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_54     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_55     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_56     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_57     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_58     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_59     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_60     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_61     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_62     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL0_net_inferred_clock_1_63     100.0 MHz     10.000        declared     group_55_166       
MC_System_CCC_0_FCCC|GL1_net_inferred_clock          100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1        100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_0      100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_1      100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_2      100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_3      100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_4      100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_5      100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_6      100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_7      100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_8      100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_9      100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_10     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_11     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_12     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_13     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_14     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_15     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_16     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_17     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_18     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_19     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_20     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_21     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_22     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_23     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_24     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_25     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_26     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_27     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_28     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_29     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_30     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_31     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_32     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_33     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_34     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_35     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_36     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_37     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_38     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_39     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_40     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_41     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_42     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_43     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_44     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_45     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_46     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_47     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_48     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_49     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_50     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_51     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_52     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_53     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_54     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_55     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_56     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_57     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_58     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_59     100.0 MHz     10.000        virtual      default_clkgroup   
MC_System_CCC_0_FCCC|GL1_net_inferred_clock_1_60     100.0 MHz     10.000        declared     group_55_165       
SQMNG|sys_clk_i                                      100.0 MHz     10.000        inferred     Inferred_clkgroup_0
=================================================================================================================

@W: MT530 :"c:\sk1astsl10_3_0_multi_axis\hdl\sqmng.vhd":489:2:489:3|Found inferred clock SQMNG|sys_clk_i which controls 140 sequential elements including init_theta_s. This clock has no specified timing constraint which may adversely impact design performance. 

Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file C:\SK1ASTSL10_3_0_multi_axis\synthesis\MC_System_top.sap.
Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 133MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Oct 08 11:16:16 2014

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