----------------------------------------------------------------------
-- Created by SmartDesign Tue Nov 14 14:10:41 2017
-- Version: v11.8 SP2 11.8.2.4
----------------------------------------------------------------------

----------------------------------------------------------------------
-- Libraries
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

library smartfusion2;
use smartfusion2.all;
----------------------------------------------------------------------
-- MC_System_top entity declaration
----------------------------------------------------------------------
entity MC_System_top is
    -- Port list
    port(
        -- Inputs
        A0_ADC_SDI_I   : in    std_logic;
        DEVRST_N       : in    std_logic;
        QA_I           : in    std_logic;
        QB_I           : in    std_logic;
        USB_ULPI_DIR   : in    std_logic;
        USB_ULPI_NXT   : in    std_logic;
        USB_ULPI_XCLK  : in    std_logic;
        -- Outputs
        A0_ADC_CS_O    : out   std_logic;
        A0_ADC_SCK_O   : out   std_logic;
        A0_ADC_SDO_O   : out   std_logic;
        A0_PWM_UH_O    : out   std_logic;
        A0_PWM_UL_O    : out   std_logic;
        A0_PWM_VH_O    : out   std_logic;
        A0_PWM_VL_O    : out   std_logic;
        A0_PWM_WH_O    : out   std_logic;
        A0_PWM_WL_O    : out   std_logic;
        A0_RUNNING_LED : out   std_logic;
        GPIO_0_M2F     : out   std_logic;
        USB_ULPI_STP   : out   std_logic;
        -- Inouts
        USB_ULPI_DATA  : inout std_logic_vector(7 downto 0)
        );
end MC_System_top;
----------------------------------------------------------------------
-- MC_System_top architecture body
----------------------------------------------------------------------
architecture RTL of MC_System_top is
----------------------------------------------------------------------
-- Component declarations
----------------------------------------------------------------------
-- BLDC_Encoder_Axis
component BLDC_Encoder_Axis
    -- Port list
    port(
        -- Inputs
        adc_sdi_i   : in  std_logic;
        paddr_i_0   : in  std_logic_vector(31 downto 0);
        penable_i_0 : in  std_logic;
        psel_i_0    : in  std_logic;
        pwdata_i_0  : in  std_logic_vector(31 downto 0);
        pwrite_i_0  : in  std_logic;
        qa_i        : in  std_logic;
        qb_i        : in  std_logic;
        reset_i     : in  std_logic;
        sys_clk_i   : in  std_logic;
        -- Outputs
        adc_cs_o    : out std_logic;
        adc_sck_o   : out std_logic;
        adc_sdo_o   : out std_logic;
        prdata_o_0  : out std_logic_vector(31 downto 0);
        pready_o_0  : out std_logic;
        pslverr_o_0 : out std_logic;
        pwm_uh      : out std_logic;
        pwm_ul      : out std_logic;
        pwm_vh      : out std_logic;
        pwm_vl      : out std_logic;
        pwm_wh      : out std_logic;
        pwm_wl      : out std_logic
        );
end component;
-- MC_System
component MC_System
    -- Port list
    port(
        -- Inputs
        AMBA_SLAVE_0_PRDATAS0  : in    std_logic_vector(31 downto 0);
        AMBA_SLAVE_0_PREADYS0  : in    std_logic;
        AMBA_SLAVE_0_PSLVERRS0 : in    std_logic;
        AMBA_SLAVE_1_PRDATAS1  : in    std_logic_vector(31 downto 0);
        AMBA_SLAVE_1_PREADYS1  : in    std_logic;
        AMBA_SLAVE_1_PSLVERRS1 : in    std_logic;
        DEVRST_N               : in    std_logic;
        USB_ULPI_DIR           : in    std_logic;
        USB_ULPI_NXT           : in    std_logic;
        USB_ULPI_XCLK          : in    std_logic;
        -- Outputs
        AMBA_SLAVE_0_PADDRS    : out   std_logic_vector(31 downto 0);
        AMBA_SLAVE_0_PENABLES  : out   std_logic;
        AMBA_SLAVE_0_PSELS0    : out   std_logic;
        AMBA_SLAVE_0_PWDATAS   : out   std_logic_vector(31 downto 0);
        AMBA_SLAVE_0_PWRITES   : out   std_logic;
        AMBA_SLAVE_1_PADDRS    : out   std_logic_vector(31 downto 0);
        AMBA_SLAVE_1_PENABLES  : out   std_logic;
        AMBA_SLAVE_1_PSELS1    : out   std_logic;
        AMBA_SLAVE_1_PWDATAS   : out   std_logic_vector(31 downto 0);
        AMBA_SLAVE_1_PWRITES   : out   std_logic;
        FAB_CCC_GL1            : out   std_logic;
        FIC_0_CLK              : out   std_logic;
        FIC_0_LOCK             : out   std_logic;
        GPIO_0_M2F             : out   std_logic;
        USB_ULPI_STP           : out   std_logic;
        -- Inouts
        USB_ULPI_DATA          : inout std_logic_vector(7 downto 0)
        );
end component;
----------------------------------------------------------------------
-- Signal declarations
----------------------------------------------------------------------
signal A0_ADC_CS_O_0                    : std_logic;
signal A0_ADC_SCK_O_0                   : std_logic;
signal A0_ADC_SDO_O_0                   : std_logic;
signal A0_PWM_UH_O_0                    : std_logic;
signal A0_PWM_UL_O_0                    : std_logic;
signal A0_PWM_VH_O_0                    : std_logic;
signal A0_PWM_WH_O_0                    : std_logic;
signal A0_PWM_WL_O_0                    : std_logic;
signal A0_RUNNING_LED_1                 : std_logic;
signal GPIO_0_M2F_net_0                 : std_logic;
signal MC_System_0_AMBA_SLAVE_0_PADDR   : std_logic_vector(31 downto 0);
signal MC_System_0_AMBA_SLAVE_0_PENABLE : std_logic;
signal MC_System_0_AMBA_SLAVE_0_PRDATA  : std_logic_vector(31 downto 0);
signal MC_System_0_AMBA_SLAVE_0_PREADY  : std_logic;
signal MC_System_0_AMBA_SLAVE_0_PSELx   : std_logic;
signal MC_System_0_AMBA_SLAVE_0_PSLVERR : std_logic;
signal MC_System_0_AMBA_SLAVE_0_PWDATA  : std_logic_vector(31 downto 0);
signal MC_System_0_AMBA_SLAVE_0_PWRITE  : std_logic;
signal MC_System_0_FIC_0_CLK            : std_logic;
signal MC_System_0_FIC_0_LOCK           : std_logic;
signal USB_ULPI_STP_1                   : std_logic;
signal GPIO_0_M2F_net_1                 : std_logic;
signal A0_PWM_UL_O_0_net_0              : std_logic;
signal A0_PWM_UH_O_0_net_0              : std_logic;
signal A0_PWM_WH_O_0_net_0              : std_logic;
signal A0_PWM_WL_O_0_net_0              : std_logic;
signal A0_ADC_SCK_O_0_net_0             : std_logic;
signal A0_RUNNING_LED_1_net_0           : std_logic;
signal A0_PWM_VH_O_0_net_0              : std_logic;
signal A0_ADC_CS_O_0_net_0              : std_logic;
signal A0_ADC_SDO_O_0_net_0             : std_logic;
signal A0_RUNNING_LED_1_net_1           : std_logic;
signal USB_ULPI_STP_1_net_0             : std_logic;
----------------------------------------------------------------------
-- TiedOff Signals
----------------------------------------------------------------------
signal AMBA_SLAVE_1_PRDATAS1_const_net_0: std_logic_vector(31 downto 0);
signal VCC_net                          : std_logic;
signal GND_net                          : std_logic;

begin
----------------------------------------------------------------------
-- Constant assignments
----------------------------------------------------------------------
 AMBA_SLAVE_1_PRDATAS1_const_net_0 <= B"00000000000000000000000000000000";
 VCC_net                           <= '1';
 GND_net                           <= '0';
----------------------------------------------------------------------
-- Top level output port assignments
----------------------------------------------------------------------
 GPIO_0_M2F_net_1       <= GPIO_0_M2F_net_0;
 GPIO_0_M2F             <= GPIO_0_M2F_net_1;
 A0_PWM_UL_O_0_net_0    <= A0_PWM_UL_O_0;
 A0_PWM_UL_O            <= A0_PWM_UL_O_0_net_0;
 A0_PWM_UH_O_0_net_0    <= A0_PWM_UH_O_0;
 A0_PWM_UH_O            <= A0_PWM_UH_O_0_net_0;
 A0_PWM_WH_O_0_net_0    <= A0_PWM_WH_O_0;
 A0_PWM_WH_O            <= A0_PWM_WH_O_0_net_0;
 A0_PWM_WL_O_0_net_0    <= A0_PWM_WL_O_0;
 A0_PWM_WL_O            <= A0_PWM_WL_O_0_net_0;
 A0_ADC_SCK_O_0_net_0   <= A0_ADC_SCK_O_0;
 A0_ADC_SCK_O           <= A0_ADC_SCK_O_0_net_0;
 A0_RUNNING_LED_1_net_0 <= A0_RUNNING_LED_1;
 A0_PWM_VL_O            <= A0_RUNNING_LED_1_net_0;
 A0_PWM_VH_O_0_net_0    <= A0_PWM_VH_O_0;
 A0_PWM_VH_O            <= A0_PWM_VH_O_0_net_0;
 A0_ADC_CS_O_0_net_0    <= A0_ADC_CS_O_0;
 A0_ADC_CS_O            <= A0_ADC_CS_O_0_net_0;
 A0_ADC_SDO_O_0_net_0   <= A0_ADC_SDO_O_0;
 A0_ADC_SDO_O           <= A0_ADC_SDO_O_0_net_0;
 A0_RUNNING_LED_1_net_1 <= A0_RUNNING_LED_1;
 A0_RUNNING_LED         <= A0_RUNNING_LED_1_net_1;
 USB_ULPI_STP_1_net_0   <= USB_ULPI_STP_1;
 USB_ULPI_STP           <= USB_ULPI_STP_1_net_0;
----------------------------------------------------------------------
-- Component instances
----------------------------------------------------------------------
-- BLDC_Encoder_Axis_0
BLDC_Encoder_Axis_0 : BLDC_Encoder_Axis
    port map( 
        -- Inputs
        reset_i     => MC_System_0_FIC_0_LOCK,
        sys_clk_i   => MC_System_0_FIC_0_CLK,
        adc_sdi_i   => A0_ADC_SDI_I,
        psel_i_0    => MC_System_0_AMBA_SLAVE_0_PSELx,
        penable_i_0 => MC_System_0_AMBA_SLAVE_0_PENABLE,
        pwrite_i_0  => MC_System_0_AMBA_SLAVE_0_PWRITE,
        qa_i        => QA_I,
        qb_i        => QB_I,
        paddr_i_0   => MC_System_0_AMBA_SLAVE_0_PADDR,
        pwdata_i_0  => MC_System_0_AMBA_SLAVE_0_PWDATA,
        -- Outputs
        pwm_wl      => A0_PWM_WL_O_0,
        pwm_uh      => A0_PWM_UH_O_0,
        pwm_ul      => A0_PWM_UL_O_0,
        pwm_vh      => A0_PWM_VH_O_0,
        pwm_vl      => A0_RUNNING_LED_1,
        pwm_wh      => A0_PWM_WH_O_0,
        adc_sdo_o   => A0_ADC_SDO_O_0,
        adc_sck_o   => A0_ADC_SCK_O_0,
        adc_cs_o    => A0_ADC_CS_O_0,
        pready_o_0  => MC_System_0_AMBA_SLAVE_0_PREADY,
        pslverr_o_0 => MC_System_0_AMBA_SLAVE_0_PSLVERR,
        prdata_o_0  => MC_System_0_AMBA_SLAVE_0_PRDATA 
        );
-- MC_System_0
MC_System_0 : MC_System
    port map( 
        -- Inputs
        USB_ULPI_DIR           => USB_ULPI_DIR,
        USB_ULPI_NXT           => USB_ULPI_NXT,
        USB_ULPI_XCLK          => USB_ULPI_XCLK,
        DEVRST_N               => DEVRST_N,
        AMBA_SLAVE_1_PREADYS1  => VCC_net, -- tied to '1' from definition
        AMBA_SLAVE_1_PSLVERRS1 => GND_net, -- tied to '0' from definition
        AMBA_SLAVE_0_PREADYS0  => MC_System_0_AMBA_SLAVE_0_PREADY,
        AMBA_SLAVE_0_PSLVERRS0 => MC_System_0_AMBA_SLAVE_0_PSLVERR,
        AMBA_SLAVE_1_PRDATAS1  => AMBA_SLAVE_1_PRDATAS1_const_net_0, -- tied to X"0" from definition
        AMBA_SLAVE_0_PRDATAS0  => MC_System_0_AMBA_SLAVE_0_PRDATA,
        -- Outputs
        USB_ULPI_STP           => USB_ULPI_STP_1,
        GPIO_0_M2F             => GPIO_0_M2F_net_0,
        FAB_CCC_GL1            => OPEN,
        FIC_0_CLK              => MC_System_0_FIC_0_CLK,
        AMBA_SLAVE_1_PSELS1    => OPEN,
        AMBA_SLAVE_1_PENABLES  => OPEN,
        AMBA_SLAVE_1_PWRITES   => OPEN,
        AMBA_SLAVE_0_PSELS0    => MC_System_0_AMBA_SLAVE_0_PSELx,
        AMBA_SLAVE_0_PENABLES  => MC_System_0_AMBA_SLAVE_0_PENABLE,
        AMBA_SLAVE_0_PWRITES   => MC_System_0_AMBA_SLAVE_0_PWRITE,
        FIC_0_LOCK             => MC_System_0_FIC_0_LOCK,
        AMBA_SLAVE_1_PADDRS    => OPEN,
        AMBA_SLAVE_1_PWDATAS   => OPEN,
        AMBA_SLAVE_0_PADDRS    => MC_System_0_AMBA_SLAVE_0_PADDR,
        AMBA_SLAVE_0_PWDATAS   => MC_System_0_AMBA_SLAVE_0_PWDATA,
        -- Inouts
        USB_ULPI_DATA          => USB_ULPI_DATA 
        );

end RTL;
