#Build: Synplify Pro I-2013.09M-SP1 , Build 034R, Jan 17 2014
#install: C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1
#OS: Windows 7 6.1
#Hostname: W764-PINNINTIA

#Implementation: synthesis

$ Start of Compile
#Thu Aug 07 14:11:30 2014

Synopsys VHDL Compiler, version comp201309rcp1, Build 078R, built Jan 14 2014
@N|Running in 64-bit mode
Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

@N: CD720 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"D:\MS_MC_single_axis\hdl\mas.vhd":35:7:35:9|Top entity is set to mas.
VHDL syntax check successful!
@N: CD630 :"D:\MS_MC_single_axis\hdl\mas.vhd":35:7:35:9|Synthesizing work.mas.mas 
@W: CG296 :"D:\MS_MC_single_axis\hdl\mas.vhd":96:29:96:35|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\MS_MC_single_axis\hdl\mas.vhd":98:22:98:34|Referenced variable s_reset_state is not in sensitivity list
@W: CG296 :"D:\MS_MC_single_axis\hdl\mas.vhd":152:5:152:11|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\MS_MC_single_axis\hdl\mas.vhd":154:23:154:35|Referenced variable s_reset_state is not in sensitivity list
@W: CD638 :"D:\MS_MC_single_axis\hdl\mas.vhd":65:8:65:20|Signal mas_done_sync is undriven 
Post processing for work.mas.mas
@END

At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Aug 07 14:11:30 2014

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Pre-mapping Report

Synopsys Generic Technology Pre-mapping, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
Product Version I-2013.09M-SP1 

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@L: D:\MS_MC_single_axis\synthesis\mas_scck.rpt 
Printing clock  summary report in "D:\MS_MC_single_axis\synthesis\mas_scck.rpt" file 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB)

@N: BN133 |Ignoring syn_hier=hard property on top-level design.

Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

syn_allowed_resources : blockrams=69,dsps=72  set on top level netlist mas


Clock Summary
**************

Start             Requested     Requested     Clock        Clock              
Clock             Frequency     Period        Type         Group              
------------------------------------------------------------------------------
mas|sys_clk_i     100.0 MHz     10.000        inferred     Inferred_clkgroup_0
==============================================================================

@W: MT530 :"d:\ms_mc_single_axis\hdl\mas.vhd":154:9:154:10|Found inferred clock mas|sys_clk_i which controls 45 sequential elements including product_o[43:0]. This clock has no specified timing constraint which may adversely impact design performance. 

Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file D:\MS_MC_single_axis\synthesis\mas.sap.
Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 132MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Aug 07 14:11:32 2014

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Map & Optimize Report

Synopsys Generic Technology Mapper, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
Product Version I-2013.09M-SP1 

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 132MB)


Available hyper_sources - for debug and ip models
	None Found


Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 132MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 132MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 132MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 132MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 132MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 132MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 132MB)


Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 132MB)


Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 132MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
------------------------------------------------------------


Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 132MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 132MB)



#### START OF CLOCK OPTIMIZATION REPORT #####[

Clock optimization not enabled
1 non-gated/non-generated clock tree(s) driving 3 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

====================================== Non-Gated/Non-Generated Clocks ======================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                     
------------------------------------------------------------------------------------------------------------
@K:CKID0001       sys_clk_i           port                   3          op_mult.un3_product_o_muladd_0[35:0]
============================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]

Writing Analyst data base D:\MS_MC_single_axis\synthesis\mas.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 132MB)

Writing EDIF Netlist and constraint files
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
I-2013.09M-SP1 

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

@W: MT246 :"d:\ms_mc_single_axis\hdl\mas.vhd":158:11:158:12|Blackbox MACC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock mas|sys_clk_i with period 10.00ns. Please declare a user-defined clock on object "p:sys_clk_i"



##### START OF TIMING REPORT #####[
# Timing Report written on Thu Aug 07 14:11:33 2014
#


Top view:               mas
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: NA

                   Requested     Estimated     Requested     Estimated               Clock        Clock              
Starting Clock     Frequency     Frequency     Period        Period        Slack     Type         Group              
---------------------------------------------------------------------------------------------------------------------
mas|sys_clk_i      100.0 MHz     NA            10.000        NA            NA        inferred     Inferred_clkgroup_0
System             100.0 MHz     NA            10.000        NA            NA        system       system_clkgroup    
=====================================================================================================================





Clock Relationships
*******************

Clocks            |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
--------------------------------------------------------------------------------------------------------
Starting  Ending  |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
--------------------------------------------------------------------------------------------------------
========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found


##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report for mas 

Mapping to part: m2s050t_esfbga896std
Cell usage:


Sequential Cells: 
SLE            1 use

DSP Blocks:    1
 MACC:         1 MultAddSub

Total LUTs:    0

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 47MB peak: 133MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Aug 07 14:11:33 2014

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