`

    #Build: Synplify Pro J-2015.03M-3, Build 048R, May 14 2015
    #install: E:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3
    #OS: Windows 7 6.1
    #Hostname: W764-MURALIA

    #Implementation: synthesis

    Synopsys HDL Compiler, version comp201503p1, Build 094R, built May 14 2015
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

    Synopsys VHDL Compiler, version comp201503p1, Build 094R, built May 14 2015
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

    @N:CD720 : std.vhd(123) | Setting time resolution to ns
    @E: :  | Can't open input file E:\Solutions_Repo\Motor Control\Development\MCSK\SK2ABLSLST10_p\RTL\SK2ABLSLST10_5_1\component\Microsemi\SolutionCore\SVM\3.0.2\RTL\svm.vhd
    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Tue Oct 13 12:37:23 2015

    ###########################################################]
    @END
    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Tue Oct 13 12:37:23 2015

    ###########################################################]

`