# Synopsys Constraint Checker, version map201609actrcp1, Build 005R, built Jan 25 2017
# Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

# Written on Wed Nov 29 12:03:30 2017


##### DESIGN INFO #######################################################

Top View:                "MC_System_top"
Constraint File(s):      "F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top.fdc"




##### SUMMARY ############################################################

Found 1 issues in 1 out of 2 constraints


##### DETAILS ############################################################



Clock Relationships
*******************

Starting     Ending     |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise                     
-----------------------------------------------------------------------------------------------------------------------------------
System       System     |     10.000           |     No paths         |     No paths         |     No paths                         
System       GL0        |     10.000           |     No paths         |     No paths         |     No paths                         
GL0          GL0        |     10.000           |     No paths         |     No paths         |     No paths                         
===================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.


Unconstrained Start/End Points
******************************

p:A0_ADC_CS_O
p:A0_ADC_SCK_O
p:A0_ADC_SDI_I
p:A0_ADC_SDO_O
p:A0_PWM_UH_O
p:A0_PWM_UL_O
p:A0_PWM_VH_O
p:A0_PWM_VL_O
p:A0_PWM_WH_O
p:A0_PWM_WL_O
p:A0_RUNNING_LED
p:DEVRST_N
p:GPIO_0_M2F
p:QA_I
p:QB_I
p:USB_ULPI_DATA[0] (bidir end point)
p:USB_ULPI_DATA[0] (bidir start point)
p:USB_ULPI_DATA[1] (bidir end point)
p:USB_ULPI_DATA[1] (bidir start point)
p:USB_ULPI_DATA[2] (bidir end point)
p:USB_ULPI_DATA[2] (bidir start point)
p:USB_ULPI_DATA[3] (bidir end point)
p:USB_ULPI_DATA[3] (bidir start point)
p:USB_ULPI_DATA[4] (bidir end point)
p:USB_ULPI_DATA[4] (bidir start point)
p:USB_ULPI_DATA[5] (bidir end point)
p:USB_ULPI_DATA[5] (bidir start point)
p:USB_ULPI_DATA[6] (bidir end point)
p:USB_ULPI_DATA[6] (bidir start point)
p:USB_ULPI_DATA[7] (bidir end point)
p:USB_ULPI_DATA[7] (bidir start point)
p:USB_ULPI_DIR
p:USB_ULPI_NXT
p:USB_ULPI_STP
p:USB_ULPI_XCLK


Inapplicable constraints
************************

create_clock -name { GL1 } { n:MC_System_0.MC_System_sb_0.CCC_0.GL1_net } -period { 10 } -add
	@E:"f:/svn/motorcontrol/release/webrelease/liberoprojects/sk1ablen10/liberoproject/sk1ablen10/sk1ablen10_5_2_1/synthesis/mc_system_top.fdc":19:0:19:0|object "n:MC_System_0.MC_System_sb_0.CCC_0.GL1_net" does not exist

Applicable constraints with issues
**********************************

(none)


Constraints with matching wildcard expressions
**********************************************

(none)


Library Report
**************


# End of Constraint Checker Report
