<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<title>Timing Report Max Delay Analysis
</title>
<text>SmartTime Version 11.8.2.4</text>
<text>Microsemi Corporation - Microsemi Libero Software Release Libero SoC v11.8 SP2 (Version 11.8.2.4)</text>
<text>Date: Wed Nov 29 12:11:04 2017
</text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>MC_System_top</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2S010</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>0 - 85 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Design State</cell>
 <cell>Post-Layout</cell>
</row>
<row>
 <cell>Data source</cell>
 <cell>Production</cell>
</row>
<row>
 <cell>Min Operating Conditions</cell>
 <cell>WORST - 1.14 V - 85 C</cell>
</row>
<row>
 <cell>Max Operating Conditions</cell>
 <cell>BEST - 1.26 V - 0 C</cell>
</row>
<row>
 <cell>Scenario for Timing Analysis</cell>
 <cell>Primary</cell>
</row>
</table>
<text></text>
<section>
<name>Summary</name>
<table>
<header>
 <cell>Clock Domain</cell>
 <cell>Period (ns)</cell>
 <cell>Frequency (MHz)</cell>
 <cell>Required Period (ns)</cell>
 <cell>Required Frequency (MHz)</cell>
 <cell>External Setup (ns)</cell>
 <cell>External Hold (ns)</cell>
 <cell>Min Clock-To-Out (ns)</cell>
 <cell>Max Clock-To-Out (ns)</cell>
</header>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>5.433</cell>
 <cell>184.060</cell>
 <cell>10.000</cell>
 <cell>100.000</cell>
 <cell>-1.430</cell>
 <cell>2.953</cell>
 <cell>6.640</cell>
 <cell>7.629</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>10.000</cell>
 <cell>100.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
<text></text>
<table>
<header>
 <cell></cell>
 <cell>Min Delay (ns)</cell>
 <cell>Max Delay (ns)</cell>
</header>
<row>
 <cell>Input to Output</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
</section>
<section>
<name>Clock Domain MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>BLDC_Encoder_Axis_0/apb3_en_if_0/rate_limit_ref_in_o[15]:EN</cell>
 <cell>5.015</cell>
 <cell>4.567</cell>
 <cell>8.116</cell>
 <cell>12.683</cell>
 <cell>0.202</cell>
 <cell>5.433</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>BLDC_Encoder_Axis_0/apb3_en_if_0/rate_limit_ref_in_o[12]:EN</cell>
 <cell>5.015</cell>
 <cell>4.567</cell>
 <cell>8.116</cell>
 <cell>12.683</cell>
 <cell>0.202</cell>
 <cell>5.433</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>BLDC_Encoder_Axis_0/apb3_en_if_0/rate_limit_ref_in_o[11]:EN</cell>
 <cell>5.015</cell>
 <cell>4.567</cell>
 <cell>8.116</cell>
 <cell>12.683</cell>
 <cell>0.202</cell>
 <cell>5.433</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>BLDC_Encoder_Axis_0/apb3_en_if_0/rate_limit_ref_in_o[17]:EN</cell>
 <cell>5.015</cell>
 <cell>4.567</cell>
 <cell>8.116</cell>
 <cell>12.683</cell>
 <cell>0.202</cell>
 <cell>5.433</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>BLDC_Encoder_Axis_0/apb3_en_if_0/rate_limit_ref_in_o[16]:EN</cell>
 <cell>5.015</cell>
 <cell>4.575</cell>
 <cell>8.116</cell>
 <cell>12.691</cell>
 <cell>0.202</cell>
 <cell>5.425</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: BLDC_Encoder_Axis_0/apb3_en_if_0/rate_limit_ref_in_o[15]:EN</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>12.683</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>8.116</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.567</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.923</cell>
 <cell>1.923</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.137</cell>
 <cell>2.060</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.113</cell>
 <cell>2.173</cell>
 <cell>13</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.195</cell>
 <cell>2.368</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.173</cell>
 <cell>2.541</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.266</cell>
 <cell>2.807</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.144</cell>
 <cell>2.951</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.150</cell>
 <cell>3.101</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/MC_System_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_HM0_ADDR[10]</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_010_IP</cell>
 <cell>+</cell>
 <cell>1.100</cell>
 <cell>4.201</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>BLDC_Encoder_Axis_0/apb3_en_if_0/prdata_o_1_0_a2_2_a2_1_a2_3[1]:B</cell>
 <cell>net</cell>
 <cell>MC_System_0_AMBA_SLAVE_0_PADDR[10]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.519</cell>
 <cell>4.720</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>BLDC_Encoder_Axis_0/apb3_en_if_0/prdata_o_1_0_a2_2_a2_1_a2_3[1]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.069</cell>
 <cell>4.789</cell>
 <cell>3</cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_Encoder_Axis_0/apb3_en_if_0/prdata_o_1_0_a2_2_a2_1_a2_0[1]:C</cell>
 <cell>net</cell>
 <cell>BLDC_Encoder_Axis_0/apb3_en_if_0/N_464</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.072</cell>
 <cell>4.861</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_Encoder_Axis_0/apb3_en_if_0/prdata_o_1_0_a2_2_a2_1_a2_0[1]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.051</cell>
 <cell>4.912</cell>
 <cell>18</cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_Encoder_Axis_0/apb3_en_if_0/adc_scale_val_o_1_sqmuxa_0_a2_0:B</cell>
 <cell>net</cell>
 <cell>BLDC_Encoder_Axis_0/apb3_en_if_0/N_466</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.579</cell>
 <cell>5.491</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_Encoder_Axis_0/apb3_en_if_0/adc_scale_val_o_1_sqmuxa_0_a2_0:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.110</cell>
 <cell>5.601</cell>
 <cell>15</cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_Encoder_Axis_0/apb3_en_if_0/rate_limit_ref_in_o_1_sqmuxa_0_a2:B</cell>
 <cell>net</cell>
 <cell>BLDC_Encoder_Axis_0/apb3_en_if_0/N_470</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.973</cell>
 <cell>6.574</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_Encoder_Axis_0/apb3_en_if_0/rate_limit_ref_in_o_1_sqmuxa_0_a2:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.110</cell>
 <cell>6.684</cell>
 <cell>18</cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_Encoder_Axis_0/apb3_en_if_0/rate_limit_ref_in_o[15]:EN</cell>
 <cell>net</cell>
 <cell>BLDC_Encoder_Axis_0/apb3_en_if_0/rate_limit_ref_in_o_1_sqmuxa</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.432</cell>
 <cell>8.116</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>8.116</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.923</cell>
 <cell>11.923</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.137</cell>
 <cell>12.060</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.114</cell>
 <cell>12.174</cell>
 <cell>14</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB21:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.197</cell>
 <cell>12.371</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB21:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.173</cell>
 <cell>12.544</cell>
 <cell>117</cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_Encoder_Axis_0/apb3_en_if_0/rate_limit_ref_in_o[15]:CLK</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB21_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.341</cell>
 <cell>12.885</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_Encoder_Axis_0/apb3_en_if_0/rate_limit_ref_in_o[15]:EN</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.202</cell>
 <cell>12.683</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>12.683</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>External Setup (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>A0_ADC_SDI_I</cell>
 <cell>BLDC_Encoder_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D</cell>
 <cell>1.186</cell>
 <cell>6.507</cell>
 <cell>6.109</cell>
 <cell>12.616</cell>
 <cell>0.197</cell>
 <cell>-1.430</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>QB_I</cell>
 <cell>BLDC_Encoder_Axis_0/MSC_i_23/s_qb_dly:D</cell>
 <cell>0.940</cell>
 <cell>6.795</cell>
 <cell>5.863</cell>
 <cell>12.658</cell>
 <cell>0.153</cell>
 <cell>-1.718</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>QA_I</cell>
 <cell>BLDC_Encoder_Axis_0/MSC_i_23/s_qa_dly:D</cell>
 <cell>0.939</cell>
 <cell>6.798</cell>
 <cell>5.862</cell>
 <cell>12.660</cell>
 <cell>0.150</cell>
 <cell>-1.721</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: A0_ADC_SDI_I</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: BLDC_Encoder_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>12.616</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>6.109</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.507</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.923</cell>
 <cell>1.923</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>A0_ADC_SDI_I</cell>
 <cell>Input Delay Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.000</cell>
 <cell>4.923</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>A0_ADC_SDI_I_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>A0_ADC_SDI_I</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>4.923</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>A0_ADC_SDI_I_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>0.917</cell>
 <cell>5.840</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>BLDC_Encoder_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D</cell>
 <cell>net</cell>
 <cell>A0_ADC_SDI_I_ibuf/U0/YIN1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.269</cell>
 <cell>6.109</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.109</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.866</cell>
 <cell>11.866</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.132</cell>
 <cell>11.998</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.110</cell>
 <cell>12.108</cell>
 <cell>14</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB19:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.189</cell>
 <cell>12.297</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB19:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.168</cell>
 <cell>12.465</cell>
 <cell>40</cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_Encoder_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:CLK</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB19_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.348</cell>
 <cell>12.813</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_Encoder_Axis_0/adc_interface_795x_0/spi_engine_inst/s_sdi:D</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:IOINFF</cell>
 <cell>-</cell>
 <cell>0.197</cell>
 <cell>12.616</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>12.616</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>BLDC_Encoder_Axis_0/MSC_i_13/s_state[8]:CLK</cell>
 <cell>A0_RUNNING_LED</cell>
 <cell>4.512</cell>
 <cell>4.237</cell>
 <cell>7.386</cell>
 <cell>11.623</cell>
 <cell>7.386</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>BLDC_Encoder_Axis_0/MSC_i_13/s_state[0]:CLK</cell>
 <cell>A0_RUNNING_LED</cell>
 <cell>4.508</cell>
 <cell>4.241</cell>
 <cell>7.382</cell>
 <cell>11.623</cell>
 <cell>7.382</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>BLDC_Encoder_Axis_0/MSC_i_13/s_state[7]:CLK</cell>
 <cell>A0_RUNNING_LED</cell>
 <cell>4.450</cell>
 <cell>4.299</cell>
 <cell>7.324</cell>
 <cell>11.623</cell>
 <cell>7.324</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>BLDC_Encoder_Axis_0/MSC_i_13/s_state[8]:CLK</cell>
 <cell>A0_PWM_UL_O</cell>
 <cell>3.901</cell>
 <cell>4.848</cell>
 <cell>6.775</cell>
 <cell>11.623</cell>
 <cell>6.775</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>BLDC_Encoder_Axis_0/MSC_i_13/s_state[0]:CLK</cell>
 <cell>A0_PWM_UL_O</cell>
 <cell>3.897</cell>
 <cell>4.852</cell>
 <cell>6.771</cell>
 <cell>11.623</cell>
 <cell>6.771</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: BLDC_Encoder_Axis_0/MSC_i_13/s_state[8]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: A0_RUNNING_LED</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>11.623</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>7.386</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.237</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.923</cell>
 <cell>1.923</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.137</cell>
 <cell>2.060</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.114</cell>
 <cell>2.174</cell>
 <cell>14</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB15:An</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.194</cell>
 <cell>2.368</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB15:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.173</cell>
 <cell>2.541</cell>
 <cell>74</cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_Encoder_Axis_0/MSC_i_13/s_state[8]:CLK</cell>
 <cell>net</cell>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB15_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.333</cell>
 <cell>2.874</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_Encoder_Axis_0/MSC_i_13/s_state[8]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.060</cell>
 <cell>2.934</cell>
 <cell>6</cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_Encoder_Axis_0/MSC_i_13/ADC_START_PROC.un101_s_state_i_a2_0_a3:B</cell>
 <cell>net</cell>
 <cell>BLDC_Encoder_Axis_0/MSC_i_13/MSC_net_83</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.253</cell>
 <cell>3.187</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>BLDC_Encoder_Axis_0/MSC_i_13/ADC_START_PROC.un101_s_state_i_a2_0_a3:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.098</cell>
 <cell>3.285</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>BLDC_Encoder_Axis_0/MSC_i_13/ADC_START_PROC.un103_s_state_i_a3_0_a2:A</cell>
 <cell>net</cell>
 <cell>BLDC_Encoder_Axis_0/MSC_i_13/MSC_net_284</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.066</cell>
 <cell>3.351</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>BLDC_Encoder_Axis_0/MSC_i_13/ADC_START_PROC.un103_s_state_i_a3_0_a2:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.060</cell>
 <cell>3.411</cell>
 <cell>32</cell>
 <cell>f</cell>
</row>
<row>
 <cell>A0_RUNNING_LED_obuf/U0/U_IOOUTFF:A</cell>
 <cell>net</cell>
 <cell>A0_PWM_UL_O_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.531</cell>
 <cell>4.942</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>A0_RUNNING_LED_obuf/U0/U_IOOUTFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOOUTFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.226</cell>
 <cell>5.168</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>A0_RUNNING_LED_obuf/U0/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>A0_RUNNING_LED_obuf/U0/DOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.481</cell>
 <cell>5.649</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>A0_RUNNING_LED_obuf/U0/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>1.737</cell>
 <cell>7.386</cell>
 <cell>0</cell>
 <cell>f</cell>
</row>
<row>
 <cell>A0_RUNNING_LED</cell>
 <cell>net</cell>
 <cell>A0_RUNNING_LED</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>7.386</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.386</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.923</cell>
 <cell>11.923</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>A0_RUNNING_LED</cell>
 <cell>Output Delay Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell>0.300</cell>
 <cell>11.623</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>11.623</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain MC_System_0/MC_System_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain MC_System_0/MC_System_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL1</name>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set Pin to Pin</name>
<section>
<name>SET Input to Output</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set User Sets</name>
</section>
</doc>
