@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\core3phasepwm_st.vhd":51:6:51:11|Formal, "period", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":2290:0:2290:18|Formal, "period", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\speed_id_iq_pi.vhd":55:4:55:12|Formal, "iq_init_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1853:0:1853:18|Formal, "iq_init_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\speed_id_iq_pi.vhd":70:4:70:20|Formal, "id_pi_ref_input_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1853:0:1853:18|Formal, "id_pi_ref_input_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\speed_id_iq_pi.vhd":71:4:71:20|Formal, "id_pi_act_input_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1853:0:1853:18|Formal, "id_pi_act_input_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\speed_id_iq_pi.vhd":73:4:73:13|Formal, "id_pi_kp_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1853:0:1853:18|Formal, "id_pi_kp_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\speed_id_iq_pi.vhd":74:4:74:13|Formal, "id_pi_ki_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1853:0:1853:18|Formal, "id_pi_ki_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\speed_id_iq_pi.vhd":75:4:75:15|Formal, "id_pi_ymax_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1853:0:1853:18|Formal, "id_pi_ymax_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\speed_id_iq_pi.vhd":76:4:76:15|Formal, "id_pi_ymin_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1853:0:1853:18|Formal, "id_pi_ymin_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\speed_id_iq_pi.vhd":77:4:77:19|Formal, "id_pi_kp_scale_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1853:0:1853:18|Formal, "id_pi_kp_scale_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\speed_id_iq_pi.vhd":78:4:78:19|Formal, "id_pi_ki_scale_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1853:0:1853:18|Formal, "id_pi_ki_scale_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\speed_id_iq_pi.vhd":81:4:81:19|Formal, "id_pi_output_y_o", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1853:0:1853:18|Formal, "id_pi_output_y_o", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\speed_id_iq_pi.vhd":83:4:83:20|Formal, "iq_pi_act_input_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1853:0:1853:18|Formal, "iq_pi_act_input_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\speed_id_iq_pi.vhd":85:4:85:13|Formal, "iq_pi_kp_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1853:0:1853:18|Formal, "iq_pi_kp_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\speed_id_iq_pi.vhd":86:4:86:13|Formal, "iq_pi_ki_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1853:0:1853:18|Formal, "iq_pi_ki_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\speed_id_iq_pi.vhd":87:4:87:15|Formal, "iq_pi_ymax_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1853:0:1853:18|Formal, "iq_pi_ymax_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\speed_id_iq_pi.vhd":88:4:88:15|Formal, "iq_pi_ymin_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1853:0:1853:18|Formal, "iq_pi_ymin_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\speed_id_iq_pi.vhd":89:4:89:19|Formal, "iq_pi_kp_scale_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1853:0:1853:18|Formal, "iq_pi_kp_scale_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\speed_id_iq_pi.vhd":90:4:90:19|Formal, "iq_pi_ki_scale_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1853:0:1853:18|Formal, "iq_pi_ki_scale_i", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\speed_id_iq_pi.vhd":93:4:93:19|Formal, "iq_pi_output_y_o", and actual agree on type but not on size
@E: CD145 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\msmc_fab_toplevel_st.vhd":1853:0:1853:18|Formal, "iq_pi_output_y_o", and actual agree on type but not on size
@E: CD297 :"D:\SK1ASTSL10_3_0_multi_axis\hdl\pwm_count.vhd":94:3:94:8|Width mismatch, location has width 16, value 18

