# Wed Nov 29 12:03:31 2017

Synopsys Generic Technology Mapper, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.09M-2

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 146MB)

@W: BN114 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\work\mc_system_sb\mc_system_sb.vhd":674:0:674:11|Removing instance SYSRESET_POR (in view: work.MC_System_sb(rtl)) of black box view:ACG4.SYSRESET(PRIM) because it does not drive other instances.

Available hyper_sources - for debug and ip models
	None Found

@W: FA239 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\actel\directcore\coreapb3\4.1.100\rtl\vhdl\core\coreapb3.vhd":648:12:648:15|ROM CoreAPB3_0.iPSELS_raw_5[1:0] (in view: work.MC_System_sb(rtl)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\actel\directcore\coreapb3\4.1.100\rtl\vhdl\core\coreapb3.vhd":648:12:648:15|ROM CoreAPB3_0.iPSELS_raw_5[1:0] (in view: work.MC_System_sb(rtl)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N: MO106 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\actel\directcore\coreapb3\4.1.100\rtl\vhdl\core\coreapb3.vhd":648:12:648:15|Found ROM .delname. (in view: work.MC_System_sb(rtl)) with 16 words by 2 bits.

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 149MB)

@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\apb3_en_if.vhd":630:8:630:9|Removing sequential instance apb3_en_if_0.pwm_gain_val_o[0] (in view: work.BLDC_Encoder_Axis(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\apb3_en_if.vhd":630:8:630:9|Removing sequential instance apb3_en_if_0.speed_window_o[12] (in view: work.BLDC_Encoder_Axis(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\apb3_en_if.vhd":630:8:630:9|Removing sequential instance apb3_en_if_0.speed_window_o[13] (in view: work.BLDC_Encoder_Axis(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\apb3_en_if.vhd":630:8:630:9|Removing sequential instance apb3_en_if_0.speed_window_o[14] (in view: work.BLDC_Encoder_Axis(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\apb3_en_if.vhd":630:8:630:9|Removing sequential instance apb3_en_if_0.speed_window_o[15] (in view: work.BLDC_Encoder_Axis(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\apb3_en_if.vhd":630:8:630:9|Removing sequential instance apb3_en_if_0.speed_window_o[16] (in view: work.BLDC_Encoder_Axis(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\apb3_en_if.vhd":630:8:630:9|Removing sequential instance apb3_en_if_0.speed_window_o[17] (in view: work.BLDC_Encoder_Axis(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
Encoding state machine state[0:5] (in view: work.adc_interface_795x(adc_interface))
original code -> new code
   000001 -> 000001
   000010 -> 000010
   000100 -> 000100
   001000 -> 001000
   010000 -> 010000
   100000 -> 100000
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[15] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[14] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[13] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[12] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[11] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[10] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[9] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[8] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[7] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[6] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[5] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[4] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[3] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd":368:8:368:9|Register bit s_channel_sel[2] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: BN132 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd":368:8:368:9|Removing instance BLDC_Encoder_Axis_0.adc_interface_795x_0.s_channel_sel[1] because it is equivalent to instance BLDC_Encoder_Axis_0.adc_interface_795x_0.s_channel_sel[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd":584:8:584:9|Register bit s_sdo_reg[0] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd":584:8:584:9|Register bit s_sdo_reg[1] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd":584:8:584:9|Register bit s_sdo_reg[2] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd":584:8:584:9|Register bit s_sdo_reg[3] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd":584:8:584:9|Register bit s_sdo_reg[4] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd":584:8:584:9|Register bit s_sdo_reg[5] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
Encoding state machine s_state[0:3] (in view: adc_scaling_lib.ADC_SCALING(adc_scaling))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
Encoding state machine s_state[0:2] (in view: work.cordic_scale(cordic_scale))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine s_state[0:2] (in view: work.OLMNG(olmng))
original code -> new code
   00 -> 00
   10 -> 01
   11 -> 10
Encoding state machine s_state[0:4] (in view: work.PI_CONTROLLER(pi_controller))
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine s_state[0:4] (in view: work.PWM_SCALING(pwm_scaling))
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine s_ramp_present_state[0:2] (in view: work.RATE_LIMITER(rate_limiter))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine s_state[0:8] (in view: work.SEQ_CONTROLLER(seq_controller))
original code -> new code
   000000001 -> 000000001
   000000010 -> 000000010
   000000100 -> 000000100
   000001000 -> 000001000
   000010000 -> 000010000
   000100000 -> 000100000
   001000000 -> 001000000
   010000000 -> 010000000
   100000000 -> 100000000
Encoding state machine s_state[0:4] (in view: work.pi_controller_spi(pi_controller_spi))
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
Encoding state machine s_state[0:2] (in view: work.SVM(svm))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10

Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 170MB)


Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 167MB peak: 170MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 164MB peak: 170MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 165MB peak: 176MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 167MB peak: 176MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 167MB peak: 176MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 166MB peak: 176MB)


Finished preparing to map (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 168MB peak: 176MB)


Finished technology mapping (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 235MB peak: 239MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:09s		    -1.35ns		4106 /      2543
   2		0h:00m:10s		    -1.34ns		3533 /      2543

   3		0h:00m:10s		    -1.34ns		3533 /      2543
   4		0h:00m:10s		    -2.18ns		3533 /      2543


   5		0h:00m:11s		    -1.31ns		3533 /      2543
@N: FP130 |Promoting Net MC_System_0_FIC_0_LOCK on CLKINT  I_72 

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 243MB peak: 246MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 244MB peak: 246MB)



@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

Clock optimization not enabled
1 non-gated/non-generated clock tree(s) driving 2560 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

===================================================================== Non-Gated/Non-Generated Clocks ======================================================================
Clock Tree ID     Driving Element                                   Drive Element Type              Fanout     Sample Instance                                             
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@K:CKID0001       MC_System_0.MC_System_sb_0.CCC_0.GL0_net_keep     clock definition on keepbuf     2560       MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST
===========================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 199MB peak: 246MB)

Writing Analyst data base F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\synwork\MC_System_top_1_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:14s; Memory used current: 234MB peak: 246MB)

Writing Verilog Simulation files
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:15s; Memory used current: 232MB peak: 246MB)


Start final timing analysis (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 232MB peak: 246MB)

@W: MT246 :"f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\work\mc_system_sb\ccc_0\mc_system_sb_ccc_0_fccc.vhd":110:4:110:11|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@N: MT615 |Found clock GL0 with period 10.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Wed Nov 29 12:03:48 2017
#


Top view:               MC_System_top
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top.fdc
                       
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: 0.860

                   Requested     Estimated      Requested     Estimated               Clock        Clock           
Starting Clock     Frequency     Frequency      Period        Period        Slack     Type         Group           
-------------------------------------------------------------------------------------------------------------------
GL0                100.0 MHz     109.4 MHz      10.000        9.140         0.860     declared     default_clkgroup
System             100.0 MHz     1029.4 MHz     10.000        0.971         9.029     system       system_clkgroup 
===================================================================================================================
@W: MT548 :"f:/svn/motorcontrol/release/webrelease/liberoprojects/sk1ablen10/liberoproject/sk1ablen10/sk1ablen10_5_2_1/synthesis/mc_system_top.fdc":19:0:19:0|Source for clock GL1 not found in netlist. Run the constraint checker to verify if constraints are applied correctly.





Clock Relationships
*******************

Clocks            |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
--------------------------------------------------------------------------------------------------------
Starting  Ending  |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
--------------------------------------------------------------------------------------------------------
System    System  |  10.000      9.029  |  No paths    -      |  No paths    -      |  No paths    -    
System    GL0     |  10.000      3.213  |  No paths    -      |  No paths    -      |  No paths    -    
GL0       GL0     |  10.000      0.860  |  No paths    -      |  No paths    -      |  No paths    -    
========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: GL0
====================================



Starting Points with Worst Slack
********************************

                                                                 Starting                                                                            Arrival          
Instance                                                         Reference     Type        Pin                Net                                    Time        Slack
                                                                 Clock                                                                                                
----------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_ADDR[10]     MC_System_0_AMBA_SLAVE_0_PADDR[10]     3.357       0.860
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_ADDR[5]      MC_System_0_AMBA_SLAVE_0_PADDR[5]      3.110       0.962
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_ADDR[9]      MC_System_0_AMBA_SLAVE_0_PADDR[9]      3.175       0.982
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_ADDR[4]      MC_System_0_AMBA_SLAVE_0_PADDR[4]      3.026       1.004
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_ADDR[6]      MC_System_0_AMBA_SLAVE_0_PADDR[6]      3.185       1.045
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_ADDR[1]      MC_System_0_AMBA_SLAVE_0_PADDR[1]      3.058       1.087
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_ADDR[7]      MC_System_0_AMBA_SLAVE_0_PADDR[7]      3.055       1.129
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_ADDR[0]      MC_System_0_AMBA_SLAVE_0_PADDR[0]      3.112       1.142
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_ADDR[2]      MC_System_0_AMBA_SLAVE_0_PADDR[2]      3.040       1.216
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_ADDR[3]      MC_System_0_AMBA_SLAVE_0_PADDR[3]      3.040       1.417
======================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                 Starting                                                                                             Required          
Instance                                                         Reference     Type        Pin                 Net                                                    Time         Slack
                                                                 Clock                                                                                                                  
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_RDATA[3]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]      9.483        0.860
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_RDATA[4]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]      9.539        0.983
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_RDATA[0]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[0]      9.617        0.994
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_RDATA[9]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[9]      9.594        1.038
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_RDATA[2]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[2]      9.706        1.083
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_RDATA[11]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[11]     9.650        1.094
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_RDATA[6]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[6]      9.651        1.095
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_RDATA[1]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[1]      9.684        1.100
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_RDATA[8]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[8]      9.668        1.112
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     GL0           MSS_010     F_HM0_RDATA[5]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[5]      9.672        1.116
========================================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.517
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.483

    - Propagation time:                      8.623
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     0.860

    Number of logic level(s):                5
    Starting point:                          MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[10]
    Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[3]
    The start point is clocked by            GL0 [rising] on pin CLK_BASE
    The end   point is clocked by            GL0 [rising] on pin CLK_BASE

Instance / Net                                                                           Pin                Pin               Arrival     No. of    
Name                                                                         Type        Name               Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST                 MSS_010     F_HM0_ADDR[10]     Out     3.357     3.357       -         
MC_System_0_AMBA_SLAVE_0_PADDR[10]                                           Net         -                  -       0.971     -           1         
BLDC_Encoder_Axis_0.apb3_en_if_0.prdata_o_1_0_a2_2_a2_1_a2_3[1]              CFG3        B                  In      -         4.328       -         
BLDC_Encoder_Axis_0.apb3_en_if_0.prdata_o_1_0_a2_2_a2_1_a2_3[1]              CFG3        Y                  Out     0.125     4.453       -         
N_464                                                                        Net         -                  -       0.590     -           3         
BLDC_Encoder_Axis_0.apb3_en_if_0.prdata_o_1_0_a2_2_a2_1_a2_3_RNIOSV81[1]     CFG4        D                  In      -         5.043       -         
BLDC_Encoder_Axis_0.apb3_en_if_0.prdata_o_1_0_a2_2_a2_1_a2_3_RNIOSV81[1]     CFG4        Y                  Out     0.250     5.293       -         
prdata_o_1_sn_m32_i_i_a2_1                                                   Net         -                  -       0.648     -           5         
BLDC_Encoder_Axis_0.apb3_en_if_0.prdata_o_1_0_a2_2_a2_1_a2_3_RNI7OD94[1]     CFG2        A                  In      -         5.941       -         
BLDC_Encoder_Axis_0.apb3_en_if_0.prdata_o_1_0_a2_2_a2_1_a2_3_RNI7OD94[1]     CFG2        Y                  Out     0.076     6.016       -         
N_484                                                                        Net         -                  -       0.827     -           19        
BLDC_Encoder_Axis_0.apb3_en_if_0.prdata_o_1_1_0_0[3]                         CFG4        B                  In      -         6.844       -         
BLDC_Encoder_Axis_0.apb3_en_if_0.prdata_o_1_1_0_0[3]                         CFG4        Y                  Out     0.143     6.987       -         
prdata_o_1_1_0_0[3]                                                          Net         -                  -       0.483     -           1         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[3]                CFG4        C                  In      -         7.470       -         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[3]                CFG4        Y                  Out     0.182     7.652       -         
MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]                            Net         -                  -       0.971     -           1         
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST                 MSS_010     F_HM0_RDATA[3]     In      -         8.623       -         
====================================================================================================================================================
Total path delay (propagation time + setup) of 9.140 is 4.649(50.9%) logic and 4.491(49.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                         Starting                                                                                           Arrival          
Instance                                                 Reference     Type               Pin        Net                                                    Time        Slack
                                                         Clock                                                                                                               
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.CCC_0.CCC_INST                System        CCC                LOCK       LOCK                                                   0.000       3.213
MC_System_0.MC_System_sb_0.FABOSC_0.I_RCOSC_25_50MHZ     System        RCOSC_25_50MHZ     CLKOUT     FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     0.000       9.029
=============================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                 Starting                                                                                             Required          
Instance                                                         Reference     Type        Pin                 Net                                                    Time         Slack
                                                                 Clock                                                                                                                  
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[3]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]      9.483        3.213
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[0]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[0]      9.617        3.347
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[2]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[2]      9.706        3.436
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[16]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[16]     9.647        3.445
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[14]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[14]     9.688        3.486
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[15]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[15]     9.695        3.493
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[12]     MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[12]     9.698        3.496
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[4]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]      9.539        3.550
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[1]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[1]      9.684        3.589
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[9]      MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[9]      9.594        3.605
========================================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.517
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.483

    - Propagation time:                      6.270
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 3.213

    Number of logic level(s):                6
    Starting point:                          MC_System_0.MC_System_sb_0.CCC_0.CCC_INST / LOCK
    Ending point:                            MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[3]
    The start point is clocked by            System [rising]
    The end   point is clocked by            GL0 [rising] on pin CLK_BASE

Instance / Net                                                                Pin                Pin               Arrival     No. of    
Name                                                              Type        Name               Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------
MC_System_0.MC_System_sb_0.CCC_0.CCC_INST                         CCC         LOCK               Out     0.000     0.000       -         
LOCK                                                              Net         -                  -       0.971     -           1         
MC_System_0.MC_System_sb_0.CCC_0.CCC_INST_RNI2QPF                 CLKINT      A                  In      -         0.971       -         
MC_System_0.MC_System_sb_0.CCC_0.CCC_INST_RNI2QPF                 CLKINT      Y                  Out     0.326     1.298       -         
MC_System_0_FIC_0_LOCK                                            Net         -                  -       0.993     -           2578      
BLDC_Encoder_Axis_0.OLMNG_0.theta_o[3]                            CFG4        D                  In      -         2.291       -         
BLDC_Encoder_Axis_0.OLMNG_0.theta_o[3]                            CFG4        Y                  Out     0.250     2.541       -         
theta_o[3]                                                        Net         -                  -       0.590     -           3         
BLDC_Encoder_Axis_0.apb3_en_if_0.prdata_o_1_14_i_m2[3]            CFG3        B                  In      -         3.131       -         
BLDC_Encoder_Axis_0.apb3_en_if_0.prdata_o_1_14_i_m2[3]            CFG3        Y                  Out     0.143     3.274       -         
N_857                                                             Net         -                  -       0.483     -           1         
BLDC_Encoder_Axis_0.apb3_en_if_0.prdata_o_1_16_i_m2[3]            CFG3        B                  In      -         3.757       -         
BLDC_Encoder_Axis_0.apb3_en_if_0.prdata_o_1_16_i_m2[3]            CFG3        Y                  Out     0.143     3.900       -         
N_805                                                             Net         -                  -       0.483     -           1         
BLDC_Encoder_Axis_0.apb3_en_if_0.prdata_o_1_1_0_0[3]              CFG4        D                  In      -         4.383       -         
BLDC_Encoder_Axis_0.apb3_en_if_0.prdata_o_1_1_0_0[3]              CFG4        Y                  Out     0.250     4.633       -         
prdata_o_1_1_0_0[3]                                               Net         -                  -       0.483     -           1         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[3]     CFG4        C                  In      -         5.116       -         
MC_System_0.MC_System_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[3]     CFG4        Y                  Out     0.182     5.298       -         
MC_System_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]                 Net         -                  -       0.971     -           1         
MC_System_0.MC_System_sb_0.MC_System_sb_MSS_0.MSS_ADLIB_INST      MSS_010     F_HM0_RDATA[3]     In      -         6.270       -         
=========================================================================================================================================
Total path delay (propagation time + setup) of 6.787 is 1.811(26.7%) logic and 4.975(73.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:16s; Memory used current: 233MB peak: 246MB)


Finished timing report (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:16s; Memory used current: 233MB peak: 246MB)

---------------------------------------
Resource Usage Report for MC_System_top 

Mapping to part: m2s010fbga484-1
Cell usage:
CCC             1 use
CLKINT          2 uses
MSS_010         1 use
RCOSC_25_50MHZ  1 use
CFG1           10 uses
CFG2           458 uses
CFG3           778 uses
CFG4           708 uses

Carry cells:
ARI1            1358 uses - used for arithmetic functions
ARI1            172 uses - used for Wide-Mux implementation
Total ARI1      1530 uses


Sequential Cells: 
SLE            2543 uses

DSP Blocks:    8 of 22 (36%)
 MACC:         3 Mults
 MACC:         5 MultAdds

I/O ports: 27
I/O primitives: 26
BIBUF          8 uses
INBUF          6 uses
OUTBUF         11 uses
TRIBUFF        1 use


Global Clock Buffers: 2 of 8 (25%)


Total LUTs:    3484

Extra resources required for RAM and MACC interface logic during P&R:

RAM64x18 Interface Logic : SLEs = 0; LUTs = 0;
RAM1K18  Interface Logic : SLEs = 0; LUTs = 0;
MACC     Interface Logic : SLEs = 288; LUTs = 288;

Total number of SLEs after P&R:  2543 + 0 + 0 + 288 = 2831;
Total number of LUTs after P&R:  3484 + 0 + 0 + 288 = 3772;

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:16s; Memory used current: 42MB peak: 246MB)

Process took 0h:00m:17s realtime, 0h:00m:16s cputime
# Wed Nov 29 12:03:48 2017

###########################################################]
