# Synopsys Constraint Checker(syntax only), version map201609actrcp1, Build 005R, built Jan 25 2017
# Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

# Written on Wed Nov 29 12:03:29 2017


##### DESIGN INFO #######################################################

Top View:                "MC_System_top"
Constraint File(s):      "F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top.fdc"

#Run constraint checker to find more issues with constraints.
#########################################################################



No issues found in constraint syntax.



Clock Summary
*************

Start      Requested     Requested     Clock        Clock                Clock
Clock      Frequency     Period        Type         Group                Load 
------------------------------------------------------------------------------
GL0        100.0 MHz     10.000        declared     default_clkgroup     2963 
GL1        100.0 MHz     10.000        declared     default_clkgroup     0    
System     100.0 MHz     10.000        system       system_clkgroup      0    
==============================================================================
