Implementation;Generate BitStream;RootName:MC_System_top
Implementation;Generate BitStream||(null)||Please refer to the log file for details||MC_System_top_generateBitstream.log;liberoaction://open_report/file/MC_System_top_generateBitstream.log||(null);(null)
HelpInfo,F:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\html,fpgahelp.qhc,errormessages.mp,F:\Microsemi\Libero_SoC_v11.8\SynplifyPro\bin\mbin\assistant
Implementation;Synthesis;RootName:MC_System_top
Implementation;Synthesis|| CL240 ||@W:Signal XTLOSC_O2F is floating; a simulation mismatch is possible.||MC_System_top_1.srr(45);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/45||MC_System_sb_FABOSC_0_OSC.vhd(16);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd'/linenumber/16
Implementation;Synthesis|| CL240 ||@W:Signal XTLOSC_CCC is floating; a simulation mismatch is possible.||MC_System_top_1.srr(46);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/46||MC_System_sb_FABOSC_0_OSC.vhd(15);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd'/linenumber/15
Implementation;Synthesis|| CL240 ||@W:Signal RCOSC_1MHZ_O2F is floating; a simulation mismatch is possible.||MC_System_top_1.srr(47);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/47||MC_System_sb_FABOSC_0_OSC.vhd(14);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd'/linenumber/14
Implementation;Synthesis|| CL240 ||@W:Signal RCOSC_1MHZ_CCC is floating; a simulation mismatch is possible.||MC_System_top_1.srr(48);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/48||MC_System_sb_FABOSC_0_OSC.vhd(13);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\work\MC_System_sb\FABOSC_0\MC_System_sb_FABOSC_0_OSC.vhd'/linenumber/13
Implementation;Synthesis|| CD434 ||@W:Signal soft_ext_reset_out in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||MC_System_top_1.srr(50);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/50||coreresetp.vhd(477);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/477
Implementation;Synthesis|| CD434 ||@W:Signal soft_reset_f2m in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||MC_System_top_1.srr(51);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/51||coreresetp.vhd(478);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/478
Implementation;Synthesis|| CD434 ||@W:Signal soft_m3_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||MC_System_top_1.srr(52);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/52||coreresetp.vhd(479);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/479
Implementation;Synthesis|| CD434 ||@W:Signal soft_mddr_ddr_axi_s_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||MC_System_top_1.srr(53);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/53||coreresetp.vhd(480);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/480
Implementation;Synthesis|| CD434 ||@W:Signal soft_fddr_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||MC_System_top_1.srr(54);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/54||coreresetp.vhd(481);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/481
Implementation;Synthesis|| CD434 ||@W:Signal soft_sdif0_phy_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||MC_System_top_1.srr(55);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/55||coreresetp.vhd(482);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/482
Implementation;Synthesis|| CD434 ||@W:Signal soft_sdif0_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||MC_System_top_1.srr(56);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/56||coreresetp.vhd(483);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/483
Implementation;Synthesis|| CD434 ||@W:Signal soft_sdif1_phy_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||MC_System_top_1.srr(57);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/57||coreresetp.vhd(484);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/484
Implementation;Synthesis|| CD434 ||@W:Signal soft_sdif1_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||MC_System_top_1.srr(58);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/58||coreresetp.vhd(485);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/485
Implementation;Synthesis|| CD434 ||@W:Signal soft_sdif2_phy_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||MC_System_top_1.srr(59);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/59||coreresetp.vhd(486);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/486
Implementation;Synthesis|| CD434 ||@W:Signal soft_sdif2_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||MC_System_top_1.srr(60);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/60||coreresetp.vhd(487);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/487
Implementation;Synthesis|| CD434 ||@W:Signal soft_sdif3_phy_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||MC_System_top_1.srr(61);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/61||coreresetp.vhd(488);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/488
Implementation;Synthesis|| CD434 ||@W:Signal soft_sdif3_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||MC_System_top_1.srr(62);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/62||coreresetp.vhd(489);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/489
Implementation;Synthesis|| CD434 ||@W:Signal soft_sdif0_0_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||MC_System_top_1.srr(63);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/63||coreresetp.vhd(490);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/490
Implementation;Synthesis|| CD434 ||@W:Signal soft_sdif0_1_core_reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||MC_System_top_1.srr(64);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/64||coreresetp.vhd(491);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/491
Implementation;Synthesis|| CL169 ||@W:Pruning unused register count_ddr_2(13 downto 0). Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(66);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/66||coreresetp.vhd(1519);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1519
Implementation;Synthesis|| CL169 ||@W:Pruning unused register count_sdif3_1(12 downto 0). Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(67);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/67||coreresetp.vhd(1495);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1495
Implementation;Synthesis|| CL169 ||@W:Pruning unused register count_sdif2_1(12 downto 0). Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(68);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/68||coreresetp.vhd(1471);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1471
Implementation;Synthesis|| CL169 ||@W:Pruning unused register count_sdif1_1(12 downto 0). Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(69);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/69||coreresetp.vhd(1447);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1447
Implementation;Synthesis|| CL169 ||@W:Pruning unused register count_sdif0_2(12 downto 0). Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(70);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/70||coreresetp.vhd(1423);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1423
Implementation;Synthesis|| CL169 ||@W:Pruning unused register count_ddr_enable_rcosc_2. Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(71);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/71||coreresetp.vhd(1395);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1395
Implementation;Synthesis|| CL169 ||@W:Pruning unused register count_ddr_enable_q1_2. Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(72);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/72||coreresetp.vhd(1395);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1395
Implementation;Synthesis|| CL169 ||@W:Pruning unused register count_sdif3_enable_rcosc_2. Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(73);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/73||coreresetp.vhd(1395);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1395
Implementation;Synthesis|| CL169 ||@W:Pruning unused register count_sdif2_enable_rcosc_2. Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(74);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/74||coreresetp.vhd(1395);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1395
Implementation;Synthesis|| CL169 ||@W:Pruning unused register count_sdif1_enable_rcosc_2. Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(75);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/75||coreresetp.vhd(1395);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1395
Implementation;Synthesis|| CL169 ||@W:Pruning unused register count_sdif0_enable_rcosc_2. Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(76);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/76||coreresetp.vhd(1395);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1395
Implementation;Synthesis|| CL169 ||@W:Pruning unused register count_sdif3_enable_q1_2. Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(77);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/77||coreresetp.vhd(1395);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1395
Implementation;Synthesis|| CL169 ||@W:Pruning unused register count_sdif2_enable_q1_2. Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(78);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/78||coreresetp.vhd(1395);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1395
Implementation;Synthesis|| CL169 ||@W:Pruning unused register count_sdif1_enable_q1_2. Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(79);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/79||coreresetp.vhd(1395);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1395
Implementation;Synthesis|| CL169 ||@W:Pruning unused register count_sdif0_enable_q1_2. Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(80);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/80||coreresetp.vhd(1395);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1395
Implementation;Synthesis|| CL169 ||@W:Pruning unused register count_sdif3_enable_3. Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(81);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/81||coreresetp.vhd(1311);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1311
Implementation;Synthesis|| CL169 ||@W:Pruning unused register count_sdif2_enable_3. Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(82);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/82||coreresetp.vhd(1252);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1252
Implementation;Synthesis|| CL169 ||@W:Pruning unused register count_sdif1_enable_3. Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(83);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/83||coreresetp.vhd(1193);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1193
Implementation;Synthesis|| CL169 ||@W:Pruning unused register count_sdif0_enable_3. Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(84);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/84||coreresetp.vhd(1134);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1134
Implementation;Synthesis|| CL169 ||@W:Pruning unused register count_ddr_enable_3. Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(85);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/85||coreresetp.vhd(1059);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1059
Implementation;Synthesis|| CL177 ||@W:Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing.||MC_System_top_1.srr(86);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/86||coreresetp.vhd(1331);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1331
Implementation;Synthesis|| CL177 ||@W:Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.||MC_System_top_1.srr(87);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/87||coreresetp.vhd(936);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/936
Implementation;Synthesis|| CL177 ||@W:Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.||MC_System_top_1.srr(88);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/88||coreresetp.vhd(936);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/936
Implementation;Synthesis|| CL177 ||@W:Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.||MC_System_top_1.srr(89);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/89||coreresetp.vhd(936);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/936
Implementation;Synthesis|| CL177 ||@W:Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.||MC_System_top_1.srr(90);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/90||coreresetp.vhd(936);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/936
Implementation;Synthesis|| CL190 ||@W:Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.||MC_System_top_1.srr(91);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/91||coreresetp.vhd(1376);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1376
Implementation;Synthesis|| CL169 ||@W:Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(92);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/92||coreresetp.vhd(1059);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1059
Implementation;Synthesis|| CL169 ||@W:Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(93);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/93||coreresetp.vhd(1376);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1376
Implementation;Synthesis|| CL169 ||@W:Pruning unused register sm2_state(2 downto 0). Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(94);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/94||coreresetp.vhd(1376);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1376
Implementation;Synthesis|| CL169 ||@W:Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(95);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/95||coreresetp.vhd(792);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/792
Implementation;Synthesis|| CL169 ||@W:Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers.||MC_System_top_1.srr(96);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/96||coreresetp.vhd(792);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/792
Implementation;Synthesis|| CD434 ||@W:Signal infill in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||MC_System_top_1.srr(99);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/99||coreapb3.vhd(1453);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd'/linenumber/1453
Implementation;Synthesis|| CD638 ||@W:Signal ia_prdata is undriven. Either assign the signal a value or remove the signal declaration.||MC_System_top_1.srr(100);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/100||coreapb3.vhd(616);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd'/linenumber/616
Implementation;Synthesis|| CL271 ||@W:Pruning unused bits 7 to 3 of s_sys_clk_count_4(7 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.||MC_System_top_1.srr(151);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/151||adc_interface_795x.vhd(539);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/539
Implementation;Synthesis|| CL190 ||@W:Optimizing register bit s_spi_mosi(0) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.||MC_System_top_1.srr(153);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/153||adc_interface_795x.vhd(197);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/197
Implementation;Synthesis|| CL190 ||@W:Optimizing register bit s_spi_mosi(1) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.||MC_System_top_1.srr(154);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/154||adc_interface_795x.vhd(197);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/197
Implementation;Synthesis|| CL190 ||@W:Optimizing register bit s_spi_mosi(2) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.||MC_System_top_1.srr(155);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/155||adc_interface_795x.vhd(197);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/197
Implementation;Synthesis|| CL190 ||@W:Optimizing register bit s_spi_mosi(3) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.||MC_System_top_1.srr(156);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/156||adc_interface_795x.vhd(197);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/197
Implementation;Synthesis|| CL190 ||@W:Optimizing register bit s_spi_mosi(4) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.||MC_System_top_1.srr(157);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/157||adc_interface_795x.vhd(197);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/197
Implementation;Synthesis|| CL190 ||@W:Optimizing register bit s_spi_mosi(5) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.||MC_System_top_1.srr(158);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/158||adc_interface_795x.vhd(197);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/197
Implementation;Synthesis|| CL190 ||@W:Optimizing register bit s_spi_mosi(13) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.||MC_System_top_1.srr(159);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/159||adc_interface_795x.vhd(197);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/197
Implementation;Synthesis|| CL190 ||@W:Optimizing register bit s_spi_mosi(14) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.||MC_System_top_1.srr(160);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/160||adc_interface_795x.vhd(197);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/197
Implementation;Synthesis|| CL190 ||@W:Optimizing register bit s_spi_mosi(15) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.||MC_System_top_1.srr(161);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/161||adc_interface_795x.vhd(197);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/197
Implementation;Synthesis|| CL279 ||@W:Pruning register bits 15 to 13 of s_spi_mosi(15 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.||MC_System_top_1.srr(162);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/162||adc_interface_795x.vhd(197);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/197
Implementation;Synthesis|| CL279 ||@W:Pruning register bits 5 to 0 of s_spi_mosi(15 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.||MC_System_top_1.srr(163);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/163||adc_interface_795x.vhd(197);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/197
Implementation;Synthesis|| CL279 ||@W:Pruning register bits 12 to 11 of s_spi_mosi(12 downto 6). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.||MC_System_top_1.srr(175);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/175||adc_interface_795x.vhd(197);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/197
Implementation;Synthesis|| CL246 ||@W:Input port bits 31 to 12 of paddr_i(31 downto 0) are unused. Assign logic for all port bits or change the input port size.||MC_System_top_1.srr(182);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/182||apb3_en_if.vhd(62);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\hdl\apb3_en_if.vhd'/linenumber/62
Implementation;Synthesis|| CL246 ||@W:Input port bits 31 to 18 of pwdata_i(31 downto 0) are unused. Assign logic for all port bits or change the input port size.||MC_System_top_1.srr(183);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/183||apb3_en_if.vhd(64);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\hdl\apb3_en_if.vhd'/linenumber/64
Implementation;Synthesis|| CL177 ||@W:Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.||MC_System_top_1.srr(281);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/281||coreresetp.vhd(936);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/936
Implementation;Synthesis|| CL177 ||@W:Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.||MC_System_top_1.srr(282);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/282||coreresetp.vhd(936);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/936
Implementation;Synthesis|| CL177 ||@W:Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.||MC_System_top_1.srr(283);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/283||coreresetp.vhd(936);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/936
Implementation;Synthesis|| CL177 ||@W:Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.||MC_System_top_1.srr(284);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/284||coreresetp.vhd(936);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/936
Implementation;Synthesis|| BN132 ||@W:Removing sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance MC_System_0.MC_System_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance.||MC_System_top_1.srr(425);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/425||coreresetp.vhd(1059);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1059
Implementation;Synthesis|| MO129 ||@W:Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation.||MC_System_top_1.srr(426);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/426||coreresetp.vhd(703);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/703
Implementation;Synthesis|| MO129 ||@W:Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation.||MC_System_top_1.srr(427);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/427||coreresetp.vhd(719);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/719
Implementation;Synthesis|| MO129 ||@W:Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation.||MC_System_top_1.srr(428);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/428||coreresetp.vhd(735);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/735
Implementation;Synthesis|| MO129 ||@W:Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation.||MC_System_top_1.srr(429);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/429||coreresetp.vhd(751);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/751
Implementation;Synthesis|| MO129 ||@W:Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation.||MC_System_top_1.srr(430);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/430||coreresetp.vhd(781);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/781
Implementation;Synthesis|| MO129 ||@W:Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation.||MC_System_top_1.srr(431);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/431||coreresetp.vhd(703);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/703
Implementation;Synthesis|| MO129 ||@W:Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation.||MC_System_top_1.srr(432);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/432||coreresetp.vhd(719);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/719
Implementation;Synthesis|| MO129 ||@W:Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation.||MC_System_top_1.srr(433);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/433||coreresetp.vhd(735);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/735
Implementation;Synthesis|| MO129 ||@W:Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation.||MC_System_top_1.srr(434);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/434||coreresetp.vhd(751);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/751
Implementation;Synthesis|| MO129 ||@W:Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation.||MC_System_top_1.srr(435);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/435||coreresetp.vhd(781);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/781
Implementation;Synthesis|| MO129 ||@W:Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation.||MC_System_top_1.srr(436);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/436||coreresetp.vhd(703);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/703
Implementation;Synthesis|| MO129 ||@W:Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation.||MC_System_top_1.srr(437);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/437||coreresetp.vhd(719);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/719
Implementation;Synthesis|| MO129 ||@W:Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation.||MC_System_top_1.srr(438);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/438||coreresetp.vhd(735);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/735
Implementation;Synthesis|| MO129 ||@W:Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation.||MC_System_top_1.srr(439);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/439||coreresetp.vhd(751);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/751
Implementation;Synthesis|| MO129 ||@W:Sequential instance MC_System_0.MC_System_sb_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation.||MC_System_top_1.srr(440);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/440||coreresetp.vhd(1331);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\actel\directcore\coreresetp\7.0.104\rtl\vhdl\core\coreresetp.vhd'/linenumber/1331
Implementation;Synthesis|| MF511 ||@W:Found issues with constraints. Please check constraint checker report "F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1_cck.rpt" .||MC_System_top_1.srr(624);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/624||null;null
Implementation;Synthesis|| BN114 ||@W:Removing instance SYSRESET_POR (in view: work.MC_System_sb(rtl)) of black box view:ACG4.SYSRESET(PRIM) because it does not drive other instances.||MC_System_top_1.srr(664);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/664||mc_system_sb.vhd(674);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\work\mc_system_sb\mc_system_sb.vhd'/linenumber/674
Implementation;Synthesis|| FA239 ||@W:ROM CoreAPB3_0.iPSELS_raw_5[1:0] (in view: work.MC_System_sb(rtl)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.||MC_System_top_1.srr(669);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/669||coreapb3.vhd(648);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\actel\directcore\coreapb3\4.1.100\rtl\vhdl\core\coreapb3.vhd'/linenumber/648
Implementation;Synthesis|| FA239 ||@W:ROM CoreAPB3_0.iPSELS_raw_5[1:0] (in view: work.MC_System_sb(rtl)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.||MC_System_top_1.srr(670);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/670||coreapb3.vhd(648);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\actel\directcore\coreapb3\4.1.100\rtl\vhdl\core\coreapb3.vhd'/linenumber/648
Implementation;Synthesis|| MO160 ||@W:Register bit s_channel_sel[15] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||MC_System_top_1.srr(690);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/690||adc_interface_795x.vhd(368);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/368
Implementation;Synthesis|| MO160 ||@W:Register bit s_channel_sel[14] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||MC_System_top_1.srr(691);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/691||adc_interface_795x.vhd(368);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/368
Implementation;Synthesis|| MO160 ||@W:Register bit s_channel_sel[13] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||MC_System_top_1.srr(692);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/692||adc_interface_795x.vhd(368);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/368
Implementation;Synthesis|| MO160 ||@W:Register bit s_channel_sel[12] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||MC_System_top_1.srr(693);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/693||adc_interface_795x.vhd(368);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/368
Implementation;Synthesis|| MO160 ||@W:Register bit s_channel_sel[11] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||MC_System_top_1.srr(694);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/694||adc_interface_795x.vhd(368);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/368
Implementation;Synthesis|| MO160 ||@W:Register bit s_channel_sel[10] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||MC_System_top_1.srr(695);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/695||adc_interface_795x.vhd(368);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/368
Implementation;Synthesis|| MO160 ||@W:Register bit s_channel_sel[9] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||MC_System_top_1.srr(696);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/696||adc_interface_795x.vhd(368);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/368
Implementation;Synthesis|| MO160 ||@W:Register bit s_channel_sel[8] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||MC_System_top_1.srr(697);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/697||adc_interface_795x.vhd(368);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/368
Implementation;Synthesis|| MO160 ||@W:Register bit s_channel_sel[7] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||MC_System_top_1.srr(698);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/698||adc_interface_795x.vhd(368);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/368
Implementation;Synthesis|| MO160 ||@W:Register bit s_channel_sel[6] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||MC_System_top_1.srr(699);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/699||adc_interface_795x.vhd(368);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/368
Implementation;Synthesis|| MO160 ||@W:Register bit s_channel_sel[5] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||MC_System_top_1.srr(700);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/700||adc_interface_795x.vhd(368);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/368
Implementation;Synthesis|| MO160 ||@W:Register bit s_channel_sel[4] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||MC_System_top_1.srr(701);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/701||adc_interface_795x.vhd(368);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/368
Implementation;Synthesis|| MO160 ||@W:Register bit s_channel_sel[3] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||MC_System_top_1.srr(702);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/702||adc_interface_795x.vhd(368);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/368
Implementation;Synthesis|| MO160 ||@W:Register bit s_channel_sel[2] (in view view:work.adc_interface_795x(adc_interface)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||MC_System_top_1.srr(703);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/703||adc_interface_795x.vhd(368);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/368
Implementation;Synthesis|| BN132 ||@W:Removing instance BLDC_Encoder_Axis_0.adc_interface_795x_0.s_channel_sel[1] because it is equivalent to instance BLDC_Encoder_Axis_0.adc_interface_795x_0.s_channel_sel[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.||MC_System_top_1.srr(704);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/704||adc_interface_795x.vhd(368);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/368
Implementation;Synthesis|| MO160 ||@W:Register bit s_sdo_reg[0] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||MC_System_top_1.srr(705);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/705||adc_interface_795x.vhd(584);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/584
Implementation;Synthesis|| MO160 ||@W:Register bit s_sdo_reg[1] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||MC_System_top_1.srr(706);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/706||adc_interface_795x.vhd(584);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/584
Implementation;Synthesis|| MO160 ||@W:Register bit s_sdo_reg[2] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||MC_System_top_1.srr(707);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/707||adc_interface_795x.vhd(584);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/584
Implementation;Synthesis|| MO160 ||@W:Register bit s_sdo_reg[3] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||MC_System_top_1.srr(708);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/708||adc_interface_795x.vhd(584);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/584
Implementation;Synthesis|| MO160 ||@W:Register bit s_sdo_reg[4] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||MC_System_top_1.srr(709);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/709||adc_interface_795x.vhd(584);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/584
Implementation;Synthesis|| MO160 ||@W:Register bit s_sdo_reg[5] (in view view:work.spi_engine(spi_engine)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||MC_System_top_1.srr(710);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/710||adc_interface_795x.vhd(584);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\hdl\adc_interface_795x.vhd'/linenumber/584
Implementation;Synthesis|| MT246 ||@W:Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) ||MC_System_top_1.srr(855);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/855||mc_system_sb_ccc_0_fccc.vhd(110);liberoaction://cross_probe/hdl/file/'f:\svn\motorcontrol\release\webrelease\liberoprojects\sk1ablen10\liberoproject\sk1ablen10\sk1ablen10_5_2_1\component\work\mc_system_sb\ccc_0\mc_system_sb_ccc_0_fccc.vhd'/linenumber/110
Implementation;Synthesis|| MT548 ||@W:Source for clock GL1 not found in netlist. Run the constraint checker to verify if constraints are applied correctly.||MC_System_top_1.srr(888);liberoaction://cross_probe/hdl/file/'F:\SVN\MotorControl\Release\WebRelease\LiberoProjects\SK1ABLEN10\LiberoProject\SK1ABLEN10\SK1ABLEN10_5_2_1\synthesis\MC_System_top_1.srr'/linenumber/888||mc_system_top.fdc(19);liberoaction://cross_probe/hdl/file/'f:/svn/motorcontrol/release/webrelease/liberoprojects/sk1ablen10/liberoproject/sk1ablen10/sk1ablen10_5_2_1/synthesis/mc_system_top.fdc'/linenumber/19
Implementation;Compile;RootName:MC_System_top
Implementation;Compile||(null)||Please refer to the log file for details about 4 Warning(s) , 7 Info(s)||MC_System_top_compile_log.log;liberoaction://open_report/file/MC_System_top_compile_log.log||(null);(null)
Implementation;Place and Route;RootName:MC_System_top
Implementation;Place and Route||(null)||Please refer to the log file for details about 1 Info(s)||MC_System_top_layout_log.log;liberoaction://open_report/file/MC_System_top_layout_log.log||(null);(null)
Implementation;Generate Bitstream||(null)||Please refer to the log file for details||MC_System_top_generateBitstream.log;liberoaction://open_report/file/MC_System_top_generateBitstream.log||(null);(null)
Implementation;Generate Bitstream;RootName:MC_System_top
