--=================================================================================================
-- File Name                           : foc_transforms_tb.vhd

-- Description                         : This module implements the test environment for
--                                       foc_transforms block

-- Targeted device                     : Microsemi-SoC
-- Author                              : India Solutions Team
--
-- SVN Revision Information            :
-- SVN $Revision                       :
-- SVN $Date                           :
--
-- COPYRIGHT 2015 BY MICROSEMI
-- THE INFORMATION CONTAINED IN THIS DOCUMENT IS SUBJECT TO LICENSING RESTRICTIONS FROM MICROSEMI
-- CORP. IF YOU ARE NOT IN POSSESSION OF WRITTEN AUTHORIZATION FROM MICROSEMI FOR USE OF THIS
-- FILE, THEN THE FILE SHOULD BE IMMEDIATELY DESTROYED AND NO BACK-UP OF THE FILE SHOULD BE MADE.
--
--=================================================================================================
--=================================================================================================
-- Libraries
--=================================================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE STD.TEXTIO.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.MATH_REAL.ALL;   -- FOR UNIFORM, TRUNC FUNCTIONS
LIBRARY MODELSIM_LIB;
USE MODELSIM_LIB.UTIL.ALL;
USE WORK.SIM_PKG.ALL;
--=================================================================================================
-- foc_transforms_tb entity declaration
--=================================================================================================
ENTITY foc_transforms_tb IS

END foc_transforms_tb;

--=================================================================================================
-- foc_transforms_tb architecture body
--=================================================================================================
ARCHITECTURE behavioral OF foc_transforms_tb IS

COMPONENT FOC_transforms IS
GENERIC(
	g_NO_MCYCLE_PATH                   : INTEGER RANGE 0 to 4 := 2
);
PORT (
	reset_i                            : IN  STD_LOGIC;
	sys_clk_i                          : IN  STD_LOGIC;
	start_clarke_i                     : IN  STD_LOGIC;
    start_park_i                       : IN  STD_LOGIC;
    start_ipark_i                      : IN  STD_LOGIC;
    start_iclarke_i                    : IN  STD_LOGIC;
	ia_i                          	   : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);
	ib_i                          	   : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);
	ialpha_i               			   : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);
	ibeta_i                			   : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);
	vd_i                   			   : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);
	vq_i                   			   : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);
	valpha_i                   		   : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);
	vbeta_i                    		   : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);
	theta_i                    		   : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);
    clarke_done_o                      : OUT STD_LOGIC;
    park_done_o                        : OUT STD_LOGIC;
    ipark_done_o                       : OUT STD_LOGIC;
    iclarke_done_o                     : OUT STD_LOGIC;
    ialpha_o             			   : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
	ibeta_o              			   : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
	id_o                   			   : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
	iq_o                   			   : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
	valpha_o              	    	   : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
	vbeta_o               			   : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
	va_o                        	   : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
	vb_o                        	   : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
	vc_o                        	   : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
);
END COMPONENT;

--=================================================================================================
-- Signal declarations
--=================================================================================================
CONSTANT SYSCLK_PERIOD                 : TIME := 100 ns;

SIGNAL sys_clk_tb                      : STD_LOGIC:= '0';
SIGNAL reset_tb                        : STD_LOGIC:= '0';
SIGNAL s_reset_tb_pul                  : STD_LOGIC;
SIGNAL s_reset_tb_dly                  : STD_LOGIC;
SIGNAL s_reset_tb_dly1                 : STD_LOGIC;
SIGNAL s_start_tb                      : STD_LOGIC;
SIGNAL s_start_tb_dly                  : STD_LOGIC;
SIGNAL counter                         : STD_LOGIC_VECTOR(11 DOWNTO 0);
--clarke
SIGNAL s_clarke_done_tb                : STD_LOGIC;
SIGNAL s_clarke_done_tb_dly            : STD_LOGIC;
SIGNAL s_clarke_done_tb_dly1           : STD_LOGIC;
SIGNAL s_counter_error_ia_tb           : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL s_counter_error_ib_tb           : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL s_ialpha_tb                     : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_ibeta_tb                      : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_error_ia_tb                   : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_error_ib_tb                   : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL m_ialpha_tb                     : STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL m_ibeta_tb                      : STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL m_ia_tb                         : STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL m_ib_tb                         : STD_LOGIC_VECTOR(19 DOWNTO 0);
--park
SIGNAL s_park_done_tb                  : STD_LOGIC;
SIGNAL s_park_done_tb_dly              : STD_LOGIC;
SIGNAL s_park_done_tb_dly1             : STD_LOGIC;
SIGNAL s_counter_error_id_tb           : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL s_counter_error_iq_tb           : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL s_id_tb                         : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_iq_tb                         : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_error_id_tb                   : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_error_iq_tb                   : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL m_id_tb                         : STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL m_iq_tb                         : STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL m_vd_tb                         : STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL m_vq_tb                         : STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL m_ialpha_park_tb                : STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL m_ibeta_park_tb                 : STD_LOGIC_VECTOR(19 DOWNTO 0);
-- ipark
SIGNAL s_ipark_done_tb                 : STD_LOGIC;
SIGNAL s_ipark_done_tb_dly             : STD_LOGIC;
SIGNAL s_ipark_done_tb_dly1            : STD_LOGIC;
SIGNAL s_counter_error_valpha_tb       : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL s_counter_error_vbeta_tb        : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL s_valpha_tb                     : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_vbeta_tb                      : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_error_valpha_tb               : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_error_vbeta_tb                : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL m_valpha_iclarke_tb             : STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL m_vbeta_iclarke_tb              : STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL m_theta_tb                      : STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL m_valpha_tb                     : STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL m_vbeta_tb                      : STD_LOGIC_VECTOR(19 DOWNTO 0);
--iclarke
SIGNAL s_iclarke_done_tb               : STD_LOGIC;
SIGNAL s_iclarke_done_tb_dly           : STD_LOGIC;
SIGNAL s_iclarke_done_tb_dly1          : STD_LOGIC;
SIGNAL s_counter_error_va_tb           : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL s_counter_error_vb_tb           : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL s_counter_error_vc_tb           : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL s_error_va_tb                   : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_error_vb_tb                   : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_error_vc_tb                   : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_va_tb                         : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_vb_tb                         : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL s_vc_tb                         : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL m_va_tb                         : STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL m_vb_tb                         : STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL m_vc_tb                         : STD_LOGIC_VECTOR(19 DOWNTO 0);
TYPE   foc_transforms_op_state is      (IDLE,IND_TEST,OUTPUT_COMPARE);

SIGNAL state                           : foc_transforms_op_state;
--========================================================
-- File read operations
--========================================================
--NA--
--========================================================
-- File Write operations
--========================================================
--NA--
--========================================================
-- Procedure Declarations
--========================================================
--NA--
BEGIN
--========================================================
-- SIGNAL spy operations
--========================================================
--NA--
--------------------------------------------------------------------------
-- Name       : RESET_GEN_PROC
-- Description: PROCESS generates the start signal
--------------------------------------------------------------------------
RESET_GEN_PROC:
    PROCESS
        VARIABLE vhdl_initial : BOOLEAN := TRUE;
    BEGIN
        IF ( vhdl_initial ) THEN
            reset_tb <= '0';
            WAIT FOR ( SYSCLK_PERIOD * 10 );
            reset_tb <= '1';
            WAIT;
        END IF;
    END PROCESS;
--------------------------------------------------------------------------
-- Name       : CLOCK_GEN
-- Description: Logic generates 10 Mhz clock
--------------------------------------------------------------------------
sys_clk_tb <= NOT sys_clk_tb AFTER (SYSCLK_PERIOD / 2.0 );

--------------------------------------------------------------------------
-- Name       : RESET_PUL_GEN_PROC
-- Description: process to generate a pulse
--------------------------------------------------------------------------
RESET_PUL_GEN_PROC:
    PROCESS(reset_tb,sys_clk_tb)
    BEGIN
        IF(reset_tb = '0') THEN
            s_reset_tb_dly <= '0';
            s_reset_tb_dly1 <= '0';
        ELSIF(RISING_EDGE (sys_clk_tb))THEN
            s_reset_tb_dly <= reset_tb;
            s_reset_tb_dly1 <= s_reset_tb_dly;
        END IF;
    END PROCESS;
    s_reset_tb_pul <= s_reset_tb_dly AND (not(s_reset_tb_dly1 ));

--------------------------------------------------------------------------
-- Name       : DELAY_PROC
-- Description: Process to delay a signal
--------------------------------------------------------------------------

DELAY_PROC:PROCESS(sys_clk_tb,s_reset_tb_dly1)
    BEGIN
        IF s_reset_tb_dly1 = '0' THEN
            s_clarke_done_tb_dly        <= '0';
            s_clarke_done_tb_dly1       <= '0';
            s_park_done_tb_dly          <= '0';
            s_park_done_tb_dly1         <= '0';
            s_ipark_done_tb_dly         <= '0';
            s_ipark_done_tb_dly1        <= '0';
            s_iclarke_done_tb_dly       <= '0';
            s_iclarke_done_tb_dly1      <= '0';
        ELSIF RISING_EDGE(sys_clk_tb) THEN
            s_clarke_done_tb_dly        <= s_clarke_done_tb;
            s_clarke_done_tb_dly1       <= s_clarke_done_tb_dly;
            s_park_done_tb_dly          <= s_park_done_tb;
            s_park_done_tb_dly1         <= s_park_done_tb_dly;
            s_ipark_done_tb_dly         <= s_ipark_done_tb;
            s_ipark_done_tb_dly1        <= s_ipark_done_tb_dly;
            s_iclarke_done_tb_dly       <= s_iclarke_done_tb;
            s_iclarke_done_tb_dly1      <= s_iclarke_done_tb_dly;
        END IF;
    END PROCESS;

--------------------------------------------------------------------------
-- Name       : RESET_TEST_PROC
-- Description: PROCESS to check the state of all outputs at reset
--------------------------------------------------------------------------
RESET_TEST_PROC:
PROCESS(s_reset_tb_pul,
        s_clarke_done_tb,
        s_park_done_tb,
        s_ipark_done_tb,
        s_iclarke_done_tb,
        s_ialpha_tb,
        s_ibeta_tb,
        s_id_tb,s_iq_tb,s_valpha_tb,s_vbeta_tb,s_va_tb,s_vb_tb,s_vc_tb)
BEGIN
    IF (s_reset_tb_pul = '1') THEN
        IF((s_clarke_done_tb = '0') AND (s_ialpha_tb = "00" & x"0000") AND (s_ibeta_tb = "00" & x"0000") AND
        (s_park_done_tb = '0') AND (s_id_tb = "00" & x"0000") AND (s_iq_tb = "00" & x"0000") AND
        (s_ipark_done_tb = '0') AND (s_valpha_tb = "00" & x"0000") AND (s_vbeta_tb = "00" & x"0000")AND
        (s_iclarke_done_tb = '0') AND (s_va_tb = "00" & x"0000") AND (s_vb_tb = "00" & x"0000") AND (s_vc_tb = "00" & x"0000") )THEN
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print(">>>>>>>>                   FOC_TRANSFORMS IP INTEGRATED SIMULATION                  <<<<<<<");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print(">>>>>>>>     THIS TESTBENCH COMPARES THE FUNCTIONALITY W.R.T THE TESTBENCH MODEL    <<<<<<<");
            print(">>>>>>>>     WITH IN THE TOLERANCE RANGE [-1,0,+1]                                  <<<<<<<");
            print(">>>>>>>>                                                                            <<<<<<<");
            print(">>>>>>>>     ALL  PARAMETERS/GENERICS ARE FIXED TO THE FOLLOWING:                   <<<<<<<");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print(">>>>>>>>     g_NO_MCYCLE_PATH        =  2                                           <<<<<<<");
            print(">>>>>>>>     g_STD_IO_WIDTH          = 18                                           <<<<<<<");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print("                                                        ");
            print("                                                        ");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print(">>>>        CLARKE_RESET_TEST : PASSED              <<<<");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print(">>>>     clarke_done_o         = 0                  <<<<");
            print(">>>>     ialpha_o              = 0                  <<<<");
            print(">>>>     ibeta_o               = 0                  <<<<");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print(">>>>        PARK_RESET_TEST : PASSED                <<<<");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print(">>>>     park_done_o           = 0                  <<<<");
            print(">>>>     ialpha_o              = 0                  <<<<");
            print(">>>>     ibeta_o               = 0                  <<<<");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print(">>>>        INVERSE_PARK_RESET_TEST : PASSED        <<<<");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print(">>>>     ipark_done_o          = 0                  <<<<");
            print(">>>>     valpha_o              = 0                  <<<<");
            print(">>>>     vbeta_o               = 0                  <<<<");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print(">>>>        INVERSE_CLARKE_RESET_TEST : PASSED      <<<<");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print(">>>>     iclarke_done_o    = 0                      <<<<");
            print(">>>>     va_o              = 0                      <<<<");
            print(">>>>     vb_o              = 0                      <<<<");
            print(">>>>     vc_o              = 0                      <<<<");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
        ELSE
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print(">>>>>>>>                   FOC_TRANSFORMS IP INTEGRATED SIMULATION                  <<<<<<<");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print(">>>>>>>>     THIS TESTBENCH COMPARES THE FUNCTIONALITY W.R.T THE TESTBENCH MODEL    <<<<<<<");
            print(">>>>>>>>     WITH IN THE TOLERANCE RANGE [-1,0,+1]                                  <<<<<<<");
            print(">>>>>>>>                                                                            <<<<<<<");
            print(">>>>>>>>     ALL  PARAMETERS/GENERICS ARE FIXED TO THE FOLLOWING:                   <<<<<<<");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print(">>>>>>>>     g_NO_MCYCLE_PATH        =  2                                           <<<<<<<");
            print(">>>>>>>>     g_STD_IO_WIDTH          = 18                                           <<<<<<<");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print("                                                        ");
            print("                                                        ");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print(">>>>        CLARKE_RESET_TEST : FAILED              <<<<");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print(">>>>     clarke_done_o        /= 0                  <<<<");
            print(">>>>     ialpha_o             /= 0                  <<<<");
            print(">>>>     ibeta_o              /= 0                  <<<<");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print(">>>>        PARK_RESET_TEST : FAILED                <<<<");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print(">>>>     park_done_o          /= 0                  <<<<");
            print(">>>>     ialpha_o             /= 0                  <<<<");
            print(">>>>     ibeta_o              /= 0                  <<<<");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print(">>>>        INVERSE_PARK_RESET_TEST : FAILED        <<<<");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print(">>>>     ipark_done_o         /= 0                  <<<<");
            print(">>>>     valpha_o             /= 0                  <<<<");
            print(">>>>     vbeta_o              /= 0                  <<<<");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print(">>>>        INVERSE_CLARKE_RESET_TEST : FAILED      <<<<");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
            print(">>>>     iclarke_done_o       /= 0                  <<<<");
            print(">>>>     va_o                 /= 0                  <<<<");
            print(">>>>     vb_o                 /= 0                  <<<<");
            print(">>>>     vc_o                 /= 0                  <<<<");
            print("<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
        END IF;
    END IF;
END PROCESS;
--------------------------------------------------------------------------
-- Name       : START_GEN_PROC
-- Description: Process generates the start signal
--------------------------------------------------------------------------
START_GEN_PROC:
    PROCESS(s_reset_tb_dly1,sys_clk_tb)
    BEGIN
        IF s_reset_tb_dly1 = '0' THEN
            s_start_tb            <= '0';
            s_start_tb_dly        <= '0';
        ELSIF RISING_EDGE(sys_clk_tb) THEN
            IF(state = IND_TEST) THEN
                s_start_tb <= '1';
            ELSIF(state = OUTPUT_COMPARE) THEN
                s_start_tb <= '0';
            ELSE
                s_start_tb <= '0';
            END IF;
        END IF;
        s_start_tb_dly <= s_start_tb;
    END PROCESS;

--------------------------------------------------------------------------
-- Name       : FOC_TRANSFORM_TB_FSM_PROC
-- Description: FSM implements foc_transforms IP testbench controller operation
--------------------------------------------------------------------------
FOC_TRANSFORM_TB_FSM_PROC:
    PROCESS(sys_clk_tb,s_reset_tb_dly1)
    BEGIN
        IF(s_reset_tb_dly1 = '0') THEN
            state                       <= IDLE;
        ELSIF (RISING_EDGE(sys_clk_tb)) THEN
            CASE(state)IS
--------------------
-- IDLE state
--------------------
            WHEN IDLE =>

                IF(counter < x"00A") THEN
                    state <= IND_TEST;
                ELSE
                    state <= IDLE;
                END IF;
--------------------
-- IND_TEST state
--------------------
            WHEN IND_TEST =>

                IF(counter < x"00A") THEN
                    state <= OUTPUT_COMPARE;
                ELSE
                    state <= IDLE;
                    print("");
                    print("");
                    print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                    print("<<<<            END OF FOC_TRANSORMS IP SIMULATION             >>>>");
                    print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                END IF;
--------------------
-- OUTPUT_COMPARE state
--------------------
            WHEN OUTPUT_COMPARE =>
                IF(s_iclarke_done_tb = '1') THEN
                    state <= IND_TEST;
                    IF(s_counter_error_ia_tb = x"000" ) AND (s_counter_error_ia_tb = x"000")THEN
                        print("                                                                 ");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        print_text_val("|  CLARKE TESTCASE   :  ",(to_integer(signed(counter))),"                                        |");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        print("   INPUTS                                                            ");
                        print_text_val("       IA_IN       =  ",(to_integer(signed(m_ia_tb))),"     ");
                        print_text_val("       IB_IN       =  ",(to_integer(signed(m_ib_tb))),"     ");
                        print("                                                                     ");
                        print("   OUTPUTS                                                           ");
                        print_text_val("       IALPHA_DUT  =  ",(to_integer(signed(s_ialpha_tb)))," ");
                        print_text_val("       IALPHA_DUT  =  ",(to_integer(signed(s_ibeta_tb))),"  ");
                        print_text_val("       IALPHA_TB   =  ",(to_integer(signed(m_ialpha_tb)))," ");
                        print_text_val("       IALPHA_TB   =  ",(to_integer(signed(m_ibeta_tb))),"  ");
                        print("                                                           ");
                        print("     STATUS            :  PASSED                           ");
                        print("     DESCRIPTION       :  TB AND DUT OUTPUTS MATCH         ");
                        print("                                                           ");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                    ELSE
                        print("                                                                 ");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        print_text_val("|  CLARKE TESTCASE   :  ",(to_integer(signed(counter))),"                                        |");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                         print("   INPUTS                                                           ");
                        print_text_val("       IA_IN       =  ",(to_integer(signed(m_ia_tb))),"     ");
                        print_text_val("       IB_IN       =  ",(to_integer(signed(m_ib_tb))),"     ");
                        print("                                                                     ");
                        print("   OUTPUTS                                                           ");
                        print_text_val("       IALPHA_DUT  =  ",(to_integer(signed(s_ialpha_tb)))," ");
                        print_text_val("       IALPHA_DUT  =  ",(to_integer(signed(s_ibeta_tb))),"  ");
                        print_text_val("       IALPHA_TB   =  ",(to_integer(signed(m_ialpha_tb)))," ");
                        print_text_val("       IALPHA_TB   =  ",(to_integer(signed(m_ibeta_tb))),"  ");
                        print("                                                           ");
                        print("     STATUS            :  FAILED                           ");
                        print("     DESCRIPTION       :  TB AND DUT OUTPUTS DO NOT MATCH  ");
                        print("                                                           ");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                    END IF;

                    IF(s_counter_error_id_tb = x"000" ) AND (s_counter_error_iq_tb = x"000")THEN
                        print("                                                                 ");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        print_text_val("|  PARK TESTCASE   :  ",(to_integer(signed(counter))),"                                          |");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        print("   INPUTS                                                                 ");
                        print_text_val("       IALPHA_IN   =  ",(to_integer(signed(m_ialpha_park_tb)))," ");
                        print_text_val("       IBETA_IN    =  ",(to_integer(signed(m_ibeta_park_tb))),"  ");
                        print("                                                                          ");
                        print("   OUTPUTS                                                                ");
                        print_text_val("       ID_DUT      =  ",(to_integer(signed(s_id_tb))),"          ");
                        print_text_val("       IQ_DUT      =  ",(to_integer(signed(s_iq_tb))),"          ");
                        print_text_val("       ID_TB       =  ",(to_integer(signed(m_id_tb))),"          ");
                        print_text_val("       IQ_TB       =  ",(to_integer(signed(m_iq_tb))),"          ");
                        print("                                                           ");
                        print("     STATUS            :  PASSED                           ");
                        print("     DESCRIPTION       :  TB AND DUT OUTPUTS MATCH         ");
                        print("                                                           ");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                    ELSE
                        print("                                                                 ");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        print_text_val("|  PARK TESTCASE   :  ",(to_integer(signed(counter))),"                                          |");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        print("   INPUTS                                                                 ");
                        print_text_val("       IALPHA_IN   =  ",(to_integer(signed(m_ialpha_park_tb)))," ");
                        print_text_val("       IBETA_IN    =  ",(to_integer(signed(m_ibeta_park_tb))),"  ");
                        print("                                                                          ");
                        print("   OUTPUTS                                                                ");
                        print_text_val("       ID_DUT      =  ",(to_integer(signed(s_id_tb))),"          ");
                        print_text_val("       IQ_DUT      =  ",(to_integer(signed(s_iq_tb))),"          ");
                        print_text_val("       ID_TB       =  ",(to_integer(signed(m_id_tb))),"          ");
                        print_text_val("       IQ_TB       =  ",(to_integer(signed(m_iq_tb))),"          ");
                        print("                                                           ");
                        print("     STATUS            :  FAILED                           ");
                        print("     DESCRIPTION       :  TB AND DUT OUTPUTS DO NOT MATCH  ");
                        print("                                                           ");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                    END IF;

                    IF(s_counter_error_valpha_tb = x"000" ) AND (s_counter_error_vbeta_tb = x"000")THEN
                        print("                                                                 ");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        print_text_val("|  IPARK TESTCASE   :  ",(to_integer(signed(counter))),"                                         |");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        print("   INPUTS                                                            ");
                        print_text_val("       VD_IN       =  ",(to_integer(signed(m_vd_tb))),"     ");
                        print_text_val("       VQ_IN       =  ",(to_integer(signed(m_vq_tb))),"     ");
                        print("                                                                     ");
                        print("   OUTPUTS                                                           ");
                        print_text_val("       VALPHA_DUT  =  ",(to_integer(signed(s_valpha_tb)))," ");
                        print_text_val("       VBETA_DUT   =  ",(to_integer(signed(s_vbeta_tb))),"  ");
                        print_text_val("       VALPHA_TB   =  ",(to_integer(signed(m_valpha_tb)))," ");
                        print_text_val("       VBETA_TB    =  ",(to_integer(signed(m_vbeta_tb))),"  ");
                        print("                                                           ");
                        print("     STATUS            :  PASSED                           ");
                        print("     DESCRIPTION       :  TB AND DUT OUTPUTS MATCH         ");
                        print("                                                           ");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                    ELSE
                        print("                                                                 ");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        print_text_val("|  IPARK TESTCASE   :  ",(to_integer(signed(counter))),"                                         |");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        print("   INPUTS                                                            ");
                        print_text_val("       VD_IN       =  ",(to_integer(signed(m_vd_tb))),"     ");
                        print_text_val("       VQ_IN       =  ",(to_integer(signed(m_vq_tb))),"     ");
                        print("                                                                     ");
                        print("   OUTPUTS                                                           ");
                        print_text_val("       VALPHA_DUT  =  ",(to_integer(signed(s_valpha_tb)))," ");
                        print_text_val("       VBETA_DUT   =  ",(to_integer(signed(s_vbeta_tb))),"  ");
                        print_text_val("       VALPHA_TB   =  ",(to_integer(signed(m_valpha_tb)))," ");
                        print_text_val("       VBETA_TB    =  ",(to_integer(signed(m_vbeta_tb))),"  ");
                        print("                                                           ");
                        print("     STATUS            :  FAILED                           ");
                        print("     DESCRIPTION       :  TB AND DUT OUTPUTS DO NOT MATCH  ");
                        print("                                                           ");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                    END IF;


                    IF(s_counter_error_va_tb = x"000" ) AND (s_counter_error_vb_tb = x"000") AND (s_counter_error_vc_tb = x"000" ) THEN
                        print("                                                                 ");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        print_text_val("|  ICLARKE TESTCASE   :  ",(to_integer(signed(counter))),"                                       |");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        print("   INPUTS                                                                    ");
                        print_text_val("       VALPHA_IN   =  ",(to_integer(signed(m_valpha_iclarke_tb)))," ");
                        print_text_val("       VBETA_IN    =  ",(to_integer(signed(m_vbeta_iclarke_tb))),"  ");
                        print("                                                                             ");
                        print("   OUTPUTS                                                                   ");
                        print_text_val("       VA_DUT      =  ",(to_integer(signed(s_va_tb))),"             ");
                        print_text_val("       VB_DUT      =  ",(to_integer(signed(s_vb_tb))),"             ");
                        print_text_val("       VC_DUT      =  ",(to_integer(signed(s_vc_tb))),"             ");
                        print_text_val("       VA_TB       =  ",(to_integer(signed(m_va_tb))),"             ");
                        print_text_val("       VB_TB       =  ",(to_integer(signed(m_vb_tb))),"             ");
                        print_text_val("       VC_TB       =  ",(to_integer(signed(m_vc_tb))),"             ");
                        print("                                                           ");
                        print("     STATUS            :  PASSED                           ");
                        print("     DESCRIPTION       :  TB AND DUT OUTPUTS MATCH         ");
                        print("                                                           ");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                    ELSE
                        print("                                                                 ");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        print_text_val("|  ICLARKE TESTCASE   :  ",(to_integer(signed(counter))),"                                            |");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                        print("   INPUTS                                                                    ");
                        print_text_val("       VALPHA_IN   =  ",(to_integer(signed(m_valpha_iclarke_tb)))," ");
                        print_text_val("       VBETA_IN    =  ",(to_integer(signed(m_vbeta_iclarke_tb))),"  ");
                        print("                                                                             ");
                        print("   OUTPUTS                                                                   ");
                        print_text_val("       VA_DUT      =  ",(to_integer(signed(s_va_tb))),"             ");
                        print_text_val("       VB_DUT      =  ",(to_integer(signed(s_vb_tb))),"             ");
                        print_text_val("       VC_DUT      =  ",(to_integer(signed(s_vc_tb))),"             ");
                        print_text_val("       VA_TB       =  ",(to_integer(signed(m_va_tb))),"             ");
                        print_text_val("       VB_TB       =  ",(to_integer(signed(m_vb_tb))),"             ");
                        print_text_val("       VC_TB       =  ",(to_integer(signed(m_vc_tb))),"             ");
                        print("                                                           ");
                        print("     STATUS            :  FAILED                           ");
                        print("     DESCRIPTION       :  TB AND DUT OUTPUTS DO NOT MATCH  ");
                        print("                                                           ");
                        print("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
                    END IF;
                ELSE
                    state <= OUTPUT_COMPARE;
                END IF;
--------------------
-- OTHERS state
--------------------
            WHEN OTHERS =>
                state               <= IDLE;
            END CASE;
        END IF;
    END PROCESS;

--------------------------------------------------------------------------
-- Name       : DATA_COMPARE_PROC
-- Description: Process compares the DUT output with the matlab reference model outputs
-------------------------------------------------------------------------
DATA_COMPARE_PROC:
    PROCESS(s_reset_tb_dly1,sys_clk_tb)
    BEGIN
        --clarke
        ERROR_COMPUTE_2 (s_reset_tb_dly1,sys_clk_tb,s_clarke_done_tb_dly,s_clarke_done_tb_dly1,m_ialpha_tb,m_ibeta_tb,s_ialpha_tb,s_ibeta_tb,s_error_ia_tb,s_error_ib_tb,s_counter_error_ia_tb,s_counter_error_ib_tb);

        --park
        ERROR_COMPUTE_2 (s_reset_tb_dly1,sys_clk_tb,s_park_done_tb_dly,s_park_done_tb_dly1,m_id_tb,m_iq_tb,s_id_tb,s_iq_tb,s_error_id_tb,s_error_iq_tb,s_counter_error_id_tb,s_counter_error_iq_tb);

        --ipark
        ERROR_COMPUTE_2 (s_reset_tb_dly1,sys_clk_tb,s_ipark_done_tb_dly,s_ipark_done_tb_dly1,m_valpha_tb,m_vbeta_tb,s_valpha_tb,s_vbeta_tb,s_error_valpha_tb,s_error_vbeta_tb,s_counter_error_valpha_tb,s_counter_error_vbeta_tb);

        --iclarke
        ERROR_COMPUTE_3 (s_reset_tb_dly1,sys_clk_tb,s_iclarke_done_tb_dly,s_iclarke_done_tb_dly1,m_va_tb,m_vb_tb,m_vc_tb,s_va_tb,s_vb_tb,s_vc_tb,s_error_va_tb,s_error_vb_tb,s_error_vc_tb,s_counter_error_va_tb,s_counter_error_vb_tb,s_counter_error_vc_tb);
    END PROCESS;
--------------------------------------------------------------------------
-- Name       : COUNT_PROC
-- Description: Counter to decide the number of iterations
--------------------------------------------------------------------------
COUNT_PROC:
    PROCESS(s_reset_tb_dly1,sys_clk_tb)
    BEGIN
        IF(s_reset_tb_dly1 = '0') THEN
            counter <= (OTHERS => '0');
        ELSIF RISING_EDGE (sys_clk_tb) THEN
            IF(state = IND_TEST) THEN
                IF(counter < x"00A") THEN
                    counter <= counter + '1';
                END IF;
            END IF;
        END IF;
    END PROCESS;

--------------------------------------------------------------------------
-- Name       : INPUT_DRIVER_PROC
-- Description: Process to provide the input test vectors
--------------------------------------------------------------------------
INPUT_DRIVER_PROC:
    PROCESS(counter)
    BEGIN
        CASE(counter) IS
        WHEN x"001" =>
            ---------------
            --clarke
            ---------------
            m_ia_tb             <= x"007FE";
            m_ib_tb             <= x"FFC1C";
            ---------------
            --park
            ---------------
            m_ialpha_park_tb    <= x"007FE";
            m_ibeta_park_tb     <= x"0001F";
            ---------------
            --ipark
            ---------------
            m_vd_tb             <= x"007FD";
            m_vq_tb             <= x"FFFFC";
            ---------------
            --iclarke
            ---------------
            m_valpha_iclarke_tb <= x"007FC";
            m_vbeta_iclarke_tb  <= x"00020";

        WHEN x"002" =>
            ---------------
            --clarke
            ---------------
            m_ia_tb             <= x"007FD";
            m_ib_tb             <= x"FFC38";
            ---------------
            --park
            ---------------
            m_ialpha_park_tb    <= x"007FD";
            m_ibeta_park_tb     <= x"0003E";
            ---------------
            --ipark
            ---------------
            m_vd_tb             <= x"007FC";
            m_vq_tb             <= x"FFFFC";
            ---------------
            --iclarke
            ---------------
            m_valpha_iclarke_tb <= x"007FC";
            m_vbeta_iclarke_tb  <= x"0003C";
        WHEN x"003" =>
            --clarke
            m_ia_tb             <= x"007FC";
            m_ib_tb             <= x"FFC55";

            --park
            m_ialpha_park_tb    <= x"007FC";
            m_ibeta_park_tb     <= x"0005F";

            --ipark
            m_vd_tb             <= x"007FD";
            m_vq_tb             <= x"FFFFC";

            --iclarke
            m_valpha_iclarke_tb <= x"007FB";
            m_vbeta_iclarke_tb  <= x"0005E";
        WHEN x"004" =>
            --clarke
            m_ia_tb             <= x"007FA";
            m_ib_tb             <= x"FFC71";

            --park
            m_ialpha_park_tb    <= x"007FA";
            m_ibeta_park_tb     <= x"0007E";

            --ipark
            m_vd_tb             <= x"00800";
            m_vq_tb             <= x"FFFFC";

            --iclarke
            m_valpha_iclarke_tb <= x"007FA";
            m_vbeta_iclarke_tb  <= x"0007E";
        WHEN x"005" =>
            --clarke
            m_ia_tb             <= x"007F8";
            m_ib_tb             <= x"FFC8E";

            --park
            m_ialpha_park_tb    <= x"007F8";
            m_ibeta_park_tb     <= x"0009F";

            --ipark
            m_vd_tb             <= x"007FC";
            m_vq_tb             <= x"FFFF9";

            --iclarke
            m_valpha_iclarke_tb <= x"007F5";
            m_vbeta_iclarke_tb  <= x"0009F";
        WHEN x"006" =>
            --clarke
            m_ia_tb             <= x"007F5";
            m_ib_tb             <= x"FFCAB";
    
            --park
            m_ialpha_park_tb    <= x"007F5";
            m_ibeta_park_tb     <= x"000BF";
    
            --ipark
            m_vd_tb             <= x"007FB";
            m_vq_tb             <= x"FFFF9";
    
            --iclarke
            m_valpha_iclarke_tb <= x"007F3";
            m_vbeta_iclarke_tb  <= x"000BE";
        WHEN x"007" =>
            --clarke
            m_ia_tb             <= x"007F2";
            m_ib_tb             <= x"FFCC9";

            --park
            m_ialpha_park_tb    <= x"007F2";
            m_ibeta_park_tb     <= x"000DF";

            --ipark
            m_vd_tb             <= x"007FD";
            m_vq_tb             <= x"FFFFB";

            --iclarke
            m_valpha_iclarke_tb <= x"007F1";
            m_vbeta_iclarke_tb  <= x"000DF";
        WHEN x"008" =>
            --clarke
            m_ia_tb             <= x"007EE";
            m_ib_tb             <= x"FFCE6";

            --park
            m_ialpha_park_tb    <= x"007EE";
            m_ibeta_park_tb     <= x"000FF";

            --ipark
            m_vd_tb             <= x"007FF";
            m_vq_tb             <= x"FFFFB";

            --iclarke
            m_valpha_iclarke_tb <= x"007ED";
            m_vbeta_iclarke_tb  <= x"00100";
        WHEN x"009" =>
            --clarke
            m_ia_tb             <= x"007EA";
            m_ib_tb             <= x"FFD04";

            --park
            m_ialpha_park_tb    <= x"007EA";
            m_ibeta_park_tb     <= x"0011F";

            --ipark
            m_vd_tb             <= x"007FF";
            m_vq_tb             <= x"FFFFB";

            --iclarke
            m_valpha_iclarke_tb <= x"007E7";
            m_vbeta_iclarke_tb  <= x"0011F";
        WHEN x"00A" =>
            --clarke
            m_ia_tb             <= x"007E5";
            m_ib_tb             <= x"FFD22";

            --park
            m_ialpha_park_tb    <= x"007E5";
            m_ibeta_park_tb     <= x"0013F";

            --ipark
            m_vd_tb             <= x"007FC";
            m_vq_tb             <= x"FFFFC";

            --iclarke
            m_valpha_iclarke_tb <= x"007E6";
            m_vbeta_iclarke_tb  <= x"00140";
        WHEN OTHERS =>
            --clarke
            m_ia_tb             <= x"0FFF7";
            m_ib_tb             <= x"F837F";

            --park
            m_ialpha_park_tb    <= x"0FFF7";
            m_ibeta_park_tb     <= x"F837F";

            --ipark
            m_vd_tb             <= x"0FFF7";
            m_vq_tb             <= x"F837F";

            --iclarke
            m_valpha_iclarke_tb <= x"0FFF7";
            m_vbeta_iclarke_tb  <= x"F837F";
        END CASE;
    END PROCESS;
--------------------------------------------------------------------------
-- Name       : OUTPUT_DATA_COMPARE_PROC
-- Description: Process to provide the output comapre values
--------------------------------------------------------------------------
OUTPUT_DATA_COMPARE_PROC:
    PROCESS(counter)
    BEGIN
        CASE (counter) IS
        WHEN x"001" =>
        --clarke
            m_ialpha_tb         <= x"007FE";
            m_ibeta_tb          <= x"0001F";
        --park
            m_id_tb             <= x"007FD";
            m_iq_tb             <= x"FFFFC";
            m_theta_tb          <= x"0028F";
        --ipark
            m_valpha_tb         <= x"007FC";
            m_vbeta_tb          <= x"0001E";
        --iclarke
            m_va_tb             <= x"007FC";
            m_vb_tb             <= x"FFC1D";
            m_vc_tb             <= x"FFBE6";
        WHEN x"002" =>
        --clarke
            m_ialpha_tb         <= x"007FD";
            m_ibeta_tb          <= x"0003E";
        --park
            m_id_tb             <= x"007FC";
            m_iq_tb             <= x"FFFFC";
            m_theta_tb          <= x"0051E";
        --ipark
            m_valpha_tb         <= x"007FC";
            m_vbeta_tb          <= x"0003D";
        --iclarke
            m_va_tb             <= x"007FC";
            m_vb_tb             <= x"FFC35";
            m_vc_tb             <= x"FFBCE";
        WHEN x"003" =>
        --clarke
            m_ialpha_tb         <= x"007FC";
            m_ibeta_tb          <= x"0005f";
        --park
            m_id_tb             <= x"007FD";
            m_iq_tb             <= x"FFFFC";
            m_theta_tb          <= x"007AE";
        --ipark
            m_valpha_tb         <= x"007FA";
            m_vbeta_tb          <= x"0005D";
        --iclarke
            m_va_tb             <= x"007FB";
            m_vb_tb             <= x"FFC53";
            m_vc_tb             <= x"FFBB1";

        WHEN x"004" =>
        --clarke
            m_ialpha_tb         <= x"007FA";
            m_ibeta_tb          <= x"0007E";
        --park
            m_id_tb             <= x"00800";
            m_iq_tb             <= x"FFFFC";
            m_theta_tb          <= x"00A3D";
        --ipark
            m_valpha_tb         <= x"007FD";
            m_vbeta_tb          <= x"0007B";
        --iclarke
            m_va_tb             <= x"007FA";
            m_vb_tb             <= x"FFC70";
            m_vc_tb             <= x"FFB95";
        WHEN x"005" =>
        --clarke
            m_ialpha_tb         <= x"007F8";
            m_ibeta_tb          <= x"0009F";
        --park
            m_id_tb             <= x"007FC";
            m_iq_tb             <= x"FFFF9";
            m_theta_tb          <= x"00CCC";
        --ipark
            m_valpha_tb         <= x"007F4";
            m_vbeta_tb          <= x"0009B";
        --iclarke
            m_va_tb             <= x"007F5";
            m_vb_tb             <= x"FFC8F";
            m_vc_tb             <= x"FFB7B";
        WHEN x"006" =>
        --clarke
            m_ialpha_tb         <= x"007F5";
            m_ibeta_tb          <= x"000BF";
        --park
            m_id_tb             <= x"007FB";
            m_iq_tb             <= x"FFFF9";
            m_theta_tb          <= x"00F5C";
        --ipark
            m_valpha_tb         <= x"007EF";
            m_vbeta_tb          <= x"000BB";
        --iclarke
            m_va_tb             <= x"007F3";
            m_vb_tb             <= x"FFCAB";
            m_vc_tb             <= x"FFB61";
        WHEN x"007" =>
        --clarke
            m_ialpha_tb         <= x"007F2";
            m_ibeta_tb          <= x"000DF";
        --park
            m_id_tb             <= x"007FD";
            m_iq_tb             <= x"FFFFB";
            m_theta_tb          <= x"011EB";
        --ipark
            m_valpha_tb         <= x"007EE";
            m_vbeta_tb          <= x"000DD";
        --iclarke
            m_va_tb             <= x"007F1";
            m_vb_tb             <= x"FFCC8";
            m_vc_tb             <= x"FFB46";
        WHEN x"008" =>
        --clarke
            m_ialpha_tb         <= x"007EE";
            m_ibeta_tb          <= x"000FF";
        --park
            m_id_tb             <= x"007FF";
            m_iq_tb             <= x"FFFFB";
            m_theta_tb          <= x"0147A";
        --ipark
            m_valpha_tb         <= x"007EE";
            m_vbeta_tb          <= x"000FB";
        --iclarke
            m_va_tb             <= x"007ED";
            m_vb_tb             <= x"FFCE7";
            m_vc_tb             <= x"FFB2B";
        WHEN x"009" =>
        --clarke
            m_ialpha_tb         <= x"007EA";
            m_ibeta_tb          <= x"0011F";
        --park
            m_id_tb             <= x"007FF";
            m_iq_tb             <= x"FFFFB";
            m_theta_tb          <= x"0170A";
        --ipark
            m_valpha_tb         <= x"007E6";
            m_vbeta_tb          <= x"0011C";
        --iclarke
            m_va_tb             <= x"007E7";
            m_vb_tb             <= x"FFD05";
            m_vc_tb             <= x"FFB13";
        WHEN x"00A" =>
        --clarke
            m_ialpha_tb         <= x"007E5";
            m_ibeta_tb          <= x"0013F";
        --park
            m_id_tb             <= x"007FC";
            m_iq_tb             <= x"FFFFC";
            m_theta_tb          <= x"01999";
        --ipark
            m_valpha_tb         <= x"007E3";
            m_vbeta_tb          <= x"0013D";
        --iclarke
            m_va_tb             <= x"007E6";
            m_vb_tb             <= x"FFD22";
            m_vc_tb             <= x"FFAF7";
        WHEN OTHERS =>
        --clarke
            m_ialpha_tb         <= x"00000";
            m_ibeta_tb          <= x"00000";
        --park
            m_id_tb             <= x"00000";
            m_iq_tb             <= x"00000";
            m_theta_tb          <= x"00000";
        --ipark
            m_valpha_tb         <= x"00000";
            m_vbeta_tb          <= x"00000";
        --iclarke
            m_va_tb             <= x"00000";
            m_vb_tb             <= x"00000";
            m_vc_tb             <= x"00000";
        END CASE;
    END PROCESS;

--=================================================================================================
-- Component Instantiations
--=================================================================================================
-------------------------------------------------
-- FOC_TRANSFORMS_UUT_INST
-------------------------------------------------
FOC_TRANSFORMS_UUT_INST: FOC_transforms
PORT MAP(
	reset_i                            => s_reset_tb_dly1,
	sys_clk_i                          => sys_clk_tb,
	start_clarke_i                     => s_start_tb_dly,
    start_park_i                       => s_clarke_done_tb_dly,
    start_ipark_i                      => s_park_done_tb_dly,
    start_iclarke_i                    => s_ipark_done_tb_dly,
	ia_i                          	   => m_ia_tb(17 DOWNTO 0),
	ib_i                          	   => m_ib_tb(17 DOWNTO 0),
	ialpha_i               			   => m_ialpha_park_tb(17 DOWNTO 0),
	ibeta_i                			   => m_ibeta_park_tb(17 DOWNTO 0),
	vd_i                   			   => m_vd_tb(17 DOWNTO 0),
	vq_i                   			   => m_vq_tb(17 DOWNTO 0),
	valpha_i                   		   => m_valpha_iclarke_tb(17 DOWNTO 0),
	vbeta_i                    		   => m_vbeta_iclarke_tb(17 DOWNTO 0),
	theta_i                    		   => m_theta_tb(17 DOWNTO 0),
    clarke_done_o                      => s_clarke_done_tb,
    park_done_o                        => s_park_done_tb,
    ipark_done_o                       => s_ipark_done_tb,
    iclarke_done_o                     => s_iclarke_done_tb,
    ialpha_o             			   => s_ialpha_tb,
	ibeta_o              			   => s_ibeta_tb,
	id_o                   			   => s_id_tb,
	iq_o                   			   => s_iq_tb,
	valpha_o              	    	   => s_valpha_tb,
	vbeta_o               			   => s_vbeta_tb,
	va_o                        	   => s_va_tb,
	vb_o                        	   => s_vb_tb,
	vc_o                        	   => s_vc_tb
);
END behavioral;