//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
//--           		     Actel Corporation           		      --
//--                             www.actel.com				      --
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
// Verilog HDL Design :  NAND FLASH Controller                                //
//         Design     :  ACTEL NAND FLASH IP                                  //
//         File name  :  nand_interface_core.v                                     //
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Description: The commands from the processor arrive at the inputs of the   //
// NAND Flash interface (i.e, this module) in coded form. Each operation      //
// to be performed is coded in a different format and coming through the 3-bit//
// wide control bus. The pin descriptions for the interface are given below.  //
// Enabling or disabling (in the case of ALE, CLE, SE, and WE) is done        //
// separately with the help of enable/disable signal inputs. These commands   //
// are decoded correctly by the NAND Flash interface block and translated as  //
// output enabling or disabling signals, which ensures the desired operation  //
// of the NAND Flash. The actual operation performed by a NAND Flash is       //
// governed by the commands written into its command register through the I/O //
// bus. The address of the data that is read or written, together with the    //
// data, are issued through the same bus.						      //
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
//-- Modification History                                                       --
//--                                                                            --
//-- Initial revision                                                           --
//--                                                                            --
//-- Revision 1.0                                                               --

//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
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////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//                               Module                                       //
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ns 
module nand_interface_core (//Write Enable signal generated by the host for the interface
                       h_wr, 
                       //Control signal generated by the host to determine which function 
                       //the interface will currently perform        
                       h_cntrl, 
                       //Enable-Disable signal generated by the host       
                       e_d, 
                       // System Clock
                       clk,          
                       //Active low Reset signal aborts the current operation and resets all the control siganls
                       nreset,         
                       //Chip enable,it controls the active vs standby mode of the device 
                       ce_n,            
                       //Read enable,it controls the data and status output on the I/O lines
                       re_n,            
                       //Address latch enable,it controls the writing to the address register 
                       ale,           
                       //Command latch enable,it controls the writing to the command register
                       cle,         
                       //Spare area enable,it controls the access to the 16 byte of spare area on each page
                       se_n,            
                       //Write enable,it controls the data and command on the I/O lines during a write sequence
                       we_n,           
                       //Write protect,it provides the protection when programming or erasing the device 
                       wp_n            
                       );

input h_wr,clk,nreset,e_d; 
input [2:0] h_cntrl;

output ce_n,re_n,ale;
output cle,se_n,we_n,wp_n;


////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//                         A R C H I T E C T U R E                            //
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////


wire n_ce,n_wp,n_ale,n_se, rew, wew, we_sig, n_cle ;
reg int_ce,int_wp,int_ale,int_se, res, wes, int_1ale, int_cle;
					    
/* multiplexed bus on which command or data is put */

wire decod0,decod1,decod2,decod3,decod4,decod5,decod6,decod7;

// command latch enable
assign decod0 = ((~h_cntrl[2]) & (~h_cntrl[1]) & (~h_cntrl[0])); 

// read data or device id 
assign decod1 = ((~h_cntrl[2]) & (~h_cntrl[1]) & (h_cntrl[0]));

 // write data or command  
assign decod2 = ((~h_cntrl[2]) & (h_cntrl[1]) & (~h_cntrl[0]));  

 // address latch enable   
assign decod3 = ((~h_cntrl[2]) & (h_cntrl[1]) & (h_cntrl[0]));

// spare area enable        
assign decod4 = ((h_cntrl[2])& (~h_cntrl[1]) & (~h_cntrl[0]));

// write protect enable      
assign decod5 = ((h_cntrl[2]) & (~h_cntrl[1]) & (h_cntrl[0]));

 // chip enable         
assign decod6 = ((h_cntrl[2]) & (h_cntrl[1]) & (~h_cntrl[0]));        

 // ready_busy
assign decod7 = ((h_cntrl[2]) & (h_cntrl[1]) & (h_cntrl[0]));           
 

always @(posedge clk) 
begin   
   if (~nreset)begin
        int_ale <= 1'b0;
    end else if (decod3)begin
        case (e_d)
            1'b0 : int_ale <= 1'b0;					
            1'b1 : int_ale <= 1'b1;
	    endcase
	end
    else 
    begin
	    int_ale <= 1'b0;
    end

end

// Process to generate se (Spare area enable) 
always @(posedge clk) 
begin  
    if (~nreset) begin
        int_se <= 1'b1;
    end else if (decod4)begin
        case (e_d)
            1'b0 : int_se <= 1'b1;					
            1'b1 : int_se <= 1'b0;
	    endcase
	end
   else 
    begin
	int_se <= 1'b1 ;
    end
end

// Process to generate wp (Write protect) 
always @(posedge clk) 
begin 
    if (~nreset)begin
        int_wp <= 1'b1;
    end else if (decod5)begin
        case (e_d)
            1'b0 : int_wp <= 1'b1;					
            1'b1 : int_wp <= 1'b0;
	    endcase
	end
   else 
    begin
	int_wp <= 1'b1 ;
    end

end

// Process to generate ce (chip enable) 
always @(posedge clk)
begin 
    if (~nreset)begin
        int_ce <= 1'b1;
    end else if (decod6)begin
        case (e_d)
            1'b0 : int_ce <= 1'b1;					
            1'b1 : int_ce <= 1'b0;
	
	    endcase
    end
    else if (decod0 && e_d)begin
        int_ce <= 1'b1;
    end
end


always @(posedge clk)
begin 
    if (~nreset)begin
        wes <= 1'b1;
    end else if ((decod2) || (decod3) || (decod7)) begin 
        case (e_d)
            1'b0 : wes <= 1'b1;					
            1'b1 : wes <= h_wr;
	    endcase
	end
    else 
    begin
	    wes <= 1'b1;
    end
	
end

//always @(posedge clk)
//begin 
//    if (~nreset)begin
//        res <= 1'b1;
//    end else if (decod1) begin 
//        case (e_d)
//            1'b0 : res <= 1'b1;					
//            1'b1 : res <= h_wr;
//	    endcase
//	end
//    else 
//    begin
//	    res <= 1'b1;
//    end
//	
//end

always @(posedge clk)
begin 
    if (~nreset)begin
        int_cle <= 1'b0;
    end else begin 
           int_cle <= decod7;
	end
	
end

////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// nand_interface output signals                                              //
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
assign n_ce = int_ce;
assign n_wp = int_wp;
assign n_ale = int_ale;
assign n_se = int_se;

assign ce_n = n_ce;
assign wp_n = n_wp;
assign ale = n_ale;
assign se_n = n_se;

assign n_cle = int_cle;
assign cle = n_cle;

assign rew = ~decod1 ;
//assign rew = res;
assign wew = wes;

assign re_n = rew;
assign we_n = wew;

endmodule
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//                               END OF FILE                                  //
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////