
/*************************************************************************************
 * NandFlash
 *
 *Dexcel Electronics Designs PVT Ltd
 *
 * - File              : Nandflash.h
 *
 * Description		   : contains Macros & Global variables for Nand Flash IP core
 *
 * (C) Copyright 2008 Dexcel Electronics Designs PVT Ltd.
 * $Revision: 0.4 $
 * $Date: Tuesday, December 08 2008 
 ************************************************************************************/


#ifndef HEADER_H_
#define HEADER_H_

/*
 * 	Defines instruction opcodes
 */
#define NAND_CMD_PAGE_READ_CYCLE1 0x00
#define	NAND_CMD_PAGE_READ_CYCLE2 0x30
#define NAND_CMD_READ_DATA_MOVE 0x35
#define NAND_CMD_RESET 0xFF
#define	NAND_CMD_PAGE_PROGRAM_CYCLE1 0x80
#define NAND_CMD_PAGE_PROGRAM_CYCLE2 0x10
#define NAND_CMD_CACHE_PRGM_CONFIRM 0x15
#define NAND_CMD_PRGM_DATA_MOVE	0x85
#define NAND_CMD_BLOCK_ERASE_CYCLE1 0x60
#define NAND_CMD_BLOCK_ERASE_CYCLE2 0xD0
#define NAND_CMD_RANDOM_DATA_INPUT 0x85
#define NAND_CMD_RANDOM_DATA_READ_CYCLE1	0x05
#define NAND_CMD_RANDOM_DATA_READ_CYCLE2	0xE0
#define NAND_CMD_READ_STATUS 0x70
#define NAND_CMD_READ_CACHE_START 0x31
#define NAND_CMD_READ_CACHE_LAST 0X3F
#define NAND_CMD_READ_UNIQUE_ID 0x65


/*
 * 	Defines Maximum read status retry count
 */
#define MAX_READ_STATUS_COUNT 100000


/*
 * 	Defines NAND status bit mask
 */
#define STATUS_BIT_0 0x01
#define STATUS_BIT_1 0x02
#define STATUS_BIT_5 0x20
#define STATUS_BIT_6 0x40

/*
 * 	Defines NAND status status response
 */
#define NAND_IO_RC_PASS 0
#define NAND_IO_RC_FAIL 1
#define NAND_IO_RC_TIMEOUT 2

/*
 * 	Defines NAND device information 
 */
#define NAND_PAGE_SIZE_BYTE 2112
#define NAND_PAGE_COUNT_PER_BLOCK 64
#define NAND_BLOCK_COUNT 2048


/*
 * 	Defines Address for  Addr and Command Register Macros
 */
#define CLE_OFFSET 0x0007	/*The offset value is for command Register */
#define ALE_OFFSET 0x0003  /*The offset value is for Address Register */
#define RD_OFFSET  0x0001  /*The offset value is for Read Register */
#define WR_OFFSET  0x0002  /*The offset value is for Write Register */
#define CE_OFFSET  0x0006	/*The offset value for chip enable*/
#define GPIO_STATUS	0x0100  /*The offset value to check for R/B signal*/

/*
 * Declares External Global Variables for Addr and Command  Registers
 */
unsigned char xdata *Gpio_Port=(unsigned char xdata *)GPIO_STATUS;
unsigned char xdata *Cle_Offset=(unsigned char xdata *)CLE_OFFSET;
unsigned char xdata *Ale_Offset=(unsigned char xdata *)ALE_OFFSET;
unsigned char xdata *Rd_Offset=(unsigned char xdata *)RD_OFFSET;
unsigned char xdata *Wr_Offset=(unsigned char xdata *)WR_OFFSET;
unsigned char xdata *Ce_Offset=(unsigned char xdata *)CE_OFFSET;

/*
 * Declares Macro for writing Addr & Command to the output port and Reading Data from the input port
 */

#define NAND_WRITE_CMD(Command) 	*(Cle_Offset)=Command		//writes command onto command register
#define NAND_WRITE_ADDR(Command)    *(Ale_Offset)=Command		//writes Addr onto Addr register
#define NAND_READ_DATA(Datum)       (*(Datum)=*(Rd_Offset))		//Reads Data from the Data register
#define NAND_WRITE_DATA(Command)    *(Wr_Offset)=Command		//writes Data onto the data register
#define NAND_WRITE_CE(Command)      *(Ce_Offset)=Command		//writes Chip enable register

/*
 * Function Declaration
 */
int NAND_Reset(void);

void putw(unsigned short );
int NAND_EraseBlock(unsigned long a_uiBlockNum);

int NAND_EraseBlock(unsigned long);

int NAND_ReadPage(
	unsigned long a_uiPageNum,
	unsigned short a_usColNum,
	unsigned short a_usReadSizeByte,
	unsigned char *a_pucReadBuf);

int NAND_ProgramPage(
	unsigned long a_uiPageNum,
	unsigned short a_usColNum,
	unsigned short a_usReadSizeByte,
	unsigned char *a_pucReadBuf);


unsigned char counter;
unsigned char Data_Rd, Data_Type,Data_Rcv;
unsigned long Block_No;
unsigned char Count_flag;



#endif /*HEADER_H_*/
