`timescale 1 ns/100 ps
// Version: 8.3 8.3.0.22


module Ram256x8(WD,RD,WEN,REN,WADDR,RADDR,WCLK,RCLK);
input [7:0] WD;
output [7:0] RD;
input  WEN, REN;
input [7:0] WADDR, RADDR;
input WCLK, RCLK;

    wire WEAP, WEBP, VCC, GND;
    
    VCC VCC_1_net(.Y(VCC));
    GND GND_1_net(.Y(GND));
    INV WEBUBBLEB(.A(REN), .Y(WEBP));
    RAM4K9 Ram256x8_R0C0(.ADDRA11(GND), .ADDRA10(GND), .ADDRA9(
        GND), .ADDRA8(GND), .ADDRA7(WADDR[7]), .ADDRA6(WADDR[6]), 
        .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]), .ADDRA3(WADDR[3]), 
        .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]), .ADDRA0(WADDR[0]), 
        .ADDRB11(GND), .ADDRB10(GND), .ADDRB9(GND), .ADDRB8(GND), 
        .ADDRB7(RADDR[7]), .ADDRB6(RADDR[6]), .ADDRB5(RADDR[5]), 
        .ADDRB4(RADDR[4]), .ADDRB3(RADDR[3]), .ADDRB2(RADDR[2]), 
        .ADDRB1(RADDR[1]), .ADDRB0(RADDR[0]), .DINA8(GND), .DINA7(
        WD[7]), .DINA6(WD[6]), .DINA5(WD[5]), .DINA4(WD[4]), 
        .DINA3(WD[3]), .DINA2(WD[2]), .DINA1(WD[1]), .DINA0(WD[0])
        , .DINB8(GND), .DINB7(GND), .DINB6(GND), .DINB5(GND), 
        .DINB4(GND), .DINB3(GND), .DINB2(GND), .DINB1(GND), 
        .DINB0(GND), .WIDTHA0(VCC), .WIDTHA1(VCC), .WIDTHB0(VCC), 
        .WIDTHB1(VCC), .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), 
        .WMODEB(GND), .BLKA(WEAP), .BLKB(WEBP), .WENA(GND), .WENB(
        VCC), .CLKA(WCLK), .CLKB(RCLK), .RESET(VCC), .DOUTA8(), 
        .DOUTA7(), .DOUTA6(), .DOUTA5(), .DOUTA4(), .DOUTA3(), 
        .DOUTA2(), .DOUTA1(), .DOUTA0(), .DOUTB8(), .DOUTB7(RD[7])
        , .DOUTB6(RD[6]), .DOUTB5(RD[5]), .DOUTB4(RD[4]), .DOUTB3(
        RD[3]), .DOUTB2(RD[2]), .DOUTB1(RD[1]), .DOUTB0(RD[0]));
    INV WEBUBBLEA(.A(WEN), .Y(WEAP));
    
endmodule

// _Disclaimer: Please leave the following comments in the file, they are for internal purposes only._


// _GEN_File_Contents_

// Version:8.3.0.22
// ACTGENU_CALL:1
// BATCH:T
// FAM:IGLOO
// OUTFORMAT:Verilog
// LPMTYPE:LPM_RAM
// LPM_HINT:TWO
// INSERT_PAD:NO
// INSERT_IOREG:NO
// GEN_BHV_VHDL_VAL:F
// GEN_BHV_VERILOG_VAL:F
// MGNTIMER:F
// MGNCMPL:T
// "DESDIR:D:/actel_ip/nand flash controller/1dec/with_uart_without_leds/nand_flash_interface/smartgen\Ram256x8"
// GEN_BEHV_MODULE:T
// SMARTGEN_DIE:M1IS6X6M2LPLV
// SMARTGEN_PACKAGE:fg484
// WWIDTH:8
// WDEPTH:256
// RWIDTH:8
// RDEPTH:256
// CLKS:2
// RESET_POLARITY:2
// INIT_RAM:F
// DEFAULT_WORD:0x00
// WCLK_EDGE:RISE
// RCLK_EDGE:RISE
// WCLOCK_PN:WCLK
// RCLOCK_PN:RCLK
// PMODE2:0
// DATA_IN_PN:WD
// WADDRESS_PN:WADDR
// WE_PN:WEN
// DATA_OUT_PN:RD
// RADDRESS_PN:RADDR
// RE_PN:REN
// WE_POLARITY:1
// RE_POLARITY:1
// PTYPE:1

// _End_Comments_

