-- Version: 8.3 8.3.0.22

library ieee;
use ieee.std_logic_1164.all;
library igloo;
use igloo.all;

entity Ram5kx8 is 
    port( WD : in std_logic_vector(7 downto 0); RD : out 
        std_logic_vector(7 downto 0);WEN, REN : in std_logic; 
        WADDR : in std_logic_vector(12 downto 0); RADDR : in 
        std_logic_vector(12 downto 0);WCLK, RCLK : in std_logic
        ) ;
end Ram5kx8;


architecture DEF_ARCH of  Ram5kx8 is

    component MX2
        port(A, B, S : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component RAM4K9
    generic (MEMORYFILE:string := "");

        port(ADDRA11, ADDRA10, ADDRA9, ADDRA8, ADDRA7, ADDRA6, 
        ADDRA5, ADDRA4, ADDRA3, ADDRA2, ADDRA1, ADDRA0, ADDRB11, 
        ADDRB10, ADDRB9, ADDRB8, ADDRB7, ADDRB6, ADDRB5, ADDRB4, 
        ADDRB3, ADDRB2, ADDRB1, ADDRB0, DINA8, DINA7, DINA6, 
        DINA5, DINA4, DINA3, DINA2, DINA1, DINA0, DINB8, DINB7, 
        DINB6, DINB5, DINB4, DINB3, DINB2, DINB1, DINB0, WIDTHA0, 
        WIDTHA1, WIDTHB0, WIDTHB1, PIPEA, PIPEB, WMODEA, WMODEB, 
        BLKA, BLKB, WENA, WENB, CLKA, CLKB, RESET : in std_logic := 
        'U'; DOUTA8, DOUTA7, DOUTA6, DOUTA5, DOUTA4, DOUTA3, 
        DOUTA2, DOUTA1, DOUTA0, DOUTB8, DOUTB7, DOUTB6, DOUTB5, 
        DOUTB4, DOUTB3, DOUTB2, DOUTB1, DOUTB0 : out std_logic) ;
    end component;

    component NAND3B
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component NAND3A
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component OR2
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component DFN1
        port(D, CLK : in std_logic := 'U'; Q : out std_logic) ;
    end component;

    component INV
        port(A : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component NAND3C
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component VCC
        port( Y : out std_logic);
    end component;

    component GND
        port( Y : out std_logic);
    end component;

    signal WEAP, WEBP, ADDRA_FF2_0_net, ADDRA_FF2_1_net, 
        ADDRA_FF2_2_net, ADDRB_FF2_0_net, ADDRB_FF2_1_net, 
        ADDRB_FF2_2_net, ENABLE_ADDRA_0_net, ENABLE_ADDRA_1_net, 
        ENABLE_ADDRA_2_net, ENABLE_ADDRA_3_net, 
        ENABLE_ADDRA_4_net, ENABLE_ADDRB_0_net, 
        ENABLE_ADDRB_1_net, ENABLE_ADDRB_2_net, 
        ENABLE_ADDRB_3_net, ENABLE_ADDRB_4_net, BLKA_EN_0_net, 
        BLKB_EN_0_net, BLKA_EN_1_net, BLKB_EN_1_net, 
        BLKA_EN_2_net, BLKB_EN_2_net, BLKA_EN_3_net, 
        BLKB_EN_3_net, BLKA_EN_4_net, BLKB_EN_4_net, 
        QX_TEMPR0_0_net, QX_TEMPR0_1_net, QX_TEMPR0_2_net, 
        QX_TEMPR0_3_net, QX_TEMPR1_0_net, QX_TEMPR1_1_net, 
        QX_TEMPR1_2_net, QX_TEMPR1_3_net, QX_TEMPR2_0_net, 
        QX_TEMPR2_1_net, QX_TEMPR2_2_net, QX_TEMPR2_3_net, 
        QX_TEMPR3_0_net, QX_TEMPR3_1_net, QX_TEMPR3_2_net, 
        QX_TEMPR3_3_net, QX_TEMPR4_0_net, QX_TEMPR4_1_net, 
        QX_TEMPR4_2_net, QX_TEMPR4_3_net, QX_TEMPR0_4_net, 
        QX_TEMPR0_5_net, QX_TEMPR0_6_net, QX_TEMPR0_7_net, 
        QX_TEMPR1_4_net, QX_TEMPR1_5_net, QX_TEMPR1_6_net, 
        QX_TEMPR1_7_net, QX_TEMPR2_4_net, QX_TEMPR2_5_net, 
        QX_TEMPR2_6_net, QX_TEMPR2_7_net, QX_TEMPR3_4_net, 
        QX_TEMPR3_5_net, QX_TEMPR3_6_net, QX_TEMPR3_7_net, 
        QX_TEMPR4_4_net, QX_TEMPR4_5_net, QX_TEMPR4_6_net, 
        QX_TEMPR4_7_net, MX2_4_Y, MX2_6_Y, MX2_17_Y, MX2_1_Y, 
        MX2_9_Y, MX2_2_Y, MX2_14_Y, MX2_13_Y, MX2_18_Y, MX2_23_Y, 
        MX2_11_Y, MX2_21_Y, MX2_7_Y, MX2_8_Y, MX2_19_Y, MX2_3_Y, 
        MX2_10_Y, MX2_5_Y, MX2_16_Y, MX2_15_Y, MX2_20_Y, MX2_0_Y, 
        MX2_12_Y, MX2_22_Y, VCC_1_net, GND_1_net : std_logic ;
    begin   

    VCC_2_net : VCC port map(Y => VCC_1_net);
    GND_2_net : GND port map(Y => GND_1_net);
    MX2_18 : MX2
      port map(A => MX2_14_Y, B => MX2_13_Y, S => ADDRB_FF2_1_net, 
        Y => MX2_18_Y);
    MX2_12 : MX2
      port map(A => QX_TEMPR2_5_net, B => QX_TEMPR3_5_net, S => 
        ADDRB_FF2_0_net, Y => MX2_12_Y);
    Ram5kx8_R2C1 : RAM4K9
      port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net, 
        ADDRA9 => WADDR(9), ADDRA8 => WADDR(8), ADDRA7 => 
        WADDR(7), ADDRA6 => WADDR(6), ADDRA5 => WADDR(5), 
        ADDRA4 => WADDR(4), ADDRA3 => WADDR(3), ADDRA2 => 
        WADDR(2), ADDRA1 => WADDR(1), ADDRA0 => WADDR(0), 
        ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 => 
        RADDR(9), ADDRB8 => RADDR(8), ADDRB7 => RADDR(7), 
        ADDRB6 => RADDR(6), ADDRB5 => RADDR(5), ADDRB4 => 
        RADDR(4), ADDRB3 => RADDR(3), ADDRB2 => RADDR(2), 
        ADDRB1 => RADDR(1), ADDRB0 => RADDR(0), DINA8 => 
        GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net, 
        DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => WD(7), 
        DINA2 => WD(6), DINA1 => WD(5), DINA0 => WD(4), DINB8 => 
        GND_1_net, DINB7 => GND_1_net, DINB6 => GND_1_net, 
        DINB5 => GND_1_net, DINB4 => GND_1_net, DINB3 => 
        GND_1_net, DINB2 => GND_1_net, DINB1 => GND_1_net, 
        DINB0 => GND_1_net, WIDTHA0 => GND_1_net, WIDTHA1 => 
        VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net, 
        PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA => 
        GND_1_net, WMODEB => GND_1_net, BLKA => BLKA_EN_2_net, 
        BLKB => BLKB_EN_2_net, WENA => GND_1_net, WENB => 
        VCC_1_net, CLKA => WCLK, CLKB => RCLK, RESET => VCC_1_net, 
        DOUTA8 => OPEN , DOUTA7 => OPEN , DOUTA6 => OPEN , 
        DOUTA5 => OPEN , DOUTA4 => OPEN , DOUTA3 => OPEN , 
        DOUTA2 => OPEN , DOUTA1 => OPEN , DOUTA0 => OPEN , 
        DOUTB8 => OPEN , DOUTB7 => OPEN , DOUTB6 => OPEN , 
        DOUTB5 => OPEN , DOUTB4 => OPEN , DOUTB3 => 
        QX_TEMPR2_7_net, DOUTB2 => QX_TEMPR2_6_net, DOUTB1 => 
        QX_TEMPR2_5_net, DOUTB0 => QX_TEMPR2_4_net);
    MX2_10 : MX2
      port map(A => QX_TEMPR2_6_net, B => QX_TEMPR3_6_net, S => 
        ADDRB_FF2_0_net, Y => MX2_10_Y);
    MX2_7 : MX2
      port map(A => QX_TEMPR0_7_net, B => QX_TEMPR1_7_net, S => 
        ADDRB_FF2_0_net, Y => MX2_7_Y);
    MX2_15 : MX2
      port map(A => QX_TEMPR2_4_net, B => QX_TEMPR3_4_net, S => 
        ADDRB_FF2_0_net, Y => MX2_15_Y);
    Ram5kx8_R0C0 : RAM4K9
      port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net, 
        ADDRA9 => WADDR(9), ADDRA8 => WADDR(8), ADDRA7 => 
        WADDR(7), ADDRA6 => WADDR(6), ADDRA5 => WADDR(5), 
        ADDRA4 => WADDR(4), ADDRA3 => WADDR(3), ADDRA2 => 
        WADDR(2), ADDRA1 => WADDR(1), ADDRA0 => WADDR(0), 
        ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 => 
        RADDR(9), ADDRB8 => RADDR(8), ADDRB7 => RADDR(7), 
        ADDRB6 => RADDR(6), ADDRB5 => RADDR(5), ADDRB4 => 
        RADDR(4), ADDRB3 => RADDR(3), ADDRB2 => RADDR(2), 
        ADDRB1 => RADDR(1), ADDRB0 => RADDR(0), DINA8 => 
        GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net, 
        DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => WD(3), 
        DINA2 => WD(2), DINA1 => WD(1), DINA0 => WD(0), DINB8 => 
        GND_1_net, DINB7 => GND_1_net, DINB6 => GND_1_net, 
        DINB5 => GND_1_net, DINB4 => GND_1_net, DINB3 => 
        GND_1_net, DINB2 => GND_1_net, DINB1 => GND_1_net, 
        DINB0 => GND_1_net, WIDTHA0 => GND_1_net, WIDTHA1 => 
        VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net, 
        PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA => 
        GND_1_net, WMODEB => GND_1_net, BLKA => BLKA_EN_0_net, 
        BLKB => BLKB_EN_0_net, WENA => GND_1_net, WENB => 
        VCC_1_net, CLKA => WCLK, CLKB => RCLK, RESET => VCC_1_net, 
        DOUTA8 => OPEN , DOUTA7 => OPEN , DOUTA6 => OPEN , 
        DOUTA5 => OPEN , DOUTA4 => OPEN , DOUTA3 => OPEN , 
        DOUTA2 => OPEN , DOUTA1 => OPEN , DOUTA0 => OPEN , 
        DOUTB8 => OPEN , DOUTB7 => OPEN , DOUTB6 => OPEN , 
        DOUTB5 => OPEN , DOUTB4 => OPEN , DOUTB3 => 
        QX_TEMPR0_3_net, DOUTB2 => QX_TEMPR0_2_net, DOUTB1 => 
        QX_TEMPR0_1_net, DOUTB0 => QX_TEMPR0_0_net);
    NAND3B_ENABLE_ADDRA_2_inst : NAND3B
      port map(A => WADDR(12), B => WADDR(10), C => WADDR(11), 
        Y => ENABLE_ADDRA_2_net);
    NAND3B_ENABLE_ADDRA_4_inst : NAND3B
      port map(A => WADDR(10), B => WADDR(11), C => WADDR(12), 
        Y => ENABLE_ADDRA_4_net);
    NAND3A_ENABLE_ADDRA_3_inst : NAND3A
      port map(A => WADDR(12), B => WADDR(11), C => WADDR(10), 
        Y => ENABLE_ADDRA_3_net);
    NAND3B_ENABLE_ADDRB_1_inst : NAND3B
      port map(A => RADDR(12), B => RADDR(11), C => RADDR(10), 
        Y => ENABLE_ADDRB_1_net);
    MX2_RD_3_inst : MX2
      port map(A => MX2_17_Y, B => QX_TEMPR4_3_net, S => 
        ADDRB_FF2_2_net, Y => RD(3));
    Ram5kx8_R1C1 : RAM4K9
      port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net, 
        ADDRA9 => WADDR(9), ADDRA8 => WADDR(8), ADDRA7 => 
        WADDR(7), ADDRA6 => WADDR(6), ADDRA5 => WADDR(5), 
        ADDRA4 => WADDR(4), ADDRA3 => WADDR(3), ADDRA2 => 
        WADDR(2), ADDRA1 => WADDR(1), ADDRA0 => WADDR(0), 
        ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 => 
        RADDR(9), ADDRB8 => RADDR(8), ADDRB7 => RADDR(7), 
        ADDRB6 => RADDR(6), ADDRB5 => RADDR(5), ADDRB4 => 
        RADDR(4), ADDRB3 => RADDR(3), ADDRB2 => RADDR(2), 
        ADDRB1 => RADDR(1), ADDRB0 => RADDR(0), DINA8 => 
        GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net, 
        DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => WD(7), 
        DINA2 => WD(6), DINA1 => WD(5), DINA0 => WD(4), DINB8 => 
        GND_1_net, DINB7 => GND_1_net, DINB6 => GND_1_net, 
        DINB5 => GND_1_net, DINB4 => GND_1_net, DINB3 => 
        GND_1_net, DINB2 => GND_1_net, DINB1 => GND_1_net, 
        DINB0 => GND_1_net, WIDTHA0 => GND_1_net, WIDTHA1 => 
        VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net, 
        PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA => 
        GND_1_net, WMODEB => GND_1_net, BLKA => BLKA_EN_1_net, 
        BLKB => BLKB_EN_1_net, WENA => GND_1_net, WENB => 
        VCC_1_net, CLKA => WCLK, CLKB => RCLK, RESET => VCC_1_net, 
        DOUTA8 => OPEN , DOUTA7 => OPEN , DOUTA6 => OPEN , 
        DOUTA5 => OPEN , DOUTA4 => OPEN , DOUTA3 => OPEN , 
        DOUTA2 => OPEN , DOUTA1 => OPEN , DOUTA0 => OPEN , 
        DOUTB8 => OPEN , DOUTB7 => OPEN , DOUTB6 => OPEN , 
        DOUTB5 => OPEN , DOUTB4 => OPEN , DOUTB3 => 
        QX_TEMPR1_7_net, DOUTB2 => QX_TEMPR1_6_net, DOUTB1 => 
        QX_TEMPR1_5_net, DOUTB0 => QX_TEMPR1_4_net);
    Ram5kx8_R3C1 : RAM4K9
      port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net, 
        ADDRA9 => WADDR(9), ADDRA8 => WADDR(8), ADDRA7 => 
        WADDR(7), ADDRA6 => WADDR(6), ADDRA5 => WADDR(5), 
        ADDRA4 => WADDR(4), ADDRA3 => WADDR(3), ADDRA2 => 
        WADDR(2), ADDRA1 => WADDR(1), ADDRA0 => WADDR(0), 
        ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 => 
        RADDR(9), ADDRB8 => RADDR(8), ADDRB7 => RADDR(7), 
        ADDRB6 => RADDR(6), ADDRB5 => RADDR(5), ADDRB4 => 
        RADDR(4), ADDRB3 => RADDR(3), ADDRB2 => RADDR(2), 
        ADDRB1 => RADDR(1), ADDRB0 => RADDR(0), DINA8 => 
        GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net, 
        DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => WD(7), 
        DINA2 => WD(6), DINA1 => WD(5), DINA0 => WD(4), DINB8 => 
        GND_1_net, DINB7 => GND_1_net, DINB6 => GND_1_net, 
        DINB5 => GND_1_net, DINB4 => GND_1_net, DINB3 => 
        GND_1_net, DINB2 => GND_1_net, DINB1 => GND_1_net, 
        DINB0 => GND_1_net, WIDTHA0 => GND_1_net, WIDTHA1 => 
        VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net, 
        PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA => 
        GND_1_net, WMODEB => GND_1_net, BLKA => BLKA_EN_3_net, 
        BLKB => BLKB_EN_3_net, WENA => GND_1_net, WENB => 
        VCC_1_net, CLKA => WCLK, CLKB => RCLK, RESET => VCC_1_net, 
        DOUTA8 => OPEN , DOUTA7 => OPEN , DOUTA6 => OPEN , 
        DOUTA5 => OPEN , DOUTA4 => OPEN , DOUTA3 => OPEN , 
        DOUTA2 => OPEN , DOUTA1 => OPEN , DOUTA0 => OPEN , 
        DOUTB8 => OPEN , DOUTB7 => OPEN , DOUTB6 => OPEN , 
        DOUTB5 => OPEN , DOUTB4 => OPEN , DOUTB3 => 
        QX_TEMPR3_7_net, DOUTB2 => QX_TEMPR3_6_net, DOUTB1 => 
        QX_TEMPR3_5_net, DOUTB0 => QX_TEMPR3_4_net);
    MX2_16 : MX2
      port map(A => QX_TEMPR0_4_net, B => QX_TEMPR1_4_net, S => 
        ADDRB_FF2_0_net, Y => MX2_16_Y);
    ORA_GATE_2_inst : OR2
      port map(A => ENABLE_ADDRA_2_net, B => WEAP, Y => 
        BLKA_EN_2_net);
    NAND3B_ENABLE_ADDRA_1_inst : NAND3B
      port map(A => WADDR(12), B => WADDR(11), C => WADDR(10), 
        Y => ENABLE_ADDRA_1_net);
    ORA_GATE_3_inst : OR2
      port map(A => ENABLE_ADDRA_3_net, B => WEAP, Y => 
        BLKA_EN_3_net);
    MX2_RD_1_inst : MX2
      port map(A => MX2_21_Y, B => QX_TEMPR4_1_net, S => 
        ADDRB_FF2_2_net, Y => RD(1));
    BFF1_0_inst : DFN1
      port map(D => RADDR(10), CLK => RCLK, Q => ADDRB_FF2_0_net);
    MX2_2 : MX2
      port map(A => MX2_1_Y, B => MX2_9_Y, S => ADDRB_FF2_1_net, 
        Y => MX2_2_Y);
    Ram5kx8_R3C0 : RAM4K9
      port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net, 
        ADDRA9 => WADDR(9), ADDRA8 => WADDR(8), ADDRA7 => 
        WADDR(7), ADDRA6 => WADDR(6), ADDRA5 => WADDR(5), 
        ADDRA4 => WADDR(4), ADDRA3 => WADDR(3), ADDRA2 => 
        WADDR(2), ADDRA1 => WADDR(1), ADDRA0 => WADDR(0), 
        ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 => 
        RADDR(9), ADDRB8 => RADDR(8), ADDRB7 => RADDR(7), 
        ADDRB6 => RADDR(6), ADDRB5 => RADDR(5), ADDRB4 => 
        RADDR(4), ADDRB3 => RADDR(3), ADDRB2 => RADDR(2), 
        ADDRB1 => RADDR(1), ADDRB0 => RADDR(0), DINA8 => 
        GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net, 
        DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => WD(3), 
        DINA2 => WD(2), DINA1 => WD(1), DINA0 => WD(0), DINB8 => 
        GND_1_net, DINB7 => GND_1_net, DINB6 => GND_1_net, 
        DINB5 => GND_1_net, DINB4 => GND_1_net, DINB3 => 
        GND_1_net, DINB2 => GND_1_net, DINB1 => GND_1_net, 
        DINB0 => GND_1_net, WIDTHA0 => GND_1_net, WIDTHA1 => 
        VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net, 
        PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA => 
        GND_1_net, WMODEB => GND_1_net, BLKA => BLKA_EN_3_net, 
        BLKB => BLKB_EN_3_net, WENA => GND_1_net, WENB => 
        VCC_1_net, CLKA => WCLK, CLKB => RCLK, RESET => VCC_1_net, 
        DOUTA8 => OPEN , DOUTA7 => OPEN , DOUTA6 => OPEN , 
        DOUTA5 => OPEN , DOUTA4 => OPEN , DOUTA3 => OPEN , 
        DOUTA2 => OPEN , DOUTA1 => OPEN , DOUTA0 => OPEN , 
        DOUTB8 => OPEN , DOUTB7 => OPEN , DOUTB6 => OPEN , 
        DOUTB5 => OPEN , DOUTB4 => OPEN , DOUTB3 => 
        QX_TEMPR3_3_net, DOUTB2 => QX_TEMPR3_2_net, DOUTB1 => 
        QX_TEMPR3_1_net, DOUTB0 => QX_TEMPR3_0_net);
    ORB_GATE_0_inst : OR2
      port map(A => ENABLE_ADDRB_0_net, B => WEBP, Y => 
        BLKB_EN_0_net);
    MX2_RD_5_inst : MX2
      port map(A => MX2_22_Y, B => QX_TEMPR4_5_net, S => 
        ADDRB_FF2_2_net, Y => RD(5));
    AFF1_2_inst : DFN1
      port map(D => WADDR(12), CLK => WCLK, Q => ADDRA_FF2_2_net);
    MX2_1 : MX2
      port map(A => QX_TEMPR0_2_net, B => QX_TEMPR1_2_net, S => 
        ADDRB_FF2_0_net, Y => MX2_1_Y);
    MX2_RD_2_inst : MX2
      port map(A => MX2_2_Y, B => QX_TEMPR4_2_net, S => 
        ADDRB_FF2_2_net, Y => RD(2));
    Ram5kx8_R1C0 : RAM4K9
      port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net, 
        ADDRA9 => WADDR(9), ADDRA8 => WADDR(8), ADDRA7 => 
        WADDR(7), ADDRA6 => WADDR(6), ADDRA5 => WADDR(5), 
        ADDRA4 => WADDR(4), ADDRA3 => WADDR(3), ADDRA2 => 
        WADDR(2), ADDRA1 => WADDR(1), ADDRA0 => WADDR(0), 
        ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 => 
        RADDR(9), ADDRB8 => RADDR(8), ADDRB7 => RADDR(7), 
        ADDRB6 => RADDR(6), ADDRB5 => RADDR(5), ADDRB4 => 
        RADDR(4), ADDRB3 => RADDR(3), ADDRB2 => RADDR(2), 
        ADDRB1 => RADDR(1), ADDRB0 => RADDR(0), DINA8 => 
        GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net, 
        DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => WD(3), 
        DINA2 => WD(2), DINA1 => WD(1), DINA0 => WD(0), DINB8 => 
        GND_1_net, DINB7 => GND_1_net, DINB6 => GND_1_net, 
        DINB5 => GND_1_net, DINB4 => GND_1_net, DINB3 => 
        GND_1_net, DINB2 => GND_1_net, DINB1 => GND_1_net, 
        DINB0 => GND_1_net, WIDTHA0 => GND_1_net, WIDTHA1 => 
        VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net, 
        PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA => 
        GND_1_net, WMODEB => GND_1_net, BLKA => BLKA_EN_1_net, 
        BLKB => BLKB_EN_1_net, WENA => GND_1_net, WENB => 
        VCC_1_net, CLKA => WCLK, CLKB => RCLK, RESET => VCC_1_net, 
        DOUTA8 => OPEN , DOUTA7 => OPEN , DOUTA6 => OPEN , 
        DOUTA5 => OPEN , DOUTA4 => OPEN , DOUTA3 => OPEN , 
        DOUTA2 => OPEN , DOUTA1 => OPEN , DOUTA0 => OPEN , 
        DOUTB8 => OPEN , DOUTB7 => OPEN , DOUTB6 => OPEN , 
        DOUTB5 => OPEN , DOUTB4 => OPEN , DOUTB3 => 
        QX_TEMPR1_3_net, DOUTB2 => QX_TEMPR1_2_net, DOUTB1 => 
        QX_TEMPR1_1_net, DOUTB0 => QX_TEMPR1_0_net);
    WEBUBBLEA : INV
      port map(A => WEN, Y => WEAP);
    BFF1_1_inst : DFN1
      port map(D => RADDR(11), CLK => RCLK, Q => ADDRB_FF2_1_net);
    ORA_GATE_1_inst : OR2
      port map(A => ENABLE_ADDRA_1_net, B => WEAP, Y => 
        BLKA_EN_1_net);
    Ram5kx8_R4C1 : RAM4K9
      port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net, 
        ADDRA9 => WADDR(9), ADDRA8 => WADDR(8), ADDRA7 => 
        WADDR(7), ADDRA6 => WADDR(6), ADDRA5 => WADDR(5), 
        ADDRA4 => WADDR(4), ADDRA3 => WADDR(3), ADDRA2 => 
        WADDR(2), ADDRA1 => WADDR(1), ADDRA0 => WADDR(0), 
        ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 => 
        RADDR(9), ADDRB8 => RADDR(8), ADDRB7 => RADDR(7), 
        ADDRB6 => RADDR(6), ADDRB5 => RADDR(5), ADDRB4 => 
        RADDR(4), ADDRB3 => RADDR(3), ADDRB2 => RADDR(2), 
        ADDRB1 => RADDR(1), ADDRB0 => RADDR(0), DINA8 => 
        GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net, 
        DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => WD(7), 
        DINA2 => WD(6), DINA1 => WD(5), DINA0 => WD(4), DINB8 => 
        GND_1_net, DINB7 => GND_1_net, DINB6 => GND_1_net, 
        DINB5 => GND_1_net, DINB4 => GND_1_net, DINB3 => 
        GND_1_net, DINB2 => GND_1_net, DINB1 => GND_1_net, 
        DINB0 => GND_1_net, WIDTHA0 => GND_1_net, WIDTHA1 => 
        VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net, 
        PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA => 
        GND_1_net, WMODEB => GND_1_net, BLKA => BLKA_EN_4_net, 
        BLKB => BLKB_EN_4_net, WENA => GND_1_net, WENB => 
        VCC_1_net, CLKA => WCLK, CLKB => RCLK, RESET => VCC_1_net, 
        DOUTA8 => OPEN , DOUTA7 => OPEN , DOUTA6 => OPEN , 
        DOUTA5 => OPEN , DOUTA4 => OPEN , DOUTA3 => OPEN , 
        DOUTA2 => OPEN , DOUTA1 => OPEN , DOUTA0 => OPEN , 
        DOUTB8 => OPEN , DOUTB7 => OPEN , DOUTB6 => OPEN , 
        DOUTB5 => OPEN , DOUTB4 => OPEN , DOUTB3 => 
        QX_TEMPR4_7_net, DOUTB2 => QX_TEMPR4_6_net, DOUTB1 => 
        QX_TEMPR4_5_net, DOUTB0 => QX_TEMPR4_4_net);
    MX2_0 : MX2
      port map(A => QX_TEMPR0_5_net, B => QX_TEMPR1_5_net, S => 
        ADDRB_FF2_0_net, Y => MX2_0_Y);
    MX2_RD_4_inst : MX2
      port map(A => MX2_20_Y, B => QX_TEMPR4_4_net, S => 
        ADDRB_FF2_2_net, Y => RD(4));
    ORA_GATE_4_inst : OR2
      port map(A => ENABLE_ADDRA_4_net, B => WEAP, Y => 
        BLKA_EN_4_net);
    Ram5kx8_R0C1 : RAM4K9
      port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net, 
        ADDRA9 => WADDR(9), ADDRA8 => WADDR(8), ADDRA7 => 
        WADDR(7), ADDRA6 => WADDR(6), ADDRA5 => WADDR(5), 
        ADDRA4 => WADDR(4), ADDRA3 => WADDR(3), ADDRA2 => 
        WADDR(2), ADDRA1 => WADDR(1), ADDRA0 => WADDR(0), 
        ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 => 
        RADDR(9), ADDRB8 => RADDR(8), ADDRB7 => RADDR(7), 
        ADDRB6 => RADDR(6), ADDRB5 => RADDR(5), ADDRB4 => 
        RADDR(4), ADDRB3 => RADDR(3), ADDRB2 => RADDR(2), 
        ADDRB1 => RADDR(1), ADDRB0 => RADDR(0), DINA8 => 
        GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net, 
        DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => WD(7), 
        DINA2 => WD(6), DINA1 => WD(5), DINA0 => WD(4), DINB8 => 
        GND_1_net, DINB7 => GND_1_net, DINB6 => GND_1_net, 
        DINB5 => GND_1_net, DINB4 => GND_1_net, DINB3 => 
        GND_1_net, DINB2 => GND_1_net, DINB1 => GND_1_net, 
        DINB0 => GND_1_net, WIDTHA0 => GND_1_net, WIDTHA1 => 
        VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net, 
        PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA => 
        GND_1_net, WMODEB => GND_1_net, BLKA => BLKA_EN_0_net, 
        BLKB => BLKB_EN_0_net, WENA => GND_1_net, WENB => 
        VCC_1_net, CLKA => WCLK, CLKB => RCLK, RESET => VCC_1_net, 
        DOUTA8 => OPEN , DOUTA7 => OPEN , DOUTA6 => OPEN , 
        DOUTA5 => OPEN , DOUTA4 => OPEN , DOUTA3 => OPEN , 
        DOUTA2 => OPEN , DOUTA1 => OPEN , DOUTA0 => OPEN , 
        DOUTB8 => OPEN , DOUTB7 => OPEN , DOUTB6 => OPEN , 
        DOUTB5 => OPEN , DOUTB4 => OPEN , DOUTB3 => 
        QX_TEMPR0_7_net, DOUTB2 => QX_TEMPR0_6_net, DOUTB1 => 
        QX_TEMPR0_5_net, DOUTB0 => QX_TEMPR0_4_net);
    NAND3A_ENABLE_ADDRB_3_inst : NAND3A
      port map(A => RADDR(12), B => RADDR(11), C => RADDR(10), 
        Y => ENABLE_ADDRB_3_net);
    MX2_5 : MX2
      port map(A => MX2_3_Y, B => MX2_10_Y, S => ADDRB_FF2_1_net, 
        Y => MX2_5_Y);
    MX2_14 : MX2
      port map(A => QX_TEMPR0_0_net, B => QX_TEMPR1_0_net, S => 
        ADDRB_FF2_0_net, Y => MX2_14_Y);
    NAND3B_ENABLE_ADDRB_4_inst : NAND3B
      port map(A => RADDR(10), B => RADDR(11), C => RADDR(12), 
        Y => ENABLE_ADDRB_4_net);
    ORB_GATE_2_inst : OR2
      port map(A => ENABLE_ADDRB_2_net, B => WEBP, Y => 
        BLKB_EN_2_net);
    NAND3C_ENABLE_ADDRA_0_inst : NAND3C
      port map(A => WADDR(12), B => WADDR(11), C => WADDR(10), 
        Y => ENABLE_ADDRA_0_net);
    ORB_GATE_3_inst : OR2
      port map(A => ENABLE_ADDRB_3_net, B => WEBP, Y => 
        BLKB_EN_3_net);
    MX2_9 : MX2
      port map(A => QX_TEMPR2_2_net, B => QX_TEMPR3_2_net, S => 
        ADDRB_FF2_0_net, Y => MX2_9_Y);
    MX2_4 : MX2
      port map(A => QX_TEMPR0_3_net, B => QX_TEMPR1_3_net, S => 
        ADDRB_FF2_0_net, Y => MX2_4_Y);
    NAND3B_ENABLE_ADDRB_2_inst : NAND3B
      port map(A => RADDR(12), B => RADDR(10), C => RADDR(11), 
        Y => ENABLE_ADDRB_2_net);
    AFF1_0_inst : DFN1
      port map(D => WADDR(10), CLK => WCLK, Q => ADDRA_FF2_0_net);
    WEBUBBLEB : INV
      port map(A => REN, Y => WEBP);
    NAND3C_ENABLE_ADDRB_0_inst : NAND3C
      port map(A => RADDR(12), B => RADDR(11), C => RADDR(10), 
        Y => ENABLE_ADDRB_0_net);
    Ram5kx8_R4C0 : RAM4K9
      port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net, 
        ADDRA9 => WADDR(9), ADDRA8 => WADDR(8), ADDRA7 => 
        WADDR(7), ADDRA6 => WADDR(6), ADDRA5 => WADDR(5), 
        ADDRA4 => WADDR(4), ADDRA3 => WADDR(3), ADDRA2 => 
        WADDR(2), ADDRA1 => WADDR(1), ADDRA0 => WADDR(0), 
        ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 => 
        RADDR(9), ADDRB8 => RADDR(8), ADDRB7 => RADDR(7), 
        ADDRB6 => RADDR(6), ADDRB5 => RADDR(5), ADDRB4 => 
        RADDR(4), ADDRB3 => RADDR(3), ADDRB2 => RADDR(2), 
        ADDRB1 => RADDR(1), ADDRB0 => RADDR(0), DINA8 => 
        GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net, 
        DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => WD(3), 
        DINA2 => WD(2), DINA1 => WD(1), DINA0 => WD(0), DINB8 => 
        GND_1_net, DINB7 => GND_1_net, DINB6 => GND_1_net, 
        DINB5 => GND_1_net, DINB4 => GND_1_net, DINB3 => 
        GND_1_net, DINB2 => GND_1_net, DINB1 => GND_1_net, 
        DINB0 => GND_1_net, WIDTHA0 => GND_1_net, WIDTHA1 => 
        VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net, 
        PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA => 
        GND_1_net, WMODEB => GND_1_net, BLKA => BLKA_EN_4_net, 
        BLKB => BLKB_EN_4_net, WENA => GND_1_net, WENB => 
        VCC_1_net, CLKA => WCLK, CLKB => RCLK, RESET => VCC_1_net, 
        DOUTA8 => OPEN , DOUTA7 => OPEN , DOUTA6 => OPEN , 
        DOUTA5 => OPEN , DOUTA4 => OPEN , DOUTA3 => OPEN , 
        DOUTA2 => OPEN , DOUTA1 => OPEN , DOUTA0 => OPEN , 
        DOUTB8 => OPEN , DOUTB7 => OPEN , DOUTB6 => OPEN , 
        DOUTB5 => OPEN , DOUTB4 => OPEN , DOUTB3 => 
        QX_TEMPR4_3_net, DOUTB2 => QX_TEMPR4_2_net, DOUTB1 => 
        QX_TEMPR4_1_net, DOUTB0 => QX_TEMPR4_0_net);
    ORB_GATE_1_inst : OR2
      port map(A => ENABLE_ADDRB_1_net, B => WEBP, Y => 
        BLKB_EN_1_net);
    MX2_RD_7_inst : MX2
      port map(A => MX2_19_Y, B => QX_TEMPR4_7_net, S => 
        ADDRB_FF2_2_net, Y => RD(7));
    AFF1_1_inst : DFN1
      port map(D => WADDR(11), CLK => WCLK, Q => ADDRA_FF2_1_net);
    ORB_GATE_4_inst : OR2
      port map(A => ENABLE_ADDRB_4_net, B => WEBP, Y => 
        BLKB_EN_4_net);
    MX2_23 : MX2
      port map(A => QX_TEMPR0_1_net, B => QX_TEMPR1_1_net, S => 
        ADDRB_FF2_0_net, Y => MX2_23_Y);
    MX2_6 : MX2
      port map(A => QX_TEMPR2_3_net, B => QX_TEMPR3_3_net, S => 
        ADDRB_FF2_0_net, Y => MX2_6_Y);
    Ram5kx8_R2C0 : RAM4K9
      port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net, 
        ADDRA9 => WADDR(9), ADDRA8 => WADDR(8), ADDRA7 => 
        WADDR(7), ADDRA6 => WADDR(6), ADDRA5 => WADDR(5), 
        ADDRA4 => WADDR(4), ADDRA3 => WADDR(3), ADDRA2 => 
        WADDR(2), ADDRA1 => WADDR(1), ADDRA0 => WADDR(0), 
        ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 => 
        RADDR(9), ADDRB8 => RADDR(8), ADDRB7 => RADDR(7), 
        ADDRB6 => RADDR(6), ADDRB5 => RADDR(5), ADDRB4 => 
        RADDR(4), ADDRB3 => RADDR(3), ADDRB2 => RADDR(2), 
        ADDRB1 => RADDR(1), ADDRB0 => RADDR(0), DINA8 => 
        GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net, 
        DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => WD(3), 
        DINA2 => WD(2), DINA1 => WD(1), DINA0 => WD(0), DINB8 => 
        GND_1_net, DINB7 => GND_1_net, DINB6 => GND_1_net, 
        DINB5 => GND_1_net, DINB4 => GND_1_net, DINB3 => 
        GND_1_net, DINB2 => GND_1_net, DINB1 => GND_1_net, 
        DINB0 => GND_1_net, WIDTHA0 => GND_1_net, WIDTHA1 => 
        VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net, 
        PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA => 
        GND_1_net, WMODEB => GND_1_net, BLKA => BLKA_EN_2_net, 
        BLKB => BLKB_EN_2_net, WENA => GND_1_net, WENB => 
        VCC_1_net, CLKA => WCLK, CLKB => RCLK, RESET => VCC_1_net, 
        DOUTA8 => OPEN , DOUTA7 => OPEN , DOUTA6 => OPEN , 
        DOUTA5 => OPEN , DOUTA4 => OPEN , DOUTA3 => OPEN , 
        DOUTA2 => OPEN , DOUTA1 => OPEN , DOUTA0 => OPEN , 
        DOUTB8 => OPEN , DOUTB7 => OPEN , DOUTB6 => OPEN , 
        DOUTB5 => OPEN , DOUTB4 => OPEN , DOUTB3 => 
        QX_TEMPR2_3_net, DOUTB2 => QX_TEMPR2_2_net, DOUTB1 => 
        QX_TEMPR2_1_net, DOUTB0 => QX_TEMPR2_0_net);
    MX2_RD_0_inst : MX2
      port map(A => MX2_18_Y, B => QX_TEMPR4_0_net, S => 
        ADDRB_FF2_2_net, Y => RD(0));
    MX2_13 : MX2
      port map(A => QX_TEMPR2_0_net, B => QX_TEMPR3_0_net, S => 
        ADDRB_FF2_0_net, Y => MX2_13_Y);
    BFF1_2_inst : DFN1
      port map(D => RADDR(12), CLK => RCLK, Q => ADDRB_FF2_2_net);
    MX2_17 : MX2
      port map(A => MX2_4_Y, B => MX2_6_Y, S => ADDRB_FF2_1_net, 
        Y => MX2_17_Y);
    MX2_21 : MX2
      port map(A => MX2_23_Y, B => MX2_11_Y, S => ADDRB_FF2_1_net, 
        Y => MX2_21_Y);
    MX2_22 : MX2
      port map(A => MX2_0_Y, B => MX2_12_Y, S => ADDRB_FF2_1_net, 
        Y => MX2_22_Y);
    ORA_GATE_0_inst : OR2
      port map(A => ENABLE_ADDRA_0_net, B => WEAP, Y => 
        BLKA_EN_0_net);
    MX2_20 : MX2
      port map(A => MX2_16_Y, B => MX2_15_Y, S => ADDRB_FF2_1_net, 
        Y => MX2_20_Y);
    MX2_19 : MX2
      port map(A => MX2_7_Y, B => MX2_8_Y, S => ADDRB_FF2_1_net, 
        Y => MX2_19_Y);
    MX2_RD_6_inst : MX2
      port map(A => MX2_5_Y, B => QX_TEMPR4_6_net, S => 
        ADDRB_FF2_2_net, Y => RD(6));
    MX2_3 : MX2
      port map(A => QX_TEMPR0_6_net, B => QX_TEMPR1_6_net, S => 
        ADDRB_FF2_0_net, Y => MX2_3_Y);
    MX2_8 : MX2
      port map(A => QX_TEMPR2_7_net, B => QX_TEMPR3_7_net, S => 
        ADDRB_FF2_0_net, Y => MX2_8_Y);
    MX2_11 : MX2
      port map(A => QX_TEMPR2_1_net, B => QX_TEMPR3_1_net, S => 
        ADDRB_FF2_0_net, Y => MX2_11_Y);
end DEF_ARCH;

-- _Disclaimer: Please leave the following comments in the file, they are for internal purposes only._


-- _GEN_File_Contents_

-- Version:8.3.0.22
-- ACTGENU_CALL:1
-- BATCH:T
-- FAM:IGLOO
-- OUTFORMAT:VHDL
-- LPMTYPE:LPM_RAM
-- LPM_HINT:TWO
-- INSERT_PAD:NO
-- INSERT_IOREG:NO
-- GEN_BHV_VHDL_VAL:F
-- GEN_BHV_VERILOG_VAL:F
-- MGNTIMER:F
-- MGNCMPL:T
-- "DESDIR:D:/actel_ip/SDRAM_Controller/5nov/26_nov/04dec/mobile_sdram_interface/smartgen\Ram5kx8"
-- GEN_BEHV_MODULE:T
-- SMARTGEN_DIE:M1IS6X6M2LPLV
-- SMARTGEN_PACKAGE:fg484
-- WWIDTH:8
-- WDEPTH:5120
-- RWIDTH:8
-- RDEPTH:5120
-- CLKS:2
-- RESET_POLARITY:2
-- INIT_RAM:F
-- DEFAULT_WORD:0x00
-- WCLK_EDGE:RISE
-- RCLK_EDGE:RISE
-- WCLOCK_PN:WCLK
-- RCLOCK_PN:RCLK
-- PMODE2:0
-- DATA_IN_PN:WD
-- WADDRESS_PN:WADDR
-- WE_PN:WEN
-- DATA_OUT_PN:RD
-- RADDRESS_PN:RADDR
-- RE_PN:REN
-- WE_POLARITY:1
-- RE_POLARITY:1
-- PTYPE:1

-- _End_Comments_

