-- mobile_sdram_interface.vhd
-- VHDL Design :                                                              --
--         Design     : Mobile SDRAM Interface                                --
--         File name  : mobile_sdram_Interface.vhd                            --
--                                                                            --
--         Created by : Himanshu Tewari                                       --
--                    :                                                       --
--         on         :                                                       --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: The Mobile SDRAM Interface IP described in this design        --
--includes a generic system interface. . The system interface illustrates the -- 
--control signals needed for the SDRAM logic block.                           --
                                                                              --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Modification History                                                       --
--                                                                            --
-- Initial revision                                                           --
--                                                                            --
-- Revision 1.0                                                               --
--         by         :                                                       --
--         on         :                                                       --
-- Modifications to                                                           --
--   1.                                                                       --
--                                                                            --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--                               L I B R A R Y                                --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

library IEEE;  

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library igloo; 

use work.pkg_constants.all;

--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--                               E N T I T Y                                  --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

entity mobile_sdram_Interface is    

port(	
	-- Mobile SDRAM interface signals
    -- Mobile SDRAM clock
	clk_to_sdram	: out	STD_LOGIC;	
    -- Active high clock enable		
	clkenb_sdram	: out 	STD_LOGIC;	
    -- Active low chip select		
	ncs_sdram	: out	STD_LOGIC;	
    -- Active low CAS		
	ncas_sdram	: out	STD_LOGIC;	
    -- Active low RAS		
	nras_sdram	: out	STD_LOGIC;	
    -- Active low write enable		
	nwe_sdram	: out	STD_LOGIC;			
    -- Lower data byte mask
	ldqm_sdram	: out	STD_LOGIC;	
    -- Upper data byte mask		
	udqm_sdram	: out	STD_LOGIC;			
	-- Bank address
	ba_sdram	: out	STD_LOGIC_VECTOR (1 downto 0);
    -- SDRAM address bus	
	add_sdram		: out	STD_LOGIC_VECTOR (11 downto 0);	
    -- SDRAM data bus
	dq_sdram	: inout	STD_LOGIC_VECTOR (15 downto 0);	
	--UART RX input
    rxd		:	in		std_logic;
    --UART TX input
    txd	:	out		std_logic;

        --JTAG signals for OCI
        TCK_s		: in std_logic;  
        TMS_s		: in std_logic;
        TDI_s		: in std_logic;
        TDO_s		: out std_logic;
        TRSTB_s		: in std_logic ; 
    -- System clock
	clk		: in	STD_LOGIC;		
    -- System reset (active low)	
	sys_rst 		: in 	STD_LOGIC		
   	);

end mobile_sdram_Interface;

--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--                         A R C H I T E C T U R E                            --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

architecture mobile_sdram_Interface_archi of mobile_sdram_Interface is

--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Component MObile SDRAM Interface Core
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
component mobile_sdram_core 

    generic (
        -- local address bus size
        SDRAM_RASIZE    : integer := 24;  
        -- max number of sdram column bits 
        SDRAM_COLBITS   : integer := 9;   
        -- max number of sdram bank bits
        SDRAM_BANKBITS  : integer := 2;  
        -- max number of sdram row bits  
        SDRAM_ROWBITS   : integer := 12;   
        -- max number of sdram row bits
        SDRAM_DATABITS   : integer := 16   
        );

port(	
	-- Mobile SDRAM interface signals
    -- Mobile SDRAM clock
	clk_to_sdram	: out	STD_LOGIC;
    -- Active high clock enable			
	clkenb_sdram	: out 	STD_LOGIC;	
    -- Active low chip select		
	ncs_sdram	: out	STD_LOGIC;
    -- Active low CAS			
	ncas_sdram	: out	STD_LOGIC;		
    -- Active low RAS	
	nras_sdram	: out	STD_LOGIC;	
    -- Active low write enable		
	nwe_sdram	: out	STD_LOGIC;			
    -- Lower data byte mask
	ldqm_sdram	: out	STD_LOGIC;
    -- Upper data byte mask
	udqm_sdram	: out	STD_LOGIC;			
	-- Bank address
	ba_sdram	: out	STD_LOGIC_VECTOR ((SDRAM_BANKBITS - 1) downto 0);
    -- SDRAM address bus	
	add_sdram		: out	STD_LOGIC_VECTOR ((SDRAM_ROWBITS - 1) downto 0);	
    -- SDRAM data bus
	dq_sdram	: inout	STD_LOGIC_VECTOR ((SDRAM_DATABITS - 1) downto 0);	
    	
	-- System interface signals

    -- System clock	
	sys_clk	 	: in	STD_LOGIC;	
    -- System reset (active low)
	reset		: in 	STD_LOGIC;	
    -- Active high read enable
    RD_EN       : in 	STD_LOGIC;
    -- Active high write enable
    WR_EN       : in 	STD_LOGIC;	
    -- System test data		
	mc_data_in : in  STD_LOGIC_VECTOR ((SDRAM_DATABITS - 1) downto 0);	
    -- System test data
	mc_data_out: out  STD_LOGIC_VECTOR ((SDRAM_DATABITS - 1) downto 0);
    -- System address bus	
	mc_addr_bus	: in 	STD_LOGIC_VECTOR ((SDRAM_RASIZE - 1) downto 0)	
   	);

end component;

--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--8051 component
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

component CORE8051
	generic (
	-- set this to 1 to instantiate OCI logic
--	USE_OCI			: integer := 0;
    USE_OCI			: integer := 1;
	-- set this to 1 to use ProASIC+ UJTAG macro for OCI logic
--	USE_UJTAG	: integer := 0;
    USE_UJTAG	: integer := 1;
	-- TRACE_DEPTH
	-- no trace:  Set value to 0
	-- 256 depth: Set value to 8
	TRACE_DEPTH	: integer := 0;
	-- TRIG_NUM
	-- no triggers:  set value to 0
	--  1 trigger:   set value to 1
	--  2 triggers:  set value to 2
	--  4 triggers:  set value to 4  
	TRIG_NUM	: integer := 0;
	-- set this to 1 to make nrsto an output from here
	NRSTOUT			: integer := 0;
	-- set this to 1 to enable flip-flop optimizations (default is 0)
	EN_FF_OPTS		: integer := 0
	);
	port (
    -- Control signal inputs
    nreset       : in  std_logic;  -- Asynch.act.low reset input
    clk          : in  std_logic;  -- Main clock input
    clkcpu       : in  std_logic;  -- CPU Clock input
    clkper       : in  std_logic;  -- Peripheral Clock input
    -- Port inputs
    port0i       : in  std_logic_vector(7 downto 0);
    port1i       : in  std_logic_vector(7 downto 0);
    port2i       : in  std_logic_vector(7 downto 0);
    port3i       : in  std_logic_vector(7 downto 0);
    -- External interrupt/Port alternate signals
    int0         : in  std_logic;  -- External interrupt 0
    int1         : in  std_logic;  -- External interrupt 1
    int0a        : in  std_logic;  -- External interrupt 0a
    int1a        : in  std_logic;  -- External interrupt 1a
    int2         : in  std_logic;  -- External interrupt 2
    int3         : in  std_logic;  -- External interrupt 3
    int4         : in  std_logic;  -- External interrupt 4
    int5         : in  std_logic;  -- External interrupt 5
    int6         : in  std_logic;  -- External interrupt 6 
    int7         : in  std_logic;  -- External interrupt 7
    -- Serial/Port alternate signals
    rxd0i        : in  std_logic;  -- Serial 0 receive data
    -- Timer/Port alternate signals
    t0           : in std_logic;  -- Timer 0 external input
    t1           : in std_logic;  -- Timer 1 external input
    -- Control signal outputs for external logic
    nrsto        : out std_logic;  -- buffered reset driver
    nrsto_nc     : inout std_logic;-- this must be a no-connect at top-level
	-- clock gating signals to control external AND gates
    clkcpu_en    : out std_logic;  -- CPU Clock enable to external gate
    clkper_en    : out std_logic;  -- Peripheral Clock enable to external gate
    -- MOVX Instruction
    movx         : out std_logic;
    -- Port outputs
    port0o       : out std_logic_vector(7 downto 0);
    port1o       : out std_logic_vector(7 downto 0);
    port2o       : out std_logic_vector(7 downto 0);
    port3o       : out std_logic_vector(7 downto 0);
    -- Serial/Port alternate signals
    rxd0o        : out std_logic;  -- Serial 0 receive clock
    txd0         : out std_logic;  -- Serial 0 transmit data
    -- External Memory interface 
    mempsacki    : in  std_logic;
    memacki      : in  std_logic;
    memdatai     : in  std_logic_vector( 7 downto 0);
    mempsacko    : out std_logic;  -- Program store acknowledge
    memdatao     : out std_logic_vector( 7 downto 0);
    memaddr      : out std_logic_vector(15 downto 0);
    mempsrd      : out std_logic;  -- Program store read enable
    memwr        : out std_logic;  -- Memory write enable
    memrd        : out std_logic;  -- Memory read enable
    -- Internal Memory interface (R0-R7,etc.)
    ramdatai     : in  std_logic_vector(7 downto 0);
    ramdatao     : out std_logic_vector(7 downto 0);
    ramaddr      : out std_logic_vector(7 downto 0);
    ramwe        : out std_logic;  -- Data file write enable
    ramoe        : out std_logic;  -- Data file output enable
    -- Special function register interface (external peripherals)
    sfrdatai     : in  std_logic_vector(7 downto 0);
    sfrdatao     : out std_logic_vector(7 downto 0);
    sfraddr      : out std_logic_vector(6 downto 0);
    sfrwe        : out std_logic;  -- SFR write enable
    sfroe        : out std_logic;   -- SFR output enable
    ----------------------------------------------------------------------
    -- On Chip Instrumentation (OCI) related signals
    ----------------------------------------------------------------------
    -- JTAG signals for OCI
    TCK          : in  std_logic; -- this should be tied high if OCI unused
    TMS          : in  std_logic;
    TDI          : in  std_logic;
    TDO          : out std_logic;
    TRSTB        : in  std_logic; -- this should be tied high if OCI unused
    -- Break bus for OCI (connect to bidirectional pad at top-level)
    BreakIn      : in  std_logic; -- this input must be grounded if unused
    BreakOut     : out std_logic;
    -- debugger code memory bank support, if banking not used, ground these
    membank      : in  std_logic_vector(3 downto 0);
    -- Debug mode program storage write signal
    dbgmempswr   : out std_logic;
    -- Trigger output
    TrigOut      : out std_logic;
    -- Auxilliary output
    AuxOut       : out std_logic;
    -- OCI signals for external RAM(s)
    TraceA       : out std_logic_vector(7 downto 0);
    TraceDI      : out std_logic_vector(19 downto 0);
    TraceDO      : in  std_logic_vector(19 downto 0);
    TraceWr      : out std_logic
    );
end component;


constant  ASIZE  : integer := 13;

--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Program memory Ram5kx8 
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

component Ram5kx8 is 
    port( WD : in std_logic_vector(7 downto 0); RD : out 
        std_logic_vector(7 downto 0);WEN, REN : in std_logic; 
        WADDR : in std_logic_vector(12 downto 0); RADDR : in 
        std_logic_vector(12 downto 0);WCLK, RCLK : in std_logic
        ) ;
end component;

--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Data memory Ram256x8 
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
component Ram256x8 
    port( WD : in std_logic_vector(7 downto 0); RD : out 
        std_logic_vector(7 downto 0);WEN, REN : in std_logic; 
        WADDR : in std_logic_vector(7 downto 0); RADDR : in 
        std_logic_vector(7 downto 0);WCLK, RCLK : in 
        std_logic) ;
end component;

--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- PLL 12 MHz
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

component pll_12mhz is 
    port(POWERDOWN, CLKA : in std_logic;  LOCK, GLA, GLB : out 
        std_logic) ;
end component;  

--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Component UART
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

component uart_core 
    port(
        -- Inputs
        BAUD_VAL : in std_logic_vector(7 downto 0);
        BIT8 : in std_logic;
        CLK : in std_logic;
        CSN : in std_logic;
        DATA_IN : in std_logic_vector(7 downto 0);
        ODD_N_EVEN : in std_logic;
        OEN : in std_logic;
        PARITY_EN : in std_logic;
        RESET_N : in std_logic;
        RX : in std_logic;
        WEN : in std_logic;
        -- Outputs
        DATA_OUT : out std_logic_vector(7 downto 0);
        OVERFLOW : out std_logic;
        PARITY_ERR : out std_logic;
        RXRDY : out std_logic;
        TX : out std_logic;
        TXRDY : out std_logic
    );
end component;

-- Program Memory interface name directions relative to Core8051
signal memdatai		: std_logic_vector(7 downto 0);
signal memaddr		: std_logic_vector(15 downto 0);
signal memdatao : std_logic_vector(7 downto 0); 
signal dbgmempswr, dbgmempswr_sig : std_logic;
signal mempsrd		: std_logic;  -- Program store read enable

-- Internal Memory interface (R0-R7,etc.) name directions relative to Core8051
signal ramdatai		: std_logic_vector(7 downto 0);
signal ramdatao		: std_logic_vector(7 downto 0);
signal ramaddr		: std_logic_vector(7 downto 0);
signal ramwe, ramwe_sig		: std_logic;
signal ramoe		: std_logic;

-- misc. signals
signal nclk			: std_logic;
signal clk8051		: std_logic;
signal zeroes		: std_logic_vector(31 downto 0);
signal ones			: std_logic_vector(31 downto 0);
signal GND_sig		: std_logic;
signal VCC_sig		: std_logic;

signal  mempsrd_sig, ramoe_sig :  std_logic;

--
signal    data_8051_in :  STD_LOGIC_VECTOR (7 downto 0);

signal    addr_8051_1byte :  STD_LOGIC_VECTOR (7 downto 0);
signal    addr_8051_2byte :  STD_LOGIC_VECTOR (7 downto 0);
signal    addr_8051_3byte :  STD_LOGIC_VECTOR (7 downto 0);

signal    RD_8051_EN , WR_8051_EN  :  	STD_LOGIC;			

signal ip_data : std_logic_vector(7 downto 0); 

signal mem_data : std_logic_vector(7 downto 0); 

signal    memwr        :  std_logic;  -- Memory write enable
signal    memrd        :  std_logic;  -- Memory read enable

signal    nreset        :  std_logic;  

 
  signal   count :  STD_LOGIC_VECTOR (1 downto 0);

signal wr_mem,sys_clk_sig, sys_clk_in :  	STD_LOGIC;	

signal lock,wr_enb,rd_enb :  	STD_LOGIC;

signal datao_1byte :  STD_LOGIC_VECTOR (7 downto 0);
signal datao_2byte :  STD_LOGIC_VECTOR (7 downto 0);

signal data_8051_out_sig, data_8051_in_sig : STD_LOGIC_VECTOR (15 downto 0);

signal addr_8051_out_sig : STD_LOGIC_VECTOR (23 downto 0);

signal p0i     :  std_logic_vector(7 downto 0);
signal p1i     :  std_logic_vector(7 downto 0);
signal p2i     :  std_logic_vector(7 downto 0);
signal p3i     :  std_logic_vector(7 downto 0);

signal p0o     :  std_logic_vector(7 downto 0);
signal p1o     :  std_logic_vector(7 downto 0);
signal p2o     :  std_logic_vector(7 downto 0);
signal p3o     :  std_logic_vector(7 downto 0);

signal csn_s, oen_s, wen_s, overflow_f, parityerr_f, rxrdy_f, txrdy_f, rxd_s : std_logic;

signal data_oled, data_uart, data_in_s : std_logic_vector(7 downto 0);

signal oen1_s, oen2_s, wen1_s, wen2_s : std_logic;

begin

--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--addressing the registers                                                    --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

    process(sys_clk_in)
    begin
       if (sys_clk_in'event and sys_clk_in = '1') then
        if(memaddr(2 downto 0) = "001" and memwr = '1')then
            addr_8051_1byte <= memdatao;
        end if;
       end if;
    end process;

    process(sys_clk_in)
    begin
       if (sys_clk_in'event and sys_clk_in = '1') then
        if(memaddr(2 downto 0) = "010" and memwr = '1')then
            addr_8051_2byte <= memdatao;
        end if;
       end if;
    end process;

    process(sys_clk_in)
    begin
       if (sys_clk_in'event and sys_clk_in = '1') then
        if(memaddr(2 downto 0) = "011" and memwr = '1')then
            addr_8051_3byte <= memdatao;
        end if;
       end if;
    end process;


    process(sys_clk_in)
    begin
       if (sys_clk_in'event and sys_clk_in = '1') then
        if(memaddr(2 downto 0) = "100" and memwr = '1')then
            datao_1byte   <= memdatao;
        end if;
       end if;
    end process;

    process(sys_clk_in)
    begin
       if (sys_clk_in'event and sys_clk_in = '1') then
        if(memaddr(2 downto 0) = "101" and memwr = '1')then
            datao_2byte   <= memdatao;
        end if;
       end if;
    end process;

    process(sys_clk_in)
    begin
        if (sys_clk_in'event and sys_clk_in = '1') then
            if(memaddr(2 downto 0) = "101" and memwr = '1')then
                wr_enb <= '1';
            else
                wr_enb <= '0'; 
            end if;
        end if;          
    end process; 
                   
    process(sys_clk_in)
    begin
        if (sys_clk_in'event and sys_clk_in = '1') then
          if(memaddr(2 downto 0) = "110" and memwr = '1')then
            rd_enb <= '1';
          else
            rd_enb <= '0'; 
          end if;          
        end if;          
    end process;                   


   data_8051_in <=  data_8051_in_sig(15 downto 8) when  (memaddr(2 downto 0) = "111" and memrd = '1') else
                    data_8051_in_sig(7 downto 0) when  (memaddr(2 downto 0) = "000" and memrd = '1') else
                    data_8051_in;

addr_8051_out_sig <=  addr_8051_3byte & addr_8051_2byte & addr_8051_1byte;
data_8051_out_sig <= datao_2byte & datao_1byte;
ip_data <= data_8051_in;

RD_8051_EN <= rd_enb;
WR_8051_EN <= wr_enb;

--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- process for reading back data from IP
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

process(memrd,sys_clk_in,ip_data,mem_data)
begin
    if (sys_clk_in'event and sys_clk_in = '1') then  
        if (memrd = '1') then
          memdatai <= ip_data;
        else
          memdatai <= mem_data; 
        end if;
    end if;
end process;

--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
    -- instantiate MICRON SDRAM macro
	-- (unused inputs connected to static values, unused
	-- outputs left unconnected)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

	mobile_sdram_core_inst : mobile_sdram_core
    generic map (

        SDRAM_RASIZE    => 24,
        SDRAM_COLBITS   => 9,
        SDRAM_BANKBITS  => 2,
        SDRAM_ROWBITS   => 12,
        SDRAM_DATABITS  => 16

    )
	port map (

	clk_to_sdram       =>  clk_to_sdram,	
	clkenb_sdram	   =>  clkenb_sdram,
	ncs_sdram	       =>  ncs_sdram,
	ncas_sdram	       =>  ncas_sdram,
	nras_sdram	       =>  nras_sdram,
	nwe_sdram	       =>  nwe_sdram,

	ldqm_sdram	       =>  ldqm_sdram,
	udqm_sdram	       =>  udqm_sdram,
	
	ba_sdram	       =>  ba_sdram,
	add_sdram		       =>  add_sdram,
	dq_sdram	       =>  dq_sdram,
	
	-- System interface signals
	sys_clk		       =>  sys_clk_sig,
	reset		       =>  sys_rst,
    RD_EN              =>  RD_8051_EN,
    WR_EN              =>  WR_8051_EN,
	mc_data_in	       =>  data_8051_out_sig,
	mc_data_out        =>  data_8051_in_sig,
	mc_addr_bus	       =>  addr_8051_out_sig
     ) ;

inst_pll_12mhz : pll_12mhz
   port map
    (
    POWERDOWN => '1',
    CLKA      => clk,
    LOCK      => lock,
    GLA       => sys_clk_sig,
    GLB       => sys_clk_in
    ) ;

	-- initialize signals
	GND_sig		<= '0';
	VCC_sig		<= '1';
	zeroes		<= (others => '0');
	ones		<= (others => '1');


    clk8051 <= sys_clk_sig ;
    nclk<=not(sys_clk_sig);
    nreset <= sys_rst;
    dbgmempswr_sig <= not(dbgmempswr);
    mempsrd_sig <= not mempsrd ;

--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
    -- instantiate Core8051 macro
	-- (unused inputs connected to static values, unused
	-- outputs left unconnected)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

	CORE8051_inst : CORE8051
    generic map (
        USE_OCI                 => 1,
        USE_UJTAG               => 1,
        TRACE_DEPTH             => 0,
        TRIG_NUM                => 0,
        NRSTOUT                 => 1,
        EN_FF_OPTS              => 0

    )
	port map (
		nreset		=> nreset,
		nrsto		=> open,
		nrsto_nc	=> open,

		clk			=> clk8051,
		clkcpu		=> clk8051,
		clkper		=> clk8051,

		clkcpu_en	=> open,
		clkper_en	=> open,

		port0i		=> p0i,
		port1i		=> p1i,
		port2i		=> p2i,
		port3i		=> p3i,

		port0o		=> p0o,
		port1o		=> p1o,
		port2o		=> p2o,
		port3o		=> p3o,

		int0		=> GND_sig,
		int1		=> GND_sig,
		int0a		=> GND_sig,
		int1a		=> GND_sig,
		int2		=> GND_sig,
		int3		=> GND_sig,
		int4		=> GND_sig,
		int5		=> GND_sig,
		int6		=> GND_sig,
		int7		=> GND_sig,

		t0			=> GND_sig,
		t1			=> GND_sig,
 
		movx		=> open,
		rxd0o		=> open,
       	txd0		=> open,
		rxd0i		=> GND_sig,

          -- code/ xdata memory
		dbgmempswr	=> dbgmempswr ,

		mempsacki	=> VCC_sig,
		memacki		=> VCC_sig,
		memdatai	=> memdatai,
		mempsacko	=> open,
		memdatao	=> memdatao ,  
		memaddr		=> memaddr,
		mempsrd		=> mempsrd,
		memwr		=> memwr,
		memrd		=> memrd,
  
    -- data memory       
		ramdatai	=> ramdatai,
		ramdatao	=> ramdatao,
		ramaddr		=> ramaddr,
		ramwe		=> ramwe,
		ramoe		=> ramoe,

   -- sfr export bus
		sfrdatai	=> zeroes(7 downto 0),
		sfrdatao	=> open,
		sfraddr		=> open,
		sfrwe		=> open,
		sfroe		=> open,

   -- JTAG interface for OCI
		TCK			=> TCK_s,
		TMS			=> TMS_s,
		TDI			=> TDI_s,
		TDO			=> TDO_s,
		TRSTB		=> TRSTB_s,

		BreakIn		=> GND_sig,
		BreakOut	=> open,
		membank		=> zeroes(3 downto 0),

		TrigOut		=> open,
		AuxOut		=> open,
		TraceA		=> open,
		TraceDI		=> open,
		TraceDO		=> zeroes(19 downto 0),
		TraceWr		=> open

	);


 process (nreset, clk) 
begin
        if (nreset = '0') then
            csn_s <= '1';
        elsif rising_edge (clk) then
            csn_s <= '0';
        end if;
end process ;

process (nreset, clk, rxd) 
begin
        if (nreset = '0') then
            rxd_s <= '1';
        elsif rising_edge (clk) then
            rxd_s <= rxd;
        end if;
end process ;


--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- UART inst
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

CoreUART_cmp_inst: uart_core 
    port map(
        -- Inputs
        BAUD_VAL   => "01001101",-- [for 12 mhz /9600]
        BIT8       => '1',
        CLK        => clk8051,
        CSN        => csn_s,
        DATA_IN    => data_in_s,
        ODD_N_EVEN => '0',
        OEN        => oen_s,
        PARITY_EN  => '0',
        RESET_N    => nreset,
        RX         => rxd_s,
        WEN        => wen_s,
        -- Outputs
        DATA_OUT   => data_uart,
        OVERFLOW   => overflow_f,
        PARITY_ERR => parityerr_f,
        RXRDY      => rxrdy_f,
        TX         => txd,
        TXRDY      => txrdy_f
    );

process (nreset, clk, oen_s, data_uart)
begin
    if (nreset = '0') then
        data_oled   <= (others => '0');
    elsif (clk'event and clk = '0') then
      if (oen_s = '0') then
        data_oled   <= data_uart ;
      end if;
    end if;
end process;

process (nreset, clk8051)
begin
    if (nreset = '0') then
       oen1_s <= '1' ;
       oen2_s <= '1' ;
    elsif (clk8051'event and clk8051 = '0') then
       oen1_s <= p2o(0) ;
       oen2_s <= oen1_s ;
    end if;
end process ;

oen_s <= '0' when (oen1_s = '0' and oen2_s = '1') else '1' ;

process (nreset, clk8051)
begin
    if (nreset = '0') then
       wen1_s <= '1' ;
       wen2_s <= '1' ;
    elsif (clk8051'event and clk8051 = '0') then
       wen1_s <= p3o(0) ;
       wen2_s <= wen1_s ;
    end if;
end process ;

wen_s <= '0' when (wen1_s = '0' and wen2_s = '1') else '1' ;

p1i <= data_oled ;

p2i(0) <= rxrdy_f ;

p2i(7 downto 1) <= "0000000" ;

p3i(0) <= txrdy_f ;

p3i(7 downto 1) <= "0000000" ;

data_in_s <= p0o;

--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Program memory Ram5kx8 inst
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

u1: Ram5kx8  
    port map
    (  
      WD     => memdatao,
      RD     => mem_data,
      WEN    => dbgmempswr,
      REN   => mempsrd,
      WADDR  => memaddr(ASIZE-1 downto 0),
      RADDR  => memaddr(ASIZE-1 downto 0),
      WCLK   => clk8051, 
      RCLK   => nclk 
     ) ;

 ramwe_sig <= not(ramwe) ;
 ramoe_sig <= not(ramoe) ;

--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Data memory Ram256x8 inst
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

u2: Ram256x8 
    port map
    ( 
      WD    => ramdatao,
      RD    => ramdatai,
      WEN   => ramwe,
      REN   => ramoe,
      WADDR => ramaddr,
      RADDR => ramaddr,
      WCLK  => clk8051, 
      RCLK  => nclk 
     ) ;

end mobile_sdram_Interface_archi;

--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- End of file
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------



