-- VHDL Design :                                                              --
--         Design     : Mobile SDRAM Interface                                --
--         File name  : mobile_sdram_core.vhd                                 --
--                                                                            --
--         Created by : Himanshu Tewari                                       --
--                    :                                                       --
--         on         :                                                       --
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-- Description: The Mobile SDRAM Interface IP described in this design        --
--includes a generic system interface. . The system interface illustrates the -- 
--control signals needed for the SDRAM logic block.                           --
                                                                              --
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-- Modification History                                                       --
--                                                                            --
-- Initial revision                                                           --
--                                                                            --
-- Revision 1.0                                                               --
--         by         :                                                       --
--         on         :                                                       --
-- Modifications to                                                           --
--   1.                                                                       --
--                                                                            --
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--                               L I B R A R Y                                --
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library IEEE;  

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library igloo; 

use work.pkg_constants.all;

--------------------------------------------------------------------------------
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--                               E N T I T Y                                  --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity mobile_sdram_core is

    generic (
        -- local address bus size
        SDRAM_RASIZE    : integer := 24;  
        -- max number of sdram column bits 
        SDRAM_COLBITS   : integer := 9;   
        -- max number of sdram bank bits
        SDRAM_BANKBITS  : integer := 2;  
        -- max number of sdram row bits  
        SDRAM_ROWBITS   : integer := 12;   
        -- max number of sdram row bits
        SDRAM_DATABITS   : integer := 16   
        );

port(	
	-- Mobile SDRAM interface signals
    -- Mobile SDRAM clock
	clk_to_sdram	: out	STD_LOGIC;
    -- Active high clock enable			
	CLKENB_SDRAM	: out 	STD_LOGIC;	
    -- Active low chip select		
	NCS_SDRAM	: out	STD_LOGIC;
    -- Active low CAS			
	NCAS_SDRAM	: out	STD_LOGIC;		
    -- Active low RAS	
	NRAS_SDRAM	: out	STD_LOGIC;	
    -- Active low write enable		
	NWE_SDRAM	: out	STD_LOGIC;			
    -- Lower data byte mask
	LDQM_SDRAM	: out	STD_LOGIC;
    -- Upper data byte mask
	UDQM_SDRAM	: out	STD_LOGIC;			
	-- Bank address
	BA_SDRAM	: out	STD_LOGIC_VECTOR ((SDRAM_BANKBITS - 1) downto 0);
    -- SDRAM address bus	
	ADD_SDRAM		: out	STD_LOGIC_VECTOR ((SDRAM_ROWBITS - 1) downto 0);	
    -- SDRAM data bus
	DQ_SDRAM	: inout	STD_LOGIC_VECTOR ((SDRAM_DATABITS - 1) downto 0);	
    	
	-- System interface signals

    -- System clock	
	sys_clk	 	: in	STD_LOGIC;	
    -- System reset (active low)
	RESET		: in 	STD_LOGIC;	
    -- Active high read enable
    RD_EN       : in 	STD_LOGIC;
    -- Active high write enable
    WR_EN       : in 	STD_LOGIC;	
    -- System test data		
	mc_data_in : in  STD_LOGIC_VECTOR ((SDRAM_DATABITS - 1) downto 0);	
    -- System test data
	mc_data_out: out  STD_LOGIC_VECTOR ((SDRAM_DATABITS - 1) downto 0);
    -- System address bus	
	mc_addr_bus	: in 	STD_LOGIC_VECTOR ((SDRAM_RASIZE - 1) downto 0)	
   	);

end mobile_sdram_core;

--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--                         A R C H I T E C T U R E                            --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture mobile_sdram_core_archi of mobile_sdram_core is

-- CONSTANT DECLARATIONS 
-- Note: see pkg_constants

-- SDRAM state machine state type
type SDRAM_STATE_TYPE is ( IDLE, PRECHRG_ST, RFSH_ST,SELF_RFSH_ST,delay_SELF_RFSH,LOAD_MR_ST, DPD_ST,
			 ACTIVE_ST, WAIT_READ_ST, WAIT_READ_ST1 , WAIT_READ_ST2, READ_ST, 
			 CAS_DELAY_ST, READ_DATA_ST, WAIT_WRITE_ST, WAIT_WRITE_ST1, WAIT_WRITE_ST2, WRITE_ST, 
			 WRITE_DATA_ST, WAIT_TWR, WAIT_TRP );

-- Synchronous state machine state identifiers
signal sdram_prs_state, sdram_nxt_state : SDRAM_STATE_TYPE;


-- SDRAM initialisation  state machine state type
type INIT_STATE_TYPE is ( IDLE_ST, PRECHRG_CMD1, PRECHRG_IDLE, LOAD_MR_CMD11, LOAD_MR_CMD12, 
     LOAD_MR_CMD21, LOAD_MR_CMD22,EXT_LOAD_MR_CMD2,EXT_LOAD_MR_CMD1, PRECHRG_CMD2,PRECHRG_CMD3, delay3,delay4, REFRESH1, NOP100NS1, REFRESH2, NOP100NS2, INIT_COMPLETE);

-- Synchronous state machine state identifiers
signal init_prs_state, init_nxt_state : INIT_STATE_TYPE;

-- SDRAM selfrefresh state machine state type
type SELF_REFRESH_ST_TYPE is ( IDLE_RFS, SELF_REFRESH_ST,NOP100NS3,NOP100NS4,SLF_RFSH_EXIT);

-- Synchronous state machine state identifiers
signal SLF_RFSH_NSTATE, SLF_RFSH_PSTATE : SELF_REFRESH_ST_TYPE;


-- Enable write to SDRAM mode register (MR)
signal ld_mr : STD_LOGIC;

-- Enable assertion of row address on SDRAM address bus
signal row_sdram_en : STD_LOGIC;

-- Active high SDRAM read enable (CPLD)
signal sdram_read_en : STD_LOGIC;

-- Active high SDRAM write enable (CPLD)
signal sdram_write_en : STD_LOGIC;

-- Write burst counter signals (4-bit counter)
signal wr_brst_cnt_en, wr_brst_load, wr_brst_clr : STD_LOGIC;
signal wr_brst_data, wr_brst_qout : STD_LOGIC_VECTOR (3 downto 0);

-- Read burst counter signals (4-bit counter)
signal rd_brst_cnt_en, rd_brst_load, rd_brst_clr : STD_LOGIC;
signal rd_brst_data, rd_brst_qout : STD_LOGIC_VECTOR (3 downto 0);

-- Burst length register (same for read or write operations)
signal burst_len : STD_LOGIC_VECTOR (3 downto 0);

-- CAS latency register
signal cas_lat : STD_LOGIC_VECTOR (1 downto 0);

-- CAS latency counter signals (2-bit counter)
signal cas_cnt_en, cas_load, cas_clr : STD_LOGIC;
signal cas_qout, cas_data : STD_LOGIC_VECTOR (1 downto 0);

-- Internal combinational SDRAM control signals
signal CLKENB_SDRAM_com, NCS_SDRAM_com, NRAS_SDRAM_com, NCAS_SDRAM_com, NWE_SDRAM_com : STD_LOGIC;

-- Internal SDRAM control signals
signal CLKENB_SDRAM_int, NCS_SDRAM_int, NRAS_SDRAM_int, NCAS_SDRAM_int, NWE_SDRAM_int : STD_LOGIC;

-- Internal SDRAM address signals

signal BA_SDRAM_int : STD_LOGIC_VECTOR ((SDRAM_BANKBITS - 1) downto 0);
signal ADD_SDRAM_int  : STD_LOGIC_VECTOR ((SDRAM_ROWBITS - 1) downto 0);

-- Registered system control, address, and data signals
signal sys_cmd_int  : STD_LOGIC_VECTOR (3 downto 0);
signal mc_addr_bus_int : STD_LOGIC_VECTOR ((SDRAM_RASIZE - 1) downto 0);
signal mc_data_int : STD_LOGIC_VECTOR ((SDRAM_DATABITS - 1) downto 0);

-- CPLD SDRAM mode and extended mode registers
signal mode_reg, ext_mode_reg : STD_LOGIC_VECTOR ((SDRAM_ROWBITS - 1) downto 0);

-- Data bus during SDRAM read cycle
signal sys_data_rd : STD_LOGIC_VECTOR ((SDRAM_DATABITS - 1) downto 0);

-- OE signal for system data bus during read operations
signal sdram_rd_oe : STD_LOGIC;

-- signals for self refresh cycle
signal self_refresh_sig : STD_LOGIC;
signal SLF_RFSH_COM,EXIT_SLF_RFSH : STD_LOGIC;
signal SYS_CMD_SLF_RFSH : STD_LOGIC_VECTOR (3 downto 0);

-- initialisation signals
signal	sys_cmd, sys_cmd_init	: STD_LOGIC_VECTOR (3 downto 0);
signal  counter_100us : STD_LOGIC_VECTOR (13 downto 0);
signal  counter_100ns : STD_LOGIC_VECTOR (3 downto 0); 
signal  sig_100ns, init_com, start_init, lock_sig, init_com_start : STD_LOGIC ; 
signal  mc_addr_bus_init : STD_LOGIC_VECTOR ((SDRAM_RASIZE - 1) downto 0) ;


--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Component UPCNT2, 2-bit counter for counting CAS length.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
component UPCNT2
port(	      
    -- Parallel data in	      
	data         : in STD_LOGIC_VECTOR (1 downto 0); 
    -- Count enable   	
	cnt_en       : in STD_LOGIC;       
    -- Load line enable                 	
	load         : in STD_LOGIC;    
    -- Active low clear                    	
	clr          : in STD_LOGIC;  
    -- Clock                      	
	clk          : in STD_LOGIC;  
    -- Parallel data out                      	
	qout         : inout STD_LOGIC_VECTOR (1 downto 0)
	);
	
end component;

--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Component:UPCNT4,4-bit counter for counting burst length.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
component UPCNT4
port(	      
    -- Parallel data in    
	data         : in STD_LOGIC_VECTOR (3 downto 0);
    -- Count enable    	
	cnt_en       : in STD_LOGIC; 
    -- Load line enable                       	
	load         : in STD_LOGIC;
    -- Active low clear                        	
	clr          : in STD_LOGIC;   
    -- Clock                     	
	clk          : in STD_LOGIC;    
    -- Parallel data out                    	
	qout         : inout STD_LOGIC_VECTOR (3 downto 0)
	);
	
end component;

begin

clk_to_sdram <= sys_clk ;

----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
--State Machine for SELF Refresh 
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------

  process(sys_clk,RESET)
  begin
         if ( RESET  = RESET_ACTIVE ) then
             SLF_RFSH_PSTATE <= IDLE_RFS;
        elsif sys_clk'event and sys_clk = '0' then
             SLF_RFSH_PSTATE <= SLF_RFSH_NSTATE ;
        end if;
  end process;

  process(SLF_RFSH_PSTATE, self_refresh_sig,RD_EN,WR_EN)
  begin
             case (SLF_RFSH_PSTATE) is
               
                when IDLE_RFS =>  

                   if (self_refresh_sig = '1') then
                       SLF_RFSH_NSTATE <= SELF_REFRESH_ST;
                   else
                       SLF_RFSH_NSTATE <= IDLE_RFS;
                   end if;

                when SELF_REFRESH_ST => 

                    if (RD_EN = '1' or WR_EN = '1') then
                        SLF_RFSH_NSTATE <= NOP100NS3;
                    else
                        SLF_RFSH_NSTATE <= SELF_REFRESH_ST;
                    end if;

                when NOP100NS3 => 
                    SLF_RFSH_NSTATE <= NOP100NS4;

                when NOP100NS4 => 
                    SLF_RFSH_NSTATE <= SLF_RFSH_EXIT;

                when SLF_RFSH_EXIT => 
                    SLF_RFSH_NSTATE <= IDLE_RFS;

                when others => 
                    SLF_RFSH_NSTATE <= IDLE_RFS;

            end case;
    end process;


    process(SLF_RFSH_PSTATE)
    begin
             case (SLF_RFSH_PSTATE) is
               
               when IDLE_RFS =>   
               SLF_RFSH_COM <= '0' ; 
               SYS_CMD_SLF_RFSH  <= "0001";


               when SELF_REFRESH_ST =>   
               SLF_RFSH_COM <= '1' ; 
               SYS_CMD_SLF_RFSH  <= SELF_REFRESH; 


               when NOP100NS3 =>   
               SLF_RFSH_COM <= '0' ; 
               SYS_CMD_SLF_RFSH  <= "0001";


               when NOP100NS4 =>   
               SLF_RFSH_COM <= '0' ; 
               SYS_CMD_SLF_RFSH  <= "0001";


               when SLF_RFSH_EXIT =>   
               SLF_RFSH_COM <= '0' ; 
               SYS_CMD_SLF_RFSH  <= "0001";
            
            end case;
    end process;

----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Process for Initial 100 us delay
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------

   process(sys_clk,RESET, counter_100us, init_com )
   begin
        if (RESET = RESET_ACTIVE) then
            counter_100us <= (others => '0');
        elsif sys_clk'event and sys_clk = '1' then
          if init_com = '0' then		
            counter_100us <= (others => '0');
          else
            counter_100us <= counter_100us + '1' ;
          end if;
        end if;
   end process ;

start_init <= '0' when init_com_start = '0' else '1';

----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
--tRFC delay
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
   process(sys_clk,RESET, sig_100ns, counter_100ns )
   begin
        if (RESET = RESET_ACTIVE) then
            counter_100ns <= (others => '0');
        elsif sys_clk'event and sys_clk = '0' then
          if sig_100ns = '0' or counter_100ns = "1001" then		
            counter_100ns <= (others => '0');
          else
            counter_100ns <= counter_100ns + '1' ;
          end if;
        end if;
   end process ;

----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
--State Machine for Initialisation 
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------

  process(sys_clk,RESET )
  begin
         if ( RESET = RESET_ACTIVE ) then
             init_prs_state <= IDLE_ST ;
        elsif sys_clk'event and sys_clk = '0' then
             init_prs_state <= init_nxt_state ;
        end if;
  end process;

  process(init_prs_state, start_init, counter_100ns,RD_EN,WR_EN)
  begin
            case (init_prs_state) is
                when IDLE_ST =>  
                    if (start_init = '1') then
                        init_nxt_state <= PRECHRG_CMD1;
                    else
                        init_nxt_state <= IDLE_ST;
                    end if;

                when PRECHRG_CMD1 => 
                    init_nxt_state <= PRECHRG_IDLE ;

                when PRECHRG_IDLE => 
                    init_nxt_state <= LOAD_MR_CMD11; 

                when LOAD_MR_CMD11 => 
                    init_nxt_state <= LOAD_MR_CMD12;

                when LOAD_MR_CMD12 => 
                    init_nxt_state <= LOAD_MR_CMD21;

                when LOAD_MR_CMD21 => 
                    init_nxt_state <= LOAD_MR_CMD22;

                when LOAD_MR_CMD22 => 
                    init_nxt_state <= PRECHRG_CMD2 ;

                when PRECHRG_CMD2 => 
                    init_nxt_state <= delay3;

                when delay3 => 
                    init_nxt_state <= EXT_LOAD_MR_CMD1; 

                when EXT_LOAD_MR_CMD1 => 
                    init_nxt_state <= EXT_LOAD_MR_CMD2;

                when EXT_LOAD_MR_CMD2 => 
                    init_nxt_state <= PRECHRG_CMD3;
               
                when PRECHRG_CMD3 => 
                    init_nxt_state <= delay4;

                when delay4 => 
                    init_nxt_state <= REFRESH1;

                when REFRESH1 => 
                    init_nxt_state <= NOP100NS1;

                when NOP100NS1 => 
                    if counter_100ns < "1001" then
                        init_nxt_state <= NOP100NS1 ;
                    else
                        init_nxt_state <= REFRESH2;
                    end if;

                when REFRESH2 => 
                    init_nxt_state <= NOP100NS2;

                when NOP100NS2 => 
                    if counter_100ns < "1001" then
                        init_nxt_state <= NOP100NS2;
                    else
                        init_nxt_state <= INIT_COMPLETE;
                    end if;

                when INIT_COMPLETE => 
                    init_nxt_state <= INIT_COMPLETE;

                when others => 
                    init_nxt_state <= IDLE_ST;
                end case ;
  end process;

  process(init_prs_state)
  begin
             case (init_prs_state) is
               
               when IDLE_ST =>  
               sig_100ns <= '0' ; 
               init_com_start <= '1' ; 
               init_com <= '1' ; 
               sys_cmd_init  <= "0001" ; 
               mc_addr_bus_init <= (others => '0');

               when PRECHRG_CMD1 => 
               sig_100ns <= '0' ; 
               init_com_start <= '0' ; 
               init_com <= '1'; 
               sys_cmd_init  <= PRECHARGE ; 
               mc_addr_bus_init <= "00" & "000000000" & "0001000000000";

               when PRECHRG_IDLE => 
               sig_100ns <= '0' ; 
               init_com_start <= '0' ; 
               init_com <= '1';  
               sys_cmd_init  <= "0001" ; 
               mc_addr_bus_init <= "00" & "000000000" & "0001000000000";

               when LOAD_MR_CMD11 => 
               sig_100ns <= '0' ; 
               init_com_start <= '0' ; 
               init_com <= '1'; 
               sys_cmd_init  <= LOAD_MR ; 
               mc_addr_bus_init <= "00" & "000000000" & "0000000100000";

               when LOAD_MR_CMD12 => 
               sig_100ns <= '0' ; 
               init_com_start <= '0' ; 
               init_com <= '1';  
               sys_cmd_init  <= "0001" ; 
               mc_addr_bus_init <= "00" & "000000000" & "0000000100000";
               when LOAD_MR_CMD21 => 
               sig_100ns <= '0' ; 
               init_com_start <= '0' ; 
               init_com <= '1'; 
               sys_cmd_init  <= LOAD_MR; 
               mc_addr_bus_init <= "00" & "000000000" & "0000000110001";

               when LOAD_MR_CMD22 => 
               sig_100ns <= '0' ; 
               init_com_start <= '0' ; 
               init_com <= '1';  
               sys_cmd_init  <= "0001" ; 
               mc_addr_bus_init <= "00" & "000000000" & "0000000110001";

               when EXT_LOAD_MR_CMD1 => 
               sig_100ns <= '0' ; 
               init_com_start <= '0' ; 
               init_com <= '1';  
               sys_cmd_init  <= LOAD_MR ; 
               mc_addr_bus_init <= "10" & "000000000" & "0000000000000";

               when EXT_LOAD_MR_CMD2 => 
               sig_100ns <= '0' ; 
               init_com_start <= '0' ; 
               init_com <= '1';  
               sys_cmd_init  <= "0001" ; 
               mc_addr_bus_init <= "10" & "000000000" & "0000000110001";

               when PRECHRG_CMD2 => 
               sig_100ns <= '0' ; 
               init_com_start <= '0' ; 
               init_com <= '1'; 
               sys_cmd_init  <= PRECHARGE ; 
               mc_addr_bus_init <= "00" & "000000000" & "0001000000000";
               
               when PRECHRG_CMD3 => 
               sig_100ns <= '0' ; 
               init_com_start <= '0' ; 
               init_com <= '1'; 
               sys_cmd_init  <= PRECHARGE ; 
               mc_addr_bus_init <= "00" & "000000000" & "0001000000000";               

               when delay3 => 
               sig_100ns <= '0' ; 
               init_com_start <= '0' ; 
               init_com <= '1';  
               sys_cmd_init  <= "0001" ; 
               mc_addr_bus_init <= "00" & "000000000" & "0001000000000";
               
               when delay4 => 
               sig_100ns <= '0' ; 
               init_com_start <= '0' ; 
               init_com <= '1';  
               sys_cmd_init  <= "0001" ; 
               mc_addr_bus_init <= "00" & "000000000" & "0001000000000";

               when REFRESH1 => 
               sig_100ns <= '0' ; 
               init_com_start <= '0' ; 
               init_com <= '1'; 
               sys_cmd_init  <= REFRESH ; 

               when NOP100NS1 => 
               sig_100ns <= '1' ; 
               init_com_start <= '0' ; 
               init_com <= '1'; 
               sys_cmd_init  <= "0001" ; 

               when REFRESH2 => 
               sig_100ns <= '0' ; 
               init_com_start <= '0' ; 
               init_com <= '1'; 
               sys_cmd_init  <= REFRESH; 

               when NOP100NS2 => 
               sig_100ns <= '1' ; 
               init_com_start <= '0' ; 
               init_com <= '1'; 
               sys_cmd_init  <= "0001" ; 

               when INIT_COMPLETE => 
               sig_100ns <= '0' ; 
               init_com_start <= '0' ; 
               init_com <= '0'; 
               sys_cmd_init  <= "0001" ; 


               when others => 
               sig_100ns <= '0' ; 
               init_com_start <= '0' ; 
               init_com <= '1'; 
               sys_cmd_init  <= "0001" ; 
               mc_addr_bus_init <= (others => '0');

            end case ;

  end process;

----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- process for assigning the command enable value
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
    process (sys_clk, RESET,SLF_RFSH_COM,init_com,WR_EN,RD_EN)
	begin
    	if   (sdram_prs_state = WAIT_WRITE_ST or sdram_prs_state = WAIT_READ_ST or  RESET = RESET_ACTIVE ) then
               sys_cmd <= "0001" ;
        elsif (sys_clk'event and sys_clk = '1') then 
    	   if (init_com = '1') then
               sys_cmd <= sys_cmd_init ;
    	   elsif (SLF_RFSH_COM = '1') then
               sys_cmd <= SYS_CMD_SLF_RFSH ;
           elsif (WR_EN = '1') then
               sys_cmd <= WRITE ;
           elsif (RD_EN = '1') then
               sys_cmd <= READ ;
           end if;
		end if;		
	end process ;


--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- COMPONENT INSTANTIATION
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------	
	-- Component: CAS_CNT
	-- Purpose:   2-bit counter to wait specified CAS latency.

	CAS_CNT : UPCNT2
	port map (		      
		data       =>  cas_data,   	  
		cnt_en     =>  cas_cnt_en,         
		load       =>  cas_load,         
		clr        =>  cas_clr,       	  
		clk        =>  sys_clk,   
		qout       =>  cas_qout ); 


	-- Component: WR_BRST_CNT
	-- Purpose:   4-bit counter to count write burst length.
	WR_BRST_CNT : UPCNT4
	port map (		      
		data       =>  wr_brst_data,   	  
		cnt_en     =>  wr_brst_cnt_en,         
		load       =>  wr_brst_load,         
		clr        =>  wr_brst_clr,       	  
		clk        =>  sys_clk,     
		qout       =>  wr_brst_qout );
		
		
	-- Component: RD_BRST_CNT
	-- Purpose:   4-bit counter to count read burst length.
	RD_BRST_CNT : UPCNT4
	port map (		      
		data       =>  rd_brst_data,   	  
		cnt_en     =>  rd_brst_cnt_en,         
		load       =>  rd_brst_load,         
		clr        =>  rd_brst_clr,       	  
		clk        =>  sys_clk,     
		qout       =>  rd_brst_qout );	
		
	
--SIGNAL DEFINITIONS

	CLKENB_SDRAM <= CLKENB_SDRAM_int;	
	NCS_SDRAM <= NCS_SDRAM_int;
	NCAS_SDRAM <= NCAS_SDRAM_int;
	NRAS_SDRAM <= NRAS_SDRAM_int;
	NWE_SDRAM <= NWE_SDRAM_int;

	LDQM_SDRAM <= '0';
	UDQM_SDRAM <= '0';

	BA_SDRAM <= BA_SDRAM_int;	
	ADD_SDRAM	<= ADD_SDRAM_int;		
	
	-- Bi-directional SDRAM DQ bus
	DQ_SDRAM <= mc_data_int when (sdram_write_en = '1') else (others => 'Z');
    -- Exit signal from self refresh state
    EXIT_SLF_RFSH <= RD_EN or WR_EN;

    process (sdram_read_en, RESET)
	begin
  	   if (RESET = RESET_ACTIVE) then
	        mc_data_out <= (others => '0');
  	   elsif (sdram_read_en = '1') then
	        mc_data_out <= DQ_SDRAM ; 
       end if;
	end process ;
	-- Default values: never loading counters	
	cas_data <= (others => '0');
	cas_load <= '0';	
	
	wr_brst_data <= (others => '0');
	rd_brst_data <= (others => '0');
	
	wr_brst_load <= '0'; 
	rd_brst_load <= '0';  		
	
	wr_brst_cnt_en <= '1' when (sdram_prs_state = WRITE_DATA_ST) else '0';
	rd_brst_cnt_en <= '1' when (sdram_prs_state = READ_DATA_ST) else '0';
	
	-- Assign burst length register
	burst_len <="0001" when (mode_reg (2 downto 0) = "000") else
			    "0010" when (mode_reg (2 downto 0) = "001") else
		       	"0100" when (mode_reg (2 downto 0) = "010") else
		       	"1000" when (mode_reg (2 downto 0) = "011") else
		       	"1111";
	
	-- Assign CAS latency register
	cas_lat <= mode_reg (5 downto 4);


--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Register system command signal (sys_cmd), system
-- address bus (mc_addr_bus), and system data bus (sys_data).
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

	SYS_CMD_REG: process (sys_clk, RESET)
	begin	
		if (RESET = RESET_ACTIVE) then		
			sys_cmd_int <= (others => '0');
			mc_addr_bus_int <= (others => '0');
			mc_data_int <= (others => '0');
				
		elsif (sys_clk'event and sys_clk = '0') then  --change 4-6-08
			sys_cmd_int <= sys_cmd;
			mc_data_int <= mc_data_in;
                if init_com = '1' then
			        mc_addr_bus_int <= mc_addr_bus_init;
                elsif  ( WR_EN = '1' or RD_EN = '1' ) then
			        mc_addr_bus_int <= mc_addr_bus;
               end if;			
		end if;				
	end process SYS_CMD_REG;

				
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--	Assign the SDRAM address bus (add_sdram) and mode registers.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

	SDRAM_ADDR: process (sys_clk, RESET, ld_mr, row_sdram_en, mc_addr_bus_int)  
	begin
	
		if (RESET = RESET_ACTIVE) then		
			ADD_SDRAM_int <= (others => '0');
			mode_reg <= (others => '0');
			ext_mode_reg <= (others => '0');
		
		elsif (sys_clk'event and sys_clk = '0') then --change 4-6-08
		
			-- Assign mode register data

			if (ld_mr = '1') then
				ADD_SDRAM_int <= mc_addr_bus_int ((SDRAM_ROWBITS - 1) downto 0);
				
				-- If write to mode register - save data
                if (mc_addr_bus_int ((SDRAM_COLBITS + SDRAM_ROWBITS + 2) downto (SDRAM_COLBITS + SDRAM_ROWBITS +1 )) = "00") then 
                    mode_reg <= mc_addr_bus_int ((SDRAM_ROWBITS - 1) downto 0);	
				-- If write to extended mode register - save data
                elsif (mc_addr_bus_int ((SDRAM_COLBITS + SDRAM_ROWBITS + 2) downto (SDRAM_COLBITS + SDRAM_ROWBITS +1 )) = "10") then
					ext_mode_reg <= mc_addr_bus_int ((SDRAM_ROWBITS - 1) downto 0);
				end if;

			-- Assign row address data
			elsif (row_sdram_en = '1') then		
				ADD_SDRAM_int <= mc_addr_bus_int ((SDRAM_ROWBITS - 1) downto 0);			
			else
			-- Assign column address data 
			-- Enable Auto Precharge
                ADD_SDRAM_int <= "010" & mc_addr_bus_int ((SDRAM_COLBITS + SDRAM_ROWBITS - 1) downto SDRAM_ROWBITS);	
			end if;		
		end if;	
	
	end process SDRAM_ADDR;
	
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--Assign bank address from mc_addr_bus_int during an ACTIVE,
--READ, WRITE, or PRECHARGE command.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
	
	ASSIGN_BA: process (RESET, sys_clk, sdram_prs_state)
	begin
		if (RESET = RESET_ACTIVE) then		
			BA_SDRAM_int <= (others => '0');
				
		elsif (sys_clk'event and sys_clk = '0') then --change 4-6-08
		
			if (sdram_prs_state = ACTIVE_ST) or (sdram_prs_state = READ_ST) or 
			   (sdram_prs_state = WRITE_ST) or (sdram_prs_state = PRECHRG_ST) or 
			   (sdram_prs_state = LOAD_MR_ST) or (sdram_prs_state = WRITE_DATA_ST) then
		
				BA_SDRAM_int <= mc_addr_bus_int ((SDRAM_COLBITS + SDRAM_ROWBITS + 1) downto (SDRAM_COLBITS + SDRAM_ROWBITS )); -- tushar changed on 22nd October 2008
                				
			else
				BA_SDRAM_int <= (others => '0');				
			end if;	
		end if;
	
	end process ASSIGN_BA;	
	
	
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Capture data in read cycle from SDRAM. Create OE signal
--	for system data bus.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

	RD_DATA: process (sys_clk, RESET, sdram_read_en)
	begin	
		if (RESET = RESET_ACTIVE) then		
			sys_data_rd <= (others => '0');
			sdram_rd_oe <= '0';

		-- Capture data on rising edge of SDRAM clock
		elsif (sys_clk'event) and (sys_clk = '1') then
					
			-- Use SDRAM read enable signal as CE
			if (sdram_read_en = '1') then				
				
				-- Use value of burst counter to determine
				-- data byte currently being read
				-- Size of data captured depends on burst size
				sys_data_rd ((SDRAM_DATABITS - 1) downto 0) <= DQ_SDRAM;
											
			end if;		
			
			sdram_rd_oe <= sdram_read_en;
			
		end if;
	
	end process RD_DATA;

	 		
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--Synchronize SDRAM controller state machine (SDRAM_CNTR)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

	SEQ: process (sys_clk, RESET, sdram_nxt_state)
	begin	
		if RESET = RESET_ACTIVE then			
			sdram_prs_state <= IDLE;
			
			CLKENB_SDRAM_int  <= '1';	
			NCS_SDRAM_int  <= '0';
			NRAS_SDRAM_int <= '1';
			NCAS_SDRAM_int <= '1';
			NWE_SDRAM_int  <= '1';
								
		-- Change state on falling edge of system clock
		elsif sys_clk'event and sys_clk = '0' then --change 4-6-08
			sdram_prs_state <= sdram_nxt_state;
			 
			-- Register SDRAM control signals
			CLKENB_SDRAM_int <= CLKENB_SDRAM_com;	
			NCS_SDRAM_int <= NCS_SDRAM_com;
			NRAS_SDRAM_int <= NRAS_SDRAM_com;
			NCAS_SDRAM_int <= NCAS_SDRAM_com;
			NWE_SDRAM_int <= NWE_SDRAM_com;		
						
		end if;
		
	end process SEQ;

				 
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Main SDRAM controller state machine.  Interprets system
--commands (sys_cmd register) and executes SDRAM command cycle.
--Counts for burst cycle and CAS latency.  Asserts all
--SDRAM control signals: CKE, CS, RAS, CAS, WE.	
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

	SDRAM_CNTR: process (sdram_prs_state, cas_qout, wr_brst_qout, rd_brst_qout,EXIT_SLF_RFSH,sys_cmd_int,self_refresh_sig) -- tushar added sys_cmd_int
	begin	
		sdram_nxt_state <= sdram_prs_state;	-- Default SM conditions
		cas_clr <= not (RESET_ACTIVE);		-- No reset of CAS counter
		cas_cnt_en <= '0';			        -- Disable CAS counter
		ld_mr <= '0';				        -- Disable MR write
		row_sdram_en <= '0';			    -- Disable row address write
		sdram_read_en <= '0';			    -- Disable read to SDRAM
		sdram_write_en <= '0';			    -- Disable write to SDRAM
		wr_brst_clr <= not (RESET_ACTIVE);	-- No reset of write burst length counter
		rd_brst_clr <= not (RESET_ACTIVE);	-- No reset of read burst length counter		
		CLKENB_SDRAM_com <= CLKENB_SDRAM_int;	
		NCS_SDRAM_com <= NCS_SDRAM_int;
		NRAS_SDRAM_com <= NRAS_SDRAM_int;
		NCAS_SDRAM_com <= NCAS_SDRAM_int;
		NWE_SDRAM_com <= NWE_SDRAM_int;							
		case sdram_prs_state is
			    
			---------------------- IDLE State ---------------------
			when IDLE =>
		
				-- NOP command values
				CLKENB_SDRAM_com  <= '1';
				NCS_SDRAM_com  <= '0';
				NRAS_SDRAM_com <= '1';
				NCAS_SDRAM_com <= '1';
				NWE_SDRAM_com  <= '1';	
				
				-- Load Mode Register		
				if (sys_cmd_int = LOAD_MR) then
					sdram_nxt_state <= LOAD_MR_ST; 
					
				-- Precharge
				elsif (sys_cmd_int = PRECHARGE) then
					sdram_nxt_state <= PRECHRG_ST; 
					
				-- Refresh
				elsif (sys_cmd_int = REFRESH) then
					sdram_nxt_state <= RFSH_ST; 
								
				-- Read or Write => ACTIVE command state
				elsif (sys_cmd_int = READ) or (sys_cmd_int = WRITE) then
					sdram_nxt_state <= ACTIVE_ST;
				
				-- Deep Power Down
				elsif (sys_cmd_int = DEEP_PD) then
					sdram_nxt_state <= DPD_ST;	
                    	
                -- self refresh state
				elsif (sys_cmd_int = SELF_REFRESH) then
					sdram_nxt_state <= SELF_RFSH_ST;	                    	
				
				-- Else condition
				-- NOP, DESELECT, or BURST_TERM
				else
					sdram_nxt_state <= IDLE;					
				end if;	
				
				-- Clear CAS latency counter
				cas_clr <= RESET_ACTIVE;				
				cas_cnt_en <= '0';
                ld_mr <= '0';
                row_sdram_en <= '0';
                sdram_read_en <= '0';
                sdram_write_en <= '0';
                self_refresh_sig <= '0';
                wr_brst_clr <= not (RESET_ACTIVE);
                rd_brst_clr <= not (RESET_ACTIVE);				
			------------------ PRECHRG_ST State -------------------
			when PRECHRG_ST =>			
			
				-- Assign SDRAM command values (PRECHARGE)
				-- PRECHARGE = Deactivate row in bank or banks
				CLKENB_SDRAM_com  <= '1';
				NCS_SDRAM_com  <= '0';
				NRAS_SDRAM_com <= '0';
				NCAS_SDRAM_com <= '1';
				NWE_SDRAM_com  <= '0';
				
				sdram_nxt_state <= IDLE;
                								
				cas_clr <= not (RESET_ACTIVE);	
                self_refresh_sig <= '0';			
				cas_cnt_en <= '0';
                ld_mr <= '0';
                row_sdram_en <= '0';
                sdram_read_en <= '0';
                sdram_write_en <= '0';
                wr_brst_clr <= not (RESET_ACTIVE);
                rd_brst_clr <= not (RESET_ACTIVE);				
			
			--------------------- RFSH_ST State ------------------
			when RFSH_ST =>
			
				-- Assign SDRAM command values (REFRESH)
				CLKENB_SDRAM_com  <= '1';
				NCS_SDRAM_com  <= '0';
				NRAS_SDRAM_com <= '0';
				NCAS_SDRAM_com <= '0';
				NWE_SDRAM_com  <= '1';
							
				sdram_nxt_state <= IDLE;				
					
				cas_clr <= not (RESET_ACTIVE);	
                self_refresh_sig <= '0';			
				cas_cnt_en <= '0';
                ld_mr <= '0';
                row_sdram_en <= '0';
                sdram_read_en <= '0';
                sdram_write_en <= '0';
                wr_brst_clr <= not (RESET_ACTIVE);
                rd_brst_clr <= not (RESET_ACTIVE);			
                
                
			--------------------- SELF_RFSH_ST State ------------------
			when SELF_RFSH_ST =>
			
				-- Assign SDRAM command values (REFRESH)
				CLKENB_SDRAM_com  <= '0'; -- cke should be low for self refresh mode.
				NCS_SDRAM_com  <= '0';
				NRAS_SDRAM_com <= '0';
				NCAS_SDRAM_com <= '0';
				NWE_SDRAM_com  <= '1';

				if (EXIT_SLF_RFSH = '1')then			
				    sdram_nxt_state <= delay_SELF_RFSH;
                else
                    sdram_nxt_state <= SELF_RFSH_ST;
                end if;		
					
				cas_clr <= not (RESET_ACTIVE);	
                self_refresh_sig <= '0';			
				cas_cnt_en <= '0';
                ld_mr <= '0';
                row_sdram_en <= '0';
                sdram_read_en <= '0';
                sdram_write_en <= '0';
                wr_brst_clr <= not (RESET_ACTIVE);
                rd_brst_clr <= not (RESET_ACTIVE);   
                
            -----for delay after slef refresh cycle-----------------

			when delay_SELF_RFSH =>
			
				-- Assign SDRAM command values (REFRESH)
				CLKENB_SDRAM_com  <= '1'; 
				NCS_SDRAM_com  <= '0';
				NRAS_SDRAM_com <= '0';
				NCAS_SDRAM_com <= '0';
				NWE_SDRAM_com  <= '1';
				

				sdram_nxt_state <= IDLE;      
                
				cas_clr <= not (RESET_ACTIVE);	
                self_refresh_sig <= '0';			
				cas_cnt_en <= '0';
                ld_mr <= '0';
                row_sdram_en <= '0';
                sdram_read_en <= '0';
                sdram_write_en <= '0';
                wr_brst_clr <= not (RESET_ACTIVE);
                rd_brst_clr <= not (RESET_ACTIVE);                                         	
			
			----------------- LOAD_MR_ST State --------------------
			when LOAD_MR_ST =>
			
				-- Assign SDRAM command values (LOAD MODE REGISTER)
				CLKENB_SDRAM_com  <= '1';
				NCS_SDRAM_com  <= '0';
				NRAS_SDRAM_com <= '0';
				NCAS_SDRAM_com <= '0';
				NWE_SDRAM_com  <= '0';			
			
				sdram_nxt_state <= IDLE;

				cas_clr <= not (RESET_ACTIVE);	
                self_refresh_sig <= '0';			
				cas_cnt_en <= '0';
                ld_mr <= '1';
                row_sdram_en <= '0';
                sdram_read_en <= '0';
                sdram_write_en <= '0';
                wr_brst_clr <= not (RESET_ACTIVE);
                rd_brst_clr <= not (RESET_ACTIVE);				
				
			----------------- DPD_ST State --------------------
			when DPD_ST =>
			
				-- Assign SDRAM command values (DEEP POWER DOWN)
				-- SDRAM data is not retained in this state.
				CLKENB_SDRAM_com  <= '0';
				NCS_SDRAM_com  <= '0';
				NRAS_SDRAM_com <= '1';
				NCAS_SDRAM_com <= '1';
				NWE_SDRAM_com  <= '0';			
					
				-- Wait for system command to exit Deep Power Down state
				-- WAKE_UP command
				if (sys_cmd_int = WAKE_UP) then					
					sdram_nxt_state <= IDLE;
                        else                                 
					sdram_nxt_state <= DPD_ST;
				end if;						

				cas_clr <= not (RESET_ACTIVE);	
                self_refresh_sig <= '0';			
				cas_cnt_en <= '0';
                ld_mr <= '0';
                row_sdram_en <= '0';
                sdram_read_en <= '0';
                sdram_write_en <= '0';
                wr_brst_clr <= not (RESET_ACTIVE);
                rd_brst_clr <= not (RESET_ACTIVE);				
				
			------------------- ACTIVE_ST State -------------------
			when ACTIVE_ST =>		
				
				-- Assign SDRAM command values (ACTIVE)
				-- ACTIVE = Select bank and activate row
				CLKENB_SDRAM_com  <= '1';
				NCS_SDRAM_com  <= '0';
				NRAS_SDRAM_com <= '0';
				NCAS_SDRAM_com <= '1';
				NWE_SDRAM_com  <= '1';	
			
				-- During ACTIVE command, write row address to SDRAM
				-- Assert row_sdram_en
--				row_sdram_en <= '1';
			
				if (sys_cmd_int = READ) then
					sdram_nxt_state <= WAIT_READ_ST;
										
				elsif (sys_cmd_int = WRITE) then
					sdram_nxt_state <= WAIT_WRITE_ST;				
                        else                                
					sdram_nxt_state <= ACTIVE_ST;
				end if;

				cas_clr <= not (RESET_ACTIVE);				
                self_refresh_sig <= '0';
				cas_cnt_en <= '0';
                ld_mr <= '0';
                row_sdram_en <= '1';
                sdram_read_en <= '0';
                sdram_write_en <= '0';
                wr_brst_clr <= not (RESET_ACTIVE);
                rd_brst_clr <= not (RESET_ACTIVE);				
						
			------------------- WAIT_READ_ST State ---------------------
			when WAIT_READ_ST =>
			
				-- NOP command values
				CLKENB_SDRAM_com  <= '1';
				NCS_SDRAM_com  <= '0';
				NRAS_SDRAM_com <= '1';
				NCAS_SDRAM_com <= '1';
				NWE_SDRAM_com  <= '1';
			

				sdram_nxt_state <= WAIT_READ_ST1 ;
                						
				cas_clr <= not (RESET_ACTIVE);		
                self_refresh_sig <= '0';		
				cas_cnt_en <= '0';
                ld_mr <= '0';
                row_sdram_en <= '0';
                sdram_read_en <= '0';
                sdram_write_en <= '0';
                wr_brst_clr <= not (RESET_ACTIVE);
                rd_brst_clr <= not (RESET_ACTIVE);				

	
			------------------- WAIT_READ_ST1 State---------------------
			when WAIT_READ_ST1 =>
			
				-- NOP command values
				CLKENB_SDRAM_com  <= '1';
				NCS_SDRAM_com  <= '0';
				NRAS_SDRAM_com <= '1';
				NCAS_SDRAM_com <= '1';
				NWE_SDRAM_com  <= '1';
			
				sdram_nxt_state <= READ_ST ;						

				cas_clr <= not (RESET_ACTIVE);	
                self_refresh_sig <= '0';			
				cas_cnt_en <= '0';
                ld_mr <= '0';
                row_sdram_en <= '0';
                sdram_read_en <= '0';
                sdram_write_en <= '0';
                wr_brst_clr <= not (RESET_ACTIVE);
                rd_brst_clr <= not (RESET_ACTIVE);				


			------------------- READ_ST State ---------------------
			when READ_ST =>
			
				-- Assign SDRAM command values (READ)
				-- READ = Select bank and column, and start READ burst
				CLKENB_SDRAM_com  <= '1';
				NCS_SDRAM_com  <= '0';
				NRAS_SDRAM_com <= '1';
				NCAS_SDRAM_com <= '0';
				NWE_SDRAM_com  <= '1';	
				
				sdram_nxt_state <= CAS_DELAY_ST;				

				cas_clr <= not (RESET_ACTIVE);	
                self_refresh_sig <= '0';			
				cas_cnt_en <= '0';
                ld_mr <= '0';
                row_sdram_en <= '0';
                sdram_read_en <= '0';
                sdram_write_en <= '0';
                wr_brst_clr <= not (RESET_ACTIVE);
                rd_brst_clr <= (RESET_ACTIVE);				
							
			----------------- CAS_DELAY_ST State ------------------
			when CAS_DELAY_ST =>
			
				-- Assign SDRAM command values (NO OPERATION -- NOP)
				CLKENB_SDRAM_com  <= '1';
				NCS_SDRAM_com  <= '0';
				NRAS_SDRAM_com <= '1';
				NCAS_SDRAM_com <= '1';
				NWE_SDRAM_com  <= '1';			
			
				-- Enable CAS latency counter
			
				-- Wait for CAS delay (read value of Mode Reg)
				if (cas_qout < cas_lat) then
					sdram_nxt_state <= CAS_DELAY_ST;
				else
					sdram_nxt_state <= READ_DATA_ST;	
				end if;

				cas_clr <= not (RESET_ACTIVE);	
                self_refresh_sig <= '0';			
				cas_cnt_en <= '1';
                ld_mr <= '0';
                row_sdram_en <= '0';
                sdram_read_en <= '0';
                sdram_write_en <= '0';
                wr_brst_clr <= not (RESET_ACTIVE);
                rd_brst_clr <= not (RESET_ACTIVE);				
			
			----------------- READ_DATA_ST State -------------------
			when READ_DATA_ST =>			
			
				-- Assign SDRAM command values (NO OPERATION -- NOP)
				CLKENB_SDRAM_com  <= '1';
				NCS_SDRAM_com  <= '0';
				NRAS_SDRAM_com <= '1';
				NCAS_SDRAM_com <= '1';
				NWE_SDRAM_com  <= '1';
						
				-- Read data from SDRAM
--				sdram_read_en <= '1';

				-- Write until burst length complete
				-- Read burst length value stored in Mode Reg
				if (rd_brst_qout < burst_len) then					
					sdram_nxt_state <= READ_DATA_ST;
				else
                    sdram_nxt_state <= SELF_RFSH_ST;  
				end if;	
				self_refresh_sig <= '1';
				cas_clr <= not (RESET_ACTIVE);				
				cas_cnt_en <= '0';
                ld_mr <= '0';
                row_sdram_en <= '0';
                sdram_read_en <= '1';
                sdram_write_en <= '0';
                wr_brst_clr <= not (RESET_ACTIVE);
                rd_brst_clr <= not (RESET_ACTIVE);				
								
			------------------- WAIT_WRITE_ST State ---------------------
			when WAIT_WRITE_ST =>
			
				-- Wait for tRCD requirement
			
				-- NOP command values
				CLKENB_SDRAM_com  <= '1';
				NCS_SDRAM_com  <= '0';
				NRAS_SDRAM_com <= '1';
				NCAS_SDRAM_com <= '1';
				NWE_SDRAM_com  <= '1';
			
				sdram_nxt_state <= WAIT_WRITE_ST1 ;				

                self_refresh_sig <= '0';
				cas_clr <= not (RESET_ACTIVE);				
				cas_cnt_en <= '0';
                ld_mr <= '0';
                row_sdram_en <= '0';
                sdram_read_en <= '0';
                sdram_write_en <= '0';
                wr_brst_clr <= not (RESET_ACTIVE);
                rd_brst_clr <= not (RESET_ACTIVE);				

			------------------- WAIT_WRITE_ST1 State ---------------------
			when WAIT_WRITE_ST1 =>
			
				-- Wait for tRCD requirement
			
				-- NOP command values
				CLKENB_SDRAM_com  <= '1';
				NCS_SDRAM_com  <= '0';
				NRAS_SDRAM_com <= '1';
				NCAS_SDRAM_com <= '1';
				NWE_SDRAM_com  <= '1';
			
				sdram_nxt_state <= WRITE_ST ;				

                self_refresh_sig <= '0';
				cas_clr <= not (RESET_ACTIVE);				
				cas_cnt_en <= '0';
                ld_mr <= '0';
                row_sdram_en <= '0';
                sdram_read_en <= '0';
                sdram_write_en <= '0';
                wr_brst_clr <= not (RESET_ACTIVE);
                rd_brst_clr <= not (RESET_ACTIVE);				

			
			------------------- WRITE_ST State ---------------------
			when WRITE_ST =>
			
				-- Assign SDRAM command values (WRITE)
				-- WRITE = Select bank and column, and start WRITE BURST
				CLKENB_SDRAM_com  <= '1';
				NCS_SDRAM_com  <= '0';
				NRAS_SDRAM_com <= '1';
				NCAS_SDRAM_com <= '0';
				NWE_SDRAM_com  <= '0';			
						
				sdram_nxt_state <= WRITE_DATA_ST;				
                
                self_refresh_sig <= '0';
				cas_clr <= not (RESET_ACTIVE);				
				cas_cnt_en <= '0';
                ld_mr <= '0';
                row_sdram_en <= '0';
                sdram_read_en <= '0';
                sdram_write_en <= '1';
                wr_brst_clr <= (RESET_ACTIVE);
                rd_brst_clr <= not (RESET_ACTIVE);				
			
			---------------- WRITE_DATA_ST State -------------------
			when WRITE_DATA_ST =>
			
				-- Write data to SDRAM
			
				-- Assign SDRAM command values (NO OPERATION -- NOP)
				CLKENB_SDRAM_com  <= '1';
				NCS_SDRAM_com  <= '0';
				NRAS_SDRAM_com <= '1';
				NCAS_SDRAM_com <= '1';
				NWE_SDRAM_com  <= '1';
				
							
				-- Write until burst length complete
				-- Read burst length value stored in Mode Reg
				if (wr_brst_qout < burst_len) then					
					sdram_nxt_state <= WRITE_DATA_ST;
				else
					sdram_nxt_state <= WAIT_TWR;
				end if;		
                	
                self_refresh_sig <= '0';
				cas_clr <= not (RESET_ACTIVE);				
				cas_cnt_en <= '0';
                ld_mr <= '0';
                row_sdram_en <= '0';
                sdram_read_en <= '0';
                sdram_write_en <= '1';
                wr_brst_clr <= not (RESET_ACTIVE);
                rd_brst_clr <= not (RESET_ACTIVE);				
			
			---------------- WAIT_TWR State -------------------
			when WAIT_TWR =>
				
				-- Design set for Auto Precharge
				-- Wait for tWR timing requirement
							
				-- NOP command values
				CLKENB_SDRAM_com  <= '1';
				NCS_SDRAM_com  <= '0';
				NRAS_SDRAM_com <= '1';
				NCAS_SDRAM_com <= '1';
				NWE_SDRAM_com  <= '1';
						
				sdram_nxt_state <= WAIT_TRP;			
                
                self_refresh_sig <= '0';
				cas_clr <= not (RESET_ACTIVE);				
				cas_cnt_en <= '0';
                ld_mr <= '0';
                row_sdram_en <= '0';
                sdram_read_en <= '0';
                sdram_write_en <= '1';
                wr_brst_clr <= not (RESET_ACTIVE);
                rd_brst_clr <= not (RESET_ACTIVE);				
			
			---------------- WAIT_TRP State -------------------
			when WAIT_TRP =>
					
				-- NOP command values
				CLKENB_SDRAM_com  <= '1';
				NCS_SDRAM_com  <= '0';
				NRAS_SDRAM_com <= '1';
				NCAS_SDRAM_com <= '1';
				NWE_SDRAM_com  <= '1';	

                sdram_nxt_state <= SELF_RFSH_ST; 
                
                self_refresh_sig <= '1';
				cas_clr <= not (RESET_ACTIVE);				
				cas_cnt_en <= '0';
                ld_mr <= '0';
                row_sdram_en <= '0';
                sdram_read_en <= '0';
                sdram_write_en <= '0';
                wr_brst_clr <= not (RESET_ACTIVE);
                rd_brst_clr <= not (RESET_ACTIVE);				
			
			-------------------- DEFAULT State --------------------
			when others =>
				sdram_nxt_state <= IDLE;

				CLKENB_SDRAM_com  <= '1';
				NCS_SDRAM_com  <= '0';
				NRAS_SDRAM_com <= '1';
				NCAS_SDRAM_com <= '1';
				NWE_SDRAM_com  <= '1';	
                
                self_refresh_sig <= '0';
				cas_clr <= not (RESET_ACTIVE);				
				cas_cnt_en <= '0';
                ld_mr <= '0';
                row_sdram_en <= '0';
                sdram_read_en <= '0';
                sdram_write_en <= '0';
                wr_brst_clr <= not (RESET_ACTIVE);
                rd_brst_clr <= not (RESET_ACTIVE);				

		end case;  

	end process SDRAM_CNTR;		
	
end mobile_sdram_core_archi;
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