Timing Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Wed Dec 28 15:12:02 2011


Design: Modbus
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        2.456
External Hold (ns):         1.390
Min Clock-To-Out (ns):      8.374
Max Clock-To-Out (ns):      16.807

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        -4.586
External Hold (ns):         3.536
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               Modbus_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        F2M_GPI_7
  To:                          Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[7]
  Delay (ns):                  1.846
  Slack (ns):
  Arrival (ns):                1.846
  Required (ns):
  Hold (ns):                   0.763
  External Hold (ns):          1.390

Path 2
  From:                        F2M_GPI_9
  To:                          Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[9]
  Delay (ns):                  2.209
  Slack (ns):
  Arrival (ns):                2.209
  Required (ns):
  Hold (ns):                   0.789
  External Hold (ns):          1.053

Path 3
  From:                        F2M_GPI_12
  To:                          Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[12]
  Delay (ns):                  2.361
  Slack (ns):
  Arrival (ns):                2.361
  Required (ns):
  Hold (ns):                   0.695
  External Hold (ns):          0.807

Path 4
  From:                        F2M_GPI_5
  To:                          Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[5]
  Delay (ns):                  2.641
  Slack (ns):
  Arrival (ns):                2.641
  Required (ns):
  Hold (ns):                   0.872
  External Hold (ns):          0.704

Path 5
  From:                        F2M_GPI_10
  To:                          Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[10]
  Delay (ns):                  2.880
  Slack (ns):
  Arrival (ns):                2.880
  Required (ns):
  Hold (ns):                   0.851
  External Hold (ns):          0.444


Expanded Path 1
  From: F2M_GPI_7
  To: Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[7]
  data arrival time                              1.846
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        F2M_GPI_7 (f)
               +     0.000          net: F2M_GPI_7
  0.000                        F2M_GPI_7_pad/U0/U0:PAD (f)
               +     0.293          cell: ADLIB:IOPAD_IN
  0.293                        F2M_GPI_7_pad/U0/U0:Y (f)
               +     0.000          net: F2M_GPI_7_pad/U0/NET1
  0.293                        F2M_GPI_7_pad/U0/U1:YIN (f)
               +     0.017          cell: ADLIB:IOIN_IB
  0.310                        F2M_GPI_7_pad/U0/U1:Y (f)
               +     1.445          net: F2M_GPI_7_c
  1.755                        Modbus_MSS_0/MSS_ADLIB_INST/U_27:PIN5 (f)
               +     0.091          cell: ADLIB:MSS_IF
  1.846                        Modbus_MSS_0/MSS_ADLIB_INST/U_27:PIN5INT (f)
               +     0.000          net: Modbus_MSS_0/MSS_ADLIB_INST/GPI[7]INT_NET
  1.846                        Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[7] (f)
                                    
  1.846                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     2.473          Clock generation
  N/C
               +     0.763          Library hold time: ADLIB:MSS_APB_IP
  N/C                          Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[7]


END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          M2F_GPO_3
  Delay (ns):                  5.901
  Slack (ns):
  Arrival (ns):                8.374
  Required (ns):
  Clock to Out (ns):           8.374

Path 2
  From:                        Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          M2F_GPO_0
  Delay (ns):                  6.126
  Slack (ns):
  Arrival (ns):                8.599
  Required (ns):
  Clock to Out (ns):           8.599

Path 3
  From:                        Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          M2F_GPO_2
  Delay (ns):                  6.166
  Slack (ns):
  Arrival (ns):                8.639
  Required (ns):
  Clock to Out (ns):           8.639

Path 4
  From:                        Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          M2F_GPO_1
  Delay (ns):                  6.186
  Slack (ns):
  Arrival (ns):                8.659
  Required (ns):
  Clock to Out (ns):           8.659


Expanded Path 1
  From: Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To: M2F_GPO_3
  data arrival time                              8.374
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     2.473          Clock generation
  2.473
               +     2.007          cell: ADLIB:MSS_APB_IP
  4.480                        Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:GPO[3] (r)
               +     0.000          net: Modbus_MSS_0/MSS_ADLIB_INST/GPO[3]INT_NET
  4.480                        Modbus_MSS_0/MSS_ADLIB_INST/U_23:PIN1INT (r)
               +     0.042          cell: ADLIB:MSS_IF
  4.522                        Modbus_MSS_0/MSS_ADLIB_INST/U_23:PIN1 (r)
               +     2.485          net: Modbus_MSS_0/MSSINT_GPO_3_A
  7.007                        M2F_GPO_3_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  7.286                        M2F_GPO_3_pad/U0/U1:DOUT (r)
               +     0.000          net: M2F_GPO_3_pad/U0/NET1
  7.286                        M2F_GPO_3_pad/U0/U0:D (r)
               +     1.088          cell: ADLIB:IOPAD_TRI
  8.374                        M2F_GPO_3_pad/U0/U0:PAD (r)
               +     0.000          net: M2F_GPO_3
  8.374                        M2F_GPO_3 (r)
                                    
  8.374                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     2.473          Clock generation
  N/C
                                    
  N/C                          M2F_GPO_3 (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.277
  Slack (ns):
  Arrival (ns):                0.277
  Required (ns):
  Hold (ns):                   1.294
  External Hold (ns):          3.536


Expanded Path 1
  From: MSS_RESET_N
  To: Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.277
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        Modbus_MSS_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.277          cell: ADLIB:IOPAD_IN
  0.277                        Modbus_MSS_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: Modbus_MSS_0/MSS_RESET_0_MSS_RESET_N_Y
  0.277                        Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.277                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          Modbus_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.248          Clock generation
  N/C
               +     0.271          net: Modbus_MSS_0/MSS_ADLIB_INST_FCLK
  N/C                          Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.294          Library hold time: ADLIB:MSS_APB_IP
  N/C                          Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain Modbus_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

