Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Wed Dec 28 15:12:02 2011


Design: Modbus
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        2.456
External Hold (ns):         1.390
Min Clock-To-Out (ns):      8.374
Max Clock-To-Out (ns):      16.807

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        -4.586
External Hold (ns):         3.536
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               Modbus_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        F2M_GPI_4
  To:                          Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[4]
  Delay (ns):                  6.464
  Slack (ns):
  Arrival (ns):                6.464
  Required (ns):
  Setup (ns):                  -0.624
  External Setup (ns):         2.456

Path 2
  From:                        F2M_GPI_11
  To:                          Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[11]
  Delay (ns):                  6.460
  Slack (ns):
  Arrival (ns):                6.460
  Required (ns):
  Setup (ns):                  -1.134
  External Setup (ns):         1.942

Path 3
  From:                        F2M_GPI_8
  To:                          Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[8]
  Delay (ns):                  6.157
  Slack (ns):
  Arrival (ns):                6.157
  Required (ns):
  Setup (ns):                  -1.092
  External Setup (ns):         1.681

Path 4
  From:                        F2M_GPI_6
  To:                          Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[6]
  Delay (ns):                  5.518
  Slack (ns):
  Arrival (ns):                5.518
  Required (ns):
  Setup (ns):                  -0.522
  External Setup (ns):         1.612

Path 5
  From:                        F2M_GPI_10
  To:                          Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[10]
  Delay (ns):                  6.078
  Slack (ns):
  Arrival (ns):                6.078
  Required (ns):
  Setup (ns):                  -1.298
  External Setup (ns):         1.396


Expanded Path 1
  From: F2M_GPI_4
  To: Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[4]
  data required time                             N/C
  data arrival time                          -   6.464
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        F2M_GPI_4 (r)
               +     0.000          net: F2M_GPI_4
  0.000                        F2M_GPI_4_pad/U0/U0:PAD (r)
               +     0.935          cell: ADLIB:IOPAD_IN
  0.935                        F2M_GPI_4_pad/U0/U0:Y (r)
               +     0.000          net: F2M_GPI_4_pad/U0/NET1
  0.935                        F2M_GPI_4_pad/U0/U1:YIN (r)
               +     0.039          cell: ADLIB:IOIN_IB
  0.974                        F2M_GPI_4_pad/U0/U1:Y (r)
               +     5.274          net: F2M_GPI_4_c
  6.248                        Modbus_MSS_0/MSS_ADLIB_INST/U_24:PIN5 (r)
               +     0.216          cell: ADLIB:MSS_IF
  6.464                        Modbus_MSS_0/MSS_ADLIB_INST/U_24:PIN5INT (r)
               +     0.000          net: Modbus_MSS_0/MSS_ADLIB_INST/GPI[4]INT_NET
  6.464                        Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[4] (r)
                                    
  6.464                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     3.384          Clock generation
  N/C
               -    -0.624          Library setup time: ADLIB:MSS_APB_IP
  N/C                          Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[4]


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          M2F_GPO_1
  Delay (ns):                  13.423
  Slack (ns):
  Arrival (ns):                16.807
  Required (ns):
  Clock to Out (ns):           16.807

Path 2
  From:                        Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          M2F_GPO_2
  Delay (ns):                  13.390
  Slack (ns):
  Arrival (ns):                16.774
  Required (ns):
  Clock to Out (ns):           16.774

Path 3
  From:                        Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          M2F_GPO_0
  Delay (ns):                  13.309
  Slack (ns):
  Arrival (ns):                16.693
  Required (ns):
  Clock to Out (ns):           16.693

Path 4
  From:                        Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          M2F_GPO_3
  Delay (ns):                  12.795
  Slack (ns):
  Arrival (ns):                16.179
  Required (ns):
  Clock to Out (ns):           16.179


Expanded Path 1
  From: Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To: M2F_GPO_1
  data required time                             N/C
  data arrival time                          -   16.807
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     3.384          Clock generation
  3.384
               +     4.043          cell: ADLIB:MSS_APB_IP
  7.427                        Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:GPO[1] (f)
               +     0.000          net: Modbus_MSS_0/MSS_ADLIB_INST/GPO[1]INT_NET
  7.427                        Modbus_MSS_0/MSS_ADLIB_INST/U_21:PIN1INT (f)
               +     0.088          cell: ADLIB:MSS_IF
  7.515                        Modbus_MSS_0/MSS_ADLIB_INST/U_21:PIN1 (f)
               +     5.323          net: Modbus_MSS_0/MSSINT_GPO_1_A
  12.838                       M2F_GPO_1_pad/U0/U1:D (f)
               +     0.600          cell: ADLIB:IOTRI_OB_EB
  13.438                       M2F_GPO_1_pad/U0/U1:DOUT (f)
               +     0.000          net: M2F_GPO_1_pad/U0/NET1
  13.438                       M2F_GPO_1_pad/U0/U0:D (f)
               +     3.369          cell: ADLIB:IOPAD_TRI
  16.807                       M2F_GPO_1_pad/U0/U0:PAD (f)
               +     0.000          net: M2F_GPO_1
  16.807                       M2F_GPO_1 (f)
                                    
  16.807                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     3.384          Clock generation
  N/C
                                    
  N/C                          M2F_GPO_1 (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.937
  Slack (ns):
  Arrival (ns):                0.937
  Required (ns):
  Setup (ns):                  -2.139
  External Setup (ns):         -4.586


Expanded Path 1
  From: MSS_RESET_N
  To: Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.937
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        Modbus_MSS_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.937          cell: ADLIB:IOPAD_IN
  0.937                        Modbus_MSS_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: Modbus_MSS_0/MSS_RESET_0_MSS_RESET_N_Y
  0.937                        Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.937                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          Modbus_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.925          Clock generation
  N/C
               +     0.459          net: Modbus_MSS_0/MSS_ADLIB_INST_FCLK
  N/C                          Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -2.139          Library setup time: ADLIB:MSS_APB_IP
  N/C                          Modbus_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain Modbus_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

