@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN115 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2708:2:2708:14|Removing instance masterstage_1 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN115 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2771:2:2771:14|Removing instance masterstage_2 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN115 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2834:2:2834:14|Removing instance masterstage_3 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN115 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2892:27:2892:38|Removing instance slavestage_0 of view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_slavestage_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2708:12:2708:18|Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2728:12:2728:18|Removing sequential instance block15 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2748:12:2748:18|Removing sequential instance block14 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2768:12:2768:18|Removing sequential instance block13 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2788:12:2788:18|Removing sequential instance block12 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2808:12:2808:18|Removing sequential instance block11 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2828:12:2828:18|Removing sequential instance block10 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2848:12:2848:17|Removing sequential instance block9 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2868:12:2868:17|Removing sequential instance block8 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2708:12:2708:18|Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2728:12:2728:18|Removing sequential instance block15 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2748:12:2748:18|Removing sequential instance block14 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2768:12:2768:18|Removing sequential instance block13 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2788:12:2788:18|Removing sequential instance block12 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2808:12:2808:18|Removing sequential instance block11 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2828:12:2828:18|Removing sequential instance block10 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2848:12:2848:17|Removing sequential instance block9 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2868:12:2868:17|Removing sequential instance block8 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2708:12:2708:18|Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2728:12:2728:18|Removing sequential instance block15 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2748:12:2748:18|Removing sequential instance block14 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2768:12:2768:18|Removing sequential instance block13 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2788:12:2788:18|Removing sequential instance block12 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2808:12:2808:18|Removing sequential instance block11 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2828:12:2828:18|Removing sequential instance block10 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2848:12:2848:17|Removing sequential instance block9 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2868:12:2868:17|Removing sequential instance block8 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2708:12:2708:18|Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2728:12:2728:18|Removing sequential instance block15 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2748:12:2748:18|Removing sequential instance block14 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2768:12:2768:18|Removing sequential instance block13 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2788:12:2788:18|Removing sequential instance block12 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2808:12:2808:18|Removing sequential instance block11 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2828:12:2828:18|Removing sequential instance block10 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2848:12:2848:17|Removing sequential instance block9 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2868:12:2868:17|Removing sequential instance block8 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_slavestage_0(verilog) because there are no references to its outputs 
@N: BN115 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":90:29:90:41|Removing instance slave_arbiter of view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing sequential instance arbRegSMCurrentState[15:0] of view:PrimLib.statemachine(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter(verilog) because there are no references to its outputs 
@N: BN225 |Writing default property annotation file E:\Ranjith\Linker_Design\synthesis\Linker_Design.sap.
