@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[20] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[21] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[22] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[23] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[24] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[25] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[26] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[27] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_3.masterDataInProg[3] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_3.masterDataInProg[2] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_3.masterDataInProg[1] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":233:0:233:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[16] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblsram\2.0.113\rtl\vlog\core\ahblsramif.v":161:3:161:8|Removing sequential instance HADDR_d[16] in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblsram\2.0.113\rtl\vlog\core\ahblsramif.v":161:3:161:8|Removing sequential instance HADDR_d[17] in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblsram\2.0.113\rtl\vlog\core\ahblsramif.v":161:3:161:8|Removing sequential instance HADDR_d[18] in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblsram\2.0.113\rtl\vlog\core\ahblsramif.v":161:3:161:8|Removing sequential instance HADDR_d[19] in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[16] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[17] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[18] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[19] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblsram\2.0.113\rtl\vlog\core\ahblsramif.v":161:3:161:8|Removing sequential instance COREAHBLSRAM_0.U_AHBLSramIf.HSIZE_d[2] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[30] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: FP130 |Promoting Net SYSRESET_0_POWER_ON_RESET_N on CLKINT  I_133 
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
