@W: CG775 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":32:7:32:17|Found Component CoreAHBLite in library COREAHBLITE_LIB
@W: CG775 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v":29:7:29:47|Found Component Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM in library COREAHBLSRAM_LIB
@W: CG775 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":32:7:32:17|Found Component CoreAHBLite in library COREAHBLITE_LIB
@W: CG775 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v":29:7:29:47|Found Component Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM in library COREAHBLSRAM_LIB
@W: CL169 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core\AHBLSramIf.v":161:3:161:8|Pruning register HWDATA_d[31:0] 
@W: CL169 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core\AHBLSramIf.v":161:3:161:8|Pruning register HTRANS_d[1:0] 
@W: CL169 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core\AHBLSramIf.v":161:3:161:8|Pruning register HSEL_d 
@W: CL169 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core\AHBLSramIf.v":161:3:161:8|Pruning register HREADYIN_d 
@W: CL271 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":229:4:229:9|Pruning bits 15 to 14 of ckRdAddr[15:9] -- not in use ...
@W: CL265 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":229:4:229:9|Pruning bit 9 of ckRdAddr[15:9] -- not in use ...
@W: CG133 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":95:31:95:49|No assignment to ahbsram_wdata_upd_r
@W: CG133 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":96:31:96:51|No assignment to u_ahbsram_wdata_upd_r
@W: CG360 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":103:31:103:42|No assignment to wire u_BUSY_all_0
@W: CG360 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":104:31:104:42|No assignment to wire u_BUSY_all_1
@W: CG360 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":105:31:105:42|No assignment to wire u_BUSY_all_2
@W: CG360 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":106:31:106:42|No assignment to wire u_BUSY_all_3
@W: CG360 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":113:31:113:49|No assignment to wire u_ahbsram_wdata_upd
@W: CG360 :"E:\Ranjith\Linker_Design\component\work\Linker_Design_MSS\Linker_Design_MSS.v":55:14:55:33|No assignment to wire FIC_0_AHB_M_HTRANS_0
@W: CL157 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\OSC_0\Linker_Design_OSC_0_OSC.v":16:7:16:24|*Output RCOSC_25_50MHZ_O2F has undriven bits -- simulation mismatch possible.
@W: CL157 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\OSC_0\Linker_Design_OSC_0_OSC.v":17:7:17:20|*Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible.
@W: CL157 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\OSC_0\Linker_Design_OSC_0_OSC.v":18:7:18:20|*Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible.
@W: CL157 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\OSC_0\Linker_Design_OSC_0_OSC.v":19:7:19:16|*Output XTLOSC_CCC has undriven bits -- simulation mismatch possible.
@W: CL157 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\OSC_0\Linker_Design_OSC_0_OSC.v":20:7:20:16|*Output XTLOSC_O2F has undriven bits -- simulation mismatch possible.
@W: CL159 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\OSC_0\Linker_Design_OSC_0_OSC.v":14:7:14:9|Input XTL is unused
@W: CL157 :"E:\Ranjith\Linker_Design\component\work\Linker_Design_MSS\Linker_Design_MSS.v":42:14:42:31|*Output FIC_0_AHB_M_HTRANS has undriven bits -- simulation mismatch possible.
@W: CL246 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v":68:28:68:32|Input port bits 31 to 20 of HADDR[31:0] are unused
@W: CL260 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":229:4:229:9|Pruning register bit 10 of ckRdAddr[13:10] 
@W: CL246 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":61:26:61:34|Input port bits 15 to 14 of writeAddr[15:0] are unused
@W: CL246 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":62:26:62:33|Input port bits 15 to 14 of readAddr[15:0] are unused
@W: CL246 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":62:26:62:33|Input port bits 10 to 0 of readAddr[15:0] are unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":60:26:60:28|Input ren is unused
@W: CL246 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":72:29:72:40|Input port bits 19 to 18 of ahbsram_addr[19:0] are unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core\AHBLSramIf.v":97:28:97:31|Input BUSY is unused
@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":128:15:128:23|Input port bit 0 of HTRANS_M0[1:0] is unused
@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":139:15:139:23|Input port bit 0 of HTRANS_M1[1:0] is unused
@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":150:15:150:23|Input port bit 0 of HTRANS_M2[1:0] is unused
@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":161:15:161:23|Input port bit 0 of HTRANS_M3[1:0] is unused
@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":171:15:171:22|Input port bit 1 of HRESP_S0[1:0] is unused
@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":184:15:184:22|Input port bit 1 of HRESP_S1[1:0] is unused
@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":197:15:197:22|Input port bit 1 of HRESP_S2[1:0] is unused
@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":210:15:210:22|Input port bit 1 of HRESP_S3[1:0] is unused
@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":223:15:223:22|Input port bit 1 of HRESP_S4[1:0] is unused
@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":236:15:236:22|Input port bit 1 of HRESP_S5[1:0] is unused
@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":249:15:249:22|Input port bit 1 of HRESP_S6[1:0] is unused
@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":262:15:262:22|Input port bit 1 of HRESP_S7[1:0] is unused
@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":275:15:275:22|Input port bit 1 of HRESP_S8[1:0] is unused
@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":288:15:288:22|Input port bit 1 of HRESP_S9[1:0] is unused
@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":301:15:301:23|Input port bit 1 of HRESP_S10[1:0] is unused
@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":314:15:314:23|Input port bit 1 of HRESP_S11[1:0] is unused
@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":327:15:327:23|Input port bit 1 of HRESP_S12[1:0] is unused
@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":340:15:340:23|Input port bit 1 of HRESP_S13[1:0] is unused
@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":353:15:353:23|Input port bit 1 of HRESP_S14[1:0] is unused
@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":366:15:366:23|Input port bit 1 of HRESP_S15[1:0] is unused
@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":379:15:379:23|Input port bit 1 of HRESP_S16[1:0] is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":131:15:131:23|Input HBURST_M0 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":132:15:132:22|Input HPROT_M0 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":142:15:142:23|Input HBURST_M1 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":143:15:143:22|Input HPROT_M1 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":153:15:153:23|Input HBURST_M2 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":154:15:154:22|Input HPROT_M2 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":164:15:164:23|Input HBURST_M3 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":165:15:165:22|Input HPROT_M3 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":58:18:58:26|Input HWDATA_M1 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":67:18:67:26|Input HWDATA_M2 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":76:18:76:26|Input HWDATA_M3 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":80:18:80:26|Input HRDATA_S0 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":81:13:81:24|Input HREADYOUT_S0 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":82:13:82:20|Input HRESP_S0 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":91:18:91:26|Input HRDATA_S1 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":92:13:92:24|Input HREADYOUT_S1 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":93:13:93:20|Input HRESP_S1 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":102:18:102:26|Input HRDATA_S2 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":103:13:103:24|Input HREADYOUT_S2 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":104:13:104:20|Input HRESP_S2 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":124:18:124:26|Input HRDATA_S4 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":125:13:125:24|Input HREADYOUT_S4 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":126:13:126:20|Input HRESP_S4 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":135:18:135:26|Input HRDATA_S5 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":136:13:136:24|Input HREADYOUT_S5 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":137:13:137:20|Input HRESP_S5 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":146:18:146:26|Input HRDATA_S6 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":147:13:147:24|Input HREADYOUT_S6 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":148:13:148:20|Input HRESP_S6 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":157:18:157:26|Input HRDATA_S7 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":158:13:158:24|Input HREADYOUT_S7 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":159:13:159:20|Input HRESP_S7 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":168:18:168:26|Input HRDATA_S8 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":169:13:169:24|Input HREADYOUT_S8 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":170:13:170:20|Input HRESP_S8 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":179:18:179:26|Input HRDATA_S9 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":180:13:180:24|Input HREADYOUT_S9 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":181:13:181:20|Input HRESP_S9 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":190:18:190:27|Input HRDATA_S10 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":191:13:191:25|Input HREADYOUT_S10 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":192:13:192:21|Input HRESP_S10 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":201:18:201:27|Input HRDATA_S11 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":202:13:202:25|Input HREADYOUT_S11 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":203:13:203:21|Input HRESP_S11 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":212:18:212:27|Input HRDATA_S12 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":213:13:213:25|Input HREADYOUT_S12 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":214:13:214:21|Input HRESP_S12 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":223:18:223:27|Input HRDATA_S13 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":224:13:224:25|Input HREADYOUT_S13 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":225:13:225:21|Input HRESP_S13 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":234:18:234:27|Input HRDATA_S14 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":235:13:235:25|Input HREADYOUT_S14 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":236:13:236:21|Input HRESP_S14 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":245:18:245:27|Input HRDATA_S15 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":246:13:246:25|Input HREADYOUT_S15 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":247:13:247:21|Input HRESP_S15 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":256:18:256:27|Input HRDATA_S16 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":257:13:257:25|Input HREADYOUT_S16 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":258:13:258:21|Input HRESP_S16 is unused
@W: CL246 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":46:15:46:33|Input port bits 3 to 2 of MPREVDATASLAVEREADY[3:0] are unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":50:16:50:25|Input SDATAREADY is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":51:16:51:21|Input SHRESP is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":60:16:60:24|Input HRDATA_S0 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":61:11:61:22|Input HREADYOUT_S0 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":62:16:62:24|Input HRDATA_S1 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":63:11:63:22|Input HREADYOUT_S1 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":64:16:64:24|Input HRDATA_S2 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":65:11:65:22|Input HREADYOUT_S2 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":66:16:66:24|Input HRDATA_S3 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":67:11:67:22|Input HREADYOUT_S3 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":68:16:68:24|Input HRDATA_S4 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":69:11:69:22|Input HREADYOUT_S4 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":70:16:70:24|Input HRDATA_S5 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":71:11:71:22|Input HREADYOUT_S5 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":72:16:72:24|Input HRDATA_S6 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":73:11:73:22|Input HREADYOUT_S6 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":74:16:74:24|Input HRDATA_S7 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":75:11:75:22|Input HREADYOUT_S7 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":76:16:76:24|Input HRDATA_S8 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":77:11:77:22|Input HREADYOUT_S8 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":78:16:78:24|Input HRDATA_S9 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":79:11:79:22|Input HREADYOUT_S9 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":80:16:80:25|Input HRDATA_S10 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":81:11:81:23|Input HREADYOUT_S10 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":82:16:82:25|Input HRDATA_S11 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":83:11:83:23|Input HREADYOUT_S11 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":84:16:84:25|Input HRDATA_S12 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":85:11:85:23|Input HREADYOUT_S12 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":86:16:86:25|Input HRDATA_S13 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":87:11:87:23|Input HREADYOUT_S13 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":88:16:88:25|Input HRDATA_S14 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":89:11:89:23|Input HREADYOUT_S14 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":90:16:90:25|Input HRDATA_S15 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":91:11:91:23|Input HREADYOUT_S15 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":92:16:92:25|Input HRDATA_S16 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":93:11:93:23|Input HREADYOUT_S16 is unused
@W: CL246 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":50:16:50:25|Input port bits 16 to 4 of SDATAREADY[16:0] are unused
@W: CL246 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":50:16:50:25|Input port bits 2 to 0 of SDATAREADY[16:0] are unused
@W: CL246 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":51:16:51:21|Input port bits 16 to 4 of SHRESP[16:0] are unused
@W: CL246 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":51:16:51:21|Input port bits 2 to 0 of SHRESP[16:0] are unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":60:16:60:24|Input HRDATA_S0 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":61:11:61:22|Input HREADYOUT_S0 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":62:16:62:24|Input HRDATA_S1 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":63:11:63:22|Input HREADYOUT_S1 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":64:16:64:24|Input HRDATA_S2 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":65:11:65:22|Input HREADYOUT_S2 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":68:16:68:24|Input HRDATA_S4 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":69:11:69:22|Input HREADYOUT_S4 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":70:16:70:24|Input HRDATA_S5 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":71:11:71:22|Input HREADYOUT_S5 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":72:16:72:24|Input HRDATA_S6 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":73:11:73:22|Input HREADYOUT_S6 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":74:16:74:24|Input HRDATA_S7 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":75:11:75:22|Input HREADYOUT_S7 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":76:16:76:24|Input HRDATA_S8 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":77:11:77:22|Input HREADYOUT_S8 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":78:16:78:24|Input HRDATA_S9 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":79:11:79:22|Input HREADYOUT_S9 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":80:16:80:25|Input HRDATA_S10 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":81:11:81:23|Input HREADYOUT_S10 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":82:16:82:25|Input HRDATA_S11 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":83:11:83:23|Input HREADYOUT_S11 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":84:16:84:25|Input HRDATA_S12 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":85:11:85:23|Input HREADYOUT_S12 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":86:16:86:25|Input HRDATA_S13 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":87:11:87:23|Input HREADYOUT_S13 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":88:16:88:25|Input HRDATA_S14 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":89:11:89:23|Input HREADYOUT_S14 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":90:16:90:25|Input HRDATA_S15 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":91:11:91:23|Input HREADYOUT_S15 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":92:16:92:25|Input HRDATA_S16 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":93:11:93:23|Input HREADYOUT_S16 is unused

