#--  Synopsys, Inc.
#--  Version I-2013.09M-SP1 
#--  Project file E:\Ranjith\Linker_Design\synthesis\synthesis_1\run_options.txt
#--  Written on Thu Apr 03 16:14:06 2014


#project files
add_file -verilog "E:/Ranjith/Linker_Design/component/work/Linker_Design/FCCC_0/Linker_Design_FCCC_0_FCCC.v"
add_file -verilog "E:/Ranjith/Linker_Design/component/work/Linker_Design_MSS/Linker_Design_MSS_syn.v"
add_file -verilog "E:/Ranjith/Linker_Design/component/work/Linker_Design_MSS/Linker_Design_MSS.v"
add_file -verilog "E:/Ranjith/Linker_Design/component/Actel/SgCore/OSC/1.0.100/osc_comps.v"
add_file -verilog "E:/Ranjith/Linker_Design/component/work/Linker_Design/OSC_0/Linker_Design_OSC_0_OSC.v"
add_file -verilog -lib COREAHBLITE_LIB "E:/Ranjith/Linker_Design/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_addrdec.v"
add_file -verilog -lib COREAHBLITE_LIB "E:/Ranjith/Linker_Design/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_defaultslavesm.v"
add_file -verilog -lib COREAHBLITE_LIB "E:/Ranjith/Linker_Design/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_masterstage.v"
add_file -verilog -lib COREAHBLITE_LIB "E:/Ranjith/Linker_Design/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_slavearbiter.v"
add_file -verilog -lib COREAHBLITE_LIB "E:/Ranjith/Linker_Design/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_slavestage.v"
add_file -verilog -lib COREAHBLITE_LIB "E:/Ranjith/Linker_Design/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_matrix4x16.v"
add_file -verilog -lib COREAHBLITE_LIB "E:/Ranjith/Linker_Design/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite.v"
add_file -verilog -lib COREAHBLSRAM_LIB "E:/Ranjith/Linker_Design/component/Actel/DirectCore/COREAHBLSRAM/2.0.113/rtl/vlog/core/AHBLSramIf.v"
add_file -verilog -lib COREAHBLSRAM_LIB "E:/Ranjith/Linker_Design/component/work/Linker_Design/COREAHBLSRAM_0/rtl/vlog/core/lsram_2048to139264x8.v"
add_file -verilog -lib COREAHBLSRAM_LIB "E:/Ranjith/Linker_Design/component/work/Linker_Design/COREAHBLSRAM_0/rtl/vlog/core/usram_128to9216x8.v"
add_file -verilog -lib COREAHBLSRAM_LIB "E:/Ranjith/Linker_Design/component/work/Linker_Design/COREAHBLSRAM_0/rtl/vlog/core/SramCtrlIf.v"
add_file -verilog -lib COREAHBLSRAM_LIB "E:/Ranjith/Linker_Design/component/work/Linker_Design/COREAHBLSRAM_0/rtl/vlog/core/CoreAHBLSRAM.v"
add_file -verilog "E:/Ranjith/Linker_Design/component/work/Linker_Design/Linker_Design.v"



#implementation: "synthesis_1"
impl -add synthesis_1 -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology SmartFusion2
set_option -part M2S050T
set_option -package FBGA896
set_option -speed_grade STD
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 1
set_option -top_module "Linker_Design"

# mapper_options
set_option -frequency 100.000000
set_option -write_verilog 1
set_option -write_vhdl 0
set_option -srs_instrumentation 1

# actel_options
set_option -RWCheckOnRam 0

# Microsemi G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -opcond COMWC
set_option -retiming 0
set_option -report_path 0
set_option -update_models_cp 0
set_option -preserve_registers 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./synthesis_1/Linker_Design.edf"
impl -active "synthesis_1"
