# Synospys Constraint Checker(syntax only), version mapact, Build 1154R, built Jan 20 2014
# Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

# Written on Thu Apr 03 16:14:11 2014


##### DESIGN INFO #######################################################

Top View:                "Linker_Design"
Constraint File(s):      "E:\Ranjith\Linker_Design\synthesis\synthesis_1\Linker_Design_fsm.sdc"

#Run constraint checker to find more issues with constraints.
#########################################################################



No issues found in constraint syntax.



Clock Summary
**************

Start                                                Requested     Requested     Clock        Clock              
Clock                                                Frequency     Period        Type         Group              
-----------------------------------------------------------------------------------------------------------------
Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_0
System                                               1.0 MHz       1000.000      system       system_clkgroup    
=================================================================================================================
