Synopsys Generic Technology Pre-mapping, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
Product Version I-2013.09M-SP1 

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

Reading constraint file: E:\Ranjith\Linker_Design\synthesis\Linker_Design_fsm.sdc
@L: E:\Ranjith\Linker_Design\synthesis\Linker_Design_scck.rpt 
Printing clock  summary report in "E:\Ranjith\Linker_Design\synthesis\Linker_Design_scck.rpt" file 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 111MB)

@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3612:27:3612:39|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_16,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_15
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3567:27:3567:39|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_15,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_14
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3522:27:3522:39|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_14,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_13
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3477:27:3477:39|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_13,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_12
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3432:27:3432:39|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_12,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_11
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3387:27:3387:39|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_11,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3297:26:3297:37|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_9,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3252:27:3252:38|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_8,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3207:27:3207:38|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_7,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3162:27:3162:38|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_6,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3117:27:3117:38|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_5,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3072:27:3072:38|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_4,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2982:27:2982:38|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_2,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3342:27:3342:39|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_10,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_1
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2937:27:2937:38|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_1,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_0
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN115 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2708:2:2708:14|Removing instance masterstage_1 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN115 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2771:2:2771:14|Removing instance masterstage_2 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN115 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2834:2:2834:14|Removing instance masterstage_3 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN115 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2892:27:2892:38|Removing instance slavestage_0 of view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_slavestage_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2708:12:2708:18|Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2728:12:2728:18|Removing sequential instance block15 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2748:12:2748:18|Removing sequential instance block14 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2768:12:2768:18|Removing sequential instance block13 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2788:12:2788:18|Removing sequential instance block12 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2808:12:2808:18|Removing sequential instance block11 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2828:12:2828:18|Removing sequential instance block10 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2848:12:2848:17|Removing sequential instance block9 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2868:12:2868:17|Removing sequential instance block8 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2708:12:2708:18|Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2728:12:2728:18|Removing sequential instance block15 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2748:12:2748:18|Removing sequential instance block14 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2768:12:2768:18|Removing sequential instance block13 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2788:12:2788:18|Removing sequential instance block12 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2808:12:2808:18|Removing sequential instance block11 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2828:12:2828:18|Removing sequential instance block10 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2848:12:2848:17|Removing sequential instance block9 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2868:12:2868:17|Removing sequential instance block8 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2708:12:2708:18|Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2728:12:2728:18|Removing sequential instance block15 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2748:12:2748:18|Removing sequential instance block14 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2768:12:2768:18|Removing sequential instance block13 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2788:12:2788:18|Removing sequential instance block12 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2808:12:2808:18|Removing sequential instance block11 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2828:12:2828:18|Removing sequential instance block10 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2848:12:2848:17|Removing sequential instance block9 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2868:12:2868:17|Removing sequential instance block8 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2708:12:2708:18|Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2728:12:2728:18|Removing sequential instance block15 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2748:12:2748:18|Removing sequential instance block14 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2768:12:2768:18|Removing sequential instance block13 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2788:12:2788:18|Removing sequential instance block12 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2808:12:2808:18|Removing sequential instance block11 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2828:12:2828:18|Removing sequential instance block10 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2848:12:2848:17|Removing sequential instance block9 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2868:12:2868:17|Removing sequential instance block8 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_slavestage_0(verilog) because there are no references to its outputs 
@N: BN115 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":90:29:90:41|Removing instance slave_arbiter of view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing sequential instance arbRegSMCurrentState[15:0] of view:PrimLib.statemachine(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter(verilog) because there are no references to its outputs 
syn_allowed_resources : blockrams=69  set on top level netlist Linker_Design


Clock Summary
**************

Start                                                Requested     Requested     Clock        Clock              
Clock                                                Frequency     Period        Type         Group              
-----------------------------------------------------------------------------------------------------------------
Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_0
System                                               1.0 MHz       1000.000      system       system_clkgroup    
=================================================================================================================

@W: MT530 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v":66:4:66:9|Found inferred clock Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock which controls 159 sequential elements including CoreAHBLite_0.matrix4x16.masterstage_0.default_slave_sm.defSlaveSMCurrentState. This clock has no specified timing constraint which may adversely impact design performance. 

Finished Pre Mapping Phase.
@W: MO111 :|Tristate driver Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS_t[0] on net Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS[0] has its enable tied to GND (module Linker_Design) 
@N: BN225 |Writing default property annotation file E:\Ranjith\Linker_Design\synthesis\Linker_Design.sap.
Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 140MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Apr 04 11:20:02 2014

###########################################################]
