<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>Linker_Design</name><vendor/><library/><version/><fileSets><fileSet fileSetId="OTHER_FILESET"><file fileid="0"><name>./Linker_Design.sdb</name><userFileType>SDB</userFileType></file><file fileid="1"><name>./FCCC_0/Linker_Design_FCCC_0_configuration.xml</name><userFileType>LOG</userFileType></file><file fileid="2"><name>./Linker_Design_DataSheet.xml</name><userFileType>log</userFileType></file></fileSet><fileSet fileSetId="ANY_SIMULATION_FILESET"><file fileid="3"><name>./subsystem.bfm</name><userFileType>unknown</userFileType></file></fileSet><fileSet fileSetId="COMPONENT_FILESET"><file fileid="4"><name>../../Actel/DirectCore/CoreAHBLite/5.0.100/CoreAHBLite.cxf</name><userFileType>CXF</userFileType></file><file fileid="5"><name>../../Actel/DirectCore/COREAHBLSRAM/2.0.113/COREAHBLSRAM.cxf</name><userFileType>CXF</userFileType></file><file fileid="6"><name>./COREAHBLSRAM_0/Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM.cxf</name><userFileType>CXF</userFileType></file><file fileid="7"><name>./FCCC_0/Linker_Design_FCCC_0_FCCC.cxf</name><userFileType>CXF</userFileType></file><file fileid="8"><name>../../Actel/SgCore/FCCC/2.0.200/FCCC.cxf</name><userFileType>CXF</userFileType></file><file fileid="9"><name>./OSC_0/Linker_Design_OSC_0_OSC.cxf</name><userFileType>CXF</userFileType></file><file fileid="10"><name>../../Actel/SgCore/OSC/1.0.100/OSC.cxf</name><userFileType>CXF</userFileType></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="11"><name>./Linker_Design.v</name><fileType>verilogSource</fileType></file></fileSet><fileSet fileSetId="STIMULUS_FILESET"><file fileid="12"><name>./testbench.v</name><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>OTHER_FILESET</fileSetRef><fileSetRef>COMPONENT_FILESET</fileSetRef><fileSetRef>STIMULUS_FILESET</fileSetRef><name>OTHER</name></view><view><fileSetRef>ANY_SIMULATION_FILESET</fileSetRef><name>SIMULATION</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel><category>SmartCoreDesign</category><function>SmartDesign</function><variation>SmartDesign</variation><vendor>Actel</vendor><version>1.0</version><vendorExtension><type>SmartCoreDesign</type></vendorExtension><vendorExtension><state value="GENERATED"/></vendorExtension><vendorExtensions><previousType/><preDesignInGoodState>false</preDesignInGoodState><componentRef library="" name="" vendor="" version=""/><dependentModules><module id_library="DirectCore" id_name="CoreAHBLite" id_vendor="Actel" id_version="5.0.100" module_class="SpiritModule" name="CoreAHBLite" state="GOOD" type="3"/><module id_library="DirectCore" id_name="COREAHBLSRAM" id_vendor="Actel" id_version="2.0.113" module_class="SpiritModule" name="COREAHBLSRAM" state="GOOD" type="3"/><module id_library="SgCore" id_name="FCCC" id_vendor="Actel" id_version="2.0.200" module_class="SpiritModule" name="FCCC" state="GOOD" type="3"/><module id_library="SgCore" id_name="OSC" id_vendor="Actel" id_version="1.0.100" module_class="SpiritModule" name="OSC" state="GOOD" type="3"/><module module_class="ComponentModule" name="Linker_Design_MSS::work" state="GOOD" type="1"/></dependentModules></vendorExtensions><busInterfaces><busInterface><name>MMUART_0_PADS</name><busType library="Internal" name="Group" vendor="Actel" version=""/><slave/><vendorExtensions><used>true</used></vendorExtensions><signalMap><signal><componentSignalName>MMUART_0_TXD</componentSignalName><busSignalName>MMUART_0_TXD</busSignalName></signal><signal><componentSignalName>MMUART_0_RXD</componentSignalName><busSignalName>MMUART_0_RXD</busSignalName></signal></signalMap></busInterface></busInterfaces><model><signals><signal><name>MMUART_0_TXD</name><direction>out</direction><export>true</export><vendorExtensions><pad>true</pad><padMacro/><padMacroPin/><used>true</used></vendorExtensions></signal><signal><name>MMUART_0_RXD</name><direction>in</direction><export>true</export><vendorExtensions><pad>true</pad><padMacro/><padMacroPin/><used>true</used></vendorExtensions></signal><signal><name>DEVRST_N</name><direction>in</direction><export>true</export><vendorExtensions><pad>true</pad><padMacro>SYSRESET</padMacro><padMacroPin>DEVRST_N</padMacroPin><used>true</used></vendorExtensions></signal></signals></model></Component>