#OPTIONS:"|-top|Linker_Design|-prodtype|synplify_pro|-primux|-dspmac|-pqdpadd|-fixsmult|-divnmod|-nram|-I|E:\\Ranjith\\Linker_Design\\synthesis\\|-I|C:\\Microsemi\\Libero_v11.3\\Synopsys\\synplify_I201309MSP1\\lib|-v2001|-devicelib|C:\\Microsemi\\Libero_v11.3\\Synopsys\\synplify_I201309MSP1\\lib\\generic\\smartfusion2.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLSRAM_LIB|-lib|COREAHBLSRAM_LIB|-lib|COREAHBLSRAM_LIB|-lib|COREAHBLSRAM_LIB|-lib|COREAHBLSRAM_LIB|-lib|work"
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#CUR:"E:\\Ranjith\\Linker_Design\\component\\Actel\\SgCore\\OSC\\1.0.100\\osc_comps.v":1390829465
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#CUR:"E:\\Ranjith\\Linker_Design\\component\\Actel\\DirectCore\\CoreAHBLite\\5.0.100\\rtl\\vlog\\core\\coreahblite_slavearbiter.v":1392095814
#CUR:"E:\\Ranjith\\Linker_Design\\component\\Actel\\DirectCore\\CoreAHBLite\\5.0.100\\rtl\\vlog\\core\\coreahblite_slavestage.v":1392095814
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#numinternalfiles:5
#defaultlanguage:verilog
0			"E:\Ranjith\Linker_Design\component\work\Linker_Design\FCCC_0\Linker_Design_FCCC_0_FCCC.v" verilog
1			"E:\Ranjith\Linker_Design\component\work\Linker_Design_MSS\Linker_Design_MSS_syn.v" verilog
2			"E:\Ranjith\Linker_Design\component\work\Linker_Design_MSS\Linker_Design_MSS.v" verilog
3			"E:\Ranjith\Linker_Design\component\Actel\SgCore\OSC\1.0.100\osc_comps.v" verilog
4			"E:\Ranjith\Linker_Design\component\work\Linker_Design\OSC_0\Linker_Design_OSC_0_OSC.v" verilog
5			"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v" verilog
6			"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v" verilog
7			"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v" verilog
8			"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v" verilog
9			"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v" verilog
10			"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v" verilog
11			"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v" verilog
12			"E:\Ranjith\Linker_Design\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core\AHBLSramIf.v" verilog
13			"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v" verilog
14			"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\usram_128to9216x8.v" verilog
15			"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v" verilog
16			"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v" verilog
17			"E:\Ranjith\Linker_Design\component\work\Linker_Design\Linker_Design.v" verilog
#Dependency Lists(Uses List)
0 -1
1 -1
2 -1
3 -1
4 -1
5 -1
6 -1
7 5 6
8 -1
9 8
10 7 9
11 10
12 -1
13 -1
14 -1
15 13 14
16 12 15
17 11 16 0 2 4
#Dependency Lists(Users Of)
0 17
1 -1
2 17
3 -1
4 17
5 7
6 7
7 10
8 9
9 10
10 11
11 17
12 16
13 15
14 15
15 16
16 17
17 -1
#Design Unit to File Association
module work Linker_Design_FCCC_0_FCCC 0
module work MSS_050 1
module work Linker_Design_MSS 2
module work RCOSC_1MHZ 3
module work RCOSC_25_50MHZ 3
module work XTLOSC 3
module work RCOSC_1MHZ_FAB 3
module work RCOSC_25_50MHZ_FAB 3
module work XTLOSC_FAB 3
module work Linker_Design_OSC_0_OSC 4
module work Linker_Design 17
module COREAHBLITE_LIB COREAHBLITE_ADDRDEC 5
module COREAHBLITE_LIB COREAHBLITE_DEFAULTSLAVESM 6
module COREAHBLITE_LIB COREAHBLITE_MASTERSTAGE 7
module COREAHBLITE_LIB COREAHBLITE_SLAVEARBITER 8
module COREAHBLITE_LIB COREAHBLITE_SLAVESTAGE 9
module COREAHBLITE_LIB COREAHBLITE_MATRIX4X16 10
module COREAHBLITE_LIB CoreAHBLite 11
module COREAHBLSRAM_LIB AHBLSramIf 12
module COREAHBLSRAM_LIB Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8 13
module COREAHBLSRAM_LIB Linker_Design_COREAHBLSRAM_0_usram_128to9216x8 14
module COREAHBLSRAM_LIB Linker_Design_COREAHBLSRAM_0_SramCtrlIf 15
module COREAHBLSRAM_LIB Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM 16
