Synopsys Generic Technology Mapper, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
Product Version I-2013.09M-SP1 

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 138MB)

@W: MO111 :"e:\ranjith\linker_design\component\work\linker_design_mss\linker_design_mss.v":42:14:42:31|Tristate driver FIC_0_AHB_M_HTRANS_1 on net FIC_0_AHB_M_HTRANS_1 has its enable tied to GND (module Linker_Design_MSS) 
@W: MO111 :"e:\ranjith\linker_design\component\work\linker_design\osc_0\linker_design_osc_0_osc.v":20:7:20:16|Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module Linker_Design_OSC_0_OSC) 
@W: MO111 :"e:\ranjith\linker_design\component\work\linker_design\osc_0\linker_design_osc_0_osc.v":19:7:19:16|Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module Linker_Design_OSC_0_OSC) 
@W: MO111 :"e:\ranjith\linker_design\component\work\linker_design\osc_0\linker_design_osc_0_osc.v":18:7:18:20|Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module Linker_Design_OSC_0_OSC) 
@W: MO111 :"e:\ranjith\linker_design\component\work\linker_design\osc_0\linker_design_osc_0_osc.v":17:7:17:20|Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module Linker_Design_OSC_0_OSC) 
@W: MO111 :"e:\ranjith\linker_design\component\work\linker_design\osc_0\linker_design_osc_0_osc.v":16:7:16:24|Tristate driver RCOSC_25_50MHZ_O2F on net RCOSC_25_50MHZ_O2F has its enable tied to GND (module Linker_Design_OSC_0_OSC) 
@W: MO111 :|Tristate driver Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS_t[0] on net Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS[0] has its enable tied to GND (module Linker_Design) 

Available hyper_sources - for debug and ip models
	None Found


Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 138MB)

@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[20] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[21] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[22] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[23] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[24] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[25] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[26] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[27] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_3.masterDataInProg[3] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_3.masterDataInProg[2] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_3.masterDataInProg[1] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":233:0:233:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[16] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[31],  because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[30]
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[29],  because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28]
Encoding state machine arbRegSMCurrentState[15:0] (view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter_0(verilog))
original code -> new code
   0000 -> 0000000000000001
   0001 -> 0000000000000010
   0010 -> 0000000000000100
   0011 -> 0000000000001000
   0100 -> 0000000000010000
   0101 -> 0000000000100000
   0110 -> 0000000001000000
   0111 -> 0000000010000000
   1000 -> 0000000100000000
   1001 -> 0000001000000000
   1010 -> 0000010000000000
   1011 -> 0000100000000000
   1100 -> 0001000000000000
   1101 -> 0010000000000000
   1110 -> 0100000000000000
   1111 -> 1000000000000000
@W: MO160 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Register bit arbRegSMCurrentState[12] is always 0, optimizing ...
@W: MO160 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Register bit arbRegSMCurrentState[8] is always 0, optimizing ...
@W: MO160 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Register bit arbRegSMCurrentState[4] is always 0, optimizing ...
Encoding state machine ahbcurr_state[2:0] (view:COREAHBLSRAM_LIB.AHBLSramIf(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblsram\2.0.113\rtl\vlog\core\ahblsramif.v":161:3:161:8|Removing sequential instance HADDR_d[16] in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblsram\2.0.113\rtl\vlog\core\ahblsramif.v":161:3:161:8|Removing sequential instance HADDR_d[17] in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblsram\2.0.113\rtl\vlog\core\ahblsramif.v":161:3:161:8|Removing sequential instance HADDR_d[18] in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblsram\2.0.113\rtl\vlog\core\ahblsramif.v":161:3:161:8|Removing sequential instance HADDR_d[19] in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs 
Encoding state machine sramcurr_state[2:0] (view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_SramCtrlIf_0s_16384s_512s_32s_0_1_2(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[16] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[17] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[18] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[19] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28],  because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_0.regHTRANS
@W: BN132 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":229:4:229:9|Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_1.ckRdAddr[11],  because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_0.ckRdAddr[11]
@W: BN132 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":229:4:229:9|Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_2.ckRdAddr[11],  because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_0.ckRdAddr[11]
@W: BN132 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":229:4:229:9|Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_3.ckRdAddr[11],  because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_0.ckRdAddr[11]
@W: BN132 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":229:4:229:9|Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_1.ckRdAddr[12],  because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_0.ckRdAddr[12]
@W: BN132 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":229:4:229:9|Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_2.ckRdAddr[12],  because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_0.ckRdAddr[12]
@W: BN132 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":229:4:229:9|Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_3.ckRdAddr[12],  because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_0.ckRdAddr[12]
@W: BN132 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":229:4:229:9|Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_1.ckRdAddr[13],  because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_0.ckRdAddr[13]
@W: BN132 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":229:4:229:9|Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_2.ckRdAddr[13],  because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_0.ckRdAddr[13]
@W: BN132 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":229:4:229:9|Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_3.ckRdAddr[13],  because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_0.ckRdAddr[13]
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblsram\2.0.113\rtl\vlog\core\ahblsramif.v":161:3:161:8|Removing sequential instance COREAHBLSRAM_0.U_AHBLSramIf.HSIZE_d[2] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[30] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 

Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 139MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 139MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 139MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 141MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 141MB)


Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 141MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 148MB peak: 151MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -1.77ns		 404 /       114
   2		0h:00m:01s		    -1.64ns		 404 /       114
------------------------------------------------------------




Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:02s		    -0.45ns		 417 /       114
------------------------------------------------------------



Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:02s		    -0.45ns		 417 /       114
------------------------------------------------------------

@N: FP130 |Promoting Net SYSRESET_0_POWER_ON_RESET_N on CLKINT  I_133 

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 141MB peak: 151MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 142MB peak: 151MB)



#### START OF CLOCK OPTIMIZATION REPORT #####[

Clock optimization not enabled
1 non-gated/non-generated clock tree(s) driving 179 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

===================================== Non-Gated/Non-Generated Clocks =====================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                   
----------------------------------------------------------------------------------------------------------
@K:CKID0001       FCCC_0.GL0_INST     CLKINT                 179        Linker_Design_MSS_0.MSS_ADLIB_INST
==========================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]

Writing Analyst data base E:\Ranjith\Linker_Design\synthesis\Linker_Design.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 139MB peak: 151MB)

Writing EDIF Netlist and constraint files
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
I-2013.09M-SP1 

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 140MB peak: 151MB)

@W: MT246 :"e:\ranjith\linker_design\component\work\linker_design\linker_design.v":632:9:632:18|Blackbox SYSRESET is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"e:\ranjith\linker_design\component\work\linker_design\fccc_0\linker_design_fccc_0_fccc.v":20:36:20:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:FCCC_0.GL0_net"



##### START OF TIMING REPORT #####[
# Timing Report written on Fri Apr 04 11:20:06 2014
#


Top view:               Linker_Design
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    E:\Ranjith\Linker_Design\synthesis\Linker_Design_fsm.sdc
                       
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: 0.572

                                                     Requested     Estimated     Requested     Estimated               Clock        Clock              
Starting Clock                                       Frequency     Frequency     Period        Period        Slack     Type         Group              
-------------------------------------------------------------------------------------------------------------------------------------------------------
Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     116.4 MHz     10.000        8.589         1.411     inferred     Inferred_clkgroup_0
System                                               100.0 MHz     354.8 MHz     10.000        2.818         7.182     system       system_clkgroup    
=======================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                                              |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                          Ending                                            |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                            System                                            |  10.000      7.182  |  No paths    -      |  No paths    -      |  No paths    -    
System                                            Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock  |  10.000      6.523  |  No paths    -      |  No paths    -      |  No paths    -    
Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock  System                                            |  10.000      0.572  |  No paths    -      |  No paths    -      |  No paths    -    
Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock  Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock  |  10.000      1.411  |  No paths    -      |  No paths    -      |  No paths    -    
==========================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                                                 Starting                                                                                                                               Arrival          
Instance                                                                         Reference                                            Type        Pin                Net                                                Time        Slack
                                                                                 Clock                                                                                                                                                   
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Linker_Design_MSS_0.MSS_ADLIB_INST                                               Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     MSS_050     F_HM0_ADDR[30]     Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[30]     2.999       0.572
Linker_Design_MSS_0.MSS_ADLIB_INST                                               Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     MSS_050     F_HM0_ADDR[29]     Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[29]     3.021       0.631
Linker_Design_MSS_0.MSS_ADLIB_INST                                               Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     MSS_050     F_HM0_SIZE[0]      Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE[0]      3.139       0.638
Linker_Design_MSS_0.MSS_ADLIB_INST                                               Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     MSS_050     F_HM0_ADDR[31]     Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[31]     3.049       0.644
Linker_Design_MSS_0.MSS_ADLIB_INST                                               Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     MSS_050     F_HM0_TRANS1       Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS[1]     3.106       0.807
Linker_Design_MSS_0.MSS_ADLIB_INST                                               Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     MSS_050     F_HM0_ADDR[28]     Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[28]     2.980       1.045
Linker_Design_MSS_0.MSS_ADLIB_INST                                               Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     MSS_050     F_HM0_SIZE[1]      Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE[1]      3.163       1.151
CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[13]     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  arbRegSMCurrentState[13]                           0.108       1.641
CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[1]      Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  arbRegSMCurrentState[1]                            0.108       1.911
CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[5]      Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  arbRegSMCurrentState[5]                            0.108       1.929
=========================================================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                       Starting                                                                                    Required          
Instance                                               Reference                                            Type        Pin          Net           Time         Slack
                                                       Clock                                                                                                         
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block0     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     RAM1K18     A_WEN[0]     wen_a0[0]     10.000       0.572
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block0     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     RAM1K18     A_WEN[0]     wen_a0[0]     10.000       0.572
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block1     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     RAM1K18     A_WEN[0]     wen_a1[0]     10.000       0.572
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block1     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     RAM1K18     A_WEN[0]     wen_a1[0]     10.000       0.572
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block2     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     RAM1K18     A_WEN[0]     wen_a2[0]     10.000       0.572
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block2     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     RAM1K18     A_WEN[0]     wen_a2[0]     10.000       0.572
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block3     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     RAM1K18     A_WEN[0]     wen_a3[0]     10.000       0.572
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block3     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     RAM1K18     A_WEN[0]     wen_a3[0]     10.000       0.572
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_3.block0     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     RAM1K18     A_WEN[0]     wen_a0[0]     10.000       0.575
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_3.block0     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     RAM1K18     A_WEN[0]     wen_a0[0]     10.000       0.575
=====================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         10.000

    - Propagation time:                      9.428
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     0.572

    Number of logic level(s):                5
    Starting point:                          Linker_Design_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[30]
    Ending point:                            COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block3 / A_WEN[0]
    The start point is clocked by            Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
    The end   point is clocked by            System [rising]

Instance / Net                                                                                     Pin                Pin               Arrival     No. of    
Name                                                                                   Type        Name               Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------
Linker_Design_MSS_0.MSS_ADLIB_INST                                                     MSS_050     F_HM0_ADDR[30]     Out     2.999     2.999       -         
Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[30]                                         Net         -                  -       1.135     -           8         
CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.MASTERADDRINPROG_i_a2_d_c_c[0]     CFG4        B                  In      -         4.134       -         
CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.MASTERADDRINPROG_i_a2_d_c_c[0]     CFG4        Y                  Out     0.143     4.277       -         
MASTERADDRINPROG_i_a2_d_c_c[0]                                                         Net         -                  -       0.678     -           3         
COREAHBLSRAM_0.U_AHBLSramIf.HSIZE_d_RNI07AN1[0]                                        CFG4        D                  In      -         4.955       -         
COREAHBLSRAM_0.U_AHBLSramIf.HSIZE_d_RNI07AN1[0]                                        CFG4        Y                  Out     0.470     5.425       -         
ahbsram_N_4                                                                            Net         -                  -       0.556     -           1         
COREAHBLSRAM_0.U_SramCtrlIf.sram_wen_mem_ss3_1                                         CFG4        B                  In      -         5.981       -         
COREAHBLSRAM_0.U_SramCtrlIf.sram_wen_mem_ss3_1                                         CFG4        Y                  Out     0.153     6.134       -         
sram_wen_mem_ss3_1                                                                     Net         -                  -       0.556     -           1         
COREAHBLSRAM_0.U_SramCtrlIf.sram_wen_mem_ss3                                           CFG4        C                  In      -         6.689       -         
COREAHBLSRAM_0.U_SramCtrlIf.sram_wen_mem_ss3                                           CFG4        Y                  Out     0.226     6.915       -         
sram_wen_mem_ss3                                                                       Net         -                  -       0.923     -           16        
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block3_RNO                                 CFG4        D                  In      -         7.838       -         
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block3_RNO                                 CFG4        Y                  Out     0.472     8.311       -         
wen_a3[0]                                                                              Net         -                  -       1.117     -           1         
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block3                                     RAM1K18     A_WEN[0]           In      -         9.428       -         
==============================================================================================================================================================
Total path delay (propagation time + setup) of 9.428 is 4.463(47.3%) logic and 4.964(52.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                       Starting                                                 Arrival          
Instance                                               Reference     Type        Pin           Net              Time        Slack
                                                       Clock                                                                     
---------------------------------------------------------------------------------------------------------------------------------
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.block1     System        RAM1K18     A_DOUT[0]     readData1[0]     0.000       6.523
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.block1     System        RAM1K18     A_DOUT[0]     readData1[0]     0.000       6.523
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.block1     System        RAM1K18     A_DOUT[0]     readData1[0]     0.000       6.523
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block1     System        RAM1K18     A_DOUT[0]     readData1[0]     0.000       6.523
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.block1     System        RAM1K18     A_DOUT[0]     readData1[0]     0.000       6.523
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block1     System        RAM1K18     A_DOUT[0]     readData1[0]     0.000       6.523
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.block1     System        RAM1K18     A_DOUT[1]     readData1[1]     0.000       6.523
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.block1     System        RAM1K18     A_DOUT[1]     readData1[1]     0.000       6.523
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.block1     System        RAM1K18     A_DOUT[1]     readData1[1]     0.000       6.523
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.block1     System        RAM1K18     A_DOUT[1]     readData1[1]     0.000       6.523
=================================================================================================================================


Ending Points with Worst Slack
******************************

                                                 Starting                                        Required          
Instance                                         Reference     Type     Pin     Net              Time         Slack
                                                 Clock                                                             
-------------------------------------------------------------------------------------------------------------------
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[0]     System        SLE      D       ram_rdata[0]     9.745        6.523
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[1]     System        SLE      D       ram_rdata[1]     9.745        6.523
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[2]     System        SLE      D       ram_rdata[2]     9.745        6.523
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[3]     System        SLE      D       ram_rdata[3]     9.745        6.523
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[4]     System        SLE      D       ram_rdata[4]     9.745        6.523
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[5]     System        SLE      D       ram_rdata[5]     9.745        6.523
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[6]     System        SLE      D       ram_rdata[6]     9.745        6.523
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[7]     System        SLE      D       ram_rdata[7]     9.745        6.523
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[8]     System        SLE      D       ram_rdata[8]     9.745        6.523
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[9]     System        SLE      D       ram_rdata[9]     9.745        6.523
===================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.255
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.745

    - Propagation time:                      3.222
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 6.523

    Number of logic level(s):                3
    Starting point:                          COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.block1 / A_DOUT[0]
    Ending point:                            COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[8] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK

Instance / Net                                                                   Pin           Pin               Arrival     No. of    
Name                                                                 Type        Name          Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.block1                   RAM1K18     A_DOUT[0]     Out     0.000     0.000       -         
readData1[0]                                                         Net         -             -       1.117     -           1         
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.readData_7_bm_1_1[0]     CFG4        B             In      -         1.117       -         
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.readData_7_bm_1_1[0]     CFG4        Y             Out     0.153     1.270       -         
readData_7_bm_1_1[0]                                                 Net         -             -       0.556     -           1         
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.readData_7_bm[0]         CFG4        D             In      -         1.826       -         
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.readData_7_bm[0]         CFG4        Y             Out     0.472     2.298       -         
readData_7_bm_1[0]                                                   Net         -             -       0.556     -           1         
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.readData_7_ns[0]         CFG3        C             In      -         2.854       -         
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.readData_7_ns[0]         CFG3        Y             Out     0.209     3.063       -         
ram_rdata[8]                                                         Net         -             -       0.159     -           1         
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[8]                         SLE         D             In      -         3.222       -         
=======================================================================================================================================
Total path delay (propagation time + setup) of 3.477 is 1.090(31.4%) logic and 2.387(68.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report for Linker_Design 

Mapping to part: m2s050tfbga896std
Cell usage:
CCC             1 use
CLKINT          2 uses
MSS_050         1 use
RCOSC_25_50MHZ  1 use
SYSRESET        1 use
CFG2           89 uses
CFG3           67 uses
CFG4           259 uses


Sequential Cells: 
SLE            114 uses

DSP Blocks:    0

I/O ports: 3
I/O primitives: 2
INBUF          1 use
TRIBUFF        1 use


Global Clock Buffers: 2


RAM/ROM usage summary
Block Rams (RAM1K18) : 32

Total LUTs:    415

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 52MB peak: 151MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Fri Apr 04 11:20:06 2014

###########################################################]
