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<doc>
<title>Compile Report</title>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.3 (Version 11.3.0.112)</text>
<text>Date: Fri Apr 04 11:20:14 2014
</text>
<section><name>Device Selection</name></section>
<table>
<header>
</header>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Device</cell>
 <cell>M2S050T</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>896 FBGA</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>STD</cell>
</row>
<row>
 <cell>Temp</cell>
 <cell>0:25:85</cell>
</row>
<row>
 <cell>Voltage</cell>
 <cell>1.26:1.20:1.14</cell>
</row>
<row>
 <cell>Core Voltage</cell>
 <cell>1.2V</cell>
</row>
<row>
 <cell>Ramp Rate</cell>
 <cell>100ms Minimum</cell>
</row>
<row>
 <cell>System Controller Suspend Mode</cell>
 <cell>No</cell>
</row>
<row>
 <cell>PLL Supply Voltage</cell>
 <cell>2.5V</cell>
</row>
<row>
 <cell>Default I/O technology</cell>
 <cell>LVCMOS 2.5V</cell>
</row>
<row>
 <cell>Restrict Probe Pins</cell>
 <cell>Yes</cell>
</row>
</table>
<section><name>Source Files</name></section>
<table>
<header>
</header>
<row>
 <cell>Topcell</cell>
 <cell>Linker_Design</cell>
</row>
<row>
 <cell>Format</cell>
 <cell>EDIF</cell>
</row>
<row>
 <cell>Source</cell>
 <cell>E:\Ranjith\Linker_Design\synthesis\Linker_Design.edn</cell>
</row>
</table>
<section><name>Options</name></section>
<table>
<header>
</header>
<row>
 <cell>Merge User SDC file(s) with Existing Timing Constraints</cell>
 <cell>true</cell>
</row>
<row>
 <cell>Abort Compile if errors are found in PDC file(s)</cell>
 <cell>true</cell>
</row>
<row>
 <cell>Limit the number of high fanout nets to display to</cell>
 <cell>10</cell>
</row>
</table>
<section><name>Netlist Optimization</name></section>
<table>
<header>
</header>
<row>
 <cell>Dangling net drivers</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Buffers</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Inverters</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Tieoff</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Fan-In combining</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Logic combining</cell>
 <cell>0</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Total macros optimized</cell>
 <cell>0</cell>
</row>
</table>
<section><name>Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Used</cell>
 <cell>Total</cell>
 <cell>Percentage</cell>
</header>
<row>
 <cell>COMB</cell>
 <cell>1567</cell>
 <cell>56340</cell>
 <cell>2.78</cell>
</row>
<row>
 <cell>SEQ</cell>
 <cell>1266</cell>
 <cell>56340</cell>
 <cell>2.25</cell>
</row>
<row>
 <cell>IO (W/ clocks)</cell>
 <cell>2</cell>
 <cell>375</cell>
 <cell>0.53</cell>
</row>
<row>
 <cell>Differential IO</cell>
 <cell>0</cell>
 <cell>187</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>GLOBAL</cell>
 <cell>2</cell>
 <cell>16</cell>
 <cell>12.50</cell>
</row>
<row>
 <cell>RGB</cell>
 <cell>2</cell>
 <cell>1088</cell>
 <cell>0.18</cell>
</row>
<row>
 <cell>RAM64x18</cell>
 <cell>0</cell>
 <cell>72</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>RAM1K18</cell>
 <cell>32</cell>
 <cell>69</cell>
 <cell>46.38</cell>
</row>
<row>
 <cell>MACC</cell>
 <cell>0</cell>
 <cell>72</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>RCOSC_25_50MHZ</cell>
 <cell>1</cell>
 <cell>1</cell>
 <cell>100.00</cell>
</row>
<row>
 <cell>RCOSC_1MHZ</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>XTLOSC</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>CCC</cell>
 <cell>1</cell>
 <cell>6</cell>
 <cell>16.67</cell>
</row>
<row>
 <cell>SERDESIF</cell>
 <cell>0</cell>
 <cell>2</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>MSS</cell>
 <cell>1</cell>
 <cell>1</cell>
 <cell>100.00</cell>
</row>
<row>
 <cell>FDDR</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>SYSCTRL</cell>
 <cell>1</cell>
 <cell>1</cell>
 <cell>100.00</cell>
</row>
</table>
<section><name>Carry Chains</name></section>
<table>
<header>
</header>
<row>
 <cell>Length</cell>
 <cell>Used</cell>
</row>
<row>
 <cell>Total</cell>
 <cell>0</cell>
</row>
</table>
<section><name>I/O Function</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>w/o register</cell>
 <cell>w/ register</cell>
 <cell>w/ DDR register</cell>
</header>
<row>
 <cell>Input I/O</cell>
 <cell>1</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Output I/O</cell>
 <cell>1</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Bidirectional I/O</cell>
 <cell>0</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Differential Input I/O Pairs</cell>
 <cell>0</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Differential Output I/O Pairs</cell>
 <cell>0</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
</table>
<section><name>I/O Technology</name></section>
<table>
<header>
 <cell>I/O Standard</cell>
 <cell>Vcci</cell>
 <cell>Vref</cell>
 <cell>Input</cell>
 <cell>Output</cell>
 <cell>Bidirectional</cell>
</header>
<row>
 <cell>LVCMOS25</cell>
 <cell> 2.50v</cell>
 <cell> N/A</cell>
 <cell> 1</cell>
 <cell> 1</cell>
 <cell> 0</cell>
</row>
</table>
<section><name>I/O Placement</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Count</cell>
 <cell>Percentage</cell>
</header>
<row>
 <cell>Locked</cell>
 <cell> 2</cell>
 <cell>100.00%</cell>
</row>
<row>
 <cell>Placed</cell>
 <cell> 0</cell>
 <cell>0.00%</cell>
</row>
<row>
 <cell>UnPlaced</cell>
 <cell> 0</cell>
 <cell>0.00%</cell>
</row>
</table>
<section><name>Nets assigned to chip global resources</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>179</cell>
 <cell>INT_NET</cell>
 <cell>Net   : FCCC_0_GL0_0</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: FCCC_0/GL0_INST/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>178</cell>
 <cell>INT_NET</cell>
 <cell>Net   : SYSRESET_0_POWER_ON_RESET_N</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: SYSRESET_0_RNIHNV1/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
</table>
<section><name>Nets assigned to row global resources</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
</table>
<section><name>High fanout nets</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>97</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/U_SramCtrlIf/ckRdAddr[12]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_SramCtrlIf/genblk1.byte_0/ckRdAddr[12]</cell>
</row>
<row>
 <cell>95</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/U_SramCtrlIf/ckRdAddr[13]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_SramCtrlIf/genblk1.byte_0/ckRdAddr[13]</cell>
</row>
<row>
 <cell>64</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/ahbsram_addr[2]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_AHBLSramIf/HADDR_d[2]</cell>
</row>
<row>
 <cell>64</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/ahbsram_addr[3]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_AHBLSramIf/HADDR_d[3]</cell>
</row>
<row>
 <cell>64</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/ahbsram_addr[4]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_AHBLSramIf/HADDR_d[4]</cell>
</row>
<row>
 <cell>64</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/ahbsram_addr[5]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_AHBLSramIf/HADDR_d[5]</cell>
</row>
<row>
 <cell>64</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/ahbsram_addr[6]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_AHBLSramIf/HADDR_d[6]</cell>
</row>
<row>
 <cell>64</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/ahbsram_addr[7]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_AHBLSramIf/HADDR_d[7]</cell>
</row>
<row>
 <cell>64</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/ahbsram_addr[8]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_AHBLSramIf/HADDR_d[8]</cell>
</row>
<row>
 <cell>64</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/ahbsram_addr[9]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_AHBLSramIf/HADDR_d[9]</cell>
</row>
</table>
<section><name>High fanout nets (through buffer trees)</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>97</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/U_SramCtrlIf/ckRdAddr[12]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_SramCtrlIf/genblk1.byte_0/ckRdAddr[12]</cell>
</row>
<row>
 <cell>95</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/U_SramCtrlIf/ckRdAddr[13]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_SramCtrlIf/genblk1.byte_0/ckRdAddr[13]</cell>
</row>
<row>
 <cell>64</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/ahbsram_addr[2]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_AHBLSramIf/HADDR_d[2]</cell>
</row>
<row>
 <cell>64</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/ahbsram_addr[3]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_AHBLSramIf/HADDR_d[3]</cell>
</row>
<row>
 <cell>64</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/ahbsram_addr[4]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_AHBLSramIf/HADDR_d[4]</cell>
</row>
<row>
 <cell>64</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/ahbsram_addr[5]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_AHBLSramIf/HADDR_d[5]</cell>
</row>
<row>
 <cell>64</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/ahbsram_addr[6]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_AHBLSramIf/HADDR_d[6]</cell>
</row>
<row>
 <cell>64</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/ahbsram_addr[7]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_AHBLSramIf/HADDR_d[7]</cell>
</row>
<row>
 <cell>64</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/ahbsram_addr[8]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_AHBLSramIf/HADDR_d[8]</cell>
</row>
<row>
 <cell>64</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/ahbsram_addr[9]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_AHBLSramIf/HADDR_d[9]</cell>
</row>
</table>
</doc>
