#Build: Synplify Pro I-2013.09M-SP1 , Build 034R, Jan 17 2014
#install: C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1
#OS: Windows 7 6.1
#Hostname: W764-TECHSUPPOR

#Implementation: synthesis

$ Start of Compile
#Thu Apr 03 09:36:05 2014

Synopsys Verilog Compiler, version comp201309rcp1, Build 078R, built Jan 14 2014
@N|Running in 64-bit mode
Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

@I::"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.v"
@I::"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vlog\umr_capim.v"
@I::"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vlog\scemi_objects.v"
@I::"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vlog\scemi_pipes.svh"
@I::"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vlog\hypermods.v"
@I::"E:\Ranjith\Linker_Design\component\work\Linker_Design\FCCC_0\Linker_Design_FCCC_0_FCCC.v"
@I::"E:\Ranjith\Linker_Design\component\work\Linker_Design_MSS\Linker_Design_MSS_syn.v"
@I::"E:\Ranjith\Linker_Design\component\work\Linker_Design_MSS\Linker_Design_MSS.v"
@I::"E:\Ranjith\Linker_Design\component\Actel\SgCore\OSC\1.0.100\osc_comps.v"
@I::"E:\Ranjith\Linker_Design\component\work\Linker_Design\OSC_0\Linker_Design_OSC_0_OSC.v"
@I::"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v"
@I::"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v"
@I::"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v"
@I::"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v"
@I::"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v"
@I::"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v"
@I::"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v"
@I::"E:\Ranjith\Linker_Design\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core\AHBLSramIf.v"
@I::"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v"
@I::"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\usram_128to9216x8.v"
@I::"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v"
@I::"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v"
@I::"E:\Ranjith\Linker_Design\component\work\Linker_Design\Linker_Design.v"
@W: CG775 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":32:7:32:17|Found Component CoreAHBLite in library COREAHBLITE_LIB
@W: CG775 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v":29:7:29:47|Found Component Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM in library COREAHBLSRAM_LIB
Verilog syntax check successful!
Selecting top level module Linker_Design
@W: CG775 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":32:7:32:17|Found Component CoreAHBLite in library COREAHBLITE_LIB
@N: CG364 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v":29:7:29:25|Synthesizing module COREAHBLITE_ADDRDEC

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000000000000
	M_AHBSLOTENABLE=17'b00000000000001000
	MSB_ADDR=32'b00000000000000000000000000011111
	SLAVE_0=16'b0000000000000001
	SLAVE_1=16'b0000000000000010
	SLAVE_2=16'b0000000000000100
	SLAVE_3=16'b0000000000001000
	SLAVE_4=16'b0000000000010000
	SLAVE_5=16'b0000000000100000
	SLAVE_6=16'b0000000001000000
	SLAVE_7=16'b0000000010000000
	SLAVE_8=16'b0000000100000000
	SLAVE_9=16'b0000001000000000
	SLAVE_10=16'b0000010000000000
	SLAVE_11=16'b0000100000000000
	SLAVE_12=16'b0001000000000000
	SLAVE_13=16'b0010000000000000
	SLAVE_14=16'b0100000000000000
	SLAVE_15=16'b1000000000000000
	NONE=16'b0000000000000000
   Generated name = COREAHBLITE_ADDRDEC_Z1

@N: CG364 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v":29:7:29:32|Synthesizing module COREAHBLITE_DEFAULTSLAVESM

@N: CG364 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":31:7:31:29|Synthesizing module COREAHBLITE_MASTERSTAGE

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000000000000
	M_AHBSLOTENABLE=17'b00000000000001000
	IDLE=1'b0
	REGISTERED=1'b1
	SLAVE_NONE=17'b00000000000000000
   Generated name = COREAHBLITE_MASTERSTAGE_1_1_0_8_0_1_0

@N: CL177 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":629:0:629:5|Sharing sequential element addrRegSMCurrentState.
@N: CG364 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v":29:7:29:25|Synthesizing module COREAHBLITE_ADDRDEC

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000000000000
	M_AHBSLOTENABLE=17'b00000000000000000
	MSB_ADDR=32'b00000000000000000000000000011111
	SLAVE_0=16'b0000000000000001
	SLAVE_1=16'b0000000000000010
	SLAVE_2=16'b0000000000000100
	SLAVE_3=16'b0000000000001000
	SLAVE_4=16'b0000000000010000
	SLAVE_5=16'b0000000000100000
	SLAVE_6=16'b0000000001000000
	SLAVE_7=16'b0000000010000000
	SLAVE_8=16'b0000000100000000
	SLAVE_9=16'b0000001000000000
	SLAVE_10=16'b0000010000000000
	SLAVE_11=16'b0000100000000000
	SLAVE_12=16'b0001000000000000
	SLAVE_13=16'b0010000000000000
	SLAVE_14=16'b0100000000000000
	SLAVE_15=16'b1000000000000000
	NONE=16'b0000000000000000
   Generated name = COREAHBLITE_ADDRDEC_Z2

@N: CG364 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":31:7:31:29|Synthesizing module COREAHBLITE_MASTERSTAGE

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000000000000
	M_AHBSLOTENABLE=17'b00000000000000000
	IDLE=1'b0
	REGISTERED=1'b1
	SLAVE_NONE=17'b00000000000000000
   Generated name = COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0

@N: CL177 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":629:0:629:5|Sharing sequential element addrRegSMCurrentState.
@N: CG364 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":28:7:28:30|Synthesizing module COREAHBLITE_SLAVEARBITER

@N: CG364 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":30:7:30:28|Synthesizing module COREAHBLITE_SLAVESTAGE

@N: CG364 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":31:7:31:28|Synthesizing module COREAHBLITE_MATRIX4X16

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000000000000
	M0_AHBSLOTENABLE=17'b00000000000001000
	M1_AHBSLOTENABLE=17'b00000000000000000
	M2_AHBSLOTENABLE=17'b00000000000000000
	M3_AHBSLOTENABLE=17'b00000000000000000
   Generated name = COREAHBLITE_MATRIX4X16_1_1_0_8_0_0_0

@N: CG364 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":32:7:32:17|Synthesizing module CoreAHBLite

	FAMILY=6'b010011
	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC_0=1'b0
	SC_1=1'b0
	SC_2=1'b0
	SC_3=1'b0
	SC_4=1'b0
	SC_5=1'b0
	SC_6=1'b0
	SC_7=1'b0
	SC_8=1'b0
	SC_9=1'b0
	SC_10=1'b0
	SC_11=1'b0
	SC_12=1'b0
	SC_13=1'b0
	SC_14=1'b0
	SC_15=1'b0
	M0_AHBSLOT0ENABLE=1'b0
	M0_AHBSLOT1ENABLE=1'b0
	M0_AHBSLOT2ENABLE=1'b0
	M0_AHBSLOT3ENABLE=1'b1
	M0_AHBSLOT4ENABLE=1'b0
	M0_AHBSLOT5ENABLE=1'b0
	M0_AHBSLOT6ENABLE=1'b0
	M0_AHBSLOT7ENABLE=1'b0
	M0_AHBSLOT8ENABLE=1'b0
	M0_AHBSLOT9ENABLE=1'b0
	M0_AHBSLOT10ENABLE=1'b0
	M0_AHBSLOT11ENABLE=1'b0
	M0_AHBSLOT12ENABLE=1'b0
	M0_AHBSLOT13ENABLE=1'b0
	M0_AHBSLOT14ENABLE=1'b0
	M0_AHBSLOT15ENABLE=1'b0
	M0_AHBSLOT16ENABLE=1'b0
	M1_AHBSLOT0ENABLE=1'b0
	M1_AHBSLOT1ENABLE=1'b0
	M1_AHBSLOT2ENABLE=1'b0
	M1_AHBSLOT3ENABLE=1'b0
	M1_AHBSLOT4ENABLE=1'b0
	M1_AHBSLOT5ENABLE=1'b0
	M1_AHBSLOT6ENABLE=1'b0
	M1_AHBSLOT7ENABLE=1'b0
	M1_AHBSLOT8ENABLE=1'b0
	M1_AHBSLOT9ENABLE=1'b0
	M1_AHBSLOT10ENABLE=1'b0
	M1_AHBSLOT11ENABLE=1'b0
	M1_AHBSLOT12ENABLE=1'b0
	M1_AHBSLOT13ENABLE=1'b0
	M1_AHBSLOT14ENABLE=1'b0
	M1_AHBSLOT15ENABLE=1'b0
	M1_AHBSLOT16ENABLE=1'b0
	M2_AHBSLOT0ENABLE=1'b0
	M2_AHBSLOT1ENABLE=1'b0
	M2_AHBSLOT2ENABLE=1'b0
	M2_AHBSLOT3ENABLE=1'b0
	M2_AHBSLOT4ENABLE=1'b0
	M2_AHBSLOT5ENABLE=1'b0
	M2_AHBSLOT6ENABLE=1'b0
	M2_AHBSLOT7ENABLE=1'b0
	M2_AHBSLOT8ENABLE=1'b0
	M2_AHBSLOT9ENABLE=1'b0
	M2_AHBSLOT10ENABLE=1'b0
	M2_AHBSLOT11ENABLE=1'b0
	M2_AHBSLOT12ENABLE=1'b0
	M2_AHBSLOT13ENABLE=1'b0
	M2_AHBSLOT14ENABLE=1'b0
	M2_AHBSLOT15ENABLE=1'b0
	M2_AHBSLOT16ENABLE=1'b0
	M3_AHBSLOT0ENABLE=1'b0
	M3_AHBSLOT1ENABLE=1'b0
	M3_AHBSLOT2ENABLE=1'b0
	M3_AHBSLOT3ENABLE=1'b0
	M3_AHBSLOT4ENABLE=1'b0
	M3_AHBSLOT5ENABLE=1'b0
	M3_AHBSLOT6ENABLE=1'b0
	M3_AHBSLOT7ENABLE=1'b0
	M3_AHBSLOT8ENABLE=1'b0
	M3_AHBSLOT9ENABLE=1'b0
	M3_AHBSLOT10ENABLE=1'b0
	M3_AHBSLOT11ENABLE=1'b0
	M3_AHBSLOT12ENABLE=1'b0
	M3_AHBSLOT13ENABLE=1'b0
	M3_AHBSLOT14ENABLE=1'b0
	M3_AHBSLOT15ENABLE=1'b0
	M3_AHBSLOT16ENABLE=1'b0
	M0_AHBSLOTENABLE=17'b00000000000001000
	M1_AHBSLOTENABLE=17'b00000000000000000
	M2_AHBSLOTENABLE=17'b00000000000000000
	M3_AHBSLOTENABLE=17'b00000000000000000
	SC=16'b0000000000000000
   Generated name = CoreAHBLite_Z3

@W: CG775 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v":29:7:29:47|Found Component Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM in library COREAHBLSRAM_LIB
@N: CG364 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core\AHBLSramIf.v":29:7:29:16|Synthesizing module AHBLSramIf

@W: CL169 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core\AHBLSramIf.v":161:3:161:8|Pruning register HWDATA_d[31:0] 

@W: CL169 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core\AHBLSramIf.v":161:3:161:8|Pruning register HTRANS_d[1:0] 

@W: CL169 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core\AHBLSramIf.v":161:3:161:8|Pruning register HSEL_d 

@W: CL169 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core\AHBLSramIf.v":161:3:161:8|Pruning register HREADYIN_d 

@N: CG364 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":29:7:29:45|Synthesizing module Linker_Design_COREAHBLSRAM_0_SramCtrlIf

	SEL_SRAM_TYPE=32'b00000000000000000000000000000000
	LSRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000000000100000000000
	USRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000000000001000000000
	AHB_DWIDTH=32'b00000000000000000000000000100000
	S_IDLE=2'b00
	S_WR=2'b01
	S_RD=2'b10
   Generated name = Linker_Design_COREAHBLSRAM_0_SramCtrlIf_0s_2048s_512s_32s_0_1_2

@N: CG364 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.v":377:7:377:13|Synthesizing module RAM1K18

@N: CG364 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":28:7:28:55|Synthesizing module Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8

	DEPTH=32'b00000000000000000000100000000000
	AHB_DWIDTH=32'b00000000000000000000000000001000
   Generated name = Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s

@W: CL169 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":229:4:229:9|Pruning register ckRdAddr[15:9] 

@N: CG179 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":381:26:381:38|Removing redundant assignment
@W: CG133 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":95:31:95:49|No assignment to ahbsram_wdata_upd_r
@W: CG133 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":96:31:96:51|No assignment to u_ahbsram_wdata_upd_r
@W: CG360 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":103:31:103:42|No assignment to wire u_BUSY_all_0

@W: CG360 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":104:31:104:42|No assignment to wire u_BUSY_all_1

@W: CG360 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":105:31:105:42|No assignment to wire u_BUSY_all_2

@W: CG360 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":106:31:106:42|No assignment to wire u_BUSY_all_3

@W: CG360 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":113:31:113:49|No assignment to wire u_ahbsram_wdata_upd

@N: CG364 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v":29:7:29:47|Synthesizing module Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM

	FAMILY=32'b00000000000000000000000000010011
	AHB_DWIDTH=32'b00000000000000000000000000100000
	AHB_AWIDTH=32'b00000000000000000000000000100000
	LSRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000000000100000000000
	USRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000000000001000000000
	SEL_SRAM_TYPE=32'b00000000000000000000000000000000
   Generated name = Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM_19s_32s_32s_2048s_512s_0s

@N: CG364 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.v":371:7:371:9|Synthesizing module VCC

@N: CG364 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.v":367:7:367:9|Synthesizing module GND

@N: CG364 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.v":362:7:362:12|Synthesizing module CLKINT

@N: CG364 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.v":722:7:722:9|Synthesizing module CCC

@N: CG364 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\FCCC_0\Linker_Design_FCCC_0_FCCC.v":5:7:5:31|Synthesizing module Linker_Design_FCCC_0_FCCC

@N: CG364 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.v":268:7:268:11|Synthesizing module INBUF

@N: CG364 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.v":280:7:280:13|Synthesizing module TRIBUFF

@N: CG364 :"E:\Ranjith\Linker_Design\component\work\Linker_Design_MSS\Linker_Design_MSS_syn.v":5:7:5:13|Synthesizing module MSS_050

@N: CG364 :"E:\Ranjith\Linker_Design\component\work\Linker_Design_MSS\Linker_Design_MSS.v":9:7:9:23|Synthesizing module Linker_Design_MSS

@W: CG360 :"E:\Ranjith\Linker_Design\component\work\Linker_Design_MSS\Linker_Design_MSS.v":57:14:57:33|No assignment to wire FIC_0_AHB_M_HTRANS_0

@N: CG364 :"E:\Ranjith\Linker_Design\component\Actel\SgCore\OSC\1.0.100\osc_comps.v":11:7:11:20|Synthesizing module RCOSC_25_50MHZ

@N: CG364 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\OSC_0\Linker_Design_OSC_0_OSC.v":5:7:5:29|Synthesizing module Linker_Design_OSC_0_OSC

@N: CG364 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.v":713:7:713:14|Synthesizing module SYSRESET

@N: CG364 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\Linker_Design.v":9:7:9:19|Synthesizing module Linker_Design

@W: CL157 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\OSC_0\Linker_Design_OSC_0_OSC.v":16:7:16:24|*Output RCOSC_25_50MHZ_O2F has undriven bits -- simulation mismatch possible.
@W: CL157 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\OSC_0\Linker_Design_OSC_0_OSC.v":17:7:17:20|*Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible.
@W: CL157 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\OSC_0\Linker_Design_OSC_0_OSC.v":18:7:18:20|*Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible.
@W: CL157 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\OSC_0\Linker_Design_OSC_0_OSC.v":19:7:19:16|*Output XTLOSC_CCC has undriven bits -- simulation mismatch possible.
@W: CL157 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\OSC_0\Linker_Design_OSC_0_OSC.v":20:7:20:16|*Output XTLOSC_O2F has undriven bits -- simulation mismatch possible.
@W: CL159 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\OSC_0\Linker_Design_OSC_0_OSC.v":14:7:14:9|Input XTL is unused
@W: CL157 :"E:\Ranjith\Linker_Design\component\work\Linker_Design_MSS\Linker_Design_MSS.v":43:14:43:31|*Output FIC_0_AHB_M_HTRANS has undriven bits -- simulation mismatch possible.
@W: CL246 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v":68:28:68:32|Input port bits 31 to 20 of HADDR[31:0] are unused

@W: CL246 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":61:26:61:34|Input port bits 15 to 11 of writeAddr[15:0] are unused

@W: CL159 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":60:26:60:28|Input ren is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":62:26:62:33|Input readAddr is unused
@N: CL201 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":127:3:127:8|Trying to extract state machine for register sramcurr_state
Extracted state machine for register sramcurr_state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@W: CL246 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":72:29:72:40|Input port bits 19 to 18 of ahbsram_addr[19:0] are unused

@N: CL201 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core\AHBLSramIf.v":185:3:185:8|Trying to extract state machine for register ahbcurr_state
Extracted state machine for register ahbcurr_state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core\AHBLSramIf.v":97:28:97:31|Input BUSY is unused
@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":128:15:128:23|Input port bit 0 of HTRANS_M0[1:0] is unused

@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":139:15:139:23|Input port bit 0 of HTRANS_M1[1:0] is unused

@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":150:15:150:23|Input port bit 0 of HTRANS_M2[1:0] is unused

@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":161:15:161:23|Input port bit 0 of HTRANS_M3[1:0] is unused

@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":171:15:171:22|Input port bit 1 of HRESP_S0[1:0] is unused

@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":184:15:184:22|Input port bit 1 of HRESP_S1[1:0] is unused

@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":197:15:197:22|Input port bit 1 of HRESP_S2[1:0] is unused

@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":210:15:210:22|Input port bit 1 of HRESP_S3[1:0] is unused

@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":223:15:223:22|Input port bit 1 of HRESP_S4[1:0] is unused

@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":236:15:236:22|Input port bit 1 of HRESP_S5[1:0] is unused

@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":249:15:249:22|Input port bit 1 of HRESP_S6[1:0] is unused

@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":262:15:262:22|Input port bit 1 of HRESP_S7[1:0] is unused

@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":275:15:275:22|Input port bit 1 of HRESP_S8[1:0] is unused

@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":288:15:288:22|Input port bit 1 of HRESP_S9[1:0] is unused

@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":301:15:301:23|Input port bit 1 of HRESP_S10[1:0] is unused

@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":314:15:314:23|Input port bit 1 of HRESP_S11[1:0] is unused

@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":327:15:327:23|Input port bit 1 of HRESP_S12[1:0] is unused

@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":340:15:340:23|Input port bit 1 of HRESP_S13[1:0] is unused

@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":353:15:353:23|Input port bit 1 of HRESP_S14[1:0] is unused

@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":366:15:366:23|Input port bit 1 of HRESP_S15[1:0] is unused

@W: CL247 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":379:15:379:23|Input port bit 1 of HRESP_S16[1:0] is unused

@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":131:15:131:23|Input HBURST_M0 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":132:15:132:22|Input HPROT_M0 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":142:15:142:23|Input HBURST_M1 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":143:15:143:22|Input HPROT_M1 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":153:15:153:23|Input HBURST_M2 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":154:15:154:22|Input HPROT_M2 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":164:15:164:23|Input HBURST_M3 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":165:15:165:22|Input HPROT_M3 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":58:18:58:26|Input HWDATA_M1 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":67:18:67:26|Input HWDATA_M2 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":76:18:76:26|Input HWDATA_M3 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":80:18:80:26|Input HRDATA_S0 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":81:13:81:24|Input HREADYOUT_S0 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":82:13:82:20|Input HRESP_S0 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":91:18:91:26|Input HRDATA_S1 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":92:13:92:24|Input HREADYOUT_S1 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":93:13:93:20|Input HRESP_S1 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":102:18:102:26|Input HRDATA_S2 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":103:13:103:24|Input HREADYOUT_S2 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":104:13:104:20|Input HRESP_S2 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":124:18:124:26|Input HRDATA_S4 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":125:13:125:24|Input HREADYOUT_S4 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":126:13:126:20|Input HRESP_S4 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":135:18:135:26|Input HRDATA_S5 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":136:13:136:24|Input HREADYOUT_S5 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":137:13:137:20|Input HRESP_S5 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":146:18:146:26|Input HRDATA_S6 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":147:13:147:24|Input HREADYOUT_S6 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":148:13:148:20|Input HRESP_S6 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":157:18:157:26|Input HRDATA_S7 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":158:13:158:24|Input HREADYOUT_S7 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":159:13:159:20|Input HRESP_S7 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":168:18:168:26|Input HRDATA_S8 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":169:13:169:24|Input HREADYOUT_S8 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":170:13:170:20|Input HRESP_S8 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":179:18:179:26|Input HRDATA_S9 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":180:13:180:24|Input HREADYOUT_S9 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":181:13:181:20|Input HRESP_S9 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":190:18:190:27|Input HRDATA_S10 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":191:13:191:25|Input HREADYOUT_S10 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":192:13:192:21|Input HRESP_S10 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":201:18:201:27|Input HRDATA_S11 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":202:13:202:25|Input HREADYOUT_S11 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":203:13:203:21|Input HRESP_S11 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":212:18:212:27|Input HRDATA_S12 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":213:13:213:25|Input HREADYOUT_S12 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":214:13:214:21|Input HRESP_S12 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":223:18:223:27|Input HRDATA_S13 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":224:13:224:25|Input HREADYOUT_S13 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":225:13:225:21|Input HRESP_S13 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":234:18:234:27|Input HRDATA_S14 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":235:13:235:25|Input HREADYOUT_S14 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":236:13:236:21|Input HRESP_S14 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":245:18:245:27|Input HRDATA_S15 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":246:13:246:25|Input HREADYOUT_S15 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":247:13:247:21|Input HRESP_S15 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":256:18:256:27|Input HRDATA_S16 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":257:13:257:25|Input HREADYOUT_S16 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":258:13:258:21|Input HRESP_S16 is unused
@W: CL246 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":46:15:46:33|Input port bits 3 to 2 of MPREVDATASLAVEREADY[3:0] are unused

@N: CL201 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Trying to extract state machine for register arbRegSMCurrentState
Extracted state machine for register arbRegSMCurrentState
State machine has 16 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
   1011
   1100
   1101
   1110
   1111
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":50:16:50:25|Input SDATAREADY is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":51:16:51:21|Input SHRESP is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":60:16:60:24|Input HRDATA_S0 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":61:11:61:22|Input HREADYOUT_S0 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":62:16:62:24|Input HRDATA_S1 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":63:11:63:22|Input HREADYOUT_S1 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":64:16:64:24|Input HRDATA_S2 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":65:11:65:22|Input HREADYOUT_S2 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":66:16:66:24|Input HRDATA_S3 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":67:11:67:22|Input HREADYOUT_S3 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":68:16:68:24|Input HRDATA_S4 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":69:11:69:22|Input HREADYOUT_S4 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":70:16:70:24|Input HRDATA_S5 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":71:11:71:22|Input HREADYOUT_S5 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":72:16:72:24|Input HRDATA_S6 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":73:11:73:22|Input HREADYOUT_S6 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":74:16:74:24|Input HRDATA_S7 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":75:11:75:22|Input HREADYOUT_S7 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":76:16:76:24|Input HRDATA_S8 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":77:11:77:22|Input HREADYOUT_S8 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":78:16:78:24|Input HRDATA_S9 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":79:11:79:22|Input HREADYOUT_S9 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":80:16:80:25|Input HRDATA_S10 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":81:11:81:23|Input HREADYOUT_S10 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":82:16:82:25|Input HRDATA_S11 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":83:11:83:23|Input HREADYOUT_S11 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":84:16:84:25|Input HRDATA_S12 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":85:11:85:23|Input HREADYOUT_S12 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":86:16:86:25|Input HRDATA_S13 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":87:11:87:23|Input HREADYOUT_S13 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":88:16:88:25|Input HRDATA_S14 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":89:11:89:23|Input HREADYOUT_S14 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":90:16:90:25|Input HRDATA_S15 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":91:11:91:23|Input HREADYOUT_S15 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":92:16:92:25|Input HRDATA_S16 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":93:11:93:23|Input HREADYOUT_S16 is unused
@W: CL246 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":50:16:50:25|Input port bits 16 to 4 of SDATAREADY[16:0] are unused

@W: CL246 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":50:16:50:25|Input port bits 2 to 0 of SDATAREADY[16:0] are unused

@W: CL246 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":51:16:51:21|Input port bits 16 to 4 of SHRESP[16:0] are unused

@W: CL246 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":51:16:51:21|Input port bits 2 to 0 of SHRESP[16:0] are unused

@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":60:16:60:24|Input HRDATA_S0 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":61:11:61:22|Input HREADYOUT_S0 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":62:16:62:24|Input HRDATA_S1 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":63:11:63:22|Input HREADYOUT_S1 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":64:16:64:24|Input HRDATA_S2 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":65:11:65:22|Input HREADYOUT_S2 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":68:16:68:24|Input HRDATA_S4 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":69:11:69:22|Input HREADYOUT_S4 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":70:16:70:24|Input HRDATA_S5 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":71:11:71:22|Input HREADYOUT_S5 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":72:16:72:24|Input HRDATA_S6 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":73:11:73:22|Input HREADYOUT_S6 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":74:16:74:24|Input HRDATA_S7 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":75:11:75:22|Input HREADYOUT_S7 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":76:16:76:24|Input HRDATA_S8 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":77:11:77:22|Input HREADYOUT_S8 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":78:16:78:24|Input HRDATA_S9 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":79:11:79:22|Input HREADYOUT_S9 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":80:16:80:25|Input HRDATA_S10 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":81:11:81:23|Input HREADYOUT_S10 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":82:16:82:25|Input HRDATA_S11 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":83:11:83:23|Input HREADYOUT_S11 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":84:16:84:25|Input HRDATA_S12 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":85:11:85:23|Input HREADYOUT_S12 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":86:16:86:25|Input HRDATA_S13 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":87:11:87:23|Input HREADYOUT_S13 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":88:16:88:25|Input HRDATA_S14 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":89:11:89:23|Input HREADYOUT_S14 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":90:16:90:25|Input HRDATA_S15 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":91:11:91:23|Input HREADYOUT_S15 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":92:16:92:25|Input HRDATA_S16 is unused
@W: CL159 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":93:11:93:23|Input HREADYOUT_S16 is unused
@END

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 85MB peak: 87MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Apr 03 09:36:05 2014

###########################################################]
Pre-mapping Report

Synopsys Generic Technology Pre-mapping, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
Product Version I-2013.09M-SP1 

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@L: E:\Ranjith\Linker_Design\synthesis\Linker_Design_scck.rpt 
Printing clock  summary report in "E:\Ranjith\Linker_Design\synthesis\Linker_Design_scck.rpt" file 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 111MB)

@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3612:27:3612:39|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_16,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_15
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3567:27:3567:39|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_15,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_14
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3522:27:3522:39|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_14,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_13
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3477:27:3477:39|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_13,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_12
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3432:27:3432:39|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_12,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_11
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3387:27:3387:39|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_11,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3297:26:3297:37|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_9,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3252:27:3252:38|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_8,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3207:27:3207:38|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_7,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3162:27:3162:38|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_6,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3117:27:3117:38|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_5,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3072:27:3072:38|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_4,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2982:27:2982:38|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_2,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3342:27:3342:39|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_10,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_1
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2937:27:2937:38|Removing user instance CoreAHBLite_0.matrix4x16.slavestage_1,  because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_0
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN115 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2708:2:2708:14|Removing instance masterstage_1 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN115 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2771:2:2771:14|Removing instance masterstage_2 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN115 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2834:2:2834:14|Removing instance masterstage_3 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN115 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2892:27:2892:38|Removing instance slavestage_0 of view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_slavestage_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2708:12:2708:18|Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2728:12:2728:18|Removing sequential instance block15 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2748:12:2748:18|Removing sequential instance block14 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2768:12:2768:18|Removing sequential instance block13 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2788:12:2788:18|Removing sequential instance block12 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2808:12:2808:18|Removing sequential instance block11 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2828:12:2828:18|Removing sequential instance block10 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2848:12:2848:17|Removing sequential instance block9 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2868:12:2868:17|Removing sequential instance block8 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2888:12:2888:17|Removing sequential instance block7 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2908:10:2908:15|Removing sequential instance block6 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2928:12:2928:17|Removing sequential instance block5 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2948:12:2948:17|Removing sequential instance block4 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2968:12:2968:17|Removing sequential instance block3 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2988:12:2988:17|Removing sequential instance block2 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":3028:12:3028:17|Removing sequential instance block0 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2708:12:2708:18|Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2728:12:2728:18|Removing sequential instance block15 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2748:12:2748:18|Removing sequential instance block14 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2768:12:2768:18|Removing sequential instance block13 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2788:12:2788:18|Removing sequential instance block12 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2808:12:2808:18|Removing sequential instance block11 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2828:12:2828:18|Removing sequential instance block10 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2848:12:2848:17|Removing sequential instance block9 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2868:12:2868:17|Removing sequential instance block8 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2888:12:2888:17|Removing sequential instance block7 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2908:10:2908:15|Removing sequential instance block6 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2928:12:2928:17|Removing sequential instance block5 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2948:12:2948:17|Removing sequential instance block4 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2968:12:2968:17|Removing sequential instance block3 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2988:12:2988:17|Removing sequential instance block2 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":3028:12:3028:17|Removing sequential instance block0 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2708:12:2708:18|Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2728:12:2728:18|Removing sequential instance block15 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2748:12:2748:18|Removing sequential instance block14 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2768:12:2768:18|Removing sequential instance block13 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2788:12:2788:18|Removing sequential instance block12 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2808:12:2808:18|Removing sequential instance block11 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2828:12:2828:18|Removing sequential instance block10 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2848:12:2848:17|Removing sequential instance block9 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2868:12:2868:17|Removing sequential instance block8 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2888:12:2888:17|Removing sequential instance block7 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2908:10:2908:15|Removing sequential instance block6 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2928:12:2928:17|Removing sequential instance block5 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2948:12:2948:17|Removing sequential instance block4 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2968:12:2968:17|Removing sequential instance block3 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2988:12:2988:17|Removing sequential instance block2 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":3028:12:3028:17|Removing sequential instance block0 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2708:12:2708:18|Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2728:12:2728:18|Removing sequential instance block15 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2748:12:2748:18|Removing sequential instance block14 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2768:12:2768:18|Removing sequential instance block13 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2788:12:2788:18|Removing sequential instance block12 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2808:12:2808:18|Removing sequential instance block11 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2828:12:2828:18|Removing sequential instance block10 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2848:12:2848:17|Removing sequential instance block9 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2868:12:2868:17|Removing sequential instance block8 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2888:12:2888:17|Removing sequential instance block7 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2908:10:2908:15|Removing sequential instance block6 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2928:12:2928:17|Removing sequential instance block5 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2948:12:2948:17|Removing sequential instance block4 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2968:12:2968:17|Removing sequential instance block3 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":2988:12:2988:17|Removing sequential instance block2 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":3028:12:3028:17|Removing sequential instance block0 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_2048s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_slavestage_0(verilog) because there are no references to its outputs 
@N: BN115 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":90:29:90:41|Removing instance slave_arbiter of view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing sequential instance arbRegSMCurrentState[15:0] of view:PrimLib.statemachine(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter(verilog) because there are no references to its outputs 
syn_allowed_resources : blockrams=69  set on top level netlist Linker_Design


Clock Summary
**************

Start                                                Requested     Requested     Clock        Clock              
Clock                                                Frequency     Period        Type         Group              
-----------------------------------------------------------------------------------------------------------------
Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_0
System                                               1.0 MHz       1000.000      system       system_clkgroup    
=================================================================================================================

@W: MT530 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v":66:4:66:9|Found inferred clock Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock which controls 147 sequential elements including CoreAHBLite_0.matrix4x16.masterstage_0.default_slave_sm.defSlaveSMCurrentState. This clock has no specified timing constraint which may adversely impact design performance. 

Finished Pre Mapping Phase.
@W: MO111 :|Tristate driver Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS_t[0] on net Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS[0] has its enable tied to GND (module Linker_Design) 
@N: BN225 |Writing default property annotation file E:\Ranjith\Linker_Design\synthesis\Linker_Design.sap.
Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 140MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Apr 03 09:36:07 2014

###########################################################]
Map & Optimize Report

Synopsys Generic Technology Mapper, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
Product Version I-2013.09M-SP1 

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 138MB)

@W: MO111 :"e:\ranjith\linker_design\component\work\linker_design_mss\linker_design_mss.v":43:14:43:31|Tristate driver FIC_0_AHB_M_HTRANS_1 on net FIC_0_AHB_M_HTRANS_1 has its enable tied to GND (module Linker_Design_MSS) 
@W: MO111 :"e:\ranjith\linker_design\component\work\linker_design\osc_0\linker_design_osc_0_osc.v":20:7:20:16|Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module Linker_Design_OSC_0_OSC) 
@W: MO111 :"e:\ranjith\linker_design\component\work\linker_design\osc_0\linker_design_osc_0_osc.v":19:7:19:16|Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module Linker_Design_OSC_0_OSC) 
@W: MO111 :"e:\ranjith\linker_design\component\work\linker_design\osc_0\linker_design_osc_0_osc.v":18:7:18:20|Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module Linker_Design_OSC_0_OSC) 
@W: MO111 :"e:\ranjith\linker_design\component\work\linker_design\osc_0\linker_design_osc_0_osc.v":17:7:17:20|Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module Linker_Design_OSC_0_OSC) 
@W: MO111 :"e:\ranjith\linker_design\component\work\linker_design\osc_0\linker_design_osc_0_osc.v":16:7:16:24|Tristate driver RCOSC_25_50MHZ_O2F on net RCOSC_25_50MHZ_O2F has its enable tied to GND (module Linker_Design_OSC_0_OSC) 
@W: MO111 :|Tristate driver Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS_t[0] on net Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS[0] has its enable tied to GND (module Linker_Design) 

Available hyper_sources - for debug and ip models
	None Found


Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 138MB)

@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[20] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[21] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[22] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[23] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[24] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[25] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[26] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[27] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_3.masterDataInProg[3] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_3.masterDataInProg[2] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_3.masterDataInProg[1] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":233:0:233:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[16] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[31],  because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[30]
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[29],  because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28]
Encoding state machine arbRegSMCurrentState[15:0] (view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter_0(verilog))
original code -> new code
   0000 -> 0000000000000001
   0001 -> 0000000000000010
   0010 -> 0000000000000100
   0011 -> 0000000000001000
   0100 -> 0000000000010000
   0101 -> 0000000000100000
   0110 -> 0000000001000000
   0111 -> 0000000010000000
   1000 -> 0000000100000000
   1001 -> 0000001000000000
   1010 -> 0000010000000000
   1011 -> 0000100000000000
   1100 -> 0001000000000000
   1101 -> 0010000000000000
   1110 -> 0100000000000000
   1111 -> 1000000000000000
@W: MO160 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Register bit arbRegSMCurrentState[12] is always 0, optimizing ...
@W: MO160 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Register bit arbRegSMCurrentState[8] is always 0, optimizing ...
@W: MO160 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Register bit arbRegSMCurrentState[4] is always 0, optimizing ...
Encoding state machine ahbcurr_state[2:0] (view:COREAHBLSRAM_LIB.AHBLSramIf(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblsram\2.0.113\rtl\vlog\core\ahblsramif.v":161:3:161:8|Removing sequential instance HADDR_d[13] in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblsram\2.0.113\rtl\vlog\core\ahblsramif.v":161:3:161:8|Removing sequential instance HADDR_d[14] in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblsram\2.0.113\rtl\vlog\core\ahblsramif.v":161:3:161:8|Removing sequential instance HADDR_d[15] in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblsram\2.0.113\rtl\vlog\core\ahblsramif.v":161:3:161:8|Removing sequential instance HADDR_d[16] in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblsram\2.0.113\rtl\vlog\core\ahblsramif.v":161:3:161:8|Removing sequential instance HADDR_d[17] in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblsram\2.0.113\rtl\vlog\core\ahblsramif.v":161:3:161:8|Removing sequential instance HADDR_d[18] in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblsram\2.0.113\rtl\vlog\core\ahblsramif.v":161:3:161:8|Removing sequential instance HADDR_d[19] in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs 
Encoding state machine sramcurr_state[2:0] (view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_SramCtrlIf_0s_2048s_512s_32s_0_1_2(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28],  because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_0.regHTRANS
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblsram\2.0.113\rtl\vlog\core\ahblsramif.v":161:3:161:8|Removing sequential instance COREAHBLSRAM_0.U_AHBLSramIf.HSIZE_d[2] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[30] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[18] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[19] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[13] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[14] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[15] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[16] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[17] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs 

Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 139MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 139MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 139MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 139MB)


Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 139MB)


Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		    -0.52ns		 205 /       105
------------------------------------------------------------




Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -0.34ns		 214 /       105
------------------------------------------------------------



Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -0.34ns		 214 /       105
------------------------------------------------------------

@N: FP130 |Promoting Net Linker_Design_MSS_0_MSS_RESET_N_M2F on CLKINT  I_138 

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 138MB peak: 145MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 138MB peak: 145MB)



#### START OF CLOCK OPTIMIZATION REPORT #####[

Clock optimization not enabled
1 non-gated/non-generated clock tree(s) driving 114 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

===================================== Non-Gated/Non-Generated Clocks =====================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                   
----------------------------------------------------------------------------------------------------------
@K:CKID0001       FCCC_0.GL0_INST     CLKINT                 114        Linker_Design_MSS_0.MSS_ADLIB_INST
==========================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]

Writing Analyst data base E:\Ranjith\Linker_Design\synthesis\Linker_Design.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 136MB peak: 145MB)

Writing EDIF Netlist and constraint files
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
I-2013.09M-SP1 

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 137MB peak: 145MB)

@W: MT246 :"e:\ranjith\linker_design\component\work\linker_design\linker_design.v":634:9:634:18|Blackbox SYSRESET is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"e:\ranjith\linker_design\component\work\linker_design\fccc_0\linker_design_fccc_0_fccc.v":20:36:20:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:FCCC_0.GL0_net"



##### START OF TIMING REPORT #####[
# Timing Report written on Thu Apr 03 09:36:10 2014
#


Top view:               Linker_Design
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: 0.391

                                                     Requested     Estimated     Requested     Estimated               Clock        Clock              
Starting Clock                                       Frequency     Frequency     Period        Period        Slack     Type         Group              
-------------------------------------------------------------------------------------------------------------------------------------------------------
Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     119.9 MHz     10.000        8.341         1.659     inferred     Inferred_clkgroup_0
System                                               100.0 MHz     895.2 MHz     10.000        1.117         8.883     system       system_clkgroup    
=======================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                                              |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                          Ending                                            |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                            System                                            |  10.000      8.883  |  No paths    -      |  No paths    -      |  No paths    -    
System                                            Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock  |  10.000      8.628  |  No paths    -      |  No paths    -      |  No paths    -    
Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock  System                                            |  10.000      0.391  |  No paths    -      |  No paths    -      |  No paths    -    
Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock  Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock  |  10.000      1.659  |  No paths    -      |  No paths    -      |  No paths    -    
==========================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                                                 Starting                                                                                                                               Arrival          
Instance                                                                         Reference                                            Type        Pin                Net                                                Time        Slack
                                                                                 Clock                                                                                                                                                   
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Linker_Design_MSS_0.MSS_ADLIB_INST                                               Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     MSS_050     F_HM0_SIZE[1]      Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE[1]      3.163       0.391
Linker_Design_MSS_0.MSS_ADLIB_INST                                               Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     MSS_050     F_HM0_SIZE[0]      Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE[0]      3.139       0.690
Linker_Design_MSS_0.MSS_ADLIB_INST                                               Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     MSS_050     F_HM0_ADDR[30]     Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[30]     2.999       0.917
Linker_Design_MSS_0.MSS_ADLIB_INST                                               Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     MSS_050     F_HM0_ADDR[31]     Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[31]     3.049       1.056
Linker_Design_MSS_0.MSS_ADLIB_INST                                               Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     MSS_050     F_HM0_TRANS1       Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS[1]     3.106       1.088
Linker_Design_MSS_0.MSS_ADLIB_INST                                               Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     MSS_050     F_HM0_ADDR[28]     Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[28]     2.980       1.182
Linker_Design_MSS_0.MSS_ADLIB_INST                                               Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     MSS_050     F_HM0_ADDR[29]     Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[29]     3.021       1.395
CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[13]     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  arbRegSMCurrentState[13]                           0.108       1.970
CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[1]      Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  arbRegSMCurrentState[1]                            0.108       2.240
CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[5]      Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  arbRegSMCurrentState[5]                            0.108       2.259
=========================================================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                       Starting                                                                                              Required          
Instance                                               Reference                                            Type        Pin          Net                     Time         Slack
                                                       Clock                                                                                                                   
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_3.block1     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     RAM1K18     A_WEN[0]     sram_wen_mem[3]         10.000       0.391
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block1     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     RAM1K18     A_WEN[0]     sram_wen_mem[2]         10.000       0.391
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_3.block1     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     RAM1K18     A_WEN[0]     sram_wen_mem[3]         10.000       0.391
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block1     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     RAM1K18     A_WEN[0]     sram_wen_mem[2]         10.000       0.391
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.block1     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     RAM1K18     A_WEN[0]     sram_wen_mem[1]         10.000       1.133
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.block1     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     RAM1K18     A_WEN[0]     sram_wen_mem[1]         10.000       1.133
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.block1     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     RAM1K18     A_WEN[0]     sram_wen_mem[0]         10.000       1.160
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.block1     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     RAM1K18     A_WEN[0]     sram_wen_mem[0]         10.000       1.160
COREAHBLSRAM_0.U_AHBLSramIf.ahbcurr_state[0]           Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE         D            ahbcurr_state_ns[0]     9.825        1.659
COREAHBLSRAM_0.U_AHBLSramIf.ahbcurr_state[1]           Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE         D            ahbcurr_state_ns[1]     9.825        1.659
===============================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         10.000

    - Propagation time:                      9.609
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     0.391

    Number of logic level(s):                5
    Starting point:                          Linker_Design_MSS_0.MSS_ADLIB_INST / F_HM0_SIZE[1]
    Ending point:                            COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_3.block1 / A_WEN[0]
    The start point is clocked by            Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
    The end   point is clocked by            System [rising]

Instance / Net                                                         Pin               Pin               Arrival     No. of    
Name                                                       Type        Name              Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------
Linker_Design_MSS_0.MSS_ADLIB_INST                         MSS_050     F_HM0_SIZE[1]     Out     3.163     3.163       -         
Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE[1]              Net         -                 -       1.126     -           3         
CoreAHBLite_0.matrix4x16.masterstage_0.GATEDHSIZE[1]       CFG3        B                 In      -         4.289       -         
CoreAHBLite_0.matrix4x16.masterstage_0.GATEDHSIZE[1]       CFG3        Y                 Out     0.164     4.454       -         
M0GATEDHSIZE[1]                                            Net         -                 -       0.678     -           3         
COREAHBLSRAM_0.U_AHBLSramIf.ahbsram_size_0_sx[1]           CFG4        D                 In      -         5.132       -         
COREAHBLSRAM_0.U_AHBLSramIf.ahbsram_size_0_sx[1]           CFG4        Y                 Out     0.470     5.602       -         
ahbsram_size_0_sx[1]                                       Net         -                 -       0.556     -           1         
COREAHBLSRAM_0.U_AHBLSramIf.ahbsram_size_0[1]              CFG4        D                 In      -         6.157       -         
COREAHBLSRAM_0.U_AHBLSramIf.ahbsram_size_0[1]              CFG4        Y                 Out     0.470     6.627       -         
ahbsram_size[1]                                            Net         -                 -       0.556     -           1         
COREAHBLSRAM_0.U_SramCtrlIf.g0_i_m2                        CFG4        D                 In      -         7.183       -         
COREAHBLSRAM_0.U_SramCtrlIf.g0_i_m2                        CFG4        Y                 Out     0.470     7.652       -         
g0_1                                                       Net         -                 -       0.630     -           2         
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_3.block1_RNO     CFG4        C                 In      -         8.282       -         
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_3.block1_RNO     CFG4        Y                 Out     0.210     8.492       -         
sram_wen_mem[3]                                            Net         -                 -       1.117     -           1         
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_3.block1         RAM1K18     A_WEN[0]          In      -         9.609       -         
=================================================================================================================================
Total path delay (propagation time + setup) of 9.609 is 4.946(51.5%) logic and 4.663(48.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                       Starting                                                  Arrival          
Instance                                               Reference     Type        Pin           Net               Time        Slack
                                                       Clock                                                                      
----------------------------------------------------------------------------------------------------------------------------------
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.block1     System        RAM1K18     A_DOUT[0]     ram_rdata[8]      0.000       8.628
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_3.block1     System        RAM1K18     A_DOUT[0]     ram_rdata[24]     0.000       8.628
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block1     System        RAM1K18     A_DOUT[0]     ram_rdata[16]     0.000       8.628
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_3.block1     System        RAM1K18     A_DOUT[0]     ram_rdata[24]     0.000       8.628
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.block1     System        RAM1K18     A_DOUT[0]     ram_rdata[0]      0.000       8.628
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.block1     System        RAM1K18     A_DOUT[0]     ram_rdata[0]      0.000       8.628
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.block1     System        RAM1K18     A_DOUT[0]     ram_rdata[8]      0.000       8.628
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block1     System        RAM1K18     A_DOUT[0]     ram_rdata[16]     0.000       8.628
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block1     System        RAM1K18     A_DOUT[1]     ram_rdata[17]     0.000       8.628
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.block1     System        RAM1K18     A_DOUT[1]     ram_rdata[1]      0.000       8.628
==================================================================================================================================


Ending Points with Worst Slack
******************************

                                                 Starting                                        Required          
Instance                                         Reference     Type     Pin     Net              Time         Slack
                                                 Clock                                                             
-------------------------------------------------------------------------------------------------------------------
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[0]     System        SLE      D       ram_rdata[0]     9.745        8.628
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[1]     System        SLE      D       ram_rdata[1]     9.745        8.628
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[2]     System        SLE      D       ram_rdata[2]     9.745        8.628
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[3]     System        SLE      D       ram_rdata[3]     9.745        8.628
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[4]     System        SLE      D       ram_rdata[4]     9.745        8.628
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[5]     System        SLE      D       ram_rdata[5]     9.745        8.628
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[6]     System        SLE      D       ram_rdata[6]     9.745        8.628
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[7]     System        SLE      D       ram_rdata[7]     9.745        8.628
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[8]     System        SLE      D       ram_rdata[8]     9.745        8.628
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[9]     System        SLE      D       ram_rdata[9]     9.745        8.628
===================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.255
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.745

    - Propagation time:                      1.117
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 8.628

    Number of logic level(s):                0
    Starting point:                          COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.block1 / A_DOUT[0]
    Ending point:                            COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[8] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK

Instance / Net                                                     Pin           Pin               Arrival     No. of    
Name                                                   Type        Name          Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.block1     RAM1K18     A_DOUT[0]     Out     0.000     0.000       -         
ram_rdata[8]                                           Net         -             -       1.117     -           1         
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[8]           SLE         D             In      -         1.117       -         
=========================================================================================================================
Total path delay (propagation time + setup) of 1.372 is 0.255(18.6%) logic and 1.117(81.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report for Linker_Design 

Mapping to part: m2s050tfbga896std
Cell usage:
CCC             1 use
CLKINT          2 uses
MSS_050         1 use
RCOSC_25_50MHZ  1 use
SYSRESET        1 use
CFG1           2 uses
CFG2           82 uses
CFG3           43 uses
CFG4           85 uses


Sequential Cells: 
SLE            105 uses

DSP Blocks:    0

I/O ports: 3
I/O primitives: 2
INBUF          1 use
TRIBUFF        1 use


Global Clock Buffers: 2


RAM/ROM usage summary
Block Rams (RAM1K18) : 4

Total LUTs:    212

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 50MB peak: 145MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Thu Apr 03 09:36:10 2014

###########################################################]
