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COREAHBLITE_LIB
COREAHBLSRAM_LIB
ENDLIST
LIST LIBRARY_COREAHBLITE_LIB
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ENDLIST
LIST LIBRARY_COREAHBLSRAM_LIB
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ENDLIST
LIST FileManager
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ENDLIST
LIST NewModulesInfo
LIST "Linker_Design::work"
FILE "<project>\component\work\Linker_Design\Linker_Design.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\subsystem.bfm,sim"
VALUE "<project>\component\work\Linker_Design\testbench.v,tb_hdl"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\work\Linker_Design\testbench.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
LiberoState=Post_Synthesis
ideSTIMULUS=StateSuccess
ideSYNTHESIS(<project>\synthesis\Linker_Design.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST PinReports
VALUE "<project>\designer\Linker_Design\Linker_Design_pinrpt_name.rpt,log"
VALUE "<project>\designer\Linker_Design\Linker_Design_pinrpt_number.rpt,log"
ENDLIST
ENDLIST
LIST "Linker_Design_MSS::work"
FILE "<project>\component\work\Linker_Design_MSS\Linker_Design_MSS.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\user.bfm,sim"
VALUE "<project>\simulation\test.bfm,sim"
VALUE "<project>\component\work\Linker_Design_MSS\testbench.v,tb_hdl"
VALUE "<project>\simulation\peripheral_init.bfm,sim"
VALUE "<project>\simulation\CompileDssBfm.tcl,sim"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\work\Linker_Design_MSS\testbench.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "CoreAHBLite::COREAHBLITE_LIB"
FILE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
VALUE "<project>\simulation\coreahblite_usertb_include.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master0.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master1.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master2.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master3.bfm,sim"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\mti\scripts\wave_user.do,do"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\test\user\testbench.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM::COREAHBLSRAM_LIB"
FILE "<project>\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v,hdl"
LIST Other_Association
VALUE "<project>\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\coreparameters.v,tb_hdl"
VALUE "<project>\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\test\user\tb.v,tb_hdl"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\coreparameters.v,tb_hdl"
VALUE "<project>\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\test\user\tb.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
LIST Linker_Design
VALUE "<project>\component\work\Linker_Design\testbench.v,tb_hdl"
ENDLIST
LIST Linker_Design_MSS
VALUE "<project>\component\work\Linker_Design_MSS\testbench.v,tb_hdl"
ENDLIST
LIST CoreAHBLite
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\test\user\testbench.v,tb_hdl"
ENDLIST
LIST Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM
VALUE "<project>\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\coreparameters.v,tb_hdl"
VALUE "<project>\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\test\user\tb.v,tb_hdl"
ENDLIST
ENDLIST
LIST Other_Association
LIST Linker_Design
VALUE "<project>\simulation\subsystem.bfm,sim"
VALUE "<project>\component\work\Linker_Design\testbench.v,tb_hdl"
ENDLIST
LIST Linker_Design_MSS
VALUE "<project>\simulation\user.bfm,sim"
VALUE "<project>\simulation\test.bfm,sim"
VALUE "<project>\component\work\Linker_Design_MSS\testbench.v,tb_hdl"
VALUE "<project>\simulation\peripheral_init.bfm,sim"
VALUE "<project>\simulation\CompileDssBfm.tcl,sim"
ENDLIST
LIST CoreAHBLite
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
VALUE "<project>\simulation\coreahblite_usertb_include.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master0.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master1.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master2.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master3.bfm,sim"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.0.100\mti\scripts\wave_user.do,do"
ENDLIST
LIST Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM
VALUE "<project>\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\coreparameters.v,tb_hdl"
VALUE "<project>\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\test\user\tb.v,tb_hdl"
ENDLIST
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1fs
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DisablePulseFiltering=false
DumpVCD=false
VCDFileName=power.vcd
VHDL2008=false
Verilog2001=false
SystemVerilog=false
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
AutoCheckConstraints=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
EnableViewDraw=FALSE
UpdateViewDrawIni=TRUE
GenerateHDLFromSchematic=TRUE
VmNetlistFlowOn=FALSE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
NAME="SoftConsole"
FUNCTION="SoftwareIDE"
TOOL="SoftConsole"
LOCATION="C:\Microsemi\Libero_v11.2\SoftConsole\Eclipse\eclipse.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="Synplify Pro ME"
FUNCTION="Synthesis"
TOOL="Synplify Pro ME"
LOCATION="C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\bin\synplify_pro.exe"
PARAM="-licensetype synplifypro_actel -batch -log synplify.log"
BATCH=1
LICENSE=""
IS32BIT="1"
EndProfile
NAME="ModelSim ME"
FUNCTION="Simulation"
TOOL="ModelSim"
LOCATION="C:\Microsemi\Libero_v11.3\Model\win32acoem\modelsim.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="FlashPro"
FUNCTION="Program"
TOOL="FlashPro"
LOCATION="C:\Microsemi\Libero_v11.3\Designer\bin\FlashPro.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "Linker_Design::work"
LIST Impl1
LiberoState=Post_Synthesis
ideSTIMULUS=StateSuccess
ideSYNTHESIS(<project>\synthesis\Linker_Design.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "Linker_Design_MSS::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "CoreAHBLite::COREAHBLITE_LIB"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM::COREAHBLSRAM_LIB"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
ORIENTATION;HORIZONTAL
Reports;Reports;0
ReportsCurrentItem;Export Programming File:Linker_Design_export.log
StartPage;StartPage;0
SmartDesign;Linker_Design;0
SmartDesign;Linker_Design_MSS;0
ACTIVEVIEW;Reports
ENDLIST
LIST ModuleSubBlockList
LIST "DESIGN_FIRMWARE::work","component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf","TRUE","FALSE"
SUBBLOCK "SmartFusion2_CMSIS::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion2_MSS_HPDMA_Driver::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion2_MSS_MMUART_Driver::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion2_MSS_NVM_Driver::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion2_MSS_System_Services_Driver::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion2_MSS_Timer_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "Linker_Design::work","component\work\Linker_Design\Linker_Design.v","TRUE","FALSE"
SUBBLOCK "Linker_Design_FCCC_0_FCCC::work","component\work\Linker_Design\FCCC_0\Linker_Design_FCCC_0_FCCC.v","FALSE","FALSE"
SUBBLOCK "Linker_Design_MSS::work","component\work\Linker_Design_MSS\Linker_Design_MSS.v","TRUE","FALSE"
SUBBLOCK "Linker_Design_OSC_0_OSC::work","component\work\Linker_Design\OSC_0\Linker_Design_OSC_0_OSC.v","FALSE","FALSE"
SUBBLOCK "CoreAHBLite::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v","FALSE","FALSE"
SUBBLOCK "Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM::COREAHBLSRAM_LIB","component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v","FALSE","FALSE"
ENDLIST
LIST "Linker_Design_FCCC_0_FCCC::work","component\work\Linker_Design\FCCC_0\Linker_Design_FCCC_0_FCCC.v","FALSE","FALSE"
ENDLIST
LIST "Linker_Design_MSS::work","component\work\Linker_Design_MSS\Linker_Design_MSS.v","TRUE","FALSE"
SUBBLOCK "MSS_050::work","component\work\Linker_Design_MSS\Linker_Design_MSS_syn.v","FALSE","FALSE"
ENDLIST
LIST "Linker_Design_OSC_0_OSC::work","component\work\Linker_Design\OSC_0\Linker_Design_OSC_0_OSC.v","FALSE","FALSE"
SUBBLOCK "RCOSC_25_50MHZ::work","component\Actel\SgCore\OSC\1.0.100\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "MSS_050::work","component\work\Linker_Design_MSS\Linker_Design_MSS_syn.v","FALSE","FALSE"
ENDLIST
LIST "RCOSC_1MHZ::work","component\Actel\SgCore\OSC\1.0.100\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "RCOSC_1MHZ_FAB::work","component\Actel\SgCore\OSC\1.0.100\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "RCOSC_25_50MHZ::work","component\Actel\SgCore\OSC\1.0.100\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "RCOSC_25_50MHZ_FAB::work","component\Actel\SgCore\OSC\1.0.100\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_CMSIS::work","","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_MSS_HPDMA_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_MSS_MMUART_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_MSS_NVM_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_MSS_System_Services_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_MSS_Timer_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "XTLOSC::work","component\Actel\SgCore\OSC\1.0.100\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "XTLOSC_FAB::work","component\Actel\SgCore\OSC\1.0.100\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM::work","","FALSE","FALSE"
ENDLIST
LIST "testbench::work","component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\test\user\tb.v","FALSE","TRUE"
SUBBLOCK "Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM::work","","FALSE","FALSE"
ENDLIST
LIST "testbench::work","component\work\Linker_Design\testbench.v","FALSE","TRUE"
SUBBLOCK "Linker_Design::work","component\work\Linker_Design\Linker_Design.v","TRUE","FALSE"
ENDLIST
LIST "testbench::work","component\work\Linker_Design_MSS\testbench.v","FALSE","TRUE"
SUBBLOCK "Linker_Design_MSS::work","component\work\Linker_Design_MSS\Linker_Design_MSS.v","TRUE","FALSE"
ENDLIST
LIST "CoreAHBLite::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_MATRIX4X16::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v","FALSE","FALSE"
ENDLIST
LIST "COREAHBLITE_ADDRDEC::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v","FALSE","FALSE"
ENDLIST
LIST "COREAHBLITE_DEFAULTSLAVESM::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v","FALSE","FALSE"
ENDLIST
LIST "COREAHBLITE_MASTERSTAGE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_ADDRDEC::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_DEFAULTSLAVESM::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v","FALSE","FALSE"
ENDLIST
LIST "COREAHBLITE_MATRIX4X16::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_MASTERSTAGE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_SLAVESTAGE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v","FALSE","FALSE"
ENDLIST
LIST "COREAHBLITE_SLAVEARBITER::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v","FALSE","FALSE"
ENDLIST
LIST "COREAHBLITE_SLAVESTAGE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_SLAVEARBITER::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v","FALSE","FALSE"
ENDLIST
LIST "BFM_AHBL::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_ahbl.v","FALSE","TRUE"
SUBBLOCK "BFM_MAIN::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_main.v","FALSE","TRUE"
ENDLIST
LIST "BFM_AHBSLAVE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_ahbslave.v","FALSE","TRUE"
SUBBLOCK "BFM_AHBSLAVEEXT::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_ahbslaveext.v","FALSE","TRUE"
ENDLIST
LIST "BFM_AHBSLAVEEXT::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_ahbslaveext.v","FALSE","TRUE"
ENDLIST
LIST "BFM_MAIN::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_main.v","FALSE","TRUE"
ENDLIST
LIST "testbench::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\test\user\testbench.v","FALSE","TRUE"
SUBBLOCK "CoreAHBLite::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v","FALSE","FALSE"
SUBBLOCK "BFM_AHBL::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_ahbl.v","FALSE","TRUE"
SUBBLOCK "BFM_AHBSLAVE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\amba_bfm\bfm_ahbslave.v","FALSE","TRUE"
ENDLIST
LIST "AHBLSramIf::COREAHBLSRAM_LIB","component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core\AHBLSramIf.v","FALSE","FALSE"
ENDLIST
LIST "Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM::COREAHBLSRAM_LIB","component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v","FALSE","FALSE"
SUBBLOCK "AHBLSramIf::COREAHBLSRAM_LIB","component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core\AHBLSramIf.v","FALSE","FALSE"
SUBBLOCK "Linker_Design_COREAHBLSRAM_0_SramCtrlIf::COREAHBLSRAM_LIB","component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v","FALSE","FALSE"
ENDLIST
LIST "Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8::COREAHBLSRAM_LIB","component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v","FALSE","FALSE"
ENDLIST
LIST "Linker_Design_COREAHBLSRAM_0_SramCtrlIf::COREAHBLSRAM_LIB","component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v","FALSE","FALSE"
SUBBLOCK "Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8::COREAHBLSRAM_LIB","component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v","FALSE","FALSE"
SUBBLOCK "Linker_Design_COREAHBLSRAM_0_usram_128to9216x8::COREAHBLSRAM_LIB","component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\usram_128to9216x8.v","FALSE","FALSE"
ENDLIST
LIST "Linker_Design_COREAHBLSRAM_0_usram_128to9216x8::COREAHBLSRAM_LIB","component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\usram_128to9216x8.v","FALSE","FALSE"
ENDLIST
ENDLIST
LIST ActiveTestBenchList
LIST "Linker_Design::work"
ACTIVETESTBENCH "","","FALSE"
ENDLIST
ENDLIST
