C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\bin64\m_generic.exe  -prodtype  synplify_pro  -encrypt  -pro  -rundir  E:\Ranjith\Linker_Design\synthesis\synthesis_1  -part M2S050T  -package FBGA896  -grade STD   -overilog "Linker_Design.vm" -maxfan 10000 -clock_globalthreshold 2 -async_globalthreshold 12 -globalthreshold 5000   -opcond COMWC  -report_path 0  -RWCheckOnRam 0    -summaryfile E:\Ranjith\Linker_Design\synthesis\synthesis_1\synlog\report\Linker_Design_fpga_mapper.xml -top_level_module  Linker_Design  -flow mapping  -mp 1 -prjfile  E:\Ranjith\Linker_Design\synthesis\synthesis_1\scratchproject.prs  -implementation synthesis_1 -licensetype  synplifypro  -oedif  E:\Ranjith\Linker_Design\synthesis\synthesis_1\Linker_Design.edf  -freq 100.000  E:\Ranjith\Linker_Design\synthesis\synthesis_1\synwork\Linker_Design_prem.srd  -tcl  E:\Ranjith\Linker_Design\synthesis\synthesis_1\Linker_Design_fsm.sdc  -sap  E:\Ranjith\Linker_Design\synthesis\synthesis_1\Linker_Design.sap  -otap  E:\Ranjith\Linker_Design\synthesis\synthesis_1\Linker_Design.tap  -omap  E:\Ranjith\Linker_Design\synthesis\synthesis_1\Linker_Design.map  -devicelib  C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.v  -sap  E:\Ranjith\Linker_Design\synthesis\synthesis_1\Linker_Design.sap  -ologparam  E:\Ranjith\Linker_Design\synthesis\synthesis_1\syntmp\Linker_Design.plg  -osyn  E:\Ranjith\Linker_Design\synthesis\synthesis_1\Linker_Design.srm  -prjdir  E:\Ranjith\Linker_Design\synthesis\  -prjname  Linker_Design_syn  -log  E:\Ranjith\Linker_Design\synthesis\synthesis_1\synlog\Linker_Design_fpga_mapper.srr 
rc:1 success:1
E:\Ranjith\Linker_Design\synthesis\synthesis_1\scratchproject.prs|o|1396521846|3882
E:\Ranjith\Linker_Design\synthesis\synthesis_1\Linker_Design.edf|o|0|0
E:\Ranjith\Linker_Design\synthesis\synthesis_1\synwork\Linker_Design_prem.srd|i|1396521851|222784
E:\Ranjith\Linker_Design\synthesis\synthesis_1\Linker_Design_fsm.sdc|i|1396521850|0
E:\Ranjith\Linker_Design\synthesis\synthesis_1\Linker_Design.sap|o|1396521851|25962
E:\Ranjith\Linker_Design\synthesis\synthesis_1\Linker_Design.tap|o|0|0
E:\Ranjith\Linker_Design\synthesis\synthesis_1\Linker_Design.map|o|1396521855|28
C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.v|i|1389673372|16267
E:\Ranjith\Linker_Design\synthesis\synthesis_1\Linker_Design.sap|o|1396521851|25962
E:\Ranjith\Linker_Design\synthesis\synthesis_1\syntmp\Linker_Design.plg|o|1396521855|1674
E:\Ranjith\Linker_Design\synthesis\synthesis_1\Linker_Design.srm|o|1396521854|178196
E:\Ranjith\Linker_Design\synthesis\synthesis_1\synlog\Linker_Design_fpga_mapper.srr|o|1396521855|43067
C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\bin64\m_generic.exe|i|1390193752|31452672
C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\bin\m_generic.exe|i|1390191066|21921280
