@W: MO111 :"e:\ranjith\linker_design\component\work\linker_design_mss\linker_design_mss.v":42:14:42:31|Tristate driver FIC_0_AHB_M_HTRANS_1 on net FIC_0_AHB_M_HTRANS_1 has its enable tied to GND (module Linker_Design_MSS) 
@W: MO111 :"e:\ranjith\linker_design\component\work\linker_design\osc_0\linker_design_osc_0_osc.v":20:7:20:16|Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module Linker_Design_OSC_0_OSC) 
@W: MO111 :"e:\ranjith\linker_design\component\work\linker_design\osc_0\linker_design_osc_0_osc.v":19:7:19:16|Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module Linker_Design_OSC_0_OSC) 
@W: MO111 :"e:\ranjith\linker_design\component\work\linker_design\osc_0\linker_design_osc_0_osc.v":18:7:18:20|Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module Linker_Design_OSC_0_OSC) 
@W: MO111 :"e:\ranjith\linker_design\component\work\linker_design\osc_0\linker_design_osc_0_osc.v":17:7:17:20|Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module Linker_Design_OSC_0_OSC) 
@W: MO111 :"e:\ranjith\linker_design\component\work\linker_design\osc_0\linker_design_osc_0_osc.v":16:7:16:24|Tristate driver RCOSC_25_50MHZ_O2F on net RCOSC_25_50MHZ_O2F has its enable tied to GND (module Linker_Design_OSC_0_OSC) 
@W: MO111 :|Tristate driver Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS_t[0] on net Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS[0] has its enable tied to GND (module Linker_Design) 
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[31],  because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[30]
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[29],  because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28]
@W: MO160 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Register bit arbRegSMCurrentState[12] is always 0, optimizing ...
@W: MO160 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Register bit arbRegSMCurrentState[8] is always 0, optimizing ...
@W: MO160 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Register bit arbRegSMCurrentState[4] is always 0, optimizing ...
@W: BN132 :"e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28],  because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_0.regHTRANS
@W: BN132 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":229:4:229:9|Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_1.ckRdAddr[11],  because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_0.ckRdAddr[11]
@W: BN132 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":229:4:229:9|Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_2.ckRdAddr[11],  because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_0.ckRdAddr[11]
@W: BN132 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":229:4:229:9|Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_3.ckRdAddr[11],  because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_0.ckRdAddr[11]
@W: BN132 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":229:4:229:9|Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_1.ckRdAddr[12],  because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_0.ckRdAddr[12]
@W: BN132 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":229:4:229:9|Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_2.ckRdAddr[12],  because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_0.ckRdAddr[12]
@W: BN132 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":229:4:229:9|Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_3.ckRdAddr[12],  because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_0.ckRdAddr[12]
@W: BN132 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":229:4:229:9|Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_1.ckRdAddr[13],  because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_0.ckRdAddr[13]
@W: BN132 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":229:4:229:9|Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_2.ckRdAddr[13],  because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_0.ckRdAddr[13]
@W: BN132 :"e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v":229:4:229:9|Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_3.ckRdAddr[13],  because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_0.ckRdAddr[13]
@W: MT246 :"e:\ranjith\linker_design\component\work\linker_design\linker_design.v":632:9:632:18|Blackbox SYSRESET is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"e:\ranjith\linker_design\component\work\linker_design\fccc_0\linker_design_fccc_0_fccc.v":20:36:20:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:FCCC_0.GL0_net"
