| Project Settings |
|---|
| Project Name | Linker_Design_syn | Implementation Name | synthesis_1 |
| Top Module | Linker_Design | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| Compile Input | Complete |
34 |
186 |
0 |
- |
0m:01s |
- |
4/3/2014
4:14:07 PM |
| FSM Explorer | Complete |
68 |
47 |
0 |
0m:01s |
0m:01s |
146MB |
4/3/2014
4:14:10 PM |
| Pre-mapping | Complete |
55 |
17 |
0 |
0m:00s |
0m:00s |
140MB |
4/3/2014
4:14:11 PM |
| Map & Optimize | Complete |
32 |
25 |
0 |
0m:03s |
0m:03s |
151MB |
4/3/2014
4:14:15 PM |
| Area Summary |
|---|
|
| Sequential Cells | 114 |
DSP Blocks (MACC)
(dsp_used) | 0 |
| I/O Cells | 2 |
Global Clock Buffers | 2 |
| Block Rams (RAM1K18)
(v_ram) | 32 |
LUTs
(total_luts) | 415 |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 116.4 MHz | 1.411 |
| System | 100.0 MHz | 895.2 MHz | 8.883 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 1 / 0 |
| |
|