#Build: Synplify Pro I-2013.09M-SP1 , Build 034R, Jan 17 2014 #install: C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1 #OS: Windows 7 6.1 #Hostname: W764-TECHSUPPOR #Implementation: synthesis_1 $ Start of Compile #Thu Apr 03 16:14:06 2014 Synopsys Verilog Compiler, version comp201309rcp1, Build 078R, built Jan 14 2014 @N: : | Running in 64-bit mode Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. @I::"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.v" @I::"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vlog\umr_capim.v" @I::"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vlog\scemi_objects.v" @I::"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vlog\scemi_pipes.svh" @I::"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vlog\hypermods.v" @I::"E:\Ranjith\Linker_Design\component\work\Linker_Design\FCCC_0\Linker_Design_FCCC_0_FCCC.v" @I::"E:\Ranjith\Linker_Design\component\work\Linker_Design_MSS\Linker_Design_MSS_syn.v" @I::"E:\Ranjith\Linker_Design\component\work\Linker_Design_MSS\Linker_Design_MSS.v" @I::"E:\Ranjith\Linker_Design\component\Actel\SgCore\OSC\1.0.100\osc_comps.v" @I::"E:\Ranjith\Linker_Design\component\work\Linker_Design\OSC_0\Linker_Design_OSC_0_OSC.v" @I::"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v" @I::"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v" @I::"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v" @I::"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v" @I::"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v" @I::"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v" @I::"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v" @I::"E:\Ranjith\Linker_Design\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core\AHBLSramIf.v" @I::"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v" @I::"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\usram_128to9216x8.v" @I::"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v" @I::"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v" @I::"E:\Ranjith\Linker_Design\component\work\Linker_Design\Linker_Design.v" @W:CG775 : coreahblite.v(32) | Found Component CoreAHBLite in library COREAHBLITE_LIB @W:CG775 : CoreAHBLSRAM.v(29) | Found Component Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM in library COREAHBLSRAM_LIB Verilog syntax check successful! Selecting top level module Linker_Design @W:CG775 : coreahblite.v(32) | Found Component CoreAHBLite in library COREAHBLITE_LIB @N:CG364 : coreahblite_addrdec.v(29) | Synthesizing module COREAHBLITE_ADDRDEC MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000001000 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z1 @N:CG364 : coreahblite_defaultslavesm.v(29) | Synthesizing module COREAHBLITE_DEFAULTSLAVESM @N:CG364 : coreahblite_masterstage.v(31) | Synthesizing module COREAHBLITE_MASTERSTAGE MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000001000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_0_8_0_1_0 @N:CL177 : coreahblite_masterstage.v(629) | Sharing sequential element addrRegSMCurrentState. @N:CG364 : coreahblite_addrdec.v(29) | Synthesizing module COREAHBLITE_ADDRDEC MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000000 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z2 @N:CG364 : coreahblite_masterstage.v(31) | Synthesizing module COREAHBLITE_MASTERSTAGE MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0 @N:CL177 : coreahblite_masterstage.v(629) | Sharing sequential element addrRegSMCurrentState. @N:CG364 : coreahblite_slavearbiter.v(28) | Synthesizing module COREAHBLITE_SLAVEARBITER @N:CG364 : coreahblite_slavestage.v(30) | Synthesizing module COREAHBLITE_SLAVESTAGE @N:CG364 : coreahblite_matrix4x16.v(31) | Synthesizing module COREAHBLITE_MATRIX4X16 MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M0_AHBSLOTENABLE=17'b00000000000001000 M1_AHBSLOTENABLE=17'b00000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 Generated name = COREAHBLITE_MATRIX4X16_1_1_0_8_0_0_0 @N:CG364 : coreahblite.v(32) | Synthesizing module CoreAHBLite FAMILY=6'b010011 MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 M0_AHBSLOT0ENABLE=1'b0 M0_AHBSLOT1ENABLE=1'b0 M0_AHBSLOT2ENABLE=1'b0 M0_AHBSLOT3ENABLE=1'b1 M0_AHBSLOT4ENABLE=1'b0 M0_AHBSLOT5ENABLE=1'b0 M0_AHBSLOT6ENABLE=1'b0 M0_AHBSLOT7ENABLE=1'b0 M0_AHBSLOT8ENABLE=1'b0 M0_AHBSLOT9ENABLE=1'b0 M0_AHBSLOT10ENABLE=1'b0 M0_AHBSLOT11ENABLE=1'b0 M0_AHBSLOT12ENABLE=1'b0 M0_AHBSLOT13ENABLE=1'b0 M0_AHBSLOT14ENABLE=1'b0 M0_AHBSLOT15ENABLE=1'b0 M0_AHBSLOT16ENABLE=1'b0 M1_AHBSLOT0ENABLE=1'b0 M1_AHBSLOT1ENABLE=1'b0 M1_AHBSLOT2ENABLE=1'b0 M1_AHBSLOT3ENABLE=1'b0 M1_AHBSLOT4ENABLE=1'b0 M1_AHBSLOT5ENABLE=1'b0 M1_AHBSLOT6ENABLE=1'b0 M1_AHBSLOT7ENABLE=1'b0 M1_AHBSLOT8ENABLE=1'b0 M1_AHBSLOT9ENABLE=1'b0 M1_AHBSLOT10ENABLE=1'b0 M1_AHBSLOT11ENABLE=1'b0 M1_AHBSLOT12ENABLE=1'b0 M1_AHBSLOT13ENABLE=1'b0 M1_AHBSLOT14ENABLE=1'b0 M1_AHBSLOT15ENABLE=1'b0 M1_AHBSLOT16ENABLE=1'b0 M2_AHBSLOT0ENABLE=1'b0 M2_AHBSLOT1ENABLE=1'b0 M2_AHBSLOT2ENABLE=1'b0 M2_AHBSLOT3ENABLE=1'b0 M2_AHBSLOT4ENABLE=1'b0 M2_AHBSLOT5ENABLE=1'b0 M2_AHBSLOT6ENABLE=1'b0 M2_AHBSLOT7ENABLE=1'b0 M2_AHBSLOT8ENABLE=1'b0 M2_AHBSLOT9ENABLE=1'b0 M2_AHBSLOT10ENABLE=1'b0 M2_AHBSLOT11ENABLE=1'b0 M2_AHBSLOT12ENABLE=1'b0 M2_AHBSLOT13ENABLE=1'b0 M2_AHBSLOT14ENABLE=1'b0 M2_AHBSLOT15ENABLE=1'b0 M2_AHBSLOT16ENABLE=1'b0 M3_AHBSLOT0ENABLE=1'b0 M3_AHBSLOT1ENABLE=1'b0 M3_AHBSLOT2ENABLE=1'b0 M3_AHBSLOT3ENABLE=1'b0 M3_AHBSLOT4ENABLE=1'b0 M3_AHBSLOT5ENABLE=1'b0 M3_AHBSLOT6ENABLE=1'b0 M3_AHBSLOT7ENABLE=1'b0 M3_AHBSLOT8ENABLE=1'b0 M3_AHBSLOT9ENABLE=1'b0 M3_AHBSLOT10ENABLE=1'b0 M3_AHBSLOT11ENABLE=1'b0 M3_AHBSLOT12ENABLE=1'b0 M3_AHBSLOT13ENABLE=1'b0 M3_AHBSLOT14ENABLE=1'b0 M3_AHBSLOT15ENABLE=1'b0 M3_AHBSLOT16ENABLE=1'b0 M0_AHBSLOTENABLE=17'b00000000000001000 M1_AHBSLOTENABLE=17'b00000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SC=16'b0000000000000000 Generated name = CoreAHBLite_Z3 @W:CG775 : CoreAHBLSRAM.v(29) | Found Component Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM in library COREAHBLSRAM_LIB @N:CG364 : AHBLSramIf.v(29) | Synthesizing module AHBLSramIf @W:CL169 : AHBLSramIf.v(161) | Pruning register HWDATA_d[31:0] @W:CL169 : AHBLSramIf.v(161) | Pruning register HTRANS_d[1:0] @W:CL169 : AHBLSramIf.v(161) | Pruning register HSEL_d @W:CL169 : AHBLSramIf.v(161) | Pruning register HREADYIN_d @N:CG364 : SramCtrlIf.v(29) | Synthesizing module Linker_Design_COREAHBLSRAM_0_SramCtrlIf SEL_SRAM_TYPE=32'b00000000000000000000000000000000 LSRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000000100000000000000 USRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000000000001000000000 AHB_DWIDTH=32'b00000000000000000000000000100000 S_IDLE=2'b00 S_WR=2'b01 S_RD=2'b10 Generated name = Linker_Design_COREAHBLSRAM_0_SramCtrlIf_0s_16384s_512s_32s_0_1_2 @N:CG364 : smartfusion2.v(377) | Synthesizing module RAM1K18 @N:CG364 : lsram_2048to139264x8.v(28) | Synthesizing module Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8 DEPTH=32'b00000000000000000100000000000000 AHB_DWIDTH=32'b00000000000000000000000000001000 Generated name = Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s @W:CL271 : lsram_2048to139264x8.v(229) | Pruning bits 15 to 14 of ckRdAddr[15:9] -- not in use ... @W:CL265 : lsram_2048to139264x8.v(229) | Pruning bit 9 of ckRdAddr[15:9] -- not in use ... @N:CG179 : SramCtrlIf.v(381) | Removing redundant assignment @W:CG133 : SramCtrlIf.v(95) | No assignment to ahbsram_wdata_upd_r @W:CG133 : SramCtrlIf.v(96) | No assignment to u_ahbsram_wdata_upd_r @W:CG360 : SramCtrlIf.v(103) | No assignment to wire u_BUSY_all_0 @W:CG360 : SramCtrlIf.v(104) | No assignment to wire u_BUSY_all_1 @W:CG360 : SramCtrlIf.v(105) | No assignment to wire u_BUSY_all_2 @W:CG360 : SramCtrlIf.v(106) | No assignment to wire u_BUSY_all_3 @W:CG360 : SramCtrlIf.v(113) | No assignment to wire u_ahbsram_wdata_upd @N:CG364 : CoreAHBLSRAM.v(29) | Synthesizing module Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM FAMILY=32'b00000000000000000000000000010011 AHB_DWIDTH=32'b00000000000000000000000000100000 AHB_AWIDTH=32'b00000000000000000000000000100000 LSRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000000100000000000000 USRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000000000001000000000 SEL_SRAM_TYPE=32'b00000000000000000000000000000000 Generated name = Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM_19s_32s_32s_16384s_512s_0s @N:CG364 : smartfusion2.v(371) | Synthesizing module VCC @N:CG364 : smartfusion2.v(367) | Synthesizing module GND @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT @N:CG364 : smartfusion2.v(722) | Synthesizing module CCC @N:CG364 : Linker_Design_FCCC_0_FCCC.v(5) | Synthesizing module Linker_Design_FCCC_0_FCCC @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF @N:CG364 : Linker_Design_MSS_syn.v(5) | Synthesizing module MSS_050 @N:CG364 : Linker_Design_MSS.v(9) | Synthesizing module Linker_Design_MSS @W:CG360 : Linker_Design_MSS.v(57) | No assignment to wire FIC_0_AHB_M_HTRANS_0 @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ @N:CG364 : Linker_Design_OSC_0_OSC.v(5) | Synthesizing module Linker_Design_OSC_0_OSC @N:CG364 : smartfusion2.v(713) | Synthesizing module SYSRESET @N:CG364 : Linker_Design.v(9) | Synthesizing module Linker_Design @W:CL157 : Linker_Design_OSC_0_OSC.v(16) | *Output RCOSC_25_50MHZ_O2F has undriven bits -- simulation mismatch possible. @W:CL157 : Linker_Design_OSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : Linker_Design_OSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible. @W:CL157 : Linker_Design_OSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : Linker_Design_OSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits -- simulation mismatch possible. @W:CL159 : Linker_Design_OSC_0_OSC.v(14) | Input XTL is unused @W:CL157 : Linker_Design_MSS.v(43) | *Output FIC_0_AHB_M_HTRANS has undriven bits -- simulation mismatch possible. @W:CL246 : CoreAHBLSRAM.v(68) | Input port bits 31 to 20 of HADDR[31:0] are unused @W:CL260 : lsram_2048to139264x8.v(229) | Pruning register bit 10 of ckRdAddr[13:10] @W:CL246 : lsram_2048to139264x8.v(61) | Input port bits 15 to 14 of writeAddr[15:0] are unused @W:CL246 : lsram_2048to139264x8.v(62) | Input port bits 15 to 14 of readAddr[15:0] are unused @W:CL246 : lsram_2048to139264x8.v(62) | Input port bits 10 to 0 of readAddr[15:0] are unused @W:CL159 : lsram_2048to139264x8.v(60) | Input ren is unused @N:CL201 : SramCtrlIf.v(127) | Trying to extract state machine for register sramcurr_state Extracted state machine for register sramcurr_state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL246 : SramCtrlIf.v(72) | Input port bits 19 to 18 of ahbsram_addr[19:0] are unused @N:CL201 : AHBLSramIf.v(185) | Trying to extract state machine for register ahbcurr_state Extracted state machine for register ahbcurr_state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL159 : AHBLSramIf.v(97) | Input BUSY is unused @W:CL247 : coreahblite.v(128) | Input port bit 0 of HTRANS_M0[1:0] is unused @W:CL247 : coreahblite.v(139) | Input port bit 0 of HTRANS_M1[1:0] is unused @W:CL247 : coreahblite.v(150) | Input port bit 0 of HTRANS_M2[1:0] is unused @W:CL247 : coreahblite.v(161) | Input port bit 0 of HTRANS_M3[1:0] is unused @W:CL247 : coreahblite.v(171) | Input port bit 1 of HRESP_S0[1:0] is unused @W:CL247 : coreahblite.v(184) | Input port bit 1 of HRESP_S1[1:0] is unused @W:CL247 : coreahblite.v(197) | Input port bit 1 of HRESP_S2[1:0] is unused @W:CL247 : coreahblite.v(210) | Input port bit 1 of HRESP_S3[1:0] is unused @W:CL247 : coreahblite.v(223) | Input port bit 1 of HRESP_S4[1:0] is unused @W:CL247 : coreahblite.v(236) | Input port bit 1 of HRESP_S5[1:0] is unused @W:CL247 : coreahblite.v(249) | Input port bit 1 of HRESP_S6[1:0] is unused @W:CL247 : coreahblite.v(262) | Input port bit 1 of HRESP_S7[1:0] is unused @W:CL247 : coreahblite.v(275) | Input port bit 1 of HRESP_S8[1:0] is unused @W:CL247 : coreahblite.v(288) | Input port bit 1 of HRESP_S9[1:0] is unused @W:CL247 : coreahblite.v(301) | Input port bit 1 of HRESP_S10[1:0] is unused @W:CL247 : coreahblite.v(314) | Input port bit 1 of HRESP_S11[1:0] is unused @W:CL247 : coreahblite.v(327) | Input port bit 1 of HRESP_S12[1:0] is unused @W:CL247 : coreahblite.v(340) | Input port bit 1 of HRESP_S13[1:0] is unused @W:CL247 : coreahblite.v(353) | Input port bit 1 of HRESP_S14[1:0] is unused @W:CL247 : coreahblite.v(366) | Input port bit 1 of HRESP_S15[1:0] is unused @W:CL247 : coreahblite.v(379) | Input port bit 1 of HRESP_S16[1:0] is unused @W:CL159 : coreahblite.v(131) | Input HBURST_M0 is unused @W:CL159 : coreahblite.v(132) | Input HPROT_M0 is unused @W:CL159 : coreahblite.v(142) | Input HBURST_M1 is unused @W:CL159 : coreahblite.v(143) | Input HPROT_M1 is unused @W:CL159 : coreahblite.v(153) | Input HBURST_M2 is unused @W:CL159 : coreahblite.v(154) | Input HPROT_M2 is unused @W:CL159 : coreahblite.v(164) | Input HBURST_M3 is unused @W:CL159 : coreahblite.v(165) | Input HPROT_M3 is unused @W:CL159 : coreahblite_matrix4x16.v(58) | Input HWDATA_M1 is unused @W:CL159 : coreahblite_matrix4x16.v(67) | Input HWDATA_M2 is unused @W:CL159 : coreahblite_matrix4x16.v(76) | Input HWDATA_M3 is unused @W:CL159 : coreahblite_matrix4x16.v(80) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_matrix4x16.v(81) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_matrix4x16.v(82) | Input HRESP_S0 is unused @W:CL159 : coreahblite_matrix4x16.v(91) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(92) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(93) | Input HRESP_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(102) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(103) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(104) | Input HRESP_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(124) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(125) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(126) | Input HRESP_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(135) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(136) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(137) | Input HRESP_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(146) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(147) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(148) | Input HRESP_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(157) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(158) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(159) | Input HRESP_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(168) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(169) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(170) | Input HRESP_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(179) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(180) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(181) | Input HRESP_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(190) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(191) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(192) | Input HRESP_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(201) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(202) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(203) | Input HRESP_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(212) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(213) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(214) | Input HRESP_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(223) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(224) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(225) | Input HRESP_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(234) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(235) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(236) | Input HRESP_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(245) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_matrix4x16.v(246) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_matrix4x16.v(247) | Input HRESP_S15 is unused @W:CL159 : coreahblite_matrix4x16.v(256) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_matrix4x16.v(257) | Input HREADYOUT_S16 is unused @W:CL159 : coreahblite_matrix4x16.v(258) | Input HRESP_S16 is unused @W:CL246 : coreahblite_slavestage.v(46) | Input port bits 3 to 2 of MPREVDATASLAVEREADY[3:0] are unused @N:CL201 : coreahblite_slavearbiter.v(452) | Trying to extract state machine for register arbRegSMCurrentState Extracted state machine for register arbRegSMCurrentState State machine has 16 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 @W:CL159 : coreahblite_masterstage.v(50) | Input SDATAREADY is unused @W:CL159 : coreahblite_masterstage.v(51) | Input SHRESP is unused @W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.v(86) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.v(87) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.v(88) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.v(89) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.v(90) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.v(91) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.v(92) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_masterstage.v(93) | Input HREADYOUT_S16 is unused @W:CL246 : coreahblite_masterstage.v(50) | Input port bits 16 to 4 of SDATAREADY[16:0] are unused @W:CL246 : coreahblite_masterstage.v(50) | Input port bits 2 to 0 of SDATAREADY[16:0] are unused @W:CL246 : coreahblite_masterstage.v(51) | Input port bits 16 to 4 of SHRESP[16:0] are unused @W:CL246 : coreahblite_masterstage.v(51) | Input port bits 2 to 0 of SHRESP[16:0] are unused @W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.v(86) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.v(87) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.v(88) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.v(89) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.v(90) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.v(91) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.v(92) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_masterstage.v(93) | Input HREADYOUT_S16 is unused @END At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 86MB peak: 87MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Apr 03 16:14:07 2014 ###########################################################] instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2708) | Removing instance masterstage_1 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2771) | Removing instance masterstage_2 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2834) | Removing instance masterstage_3 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2892) | Removing instance slavestage_0 of view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_slavestage_0(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2708) | Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2728) | Removing sequential instance block15 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2748) | Removing sequential instance block14 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2768) | Removing sequential instance block13 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2788) | Removing sequential instance block12 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2808) | Removing sequential instance block11 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2828) | Removing sequential instance block10 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2848) | Removing sequential instance block9 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2868) | Removing sequential instance block8 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_3(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2708) | Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2728) | Removing sequential instance block15 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2748) | Removing sequential instance block14 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2768) | Removing sequential instance block13 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2788) | Removing sequential instance block12 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2808) | Removing sequential instance block11 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2828) | Removing sequential instance block10 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2848) | Removing sequential instance block9 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2868) | Removing sequential instance block8 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_2(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2708) | Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2728) | Removing sequential instance block15 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2748) | Removing sequential instance block14 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2768) | Removing sequential instance block13 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2788) | Removing sequential instance block12 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2808) | Removing sequential instance block11 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2828) | Removing sequential instance block10 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2848) | Removing sequential instance block9 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2868) | Removing sequential instance block8 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_1(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2708) | Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2728) | Removing sequential instance block15 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2748) | Removing sequential instance block14 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2768) | Removing sequential instance block13 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2788) | Removing sequential instance block12 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2808) | Removing sequential instance block11 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2828) | Removing sequential instance block10 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2848) | Removing sequential instance block9 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2868) | Removing sequential instance block8 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_genblk1\.byte_0(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(82) | Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_slavestage_0(verilog) because there are no references to its outputs @N:BN115 : coreahblite_slavestage.v(90) | Removing instance slave_arbiter of view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(452) | Removing sequential instance arbRegSMCurrentState[15:0] of view:PrimLib.statemachine(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter(verilog) because there are no references to its outputs syn_allowed_resources : blockrams=69 set on top level netlist Linker_Design Clock Summary ************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ----------------------------------------------------------------------------------------------------------------- Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 System 1.0 MHz 1000.000 system system_clkgroup ================================================================================================================= @W:MT530 : coreahblite_defaultslavesm.v(66) | Found inferred clock Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock which controls 159 sequential elements including CoreAHBLite_0.matrix4x16.masterstage_0.default_slave_sm.defSlaveSMCurrentState. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @W:MO111 : | Tristate driver Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS_t[0] on net Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS[0] has its enable tied to GND (module Linker_Design) @N:BN225 : | Writing default property annotation file E:\Ranjith\Linker_Design\synthesis\synthesis_1\Linker_Design.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 140MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Apr 03 16:14:11 2014 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2013.09M-SP1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 138MB) @W:MO111 : linker_design_mss.v(43) | Tristate driver FIC_0_AHB_M_HTRANS_1 on net FIC_0_AHB_M_HTRANS_1 has its enable tied to GND (module Linker_Design_MSS) @W:MO111 : linker_design_osc_0_osc.v(20) | Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module Linker_Design_OSC_0_OSC) @W:MO111 : linker_design_osc_0_osc.v(19) | Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module Linker_Design_OSC_0_OSC) @W:MO111 : linker_design_osc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module Linker_Design_OSC_0_OSC) @W:MO111 : linker_design_osc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module Linker_Design_OSC_0_OSC) @W:MO111 : linker_design_osc_0_osc.v(16) | Tristate driver RCOSC_25_50MHZ_O2F on net RCOSC_25_50MHZ_O2F has its enable tied to GND (module Linker_Design_OSC_0_OSC) @W:MO111 : | Tristate driver Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS_t[0] on net Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS[0] has its enable tied to GND (module Linker_Design) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 138MB) @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[20] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[21] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[22] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[23] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[24] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[25] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[26] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[27] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(82) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_3.masterDataInProg[3] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(82) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_3.masterDataInProg[2] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(82) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_3.masterDataInProg[1] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(233) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[16] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs @W:BN132 : coreahblite_masterstage.v(167) | Removing instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[31], because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[30] @W:BN132 : coreahblite_masterstage.v(167) | Removing instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[29], because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28] Encoding state machine arbRegSMCurrentState[15:0] (view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter_0(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @W:MO160 : coreahblite_slavearbiter.v(452) | Register bit arbRegSMCurrentState[12] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(452) | Register bit arbRegSMCurrentState[8] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(452) | Register bit arbRegSMCurrentState[4] is always 0, optimizing ... Encoding state machine ahbcurr_state[2:0] (view:COREAHBLSRAM_LIB.AHBLSramIf(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:BN362 : ahblsramif.v(161) | Removing sequential instance HADDR_d[16] in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs @N:BN362 : ahblsramif.v(161) | Removing sequential instance HADDR_d[17] in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs @N:BN362 : ahblsramif.v(161) | Removing sequential instance HADDR_d[18] in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs @N:BN362 : ahblsramif.v(161) | Removing sequential instance HADDR_d[19] in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs Encoding state machine sramcurr_state[2:0] (view:COREAHBLSRAM_LIB.Linker_Design_COREAHBLSRAM_0_SramCtrlIf_0s_16384s_512s_32s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[16] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[17] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[18] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[19] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs @W:BN132 : coreahblite_masterstage.v(167) | Removing instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28], because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_0.regHTRANS @W:BN132 : lsram_2048to139264x8.v(229) | Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_3.ckRdAddr[11], because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_2.ckRdAddr[11] @W:BN132 : lsram_2048to139264x8.v(229) | Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_2.ckRdAddr[11], because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_1.ckRdAddr[11] @W:BN132 : lsram_2048to139264x8.v(229) | Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_1.ckRdAddr[11], because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_0.ckRdAddr[11] @W:BN132 : lsram_2048to139264x8.v(229) | Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_3.ckRdAddr[12], because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_2.ckRdAddr[12] @W:BN132 : lsram_2048to139264x8.v(229) | Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_2.ckRdAddr[12], because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_1.ckRdAddr[12] @W:BN132 : lsram_2048to139264x8.v(229) | Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_1.ckRdAddr[12], because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_0.ckRdAddr[12] @W:BN132 : lsram_2048to139264x8.v(229) | Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_3.ckRdAddr[13], because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_2.ckRdAddr[13] @W:BN132 : lsram_2048to139264x8.v(229) | Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_2.ckRdAddr[13], because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_1.ckRdAddr[13] @W:BN132 : lsram_2048to139264x8.v(229) | Removing instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_1.ckRdAddr[13], because it is equivalent to instance COREAHBLSRAM_0.U_SramCtrlIf.genblk1.byte_0.ckRdAddr[13] @N:BN362 : ahblsramif.v(161) | Removing sequential instance COREAHBLSRAM_0.U_AHBLSramIf.HSIZE_d[2] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[30] in hierarchy view:work.Linker_Design(verilog) because there are no references to its outputs Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 141MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 141MB) Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 141MB) Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 149MB peak: 151MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:01s -1.77ns 404 / 114 2 0h:00m:01s -1.64ns 404 / 114 ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:02s -0.45ns 417 / 114 ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:02s -0.45ns 417 / 114 ------------------------------------------------------------ @N:FP130 : | Promoting Net Linker_Design_MSS_0_MSS_RESET_N_M2F on CLKINT I_133 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 141MB peak: 151MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 142MB peak: 151MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 1 non-gated/non-generated clock tree(s) driving 179 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks ===================================== Non-Gated/Non-Generated Clocks ===================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ---------------------------------------------------------------------------------------------------------- ClockId0001 FCCC_0.GL0_INST CLKINT 179 Linker_Design_MSS_0.MSS_ADLIB_INST ========================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Writing Analyst data base E:\Ranjith\Linker_Design\synthesis\synthesis_1\Linker_Design.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 139MB peak: 151MB) Writing EDIF Netlist and constraint files @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF I-2013.09M-SP1 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 140MB peak: 151MB) Writing Verilog Simulation files Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 139MB peak: 151MB) @W:MT246 : linker_design.v(634) | Blackbox SYSRESET is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : linker_design_fccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:FCCC_0.GL0_net" ##### START OF TIMING REPORT #####[ # Timing Report written on Thu Apr 03 16:14:15 2014 # Top view: Linker_Design Requested Frequency: 100.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): E:\Ranjith\Linker_Design\synthesis\synthesis_1\Linker_Design_fsm.sdc @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 0.572 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------------- Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 116.4 MHz 10.000 8.589 1.411 inferred Inferred_clkgroup_0 System 100.0 MHz 895.2 MHz 10.000 1.117 8.883 system system_clkgroup ======================================================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ System System | 10.000 8.883 | No paths - | No paths - | No paths - System Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock | 10.000 6.523 | No paths - | No paths - | No paths - Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock System | 10.000 0.572 | No paths - | No paths - | No paths - Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock | 10.000 1.411 | No paths - | No paths - | No paths - ========================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Linker_Design_MSS_0.MSS_ADLIB_INST Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock MSS_050 F_HM0_ADDR[30] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[30] 2.999 0.572 Linker_Design_MSS_0.MSS_ADLIB_INST Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock MSS_050 F_HM0_ADDR[29] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[29] 3.021 0.631 Linker_Design_MSS_0.MSS_ADLIB_INST Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock MSS_050 F_HM0_SIZE[0] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE[0] 3.139 0.638 Linker_Design_MSS_0.MSS_ADLIB_INST Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock MSS_050 F_HM0_ADDR[31] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[31] 3.049 0.644 Linker_Design_MSS_0.MSS_ADLIB_INST Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock MSS_050 F_HM0_TRANS1 Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS[1] 3.106 0.807 Linker_Design_MSS_0.MSS_ADLIB_INST Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock MSS_050 F_HM0_ADDR[28] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[28] 2.980 1.045 Linker_Design_MSS_0.MSS_ADLIB_INST Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock MSS_050 F_HM0_SIZE[1] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE[1] 3.163 1.151 CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[13] Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock SLE Q arbRegSMCurrentState[13] 0.108 1.641 CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[1] Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock SLE Q arbRegSMCurrentState[1] 0.108 1.911 CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[5] Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock SLE Q arbRegSMCurrentState[5] 0.108 1.929 ========================================================================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------- COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block0 Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock RAM1K18 A_WEN[0] wen_a0[0] 10.000 0.572 COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block0 Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock RAM1K18 A_WEN[0] wen_a0[0] 10.000 0.572 COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block1 Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock RAM1K18 A_WEN[0] wen_a1[0] 10.000 0.572 COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block1 Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock RAM1K18 A_WEN[0] wen_a1[0] 10.000 0.572 COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block2 Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock RAM1K18 A_WEN[0] wen_a2[0] 10.000 0.572 COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block2 Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock RAM1K18 A_WEN[0] wen_a2[0] 10.000 0.572 COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block3 Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock RAM1K18 A_WEN[0] wen_a3[0] 10.000 0.572 COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block3 Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock RAM1K18 A_WEN[0] wen_a3[0] 10.000 0.572 COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_3.block0 Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock RAM1K18 A_WEN[0] wen_a0[0] 10.000 0.575 COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_3.block0 Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock RAM1K18 A_WEN[0] wen_a0[0] 10.000 0.575 ===================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 10.000 - Propagation time: 9.428 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 0.572 Number of logic level(s): 5 Starting point: Linker_Design_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[30] Ending point: COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block3 / A_WEN[0] The start point is clocked by Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------------- Linker_Design_MSS_0.MSS_ADLIB_INST MSS_050 F_HM0_ADDR[30] Out 2.999 2.999 - Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[30] Net - - 1.135 - 8 CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.MASTERADDRINPROG_i_a2_d_c_c[0] CFG4 B In - 4.134 - CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.MASTERADDRINPROG_i_a2_d_c_c[0] CFG4 Y Out 0.143 4.277 - MASTERADDRINPROG_i_a2_d_c_c[0] Net - - 0.678 - 3 COREAHBLSRAM_0.U_AHBLSramIf.HSIZE_d_RNI07AN1[0] CFG4 D In - 4.955 - COREAHBLSRAM_0.U_AHBLSramIf.HSIZE_d_RNI07AN1[0] CFG4 Y Out 0.470 5.425 - ahbsram_N_4 Net - - 0.556 - 1 COREAHBLSRAM_0.U_SramCtrlIf.sram_wen_mem_ss3_1 CFG4 B In - 5.981 - COREAHBLSRAM_0.U_SramCtrlIf.sram_wen_mem_ss3_1 CFG4 Y Out 0.153 6.134 - sram_wen_mem_ss3_1 Net - - 0.556 - 1 COREAHBLSRAM_0.U_SramCtrlIf.sram_wen_mem_ss3 CFG4 C In - 6.689 - COREAHBLSRAM_0.U_SramCtrlIf.sram_wen_mem_ss3 CFG4 Y Out 0.226 6.915 - sram_wen_mem_ss3 Net - - 0.923 - 16 COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block3_RNO CFG4 D In - 7.838 - COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block3_RNO CFG4 Y Out 0.472 8.311 - wen_a3[0] Net - - 1.117 - 1 COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block3 RAM1K18 A_WEN[0] In - 9.428 - ============================================================================================================================================================== Total path delay (propagation time + setup) of 9.428 is 4.463(47.3%) logic and 4.964(52.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------- COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.block1 System RAM1K18 A_DOUT[0] readData1[0] 0.000 6.523 COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.block1 System RAM1K18 A_DOUT[0] readData1[0] 0.000 6.523 COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.block1 System RAM1K18 A_DOUT[0] readData1[0] 0.000 6.523 COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.block1 System RAM1K18 A_DOUT[0] readData1[0] 0.000 6.523 COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block1 System RAM1K18 A_DOUT[0] readData1[0] 0.000 6.523 COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block1 System RAM1K18 A_DOUT[0] readData1[0] 0.000 6.523 COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.block1 System RAM1K18 A_DOUT[1] readData1[1] 0.000 6.523 COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.block1 System RAM1K18 A_DOUT[1] readData1[1] 0.000 6.523 COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.block1 System RAM1K18 A_DOUT[1] readData1[1] 0.000 6.523 COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.block1 System RAM1K18 A_DOUT[1] readData1[1] 0.000 6.523 ================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------- COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[0] System SLE D ram_rdata[0] 9.745 6.523 COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[1] System SLE D ram_rdata[1] 9.745 6.523 COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[2] System SLE D ram_rdata[2] 9.745 6.523 COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[3] System SLE D ram_rdata[3] 9.745 6.523 COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[4] System SLE D ram_rdata[4] 9.745 6.523 COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[5] System SLE D ram_rdata[5] 9.745 6.523 COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[6] System SLE D ram_rdata[6] 9.745 6.523 COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[7] System SLE D ram_rdata[7] 9.745 6.523 COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[8] System SLE D ram_rdata[8] 9.745 6.523 COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[9] System SLE D ram_rdata[9] 9.745 6.523 =================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.745 - Propagation time: 3.222 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 6.523 Number of logic level(s): 3 Starting point: COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.block1 / A_DOUT[0] Ending point: COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[0] / D The start point is clocked by System [rising] The end point is clocked by Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------- COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.block1 RAM1K18 A_DOUT[0] Out 0.000 0.000 - readData1[0] Net - - 1.117 - 1 COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.readData_7_bm_1_1[0] CFG4 B In - 1.117 - COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.readData_7_bm_1_1[0] CFG4 Y Out 0.153 1.270 - readData_7_bm_1_1[0] Net - - 0.556 - 1 COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.readData_7_bm[0] CFG4 D In - 1.826 - COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.readData_7_bm[0] CFG4 Y Out 0.472 2.298 - readData_7_bm_2[0] Net - - 0.556 - 1 COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.readData_7_ns[0] CFG3 C In - 2.854 - COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.readData_7_ns[0] CFG3 Y Out 0.209 3.063 - ram_rdata[0] Net - - 0.159 - 1 COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[0] SLE D In - 3.222 - ======================================================================================================================================= Total path delay (propagation time + setup) of 3.477 is 1.090(31.4%) logic and 2.387(68.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report for Linker_Design Mapping to part: m2s050tfbga896std Cell usage: CCC 1 use CLKINT 2 uses MSS_050 1 use RCOSC_25_50MHZ 1 use SYSRESET 1 use CFG2 89 uses CFG3 67 uses CFG4 259 uses Sequential Cells: SLE 114 uses DSP Blocks: 0 I/O ports: 3 I/O primitives: 2 INBUF 1 use TRIBUFF 1 use Global Clock Buffers: 2 RAM/ROM usage summary Block Rams (RAM1K18) : 32 Total LUTs: 415 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 52MB peak: 151MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime # Thu Apr 03 16:14:15 2014 ###########################################################]