@N|Running in 64-bit mode
@N: CG364 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v":29:7:29:25|Synthesizing module COREAHBLITE_ADDRDEC
@N: CG364 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v":29:7:29:32|Synthesizing module COREAHBLITE_DEFAULTSLAVESM
@N: CG364 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":31:7:31:29|Synthesizing module COREAHBLITE_MASTERSTAGE
@N: CL177 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":629:0:629:5|Sharing sequential element addrRegSMCurrentState.
@N: CG364 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v":29:7:29:25|Synthesizing module COREAHBLITE_ADDRDEC
@N: CG364 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":31:7:31:29|Synthesizing module COREAHBLITE_MASTERSTAGE
@N: CL177 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":629:0:629:5|Sharing sequential element addrRegSMCurrentState.
@N: CG364 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":28:7:28:30|Synthesizing module COREAHBLITE_SLAVEARBITER
@N: CG364 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":30:7:30:28|Synthesizing module COREAHBLITE_SLAVESTAGE
@N: CG364 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":31:7:31:28|Synthesizing module COREAHBLITE_MATRIX4X16
@N: CG364 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":32:7:32:17|Synthesizing module CoreAHBLite
@N: CG364 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core\AHBLSramIf.v":29:7:29:16|Synthesizing module AHBLSramIf
@N: CG364 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":29:7:29:45|Synthesizing module Linker_Design_COREAHBLSRAM_0_SramCtrlIf
@N: CG364 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.v":377:7:377:13|Synthesizing module RAM1K18
@N: CG364 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":28:7:28:55|Synthesizing module Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8
@N: CG179 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":381:26:381:38|Removing redundant assignment
@N: CG364 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v":29:7:29:47|Synthesizing module Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM
@N: CG364 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.v":371:7:371:9|Synthesizing module VCC
@N: CG364 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.v":367:7:367:9|Synthesizing module GND
@N: CG364 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.v":362:7:362:12|Synthesizing module CLKINT
@N: CG364 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.v":722:7:722:9|Synthesizing module CCC
@N: CG364 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\FCCC_0\Linker_Design_FCCC_0_FCCC.v":5:7:5:31|Synthesizing module Linker_Design_FCCC_0_FCCC
@N: CG364 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.v":268:7:268:11|Synthesizing module INBUF
@N: CG364 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.v":280:7:280:13|Synthesizing module TRIBUFF
@N: CG364 :"E:\Ranjith\Linker_Design\component\work\Linker_Design_MSS\Linker_Design_MSS_syn.v":5:7:5:13|Synthesizing module MSS_050
@N: CG364 :"E:\Ranjith\Linker_Design\component\work\Linker_Design_MSS\Linker_Design_MSS.v":9:7:9:23|Synthesizing module Linker_Design_MSS
@N: CG364 :"E:\Ranjith\Linker_Design\component\Actel\SgCore\OSC\1.0.100\osc_comps.v":11:7:11:20|Synthesizing module RCOSC_25_50MHZ
@N: CG364 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\OSC_0\Linker_Design_OSC_0_OSC.v":5:7:5:29|Synthesizing module Linker_Design_OSC_0_OSC
@N: CG364 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.v":713:7:713:14|Synthesizing module SYSRESET
@N: CG364 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\Linker_Design.v":9:7:9:19|Synthesizing module Linker_Design
@N: CL201 :"E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":127:3:127:8|Trying to extract state machine for register sramcurr_state
@N: CL201 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core\AHBLSramIf.v":185:3:185:8|Trying to extract state machine for register ahbcurr_state
@N: CL201 :"E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Trying to extract state machine for register arbRegSMCurrentState

