C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\bin64\c_ver.exe  -osyn  E:\Ranjith\Linker_Design\synthesis\synthesis_1\synwork\Linker_Design_comp.srs  -top  Linker_Design  -prodtype  synplify_pro  -primux -dspmac -pqdpadd -fixsmult   -divnmod -nram -I E:\Ranjith\Linker_Design\synthesis\  -I C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib  -v2001  -devicelib  C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.v  -encrypt  -pro  -dmgen  E:\Ranjith\Linker_Design\synthesis\synthesis_1\dm  -ui -fid2 -ram -sharing on  -ll 2000 -autosm -lib work E:\Ranjith\Linker_Design\component\work\Linker_Design\FCCC_0\Linker_Design_FCCC_0_FCCC.v -lib work E:\Ranjith\Linker_Design\component\work\Linker_Design_MSS\Linker_Design_MSS_syn.v -lib work E:\Ranjith\Linker_Design\component\work\Linker_Design_MSS\Linker_Design_MSS.v -lib work E:\Ranjith\Linker_Design\component\Actel\SgCore\OSC\1.0.100\osc_comps.v -lib work E:\Ranjith\Linker_Design\component\work\Linker_Design\OSC_0\Linker_Design_OSC_0_OSC.v -lib COREAHBLITE_LIB E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v -lib COREAHBLITE_LIB E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v -lib COREAHBLITE_LIB E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v -lib COREAHBLITE_LIB E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v -lib COREAHBLITE_LIB E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v -lib COREAHBLITE_LIB E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v -lib COREAHBLITE_LIB E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v -lib COREAHBLSRAM_LIB E:\Ranjith\Linker_Design\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core\AHBLSramIf.v -lib COREAHBLSRAM_LIB E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v -lib COREAHBLSRAM_LIB E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\usram_128to9216x8.v -lib COREAHBLSRAM_LIB E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v -lib COREAHBLSRAM_LIB E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v -lib work E:\Ranjith\Linker_Design\component\work\Linker_Design\Linker_Design.v -loga  E:\Ranjith\Linker_Design\synthesis\synthesis_1\Linker_Design.srr 
rc:1 success:1
E:\Ranjith\Linker_Design\synthesis\synthesis_1\synwork\Linker_Design_comp.srs|o|1396521847|200714
C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.v|i|1389673372|16267
E:\Ranjith\Linker_Design\component\work\Linker_Design\FCCC_0\Linker_Design_FCCC_0_FCCC.v|i|1396498750|1727
E:\Ranjith\Linker_Design\component\work\Linker_Design_MSS\Linker_Design_MSS_syn.v|i|1396497922|77142
E:\Ranjith\Linker_Design\component\work\Linker_Design_MSS\Linker_Design_MSS.v|i|1396497922|53043
E:\Ranjith\Linker_Design\component\Actel\SgCore\OSC\1.0.100\osc_comps.v|i|1390829465|924
E:\Ranjith\Linker_Design\component\work\Linker_Design\OSC_0\Linker_Design_OSC_0_OSC.v|i|1396498752|538
E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v|i|1392095814|6867
E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v|i|1392095814|2175
E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v|i|1392095814|16975
E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v|i|1392095814|14771
E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v|i|1392095814|8597
E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v|i|1392095814|208467
E:\Ranjith\Linker_Design\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v|i|1392095814|21688
E:\Ranjith\Linker_Design\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core\AHBLSramIf.v|i|1390997854|7954
E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v|i|1396498749|128116
E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\usram_128to9216x8.v|i|1396498749|125246
E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v|i|1396498749|15887
E:\Ranjith\Linker_Design\component\work\Linker_Design\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v|i|1396498749|6265
E:\Ranjith\Linker_Design\component\work\Linker_Design\Linker_Design.v|i|1396498752|28190
E:\Ranjith\Linker_Design\synthesis\synthesis_1\Linker_Design.srr|o|1396521847|45979
C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\bin64\c_ver.exe|i|1389638658|5733376
C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\bin\c_ver.exe|i|1389638444|2205696
