//
// Written by Synplify
// Product Version "I-2013.09M-SP1 "
// Program "Synplify Pro", Mapper "mapact, Build 1154R"
// Thu Apr 03 16:14:15 2014
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "\c:\microsemi\libero_v11.3\synopsys\synplify_i201309msp1\lib\generic\smartfusion2.v "
// file 1 "\c:\microsemi\libero_v11.3\synopsys\synplify_i201309msp1\lib\vlog\umr_capim.v "
// file 2 "\c:\microsemi\libero_v11.3\synopsys\synplify_i201309msp1\lib\vlog\scemi_objects.v "
// file 3 "\c:\microsemi\libero_v11.3\synopsys\synplify_i201309msp1\lib\vlog\scemi_pipes.svh "
// file 4 "\c:\microsemi\libero_v11.3\synopsys\synplify_i201309msp1\lib\vlog\hypermods.v "
// file 5 "\e:\ranjith\linker_design\component\work\linker_design\fccc_0\linker_design_fccc_0_fccc.v "
// file 6 "\e:\ranjith\linker_design\component\work\linker_design_mss\linker_design_mss_syn.v "
// file 7 "\e:\ranjith\linker_design\component\work\linker_design_mss\linker_design_mss.v "
// file 8 "\e:\ranjith\linker_design\component\actel\sgcore\osc\1.0.100\osc_comps.v "
// file 9 "\e:\ranjith\linker_design\component\work\linker_design\osc_0\linker_design_osc_0_osc.v "
// file 10 "\e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v "
// file 11 "\e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v "
// file 12 "\e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v "
// file 13 "\e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v "
// file 14 "\e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v "
// file 15 "\e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v "
// file 16 "\e:\ranjith\linker_design\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite.v "
// file 17 "\e:\ranjith\linker_design\component\actel\directcore\coreahblsram\2.0.113\rtl\vlog\core\ahblsramif.v "
// file 18 "\e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\lsram_2048to139264x8.v "
// file 19 "\e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\usram_128to9216x8.v "
// file 20 "\e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\sramctrlif.v "
// file 21 "\e:\ranjith\linker_design\component\work\linker_design\coreahblsram_0\rtl\vlog\core\coreahblsram.v "
// file 22 "\e:\ranjith\linker_design\component\work\linker_design\linker_design.v "
// file 23 "\e:\ranjith\linker_design\synthesis\synthesis_1\linker_design_fsm.sdc "

`timescale 100 ps/100 ps
(* HRESPEXTEND=1 , IDLE=0 *)module COREAHBLITE_DEFAULTSLAVESM_default_slave_sm (
  defSlaveSMCurrentState,
  Linker_Design_MSS_0_MSS_RESET_N_M2F,
  FCCC_0_GL0_0,
  DEFSLAVEDATASEL_10,
  DEFSLAVEDATASEL_11,
  DEFSLAVEDATASEL_9,
  un1_HREADY_M_pre24_1,
  defSlaveSMNextState_m
)
;
output defSlaveSMCurrentState ;
input Linker_Design_MSS_0_MSS_RESET_N_M2F ;
input FCCC_0_GL0_0 ;
input DEFSLAVEDATASEL_10 ;
input DEFSLAVEDATASEL_11 ;
input DEFSLAVEDATASEL_9 ;
input un1_HREADY_M_pre24_1 ;
output defSlaveSMNextState_m ;
wire defSlaveSMCurrentState ;
wire Linker_Design_MSS_0_MSS_RESET_N_M2F ;
wire FCCC_0_GL0_0 ;
wire DEFSLAVEDATASEL_10 ;
wire DEFSLAVEDATASEL_11 ;
wire DEFSLAVEDATASEL_9 ;
wire un1_HREADY_M_pre24_1 ;
wire defSlaveSMNextState_m ;
wire VCC ;
wire defSlaveSMNextState_Z ;
wire GND ;
// @11:66
  SLE defSlaveSMCurrentState_Z (
	.Q(defSlaveSMCurrentState),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(defSlaveSMNextState_Z),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @11:45
  CFG4 defSlaveSMNextState (
	.A(DEFSLAVEDATASEL_10),
	.B(defSlaveSMCurrentState),
	.C(DEFSLAVEDATASEL_11),
	.D(DEFSLAVEDATASEL_9),
	.Y(defSlaveSMNextState_Z)
);
defparam defSlaveSMNextState.INIT=16'h3332;
// @12:254
  CFG2 defSlaveSMCurrentState_RNIMKVA (
	.A(un1_HREADY_M_pre24_1),
	.B(defSlaveSMCurrentState),
	.Y(defSlaveSMNextState_m)
);
defparam defSlaveSMCurrentState_RNIMKVA.INIT=4'h1;
  GND GND_Z (
	.Y(GND)
);
  VCC VCC_Z (
	.Y(VCC)
);
endmodule /* COREAHBLITE_DEFAULTSLAVESM_default_slave_sm */

module COREAHBLITE_MASTERSTAGE_1_1_0_8_0_1_0 (
  regHADDR,
  regHSIZE,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE,
  PREGATEDHADDR,
  M0GATEDHSIZE,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS,
  SADDRSEL_2,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29,
  SADDRSEL_0,
  arbRegSMCurrentState_3,
  arbRegSMCurrentState_0,
  SADDRSEL_1_4,
  SADDRSEL_1_0,
  masterDataInProg,
  Linker_Design_MSS_0_MSS_RESET_N_M2F,
  FCCC_0_GL0_0,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE,
  regHTRANS,
  m0s3DataSel,
  m0s3AddrSel,
  masterRegAddrSel,
  M0GATEDHWRITE,
  HREADY_M_pre24,
  N_156,
  un1_HREADY_M_pre24_1,
  CoreAHBLite_0_AHBmslave3_HREADY,
  un1_HREADY_M_pre24_1_i_0,
  HREADY_M_iv_i_0,
  defSlaveSMCurrentState
)
;
output [15:0] regHADDR ;
output [1:0] regHSIZE ;
input [1:0] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE ;
output [28:28] PREGATEDHADDR ;
output [1:1] M0GATEDHSIZE ;
input [1:1] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS ;
output [2:2] SADDRSEL_2 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29 ;
output [3:3] SADDRSEL_0 ;
input arbRegSMCurrentState_3 ;
input arbRegSMCurrentState_0 ;
output SADDRSEL_1_4 ;
output SADDRSEL_1_0 ;
input [0:0] masterDataInProg ;
input Linker_Design_MSS_0_MSS_RESET_N_M2F ;
input FCCC_0_GL0_0 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE ;
output regHTRANS ;
output m0s3DataSel ;
output m0s3AddrSel ;
output masterRegAddrSel ;
output M0GATEDHWRITE ;
output HREADY_M_pre24 ;
input N_156 ;
output un1_HREADY_M_pre24_1 ;
input CoreAHBLite_0_AHBmslave3_HREADY ;
output un1_HREADY_M_pre24_1_i_0 ;
output HREADY_M_iv_i_0 ;
output defSlaveSMCurrentState ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29 ;
wire arbRegSMCurrentState_3 ;
wire arbRegSMCurrentState_0 ;
wire SADDRSEL_1_4 ;
wire SADDRSEL_1_0 ;
wire Linker_Design_MSS_0_MSS_RESET_N_M2F ;
wire FCCC_0_GL0_0 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE ;
wire regHTRANS ;
wire m0s3DataSel ;
wire m0s3AddrSel ;
wire masterRegAddrSel ;
wire M0GATEDHWRITE ;
wire HREADY_M_pre24 ;
wire N_156 ;
wire un1_HREADY_M_pre24_1 ;
wire CoreAHBLite_0_AHBmslave3_HREADY ;
wire un1_HREADY_M_pre24_1_i_0 ;
wire HREADY_M_iv_i_0 ;
wire defSlaveSMCurrentState ;
wire [15:0] SDATASELInt;
wire [15:0] SADDRSEL;
wire [5:5] SADDRSEL_1;
wire [0:0] SADDRSEL_3_0;
wire [8:8] SADDRSEL_3_1;
wire [15:7] SADDRSEL_3;
wire VCC ;
wire masterAddrClockEnable ;
wire GND ;
wire regHWRITE_Z ;
wire PREVDATASLAVEREADY_iv_i_0 ;
wire d_masterRegAddrSel ;
wire un1_SDATASELInt_29_1_Z ;
wire un1_SDATASELInt_29_11_Z ;
wire un1_SDATASELInt_29_10_Z ;
wire un1_SDATASELInt_29_9_Z ;
wire DEFSLAVEDATASEL_10_Z ;
wire DEFSLAVEDATASEL_9_Z ;
wire DEFSLAVEDATASEL_8_Z ;
wire un1_SDATASELInt_29_12_Z ;
wire DEFSLAVEDATASEL_11_Z ;
wire d_masterRegAddrSel_0_tz ;
wire d_masterRegAddrSel_0_1_Z ;
wire masterAddrClockEnable_0_1_Z ;
wire defSlaveSMNextState_m ;
wire HREADY_M_iv_Z ;
wire masterAddrClockEnable4_0_Z ;
wire N_321 ;
wire N_319 ;
wire N_318 ;
wire N_317 ;
wire N_316 ;
wire N_134 ;
wire N_133 ;
wire N_105 ;
wire N_104 ;
wire N_103 ;
wire N_102 ;
wire N_101 ;
wire N_100 ;
wire N_99 ;
wire N_98 ;
// @12:167
  SLE \regHADDR_Z[0]  (
	.Q(regHADDR[0]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0),
	.EN(masterAddrClockEnable),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:167
  SLE \regHADDR_Z[1]  (
	.Q(regHADDR[1]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1),
	.EN(masterAddrClockEnable),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:167
  SLE \regHADDR_Z[2]  (
	.Q(regHADDR[2]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2),
	.EN(masterAddrClockEnable),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:167
  SLE \regHADDR_Z[3]  (
	.Q(regHADDR[3]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3),
	.EN(masterAddrClockEnable),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:167
  SLE \regHADDR_Z[4]  (
	.Q(regHADDR[4]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4),
	.EN(masterAddrClockEnable),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:167
  SLE \regHADDR_Z[5]  (
	.Q(regHADDR[5]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5),
	.EN(masterAddrClockEnable),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:167
  SLE \regHADDR_Z[6]  (
	.Q(regHADDR[6]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6),
	.EN(masterAddrClockEnable),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:167
  SLE \regHADDR_Z[7]  (
	.Q(regHADDR[7]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7),
	.EN(masterAddrClockEnable),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:167
  SLE \regHADDR_Z[8]  (
	.Q(regHADDR[8]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8),
	.EN(masterAddrClockEnable),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:167
  SLE \regHADDR_Z[9]  (
	.Q(regHADDR[9]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9),
	.EN(masterAddrClockEnable),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:167
  SLE \regHADDR_Z[10]  (
	.Q(regHADDR[10]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10),
	.EN(masterAddrClockEnable),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:167
  SLE \regHADDR_Z[11]  (
	.Q(regHADDR[11]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11),
	.EN(masterAddrClockEnable),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:167
  SLE \regHADDR_Z[12]  (
	.Q(regHADDR[12]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12),
	.EN(masterAddrClockEnable),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:167
  SLE \regHADDR_Z[13]  (
	.Q(regHADDR[13]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13),
	.EN(masterAddrClockEnable),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:167
  SLE \regHADDR_Z[14]  (
	.Q(regHADDR[14]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14),
	.EN(masterAddrClockEnable),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:167
  SLE \regHADDR_Z[15]  (
	.Q(regHADDR[15]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15),
	.EN(masterAddrClockEnable),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:167
  SLE \regHSIZE_Z[0]  (
	.Q(regHSIZE[0]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE[0]),
	.EN(masterAddrClockEnable),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:167
  SLE \regHSIZE_Z[1]  (
	.Q(regHSIZE[1]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE[1]),
	.EN(masterAddrClockEnable),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:167
  SLE regHWRITE (
	.Q(regHWRITE_Z),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE),
	.EN(masterAddrClockEnable),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:167
  SLE regHTRANS_Z (
	.Q(regHTRANS),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(VCC),
	.EN(masterAddrClockEnable),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:233
  SLE \SDATASELInt[0]  (
	.Q(SDATASELInt[0]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(SADDRSEL[0]),
	.EN(PREVDATASLAVEREADY_iv_i_0),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:233
  SLE \SDATASELInt[1]  (
	.Q(SDATASELInt[1]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(SADDRSEL[1]),
	.EN(PREVDATASLAVEREADY_iv_i_0),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:233
  SLE \SDATASELInt[2]  (
	.Q(SDATASELInt[2]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(SADDRSEL[2]),
	.EN(PREVDATASLAVEREADY_iv_i_0),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:233
  SLE \SDATASELInt[3]  (
	.Q(m0s3DataSel),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(m0s3AddrSel),
	.EN(PREVDATASLAVEREADY_iv_i_0),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:233
  SLE \SDATASELInt[4]  (
	.Q(SDATASELInt[4]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(SADDRSEL[4]),
	.EN(PREVDATASLAVEREADY_iv_i_0),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:233
  SLE \SDATASELInt[5]  (
	.Q(SDATASELInt[5]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(SADDRSEL[5]),
	.EN(PREVDATASLAVEREADY_iv_i_0),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:233
  SLE \SDATASELInt[6]  (
	.Q(SDATASELInt[6]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(SADDRSEL[6]),
	.EN(PREVDATASLAVEREADY_iv_i_0),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:233
  SLE \SDATASELInt[7]  (
	.Q(SDATASELInt[7]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(SADDRSEL[7]),
	.EN(PREVDATASLAVEREADY_iv_i_0),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:233
  SLE \SDATASELInt[8]  (
	.Q(SDATASELInt[8]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(SADDRSEL[8]),
	.EN(PREVDATASLAVEREADY_iv_i_0),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:233
  SLE \SDATASELInt[9]  (
	.Q(SDATASELInt[9]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(SADDRSEL[9]),
	.EN(PREVDATASLAVEREADY_iv_i_0),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:233
  SLE \SDATASELInt[10]  (
	.Q(SDATASELInt[10]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(SADDRSEL[10]),
	.EN(PREVDATASLAVEREADY_iv_i_0),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:233
  SLE \SDATASELInt[11]  (
	.Q(SDATASELInt[11]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(SADDRSEL[11]),
	.EN(PREVDATASLAVEREADY_iv_i_0),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:233
  SLE \SDATASELInt[12]  (
	.Q(SDATASELInt[12]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(SADDRSEL[12]),
	.EN(PREVDATASLAVEREADY_iv_i_0),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:233
  SLE \SDATASELInt[13]  (
	.Q(SDATASELInt[13]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(SADDRSEL[13]),
	.EN(PREVDATASLAVEREADY_iv_i_0),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:233
  SLE \SDATASELInt[14]  (
	.Q(SDATASELInt[14]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(SADDRSEL[14]),
	.EN(PREVDATASLAVEREADY_iv_i_0),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:233
  SLE \SDATASELInt[15]  (
	.Q(SDATASELInt[15]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(SADDRSEL[15]),
	.EN(PREVDATASLAVEREADY_iv_i_0),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:629
  SLE masterRegAddrSel_Z (
	.Q(masterRegAddrSel),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(d_masterRegAddrSel),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @12:263
  CFG2 un1_SDATASELInt_29_1 (
	.A(SDATASELInt[6]),
	.B(SDATASELInt[7]),
	.Y(un1_SDATASELInt_29_1_Z)
);
defparam un1_SDATASELInt_29_1.INIT=4'h1;
// @12:191
  CFG3 \PREGATEDHADDR_cZ[28]  (
	.A(masterRegAddrSel),
	.B(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28),
	.C(regHTRANS),
	.Y(PREGATEDHADDR[28])
);
defparam \PREGATEDHADDR_cZ[28] .INIT=8'hE4;
// @12:191
  CFG3 \GATEDHSIZE[1]  (
	.A(masterRegAddrSel),
	.B(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE[1]),
	.C(regHSIZE[1]),
	.Y(M0GATEDHSIZE[1])
);
defparam \GATEDHSIZE[1] .INIT=8'hE4;
// @12:191
  CFG3 GATEDHWRITE (
	.A(masterRegAddrSel),
	.B(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE),
	.C(regHWRITE_Z),
	.Y(M0GATEDHWRITE)
);
defparam GATEDHWRITE.INIT=8'hE4;
// @12:263
  CFG4 un1_SDATASELInt_29_11 (
	.A(SDATASELInt[2]),
	.B(SDATASELInt[1]),
	.C(SDATASELInt[0]),
	.D(m0s3DataSel),
	.Y(un1_SDATASELInt_29_11_Z)
);
defparam un1_SDATASELInt_29_11.INIT=16'h0001;
// @12:263
  CFG4 un1_SDATASELInt_29_10 (
	.A(SDATASELInt[15]),
	.B(SDATASELInt[12]),
	.C(SDATASELInt[10]),
	.D(SDATASELInt[8]),
	.Y(un1_SDATASELInt_29_10_Z)
);
defparam un1_SDATASELInt_29_10.INIT=16'h0001;
// @12:263
  CFG4 un1_SDATASELInt_29_9 (
	.A(SDATASELInt[14]),
	.B(SDATASELInt[13]),
	.C(SDATASELInt[9]),
	.D(SDATASELInt[5]),
	.Y(un1_SDATASELInt_29_9_Z)
);
defparam un1_SDATASELInt_29_9.INIT=16'h0001;
// @12:156
  CFG4 DEFSLAVEDATASEL_10 (
	.A(SDATASELInt[8]),
	.B(SDATASELInt[7]),
	.C(SDATASELInt[6]),
	.D(SDATASELInt[5]),
	.Y(DEFSLAVEDATASEL_10_Z)
);
defparam DEFSLAVEDATASEL_10.INIT=16'hFFFE;
// @12:156
  CFG4 DEFSLAVEDATASEL_9 (
	.A(SDATASELInt[4]),
	.B(SDATASELInt[2]),
	.C(SDATASELInt[1]),
	.D(SDATASELInt[0]),
	.Y(DEFSLAVEDATASEL_9_Z)
);
defparam DEFSLAVEDATASEL_9.INIT=16'hFFFE;
// @12:156
  CFG4 DEFSLAVEDATASEL_8 (
	.A(SDATASELInt[15]),
	.B(SDATASELInt[14]),
	.C(SDATASELInt[13]),
	.D(SDATASELInt[12]),
	.Y(DEFSLAVEDATASEL_8_Z)
);
defparam DEFSLAVEDATASEL_8.INIT=16'hFFFE;
// @12:263
  CFG4 HREADY_M_pre24_c (
	.A(SDATASELInt[2]),
	.B(SDATASELInt[1]),
	.C(SDATASELInt[0]),
	.D(m0s3DataSel),
	.Y(HREADY_M_pre24)
);
defparam HREADY_M_pre24_c.INIT=16'h0100;
// @12:222
  CFG3 \SADDRSEL_1[12]  (
	.A(masterRegAddrSel),
	.B(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS[1]),
	.Y(SADDRSEL_1[5])
);
defparam \SADDRSEL_1[12] .INIT=8'h40;
// @12:222
  CFG3 \SADDRSEL_2[0]  (
	.A(masterRegAddrSel),
	.B(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31),
	.Y(SADDRSEL_2[2])
);
defparam \SADDRSEL_2[0] .INIT=8'hAB;
// @12:222
  CFG3 \SADDRSEL_3_0[0]  (
	.A(masterRegAddrSel),
	.B(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS[1]),
	.Y(SADDRSEL_3_0[0])
);
defparam \SADDRSEL_3_0[0] .INIT=8'h10;
// @12:222
  CFG4 \SADDRSEL_3_1[8]  (
	.A(regHTRANS),
	.B(masterRegAddrSel),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29),
	.Y(SADDRSEL_3_1[8])
);
defparam \SADDRSEL_3_1[8] .INIT=16'h4447;
// @12:222
  CFG4 \SADDRSEL_0_cZ[3]  (
	.A(masterRegAddrSel),
	.B(regHTRANS),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS[1]),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29),
	.Y(SADDRSEL_1_4)
);
defparam \SADDRSEL_0_cZ[3] .INIT=16'hD888;
// @12:222
  CFG4 \SADDRSEL_0_0[3]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31),
	.B(PREGATEDHADDR[28]),
	.C(masterRegAddrSel),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30),
	.Y(SADDRSEL_0[3])
);
defparam \SADDRSEL_0_0[3] .INIT=16'hC0C4;
// @12:263
  CFG4 un1_SDATASELInt_29_12 (
	.A(SDATASELInt[4]),
	.B(SDATASELInt[11]),
	.C(un1_SDATASELInt_29_9_Z),
	.D(un1_SDATASELInt_29_1_Z),
	.Y(un1_SDATASELInt_29_12_Z)
);
defparam un1_SDATASELInt_29_12.INIT=16'h1000;
// @12:156
  CFG4 DEFSLAVEDATASEL_11 (
	.A(SDATASELInt[11]),
	.B(SDATASELInt[10]),
	.C(SDATASELInt[9]),
	.D(DEFSLAVEDATASEL_8_Z),
	.Y(DEFSLAVEDATASEL_11_Z)
);
defparam DEFSLAVEDATASEL_11.INIT=16'hFFFE;
// @12:565
  CFG3 d_masterRegAddrSel_1_tz (
	.A(arbRegSMCurrentState_3),
	.B(arbRegSMCurrentState_0),
	.C(N_156),
	.Y(d_masterRegAddrSel_0_tz)
);
defparam d_masterRegAddrSel_1_tz.INIT=8'h10;
// @12:222
  CFG4 \SADDRSEL_3[8]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS[1]),
	.B(SADDRSEL_3_1[8]),
	.C(masterRegAddrSel),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31),
	.Y(SADDRSEL_3[9])
);
defparam \SADDRSEL_3[8] .INIT=16'h0800;
// @12:222
  CFG4 \SADDRSEL_3[14]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31),
	.B(SADDRSEL_1_4),
	.C(masterRegAddrSel),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30),
	.Y(SADDRSEL_3[15])
);
defparam \SADDRSEL_3[14] .INIT=16'h0800;
// @12:222
  CFG4 \SADDRSEL_3[6]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31),
	.B(SADDRSEL_1_4),
	.C(masterRegAddrSel),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30),
	.Y(SADDRSEL_3[7])
);
defparam \SADDRSEL_3[6] .INIT=16'h0400;
// @12:222
  CFG4 \SADDRSEL_3[10]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31),
	.B(SADDRSEL_1_4),
	.C(masterRegAddrSel),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30),
	.Y(SADDRSEL_3[11])
);
defparam \SADDRSEL_3[10] .INIT=16'h0008;
// @12:222
  CFG2 \SADDRSEL_1[3]  (
	.A(SADDRSEL_1_4),
	.B(PREGATEDHADDR[28]),
	.Y(SADDRSEL_1_0)
);
defparam \SADDRSEL_1[3] .INIT=4'h8;
// @12:222
  CFG3 \SADDRSEL[3]  (
	.A(SADDRSEL_1_4),
	.B(PREGATEDHADDR[28]),
	.C(SADDRSEL_2[2]),
	.Y(m0s3AddrSel)
);
defparam \SADDRSEL[3] .INIT=8'h80;
// @12:222
  CFG3 \SADDRSEL[2]  (
	.A(SADDRSEL_1_4),
	.B(PREGATEDHADDR[28]),
	.C(SADDRSEL_2[2]),
	.Y(SADDRSEL[2])
);
defparam \SADDRSEL[2] .INIT=8'h20;
// @12:222
  CFG4 \SADDRSEL[12]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31),
	.B(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29),
	.C(PREGATEDHADDR[28]),
	.D(SADDRSEL_1[5]),
	.Y(SADDRSEL[12])
);
defparam \SADDRSEL[12] .INIT=16'h0200;
// @12:222
  CFG4 \SADDRSEL[13]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31),
	.B(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29),
	.C(PREGATEDHADDR[28]),
	.D(SADDRSEL_1[5]),
	.Y(SADDRSEL[13])
);
defparam \SADDRSEL[13] .INIT=16'h2000;
// @12:222
  CFG4 \SADDRSEL[4]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31),
	.B(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29),
	.C(PREGATEDHADDR[28]),
	.D(SADDRSEL_1[5]),
	.Y(SADDRSEL[4])
);
defparam \SADDRSEL[4] .INIT=16'h0100;
// @12:222
  CFG4 \SADDRSEL[5]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31),
	.B(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29),
	.C(PREGATEDHADDR[28]),
	.D(SADDRSEL_1[5]),
	.Y(SADDRSEL[5])
);
defparam \SADDRSEL[5] .INIT=16'h1000;
// @12:222
  CFG2 \SADDRSEL[15]  (
	.A(SADDRSEL_3[15]),
	.B(PREGATEDHADDR[28]),
	.Y(SADDRSEL[15])
);
defparam \SADDRSEL[15] .INIT=4'h8;
// @12:222
  CFG2 \SADDRSEL[14]  (
	.A(SADDRSEL_3[15]),
	.B(PREGATEDHADDR[28]),
	.Y(SADDRSEL[14])
);
defparam \SADDRSEL[14] .INIT=4'h2;
// @12:222
  CFG2 \SADDRSEL[9]  (
	.A(SADDRSEL_3[9]),
	.B(PREGATEDHADDR[28]),
	.Y(SADDRSEL[9])
);
defparam \SADDRSEL[9] .INIT=4'h8;
// @12:222
  CFG2 \SADDRSEL[8]  (
	.A(SADDRSEL_3[9]),
	.B(PREGATEDHADDR[28]),
	.Y(SADDRSEL[8])
);
defparam \SADDRSEL[8] .INIT=4'h2;
// @12:222
  CFG2 \SADDRSEL[6]  (
	.A(SADDRSEL_3[7]),
	.B(PREGATEDHADDR[28]),
	.Y(SADDRSEL[6])
);
defparam \SADDRSEL[6] .INIT=4'h2;
// @12:222
  CFG2 \SADDRSEL[7]  (
	.A(SADDRSEL_3[7]),
	.B(PREGATEDHADDR[28]),
	.Y(SADDRSEL[7])
);
defparam \SADDRSEL[7] .INIT=4'h8;
// @12:222
  CFG2 \SADDRSEL[10]  (
	.A(SADDRSEL_3[11]),
	.B(PREGATEDHADDR[28]),
	.Y(SADDRSEL[10])
);
defparam \SADDRSEL[10] .INIT=4'h2;
// @12:222
  CFG2 \SADDRSEL[11]  (
	.A(SADDRSEL_3[11]),
	.B(PREGATEDHADDR[28]),
	.Y(SADDRSEL[11])
);
defparam \SADDRSEL[11] .INIT=4'h8;
// @12:222
  CFG3 \SADDRSEL[0]  (
	.A(SADDRSEL_2[2]),
	.B(SADDRSEL_3_0[0]),
	.C(PREGATEDHADDR[28]),
	.Y(SADDRSEL[0])
);
defparam \SADDRSEL[0] .INIT=8'h08;
// @12:222
  CFG3 \SADDRSEL[1]  (
	.A(SADDRSEL_2[2]),
	.B(SADDRSEL_3_0[0]),
	.C(PREGATEDHADDR[28]),
	.Y(SADDRSEL[1])
);
defparam \SADDRSEL[1] .INIT=8'h80;
// @12:262
  CFG4 un1_HREADY_M_pre24_1_c (
	.A(HREADY_M_pre24),
	.B(un1_SDATASELInt_29_12_Z),
	.C(un1_SDATASELInt_29_10_Z),
	.D(un1_SDATASELInt_29_11_Z),
	.Y(un1_HREADY_M_pre24_1)
);
defparam un1_HREADY_M_pre24_1_c.INIT=16'hEAAA;
// @12:565
  CFG4 d_masterRegAddrSel_0_1 (
	.A(d_masterRegAddrSel_0_tz),
	.B(CoreAHBLite_0_AHBmslave3_HREADY),
	.C(SADDRSEL_2[2]),
	.D(PREGATEDHADDR[28]),
	.Y(d_masterRegAddrSel_0_1_Z)
);
defparam d_masterRegAddrSel_0_1.INIT=16'hB000;
// @12:565
  CFG4 masterAddrClockEnable_0_1 (
	.A(CoreAHBLite_0_AHBmslave3_HREADY),
	.B(masterRegAddrSel),
	.C(PREGATEDHADDR[28]),
	.D(d_masterRegAddrSel_0_tz),
	.Y(masterAddrClockEnable_0_1_Z)
);
defparam masterAddrClockEnable_0_1.INIT=16'h3010;
// @12:254
  CFG4 un1_SDATASELInt_29_10_RNIB9121 (
	.A(HREADY_M_pre24),
	.B(un1_SDATASELInt_29_12_Z),
	.C(un1_SDATASELInt_29_10_Z),
	.D(un1_SDATASELInt_29_11_Z),
	.Y(un1_HREADY_M_pre24_1_i_0)
);
defparam un1_SDATASELInt_29_10_RNIB9121.INIT=16'h1555;
// @12:254
  CFG4 HREADY_M_iv (
	.A(masterDataInProg[0]),
	.B(CoreAHBLite_0_AHBmslave3_HREADY),
	.C(HREADY_M_pre24),
	.D(defSlaveSMNextState_m),
	.Y(HREADY_M_iv_Z)
);
defparam HREADY_M_iv.INIT=16'hFF70;
// @12:568
  CFG2 masterAddrClockEnable4_0 (
	.A(HREADY_M_iv_Z),
	.B(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS[1]),
	.Y(masterAddrClockEnable4_0_Z)
);
defparam masterAddrClockEnable4_0.INIT=4'h4;
// @12:568
  CFG4 HREADY_M_pre24_RNIJ6VG1 (
	.A(masterDataInProg[0]),
	.B(CoreAHBLite_0_AHBmslave3_HREADY),
	.C(HREADY_M_pre24),
	.D(defSlaveSMNextState_m),
	.Y(HREADY_M_iv_i_0)
);
defparam HREADY_M_pre24_RNIJ6VG1.INIT=16'h008F;
// @12:233
  CFG3 HREADY_M_pre24_RNIIG041 (
	.A(defSlaveSMNextState_m),
	.B(CoreAHBLite_0_AHBmslave3_HREADY),
	.C(HREADY_M_pre24),
	.Y(PREVDATASLAVEREADY_iv_i_0)
);
defparam HREADY_M_pre24_RNIIG041.INIT=8'h45;
// @12:565
  CFG4 masterAddrClockEnable_0 (
	.A(SADDRSEL_1_4),
	.B(SADDRSEL_2[2]),
	.C(masterAddrClockEnable_0_1_Z),
	.D(masterAddrClockEnable4_0_Z),
	.Y(masterAddrClockEnable)
);
defparam masterAddrClockEnable_0.INIT=16'h8000;
// @12:565
  CFG4 d_masterRegAddrSel_0 (
	.A(masterAddrClockEnable4_0_Z),
	.B(d_masterRegAddrSel_0_1_Z),
	.C(masterRegAddrSel),
	.D(SADDRSEL_1_4),
	.Y(d_masterRegAddrSel)
);
defparam d_masterRegAddrSel_0.INIT=16'hC800;
// @12:642
  COREAHBLITE_DEFAULTSLAVESM_default_slave_sm default_slave_sm (
	.defSlaveSMCurrentState(defSlaveSMCurrentState),
	.Linker_Design_MSS_0_MSS_RESET_N_M2F(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.FCCC_0_GL0_0(FCCC_0_GL0_0),
	.DEFSLAVEDATASEL_10(DEFSLAVEDATASEL_10_Z),
	.DEFSLAVEDATASEL_11(DEFSLAVEDATASEL_11_Z),
	.DEFSLAVEDATASEL_9(DEFSLAVEDATASEL_9_Z),
	.un1_HREADY_M_pre24_1(un1_HREADY_M_pre24_1),
	.defSlaveSMNextState_m(defSlaveSMNextState_m)
);
  GND GND_Z (
	.Y(GND)
);
  VCC VCC_Z (
	.Y(VCC)
);
endmodule /* COREAHBLITE_MASTERSTAGE_1_1_0_8_0_1_0 */

(* MASTER_NONE=0 , MASTER_3=8 , MASTER_2=4 , MASTER_1=2 , MASTER_0=1 , M3LOCKEXTEND=15 , M3LOCK=14 , M3DONE=13 , M3EXTEND=12 , M2LOCKEXTEND=11 , M2LOCK=10 , M2DONE=9 , M2EXTEND=8 , M1LOCKEXTEND=7 , M1LOCK=6 , M1DONE=5 , M1EXTEND=4 , M0LOCKEXTEND=3 , M0LOCK=2 , M0DONE=1 , M0EXTEND=0 *)module COREAHBLITE_SLAVEARBITER_slave_arbiter_0 (
  arbRegSMCurrentState_0,
  arbRegSMCurrentState_3,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR,
  MASTERADDRINPROG_i_a2_d_c_c,
  SADDRSEL_2,
  MASTERADDRINPROG_i_a2_c,
  regHSIZE,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE,
  MASTERADDRINPROG_i_a2_0_0_0_0,
  M0GATEDHSIZE,
  SADDRSEL_1_0,
  SADDRSEL_1_4,
  SADDRSEL_0,
  CoreAHBLite_0_AHBmslave3_HSIZE,
  Linker_Design_MSS_0_MSS_RESET_N_M2F,
  FCCC_0_GL0_0,
  CoreAHBLite_0_AHBmslave3_HREADY,
  m0s3AddrSel,
  N_156,
  masterRegAddrSel,
  N_152,
  N_152_i_0
)
;
output arbRegSMCurrentState_0 ;
output arbRegSMCurrentState_3 ;
input [31:30] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR ;
output [0:0] MASTERADDRINPROG_i_a2_d_c_c ;
input [2:2] SADDRSEL_2 ;
output [0:0] MASTERADDRINPROG_i_a2_c ;
input [0:0] regHSIZE ;
input [0:0] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE ;
output [0:0] MASTERADDRINPROG_i_a2_0_0_0_0 ;
input [1:1] M0GATEDHSIZE ;
input SADDRSEL_1_0 ;
input SADDRSEL_1_4 ;
input [3:3] SADDRSEL_0 ;
output [1:0] CoreAHBLite_0_AHBmslave3_HSIZE ;
input Linker_Design_MSS_0_MSS_RESET_N_M2F ;
input FCCC_0_GL0_0 ;
input CoreAHBLite_0_AHBmslave3_HREADY ;
input m0s3AddrSel ;
output N_156 ;
input masterRegAddrSel ;
output N_152 ;
output N_152_i_0 ;
wire arbRegSMCurrentState_0 ;
wire arbRegSMCurrentState_3 ;
wire SADDRSEL_1_0 ;
wire SADDRSEL_1_4 ;
wire Linker_Design_MSS_0_MSS_RESET_N_M2F ;
wire FCCC_0_GL0_0 ;
wire CoreAHBLite_0_AHBmslave3_HREADY ;
wire m0s3AddrSel ;
wire N_156 ;
wire masterRegAddrSel ;
wire N_152 ;
wire N_152_i_0 ;
wire [14:1] arbRegSMCurrentState;
wire [3:2] masterAddrInProg;
wire [13:5] arbRegSMCurrentState_ns;
wire [0:0] MASTERADDRINPROG_i_a2_d_c_d;
wire [0:0] MASTERADDRINPROG_i_a2_d_0_c;
wire [0:0] MASTERADDRINPROG_i_a2_d_d;
wire VCC ;
wire N_126_i_0 ;
wire GND ;
wire N_128_i_0 ;
wire N_104_i_0 ;
wire N_106_i_0 ;
wire N_108_i_0 ;
wire N_110_i_0 ;
wire N_114_i_0 ;
wire HSEL8_sn ;
wire N_116_i_0 ;
wire N_120_i_0 ;
wire N_122_i_0 ;
wire N_106_i_1 ;
wire N_157 ;
wire N_45 ;
wire N_44 ;
wire N_43 ;
wire N_42 ;
wire N_41 ;
wire N_40 ;
wire N_39 ;
wire N_38 ;
wire N_37 ;
wire N_36 ;
wire N_35 ;
wire N_34 ;
wire N_33 ;
wire N_32 ;
wire N_31 ;
wire N_30 ;
// @13:452
  SLE \arbRegSMCurrentState[14]  (
	.Q(arbRegSMCurrentState[14]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(N_126_i_0),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @13:452
  SLE \arbRegSMCurrentState[15]  (
	.Q(masterAddrInProg[3]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(N_128_i_0),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @13:452
  SLE \arbRegSMCurrentState[0]  (
	.Q(arbRegSMCurrentState_0),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(N_104_i_0),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @13:452
  SLE \arbRegSMCurrentState[1]  (
	.Q(arbRegSMCurrentState[1]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(N_106_i_0),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @13:452
  SLE \arbRegSMCurrentState[2]  (
	.Q(arbRegSMCurrentState[2]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(N_108_i_0),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @13:452
  SLE \arbRegSMCurrentState[3]  (
	.Q(arbRegSMCurrentState_3),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(N_110_i_0),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @13:452
  SLE \arbRegSMCurrentState[5]  (
	.Q(arbRegSMCurrentState[5]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(arbRegSMCurrentState_ns[5]),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @13:452
  SLE \arbRegSMCurrentState[6]  (
	.Q(arbRegSMCurrentState[6]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(N_114_i_0),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @13:452
  SLE \arbRegSMCurrentState[7]  (
	.Q(HSEL8_sn),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(N_116_i_0),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @13:452
  SLE \arbRegSMCurrentState[9]  (
	.Q(arbRegSMCurrentState[9]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(arbRegSMCurrentState_ns[9]),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @13:452
  SLE \arbRegSMCurrentState[10]  (
	.Q(arbRegSMCurrentState[10]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(N_120_i_0),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @13:452
  SLE \arbRegSMCurrentState[11]  (
	.Q(masterAddrInProg[2]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(N_122_i_0),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @13:452
  SLE \arbRegSMCurrentState[13]  (
	.Q(arbRegSMCurrentState[13]),
	.ADn(GND),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(arbRegSMCurrentState_ns[13]),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @13:452
  CFG4 \arbRegSMCurrentState_RNO[1]  (
	.A(CoreAHBLite_0_AHBmslave3_HREADY),
	.B(N_106_i_1),
	.C(arbRegSMCurrentState[2]),
	.D(arbRegSMCurrentState[1]),
	.Y(N_106_i_0)
);
defparam \arbRegSMCurrentState_RNO[1] .INIT=16'hFEF2;
// @13:452
  CFG4 \arbRegSMCurrentState_RNO_0[1]  (
	.A(CoreAHBLite_0_AHBmslave3_HREADY),
	.B(m0s3AddrSel),
	.C(arbRegSMCurrentState_0),
	.D(N_157),
	.Y(N_106_i_1)
);
defparam \arbRegSMCurrentState_RNO_0[1] .INIT=16'h1B13;
// @13:452
  CFG4 \arbRegSMCurrentState_ns_i_a2_0[0]  (
	.A(arbRegSMCurrentState[9]),
	.B(arbRegSMCurrentState[5]),
	.C(arbRegSMCurrentState[1]),
	.D(arbRegSMCurrentState[13]),
	.Y(N_156)
);
defparam \arbRegSMCurrentState_ns_i_a2_0[0] .INIT=16'h0001;
// @13:452
  CFG3 \arbRegSMCurrentState_ns_i_a2_1[1]  (
	.A(arbRegSMCurrentState[13]),
	.B(arbRegSMCurrentState[9]),
	.C(arbRegSMCurrentState[5]),
	.Y(N_157)
);
defparam \arbRegSMCurrentState_ns_i_a2_1[1] .INIT=8'h01;
// @13:67
  CFG4 \MASTERADDRINPROG_i_a2_d_c_d[0]  (
	.A(masterRegAddrSel),
	.B(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[31]),
	.C(arbRegSMCurrentState_3),
	.D(arbRegSMCurrentState_0),
	.Y(MASTERADDRINPROG_i_a2_d_c_d[0])
);
defparam \MASTERADDRINPROG_i_a2_d_c_d[0] .INIT=16'hFFFB;
// @13:67
  CFG4 \MASTERADDRINPROG_i_a2_d_c_c_cZ[0]  (
	.A(masterRegAddrSel),
	.B(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[30]),
	.C(arbRegSMCurrentState_3),
	.D(arbRegSMCurrentState_0),
	.Y(MASTERADDRINPROG_i_a2_d_c_c[0])
);
defparam \MASTERADDRINPROG_i_a2_d_c_c_cZ[0] .INIT=16'hFFFB;
// @13:67
  CFG3 \MASTERADDRINPROG_i_a2_d_0_c[0]  (
	.A(arbRegSMCurrentState_3),
	.B(arbRegSMCurrentState_0),
	.C(SADDRSEL_2[2]),
	.Y(MASTERADDRINPROG_i_a2_d_0_c[0])
);
defparam \MASTERADDRINPROG_i_a2_d_0_c[0] .INIT=8'hFE;
// @13:67
  CFG3 \MASTERADDRINPROG_i_a2_c_cZ[0]  (
	.A(arbRegSMCurrentState_3),
	.B(arbRegSMCurrentState_0),
	.C(N_156),
	.Y(MASTERADDRINPROG_i_a2_c[0])
);
defparam \MASTERADDRINPROG_i_a2_c_cZ[0] .INIT=8'hEF;
// @13:452
  CFG2 \arbRegSMCurrentState_RNO[11]  (
	.A(CoreAHBLite_0_AHBmslave3_HREADY),
	.B(masterAddrInProg[2]),
	.Y(N_122_i_0)
);
defparam \arbRegSMCurrentState_RNO[11] .INIT=4'h4;
// @13:452
  CFG2 \arbRegSMCurrentState_RNO[10]  (
	.A(CoreAHBLite_0_AHBmslave3_HREADY),
	.B(masterAddrInProg[2]),
	.Y(N_120_i_0)
);
defparam \arbRegSMCurrentState_RNO[10] .INIT=4'h8;
// @13:452
  CFG2 \arbRegSMCurrentState_RNO[7]  (
	.A(CoreAHBLite_0_AHBmslave3_HREADY),
	.B(HSEL8_sn),
	.Y(N_116_i_0)
);
defparam \arbRegSMCurrentState_RNO[7] .INIT=4'h4;
// @13:452
  CFG2 \arbRegSMCurrentState_RNO[6]  (
	.A(CoreAHBLite_0_AHBmslave3_HREADY),
	.B(HSEL8_sn),
	.Y(N_114_i_0)
);
defparam \arbRegSMCurrentState_RNO[6] .INIT=4'h8;
// @13:452
  CFG2 \arbRegSMCurrentState_RNO[3]  (
	.A(CoreAHBLite_0_AHBmslave3_HREADY),
	.B(arbRegSMCurrentState_3),
	.Y(N_110_i_0)
);
defparam \arbRegSMCurrentState_RNO[3] .INIT=4'h4;
// @13:452
  CFG2 \arbRegSMCurrentState_RNO[2]  (
	.A(CoreAHBLite_0_AHBmslave3_HREADY),
	.B(arbRegSMCurrentState_3),
	.Y(N_108_i_0)
);
defparam \arbRegSMCurrentState_RNO[2] .INIT=4'h8;
// @13:452
  CFG2 \arbRegSMCurrentState_RNO[15]  (
	.A(CoreAHBLite_0_AHBmslave3_HREADY),
	.B(masterAddrInProg[3]),
	.Y(N_128_i_0)
);
defparam \arbRegSMCurrentState_RNO[15] .INIT=4'h4;
// @13:452
  CFG2 \arbRegSMCurrentState_RNO[14]  (
	.A(CoreAHBLite_0_AHBmslave3_HREADY),
	.B(masterAddrInProg[3]),
	.Y(N_126_i_0)
);
defparam \arbRegSMCurrentState_RNO[14] .INIT=4'h8;
// @13:67
  CFG4 \MASTERADDRINPROG_i_a2_0_0_0_0_cZ[0]  (
	.A(masterRegAddrSel),
	.B(regHSIZE[0]),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE[0]),
	.D(MASTERADDRINPROG_i_a2_c[0]),
	.Y(MASTERADDRINPROG_i_a2_0_0_0_0[0])
);
defparam \MASTERADDRINPROG_i_a2_0_0_0_0_cZ[0] .INIT=16'hD800;
// @13:67
  CFG3 \MASTERADDRINPROG_i_a2_d_0_d[0]  (
	.A(arbRegSMCurrentState_3),
	.B(arbRegSMCurrentState_0),
	.C(SADDRSEL_1_0),
	.Y(MASTERADDRINPROG_i_a2_d_d[0])
);
defparam \MASTERADDRINPROG_i_a2_d_0_d[0] .INIT=8'hFE;
// @14:104
  CFG4 \MASTERADDRINPROG_i_a2_d_0_c_RNIL1R51[0]  (
	.A(M0GATEDHSIZE[1]),
	.B(MASTERADDRINPROG_i_a2_c[0]),
	.C(MASTERADDRINPROG_i_a2_d_d[0]),
	.D(MASTERADDRINPROG_i_a2_d_0_c[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HSIZE[1])
);
defparam \MASTERADDRINPROG_i_a2_d_0_c_RNIL1R51[0] .INIT=16'h8000;
// @13:67
  CFG4 \MASTERADDRINPROG_i_a2[0]  (
	.A(arbRegSMCurrentState_3),
	.B(arbRegSMCurrentState_0),
	.C(N_156),
	.D(m0s3AddrSel),
	.Y(N_152)
);
defparam \MASTERADDRINPROG_i_a2[0] .INIT=16'h1011;
// @13:452
  CFG4 \arbRegSMCurrentState_ns[13]  (
	.A(arbRegSMCurrentState[14]),
	.B(arbRegSMCurrentState[13]),
	.C(SADDRSEL_1_4),
	.D(SADDRSEL_0[3]),
	.Y(arbRegSMCurrentState_ns[13])
);
defparam \arbRegSMCurrentState_ns[13] .INIT=16'hAEEE;
// @13:452
  CFG4 \arbRegSMCurrentState_ns[9]  (
	.A(arbRegSMCurrentState[10]),
	.B(arbRegSMCurrentState[9]),
	.C(SADDRSEL_1_4),
	.D(SADDRSEL_0[3]),
	.Y(arbRegSMCurrentState_ns[9])
);
defparam \arbRegSMCurrentState_ns[9] .INIT=16'hAEEE;
// @13:452
  CFG4 \arbRegSMCurrentState_ns[5]  (
	.A(arbRegSMCurrentState[6]),
	.B(arbRegSMCurrentState[5]),
	.C(SADDRSEL_1_4),
	.D(SADDRSEL_0[3]),
	.Y(arbRegSMCurrentState_ns[5])
);
defparam \arbRegSMCurrentState_ns[5] .INIT=16'hAEEE;
// @14:104
  CFG4 \MASTERADDRINPROG_i_a2_d_c_d_RNIK7E71[0]  (
	.A(MASTERADDRINPROG_i_a2_0_0_0_0[0]),
	.B(MASTERADDRINPROG_i_a2_d_d[0]),
	.C(MASTERADDRINPROG_i_a2_d_c_d[0]),
	.D(MASTERADDRINPROG_i_a2_d_c_c[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HSIZE[0])
);
defparam \MASTERADDRINPROG_i_a2_d_c_d_RNIK7E71[0] .INIT=16'h8000;
// @17:185
  CFG4 \arbRegSMCurrentState_ns_i_a2_0_RNINH3C1[0]  (
	.A(arbRegSMCurrentState_3),
	.B(arbRegSMCurrentState_0),
	.C(N_156),
	.D(m0s3AddrSel),
	.Y(N_152_i_0)
);
defparam \arbRegSMCurrentState_ns_i_a2_0_RNINH3C1[0] .INIT=16'hEFEE;
// @13:452
  CFG4 \arbRegSMCurrentState_RNO[0]  (
	.A(CoreAHBLite_0_AHBmslave3_HREADY),
	.B(m0s3AddrSel),
	.C(arbRegSMCurrentState_0),
	.D(N_156),
	.Y(N_104_i_0)
);
defparam \arbRegSMCurrentState_RNO[0] .INIT=16'h5054;
//@13:452
  GND GND_Z (
	.Y(GND)
);
  VCC VCC_Z (
	.Y(VCC)
);
endmodule /* COREAHBLITE_SLAVEARBITER_slave_arbiter_0 */

(* MASTER_NONE=0 , TRN_IDLE=0 *)module COREAHBLITE_SLAVESTAGE_slavestage_3 (
  masterDataInProg,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA,
  CoreAHBLite_0_AHBmslave3_HWDATA,
  SADDRSEL_2,
  arbRegSMCurrentState_3,
  arbRegSMCurrentState_0,
  regHADDR,
  CoreAHBLite_0_AHBmslave3_HADDR,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31,
  MASTERADDRINPROG_i_a2_d_c_c,
  MASTERADDRINPROG_i_a2_c,
  regHSIZE,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE,
  MASTERADDRINPROG_i_a2_0_0_0_0,
  M0GATEDHSIZE,
  SADDRSEL_1_4,
  SADDRSEL_1_0,
  SADDRSEL_0,
  CoreAHBLite_0_AHBmslave3_HSIZE,
  Linker_Design_MSS_0_MSS_RESET_N_M2F,
  FCCC_0_GL0_0,
  CoreAHBLite_0_AHBmslave3_HREADY,
  masterRegAddrSel,
  regHTRANS,
  N_156,
  M0GATEDHWRITE,
  CoreAHBLite_0_AHBmslave3_HWRITE,
  m0s3DataSel,
  un1_HREADY_M_pre24_1,
  defSlaveSMCurrentState,
  N_152,
  HTRANS_0,
  m0s3AddrSel
)
;
output [0:0] masterDataInProg ;
input [31:0] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA ;
output [31:0] CoreAHBLite_0_AHBmslave3_HWDATA ;
input [2:2] SADDRSEL_2 ;
output arbRegSMCurrentState_3 ;
output arbRegSMCurrentState_0 ;
input [15:0] regHADDR ;
output [15:0] CoreAHBLite_0_AHBmslave3_HADDR ;
input [1:1] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31 ;
output [0:0] MASTERADDRINPROG_i_a2_d_c_c ;
output [0:0] MASTERADDRINPROG_i_a2_c ;
input [0:0] regHSIZE ;
input [0:0] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE ;
output [0:0] MASTERADDRINPROG_i_a2_0_0_0_0 ;
input [1:1] M0GATEDHSIZE ;
input SADDRSEL_1_4 ;
input SADDRSEL_1_0 ;
input [3:3] SADDRSEL_0 ;
output [1:0] CoreAHBLite_0_AHBmslave3_HSIZE ;
input Linker_Design_MSS_0_MSS_RESET_N_M2F ;
input FCCC_0_GL0_0 ;
input CoreAHBLite_0_AHBmslave3_HREADY ;
input masterRegAddrSel ;
input regHTRANS ;
output N_156 ;
input M0GATEDHWRITE ;
output CoreAHBLite_0_AHBmslave3_HWRITE ;
input m0s3DataSel ;
input un1_HREADY_M_pre24_1 ;
input defSlaveSMCurrentState ;
output N_152 ;
output HTRANS_0 ;
input m0s3AddrSel ;
wire arbRegSMCurrentState_3 ;
wire arbRegSMCurrentState_0 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31 ;
wire SADDRSEL_1_4 ;
wire SADDRSEL_1_0 ;
wire Linker_Design_MSS_0_MSS_RESET_N_M2F ;
wire FCCC_0_GL0_0 ;
wire CoreAHBLite_0_AHBmslave3_HREADY ;
wire masterRegAddrSel ;
wire regHTRANS ;
wire N_156 ;
wire M0GATEDHWRITE ;
wire CoreAHBLite_0_AHBmslave3_HWRITE ;
wire m0s3DataSel ;
wire un1_HREADY_M_pre24_1 ;
wire defSlaveSMCurrentState ;
wire N_152 ;
wire HTRANS_0 ;
wire m0s3AddrSel ;
wire VCC ;
wire N_152_i_0 ;
wire GND ;
wire HWRITE_a0_0_Z ;
wire HWRITE_a0_Z ;
wire un1_HTRANS_Z ;
wire N_119 ;
wire N_118 ;
wire N_117 ;
// @14:82
  SLE \masterDataInProg_Z[0]  (
	.Q(masterDataInProg[0]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(N_152_i_0),
	.EN(CoreAHBLite_0_AHBmslave3_HREADY),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @14:162
  CFG2 \HWDATA[0]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[0]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[0])
);
defparam \HWDATA[0] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[1]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[1]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[1])
);
defparam \HWDATA[1] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[2]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[2]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[2])
);
defparam \HWDATA[2] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[3]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[3]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[3])
);
defparam \HWDATA[3] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[4]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[4]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[4])
);
defparam \HWDATA[4] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[5]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[5]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[5])
);
defparam \HWDATA[5] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[6]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[6]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[6])
);
defparam \HWDATA[6] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[7]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[7]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[7])
);
defparam \HWDATA[7] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[8]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[8]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[8])
);
defparam \HWDATA[8] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[9]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[9]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[9])
);
defparam \HWDATA[9] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[10]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[10]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[10])
);
defparam \HWDATA[10] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[11]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[11]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[11])
);
defparam \HWDATA[11] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[12]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[12]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[12])
);
defparam \HWDATA[12] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[13]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[13]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[13])
);
defparam \HWDATA[13] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[14]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[14]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[14])
);
defparam \HWDATA[14] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[15]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[15]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[15])
);
defparam \HWDATA[15] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[16]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[16]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[16])
);
defparam \HWDATA[16] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[17]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[17]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[17])
);
defparam \HWDATA[17] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[18]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[18]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[18])
);
defparam \HWDATA[18] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[19]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[19]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[19])
);
defparam \HWDATA[19] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[20]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[20]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[20])
);
defparam \HWDATA[20] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[21]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[21]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[21])
);
defparam \HWDATA[21] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[22]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[22]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[22])
);
defparam \HWDATA[22] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[23]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[23]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[23])
);
defparam \HWDATA[23] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[24]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[24]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[24])
);
defparam \HWDATA[24] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[25]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[25]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[25])
);
defparam \HWDATA[25] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[26]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[26]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[26])
);
defparam \HWDATA[26] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[27]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[27]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[27])
);
defparam \HWDATA[27] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[28]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[28]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[28])
);
defparam \HWDATA[28] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[29]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[29]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[29])
);
defparam \HWDATA[29] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[30]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[30]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[30])
);
defparam \HWDATA[30] .INIT=4'h8;
// @14:162
  CFG2 \HWDATA[31]  (
	.A(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[31]),
	.B(masterDataInProg[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HWDATA[31])
);
defparam \HWDATA[31] .INIT=4'h8;
// @14:104
  CFG4 HWRITE_a0_0 (
	.A(masterRegAddrSel),
	.B(regHTRANS),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28),
	.D(N_156),
	.Y(HWRITE_a0_0_Z)
);
defparam HWRITE_a0_0.INIT=16'h00D8;
// @14:104
  CFG4 HWRITE_a0 (
	.A(SADDRSEL_2[2]),
	.B(SADDRSEL_1_4),
	.C(HWRITE_a0_0_Z),
	.D(M0GATEDHWRITE),
	.Y(HWRITE_a0_Z)
);
defparam HWRITE_a0.INIT=16'h8000;
// @14:104
  CFG4 HWRITE_0 (
	.A(M0GATEDHWRITE),
	.B(HWRITE_a0_Z),
	.C(arbRegSMCurrentState_3),
	.D(arbRegSMCurrentState_0),
	.Y(CoreAHBLite_0_AHBmslave3_HWRITE)
);
defparam HWRITE_0.INIT=16'hEEEC;
// @14:158
  CFG3 un1_HTRANS (
	.A(m0s3DataSel),
	.B(un1_HREADY_M_pre24_1),
	.C(defSlaveSMCurrentState),
	.Y(un1_HTRANS_Z)
);
defparam un1_HTRANS.INIT=8'hFE;
// @14:104
  CFG4 \HADDR[0]  (
	.A(regHADDR[0]),
	.B(masterRegAddrSel),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0),
	.D(N_152),
	.Y(CoreAHBLite_0_AHBmslave3_HADDR[0])
);
defparam \HADDR[0] .INIT=16'h00B8;
// @14:104
  CFG4 \HADDR[1]  (
	.A(regHADDR[1]),
	.B(masterRegAddrSel),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1),
	.D(N_152),
	.Y(CoreAHBLite_0_AHBmslave3_HADDR[1])
);
defparam \HADDR[1] .INIT=16'h00B8;
// @14:104
  CFG4 \HADDR[2]  (
	.A(regHADDR[2]),
	.B(masterRegAddrSel),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2),
	.D(N_152),
	.Y(CoreAHBLite_0_AHBmslave3_HADDR[2])
);
defparam \HADDR[2] .INIT=16'h00B8;
// @14:104
  CFG4 \HADDR[3]  (
	.A(regHADDR[3]),
	.B(masterRegAddrSel),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3),
	.D(N_152),
	.Y(CoreAHBLite_0_AHBmslave3_HADDR[3])
);
defparam \HADDR[3] .INIT=16'h00B8;
// @14:104
  CFG4 \HADDR[4]  (
	.A(regHADDR[4]),
	.B(masterRegAddrSel),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4),
	.D(N_152),
	.Y(CoreAHBLite_0_AHBmslave3_HADDR[4])
);
defparam \HADDR[4] .INIT=16'h00B8;
// @14:104
  CFG4 \HADDR[5]  (
	.A(regHADDR[5]),
	.B(masterRegAddrSel),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5),
	.D(N_152),
	.Y(CoreAHBLite_0_AHBmslave3_HADDR[5])
);
defparam \HADDR[5] .INIT=16'h00B8;
// @14:104
  CFG4 \HADDR[6]  (
	.A(regHADDR[6]),
	.B(masterRegAddrSel),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6),
	.D(N_152),
	.Y(CoreAHBLite_0_AHBmslave3_HADDR[6])
);
defparam \HADDR[6] .INIT=16'h00B8;
// @14:104
  CFG4 \HADDR[7]  (
	.A(regHADDR[7]),
	.B(masterRegAddrSel),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7),
	.D(N_152),
	.Y(CoreAHBLite_0_AHBmslave3_HADDR[7])
);
defparam \HADDR[7] .INIT=16'h00B8;
// @14:104
  CFG4 \HADDR[8]  (
	.A(regHADDR[8]),
	.B(masterRegAddrSel),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8),
	.D(N_152),
	.Y(CoreAHBLite_0_AHBmslave3_HADDR[8])
);
defparam \HADDR[8] .INIT=16'h00B8;
// @14:104
  CFG4 \HADDR[9]  (
	.A(regHADDR[9]),
	.B(masterRegAddrSel),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9),
	.D(N_152),
	.Y(CoreAHBLite_0_AHBmslave3_HADDR[9])
);
defparam \HADDR[9] .INIT=16'h00B8;
// @14:104
  CFG4 \HADDR[10]  (
	.A(regHADDR[10]),
	.B(masterRegAddrSel),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10),
	.D(N_152),
	.Y(CoreAHBLite_0_AHBmslave3_HADDR[10])
);
defparam \HADDR[10] .INIT=16'h00B8;
// @14:104
  CFG4 \HADDR[11]  (
	.A(regHADDR[11]),
	.B(masterRegAddrSel),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11),
	.D(N_152),
	.Y(CoreAHBLite_0_AHBmslave3_HADDR[11])
);
defparam \HADDR[11] .INIT=16'h00B8;
// @14:104
  CFG4 \HADDR[12]  (
	.A(regHADDR[12]),
	.B(masterRegAddrSel),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12),
	.D(N_152),
	.Y(CoreAHBLite_0_AHBmslave3_HADDR[12])
);
defparam \HADDR[12] .INIT=16'h00B8;
// @14:104
  CFG4 \HADDR[13]  (
	.A(regHADDR[13]),
	.B(masterRegAddrSel),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13),
	.D(N_152),
	.Y(CoreAHBLite_0_AHBmslave3_HADDR[13])
);
defparam \HADDR[13] .INIT=16'h00B8;
// @14:104
  CFG4 \HADDR[14]  (
	.A(regHADDR[14]),
	.B(masterRegAddrSel),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14),
	.D(N_152),
	.Y(CoreAHBLite_0_AHBmslave3_HADDR[14])
);
defparam \HADDR[14] .INIT=16'h00B8;
// @14:104
  CFG4 \HADDR[15]  (
	.A(regHADDR[15]),
	.B(masterRegAddrSel),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15),
	.D(N_152),
	.Y(CoreAHBLite_0_AHBmslave3_HADDR[15])
);
defparam \HADDR[15] .INIT=16'h00B8;
// @14:158
  CFG4 HTRANS_0_c (
	.A(masterRegAddrSel),
	.B(regHTRANS),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS[1]),
	.D(un1_HTRANS_Z),
	.Y(HTRANS_0)
);
defparam HTRANS_0_c.INIT=16'hD800;
// @14:90
  COREAHBLITE_SLAVEARBITER_slave_arbiter_0 slave_arbiter (
	.arbRegSMCurrentState_0(arbRegSMCurrentState_0),
	.arbRegSMCurrentState_3(arbRegSMCurrentState_3),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR({Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31, Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30}),
	.MASTERADDRINPROG_i_a2_d_c_c(MASTERADDRINPROG_i_a2_d_c_c[0]),
	.SADDRSEL_2(SADDRSEL_2[2]),
	.MASTERADDRINPROG_i_a2_c(MASTERADDRINPROG_i_a2_c[0]),
	.regHSIZE(regHSIZE[0]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE[0]),
	.MASTERADDRINPROG_i_a2_0_0_0_0(MASTERADDRINPROG_i_a2_0_0_0_0[0]),
	.M0GATEDHSIZE(M0GATEDHSIZE[1]),
	.SADDRSEL_1_0(SADDRSEL_1_0),
	.SADDRSEL_1_4(SADDRSEL_1_4),
	.SADDRSEL_0(SADDRSEL_0[3]),
	.CoreAHBLite_0_AHBmslave3_HSIZE(CoreAHBLite_0_AHBmslave3_HSIZE[1:0]),
	.Linker_Design_MSS_0_MSS_RESET_N_M2F(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.FCCC_0_GL0_0(FCCC_0_GL0_0),
	.CoreAHBLite_0_AHBmslave3_HREADY(CoreAHBLite_0_AHBmslave3_HREADY),
	.m0s3AddrSel(m0s3AddrSel),
	.N_156(N_156),
	.masterRegAddrSel(masterRegAddrSel),
	.N_152(N_152),
	.N_152_i_0(N_152_i_0)
);
  GND GND_Z (
	.Y(GND)
);
  VCC VCC_Z (
	.Y(VCC)
);
endmodule /* COREAHBLITE_SLAVESTAGE_slavestage_3 */

module COREAHBLITE_MATRIX4X16_1_1_0_8_0_0_0 (
  regHSIZE_1,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE,
  PREGATEDHADDR,
  M0GATEDHSIZE,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS,
  SADDRSEL_2,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29,
  arbRegSMCurrentState_3,
  arbRegSMCurrentState_0,
  SADDRSEL_1_4,
  SADDRSEL_1_0,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA,
  CoreAHBLite_0_AHBmslave3_HWDATA,
  CoreAHBLite_0_AHBmslave3_HADDR,
  MASTERADDRINPROG_i_a2_d_c_c,
  MASTERADDRINPROG_i_a2_c,
  MASTERADDRINPROG_i_a2_0_0_0_0,
  CoreAHBLite_0_AHBmslave3_HSIZE,
  Linker_Design_MSS_0_MSS_RESET_N_M2F,
  FCCC_0_GL0_0,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE,
  regHTRANS,
  masterRegAddrSel,
  M0GATEDHWRITE,
  HREADY_M_pre24,
  N_156,
  CoreAHBLite_0_AHBmslave3_HREADY,
  un1_HREADY_M_pre24_1_i_0,
  HREADY_M_iv_i_0,
  CoreAHBLite_0_AHBmslave3_HWRITE,
  N_152,
  HTRANS_0
)
;
output regHSIZE_1 ;
input [1:0] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE ;
output [28:28] PREGATEDHADDR ;
output [1:1] M0GATEDHSIZE ;
input [1:1] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS ;
output [2:2] SADDRSEL_2 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29 ;
output arbRegSMCurrentState_3 ;
output arbRegSMCurrentState_0 ;
output SADDRSEL_1_4 ;
output SADDRSEL_1_0 ;
input [31:0] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA ;
output [31:0] CoreAHBLite_0_AHBmslave3_HWDATA ;
output [15:0] CoreAHBLite_0_AHBmslave3_HADDR ;
output [0:0] MASTERADDRINPROG_i_a2_d_c_c ;
output [0:0] MASTERADDRINPROG_i_a2_c ;
output [0:0] MASTERADDRINPROG_i_a2_0_0_0_0 ;
output [1:0] CoreAHBLite_0_AHBmslave3_HSIZE ;
input Linker_Design_MSS_0_MSS_RESET_N_M2F ;
input FCCC_0_GL0_0 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE ;
output regHTRANS ;
output masterRegAddrSel ;
output M0GATEDHWRITE ;
output HREADY_M_pre24 ;
output N_156 ;
input CoreAHBLite_0_AHBmslave3_HREADY ;
output un1_HREADY_M_pre24_1_i_0 ;
output HREADY_M_iv_i_0 ;
output CoreAHBLite_0_AHBmslave3_HWRITE ;
output N_152 ;
output HTRANS_0 ;
wire regHSIZE_1 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29 ;
wire arbRegSMCurrentState_3 ;
wire arbRegSMCurrentState_0 ;
wire SADDRSEL_1_4 ;
wire SADDRSEL_1_0 ;
wire Linker_Design_MSS_0_MSS_RESET_N_M2F ;
wire FCCC_0_GL0_0 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE ;
wire regHTRANS ;
wire masterRegAddrSel ;
wire M0GATEDHWRITE ;
wire HREADY_M_pre24 ;
wire N_156 ;
wire CoreAHBLite_0_AHBmslave3_HREADY ;
wire un1_HREADY_M_pre24_1_i_0 ;
wire HREADY_M_iv_i_0 ;
wire CoreAHBLite_0_AHBmslave3_HWRITE ;
wire N_152 ;
wire HTRANS_0 ;
wire [15:0] regHADDR;
wire [0:0] regHSIZE;
wire [3:3] SADDRSEL_0;
wire [0:0] masterDataInProg;
wire m0s3DataSel ;
wire m0s3AddrSel ;
wire un1_HREADY_M_pre24_1 ;
wire defSlaveSMCurrentState ;
wire GND ;
wire VCC ;
// @15:2645
  COREAHBLITE_MASTERSTAGE_1_1_0_8_0_1_0 masterstage_0 (
	.regHADDR(regHADDR[15:0]),
	.regHSIZE({regHSIZE_1, regHSIZE[0]}),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE[1:0]),
	.PREGATEDHADDR(PREGATEDHADDR[28]),
	.M0GATEDHSIZE(M0GATEDHSIZE[1]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS[1]),
	.SADDRSEL_2(SADDRSEL_2[2]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29),
	.SADDRSEL_0(SADDRSEL_0[3]),
	.arbRegSMCurrentState_3(arbRegSMCurrentState_3),
	.arbRegSMCurrentState_0(arbRegSMCurrentState_0),
	.SADDRSEL_1_4(SADDRSEL_1_4),
	.SADDRSEL_1_0(SADDRSEL_1_0),
	.masterDataInProg(masterDataInProg[0]),
	.Linker_Design_MSS_0_MSS_RESET_N_M2F(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.FCCC_0_GL0_0(FCCC_0_GL0_0),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE),
	.regHTRANS(regHTRANS),
	.m0s3DataSel(m0s3DataSel),
	.m0s3AddrSel(m0s3AddrSel),
	.masterRegAddrSel(masterRegAddrSel),
	.M0GATEDHWRITE(M0GATEDHWRITE),
	.HREADY_M_pre24(HREADY_M_pre24),
	.N_156(N_156),
	.un1_HREADY_M_pre24_1(un1_HREADY_M_pre24_1),
	.CoreAHBLite_0_AHBmslave3_HREADY(CoreAHBLite_0_AHBmslave3_HREADY),
	.un1_HREADY_M_pre24_1_i_0(un1_HREADY_M_pre24_1_i_0),
	.HREADY_M_iv_i_0(HREADY_M_iv_i_0),
	.defSlaveSMCurrentState(defSlaveSMCurrentState)
);
// @15:3027
  COREAHBLITE_SLAVESTAGE_slavestage_3 slavestage_3 (
	.masterDataInProg(masterDataInProg[0]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[31:0]),
	.CoreAHBLite_0_AHBmslave3_HWDATA(CoreAHBLite_0_AHBmslave3_HWDATA[31:0]),
	.SADDRSEL_2(SADDRSEL_2[2]),
	.arbRegSMCurrentState_3(arbRegSMCurrentState_3),
	.arbRegSMCurrentState_0(arbRegSMCurrentState_0),
	.regHADDR(regHADDR[15:0]),
	.CoreAHBLite_0_AHBmslave3_HADDR(CoreAHBLite_0_AHBmslave3_HADDR[15:0]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS[1]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31),
	.MASTERADDRINPROG_i_a2_d_c_c(MASTERADDRINPROG_i_a2_d_c_c[0]),
	.MASTERADDRINPROG_i_a2_c(MASTERADDRINPROG_i_a2_c[0]),
	.regHSIZE(regHSIZE[0]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE[0]),
	.MASTERADDRINPROG_i_a2_0_0_0_0(MASTERADDRINPROG_i_a2_0_0_0_0[0]),
	.M0GATEDHSIZE(M0GATEDHSIZE[1]),
	.SADDRSEL_1_4(SADDRSEL_1_4),
	.SADDRSEL_1_0(SADDRSEL_1_0),
	.SADDRSEL_0(SADDRSEL_0[3]),
	.CoreAHBLite_0_AHBmslave3_HSIZE(CoreAHBLite_0_AHBmslave3_HSIZE[1:0]),
	.Linker_Design_MSS_0_MSS_RESET_N_M2F(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.FCCC_0_GL0_0(FCCC_0_GL0_0),
	.CoreAHBLite_0_AHBmslave3_HREADY(CoreAHBLite_0_AHBmslave3_HREADY),
	.masterRegAddrSel(masterRegAddrSel),
	.regHTRANS(regHTRANS),
	.N_156(N_156),
	.M0GATEDHWRITE(M0GATEDHWRITE),
	.CoreAHBLite_0_AHBmslave3_HWRITE(CoreAHBLite_0_AHBmslave3_HWRITE),
	.m0s3DataSel(m0s3DataSel),
	.un1_HREADY_M_pre24_1(un1_HREADY_M_pre24_1),
	.defSlaveSMCurrentState(defSlaveSMCurrentState),
	.N_152(N_152),
	.HTRANS_0(HTRANS_0),
	.m0s3AddrSel(m0s3AddrSel)
);
  GND GND_Z (
	.Y(GND)
);
  VCC VCC_Z (
	.Y(VCC)
);
endmodule /* COREAHBLITE_MATRIX4X16_1_1_0_8_0_0_0 */

module CoreAHBLite_Z3 (
  regHSIZE,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE,
  PREGATEDHADDR,
  M0GATEDHSIZE,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS,
  SADDRSEL_2,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29,
  arbRegSMCurrentState_3,
  arbRegSMCurrentState_0,
  SADDRSEL_1_4,
  SADDRSEL_1_0,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA,
  CoreAHBLite_0_AHBmslave3_HWDATA,
  CoreAHBLite_0_AHBmslave3_HADDR,
  MASTERADDRINPROG_i_a2_d_c_c,
  MASTERADDRINPROG_i_a2_c,
  MASTERADDRINPROG_i_a2_0_0_0_0,
  CoreAHBLite_0_AHBmslave3_HSIZE,
  Linker_Design_MSS_0_MSS_RESET_N_M2F,
  FCCC_0_GL0_0,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE,
  regHTRANS,
  masterRegAddrSel,
  M0GATEDHWRITE,
  HREADY_M_pre24,
  N_156,
  CoreAHBLite_0_AHBmslave3_HREADY,
  un1_HREADY_M_pre24_1_i_0,
  HREADY_M_iv_i_0,
  CoreAHBLite_0_AHBmslave3_HWRITE,
  N_152,
  HTRANS_0
)
;
output [1:1] regHSIZE ;
input [1:0] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE ;
output [28:28] PREGATEDHADDR ;
output [1:1] M0GATEDHSIZE ;
input [1:1] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS ;
output [2:2] SADDRSEL_2 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29 ;
output arbRegSMCurrentState_3 ;
output arbRegSMCurrentState_0 ;
output SADDRSEL_1_4 ;
output SADDRSEL_1_0 ;
input [31:0] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA ;
output [31:0] CoreAHBLite_0_AHBmslave3_HWDATA ;
output [15:0] CoreAHBLite_0_AHBmslave3_HADDR ;
output [0:0] MASTERADDRINPROG_i_a2_d_c_c ;
output [0:0] MASTERADDRINPROG_i_a2_c ;
output [0:0] MASTERADDRINPROG_i_a2_0_0_0_0 ;
output [1:0] CoreAHBLite_0_AHBmslave3_HSIZE ;
input Linker_Design_MSS_0_MSS_RESET_N_M2F ;
input FCCC_0_GL0_0 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE ;
output regHTRANS ;
output masterRegAddrSel ;
output M0GATEDHWRITE ;
output HREADY_M_pre24 ;
output N_156 ;
input CoreAHBLite_0_AHBmslave3_HREADY ;
output un1_HREADY_M_pre24_1_i_0 ;
output HREADY_M_iv_i_0 ;
output CoreAHBLite_0_AHBmslave3_HWRITE ;
output N_152 ;
output HTRANS_0 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29 ;
wire arbRegSMCurrentState_3 ;
wire arbRegSMCurrentState_0 ;
wire SADDRSEL_1_4 ;
wire SADDRSEL_1_0 ;
wire Linker_Design_MSS_0_MSS_RESET_N_M2F ;
wire FCCC_0_GL0_0 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE ;
wire regHTRANS ;
wire masterRegAddrSel ;
wire M0GATEDHWRITE ;
wire HREADY_M_pre24 ;
wire N_156 ;
wire CoreAHBLite_0_AHBmslave3_HREADY ;
wire un1_HREADY_M_pre24_1_i_0 ;
wire HREADY_M_iv_i_0 ;
wire CoreAHBLite_0_AHBmslave3_HWRITE ;
wire N_152 ;
wire HTRANS_0 ;
wire GND ;
wire VCC ;
// @16:548
  COREAHBLITE_MATRIX4X16_1_1_0_8_0_0_0 matrix4x16 (
	.regHSIZE_1(regHSIZE[1]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE[1:0]),
	.PREGATEDHADDR(PREGATEDHADDR[28]),
	.M0GATEDHSIZE(M0GATEDHSIZE[1]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS[1]),
	.SADDRSEL_2(SADDRSEL_2[2]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29),
	.arbRegSMCurrentState_3(arbRegSMCurrentState_3),
	.arbRegSMCurrentState_0(arbRegSMCurrentState_0),
	.SADDRSEL_1_4(SADDRSEL_1_4),
	.SADDRSEL_1_0(SADDRSEL_1_0),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[31:0]),
	.CoreAHBLite_0_AHBmslave3_HWDATA(CoreAHBLite_0_AHBmslave3_HWDATA[31:0]),
	.CoreAHBLite_0_AHBmslave3_HADDR(CoreAHBLite_0_AHBmslave3_HADDR[15:0]),
	.MASTERADDRINPROG_i_a2_d_c_c(MASTERADDRINPROG_i_a2_d_c_c[0]),
	.MASTERADDRINPROG_i_a2_c(MASTERADDRINPROG_i_a2_c[0]),
	.MASTERADDRINPROG_i_a2_0_0_0_0(MASTERADDRINPROG_i_a2_0_0_0_0[0]),
	.CoreAHBLite_0_AHBmslave3_HSIZE(CoreAHBLite_0_AHBmslave3_HSIZE[1:0]),
	.Linker_Design_MSS_0_MSS_RESET_N_M2F(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.FCCC_0_GL0_0(FCCC_0_GL0_0),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE),
	.regHTRANS(regHTRANS),
	.masterRegAddrSel(masterRegAddrSel),
	.M0GATEDHWRITE(M0GATEDHWRITE),
	.HREADY_M_pre24(HREADY_M_pre24),
	.N_156(N_156),
	.CoreAHBLite_0_AHBmslave3_HREADY(CoreAHBLite_0_AHBmslave3_HREADY),
	.un1_HREADY_M_pre24_1_i_0(un1_HREADY_M_pre24_1_i_0),
	.HREADY_M_iv_i_0(HREADY_M_iv_i_0),
	.CoreAHBLite_0_AHBmslave3_HWRITE(CoreAHBLite_0_AHBmslave3_HWRITE),
	.N_152(N_152),
	.HTRANS_0(HTRANS_0)
);
  GND GND_Z (
	.Y(GND)
);
  VCC VCC_Z (
	.Y(VCC)
);
endmodule /* CoreAHBLite_Z3 */

module AHBLSramIf (
  ahbsram_addr,
  CoreAHBLite_0_AHBmslave3_HADDR,
  CoreAHBLite_0_AHBmslave3_HSIZE,
  ahbcurr_state,
  arbRegSMCurrentState_0,
  arbRegSMCurrentState_3,
  CoreAHBLite_0_AHBmslave3_HRDATA,
  CoreAHBLite_0_AHBmslave3_HRDATA_m,
  SADDRSEL_2,
  PREGATEDHADDR,
  M0GATEDHSIZE,
  ahbsram_size_0_0,
  MASTERADDRINPROG_i_a2_0_0_0_0,
  MASTERADDRINPROG_i_a2_d_c_c,
  SADDRSEL_1_4,
  SADDRSEL_1_0,
  Linker_Design_MSS_0_MSS_RESET_N_M2F,
  FCCC_0_GL0_0,
  CoreAHBLite_0_AHBmslave3_HWRITE,
  ahbsram_req_d1,
  CoreAHBLite_0_AHBmslave3_HREADY,
  N_152,
  sramahb_ack,
  HTRANS_0,
  d_N_3_mux,
  ahbsram_write,
  HREADY_M_pre24,
  N_156,
  M0GATEDHWRITE,
  ahbsram_N_4
)
;
output [15:0] ahbsram_addr ;
input [15:0] CoreAHBLite_0_AHBmslave3_HADDR ;
input [1:0] CoreAHBLite_0_AHBmslave3_HSIZE ;
output [1:0] ahbcurr_state ;
input arbRegSMCurrentState_0 ;
input arbRegSMCurrentState_3 ;
input [31:0] CoreAHBLite_0_AHBmslave3_HRDATA ;
output [31:0] CoreAHBLite_0_AHBmslave3_HRDATA_m ;
input [2:2] SADDRSEL_2 ;
input [28:28] PREGATEDHADDR ;
input [1:1] M0GATEDHSIZE ;
output [1:1] ahbsram_size_0_0 ;
input [0:0] MASTERADDRINPROG_i_a2_0_0_0_0 ;
input [0:0] MASTERADDRINPROG_i_a2_d_c_c ;
input SADDRSEL_1_4 ;
input SADDRSEL_1_0 ;
input Linker_Design_MSS_0_MSS_RESET_N_M2F ;
input FCCC_0_GL0_0 ;
input CoreAHBLite_0_AHBmslave3_HWRITE ;
output ahbsram_req_d1 ;
output CoreAHBLite_0_AHBmslave3_HREADY ;
input N_152 ;
input sramahb_ack ;
input HTRANS_0 ;
output d_N_3_mux ;
output ahbsram_write ;
input HREADY_M_pre24 ;
input N_156 ;
input M0GATEDHWRITE ;
output ahbsram_N_4 ;
wire arbRegSMCurrentState_0 ;
wire arbRegSMCurrentState_3 ;
wire SADDRSEL_1_4 ;
wire SADDRSEL_1_0 ;
wire Linker_Design_MSS_0_MSS_RESET_N_M2F ;
wire FCCC_0_GL0_0 ;
wire CoreAHBLite_0_AHBmslave3_HWRITE ;
wire ahbsram_req_d1 ;
wire CoreAHBLite_0_AHBmslave3_HREADY ;
wire N_152 ;
wire sramahb_ack ;
wire HTRANS_0 ;
wire d_N_3_mux ;
wire ahbsram_write ;
wire HREADY_M_pre24 ;
wire N_156 ;
wire M0GATEDHWRITE ;
wire ahbsram_N_4 ;
wire [1:0] HSIZE_d;
wire [1:0] ahbcurr_state_ns;
wire [1:1] ahbsram_size_a1_1;
wire VCC ;
wire latchahbcmd_0_sqmuxa ;
wire GND ;
wire HWRITE_d_Z ;
wire CoreAHBLite_0_AHBmslave3_HREADY_i_0 ;
wire m8_0_ns_1 ;
wire validahbcmd_a1_0_Z ;
wire N_44 ;
wire m5_a0_1 ;
wire validahbcmd_a0_3_1_Z ;
wire m5_a1 ;
wire m5_0_0 ;
wire N_320 ;
wire N_51 ;
wire N_50 ;
wire N_49 ;
wire N_48 ;
wire N_20 ;
wire N_19 ;
wire N_18 ;
// @17:161
  SLE \HADDR_d[0]  (
	.Q(ahbsram_addr[0]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(CoreAHBLite_0_AHBmslave3_HADDR[0]),
	.EN(latchahbcmd_0_sqmuxa),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @17:161
  SLE \HADDR_d[1]  (
	.Q(ahbsram_addr[1]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(CoreAHBLite_0_AHBmslave3_HADDR[1]),
	.EN(latchahbcmd_0_sqmuxa),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @17:161
  SLE \HADDR_d[2]  (
	.Q(ahbsram_addr[2]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(CoreAHBLite_0_AHBmslave3_HADDR[2]),
	.EN(latchahbcmd_0_sqmuxa),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @17:161
  SLE \HADDR_d[3]  (
	.Q(ahbsram_addr[3]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(CoreAHBLite_0_AHBmslave3_HADDR[3]),
	.EN(latchahbcmd_0_sqmuxa),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @17:161
  SLE \HADDR_d[4]  (
	.Q(ahbsram_addr[4]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(CoreAHBLite_0_AHBmslave3_HADDR[4]),
	.EN(latchahbcmd_0_sqmuxa),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @17:161
  SLE \HADDR_d[5]  (
	.Q(ahbsram_addr[5]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(CoreAHBLite_0_AHBmslave3_HADDR[5]),
	.EN(latchahbcmd_0_sqmuxa),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @17:161
  SLE \HADDR_d[6]  (
	.Q(ahbsram_addr[6]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(CoreAHBLite_0_AHBmslave3_HADDR[6]),
	.EN(latchahbcmd_0_sqmuxa),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @17:161
  SLE \HADDR_d[7]  (
	.Q(ahbsram_addr[7]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(CoreAHBLite_0_AHBmslave3_HADDR[7]),
	.EN(latchahbcmd_0_sqmuxa),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @17:161
  SLE \HADDR_d[8]  (
	.Q(ahbsram_addr[8]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(CoreAHBLite_0_AHBmslave3_HADDR[8]),
	.EN(latchahbcmd_0_sqmuxa),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @17:161
  SLE \HADDR_d[9]  (
	.Q(ahbsram_addr[9]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(CoreAHBLite_0_AHBmslave3_HADDR[9]),
	.EN(latchahbcmd_0_sqmuxa),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @17:161
  SLE \HADDR_d[10]  (
	.Q(ahbsram_addr[10]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(CoreAHBLite_0_AHBmslave3_HADDR[10]),
	.EN(latchahbcmd_0_sqmuxa),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @17:161
  SLE \HADDR_d[11]  (
	.Q(ahbsram_addr[11]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(CoreAHBLite_0_AHBmslave3_HADDR[11]),
	.EN(latchahbcmd_0_sqmuxa),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @17:161
  SLE \HADDR_d[12]  (
	.Q(ahbsram_addr[12]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(CoreAHBLite_0_AHBmslave3_HADDR[12]),
	.EN(latchahbcmd_0_sqmuxa),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @17:161
  SLE \HADDR_d[13]  (
	.Q(ahbsram_addr[13]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(CoreAHBLite_0_AHBmslave3_HADDR[13]),
	.EN(latchahbcmd_0_sqmuxa),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @17:161
  SLE \HADDR_d[14]  (
	.Q(ahbsram_addr[14]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(CoreAHBLite_0_AHBmslave3_HADDR[14]),
	.EN(latchahbcmd_0_sqmuxa),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @17:161
  SLE \HADDR_d[15]  (
	.Q(ahbsram_addr[15]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(CoreAHBLite_0_AHBmslave3_HADDR[15]),
	.EN(latchahbcmd_0_sqmuxa),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @17:161
  SLE \HSIZE_d[0]  (
	.Q(HSIZE_d[0]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(CoreAHBLite_0_AHBmslave3_HSIZE[0]),
	.EN(latchahbcmd_0_sqmuxa),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @17:161
  SLE \HSIZE_d[1]  (
	.Q(HSIZE_d[1]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(CoreAHBLite_0_AHBmslave3_HSIZE[1]),
	.EN(latchahbcmd_0_sqmuxa),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @17:161
  SLE HWRITE_d (
	.Q(HWRITE_d_Z),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(CoreAHBLite_0_AHBmslave3_HWRITE),
	.EN(latchahbcmd_0_sqmuxa),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @17:251
  SLE ahbsram_req_d1_Z (
	.Q(ahbsram_req_d1),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(CoreAHBLite_0_AHBmslave3_HREADY_i_0),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @17:185
  SLE \ahbcurr_state_Z[0]  (
	.Q(ahbcurr_state[0]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ahbcurr_state_ns[0]),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @17:185
  SLE \ahbcurr_state_Z[1]  (
	.Q(ahbcurr_state[1]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ahbcurr_state_ns[1]),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @17:185
  CFG4 \ahbcurr_state_ns_1_0_.m8_0_ns  (
	.A(CoreAHBLite_0_AHBmslave3_HREADY),
	.B(m8_0_ns_1),
	.C(CoreAHBLite_0_AHBmslave3_HWRITE),
	.D(N_152),
	.Y(ahbcurr_state_ns[1])
);
defparam \ahbcurr_state_ns_1_0_.m8_0_ns .INIT=16'h4446;
// @17:185
  CFG4 \ahbcurr_state_ns_1_0_.m8_0_ns_1  (
	.A(sramahb_ack),
	.B(ahbcurr_state[0]),
	.C(CoreAHBLite_0_AHBmslave3_HREADY),
	.D(HTRANS_0),
	.Y(m8_0_ns_1)
);
defparam \ahbcurr_state_ns_1_0_.m8_0_ns_1 .INIT=16'h01F1;
// @17:185
  CFG2 \ahbcurr_state_ns_1_0_.m5_a0_0  (
	.A(ahbcurr_state[0]),
	.B(ahbcurr_state[1]),
	.Y(CoreAHBLite_0_AHBmslave3_HREADY)
);
defparam \ahbcurr_state_ns_1_0_.m5_a0_0 .INIT=4'h1;
// @20:188
  CFG2 \HSIZE_d_RNIJT7J[0]  (
	.A(ahbsram_addr[1]),
	.B(HSIZE_d[0]),
	.Y(d_N_3_mux)
);
defparam \HSIZE_d_RNIJT7J[0] .INIT=4'h4;
// @13:452
  CFG2 \ahbcurr_state_ns_1_0_.CoreAHBLite_0_AHBmslave3_HREADY_i  (
	.A(ahbcurr_state[0]),
	.B(ahbcurr_state[1]),
	.Y(CoreAHBLite_0_AHBmslave3_HREADY_i_0)
);
defparam \ahbcurr_state_ns_1_0_.CoreAHBLite_0_AHBmslave3_HREADY_i .INIT=4'hE;
// @17:149
  CFG3 validahbcmd_a1_0 (
	.A(arbRegSMCurrentState_0),
	.B(CoreAHBLite_0_AHBmslave3_HREADY),
	.C(arbRegSMCurrentState_3),
	.Y(validahbcmd_a1_0_Z)
);
defparam validahbcmd_a1_0.INIT=8'hC8;
// @17:249
  CFG3 \ahbcurr_state_RNIAM2U[1]  (
	.A(sramahb_ack),
	.B(ahbcurr_state[0]),
	.C(ahbcurr_state[1]),
	.Y(N_44)
);
defparam \ahbcurr_state_RNIAM2U[1] .INIT=8'hAB;
// @17:246
  CFG4 ahbsram_write_c (
	.A(HWRITE_d_Z),
	.B(ahbsram_req_d1),
	.C(sramahb_ack),
	.D(CoreAHBLite_0_AHBmslave3_HREADY),
	.Y(ahbsram_write)
);
defparam ahbsram_write_c.INIT=16'h0002;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[0]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[0]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[0])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[0] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[1]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[1]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[1])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[1] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[2]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[2]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[2])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[2] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[3]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[3]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[3])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[3] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[4]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[4]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[4])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[4] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[5]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[5]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[5])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[5] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[6]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[6]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[6])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[6] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[7]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[7]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[7])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[7] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[8]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[8]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[8])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[8] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[9]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[9]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[9])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[9] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[10]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[10]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[10])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[10] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[11]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[11]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[11])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[11] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[12]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[12]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[12])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[12] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[13]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[13]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[13])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[13] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[14]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[14]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[14])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[14] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[15]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[15]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[15])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[15] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[16]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[16]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[16])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[16] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[17]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[17]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[17])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[17] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[18]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[18]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[18])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[18] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[19]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[19]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[19])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[19] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[20]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[20]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[20])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[20] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[21]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[21]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[21])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[21] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[22]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[22]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[22])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[22] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[23]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[23]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[23])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[23] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[24]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[24]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[24])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[24] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[25]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[25]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[25])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[25] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[26]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[26]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[26])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[26] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[27]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[27]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[27])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[27] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[28]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[28]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[28])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[28] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[29]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[29]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[29])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[29] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[30]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[30]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[30])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[30] .INIT=4'h8;
// @12:262
  CFG2 \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[31]  (
	.A(HREADY_M_pre24),
	.B(CoreAHBLite_0_AHBmslave3_HRDATA[31]),
	.Y(CoreAHBLite_0_AHBmslave3_HRDATA_m[31])
);
defparam \CoreAHBLite_0_AHBmslave3_HRDATA_m_cZ[31] .INIT=4'h8;
// @17:249
  CFG3 \ahbsram_size_a1_1[1]  (
	.A(arbRegSMCurrentState_3),
	.B(arbRegSMCurrentState_0),
	.C(N_44),
	.Y(ahbsram_size_a1_1[1])
);
defparam \ahbsram_size_a1_1[1] .INIT=8'hE0;
// @17:185
  CFG4 \ahbcurr_state_ns_1_0_.m5_a0_1  (
	.A(N_156),
	.B(CoreAHBLite_0_AHBmslave3_HREADY),
	.C(M0GATEDHWRITE),
	.D(SADDRSEL_2[2]),
	.Y(m5_a0_1)
);
defparam \ahbcurr_state_ns_1_0_.m5_a0_1 .INIT=16'h4000;
// @17:149
  CFG4 validahbcmd_a0_3_1 (
	.A(N_156),
	.B(CoreAHBLite_0_AHBmslave3_HREADY),
	.C(PREGATEDHADDR[28]),
	.D(SADDRSEL_2[2]),
	.Y(validahbcmd_a0_3_1_Z)
);
defparam validahbcmd_a0_3_1.INIT=16'h4000;
// @17:249
  CFG4 \ahbsram_size_0_0_cZ[1]  (
	.A(HSIZE_d[1]),
	.B(N_44),
	.C(ahbsram_size_a1_1[1]),
	.D(M0GATEDHSIZE[1]),
	.Y(ahbsram_size_0_0[1])
);
defparam \ahbsram_size_0_0_cZ[1] .INIT=16'hF222;
// @17:249
  CFG4 \HSIZE_d_RNI07AN1[0]  (
	.A(N_44),
	.B(HSIZE_d[0]),
	.C(MASTERADDRINPROG_i_a2_0_0_0_0[0]),
	.D(MASTERADDRINPROG_i_a2_d_c_c[0]),
	.Y(ahbsram_N_4)
);
defparam \HSIZE_d_RNI07AN1[0] .INIT=16'hE444;
// @17:185
  CFG3 \ahbcurr_state_ns_1_0_.m5_a1  (
	.A(validahbcmd_a1_0_Z),
	.B(M0GATEDHWRITE),
	.C(HTRANS_0),
	.Y(m5_a1)
);
defparam \ahbcurr_state_ns_1_0_.m5_a1 .INIT=8'h80;
// @17:149
  CFG4 validahbcmd_0 (
	.A(HTRANS_0),
	.B(validahbcmd_a1_0_Z),
	.C(validahbcmd_a0_3_1_Z),
	.D(SADDRSEL_1_4),
	.Y(latchahbcmd_0_sqmuxa)
);
defparam validahbcmd_0.INIT=16'hA888;
// @17:185
  CFG4 \ahbcurr_state_ns_1_0_.m5_0_0  (
	.A(ahbcurr_state[0]),
	.B(m5_a1),
	.C(ahbcurr_state[1]),
	.D(sramahb_ack),
	.Y(m5_0_0)
);
defparam \ahbcurr_state_ns_1_0_.m5_0_0 .INIT=16'hCCCE;
// @17:185
  CFG4 \ahbcurr_state_ns_1_0_.m5_0  (
	.A(HTRANS_0),
	.B(SADDRSEL_1_0),
	.C(m5_a0_1),
	.D(m5_0_0),
	.Y(ahbcurr_state_ns[0])
);
defparam \ahbcurr_state_ns_1_0_.m5_0 .INIT=16'hFF80;
//@21:106
//@21:106
//@21:106
//@21:106
//@17:185
  GND GND_Z (
	.Y(GND)
);
  VCC VCC_Z (
	.Y(VCC)
);
endmodule /* AHBLSramIf */

module Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s (
  ckRdAddr,
  ram_rdata,
  wen_a7_0_a2_0_a2_0,
  wen_a1_0_a2_0_a2_0,
  wen_a0_0_a2_0_a2_0,
  sram_wen_mem_m3_0,
  wen_a6_0_a2_1_a2_0,
  sram_wen_mem_m4,
  wen_a5_0_a2_1_a2_0,
  wen_a3_0_a2_0_a2_0,
  wen_a2_0_a2_0_a2_0,
  CoreAHBLite_0_AHBmslave3_HWDATA,
  ahbsram_addr,
  Linker_Design_MSS_0_MSS_RESET_N_M2F,
  FCCC_0_GL0_0,
  sram_N_3_mux_0
)
;
output [13:11] ckRdAddr ;
output [7:0] ram_rdata ;
output [0:0] wen_a7_0_a2_0_a2_0 ;
output [0:0] wen_a1_0_a2_0_a2_0 ;
output [0:0] wen_a0_0_a2_0_a2_0 ;
input [0:0] sram_wen_mem_m3_0 ;
input [0:0] wen_a6_0_a2_1_a2_0 ;
input [0:0] sram_wen_mem_m4 ;
input [0:0] wen_a5_0_a2_1_a2_0 ;
input [0:0] wen_a3_0_a2_0_a2_0 ;
input [0:0] wen_a2_0_a2_0_a2_0 ;
input [7:0] CoreAHBLite_0_AHBmslave3_HWDATA ;
input [15:2] ahbsram_addr ;
input Linker_Design_MSS_0_MSS_RESET_N_M2F ;
input FCCC_0_GL0_0 ;
input sram_N_3_mux_0 ;
wire Linker_Design_MSS_0_MSS_RESET_N_M2F ;
wire FCCC_0_GL0_0 ;
wire sram_N_3_mux_0 ;
wire [17:0] readData6;
wire [17:0] readData2;
wire [7:0] readData_7_am_1_1;
wire [7:0] readData_7_am_2;
wire [17:0] readData4;
wire [17:0] readData0;
wire [17:0] readData7;
wire [17:0] readData5;
wire [7:0] readData_7_bm_1_1;
wire [7:0] readData_7_bm_2;
wire [17:0] readData3;
wire [17:0] readData1;
wire [0:0] wen_a4_0_a2_0_a2_0;
wire [0:0] wen_a6;
wire [0:0] wen_a5;
wire [0:0] wen_a4;
wire [0:0] wen_a3;
wire [0:0] wen_a2;
wire [0:0] wen_a1;
wire [0:0] wen_a0;
wire [0:0] wen_a7;
wire [17:0] block0_B_DOUT;
wire [17:0] block1_B_DOUT;
wire [17:0] block2_B_DOUT;
wire [17:0] block3_B_DOUT;
wire [17:0] block4_B_DOUT;
wire [17:0] block5_B_DOUT;
wire [17:0] block6_B_DOUT;
wire [17:0] block7_B_DOUT;
wire VCC ;
wire GND ;
wire N_9 ;
wire N_8 ;
wire N_7 ;
wire N_6 ;
wire N_5 ;
wire N_4 ;
wire N_3 ;
wire N_2 ;
wire N_1 ;
wire lsram_2k_BUSY_0 ;
wire lsram_2k_BUSY_1 ;
wire lsram_2k_BUSY_2 ;
wire lsram_2k_BUSY_3 ;
wire lsram_2k_BUSY_4 ;
wire lsram_2k_BUSY_5 ;
wire lsram_2k_BUSY_6 ;
wire lsram_2k_BUSY_7 ;
// @18:229
  SLE \ckRdAddr_Z[11]  (
	.Q(ckRdAddr[11]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ahbsram_addr[13]),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @18:229
  SLE \ckRdAddr_Z[12]  (
	.Q(ckRdAddr[12]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ahbsram_addr[14]),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @18:229
  SLE \ckRdAddr_Z[13]  (
	.Q(ckRdAddr[13]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ahbsram_addr[15]),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @18:1043
  CFG4 \readData_7_am[0]  (
	.A(readData6[0]),
	.B(readData2[0]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[0]),
	.Y(readData_7_am_2[0])
);
defparam \readData_7_am[0] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[0]  (
	.A(readData4[0]),
	.B(readData0[0]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[0])
);
defparam \readData_7_am_1_1[0] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[0]  (
	.A(readData7[0]),
	.B(readData5[0]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[0]),
	.Y(readData_7_bm_2[0])
);
defparam \readData_7_bm[0] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[0]  (
	.A(readData3[0]),
	.B(readData1[0]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[0])
);
defparam \readData_7_bm_1_1[0] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[1]  (
	.A(readData6[1]),
	.B(readData2[1]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[1]),
	.Y(readData_7_am_2[1])
);
defparam \readData_7_am[1] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[1]  (
	.A(readData4[1]),
	.B(readData0[1]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[1])
);
defparam \readData_7_am_1_1[1] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[1]  (
	.A(readData7[1]),
	.B(readData5[1]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[1]),
	.Y(readData_7_bm_2[1])
);
defparam \readData_7_bm[1] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[1]  (
	.A(readData3[1]),
	.B(readData1[1]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[1])
);
defparam \readData_7_bm_1_1[1] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[2]  (
	.A(readData6[2]),
	.B(readData2[2]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[2]),
	.Y(readData_7_am_2[2])
);
defparam \readData_7_am[2] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[2]  (
	.A(readData4[2]),
	.B(readData0[2]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[2])
);
defparam \readData_7_am_1_1[2] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[2]  (
	.A(readData7[2]),
	.B(readData5[2]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[2]),
	.Y(readData_7_bm_2[2])
);
defparam \readData_7_bm[2] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[2]  (
	.A(readData3[2]),
	.B(readData1[2]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[2])
);
defparam \readData_7_bm_1_1[2] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[3]  (
	.A(readData6[3]),
	.B(readData2[3]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[3]),
	.Y(readData_7_am_2[3])
);
defparam \readData_7_am[3] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[3]  (
	.A(readData4[3]),
	.B(readData0[3]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[3])
);
defparam \readData_7_am_1_1[3] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[3]  (
	.A(readData7[3]),
	.B(readData5[3]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[3]),
	.Y(readData_7_bm_2[3])
);
defparam \readData_7_bm[3] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[3]  (
	.A(readData3[3]),
	.B(readData1[3]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[3])
);
defparam \readData_7_bm_1_1[3] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[4]  (
	.A(readData6[4]),
	.B(readData2[4]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[4]),
	.Y(readData_7_am_2[4])
);
defparam \readData_7_am[4] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[4]  (
	.A(readData4[4]),
	.B(readData0[4]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[4])
);
defparam \readData_7_am_1_1[4] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[4]  (
	.A(readData7[4]),
	.B(readData5[4]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[4]),
	.Y(readData_7_bm_2[4])
);
defparam \readData_7_bm[4] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[4]  (
	.A(readData3[4]),
	.B(readData1[4]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[4])
);
defparam \readData_7_bm_1_1[4] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[5]  (
	.A(readData6[5]),
	.B(readData2[5]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[5]),
	.Y(readData_7_am_2[5])
);
defparam \readData_7_am[5] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[5]  (
	.A(readData4[5]),
	.B(readData0[5]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[5])
);
defparam \readData_7_am_1_1[5] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[5]  (
	.A(readData7[5]),
	.B(readData5[5]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[5]),
	.Y(readData_7_bm_2[5])
);
defparam \readData_7_bm[5] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[5]  (
	.A(readData3[5]),
	.B(readData1[5]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[5])
);
defparam \readData_7_bm_1_1[5] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[6]  (
	.A(readData6[6]),
	.B(readData2[6]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[6]),
	.Y(readData_7_am_2[6])
);
defparam \readData_7_am[6] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[6]  (
	.A(readData4[6]),
	.B(readData0[6]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[6])
);
defparam \readData_7_am_1_1[6] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[6]  (
	.A(readData7[6]),
	.B(readData5[6]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[6]),
	.Y(readData_7_bm_2[6])
);
defparam \readData_7_bm[6] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[6]  (
	.A(readData3[6]),
	.B(readData1[6]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[6])
);
defparam \readData_7_bm_1_1[6] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[7]  (
	.A(readData6[7]),
	.B(readData2[7]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[7]),
	.Y(readData_7_am_2[7])
);
defparam \readData_7_am[7] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[7]  (
	.A(readData4[7]),
	.B(readData0[7]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[7])
);
defparam \readData_7_am_1_1[7] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[7]  (
	.A(readData7[7]),
	.B(readData5[7]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[7]),
	.Y(readData_7_bm_2[7])
);
defparam \readData_7_bm[7] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[7]  (
	.A(readData3[7]),
	.B(readData1[7]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[7])
);
defparam \readData_7_bm_1_1[7] .INIT=16'h05F3;
// @18:1043
  CFG3 \readData_7_ns[0]  (
	.A(readData_7_am_2[0]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_2[0]),
	.Y(ram_rdata[0])
);
defparam \readData_7_ns[0] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[1]  (
	.A(readData_7_am_2[1]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_2[1]),
	.Y(ram_rdata[1])
);
defparam \readData_7_ns[1] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[2]  (
	.A(readData_7_am_2[2]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_2[2]),
	.Y(ram_rdata[2])
);
defparam \readData_7_ns[2] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[3]  (
	.A(readData_7_am_2[3]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_2[3]),
	.Y(ram_rdata[3])
);
defparam \readData_7_ns[3] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[4]  (
	.A(readData_7_am_2[4]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_2[4]),
	.Y(ram_rdata[4])
);
defparam \readData_7_ns[4] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[5]  (
	.A(readData_7_am_2[5]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_2[5]),
	.Y(ram_rdata[5])
);
defparam \readData_7_ns[5] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[6]  (
	.A(readData_7_am_2[6]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_2[6]),
	.Y(ram_rdata[6])
);
defparam \readData_7_ns[6] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[7]  (
	.A(readData_7_am_2[7]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_2[7]),
	.Y(ram_rdata[7])
);
defparam \readData_7_ns[7] .INIT=8'hE2;
// @18:950
  CFG3 \wen_a4_0_a2_0_a2_0[0]  (
	.A(ahbsram_addr[15]),
	.B(ahbsram_addr[14]),
	.C(ahbsram_addr[13]),
	.Y(wen_a4_0_a2_0_a2_0[0])
);
defparam \wen_a4_0_a2_0_a2_0[0] .INIT=8'h02;
// @18:950
  CFG3 \wen_a7_0_a2_0_a2_0_cZ[0]  (
	.A(ahbsram_addr[15]),
	.B(ahbsram_addr[14]),
	.C(ahbsram_addr[13]),
	.Y(wen_a7_0_a2_0_a2_0[0])
);
defparam \wen_a7_0_a2_0_a2_0_cZ[0] .INIT=8'h80;
// @18:950
  CFG3 \wen_a1_0_a2_0_a2_0_cZ[0]  (
	.A(ahbsram_addr[15]),
	.B(ahbsram_addr[14]),
	.C(ahbsram_addr[13]),
	.Y(wen_a1_0_a2_0_a2_0[0])
);
defparam \wen_a1_0_a2_0_a2_0_cZ[0] .INIT=8'h10;
// @18:950
  CFG3 \wen_a0_0_a2_0_a2_0_cZ[0]  (
	.A(ahbsram_addr[15]),
	.B(ahbsram_addr[14]),
	.C(ahbsram_addr[13]),
	.Y(wen_a0_0_a2_0_a2_0[0])
);
defparam \wen_a0_0_a2_0_a2_0_cZ[0] .INIT=8'h01;
// @18:950
  CFG4 \wen_a6_0_a2_1_a2[0]  (
	.A(sram_wen_mem_m3_0[0]),
	.B(wen_a6_0_a2_1_a2_0[0]),
	.C(sram_wen_mem_m4[0]),
	.D(sram_N_3_mux_0),
	.Y(wen_a6[0])
);
defparam \wen_a6_0_a2_1_a2[0] .INIT=16'h80C0;
// @18:950
  CFG4 \wen_a5_0_a2_1_a2[0]  (
	.A(sram_wen_mem_m3_0[0]),
	.B(wen_a5_0_a2_1_a2_0[0]),
	.C(sram_wen_mem_m4[0]),
	.D(sram_N_3_mux_0),
	.Y(wen_a5[0])
);
defparam \wen_a5_0_a2_1_a2[0] .INIT=16'h80C0;
// @18:950
  CFG4 \wen_a4_0_a2_0_a2[0]  (
	.A(sram_wen_mem_m3_0[0]),
	.B(wen_a4_0_a2_0_a2_0[0]),
	.C(sram_wen_mem_m4[0]),
	.D(sram_N_3_mux_0),
	.Y(wen_a4[0])
);
defparam \wen_a4_0_a2_0_a2[0] .INIT=16'h80C0;
// @18:950
  CFG4 \wen_a3_0_a2_0_a2[0]  (
	.A(sram_wen_mem_m3_0[0]),
	.B(wen_a3_0_a2_0_a2_0[0]),
	.C(sram_wen_mem_m4[0]),
	.D(sram_N_3_mux_0),
	.Y(wen_a3[0])
);
defparam \wen_a3_0_a2_0_a2[0] .INIT=16'h80C0;
// @18:950
  CFG4 \wen_a2_0_a2_0_a2[0]  (
	.A(sram_wen_mem_m3_0[0]),
	.B(wen_a2_0_a2_0_a2_0[0]),
	.C(sram_wen_mem_m4[0]),
	.D(sram_N_3_mux_0),
	.Y(wen_a2[0])
);
defparam \wen_a2_0_a2_0_a2[0] .INIT=16'h80C0;
// @18:950
  CFG4 \wen_a1_0_a2_0_a2[0]  (
	.A(sram_wen_mem_m3_0[0]),
	.B(wen_a1_0_a2_0_a2_0[0]),
	.C(sram_wen_mem_m4[0]),
	.D(sram_N_3_mux_0),
	.Y(wen_a1[0])
);
defparam \wen_a1_0_a2_0_a2[0] .INIT=16'h80C0;
// @18:950
  CFG4 \wen_a0_0_a2_0_a2[0]  (
	.A(sram_wen_mem_m3_0[0]),
	.B(wen_a0_0_a2_0_a2_0[0]),
	.C(sram_wen_mem_m4[0]),
	.D(sram_N_3_mux_0),
	.Y(wen_a0[0])
);
defparam \wen_a0_0_a2_0_a2[0] .INIT=16'h80C0;
// @18:950
  CFG4 \wen_a7_0_a2_0_a2[0]  (
	.A(sram_wen_mem_m3_0[0]),
	.B(wen_a7_0_a2_0_a2_0[0]),
	.C(sram_wen_mem_m4[0]),
	.D(sram_N_3_mux_0),
	.Y(wen_a7[0])
);
defparam \wen_a7_0_a2_0_a2[0] .INIT=16'h80C0;
//@20:247
//@20:247
//@20:247
//@20:247
//@20:247
//@20:247
//@20:247
//@20:247
//@20:247
// @18:3028
  RAM1K18 block0 (
	.A_DOUT(readData0[17:0]),
	.B_DOUT(block0_B_DOUT[17:0]),
	.BUSY(lsram_2k_BUSY_0),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[7:0]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a0[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[7:0]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:3008
  RAM1K18 block1 (
	.A_DOUT(readData1[17:0]),
	.B_DOUT(block1_B_DOUT[17:0]),
	.BUSY(lsram_2k_BUSY_1),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[7:0]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a1[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[7:0]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2988
  RAM1K18 block2 (
	.A_DOUT(readData2[17:0]),
	.B_DOUT(block2_B_DOUT[17:0]),
	.BUSY(lsram_2k_BUSY_2),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[7:0]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a2[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[7:0]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2968
  RAM1K18 block3 (
	.A_DOUT(readData3[17:0]),
	.B_DOUT(block3_B_DOUT[17:0]),
	.BUSY(lsram_2k_BUSY_3),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[7:0]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a3[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[7:0]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2948
  RAM1K18 block4 (
	.A_DOUT(readData4[17:0]),
	.B_DOUT(block4_B_DOUT[17:0]),
	.BUSY(lsram_2k_BUSY_4),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[7:0]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a4[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[7:0]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2928
  RAM1K18 block5 (
	.A_DOUT(readData5[17:0]),
	.B_DOUT(block5_B_DOUT[17:0]),
	.BUSY(lsram_2k_BUSY_5),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[7:0]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a5[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[7:0]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2908
  RAM1K18 block6 (
	.A_DOUT(readData6[17:0]),
	.B_DOUT(block6_B_DOUT[17:0]),
	.BUSY(lsram_2k_BUSY_6),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[7:0]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a6[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[7:0]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2888
  RAM1K18 block7 (
	.A_DOUT(readData7[17:0]),
	.B_DOUT(block7_B_DOUT[17:0]),
	.BUSY(lsram_2k_BUSY_7),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[7:0]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a7[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[7:0]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
  GND GND_Z (
	.Y(GND)
);
  VCC VCC_Z (
	.Y(VCC)
);
endmodule /* Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s */

module Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_0 (
  sram_wen_mem_m4,
  sram_wen_mem_m3,
  ckRdAddr,
  ram_rdata,
  wen_a3_0_a2_0_a2_0,
  wen_a2_0_a2_0_a2_0,
  wen_a5_0_a2_1_a2_0,
  wen_a6_0_a2_1_a2_0,
  wen_a1_0_a2_0_a2_0,
  wen_a7_0_a2_0_a2_0,
  CoreAHBLite_0_AHBmslave3_HWDATA,
  ahbsram_addr,
  sram_N_3_mux_0,
  FCCC_0_GL0_0,
  Linker_Design_MSS_0_MSS_RESET_N_M2F
)
;
input [0:0] sram_wen_mem_m4 ;
input [1:1] sram_wen_mem_m3 ;
input [13:11] ckRdAddr ;
output [15:8] ram_rdata ;
output [0:0] wen_a3_0_a2_0_a2_0 ;
output [0:0] wen_a2_0_a2_0_a2_0 ;
output [0:0] wen_a5_0_a2_1_a2_0 ;
output [0:0] wen_a6_0_a2_1_a2_0 ;
input [0:0] wen_a1_0_a2_0_a2_0 ;
input [0:0] wen_a7_0_a2_0_a2_0 ;
input [15:8] CoreAHBLite_0_AHBmslave3_HWDATA ;
input [15:0] ahbsram_addr ;
input sram_N_3_mux_0 ;
input FCCC_0_GL0_0 ;
input Linker_Design_MSS_0_MSS_RESET_N_M2F ;
wire sram_N_3_mux_0 ;
wire FCCC_0_GL0_0 ;
wire Linker_Design_MSS_0_MSS_RESET_N_M2F ;
wire [0:0] wen_a0;
wire [0:0] wen_a4;
wire [17:0] readData6;
wire [17:0] readData2;
wire [7:0] readData_7_am_1_1;
wire [7:0] readData_7_am_1;
wire [17:0] readData4;
wire [17:0] readData0;
wire [17:0] readData7;
wire [17:0] readData5;
wire [7:0] readData_7_bm_1_1;
wire [7:0] readData_7_bm_1;
wire [17:0] readData3;
wire [17:0] readData1;
wire [0:0] wen_a6;
wire [0:0] wen_a5;
wire [0:0] wen_a3;
wire [0:0] wen_a2;
wire [0:0] wen_a1;
wire [0:0] wen_a7;
wire [17:0] block0_B_DOUT_0;
wire [17:0] block1_B_DOUT_0;
wire [17:0] block2_B_DOUT_0;
wire [17:0] block3_B_DOUT_0;
wire [17:0] block4_B_DOUT_0;
wire [17:0] block5_B_DOUT_0;
wire [17:0] block6_B_DOUT_0;
wire [17:0] block7_B_DOUT_0;
wire g0_0_a2_2 ;
wire g0_1 ;
wire N_9 ;
wire N_8 ;
wire N_7 ;
wire N_6 ;
wire N_5 ;
wire N_4 ;
wire N_3 ;
wire N_2 ;
wire N_1 ;
wire lsram_2k_BUSY_0 ;
wire VCC ;
wire GND ;
wire lsram_2k_BUSY_1 ;
wire lsram_2k_BUSY_2 ;
wire lsram_2k_BUSY_3 ;
wire lsram_2k_BUSY_4 ;
wire lsram_2k_BUSY_5 ;
wire lsram_2k_BUSY_6 ;
wire lsram_2k_BUSY_7 ;
  CFG4 block0_RNO_0 (
	.A(ahbsram_addr[15]),
	.B(ahbsram_addr[14]),
	.C(ahbsram_addr[13]),
	.D(sram_wen_mem_m4[0]),
	.Y(g0_0_a2_2)
);
defparam block0_RNO_0.INIT=16'h0100;
// @18:950
  CFG4 block0_RNO (
	.A(ahbsram_addr[0]),
	.B(ahbsram_addr[1]),
	.C(g0_0_a2_2),
	.D(sram_N_3_mux_0),
	.Y(wen_a0[0])
);
defparam block0_RNO.INIT=16'h20F0;
  CFG3 block4_RNO_0 (
	.A(ahbsram_addr[15]),
	.B(ahbsram_addr[14]),
	.C(ahbsram_addr[13]),
	.Y(g0_1)
);
defparam block4_RNO_0.INIT=8'h02;
// @18:950
  CFG4 block4_RNO (
	.A(sram_wen_mem_m3[1]),
	.B(sram_N_3_mux_0),
	.C(g0_1),
	.D(sram_wen_mem_m4[0]),
	.Y(wen_a4[0])
);
defparam block4_RNO.INIT=16'hB080;
// @18:1043
  CFG4 \readData_7_am[0]  (
	.A(readData6[0]),
	.B(readData2[0]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[0]),
	.Y(readData_7_am_1[0])
);
defparam \readData_7_am[0] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[0]  (
	.A(readData4[0]),
	.B(readData0[0]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[0])
);
defparam \readData_7_am_1_1[0] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[0]  (
	.A(readData7[0]),
	.B(readData5[0]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[0]),
	.Y(readData_7_bm_1[0])
);
defparam \readData_7_bm[0] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[0]  (
	.A(readData3[0]),
	.B(readData1[0]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[0])
);
defparam \readData_7_bm_1_1[0] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[1]  (
	.A(readData6[1]),
	.B(readData2[1]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[1]),
	.Y(readData_7_am_1[1])
);
defparam \readData_7_am[1] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[1]  (
	.A(readData4[1]),
	.B(readData0[1]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[1])
);
defparam \readData_7_am_1_1[1] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[1]  (
	.A(readData7[1]),
	.B(readData5[1]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[1]),
	.Y(readData_7_bm_1[1])
);
defparam \readData_7_bm[1] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[1]  (
	.A(readData3[1]),
	.B(readData1[1]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[1])
);
defparam \readData_7_bm_1_1[1] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[2]  (
	.A(readData6[2]),
	.B(readData2[2]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[2]),
	.Y(readData_7_am_1[2])
);
defparam \readData_7_am[2] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[2]  (
	.A(readData4[2]),
	.B(readData0[2]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[2])
);
defparam \readData_7_am_1_1[2] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[2]  (
	.A(readData7[2]),
	.B(readData5[2]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[2]),
	.Y(readData_7_bm_1[2])
);
defparam \readData_7_bm[2] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[2]  (
	.A(readData3[2]),
	.B(readData1[2]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[2])
);
defparam \readData_7_bm_1_1[2] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[3]  (
	.A(readData6[3]),
	.B(readData2[3]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[3]),
	.Y(readData_7_am_1[3])
);
defparam \readData_7_am[3] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[3]  (
	.A(readData4[3]),
	.B(readData0[3]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[3])
);
defparam \readData_7_am_1_1[3] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[3]  (
	.A(readData7[3]),
	.B(readData5[3]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[3]),
	.Y(readData_7_bm_1[3])
);
defparam \readData_7_bm[3] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[3]  (
	.A(readData3[3]),
	.B(readData1[3]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[3])
);
defparam \readData_7_bm_1_1[3] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[4]  (
	.A(readData6[4]),
	.B(readData2[4]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[4]),
	.Y(readData_7_am_1[4])
);
defparam \readData_7_am[4] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[4]  (
	.A(readData4[4]),
	.B(readData0[4]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[4])
);
defparam \readData_7_am_1_1[4] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[4]  (
	.A(readData7[4]),
	.B(readData5[4]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[4]),
	.Y(readData_7_bm_1[4])
);
defparam \readData_7_bm[4] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[4]  (
	.A(readData3[4]),
	.B(readData1[4]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[4])
);
defparam \readData_7_bm_1_1[4] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[5]  (
	.A(readData6[5]),
	.B(readData2[5]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[5]),
	.Y(readData_7_am_1[5])
);
defparam \readData_7_am[5] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[5]  (
	.A(readData4[5]),
	.B(readData0[5]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[5])
);
defparam \readData_7_am_1_1[5] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[5]  (
	.A(readData7[5]),
	.B(readData5[5]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[5]),
	.Y(readData_7_bm_1[5])
);
defparam \readData_7_bm[5] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[5]  (
	.A(readData3[5]),
	.B(readData1[5]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[5])
);
defparam \readData_7_bm_1_1[5] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[6]  (
	.A(readData6[6]),
	.B(readData2[6]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[6]),
	.Y(readData_7_am_1[6])
);
defparam \readData_7_am[6] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[6]  (
	.A(readData4[6]),
	.B(readData0[6]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[6])
);
defparam \readData_7_am_1_1[6] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[6]  (
	.A(readData7[6]),
	.B(readData5[6]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[6]),
	.Y(readData_7_bm_1[6])
);
defparam \readData_7_bm[6] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[6]  (
	.A(readData3[6]),
	.B(readData1[6]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[6])
);
defparam \readData_7_bm_1_1[6] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[7]  (
	.A(readData6[7]),
	.B(readData2[7]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[7]),
	.Y(readData_7_am_1[7])
);
defparam \readData_7_am[7] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[7]  (
	.A(readData4[7]),
	.B(readData0[7]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[7])
);
defparam \readData_7_am_1_1[7] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[7]  (
	.A(readData7[7]),
	.B(readData5[7]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[7]),
	.Y(readData_7_bm_1[7])
);
defparam \readData_7_bm[7] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[7]  (
	.A(readData3[7]),
	.B(readData1[7]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[7])
);
defparam \readData_7_bm_1_1[7] .INIT=16'h05F3;
// @18:1043
  CFG3 \readData_7_ns[0]  (
	.A(readData_7_am_1[0]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_1[0]),
	.Y(ram_rdata[8])
);
defparam \readData_7_ns[0] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[1]  (
	.A(readData_7_am_1[1]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_1[1]),
	.Y(ram_rdata[9])
);
defparam \readData_7_ns[1] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[2]  (
	.A(readData_7_am_1[2]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_1[2]),
	.Y(ram_rdata[10])
);
defparam \readData_7_ns[2] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[3]  (
	.A(readData_7_am_1[3]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_1[3]),
	.Y(ram_rdata[11])
);
defparam \readData_7_ns[3] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[4]  (
	.A(readData_7_am_1[4]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_1[4]),
	.Y(ram_rdata[12])
);
defparam \readData_7_ns[4] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[5]  (
	.A(readData_7_am_1[5]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_1[5]),
	.Y(ram_rdata[13])
);
defparam \readData_7_ns[5] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[6]  (
	.A(readData_7_am_1[6]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_1[6]),
	.Y(ram_rdata[14])
);
defparam \readData_7_ns[6] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[7]  (
	.A(readData_7_am_1[7]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_1[7]),
	.Y(ram_rdata[15])
);
defparam \readData_7_ns[7] .INIT=8'hE2;
// @18:950
  CFG3 \wen_a3_0_a2_0_a2_0_cZ[0]  (
	.A(ahbsram_addr[15]),
	.B(ahbsram_addr[14]),
	.C(ahbsram_addr[13]),
	.Y(wen_a3_0_a2_0_a2_0[0])
);
defparam \wen_a3_0_a2_0_a2_0_cZ[0] .INIT=8'h40;
// @18:950
  CFG3 \wen_a2_0_a2_0_a2_0_cZ[0]  (
	.A(ahbsram_addr[15]),
	.B(ahbsram_addr[14]),
	.C(ahbsram_addr[13]),
	.Y(wen_a2_0_a2_0_a2_0[0])
);
defparam \wen_a2_0_a2_0_a2_0_cZ[0] .INIT=8'h04;
// @18:950
  CFG3 \wen_a5_0_a2_1_a2_0_cZ[0]  (
	.A(ahbsram_addr[15]),
	.B(ahbsram_addr[14]),
	.C(ahbsram_addr[13]),
	.Y(wen_a5_0_a2_1_a2_0[0])
);
defparam \wen_a5_0_a2_1_a2_0_cZ[0] .INIT=8'h20;
// @18:950
  CFG3 \wen_a6_0_a2_1_a2_0_cZ[0]  (
	.A(ahbsram_addr[15]),
	.B(ahbsram_addr[14]),
	.C(ahbsram_addr[13]),
	.Y(wen_a6_0_a2_1_a2_0[0])
);
defparam \wen_a6_0_a2_1_a2_0_cZ[0] .INIT=8'h08;
// @18:950
  CFG4 \wen_a6_0_a2_1_a2[0]  (
	.A(sram_wen_mem_m3[1]),
	.B(sram_N_3_mux_0),
	.C(wen_a6_0_a2_1_a2_0[0]),
	.D(sram_wen_mem_m4[0]),
	.Y(wen_a6[0])
);
defparam \wen_a6_0_a2_1_a2[0] .INIT=16'hB080;
// @18:950
  CFG4 \wen_a5_0_a2_1_a2[0]  (
	.A(sram_wen_mem_m3[1]),
	.B(sram_N_3_mux_0),
	.C(wen_a5_0_a2_1_a2_0[0]),
	.D(sram_wen_mem_m4[0]),
	.Y(wen_a5[0])
);
defparam \wen_a5_0_a2_1_a2[0] .INIT=16'hB080;
// @18:950
  CFG4 \wen_a3_0_a2_0_a2[0]  (
	.A(sram_wen_mem_m3[1]),
	.B(sram_N_3_mux_0),
	.C(wen_a3_0_a2_0_a2_0[0]),
	.D(sram_wen_mem_m4[0]),
	.Y(wen_a3[0])
);
defparam \wen_a3_0_a2_0_a2[0] .INIT=16'hB080;
// @18:950
  CFG4 \wen_a2_0_a2_0_a2[0]  (
	.A(sram_wen_mem_m3[1]),
	.B(sram_N_3_mux_0),
	.C(wen_a2_0_a2_0_a2_0[0]),
	.D(sram_wen_mem_m4[0]),
	.Y(wen_a2[0])
);
defparam \wen_a2_0_a2_0_a2[0] .INIT=16'hB080;
// @18:950
  CFG4 \wen_a1_0_a2_0_a2[0]  (
	.A(sram_wen_mem_m3[1]),
	.B(sram_N_3_mux_0),
	.C(wen_a1_0_a2_0_a2_0[0]),
	.D(sram_wen_mem_m4[0]),
	.Y(wen_a1[0])
);
defparam \wen_a1_0_a2_0_a2[0] .INIT=16'hB080;
// @18:950
  CFG4 \wen_a7_0_a2_0_a2[0]  (
	.A(sram_wen_mem_m3[1]),
	.B(sram_N_3_mux_0),
	.C(wen_a7_0_a2_0_a2_0[0]),
	.D(sram_wen_mem_m4[0]),
	.Y(wen_a7[0])
);
defparam \wen_a7_0_a2_0_a2[0] .INIT=16'hB080;
//@20:262
//@20:262
//@20:262
//@20:262
//@20:262
//@20:262
//@20:262
//@20:262
//@20:262
// @18:3028
  RAM1K18 block0 (
	.A_DOUT(readData0[17:0]),
	.B_DOUT(block0_B_DOUT_0[17:0]),
	.BUSY(lsram_2k_BUSY_0),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[15:8]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a0[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[15:8]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:3008
  RAM1K18 block1 (
	.A_DOUT(readData1[17:0]),
	.B_DOUT(block1_B_DOUT_0[17:0]),
	.BUSY(lsram_2k_BUSY_1),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[15:8]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a1[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[15:8]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2988
  RAM1K18 block2 (
	.A_DOUT(readData2[17:0]),
	.B_DOUT(block2_B_DOUT_0[17:0]),
	.BUSY(lsram_2k_BUSY_2),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[15:8]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a2[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[15:8]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2968
  RAM1K18 block3 (
	.A_DOUT(readData3[17:0]),
	.B_DOUT(block3_B_DOUT_0[17:0]),
	.BUSY(lsram_2k_BUSY_3),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[15:8]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a3[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[15:8]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2948
  RAM1K18 block4 (
	.A_DOUT(readData4[17:0]),
	.B_DOUT(block4_B_DOUT_0[17:0]),
	.BUSY(lsram_2k_BUSY_4),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[15:8]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a4[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[15:8]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2928
  RAM1K18 block5 (
	.A_DOUT(readData5[17:0]),
	.B_DOUT(block5_B_DOUT_0[17:0]),
	.BUSY(lsram_2k_BUSY_5),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[15:8]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a5[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[15:8]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2908
  RAM1K18 block6 (
	.A_DOUT(readData6[17:0]),
	.B_DOUT(block6_B_DOUT_0[17:0]),
	.BUSY(lsram_2k_BUSY_6),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[15:8]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a6[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[15:8]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2888
  RAM1K18 block7 (
	.A_DOUT(readData7[17:0]),
	.B_DOUT(block7_B_DOUT_0[17:0]),
	.BUSY(lsram_2k_BUSY_7),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[15:8]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a7[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[15:8]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
  GND GND_Z (
	.Y(GND)
);
  VCC VCC_Z (
	.Y(VCC)
);
endmodule /* Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_0 */

module Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_1 (
  sram_wen_mem_m4,
  ckRdAddr,
  ram_rdata,
  wen_a3_0_a2_0_a2_0,
  sram_wen_mem_m2,
  wen_a0_0_a2_0_a2_0,
  wen_a1_0_a2_0_a2_0,
  wen_a2_0_a2_0_a2_0,
  CoreAHBLite_0_AHBmslave3_HWDATA,
  ahbsram_addr,
  sram_wen_mem_ss3,
  FCCC_0_GL0_0,
  Linker_Design_MSS_0_MSS_RESET_N_M2F
)
;
input [0:0] sram_wen_mem_m4 ;
input [13:11] ckRdAddr ;
output [23:16] ram_rdata ;
input [0:0] wen_a3_0_a2_0_a2_0 ;
input [2:2] sram_wen_mem_m2 ;
input [0:0] wen_a0_0_a2_0_a2_0 ;
input [0:0] wen_a1_0_a2_0_a2_0 ;
input [0:0] wen_a2_0_a2_0_a2_0 ;
input [23:16] CoreAHBLite_0_AHBmslave3_HWDATA ;
input [15:0] ahbsram_addr ;
input sram_wen_mem_ss3 ;
input FCCC_0_GL0_0 ;
input Linker_Design_MSS_0_MSS_RESET_N_M2F ;
wire sram_wen_mem_ss3 ;
wire FCCC_0_GL0_0 ;
wire Linker_Design_MSS_0_MSS_RESET_N_M2F ;
wire [0:0] wen_a4;
wire [0:0] wen_a5;
wire [0:0] wen_a6;
wire [0:0] wen_a7;
wire [17:0] readData6;
wire [17:0] readData2;
wire [7:0] readData_7_am_1_1;
wire [7:0] readData_7_am_0;
wire [17:0] readData4;
wire [17:0] readData0;
wire [17:0] readData7;
wire [17:0] readData5;
wire [7:0] readData_7_bm_1_1;
wire [7:0] readData_7_bm_0;
wire [17:0] readData3;
wire [17:0] readData1;
wire [0:0] wen_a3;
wire [0:0] wen_a0;
wire [0:0] wen_a1;
wire [0:0] wen_a2;
wire [17:0] block0_B_DOUT_1;
wire [17:0] block1_B_DOUT_1;
wire [17:0] block2_B_DOUT_1;
wire [17:0] block3_B_DOUT_1;
wire [17:0] block4_B_DOUT_1;
wire [17:0] block5_B_DOUT_1;
wire [17:0] block6_B_DOUT_1;
wire [17:0] block7_B_DOUT_1;
wire g0_i_2_2 ;
wire g0_i_2_1 ;
wire g0_i_2_0 ;
wire g0_i_2 ;
wire N_9 ;
wire N_8 ;
wire N_7 ;
wire N_6 ;
wire N_5 ;
wire N_4 ;
wire N_3 ;
wire N_2 ;
wire N_1 ;
wire lsram_2k_BUSY_0 ;
wire VCC ;
wire GND ;
wire lsram_2k_BUSY_1 ;
wire lsram_2k_BUSY_2 ;
wire lsram_2k_BUSY_3 ;
wire lsram_2k_BUSY_4 ;
wire lsram_2k_BUSY_5 ;
wire lsram_2k_BUSY_6 ;
wire lsram_2k_BUSY_7 ;
  CFG4 block4_RNO_0 (
	.A(ahbsram_addr[15]),
	.B(ahbsram_addr[14]),
	.C(ahbsram_addr[13]),
	.D(sram_wen_mem_m4[0]),
	.Y(g0_i_2_2)
);
defparam block4_RNO_0.INIT=16'hFDFF;
// @18:950
  CFG4 block4_RNO (
	.A(ahbsram_addr[0]),
	.B(ahbsram_addr[1]),
	.C(g0_i_2_2),
	.D(sram_wen_mem_ss3),
	.Y(wen_a4[0])
);
defparam block4_RNO.INIT=16'h0F04;
  CFG4 block5_RNO_0 (
	.A(ahbsram_addr[15]),
	.B(ahbsram_addr[14]),
	.C(ahbsram_addr[13]),
	.D(sram_wen_mem_m4[0]),
	.Y(g0_i_2_1)
);
defparam block5_RNO_0.INIT=16'hDFFF;
// @18:950
  CFG4 block5_RNO (
	.A(ahbsram_addr[0]),
	.B(ahbsram_addr[1]),
	.C(g0_i_2_1),
	.D(sram_wen_mem_ss3),
	.Y(wen_a5[0])
);
defparam block5_RNO.INIT=16'h0F04;
  CFG4 block6_RNO_0 (
	.A(ahbsram_addr[15]),
	.B(ahbsram_addr[14]),
	.C(ahbsram_addr[13]),
	.D(sram_wen_mem_m4[0]),
	.Y(g0_i_2_0)
);
defparam block6_RNO_0.INIT=16'hF7FF;
// @18:950
  CFG4 block6_RNO (
	.A(ahbsram_addr[0]),
	.B(ahbsram_addr[1]),
	.C(g0_i_2_0),
	.D(sram_wen_mem_ss3),
	.Y(wen_a6[0])
);
defparam block6_RNO.INIT=16'h0F04;
  CFG4 block7_RNO_0 (
	.A(ahbsram_addr[15]),
	.B(ahbsram_addr[14]),
	.C(ahbsram_addr[13]),
	.D(sram_wen_mem_m4[0]),
	.Y(g0_i_2)
);
defparam block7_RNO_0.INIT=16'h7FFF;
// @18:950
  CFG4 block7_RNO (
	.A(ahbsram_addr[0]),
	.B(ahbsram_addr[1]),
	.C(g0_i_2),
	.D(sram_wen_mem_ss3),
	.Y(wen_a7[0])
);
defparam block7_RNO.INIT=16'h0F04;
// @18:1043
  CFG4 \readData_7_am[0]  (
	.A(readData6[0]),
	.B(readData2[0]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[0]),
	.Y(readData_7_am_0[0])
);
defparam \readData_7_am[0] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[0]  (
	.A(readData4[0]),
	.B(readData0[0]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[0])
);
defparam \readData_7_am_1_1[0] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[0]  (
	.A(readData7[0]),
	.B(readData5[0]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[0]),
	.Y(readData_7_bm_0[0])
);
defparam \readData_7_bm[0] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[0]  (
	.A(readData3[0]),
	.B(readData1[0]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[0])
);
defparam \readData_7_bm_1_1[0] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[1]  (
	.A(readData6[1]),
	.B(readData2[1]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[1]),
	.Y(readData_7_am_0[1])
);
defparam \readData_7_am[1] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[1]  (
	.A(readData4[1]),
	.B(readData0[1]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[1])
);
defparam \readData_7_am_1_1[1] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[1]  (
	.A(readData7[1]),
	.B(readData5[1]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[1]),
	.Y(readData_7_bm_0[1])
);
defparam \readData_7_bm[1] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[1]  (
	.A(readData3[1]),
	.B(readData1[1]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[1])
);
defparam \readData_7_bm_1_1[1] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[2]  (
	.A(readData6[2]),
	.B(readData2[2]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[2]),
	.Y(readData_7_am_0[2])
);
defparam \readData_7_am[2] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[2]  (
	.A(readData4[2]),
	.B(readData0[2]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[2])
);
defparam \readData_7_am_1_1[2] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[2]  (
	.A(readData7[2]),
	.B(readData5[2]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[2]),
	.Y(readData_7_bm_0[2])
);
defparam \readData_7_bm[2] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[2]  (
	.A(readData3[2]),
	.B(readData1[2]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[2])
);
defparam \readData_7_bm_1_1[2] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[3]  (
	.A(readData6[3]),
	.B(readData2[3]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[3]),
	.Y(readData_7_am_0[3])
);
defparam \readData_7_am[3] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[3]  (
	.A(readData4[3]),
	.B(readData0[3]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[3])
);
defparam \readData_7_am_1_1[3] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[3]  (
	.A(readData7[3]),
	.B(readData5[3]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[3]),
	.Y(readData_7_bm_0[3])
);
defparam \readData_7_bm[3] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[3]  (
	.A(readData3[3]),
	.B(readData1[3]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[3])
);
defparam \readData_7_bm_1_1[3] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[4]  (
	.A(readData6[4]),
	.B(readData2[4]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[4]),
	.Y(readData_7_am_0[4])
);
defparam \readData_7_am[4] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[4]  (
	.A(readData4[4]),
	.B(readData0[4]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[4])
);
defparam \readData_7_am_1_1[4] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[4]  (
	.A(readData7[4]),
	.B(readData5[4]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[4]),
	.Y(readData_7_bm_0[4])
);
defparam \readData_7_bm[4] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[4]  (
	.A(readData3[4]),
	.B(readData1[4]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[4])
);
defparam \readData_7_bm_1_1[4] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[5]  (
	.A(readData6[5]),
	.B(readData2[5]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[5]),
	.Y(readData_7_am_0[5])
);
defparam \readData_7_am[5] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[5]  (
	.A(readData4[5]),
	.B(readData0[5]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[5])
);
defparam \readData_7_am_1_1[5] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[5]  (
	.A(readData7[5]),
	.B(readData5[5]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[5]),
	.Y(readData_7_bm_0[5])
);
defparam \readData_7_bm[5] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[5]  (
	.A(readData3[5]),
	.B(readData1[5]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[5])
);
defparam \readData_7_bm_1_1[5] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[6]  (
	.A(readData6[6]),
	.B(readData2[6]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[6]),
	.Y(readData_7_am_0[6])
);
defparam \readData_7_am[6] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[6]  (
	.A(readData4[6]),
	.B(readData0[6]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[6])
);
defparam \readData_7_am_1_1[6] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[6]  (
	.A(readData7[6]),
	.B(readData5[6]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[6]),
	.Y(readData_7_bm_0[6])
);
defparam \readData_7_bm[6] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[6]  (
	.A(readData3[6]),
	.B(readData1[6]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[6])
);
defparam \readData_7_bm_1_1[6] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[7]  (
	.A(readData6[7]),
	.B(readData2[7]),
	.C(ckRdAddr[12]),
	.D(readData_7_am_1_1[7]),
	.Y(readData_7_am_0[7])
);
defparam \readData_7_am[7] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_am_1_1[7]  (
	.A(readData4[7]),
	.B(readData0[7]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[7])
);
defparam \readData_7_am_1_1[7] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[7]  (
	.A(readData7[7]),
	.B(readData5[7]),
	.C(ckRdAddr[13]),
	.D(readData_7_bm_1_1[7]),
	.Y(readData_7_bm_0[7])
);
defparam \readData_7_bm[7] .INIT=16'hC0AF;
// @18:1043
  CFG4 \readData_7_bm_1_1[7]  (
	.A(readData3[7]),
	.B(readData1[7]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[7])
);
defparam \readData_7_bm_1_1[7] .INIT=16'h05F3;
// @18:1043
  CFG3 \readData_7_ns[0]  (
	.A(readData_7_am_0[0]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_0[0]),
	.Y(ram_rdata[16])
);
defparam \readData_7_ns[0] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[1]  (
	.A(readData_7_am_0[1]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_0[1]),
	.Y(ram_rdata[17])
);
defparam \readData_7_ns[1] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[2]  (
	.A(readData_7_am_0[2]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_0[2]),
	.Y(ram_rdata[18])
);
defparam \readData_7_ns[2] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[3]  (
	.A(readData_7_am_0[3]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_0[3]),
	.Y(ram_rdata[19])
);
defparam \readData_7_ns[3] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[4]  (
	.A(readData_7_am_0[4]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_0[4]),
	.Y(ram_rdata[20])
);
defparam \readData_7_ns[4] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[5]  (
	.A(readData_7_am_0[5]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_0[5]),
	.Y(ram_rdata[21])
);
defparam \readData_7_ns[5] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[6]  (
	.A(readData_7_am_0[6]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_0[6]),
	.Y(ram_rdata[22])
);
defparam \readData_7_ns[6] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[7]  (
	.A(readData_7_am_0[7]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm_0[7]),
	.Y(ram_rdata[23])
);
defparam \readData_7_ns[7] .INIT=8'hE2;
  CFG4 block3_RNO (
	.A(wen_a3_0_a2_0_a2_0[0]),
	.B(sram_wen_mem_m4[0]),
	.C(sram_wen_mem_m2[2]),
	.D(sram_wen_mem_ss3),
	.Y(wen_a3[0])
);
defparam block3_RNO.INIT=16'h88A0;
// @18:950
  CFG4 \wen_a0_0_a2_0_a2[0]  (
	.A(wen_a0_0_a2_0_a2_0[0]),
	.B(sram_wen_mem_m4[0]),
	.C(sram_wen_mem_m2[2]),
	.D(sram_wen_mem_ss3),
	.Y(wen_a0[0])
);
defparam \wen_a0_0_a2_0_a2[0] .INIT=16'h88A0;
// @18:950
  CFG4 \wen_a1_0_a2_0_a2[0]  (
	.A(wen_a1_0_a2_0_a2_0[0]),
	.B(sram_wen_mem_m4[0]),
	.C(sram_wen_mem_m2[2]),
	.D(sram_wen_mem_ss3),
	.Y(wen_a1[0])
);
defparam \wen_a1_0_a2_0_a2[0] .INIT=16'h88A0;
// @18:950
  CFG4 \wen_a2_0_a2_0_a2[0]  (
	.A(wen_a2_0_a2_0_a2_0[0]),
	.B(sram_wen_mem_m4[0]),
	.C(sram_wen_mem_m2[2]),
	.D(sram_wen_mem_ss3),
	.Y(wen_a2[0])
);
defparam \wen_a2_0_a2_0_a2[0] .INIT=16'h88A0;
//@20:277
//@20:277
//@20:277
//@20:277
//@20:277
//@20:277
//@20:277
//@20:277
//@20:277
// @18:3028
  RAM1K18 block0 (
	.A_DOUT(readData0[17:0]),
	.B_DOUT(block0_B_DOUT_1[17:0]),
	.BUSY(lsram_2k_BUSY_0),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[23:16]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a0[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[23:16]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:3008
  RAM1K18 block1 (
	.A_DOUT(readData1[17:0]),
	.B_DOUT(block1_B_DOUT_1[17:0]),
	.BUSY(lsram_2k_BUSY_1),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[23:16]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a1[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[23:16]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2988
  RAM1K18 block2 (
	.A_DOUT(readData2[17:0]),
	.B_DOUT(block2_B_DOUT_1[17:0]),
	.BUSY(lsram_2k_BUSY_2),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[23:16]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a2[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[23:16]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2968
  RAM1K18 block3 (
	.A_DOUT(readData3[17:0]),
	.B_DOUT(block3_B_DOUT_1[17:0]),
	.BUSY(lsram_2k_BUSY_3),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[23:16]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a3[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[23:16]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2948
  RAM1K18 block4 (
	.A_DOUT(readData4[17:0]),
	.B_DOUT(block4_B_DOUT_1[17:0]),
	.BUSY(lsram_2k_BUSY_4),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[23:16]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a4[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[23:16]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2928
  RAM1K18 block5 (
	.A_DOUT(readData5[17:0]),
	.B_DOUT(block5_B_DOUT_1[17:0]),
	.BUSY(lsram_2k_BUSY_5),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[23:16]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a5[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[23:16]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2908
  RAM1K18 block6 (
	.A_DOUT(readData6[17:0]),
	.B_DOUT(block6_B_DOUT_1[17:0]),
	.BUSY(lsram_2k_BUSY_6),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[23:16]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a6[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[23:16]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2888
  RAM1K18 block7 (
	.A_DOUT(readData7[17:0]),
	.B_DOUT(block7_B_DOUT_1[17:0]),
	.BUSY(lsram_2k_BUSY_7),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[23:16]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a7[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[23:16]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
  GND GND_Z (
	.Y(GND)
);
  VCC VCC_Z (
	.Y(VCC)
);
endmodule /* Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_1 */

module Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_2 (
  sram_wen_mem_m4,
  ckRdAddr,
  ram_rdata,
  CoreAHBLite_0_AHBmslave3_HWDATA,
  ahbsram_addr,
  sram_wen_mem_ss3,
  FCCC_0_GL0_0,
  Linker_Design_MSS_0_MSS_RESET_N_M2F
)
;
input [0:0] sram_wen_mem_m4 ;
input [13:11] ckRdAddr ;
output [31:24] ram_rdata ;
input [31:24] CoreAHBLite_0_AHBmslave3_HWDATA ;
input [15:0] ahbsram_addr ;
input sram_wen_mem_ss3 ;
input FCCC_0_GL0_0 ;
input Linker_Design_MSS_0_MSS_RESET_N_M2F ;
wire sram_wen_mem_ss3 ;
wire FCCC_0_GL0_0 ;
wire Linker_Design_MSS_0_MSS_RESET_N_M2F ;
wire [0:0] wen_a0;
wire [0:0] wen_a1;
wire [0:0] wen_a2;
wire [0:0] wen_a3;
wire [0:0] wen_a4;
wire [0:0] wen_a5;
wire [0:0] wen_a6;
wire [0:0] wen_a7;
wire [7:0] readData_7_am_1_1;
wire [17:0] readData6;
wire [17:0] readData2;
wire [7:0] readData_7_am;
wire [17:0] readData4;
wire [17:0] readData0;
wire [7:0] readData_7_bm_1_1;
wire [17:0] readData7;
wire [17:0] readData5;
wire [7:0] readData_7_bm;
wire [17:0] readData3;
wire [17:0] readData1;
wire [17:0] block0_B_DOUT_2;
wire [17:0] block1_B_DOUT_2;
wire [17:0] block2_B_DOUT_2;
wire [17:0] block3_B_DOUT_2;
wire [17:0] block4_B_DOUT_2;
wire [17:0] block5_B_DOUT_2;
wire [17:0] block6_B_DOUT_2;
wire [17:0] block7_B_DOUT_2;
wire g0_i_2_6 ;
wire g0_i_2_5 ;
wire g0_i_2_4 ;
wire g0_i_2_3 ;
wire g0_i_2_2 ;
wire g0_i_2_1 ;
wire g0_i_2_0 ;
wire g0_i_2 ;
wire N_9 ;
wire N_8 ;
wire N_7 ;
wire N_6 ;
wire N_5 ;
wire N_4 ;
wire N_3 ;
wire N_2 ;
wire N_1 ;
wire lsram_2k_BUSY_0 ;
wire VCC ;
wire GND ;
wire lsram_2k_BUSY_1 ;
wire lsram_2k_BUSY_2 ;
wire lsram_2k_BUSY_3 ;
wire lsram_2k_BUSY_4 ;
wire lsram_2k_BUSY_5 ;
wire lsram_2k_BUSY_6 ;
wire lsram_2k_BUSY_7 ;
  CFG4 block0_RNO_0 (
	.A(ahbsram_addr[15]),
	.B(ahbsram_addr[14]),
	.C(ahbsram_addr[13]),
	.D(sram_wen_mem_m4[0]),
	.Y(g0_i_2_6)
);
defparam block0_RNO_0.INIT=16'hFEFF;
// @18:950
  CFG4 block0_RNO (
	.A(ahbsram_addr[0]),
	.B(ahbsram_addr[1]),
	.C(g0_i_2_6),
	.D(sram_wen_mem_ss3),
	.Y(wen_a0[0])
);
defparam block0_RNO.INIT=16'h0F08;
  CFG4 block1_RNO_0 (
	.A(ahbsram_addr[15]),
	.B(ahbsram_addr[14]),
	.C(ahbsram_addr[13]),
	.D(sram_wen_mem_m4[0]),
	.Y(g0_i_2_5)
);
defparam block1_RNO_0.INIT=16'hEFFF;
// @18:950
  CFG4 block1_RNO (
	.A(ahbsram_addr[0]),
	.B(ahbsram_addr[1]),
	.C(g0_i_2_5),
	.D(sram_wen_mem_ss3),
	.Y(wen_a1[0])
);
defparam block1_RNO.INIT=16'h0F08;
  CFG4 block2_RNO_0 (
	.A(ahbsram_addr[15]),
	.B(ahbsram_addr[14]),
	.C(ahbsram_addr[13]),
	.D(sram_wen_mem_m4[0]),
	.Y(g0_i_2_4)
);
defparam block2_RNO_0.INIT=16'hFBFF;
// @18:950
  CFG4 block2_RNO (
	.A(ahbsram_addr[0]),
	.B(ahbsram_addr[1]),
	.C(g0_i_2_4),
	.D(sram_wen_mem_ss3),
	.Y(wen_a2[0])
);
defparam block2_RNO.INIT=16'h0F08;
  CFG4 block3_RNO_0 (
	.A(ahbsram_addr[15]),
	.B(ahbsram_addr[14]),
	.C(ahbsram_addr[13]),
	.D(sram_wen_mem_m4[0]),
	.Y(g0_i_2_3)
);
defparam block3_RNO_0.INIT=16'hBFFF;
// @18:950
  CFG4 block3_RNO (
	.A(ahbsram_addr[0]),
	.B(ahbsram_addr[1]),
	.C(g0_i_2_3),
	.D(sram_wen_mem_ss3),
	.Y(wen_a3[0])
);
defparam block3_RNO.INIT=16'h0F08;
  CFG4 block4_RNO_0 (
	.A(ahbsram_addr[15]),
	.B(ahbsram_addr[14]),
	.C(ahbsram_addr[13]),
	.D(sram_wen_mem_m4[0]),
	.Y(g0_i_2_2)
);
defparam block4_RNO_0.INIT=16'hFDFF;
// @18:950
  CFG4 block4_RNO (
	.A(ahbsram_addr[0]),
	.B(ahbsram_addr[1]),
	.C(g0_i_2_2),
	.D(sram_wen_mem_ss3),
	.Y(wen_a4[0])
);
defparam block4_RNO.INIT=16'h0F08;
  CFG4 block5_RNO_0 (
	.A(ahbsram_addr[15]),
	.B(ahbsram_addr[14]),
	.C(ahbsram_addr[13]),
	.D(sram_wen_mem_m4[0]),
	.Y(g0_i_2_1)
);
defparam block5_RNO_0.INIT=16'hDFFF;
// @18:950
  CFG4 block5_RNO (
	.A(ahbsram_addr[0]),
	.B(ahbsram_addr[1]),
	.C(g0_i_2_1),
	.D(sram_wen_mem_ss3),
	.Y(wen_a5[0])
);
defparam block5_RNO.INIT=16'h0F08;
  CFG4 block6_RNO_0 (
	.A(ahbsram_addr[15]),
	.B(ahbsram_addr[14]),
	.C(ahbsram_addr[13]),
	.D(sram_wen_mem_m4[0]),
	.Y(g0_i_2_0)
);
defparam block6_RNO_0.INIT=16'hF7FF;
// @18:950
  CFG4 block6_RNO (
	.A(ahbsram_addr[0]),
	.B(ahbsram_addr[1]),
	.C(g0_i_2_0),
	.D(sram_wen_mem_ss3),
	.Y(wen_a6[0])
);
defparam block6_RNO.INIT=16'h0F08;
  CFG4 block7_RNO_0 (
	.A(ahbsram_addr[15]),
	.B(ahbsram_addr[14]),
	.C(ahbsram_addr[13]),
	.D(sram_wen_mem_m4[0]),
	.Y(g0_i_2)
);
defparam block7_RNO_0.INIT=16'h7FFF;
// @18:950
  CFG4 block7_RNO (
	.A(ahbsram_addr[0]),
	.B(ahbsram_addr[1]),
	.C(g0_i_2),
	.D(sram_wen_mem_ss3),
	.Y(wen_a7[0])
);
defparam block7_RNO.INIT=16'h0F08;
// @18:1043
  CFG4 \readData_7_am[0]  (
	.A(ckRdAddr[12]),
	.B(readData_7_am_1_1[0]),
	.C(readData6[0]),
	.D(readData2[0]),
	.Y(readData_7_am[0])
);
defparam \readData_7_am[0] .INIT=16'hB931;
// @18:1043
  CFG4 \readData_7_am_1_1[0]  (
	.A(readData4[0]),
	.B(readData0[0]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[0])
);
defparam \readData_7_am_1_1[0] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[0]  (
	.A(ckRdAddr[13]),
	.B(readData_7_bm_1_1[0]),
	.C(readData7[0]),
	.D(readData5[0]),
	.Y(readData_7_bm[0])
);
defparam \readData_7_bm[0] .INIT=16'hB931;
// @18:1043
  CFG4 \readData_7_bm_1_1[0]  (
	.A(readData3[0]),
	.B(readData1[0]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[0])
);
defparam \readData_7_bm_1_1[0] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[1]  (
	.A(ckRdAddr[12]),
	.B(readData_7_am_1_1[1]),
	.C(readData6[1]),
	.D(readData2[1]),
	.Y(readData_7_am[1])
);
defparam \readData_7_am[1] .INIT=16'hB931;
// @18:1043
  CFG4 \readData_7_am_1_1[1]  (
	.A(readData4[1]),
	.B(readData0[1]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[1])
);
defparam \readData_7_am_1_1[1] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[1]  (
	.A(ckRdAddr[13]),
	.B(readData_7_bm_1_1[1]),
	.C(readData7[1]),
	.D(readData5[1]),
	.Y(readData_7_bm[1])
);
defparam \readData_7_bm[1] .INIT=16'hB931;
// @18:1043
  CFG4 \readData_7_bm_1_1[1]  (
	.A(readData3[1]),
	.B(readData1[1]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[1])
);
defparam \readData_7_bm_1_1[1] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[2]  (
	.A(ckRdAddr[12]),
	.B(readData_7_am_1_1[2]),
	.C(readData6[2]),
	.D(readData2[2]),
	.Y(readData_7_am[2])
);
defparam \readData_7_am[2] .INIT=16'hB931;
// @18:1043
  CFG4 \readData_7_am_1_1[2]  (
	.A(readData4[2]),
	.B(readData0[2]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[2])
);
defparam \readData_7_am_1_1[2] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[2]  (
	.A(ckRdAddr[13]),
	.B(readData_7_bm_1_1[2]),
	.C(readData7[2]),
	.D(readData5[2]),
	.Y(readData_7_bm[2])
);
defparam \readData_7_bm[2] .INIT=16'hB931;
// @18:1043
  CFG4 \readData_7_bm_1_1[2]  (
	.A(readData3[2]),
	.B(readData1[2]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[2])
);
defparam \readData_7_bm_1_1[2] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[3]  (
	.A(ckRdAddr[12]),
	.B(readData_7_am_1_1[3]),
	.C(readData6[3]),
	.D(readData2[3]),
	.Y(readData_7_am[3])
);
defparam \readData_7_am[3] .INIT=16'hB931;
// @18:1043
  CFG4 \readData_7_am_1_1[3]  (
	.A(readData4[3]),
	.B(readData0[3]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[3])
);
defparam \readData_7_am_1_1[3] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[3]  (
	.A(ckRdAddr[13]),
	.B(readData_7_bm_1_1[3]),
	.C(readData7[3]),
	.D(readData5[3]),
	.Y(readData_7_bm[3])
);
defparam \readData_7_bm[3] .INIT=16'hB931;
// @18:1043
  CFG4 \readData_7_bm_1_1[3]  (
	.A(readData3[3]),
	.B(readData1[3]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[3])
);
defparam \readData_7_bm_1_1[3] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[4]  (
	.A(ckRdAddr[12]),
	.B(readData_7_am_1_1[4]),
	.C(readData6[4]),
	.D(readData2[4]),
	.Y(readData_7_am[4])
);
defparam \readData_7_am[4] .INIT=16'hB931;
// @18:1043
  CFG4 \readData_7_am_1_1[4]  (
	.A(readData4[4]),
	.B(readData0[4]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[4])
);
defparam \readData_7_am_1_1[4] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[4]  (
	.A(ckRdAddr[13]),
	.B(readData_7_bm_1_1[4]),
	.C(readData7[4]),
	.D(readData5[4]),
	.Y(readData_7_bm[4])
);
defparam \readData_7_bm[4] .INIT=16'hB931;
// @18:1043
  CFG4 \readData_7_bm_1_1[4]  (
	.A(readData3[4]),
	.B(readData1[4]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[4])
);
defparam \readData_7_bm_1_1[4] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[5]  (
	.A(ckRdAddr[12]),
	.B(readData_7_am_1_1[5]),
	.C(readData6[5]),
	.D(readData2[5]),
	.Y(readData_7_am[5])
);
defparam \readData_7_am[5] .INIT=16'hB931;
// @18:1043
  CFG4 \readData_7_am_1_1[5]  (
	.A(readData4[5]),
	.B(readData0[5]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[5])
);
defparam \readData_7_am_1_1[5] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[5]  (
	.A(ckRdAddr[13]),
	.B(readData_7_bm_1_1[5]),
	.C(readData7[5]),
	.D(readData5[5]),
	.Y(readData_7_bm[5])
);
defparam \readData_7_bm[5] .INIT=16'hB931;
// @18:1043
  CFG4 \readData_7_bm_1_1[5]  (
	.A(readData3[5]),
	.B(readData1[5]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[5])
);
defparam \readData_7_bm_1_1[5] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[6]  (
	.A(ckRdAddr[12]),
	.B(readData_7_am_1_1[6]),
	.C(readData6[6]),
	.D(readData2[6]),
	.Y(readData_7_am[6])
);
defparam \readData_7_am[6] .INIT=16'hB931;
// @18:1043
  CFG4 \readData_7_am_1_1[6]  (
	.A(readData4[6]),
	.B(readData0[6]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[6])
);
defparam \readData_7_am_1_1[6] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[6]  (
	.A(ckRdAddr[13]),
	.B(readData_7_bm_1_1[6]),
	.C(readData7[6]),
	.D(readData5[6]),
	.Y(readData_7_bm[6])
);
defparam \readData_7_bm[6] .INIT=16'hB931;
// @18:1043
  CFG4 \readData_7_bm_1_1[6]  (
	.A(readData3[6]),
	.B(readData1[6]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[6])
);
defparam \readData_7_bm_1_1[6] .INIT=16'h05F3;
// @18:1043
  CFG4 \readData_7_am[7]  (
	.A(ckRdAddr[12]),
	.B(readData_7_am_1_1[7]),
	.C(readData6[7]),
	.D(readData2[7]),
	.Y(readData_7_am[7])
);
defparam \readData_7_am[7] .INIT=16'hB931;
// @18:1043
  CFG4 \readData_7_am_1_1[7]  (
	.A(readData4[7]),
	.B(readData0[7]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_am_1_1[7])
);
defparam \readData_7_am_1_1[7] .INIT=16'h0F53;
// @18:1043
  CFG4 \readData_7_bm[7]  (
	.A(ckRdAddr[12]),
	.B(readData_7_bm_1_1[7]),
	.C(readData7[7]),
	.D(readData3[7]),
	.Y(readData_7_bm[7])
);
defparam \readData_7_bm[7] .INIT=16'hB931;
// @18:1043
  CFG4 \readData_7_bm_1_1[7]  (
	.A(readData5[7]),
	.B(readData1[7]),
	.C(ckRdAddr[13]),
	.D(ckRdAddr[12]),
	.Y(readData_7_bm_1_1[7])
);
defparam \readData_7_bm_1_1[7] .INIT=16'h0F53;
// @18:1043
  CFG3 \readData_7_ns[0]  (
	.A(readData_7_am[0]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm[0]),
	.Y(ram_rdata[24])
);
defparam \readData_7_ns[0] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[1]  (
	.A(readData_7_am[1]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm[1]),
	.Y(ram_rdata[25])
);
defparam \readData_7_ns[1] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[2]  (
	.A(readData_7_am[2]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm[2]),
	.Y(ram_rdata[26])
);
defparam \readData_7_ns[2] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[3]  (
	.A(readData_7_am[3]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm[3]),
	.Y(ram_rdata[27])
);
defparam \readData_7_ns[3] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[4]  (
	.A(readData_7_am[4]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm[4]),
	.Y(ram_rdata[28])
);
defparam \readData_7_ns[4] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[5]  (
	.A(readData_7_am[5]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm[5]),
	.Y(ram_rdata[29])
);
defparam \readData_7_ns[5] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[6]  (
	.A(readData_7_am[6]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm[6]),
	.Y(ram_rdata[30])
);
defparam \readData_7_ns[6] .INIT=8'hE2;
// @18:1043
  CFG3 \readData_7_ns[7]  (
	.A(readData_7_am[7]),
	.B(ckRdAddr[11]),
	.C(readData_7_bm[7]),
	.Y(ram_rdata[31])
);
defparam \readData_7_ns[7] .INIT=8'hE2;
//@20:292
//@20:292
//@20:292
//@20:292
//@20:292
//@20:292
//@20:292
//@20:292
//@20:292
// @18:3028
  RAM1K18 block0 (
	.A_DOUT(readData0[17:0]),
	.B_DOUT(block0_B_DOUT_2[17:0]),
	.BUSY(lsram_2k_BUSY_0),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[31:24]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a0[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[31:24]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:3008
  RAM1K18 block1 (
	.A_DOUT(readData1[17:0]),
	.B_DOUT(block1_B_DOUT_2[17:0]),
	.BUSY(lsram_2k_BUSY_1),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[31:24]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a1[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[31:24]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2988
  RAM1K18 block2 (
	.A_DOUT(readData2[17:0]),
	.B_DOUT(block2_B_DOUT_2[17:0]),
	.BUSY(lsram_2k_BUSY_2),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[31:24]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a2[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[31:24]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2968
  RAM1K18 block3 (
	.A_DOUT(readData3[17:0]),
	.B_DOUT(block3_B_DOUT_2[17:0]),
	.BUSY(lsram_2k_BUSY_3),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[31:24]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a3[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[31:24]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2948
  RAM1K18 block4 (
	.A_DOUT(readData4[17:0]),
	.B_DOUT(block4_B_DOUT_2[17:0]),
	.BUSY(lsram_2k_BUSY_4),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[31:24]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a4[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[31:24]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2928
  RAM1K18 block5 (
	.A_DOUT(readData5[17:0]),
	.B_DOUT(block5_B_DOUT_2[17:0]),
	.BUSY(lsram_2k_BUSY_5),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[31:24]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a5[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[31:24]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2908
  RAM1K18 block6 (
	.A_DOUT(readData6[17:0]),
	.B_DOUT(block6_B_DOUT_2[17:0]),
	.BUSY(lsram_2k_BUSY_6),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[31:24]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a6[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[31:24]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
// @18:2888
  RAM1K18 block7 (
	.A_DOUT(readData7[17:0]),
	.B_DOUT(block7_B_DOUT_2[17:0]),
	.BUSY(lsram_2k_BUSY_7),
	.A_CLK(FCCC_0_GL0_0),
	.A_DOUT_CLK(VCC),
	.A_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.A_DOUT_EN(VCC),
	.A_BLK({VCC, VCC, VCC}),
	.A_DOUT_ARST_N(VCC),
	.A_DOUT_SRST_N(VCC),
	.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[31:24]}),
	.A_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.A_WEN({GND, wen_a7[0]}),
	.B_CLK(FCCC_0_GL0_0),
	.B_DOUT_CLK(VCC),
	.B_ARST_N(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.B_DOUT_EN(VCC),
	.B_BLK({VCC, VCC, VCC}),
	.B_DOUT_ARST_N(VCC),
	.B_DOUT_SRST_N(VCC),
	.B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, CoreAHBLite_0_AHBmslave3_HWDATA[31:24]}),
	.B_ADDR({ahbsram_addr[12:2], GND, GND, GND}),
	.B_WEN({GND, GND}),
	.A_EN(VCC),
	.A_DOUT_LAT(VCC),
	.A_WIDTH({GND, VCC, VCC}),
	.A_WMODE(GND),
	.B_EN(VCC),
	.B_DOUT_LAT(VCC),
	.B_WIDTH({GND, VCC, VCC}),
	.B_WMODE(GND),
	.SII_LOCK(GND)
);
  GND GND_Z (
	.Y(GND)
);
  VCC VCC_Z (
	.Y(VCC)
);
endmodule /* Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_2 */

module Linker_Design_COREAHBLSRAM_0_SramCtrlIf_0s_16384s_512s_32s_0_1_2 (
  CoreAHBLite_0_AHBmslave3_HRDATA,
  ahbcurr_state,
  MASTERADDRINPROG_i_a2_c,
  ahbsram_size_0_0,
  SADDRSEL_1,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE,
  regHSIZE,
  PREGATEDHADDR,
  SADDRSEL_2,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0,
  arbRegSMCurrentState_3,
  arbRegSMCurrentState_0,
  MASTERADDRINPROG_i_a2_d_c_c,
  MASTERADDRINPROG_i_a2_0_0_0_0,
  ahbsram_addr,
  CoreAHBLite_0_AHBmslave3_HWDATA,
  Linker_Design_MSS_0_MSS_RESET_N_M2F,
  FCCC_0_GL0_0,
  sramahb_ack,
  ahbsram_N_4,
  masterRegAddrSel,
  regHTRANS,
  CoreAHBLite_0_AHBmslave3_HREADY,
  ahbsram_req_d1,
  ahbsram_write,
  d_N_3_mux
)
;
output [31:0] CoreAHBLite_0_AHBmslave3_HRDATA ;
input [1:0] ahbcurr_state ;
input [0:0] MASTERADDRINPROG_i_a2_c ;
input [1:1] ahbsram_size_0_0 ;
input [7:7] SADDRSEL_1 ;
input [1:1] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE ;
input [1:1] regHSIZE ;
input [28:28] PREGATEDHADDR ;
input [2:2] SADDRSEL_2 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0 ;
input arbRegSMCurrentState_3 ;
input arbRegSMCurrentState_0 ;
input [0:0] MASTERADDRINPROG_i_a2_d_c_c ;
input [0:0] MASTERADDRINPROG_i_a2_0_0_0_0 ;
input [15:0] ahbsram_addr ;
input [31:0] CoreAHBLite_0_AHBmslave3_HWDATA ;
input Linker_Design_MSS_0_MSS_RESET_N_M2F ;
input FCCC_0_GL0_0 ;
output sramahb_ack ;
input ahbsram_N_4 ;
input masterRegAddrSel ;
input regHTRANS ;
input CoreAHBLite_0_AHBmslave3_HREADY ;
input ahbsram_req_d1 ;
input ahbsram_write ;
input d_N_3_mux ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0 ;
wire arbRegSMCurrentState_3 ;
wire arbRegSMCurrentState_0 ;
wire Linker_Design_MSS_0_MSS_RESET_N_M2F ;
wire FCCC_0_GL0_0 ;
wire sramahb_ack ;
wire ahbsram_N_4 ;
wire masterRegAddrSel ;
wire regHTRANS ;
wire CoreAHBLite_0_AHBmslave3_HREADY ;
wire ahbsram_req_d1 ;
wire ahbsram_write ;
wire d_N_3_mux ;
wire [31:0] ram_rdata;
wire [1:0] sramcurr_state;
wire [1:0] sramcurr_state_ns;
wire [0:0] sram_wen_mem_m4;
wire [1:1] sram_wen_mem_m3;
wire [0:0] sram_wen_mem_m3_0;
wire [2:2] sram_wen_mem_m2;
wire [13:11] ckRdAddr;
wire [0:0] wen_a7_0_a2_0_a2_0;
wire [0:0] wen_a1_0_a2_0_a2_0;
wire [0:0] wen_a0_0_a2_0_a2_0;
wire [0:0] wen_a6_0_a2_1_a2_0;
wire [0:0] wen_a5_0_a2_1_a2_0;
wire [0:0] wen_a3_0_a2_0_a2_0;
wire [0:0] wen_a2_0_a2_0_a2_0;
wire VCC ;
wire sram_ren_d_Z ;
wire GND ;
wire sram_done_Z ;
wire sram_ren_0_sqmuxa ;
wire N_40_i_0 ;
wire sram_ren_1_sqmuxa ;
wire sram_m1_e_0_1_0_1 ;
wire sram_m6_i_1 ;
wire sram_wen_mem_ss3_1_Z ;
wire sramahb_ack_RNI64JU2_Z ;
wire sram_wen_mem_ss3_Z ;
wire sram_m6_i_a4_0 ;
wire sram_m2_e_0_Z ;
wire sramahb_ack_RNIUTM83_Z ;
wire sram_N_3_mux_0 ;
wire sram_m1_e_0_1 ;
wire sram_N_3_mux ;
wire N_20 ;
wire N_19 ;
wire N_18 ;
// @20:373
  SLE \sramahb_rdata[0]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[0]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[0]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[1]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[1]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[1]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[2]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[2]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[2]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[3]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[3]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[3]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[4]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[4]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[4]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[5]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[5]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[5]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[6]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[6]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[6]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[7]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[7]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[7]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[8]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[8]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[8]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[9]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[9]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[9]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[10]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[10]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[10]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[11]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[11]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[11]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[12]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[12]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[12]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[13]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[13]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[13]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[14]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[14]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[14]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[15]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[15]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[15]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[16]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[16]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[16]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[17]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[17]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[17]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[18]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[18]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[18]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[19]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[19]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[19]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[20]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[20]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[20]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[21]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[21]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[21]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[22]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[22]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[22]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[23]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[23]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[23]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[24]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[24]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[24]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[25]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[25]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[25]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[26]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[26]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[26]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[27]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[27]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[27]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[28]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[28]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[28]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[29]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[29]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[29]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[30]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[30]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[30]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:373
  SLE \sramahb_rdata[31]  (
	.Q(CoreAHBLite_0_AHBmslave3_HRDATA[31]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(ram_rdata[31]),
	.EN(sram_ren_d_Z),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:127
  SLE \sramcurr_state[0]  (
	.Q(sramcurr_state[0]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(sramcurr_state_ns[0]),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:127
  SLE \sramcurr_state[1]  (
	.Q(sramcurr_state[1]),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(sramcurr_state_ns[1]),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:396
  SLE sram_done (
	.Q(sram_done_Z),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(sram_ren_0_sqmuxa),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:409
  SLE sramahb_ack_Z (
	.Q(sramahb_ack),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(N_40_i_0),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:385
  SLE sram_ren_d (
	.Q(sram_ren_d_Z),
	.ADn(VCC),
	.ALn(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.CLK(FCCC_0_GL0_0),
	.D(sram_ren_1_sqmuxa),
	.EN(VCC),
	.LAT(GND),
	.SD(GND),
	.SLn(VCC)
);
// @20:184
  CFG4 sramahb_ack_RNIP6VA1 (
	.A(ahbcurr_state[0]),
	.B(ahbcurr_state[1]),
	.C(MASTERADDRINPROG_i_a2_c[0]),
	.D(sramahb_ack),
	.Y(sram_m1_e_0_1_0_1)
);
defparam sramahb_ack_RNIP6VA1.INIT=16'h0FEF;
// @20:184
  CFG4 sram_wen_mem_ss3 (
	.A(ahbsram_size_0_0[1]),
	.B(sram_m6_i_1),
	.C(sram_wen_mem_ss3_1_Z),
	.D(sramahb_ack_RNI64JU2_Z),
	.Y(sram_wen_mem_ss3_Z)
);
defparam sram_wen_mem_ss3.INIT=16'hFFAE;
// @20:184
  CFG4 sram_wen_mem_ss3_1 (
	.A(SADDRSEL_1[7]),
	.B(ahbsram_N_4),
	.C(sram_m6_i_a4_0),
	.D(sram_m2_e_0_Z),
	.Y(sram_wen_mem_ss3_1_Z)
);
defparam sram_wen_mem_ss3_1.INIT=16'h73F3;
// @20:184
  CFG4 sramahb_ack_RNI2AMV8 (
	.A(sram_m6_i_1),
	.B(ahbsram_size_0_0[1]),
	.C(sramahb_ack_RNIUTM83_Z),
	.D(sramahb_ack_RNI64JU2_Z),
	.Y(sram_N_3_mux_0)
);
defparam sramahb_ack_RNI2AMV8.INIT=16'h0032;
// @20:188
  CFG3 sramahb_ack_RNIUTM83 (
	.A(sram_m2_e_0_Z),
	.B(SADDRSEL_1[7]),
	.C(sram_m6_i_a4_0),
	.Y(sramahb_ack_RNIUTM83_Z)
);
defparam sramahb_ack_RNIUTM83.INIT=8'h70;
// @20:184
  CFG4 sramahb_ack_RNI8TTF2 (
	.A(sram_m1_e_0_1_0_1),
	.B(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE[1]),
	.C(regHSIZE[1]),
	.D(masterRegAddrSel),
	.Y(sram_m1_e_0_1)
);
defparam sramahb_ack_RNI8TTF2.INIT=16'hAFBB;
// @20:184
  CFG3 sram_ren_0_sqmuxa_1_0_a2_RNIH5941 (
	.A(ahbsram_addr[1]),
	.B(sram_wen_mem_m4[0]),
	.C(ahbsram_addr[0]),
	.Y(sram_wen_mem_m3[1])
);
defparam sram_ren_0_sqmuxa_1_0_a2_RNIH5941.INIT=8'h40;
// @20:184
  CFG4 sramahb_ack_RNI64JU2 (
	.A(PREGATEDHADDR[28]),
	.B(sram_m1_e_0_1),
	.C(SADDRSEL_1[7]),
	.D(SADDRSEL_2[2]),
	.Y(sramahb_ack_RNI64JU2_Z)
);
defparam sramahb_ack_RNI64JU2.INIT=16'h2000;
// @20:184
  CFG2 \sram_wen_mem_m3_0[0]  (
	.A(ahbsram_addr[1]),
	.B(ahbsram_addr[0]),
	.Y(sram_wen_mem_m3_0[0])
);
defparam \sram_wen_mem_m3_0[0] .INIT=4'h1;
// @20:188
  CFG4 sram_m2_e_0 (
	.A(masterRegAddrSel),
	.B(regHTRANS),
	.C(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3),
	.D(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0),
	.Y(sram_m2_e_0_Z)
);
defparam sram_m2_e_0.INIT=16'h8D88;
// @20:188
  CFG4 sramahb_ack_RNILKSH1 (
	.A(sramahb_ack),
	.B(arbRegSMCurrentState_3),
	.C(arbRegSMCurrentState_0),
	.D(CoreAHBLite_0_AHBmslave3_HREADY),
	.Y(sram_m6_i_a4_0)
);
defparam sramahb_ack_RNILKSH1.INIT=16'h0302;
// @20:188
  CFG4 sramahb_ack_RNI4AE81 (
	.A(ahbcurr_state[1]),
	.B(sramahb_ack),
	.C(ahbcurr_state[0]),
	.D(ahbsram_addr[1]),
	.Y(sram_N_3_mux)
);
defparam sramahb_ack_RNI4AE81.INIT=16'h00CD;
// @20:143
  CFG4 sram_ren_0_sqmuxa_0_a2 (
	.A(ahbsram_req_d1),
	.B(sramcurr_state[1]),
	.C(sramcurr_state[0]),
	.D(CoreAHBLite_0_AHBmslave3_HREADY),
	.Y(sram_ren_0_sqmuxa)
);
defparam sram_ren_0_sqmuxa_0_a2.INIT=16'h0001;
// @20:409
  CFG3 sramahb_ack_RNO (
	.A(sramcurr_state[0]),
	.B(sram_done_Z),
	.C(sramcurr_state[1]),
	.Y(N_40_i_0)
);
defparam sramahb_ack_RNO.INIT=8'hC8;
// @20:143
  CFG3 sram_ren_0_sqmuxa_1_0_a2 (
	.A(sramcurr_state[0]),
	.B(ahbsram_write),
	.C(sramcurr_state[1]),
	.Y(sram_wen_mem_m4[0])
);
defparam sram_ren_0_sqmuxa_1_0_a2.INIT=8'h04;
// @20:143
  CFG2 sram_ren_1_sqmuxa_0_a2 (
	.A(ahbsram_write),
	.B(sram_ren_0_sqmuxa),
	.Y(sram_ren_1_sqmuxa)
);
defparam sram_ren_1_sqmuxa_0_a2.INIT=4'h4;
// @20:184
  CFG3 \sram_wen_mem_m2[2]  (
	.A(ahbsram_addr[1]),
	.B(sram_wen_mem_m4[0]),
	.C(ahbsram_addr[0]),
	.Y(sram_wen_mem_m2[2])
);
defparam \sram_wen_mem_m2[2] .INIT=8'h08;
// @20:127
  CFG4 \sramcurr_state_ns_1_0_.m5  (
	.A(sram_done_Z),
	.B(sramcurr_state[1]),
	.C(sramcurr_state[0]),
	.D(ahbsram_write),
	.Y(sramcurr_state_ns[0])
);
defparam \sramcurr_state_ns_1_0_.m5 .INIT=16'h1310;
// @20:188
  CFG4 sramahb_ack_RNIKE1C2 (
	.A(MASTERADDRINPROG_i_a2_d_c_c[0]),
	.B(MASTERADDRINPROG_i_a2_0_0_0_0[0]),
	.C(d_N_3_mux),
	.D(sram_N_3_mux),
	.Y(sram_m6_i_1)
);
defparam sramahb_ack_RNIKE1C2.INIT=16'h770F;
// @20:127
  CFG4 \sramcurr_state_ns_1_0_.m8  (
	.A(sramcurr_state[0]),
	.B(sram_ren_1_sqmuxa),
	.C(sram_done_Z),
	.D(sramcurr_state[1]),
	.Y(sramcurr_state_ns[1])
);
defparam \sramcurr_state_ns_1_0_.m8 .INIT=16'h0544;
//@20:127
// @20:247
  Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s \genblk1.byte_0  (
	.ckRdAddr(ckRdAddr[13:11]),
	.ram_rdata(ram_rdata[7:0]),
	.wen_a7_0_a2_0_a2_0(wen_a7_0_a2_0_a2_0[0]),
	.wen_a1_0_a2_0_a2_0(wen_a1_0_a2_0_a2_0[0]),
	.wen_a0_0_a2_0_a2_0(wen_a0_0_a2_0_a2_0[0]),
	.sram_wen_mem_m3_0(sram_wen_mem_m3_0[0]),
	.wen_a6_0_a2_1_a2_0(wen_a6_0_a2_1_a2_0[0]),
	.sram_wen_mem_m4(sram_wen_mem_m4[0]),
	.wen_a5_0_a2_1_a2_0(wen_a5_0_a2_1_a2_0[0]),
	.wen_a3_0_a2_0_a2_0(wen_a3_0_a2_0_a2_0[0]),
	.wen_a2_0_a2_0_a2_0(wen_a2_0_a2_0_a2_0[0]),
	.CoreAHBLite_0_AHBmslave3_HWDATA(CoreAHBLite_0_AHBmslave3_HWDATA[7:0]),
	.ahbsram_addr(ahbsram_addr[15:2]),
	.Linker_Design_MSS_0_MSS_RESET_N_M2F(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.FCCC_0_GL0_0(FCCC_0_GL0_0),
	.sram_N_3_mux_0(sram_N_3_mux_0)
);
// @20:262
  Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_0 \genblk1.byte_1  (
	.sram_wen_mem_m4(sram_wen_mem_m4[0]),
	.sram_wen_mem_m3(sram_wen_mem_m3[1]),
	.ckRdAddr(ckRdAddr[13:11]),
	.ram_rdata(ram_rdata[15:8]),
	.wen_a3_0_a2_0_a2_0(wen_a3_0_a2_0_a2_0[0]),
	.wen_a2_0_a2_0_a2_0(wen_a2_0_a2_0_a2_0[0]),
	.wen_a5_0_a2_1_a2_0(wen_a5_0_a2_1_a2_0[0]),
	.wen_a6_0_a2_1_a2_0(wen_a6_0_a2_1_a2_0[0]),
	.wen_a1_0_a2_0_a2_0(wen_a1_0_a2_0_a2_0[0]),
	.wen_a7_0_a2_0_a2_0(wen_a7_0_a2_0_a2_0[0]),
	.CoreAHBLite_0_AHBmslave3_HWDATA(CoreAHBLite_0_AHBmslave3_HWDATA[15:8]),
	.ahbsram_addr(ahbsram_addr[15:0]),
	.sram_N_3_mux_0(sram_N_3_mux_0),
	.FCCC_0_GL0_0(FCCC_0_GL0_0),
	.Linker_Design_MSS_0_MSS_RESET_N_M2F(Linker_Design_MSS_0_MSS_RESET_N_M2F)
);
// @20:277
  Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_1 \genblk1.byte_2  (
	.sram_wen_mem_m4(sram_wen_mem_m4[0]),
	.ckRdAddr(ckRdAddr[13:11]),
	.ram_rdata(ram_rdata[23:16]),
	.wen_a3_0_a2_0_a2_0(wen_a3_0_a2_0_a2_0[0]),
	.sram_wen_mem_m2(sram_wen_mem_m2[2]),
	.wen_a0_0_a2_0_a2_0(wen_a0_0_a2_0_a2_0[0]),
	.wen_a1_0_a2_0_a2_0(wen_a1_0_a2_0_a2_0[0]),
	.wen_a2_0_a2_0_a2_0(wen_a2_0_a2_0_a2_0[0]),
	.CoreAHBLite_0_AHBmslave3_HWDATA(CoreAHBLite_0_AHBmslave3_HWDATA[23:16]),
	.ahbsram_addr(ahbsram_addr[15:0]),
	.sram_wen_mem_ss3(sram_wen_mem_ss3_Z),
	.FCCC_0_GL0_0(FCCC_0_GL0_0),
	.Linker_Design_MSS_0_MSS_RESET_N_M2F(Linker_Design_MSS_0_MSS_RESET_N_M2F)
);
// @20:292
  Linker_Design_COREAHBLSRAM_0_lsram_2048to139264x8_16384s_8s_2 \genblk1.byte_3  (
	.sram_wen_mem_m4(sram_wen_mem_m4[0]),
	.ckRdAddr(ckRdAddr[13:11]),
	.ram_rdata(ram_rdata[31:24]),
	.CoreAHBLite_0_AHBmslave3_HWDATA(CoreAHBLite_0_AHBmslave3_HWDATA[31:24]),
	.ahbsram_addr(ahbsram_addr[15:0]),
	.sram_wen_mem_ss3(sram_wen_mem_ss3_Z),
	.FCCC_0_GL0_0(FCCC_0_GL0_0),
	.Linker_Design_MSS_0_MSS_RESET_N_M2F(Linker_Design_MSS_0_MSS_RESET_N_M2F)
);
  GND GND_Z (
	.Y(GND)
);
  VCC VCC_Z (
	.Y(VCC)
);
endmodule /* Linker_Design_COREAHBLSRAM_0_SramCtrlIf_0s_16384s_512s_32s_0_1_2 */

module Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM_19s_32s_32s_16384s_512s_0s (
  CoreAHBLite_0_AHBmslave3_HADDR,
  CoreAHBLite_0_AHBmslave3_HSIZE,
  arbRegSMCurrentState_0,
  arbRegSMCurrentState_3,
  CoreAHBLite_0_AHBmslave3_HRDATA_m,
  SADDRSEL_2,
  PREGATEDHADDR,
  M0GATEDHSIZE,
  MASTERADDRINPROG_i_a2_0_0_0_0,
  MASTERADDRINPROG_i_a2_d_c_c,
  SADDRSEL_1_4,
  SADDRSEL_1_0,
  MASTERADDRINPROG_i_a2_c,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE,
  regHSIZE,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0,
  CoreAHBLite_0_AHBmslave3_HWDATA,
  Linker_Design_MSS_0_MSS_RESET_N_M2F,
  FCCC_0_GL0_0,
  CoreAHBLite_0_AHBmslave3_HWRITE,
  CoreAHBLite_0_AHBmslave3_HREADY,
  N_152,
  HTRANS_0,
  HREADY_M_pre24,
  N_156,
  M0GATEDHWRITE,
  masterRegAddrSel,
  regHTRANS
)
;
input [15:0] CoreAHBLite_0_AHBmslave3_HADDR ;
input [1:0] CoreAHBLite_0_AHBmslave3_HSIZE ;
input arbRegSMCurrentState_0 ;
input arbRegSMCurrentState_3 ;
output [31:0] CoreAHBLite_0_AHBmslave3_HRDATA_m ;
input [2:2] SADDRSEL_2 ;
input [28:28] PREGATEDHADDR ;
input [1:1] M0GATEDHSIZE ;
input [0:0] MASTERADDRINPROG_i_a2_0_0_0_0 ;
input [0:0] MASTERADDRINPROG_i_a2_d_c_c ;
input SADDRSEL_1_4 ;
input SADDRSEL_1_0 ;
input [0:0] MASTERADDRINPROG_i_a2_c ;
input [1:1] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE ;
input [1:1] regHSIZE ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3 ;
input Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0 ;
input [31:0] CoreAHBLite_0_AHBmslave3_HWDATA ;
input Linker_Design_MSS_0_MSS_RESET_N_M2F ;
input FCCC_0_GL0_0 ;
input CoreAHBLite_0_AHBmslave3_HWRITE ;
output CoreAHBLite_0_AHBmslave3_HREADY ;
input N_152 ;
input HTRANS_0 ;
input HREADY_M_pre24 ;
input N_156 ;
input M0GATEDHWRITE ;
input masterRegAddrSel ;
input regHTRANS ;
wire arbRegSMCurrentState_0 ;
wire arbRegSMCurrentState_3 ;
wire SADDRSEL_1_4 ;
wire SADDRSEL_1_0 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0 ;
wire Linker_Design_MSS_0_MSS_RESET_N_M2F ;
wire FCCC_0_GL0_0 ;
wire CoreAHBLite_0_AHBmslave3_HWRITE ;
wire CoreAHBLite_0_AHBmslave3_HREADY ;
wire N_152 ;
wire HTRANS_0 ;
wire HREADY_M_pre24 ;
wire N_156 ;
wire M0GATEDHWRITE ;
wire masterRegAddrSel ;
wire regHTRANS ;
wire [15:0] ahbsram_addr;
wire [1:0] ahbcurr_state;
wire [31:0] CoreAHBLite_0_AHBmslave3_HRDATA;
wire [1:1] ahbsram_size_0_0;
wire ahbsram_req_d1 ;
wire sramahb_ack ;
wire d_N_3_mux ;
wire ahbsram_write ;
wire ahbsram_N_4 ;
wire GND ;
wire VCC ;
// @21:106
  AHBLSramIf U_AHBLSramIf (
	.ahbsram_addr(ahbsram_addr[15:0]),
	.CoreAHBLite_0_AHBmslave3_HADDR(CoreAHBLite_0_AHBmslave3_HADDR[15:0]),
	.CoreAHBLite_0_AHBmslave3_HSIZE(CoreAHBLite_0_AHBmslave3_HSIZE[1:0]),
	.ahbcurr_state(ahbcurr_state[1:0]),
	.arbRegSMCurrentState_0(arbRegSMCurrentState_0),
	.arbRegSMCurrentState_3(arbRegSMCurrentState_3),
	.CoreAHBLite_0_AHBmslave3_HRDATA(CoreAHBLite_0_AHBmslave3_HRDATA[31:0]),
	.CoreAHBLite_0_AHBmslave3_HRDATA_m(CoreAHBLite_0_AHBmslave3_HRDATA_m[31:0]),
	.SADDRSEL_2(SADDRSEL_2[2]),
	.PREGATEDHADDR(PREGATEDHADDR[28]),
	.M0GATEDHSIZE(M0GATEDHSIZE[1]),
	.ahbsram_size_0_0(ahbsram_size_0_0[1]),
	.MASTERADDRINPROG_i_a2_0_0_0_0(MASTERADDRINPROG_i_a2_0_0_0_0[0]),
	.MASTERADDRINPROG_i_a2_d_c_c(MASTERADDRINPROG_i_a2_d_c_c[0]),
	.SADDRSEL_1_4(SADDRSEL_1_4),
	.SADDRSEL_1_0(SADDRSEL_1_0),
	.Linker_Design_MSS_0_MSS_RESET_N_M2F(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.FCCC_0_GL0_0(FCCC_0_GL0_0),
	.CoreAHBLite_0_AHBmslave3_HWRITE(CoreAHBLite_0_AHBmslave3_HWRITE),
	.ahbsram_req_d1(ahbsram_req_d1),
	.CoreAHBLite_0_AHBmslave3_HREADY(CoreAHBLite_0_AHBmslave3_HREADY),
	.N_152(N_152),
	.sramahb_ack(sramahb_ack),
	.HTRANS_0(HTRANS_0),
	.d_N_3_mux(d_N_3_mux),
	.ahbsram_write(ahbsram_write),
	.HREADY_M_pre24(HREADY_M_pre24),
	.N_156(N_156),
	.M0GATEDHWRITE(M0GATEDHWRITE),
	.ahbsram_N_4(ahbsram_N_4)
);
// @21:140
  Linker_Design_COREAHBLSRAM_0_SramCtrlIf_0s_16384s_512s_32s_0_1_2 U_SramCtrlIf (
	.CoreAHBLite_0_AHBmslave3_HRDATA(CoreAHBLite_0_AHBmslave3_HRDATA[31:0]),
	.ahbcurr_state(ahbcurr_state[1:0]),
	.MASTERADDRINPROG_i_a2_c(MASTERADDRINPROG_i_a2_c[0]),
	.ahbsram_size_0_0(ahbsram_size_0_0[1]),
	.SADDRSEL_1(SADDRSEL_1_4),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE[1]),
	.regHSIZE(regHSIZE[1]),
	.PREGATEDHADDR(PREGATEDHADDR[28]),
	.SADDRSEL_2(SADDRSEL_2[2]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0),
	.arbRegSMCurrentState_3(arbRegSMCurrentState_3),
	.arbRegSMCurrentState_0(arbRegSMCurrentState_0),
	.MASTERADDRINPROG_i_a2_d_c_c(MASTERADDRINPROG_i_a2_d_c_c[0]),
	.MASTERADDRINPROG_i_a2_0_0_0_0(MASTERADDRINPROG_i_a2_0_0_0_0[0]),
	.ahbsram_addr(ahbsram_addr[15:0]),
	.CoreAHBLite_0_AHBmslave3_HWDATA(CoreAHBLite_0_AHBmslave3_HWDATA[31:0]),
	.Linker_Design_MSS_0_MSS_RESET_N_M2F(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.FCCC_0_GL0_0(FCCC_0_GL0_0),
	.sramahb_ack(sramahb_ack),
	.ahbsram_N_4(ahbsram_N_4),
	.masterRegAddrSel(masterRegAddrSel),
	.regHTRANS(regHTRANS),
	.CoreAHBLite_0_AHBmslave3_HREADY(CoreAHBLite_0_AHBmslave3_HREADY),
	.ahbsram_req_d1(ahbsram_req_d1),
	.ahbsram_write(ahbsram_write),
	.d_N_3_mux(d_N_3_mux)
);
  GND GND_Z (
	.Y(GND)
);
  VCC VCC_Z (
	.Y(VCC)
);
endmodule /* Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM_19s_32s_32s_16384s_512s_0s */

module Linker_Design_FCCC_0_FCCC (
  FCCC_0_GL0_0,
  FCCC_0_LOCK,
  OSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
)
;
output FCCC_0_GL0_0 ;
output FCCC_0_LOCK ;
input OSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC ;
wire FCCC_0_GL0_0 ;
wire FCCC_0_LOCK ;
wire OSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC ;
wire [7:0] PRDATA;
wire GL0_net ;
wire Y0 ;
wire Y1 ;
wire Y2 ;
wire Y3 ;
wire BUSY ;
wire VCC ;
wire GND ;
wire GL1 ;
wire GL2 ;
wire GL3 ;
// @5:18
  CLKINT GL0_INST (
	.A(GL0_net),
	.Y(FCCC_0_GL0_0)
);
//@22:592
// @5:20
  CCC CCC_INST (
	.Y0(Y0),
	.Y1(Y1),
	.Y2(Y2),
	.Y3(Y3),
	.PRDATA(PRDATA[7:0]),
	.LOCK(FCCC_0_LOCK),
	.BUSY(BUSY),
	.CLK0(VCC),
	.CLK1(VCC),
	.CLK2(VCC),
	.CLK3(VCC),
	.NGMUX0_SEL(GND),
	.NGMUX1_SEL(GND),
	.NGMUX2_SEL(GND),
	.NGMUX3_SEL(GND),
	.NGMUX0_HOLD_N(VCC),
	.NGMUX1_HOLD_N(VCC),
	.NGMUX2_HOLD_N(VCC),
	.NGMUX3_HOLD_N(VCC),
	.NGMUX0_ARST_N(VCC),
	.NGMUX1_ARST_N(VCC),
	.NGMUX2_ARST_N(VCC),
	.NGMUX3_ARST_N(VCC),
	.PLL_BYPASS_N(VCC),
	.PLL_ARST_N(VCC),
	.PLL_POWERDOWN_N(VCC),
	.GPD0_ARST_N(VCC),
	.GPD1_ARST_N(VCC),
	.GPD2_ARST_N(VCC),
	.GPD3_ARST_N(VCC),
	.PRESET_N(GND),
	.PCLK(VCC),
	.PSEL(VCC),
	.PENABLE(VCC),
	.PWRITE(VCC),
	.PADDR({VCC, VCC, VCC, VCC, VCC, VCC}),
	.PWDATA({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
	.CLK0_PAD(GND),
	.CLK1_PAD(GND),
	.CLK2_PAD(GND),
	.CLK3_PAD(GND),
	.GL0(GL0_net),
	.GL1(GL1),
	.GL2(GL2),
	.GL3(GL3),
	.RCOSC_25_50MHZ(OSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC),
	.RCOSC_1MHZ(GND),
	.XTLOSC(GND)
);
defparam CCC_INST.INIT=212'h0000007FB8000045164000318C6318C1F18C61EC0404040400101;
defparam CCC_INST.VCOFREQUENCY=800.0;
  GND GND_Z (
	.Y(GND)
);
  VCC VCC_Z (
	.Y(VCC)
);
endmodule /* Linker_Design_FCCC_0_FCCC */

module Linker_Design_MSS (
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA,
  CoreAHBLite_0_AHBmslave3_HRDATA_m,
  Linker_Design_MSS_0_MSS_RESET_N_M2F,
  MMUART_0_TXD,
  MMUART_0_RXD,
  Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE,
  FCCC_0_GL0_0,
  HREADY_M_iv_i_0,
  un1_HREADY_M_pre24_1_i_0,
  FCCC_0_LOCK,
  SYSRESET_0_POWER_ON_RESET_N
)
;
output Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0 ;
output Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1 ;
output Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2 ;
output Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3 ;
output Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4 ;
output Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5 ;
output Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6 ;
output Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7 ;
output Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8 ;
output Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9 ;
output Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10 ;
output Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11 ;
output Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12 ;
output Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13 ;
output Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14 ;
output Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15 ;
output Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28 ;
output Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29 ;
output Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30 ;
output Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31 ;
output [1:0] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE ;
output [1:1] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS ;
output [31:0] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA ;
input [31:0] CoreAHBLite_0_AHBmslave3_HRDATA_m ;
output Linker_Design_MSS_0_MSS_RESET_N_M2F ;
output MMUART_0_TXD /* synthesis syn_tristate = 1 */ ;
input MMUART_0_RXD ;
output Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE ;
input FCCC_0_GL0_0 ;
input HREADY_M_iv_i_0 ;
input un1_HREADY_M_pre24_1_i_0 ;
input FCCC_0_LOCK ;
input SYSRESET_0_POWER_ON_RESET_N ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30 ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31 ;
wire Linker_Design_MSS_0_MSS_RESET_N_M2F ;
wire MMUART_0_TXD ;
wire MMUART_0_RXD ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE ;
wire FCCC_0_GL0_0 ;
wire HREADY_M_iv_i_0 ;
wire un1_HREADY_M_pre24_1_i_0 ;
wire FCCC_0_LOCK ;
wire SYSRESET_0_POWER_ON_RESET_N ;
wire [7:0] EDAC_ERROR;
wire [31:0] F_FM0_RDATA;
wire [31:0] F_FM1_RDATA;
wire [27:16] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR;
wire [31:0] F_HM1_ADDR;
wire [1:0] F_HM1_SIZE;
wire [31:0] F_HM1_WDATA;
wire [1:0] FAB_OPMODE;
wire [3:0] FAB_VCONTROL;
wire [1:0] FAB_XCVRSEL;
wire [7:0] FAB_XDATAOUT;
wire [1:0] FIC32_0_MASTER;
wire [1:0] FIC32_1_MASTER;
wire [15:0] H2F_INTERRUPT;
wire [15:2] PER2_FABRIC_PADDR;
wire [31:0] PER2_FABRIC_PWDATA;
wire [9:0] TCGF;
wire [3:0] TRACEDATA;
wire [3:0] TXD_RIF;
wire [7:0] TXDF;
wire [3:0] F_BID;
wire [1:0] F_BRESP_HRESP0;
wire [63:0] F_RDATA_HRDATA01;
wire [3:0] F_RID;
wire [1:0] F_RRESP_HRESP1;
wire [15:0] MDDR_FABRIC_PRDATA;
wire [31:0] REV_ARADDR;
wire [1:0] REV_ARBURST;
wire [3:0] REV_ARID;
wire [3:0] REV_ARLEN;
wire [1:0] REV_ARLOCK;
wire [1:0] REV_ARSIZE;
wire [31:0] REV_AWADDR;
wire [1:0] REV_AWLOCK;
wire [1:0] REV_AWSIZE;
wire [3:0] REV_WID;
wire [7:0] REV_WSTRB;
wire [15:0] DRAM_ADDR;
wire [2:0] DRAM_BA;
wire [4:0] DRAM_DM_RDQS_OUT;
wire [35:0] DRAM_DQ_OUT;
wire [4:0] DRAM_DQS_OUT;
wire [2:0] DRAM_FIFO_WE_OUT;
wire [4:0] DM_OE;
wire [35:0] DRAM_DQ_OE;
wire [4:0] DRAM_DQS_OE;
wire FPGA_RESET_N ;
wire MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OUT ;
wire MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OE ;
wire MMUART_0_RXD_PAD_Y ;
wire CAN_RXBUS_MGPIO3A_H2F_A ;
wire CAN_RXBUS_MGPIO3A_H2F_B ;
wire CAN_TX_EBL_MGPIO4A_H2F_A ;
wire CAN_TX_EBL_MGPIO4A_H2F_B ;
wire CAN_TXBUS_MGPIO2A_H2F_A ;
wire CAN_TXBUS_MGPIO2A_H2F_B ;
wire CLK_CONFIG_APB ;
wire COMMS_INT ;
wire CONFIG_PRESET_N ;
wire F_FM0_READYOUT ;
wire F_FM0_RESP ;
wire F_FM1_READYOUT ;
wire F_FM1_RESP ;
wire F_HM0_ENABLE ;
wire F_HM0_SEL ;
wire F_HM1_ENABLE ;
wire F_HM1_SEL ;
wire F_HM1_TRANS1 ;
wire F_HM1_WRITE ;
wire FAB_CHRGVBUS ;
wire FAB_DISCHRGVBUS ;
wire FAB_DMPULLDOWN ;
wire FAB_DPPULLDOWN ;
wire FAB_DRVVBUS ;
wire FAB_IDPULLUP ;
wire FAB_SUSPENDM ;
wire FAB_TERMSEL ;
wire FAB_TXVALID ;
wire FAB_VCONTROLLOADM ;
wire FACC_GLMUX_SEL ;
wire GTX_CLK ;
wire H2F_NMI ;
wire H2FCALIB ;
wire I2C0_SCL_MGPIO31B_H2F_A ;
wire I2C0_SCL_MGPIO31B_H2F_B ;
wire I2C0_SDA_MGPIO30B_H2F_A ;
wire I2C0_SDA_MGPIO30B_H2F_B ;
wire I2C1_SCL_MGPIO1A_H2F_A ;
wire I2C1_SCL_MGPIO1A_H2F_B ;
wire I2C1_SDA_MGPIO0A_H2F_A ;
wire I2C1_SDA_MGPIO0A_H2F_B ;
wire MDCF ;
wire MDOENF ;
wire MDOF ;
wire MMUART0_CTS_MGPIO19B_H2F_A ;
wire MMUART0_CTS_MGPIO19B_H2F_B ;
wire MMUART0_DCD_MGPIO22B_H2F_A ;
wire MMUART0_DCD_MGPIO22B_H2F_B ;
wire MMUART0_DSR_MGPIO20B_H2F_A ;
wire MMUART0_DSR_MGPIO20B_H2F_B ;
wire MMUART0_DTR_MGPIO18B_H2F_A ;
wire MMUART0_DTR_MGPIO18B_H2F_B ;
wire MMUART0_RI_MGPIO21B_H2F_A ;
wire MMUART0_RI_MGPIO21B_H2F_B ;
wire MMUART0_RTS_MGPIO17B_H2F_A ;
wire MMUART0_RTS_MGPIO17B_H2F_B ;
wire MMUART0_RXD_MGPIO28B_H2F_A ;
wire MMUART0_RXD_MGPIO28B_H2F_B ;
wire MMUART0_SCK_MGPIO29B_H2F_A ;
wire MMUART0_SCK_MGPIO29B_H2F_B ;
wire MMUART0_TXD_MGPIO27B_H2F_A ;
wire MMUART0_TXD_MGPIO27B_H2F_B ;
wire MMUART1_DTR_MGPIO12B_H2F_A ;
wire MMUART1_RTS_MGPIO11B_H2F_A ;
wire MMUART1_RTS_MGPIO11B_H2F_B ;
wire MMUART1_RXD_MGPIO26B_H2F_A ;
wire MMUART1_RXD_MGPIO26B_H2F_B ;
wire MMUART1_SCK_MGPIO25B_H2F_A ;
wire MMUART1_SCK_MGPIO25B_H2F_B ;
wire MMUART1_TXD_MGPIO24B_H2F_A ;
wire MMUART1_TXD_MGPIO24B_H2F_B ;
wire MPLL_LOCK ;
wire PER2_FABRIC_PENABLE ;
wire PER2_FABRIC_PSEL ;
wire PER2_FABRIC_PWRITE ;
wire RTC_MATCH ;
wire SLEEPDEEP ;
wire SLEEPHOLDACK ;
wire SLEEPING ;
wire SMBALERT_NO0 ;
wire SMBALERT_NO1 ;
wire SMBSUS_NO0 ;
wire SMBSUS_NO1 ;
wire SPI0_CLK_OUT ;
wire SPI0_SDI_MGPIO5A_H2F_A ;
wire SPI0_SDI_MGPIO5A_H2F_B ;
wire SPI0_SDO_MGPIO6A_H2F_A ;
wire SPI0_SDO_MGPIO6A_H2F_B ;
wire SPI0_SS0_MGPIO7A_H2F_A ;
wire SPI0_SS0_MGPIO7A_H2F_B ;
wire SPI0_SS1_MGPIO8A_H2F_A ;
wire SPI0_SS1_MGPIO8A_H2F_B ;
wire SPI0_SS2_MGPIO9A_H2F_A ;
wire SPI0_SS2_MGPIO9A_H2F_B ;
wire SPI0_SS3_MGPIO10A_H2F_A ;
wire SPI0_SS3_MGPIO10A_H2F_B ;
wire SPI0_SS4_MGPIO19A_H2F_A ;
wire SPI0_SS5_MGPIO20A_H2F_A ;
wire SPI0_SS6_MGPIO21A_H2F_A ;
wire SPI0_SS7_MGPIO22A_H2F_A ;
wire SPI1_CLK_OUT ;
wire SPI1_SDI_MGPIO11A_H2F_A ;
wire SPI1_SDI_MGPIO11A_H2F_B ;
wire SPI1_SDO_MGPIO12A_H2F_A ;
wire SPI1_SDO_MGPIO12A_H2F_B ;
wire SPI1_SS0_MGPIO13A_H2F_A ;
wire SPI1_SS0_MGPIO13A_H2F_B ;
wire SPI1_SS1_MGPIO14A_H2F_A ;
wire SPI1_SS1_MGPIO14A_H2F_B ;
wire SPI1_SS2_MGPIO15A_H2F_A ;
wire SPI1_SS2_MGPIO15A_H2F_B ;
wire SPI1_SS3_MGPIO16A_H2F_A ;
wire SPI1_SS3_MGPIO16A_H2F_B ;
wire SPI1_SS4_MGPIO17A_H2F_A ;
wire SPI1_SS5_MGPIO18A_H2F_A ;
wire SPI1_SS6_MGPIO23A_H2F_A ;
wire SPI1_SS7_MGPIO24A_H2F_A ;
wire TRACECLK ;
wire TX_CLK ;
wire TX_ENF ;
wire TX_ERRF ;
wire TXCTL_EN_RIF ;
wire TXEV ;
wire WDOGTIMEOUT ;
wire F_ARREADY_HREADYOUT1 ;
wire F_AWREADY_HREADYOUT0 ;
wire F_BVALID ;
wire F_RLAST ;
wire F_RVALID ;
wire F_WREADY ;
wire MDDR_FABRIC_PREADY ;
wire MDDR_FABRIC_PSLVERR ;
wire REV_RREADY ;
wire VCC ;
wire GND ;
wire CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT ;
wire CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT ;
wire CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT ;
wire DRAM_CASN ;
wire DRAM_CKE ;
wire DRAM_CLK ;
wire DRAM_CSN ;
wire DRAM_ODT ;
wire DRAM_RASN ;
wire DRAM_RSTN ;
wire DRAM_WEN ;
wire I2C0_SCL_USBC_DATA1_MGPIO31B_OUT ;
wire I2C0_SDA_USBC_DATA0_MGPIO30B_OUT ;
wire I2C1_SCL_USBA_DATA4_MGPIO1A_OUT ;
wire I2C1_SDA_USBA_DATA3_MGPIO0A_OUT ;
wire MGPIO0B_OUT ;
wire MGPIO10B_OUT ;
wire MGPIO1B_OUT ;
wire MGPIO25A_OUT ;
wire MGPIO26A_OUT ;
wire MGPIO27A_OUT ;
wire MGPIO28A_OUT ;
wire MGPIO29A_OUT ;
wire MGPIO2B_OUT ;
wire MGPIO30A_OUT ;
wire MGPIO31A_OUT ;
wire MGPIO3B_OUT ;
wire MGPIO4B_OUT ;
wire MGPIO5B_OUT ;
wire MGPIO6B_OUT ;
wire MGPIO7B_OUT ;
wire MGPIO8B_OUT ;
wire MGPIO9B_OUT ;
wire MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT ;
wire MMUART0_DCD_MGPIO22B_OUT ;
wire MMUART0_DSR_MGPIO20B_OUT ;
wire MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT ;
wire MMUART0_RI_MGPIO21B_OUT ;
wire MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT ;
wire MMUART0_RXD_USBC_STP_MGPIO28B_OUT ;
wire MMUART0_SCK_USBC_NXT_MGPIO29B_OUT ;
wire MMUART1_CTS_MGPIO13B_OUT ;
wire MMUART1_DCD_MGPIO16B_OUT ;
wire MMUART1_DSR_MGPIO14B_OUT ;
wire MMUART1_DTR_MGPIO12B_OUT ;
wire MMUART1_RI_MGPIO15B_OUT ;
wire MMUART1_RTS_MGPIO11B_OUT ;
wire MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT ;
wire MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT ;
wire MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT ;
wire RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT ;
wire RGMII_MDC_RMII_MDC_OUT ;
wire RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT ;
wire RGMII_RX_CLK_OUT ;
wire RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT ;
wire RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT ;
wire RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT ;
wire RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT ;
wire RGMII_RXD3_USBB_DATA4_OUT ;
wire RGMII_TX_CLK_OUT ;
wire RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT ;
wire RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT ;
wire RGMII_TXD1_RMII_TXD1_USBB_STP_OUT ;
wire RGMII_TXD2_USBB_DATA5_OUT ;
wire RGMII_TXD3_USBB_DATA6_OUT ;
wire SPI0_SCK_USBA_XCLK_OUT ;
wire SPI0_SDI_USBA_DIR_MGPIO5A_OUT ;
wire SPI0_SDO_USBA_STP_MGPIO6A_OUT ;
wire SPI0_SS0_USBA_NXT_MGPIO7A_OUT ;
wire SPI0_SS1_USBA_DATA5_MGPIO8A_OUT ;
wire SPI0_SS2_USBA_DATA6_MGPIO9A_OUT ;
wire SPI0_SS3_USBA_DATA7_MGPIO10A_OUT ;
wire SPI0_SS4_MGPIO19A_OUT ;
wire SPI0_SS5_MGPIO20A_OUT ;
wire SPI0_SS6_MGPIO21A_OUT ;
wire SPI0_SS7_MGPIO22A_OUT ;
wire SPI1_SCK_OUT ;
wire SPI1_SDI_MGPIO11A_OUT ;
wire SPI1_SDO_MGPIO12A_OUT ;
wire SPI1_SS0_MGPIO13A_OUT ;
wire SPI1_SS1_MGPIO14A_OUT ;
wire SPI1_SS2_MGPIO15A_OUT ;
wire SPI1_SS3_MGPIO16A_OUT ;
wire SPI1_SS4_MGPIO17A_OUT ;
wire SPI1_SS5_MGPIO18A_OUT ;
wire SPI1_SS6_MGPIO23A_OUT ;
wire SPI1_SS7_MGPIO24A_OUT ;
wire USBC_XCLK_OUT ;
wire USBD_DATA0_OUT ;
wire USBD_DATA1_OUT ;
wire USBD_DATA2_OUT ;
wire USBD_DATA3_OUT ;
wire USBD_DATA4_OUT ;
wire USBD_DATA5_OUT ;
wire USBD_DATA6_OUT ;
wire USBD_DATA7_MGPIO23B_OUT ;
wire USBD_DIR_OUT ;
wire USBD_NXT_OUT ;
wire USBD_STP_OUT ;
wire USBD_XCLK_OUT ;
wire CAN_RXBUS_USBA_DATA1_MGPIO3A_OE ;
wire CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE ;
wire CAN_TXBUS_USBA_DATA0_MGPIO2A_OE ;
wire I2C0_SCL_USBC_DATA1_MGPIO31B_OE ;
wire I2C0_SDA_USBC_DATA0_MGPIO30B_OE ;
wire I2C1_SCL_USBA_DATA4_MGPIO1A_OE ;
wire I2C1_SDA_USBA_DATA3_MGPIO0A_OE ;
wire MGPIO0B_OE ;
wire MGPIO10B_OE ;
wire MGPIO1B_OE ;
wire MGPIO25A_OE ;
wire MGPIO26A_OE ;
wire MGPIO27A_OE ;
wire MGPIO28A_OE ;
wire MGPIO29A_OE ;
wire MGPIO2B_OE ;
wire MGPIO30A_OE ;
wire MGPIO31A_OE ;
wire MGPIO3B_OE ;
wire MGPIO4B_OE ;
wire MGPIO5B_OE ;
wire MGPIO6B_OE ;
wire MGPIO7B_OE ;
wire MGPIO8B_OE ;
wire MGPIO9B_OE ;
wire MMUART0_CTS_USBC_DATA7_MGPIO19B_OE ;
wire MMUART0_DCD_MGPIO22B_OE ;
wire MMUART0_DSR_MGPIO20B_OE ;
wire MMUART0_DTR_USBC_DATA6_MGPIO18B_OE ;
wire MMUART0_RI_MGPIO21B_OE ;
wire MMUART0_RTS_USBC_DATA5_MGPIO17B_OE ;
wire MMUART0_RXD_USBC_STP_MGPIO28B_OE ;
wire MMUART0_SCK_USBC_NXT_MGPIO29B_OE ;
wire MMUART1_CTS_MGPIO13B_OE ;
wire MMUART1_DCD_MGPIO16B_OE ;
wire MMUART1_DSR_MGPIO14B_OE ;
wire MMUART1_DTR_MGPIO12B_OE ;
wire MMUART1_RI_MGPIO15B_OE ;
wire MMUART1_RTS_MGPIO11B_OE ;
wire MMUART1_RXD_USBC_DATA3_MGPIO26B_OE ;
wire MMUART1_SCK_USBC_DATA4_MGPIO25B_OE ;
wire MMUART1_TXD_USBC_DATA2_MGPIO24B_OE ;
wire RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE ;
wire RGMII_MDC_RMII_MDC_OE ;
wire RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE ;
wire RGMII_RX_CLK_OE ;
wire RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE ;
wire RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE ;
wire RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE ;
wire RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE ;
wire RGMII_RXD3_USBB_DATA4_OE ;
wire RGMII_TX_CLK_OE ;
wire RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE ;
wire RGMII_TXD0_RMII_TXD0_USBB_DIR_OE ;
wire RGMII_TXD1_RMII_TXD1_USBB_STP_OE ;
wire RGMII_TXD2_USBB_DATA5_OE ;
wire RGMII_TXD3_USBB_DATA6_OE ;
wire SPI0_SCK_USBA_XCLK_OE ;
wire SPI0_SDI_USBA_DIR_MGPIO5A_OE ;
wire SPI0_SDO_USBA_STP_MGPIO6A_OE ;
wire SPI0_SS0_USBA_NXT_MGPIO7A_OE ;
wire SPI0_SS1_USBA_DATA5_MGPIO8A_OE ;
wire SPI0_SS2_USBA_DATA6_MGPIO9A_OE ;
wire SPI0_SS3_USBA_DATA7_MGPIO10A_OE ;
wire SPI0_SS4_MGPIO19A_OE ;
wire SPI0_SS5_MGPIO20A_OE ;
wire SPI0_SS6_MGPIO21A_OE ;
wire SPI0_SS7_MGPIO22A_OE ;
wire SPI1_SCK_OE ;
wire SPI1_SDI_MGPIO11A_OE ;
wire SPI1_SDO_MGPIO12A_OE ;
wire SPI1_SS0_MGPIO13A_OE ;
wire SPI1_SS1_MGPIO14A_OE ;
wire SPI1_SS2_MGPIO15A_OE ;
wire SPI1_SS3_MGPIO16A_OE ;
wire SPI1_SS4_MGPIO17A_OE ;
wire SPI1_SS5_MGPIO18A_OE ;
wire SPI1_SS6_MGPIO23A_OE ;
wire SPI1_SS7_MGPIO24A_OE ;
wire USBC_XCLK_OE ;
wire USBD_DATA0_OE ;
wire USBD_DATA1_OE ;
wire USBD_DATA2_OE ;
wire USBD_DATA3_OE ;
wire USBD_DATA4_OE ;
wire USBD_DATA5_OE ;
wire USBD_DATA6_OE ;
wire USBD_DATA7_MGPIO23B_OE ;
wire USBD_DIR_OE ;
wire USBD_NXT_OE ;
wire USBD_STP_OE ;
wire USBD_XCLK_OE ;
  CLKINT MSS_ADLIB_INST_RNIO44E (
	.A(FPGA_RESET_N),
	.Y(Linker_Design_MSS_0_MSS_RESET_N_M2F)
);
// @7:192
  TRIBUFF MMUART_0_TXD_PAD (
	.PAD(MMUART_0_TXD),
	.D(MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OUT),
	.E(MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OE)
);
// @7:184
  INBUF MMUART_0_RXD_PAD (
	.Y(MMUART_0_RXD_PAD_Y),
	.PAD(MMUART_0_RXD)
);
// @7:205
  MSS_050 MSS_ADLIB_INST (
	.CAN_RXBUS_MGPIO3A_H2F_A(CAN_RXBUS_MGPIO3A_H2F_A),
	.CAN_RXBUS_MGPIO3A_H2F_B(CAN_RXBUS_MGPIO3A_H2F_B),
	.CAN_TX_EBL_MGPIO4A_H2F_A(CAN_TX_EBL_MGPIO4A_H2F_A),
	.CAN_TX_EBL_MGPIO4A_H2F_B(CAN_TX_EBL_MGPIO4A_H2F_B),
	.CAN_TXBUS_MGPIO2A_H2F_A(CAN_TXBUS_MGPIO2A_H2F_A),
	.CAN_TXBUS_MGPIO2A_H2F_B(CAN_TXBUS_MGPIO2A_H2F_B),
	.CLK_CONFIG_APB(CLK_CONFIG_APB),
	.COMMS_INT(COMMS_INT),
	.CONFIG_PRESET_N(CONFIG_PRESET_N),
	.EDAC_ERROR(EDAC_ERROR[7:0]),
	.F_FM0_RDATA(F_FM0_RDATA[31:0]),
	.F_FM0_READYOUT(F_FM0_READYOUT),
	.F_FM0_RESP(F_FM0_RESP),
	.F_FM1_RDATA(F_FM1_RDATA[31:0]),
	.F_FM1_READYOUT(F_FM1_READYOUT),
	.F_FM1_RESP(F_FM1_RESP),
	.F_HM0_ADDR({Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31, Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30, Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29, Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28, Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[27:16], Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15, Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14, Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13, Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12, Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11, Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10, Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9, Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8, Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7, Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6, Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5, Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4, Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3, Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2, Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1, Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0}),
	.F_HM0_ENABLE(F_HM0_ENABLE),
	.F_HM0_SEL(F_HM0_SEL),
	.F_HM0_SIZE(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE[1:0]),
	.F_HM0_TRANS1(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS[1]),
	.F_HM0_WDATA(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[31:0]),
	.F_HM0_WRITE(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE),
	.F_HM1_ADDR(F_HM1_ADDR[31:0]),
	.F_HM1_ENABLE(F_HM1_ENABLE),
	.F_HM1_SEL(F_HM1_SEL),
	.F_HM1_SIZE(F_HM1_SIZE[1:0]),
	.F_HM1_TRANS1(F_HM1_TRANS1),
	.F_HM1_WDATA(F_HM1_WDATA[31:0]),
	.F_HM1_WRITE(F_HM1_WRITE),
	.FAB_CHRGVBUS(FAB_CHRGVBUS),
	.FAB_DISCHRGVBUS(FAB_DISCHRGVBUS),
	.FAB_DMPULLDOWN(FAB_DMPULLDOWN),
	.FAB_DPPULLDOWN(FAB_DPPULLDOWN),
	.FAB_DRVVBUS(FAB_DRVVBUS),
	.FAB_IDPULLUP(FAB_IDPULLUP),
	.FAB_OPMODE(FAB_OPMODE[1:0]),
	.FAB_SUSPENDM(FAB_SUSPENDM),
	.FAB_TERMSEL(FAB_TERMSEL),
	.FAB_TXVALID(FAB_TXVALID),
	.FAB_VCONTROL(FAB_VCONTROL[3:0]),
	.FAB_VCONTROLLOADM(FAB_VCONTROLLOADM),
	.FAB_XCVRSEL(FAB_XCVRSEL[1:0]),
	.FAB_XDATAOUT(FAB_XDATAOUT[7:0]),
	.FACC_GLMUX_SEL(FACC_GLMUX_SEL),
	.FIC32_0_MASTER(FIC32_0_MASTER[1:0]),
	.FIC32_1_MASTER(FIC32_1_MASTER[1:0]),
	.FPGA_RESET_N(FPGA_RESET_N),
	.GTX_CLK(GTX_CLK),
	.H2F_INTERRUPT(H2F_INTERRUPT[15:0]),
	.H2F_NMI(H2F_NMI),
	.H2FCALIB(H2FCALIB),
	.I2C0_SCL_MGPIO31B_H2F_A(I2C0_SCL_MGPIO31B_H2F_A),
	.I2C0_SCL_MGPIO31B_H2F_B(I2C0_SCL_MGPIO31B_H2F_B),
	.I2C0_SDA_MGPIO30B_H2F_A(I2C0_SDA_MGPIO30B_H2F_A),
	.I2C0_SDA_MGPIO30B_H2F_B(I2C0_SDA_MGPIO30B_H2F_B),
	.I2C1_SCL_MGPIO1A_H2F_A(I2C1_SCL_MGPIO1A_H2F_A),
	.I2C1_SCL_MGPIO1A_H2F_B(I2C1_SCL_MGPIO1A_H2F_B),
	.I2C1_SDA_MGPIO0A_H2F_A(I2C1_SDA_MGPIO0A_H2F_A),
	.I2C1_SDA_MGPIO0A_H2F_B(I2C1_SDA_MGPIO0A_H2F_B),
	.MDCF(MDCF),
	.MDOENF(MDOENF),
	.MDOF(MDOF),
	.MMUART0_CTS_MGPIO19B_H2F_A(MMUART0_CTS_MGPIO19B_H2F_A),
	.MMUART0_CTS_MGPIO19B_H2F_B(MMUART0_CTS_MGPIO19B_H2F_B),
	.MMUART0_DCD_MGPIO22B_H2F_A(MMUART0_DCD_MGPIO22B_H2F_A),
	.MMUART0_DCD_MGPIO22B_H2F_B(MMUART0_DCD_MGPIO22B_H2F_B),
	.MMUART0_DSR_MGPIO20B_H2F_A(MMUART0_DSR_MGPIO20B_H2F_A),
	.MMUART0_DSR_MGPIO20B_H2F_B(MMUART0_DSR_MGPIO20B_H2F_B),
	.MMUART0_DTR_MGPIO18B_H2F_A(MMUART0_DTR_MGPIO18B_H2F_A),
	.MMUART0_DTR_MGPIO18B_H2F_B(MMUART0_DTR_MGPIO18B_H2F_B),
	.MMUART0_RI_MGPIO21B_H2F_A(MMUART0_RI_MGPIO21B_H2F_A),
	.MMUART0_RI_MGPIO21B_H2F_B(MMUART0_RI_MGPIO21B_H2F_B),
	.MMUART0_RTS_MGPIO17B_H2F_A(MMUART0_RTS_MGPIO17B_H2F_A),
	.MMUART0_RTS_MGPIO17B_H2F_B(MMUART0_RTS_MGPIO17B_H2F_B),
	.MMUART0_RXD_MGPIO28B_H2F_A(MMUART0_RXD_MGPIO28B_H2F_A),
	.MMUART0_RXD_MGPIO28B_H2F_B(MMUART0_RXD_MGPIO28B_H2F_B),
	.MMUART0_SCK_MGPIO29B_H2F_A(MMUART0_SCK_MGPIO29B_H2F_A),
	.MMUART0_SCK_MGPIO29B_H2F_B(MMUART0_SCK_MGPIO29B_H2F_B),
	.MMUART0_TXD_MGPIO27B_H2F_A(MMUART0_TXD_MGPIO27B_H2F_A),
	.MMUART0_TXD_MGPIO27B_H2F_B(MMUART0_TXD_MGPIO27B_H2F_B),
	.MMUART1_DTR_MGPIO12B_H2F_A(MMUART1_DTR_MGPIO12B_H2F_A),
	.MMUART1_RTS_MGPIO11B_H2F_A(MMUART1_RTS_MGPIO11B_H2F_A),
	.MMUART1_RTS_MGPIO11B_H2F_B(MMUART1_RTS_MGPIO11B_H2F_B),
	.MMUART1_RXD_MGPIO26B_H2F_A(MMUART1_RXD_MGPIO26B_H2F_A),
	.MMUART1_RXD_MGPIO26B_H2F_B(MMUART1_RXD_MGPIO26B_H2F_B),
	.MMUART1_SCK_MGPIO25B_H2F_A(MMUART1_SCK_MGPIO25B_H2F_A),
	.MMUART1_SCK_MGPIO25B_H2F_B(MMUART1_SCK_MGPIO25B_H2F_B),
	.MMUART1_TXD_MGPIO24B_H2F_A(MMUART1_TXD_MGPIO24B_H2F_A),
	.MMUART1_TXD_MGPIO24B_H2F_B(MMUART1_TXD_MGPIO24B_H2F_B),
	.MPLL_LOCK(MPLL_LOCK),
	.PER2_FABRIC_PADDR(PER2_FABRIC_PADDR[15:2]),
	.PER2_FABRIC_PENABLE(PER2_FABRIC_PENABLE),
	.PER2_FABRIC_PSEL(PER2_FABRIC_PSEL),
	.PER2_FABRIC_PWDATA(PER2_FABRIC_PWDATA[31:0]),
	.PER2_FABRIC_PWRITE(PER2_FABRIC_PWRITE),
	.RTC_MATCH(RTC_MATCH),
	.SLEEPDEEP(SLEEPDEEP),
	.SLEEPHOLDACK(SLEEPHOLDACK),
	.SLEEPING(SLEEPING),
	.SMBALERT_NO0(SMBALERT_NO0),
	.SMBALERT_NO1(SMBALERT_NO1),
	.SMBSUS_NO0(SMBSUS_NO0),
	.SMBSUS_NO1(SMBSUS_NO1),
	.SPI0_CLK_OUT(SPI0_CLK_OUT),
	.SPI0_SDI_MGPIO5A_H2F_A(SPI0_SDI_MGPIO5A_H2F_A),
	.SPI0_SDI_MGPIO5A_H2F_B(SPI0_SDI_MGPIO5A_H2F_B),
	.SPI0_SDO_MGPIO6A_H2F_A(SPI0_SDO_MGPIO6A_H2F_A),
	.SPI0_SDO_MGPIO6A_H2F_B(SPI0_SDO_MGPIO6A_H2F_B),
	.SPI0_SS0_MGPIO7A_H2F_A(SPI0_SS0_MGPIO7A_H2F_A),
	.SPI0_SS0_MGPIO7A_H2F_B(SPI0_SS0_MGPIO7A_H2F_B),
	.SPI0_SS1_MGPIO8A_H2F_A(SPI0_SS1_MGPIO8A_H2F_A),
	.SPI0_SS1_MGPIO8A_H2F_B(SPI0_SS1_MGPIO8A_H2F_B),
	.SPI0_SS2_MGPIO9A_H2F_A(SPI0_SS2_MGPIO9A_H2F_A),
	.SPI0_SS2_MGPIO9A_H2F_B(SPI0_SS2_MGPIO9A_H2F_B),
	.SPI0_SS3_MGPIO10A_H2F_A(SPI0_SS3_MGPIO10A_H2F_A),
	.SPI0_SS3_MGPIO10A_H2F_B(SPI0_SS3_MGPIO10A_H2F_B),
	.SPI0_SS4_MGPIO19A_H2F_A(SPI0_SS4_MGPIO19A_H2F_A),
	.SPI0_SS5_MGPIO20A_H2F_A(SPI0_SS5_MGPIO20A_H2F_A),
	.SPI0_SS6_MGPIO21A_H2F_A(SPI0_SS6_MGPIO21A_H2F_A),
	.SPI0_SS7_MGPIO22A_H2F_A(SPI0_SS7_MGPIO22A_H2F_A),
	.SPI1_CLK_OUT(SPI1_CLK_OUT),
	.SPI1_SDI_MGPIO11A_H2F_A(SPI1_SDI_MGPIO11A_H2F_A),
	.SPI1_SDI_MGPIO11A_H2F_B(SPI1_SDI_MGPIO11A_H2F_B),
	.SPI1_SDO_MGPIO12A_H2F_A(SPI1_SDO_MGPIO12A_H2F_A),
	.SPI1_SDO_MGPIO12A_H2F_B(SPI1_SDO_MGPIO12A_H2F_B),
	.SPI1_SS0_MGPIO13A_H2F_A(SPI1_SS0_MGPIO13A_H2F_A),
	.SPI1_SS0_MGPIO13A_H2F_B(SPI1_SS0_MGPIO13A_H2F_B),
	.SPI1_SS1_MGPIO14A_H2F_A(SPI1_SS1_MGPIO14A_H2F_A),
	.SPI1_SS1_MGPIO14A_H2F_B(SPI1_SS1_MGPIO14A_H2F_B),
	.SPI1_SS2_MGPIO15A_H2F_A(SPI1_SS2_MGPIO15A_H2F_A),
	.SPI1_SS2_MGPIO15A_H2F_B(SPI1_SS2_MGPIO15A_H2F_B),
	.SPI1_SS3_MGPIO16A_H2F_A(SPI1_SS3_MGPIO16A_H2F_A),
	.SPI1_SS3_MGPIO16A_H2F_B(SPI1_SS3_MGPIO16A_H2F_B),
	.SPI1_SS4_MGPIO17A_H2F_A(SPI1_SS4_MGPIO17A_H2F_A),
	.SPI1_SS5_MGPIO18A_H2F_A(SPI1_SS5_MGPIO18A_H2F_A),
	.SPI1_SS6_MGPIO23A_H2F_A(SPI1_SS6_MGPIO23A_H2F_A),
	.SPI1_SS7_MGPIO24A_H2F_A(SPI1_SS7_MGPIO24A_H2F_A),
	.TCGF(TCGF[9:0]),
	.TRACECLK(TRACECLK),
	.TRACEDATA(TRACEDATA[3:0]),
	.TX_CLK(TX_CLK),
	.TX_ENF(TX_ENF),
	.TX_ERRF(TX_ERRF),
	.TXCTL_EN_RIF(TXCTL_EN_RIF),
	.TXD_RIF(TXD_RIF[3:0]),
	.TXDF(TXDF[7:0]),
	.TXEV(TXEV),
	.WDOGTIMEOUT(WDOGTIMEOUT),
	.F_ARREADY_HREADYOUT1(F_ARREADY_HREADYOUT1),
	.F_AWREADY_HREADYOUT0(F_AWREADY_HREADYOUT0),
	.F_BID(F_BID[3:0]),
	.F_BRESP_HRESP0(F_BRESP_HRESP0[1:0]),
	.F_BVALID(F_BVALID),
	.F_RDATA_HRDATA01(F_RDATA_HRDATA01[63:0]),
	.F_RID(F_RID[3:0]),
	.F_RLAST(F_RLAST),
	.F_RRESP_HRESP1(F_RRESP_HRESP1[1:0]),
	.F_RVALID(F_RVALID),
	.F_WREADY(F_WREADY),
	.MDDR_FABRIC_PRDATA(MDDR_FABRIC_PRDATA[15:0]),
	.MDDR_FABRIC_PREADY(MDDR_FABRIC_PREADY),
	.MDDR_FABRIC_PSLVERR(MDDR_FABRIC_PSLVERR),
	.REV_ARADDR(REV_ARADDR[31:0]),
	.REV_ARBURST(REV_ARBURST[1:0]),
	.REV_ARID(REV_ARID[3:0]),
	.REV_ARLEN(REV_ARLEN[3:0]),
	.REV_ARLOCK(REV_ARLOCK[1:0]),
	.REV_ARSIZE(REV_ARSIZE[1:0]),
	.REV_AWADDR(REV_AWADDR[31:0]),
	.REV_AWLOCK(REV_AWLOCK[1:0]),
	.REV_AWSIZE(REV_AWSIZE[1:0]),
	.REV_RREADY(REV_RREADY),
	.REV_WID(REV_WID[3:0]),
	.REV_WSTRB(REV_WSTRB[7:0]),
	.CAN_RXBUS_F2H_SCP(VCC),
	.CAN_TX_EBL_F2H_SCP(VCC),
	.CAN_TXBUS_F2H_SCP(VCC),
	.CLK_BASE(FCCC_0_GL0_0),
	.COLF(VCC),
	.CRSF(VCC),
	.F2_DMAREADY({VCC, VCC}),
	.F2H_INTERRUPT({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
	.F2HCALIB(VCC),
	.F_DMAREADY({VCC, VCC}),
	.F_FM0_ADDR({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
	.F_FM0_ENABLE(GND),
	.F_FM0_MASTLOCK(GND),
	.F_FM0_READY(VCC),
	.F_FM0_SEL(GND),
	.F_FM0_SIZE({GND, GND}),
	.F_FM0_TRANS1(GND),
	.F_FM0_WDATA({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
	.F_FM0_WRITE(GND),
	.F_FM1_ADDR({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
	.F_FM1_ENABLE(GND),
	.F_FM1_MASTLOCK(GND),
	.F_FM1_READY(VCC),
	.F_FM1_SEL(GND),
	.F_FM1_SIZE({GND, GND}),
	.F_FM1_TRANS1(GND),
	.F_FM1_WDATA({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
	.F_FM1_WRITE(GND),
	.F_HM0_RDATA(CoreAHBLite_0_AHBmslave3_HRDATA_m[31:0]),
	.F_HM0_READY(HREADY_M_iv_i_0),
	.F_HM0_RESP(un1_HREADY_M_pre24_1_i_0),
	.F_HM1_RDATA({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
	.F_HM1_READY(VCC),
	.F_HM1_RESP(GND),
	.FAB_AVALID(VCC),
	.FAB_HOSTDISCON(VCC),
	.FAB_IDDIG(VCC),
	.FAB_LINESTATE({VCC, VCC}),
	.FAB_M3_RESET_N(VCC),
	.FAB_PLL_LOCK(FCCC_0_LOCK),
	.FAB_RXACTIVE(VCC),
	.FAB_RXERROR(VCC),
	.FAB_RXVALID(VCC),
	.FAB_RXVALIDH(GND),
	.FAB_SESSEND(VCC),
	.FAB_TXREADY(VCC),
	.FAB_VBUSVALID(VCC),
	.FAB_VSTATUS({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
	.FAB_XDATAIN({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
	.GTX_CLKPF(VCC),
	.I2C0_BCLK(VCC),
	.I2C0_SCL_F2H_SCP(VCC),
	.I2C0_SDA_F2H_SCP(VCC),
	.I2C1_BCLK(VCC),
	.I2C1_SCL_F2H_SCP(VCC),
	.I2C1_SDA_F2H_SCP(VCC),
	.MDIF(VCC),
	.MGPIO0A_F2H_GPIN(VCC),
	.MGPIO10A_F2H_GPIN(VCC),
	.MGPIO11A_F2H_GPIN(VCC),
	.MGPIO11B_F2H_GPIN(VCC),
	.MGPIO12A_F2H_GPIN(VCC),
	.MGPIO13A_F2H_GPIN(VCC),
	.MGPIO14A_F2H_GPIN(VCC),
	.MGPIO15A_F2H_GPIN(VCC),
	.MGPIO16A_F2H_GPIN(VCC),
	.MGPIO17B_F2H_GPIN(VCC),
	.MGPIO18B_F2H_GPIN(VCC),
	.MGPIO19B_F2H_GPIN(VCC),
	.MGPIO1A_F2H_GPIN(VCC),
	.MGPIO20B_F2H_GPIN(VCC),
	.MGPIO21B_F2H_GPIN(VCC),
	.MGPIO22B_F2H_GPIN(VCC),
	.MGPIO24B_F2H_GPIN(VCC),
	.MGPIO25B_F2H_GPIN(VCC),
	.MGPIO26B_F2H_GPIN(VCC),
	.MGPIO27B_F2H_GPIN(VCC),
	.MGPIO28B_F2H_GPIN(VCC),
	.MGPIO29B_F2H_GPIN(VCC),
	.MGPIO2A_F2H_GPIN(VCC),
	.MGPIO30B_F2H_GPIN(VCC),
	.MGPIO31B_F2H_GPIN(VCC),
	.MGPIO3A_F2H_GPIN(VCC),
	.MGPIO4A_F2H_GPIN(VCC),
	.MGPIO5A_F2H_GPIN(VCC),
	.MGPIO6A_F2H_GPIN(VCC),
	.MGPIO7A_F2H_GPIN(VCC),
	.MGPIO8A_F2H_GPIN(VCC),
	.MGPIO9A_F2H_GPIN(VCC),
	.MMUART0_CTS_F2H_SCP(VCC),
	.MMUART0_DCD_F2H_SCP(VCC),
	.MMUART0_DSR_F2H_SCP(VCC),
	.MMUART0_DTR_F2H_SCP(VCC),
	.MMUART0_RI_F2H_SCP(VCC),
	.MMUART0_RTS_F2H_SCP(VCC),
	.MMUART0_RXD_F2H_SCP(VCC),
	.MMUART0_SCK_F2H_SCP(VCC),
	.MMUART0_TXD_F2H_SCP(VCC),
	.MMUART1_CTS_F2H_SCP(VCC),
	.MMUART1_DCD_F2H_SCP(VCC),
	.MMUART1_DSR_F2H_SCP(VCC),
	.MMUART1_RI_F2H_SCP(VCC),
	.MMUART1_RTS_F2H_SCP(VCC),
	.MMUART1_RXD_F2H_SCP(VCC),
	.MMUART1_SCK_F2H_SCP(VCC),
	.MMUART1_TXD_F2H_SCP(VCC),
	.PER2_FABRIC_PRDATA({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
	.PER2_FABRIC_PREADY(VCC),
	.PER2_FABRIC_PSLVERR(VCC),
	.RCGF({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
	.RX_CLKPF(VCC),
	.RX_DVF(VCC),
	.RX_ERRF(VCC),
	.RX_EV(VCC),
	.RXDF({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
	.SLEEPHOLDREQ(VCC),
	.SMBALERT_NI0(VCC),
	.SMBALERT_NI1(VCC),
	.SMBSUS_NI0(VCC),
	.SMBSUS_NI1(VCC),
	.SPI0_CLK_IN(VCC),
	.SPI0_SDI_F2H_SCP(VCC),
	.SPI0_SDO_F2H_SCP(VCC),
	.SPI0_SS0_F2H_SCP(VCC),
	.SPI0_SS1_F2H_SCP(VCC),
	.SPI0_SS2_F2H_SCP(VCC),
	.SPI0_SS3_F2H_SCP(VCC),
	.SPI1_CLK_IN(VCC),
	.SPI1_SDI_F2H_SCP(VCC),
	.SPI1_SDO_F2H_SCP(VCC),
	.SPI1_SS0_F2H_SCP(VCC),
	.SPI1_SS1_F2H_SCP(VCC),
	.SPI1_SS2_F2H_SCP(VCC),
	.SPI1_SS3_F2H_SCP(VCC),
	.TX_CLKPF(VCC),
	.USER_MSS_GPIO_RESET_N(VCC),
	.USER_MSS_RESET_N(SYSRESET_0_POWER_ON_RESET_N),
	.XCLK_FAB(VCC),
	.CLK_MDDR_APB(VCC),
	.F_ARADDR_HADDR1({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
	.F_ARBURST_HTRANS1({GND, GND}),
	.F_ARID_HSEL1({GND, GND, GND, GND}),
	.F_ARLEN_HBURST1({GND, GND, GND, GND}),
	.F_ARLOCK_HMASTLOCK1({GND, GND}),
	.F_ARSIZE_HSIZE1({GND, GND}),
	.F_ARVALID_HWRITE1(GND),
	.F_AWADDR_HADDR0({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
	.F_AWBURST_HTRANS0({GND, GND}),
	.F_AWID_HSEL0({GND, GND, GND, GND}),
	.F_AWLEN_HBURST0({GND, GND, GND, GND}),
	.F_AWLOCK_HMASTLOCK0({GND, GND}),
	.F_AWSIZE_HSIZE0({GND, GND}),
	.F_AWVALID_HWRITE0(GND),
	.F_BREADY(GND),
	.F_RMW_AXI(GND),
	.F_RREADY(GND),
	.F_WDATA_HWDATA01({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
	.F_WID_HREADY01({GND, GND, GND, GND}),
	.F_WLAST(GND),
	.F_WSTRB({GND, GND, GND, GND, GND, GND, GND, GND}),
	.F_WVALID(GND),
	.FPGA_MDDR_ARESET_N(VCC),
	.MDDR_FABRIC_PADDR({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
	.MDDR_FABRIC_PENABLE(VCC),
	.MDDR_FABRIC_PSEL(VCC),
	.MDDR_FABRIC_PWDATA({VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC}),
	.MDDR_FABRIC_PWRITE(VCC),
	.PRESET_N(GND),
	.CAN_RXBUS_USBA_DATA1_MGPIO3A_IN(GND),
	.CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN(GND),
	.CAN_TXBUS_USBA_DATA0_MGPIO2A_IN(GND),
	.DM_IN({GND, GND, GND, GND, GND}),
	.DRAM_DQ_IN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),
	.DRAM_DQS_IN({GND, GND, GND, GND, GND}),
	.DRAM_FIFO_WE_IN({GND, GND, GND}),
	.I2C0_SCL_USBC_DATA1_MGPIO31B_IN(GND),
	.I2C0_SDA_USBC_DATA0_MGPIO30B_IN(GND),
	.I2C1_SCL_USBA_DATA4_MGPIO1A_IN(GND),
	.I2C1_SDA_USBA_DATA3_MGPIO0A_IN(GND),
	.MGPIO0B_IN(GND),
	.MGPIO10B_IN(GND),
	.MGPIO1B_IN(GND),
	.MGPIO25A_IN(GND),
	.MGPIO26A_IN(GND),
	.MGPIO27A_IN(GND),
	.MGPIO28A_IN(GND),
	.MGPIO29A_IN(GND),
	.MGPIO2B_IN(GND),
	.MGPIO30A_IN(GND),
	.MGPIO31A_IN(GND),
	.MGPIO3B_IN(GND),
	.MGPIO4B_IN(GND),
	.MGPIO5B_IN(GND),
	.MGPIO6B_IN(GND),
	.MGPIO7B_IN(GND),
	.MGPIO8B_IN(GND),
	.MGPIO9B_IN(GND),
	.MMUART0_CTS_USBC_DATA7_MGPIO19B_IN(GND),
	.MMUART0_DCD_MGPIO22B_IN(GND),
	.MMUART0_DSR_MGPIO20B_IN(GND),
	.MMUART0_DTR_USBC_DATA6_MGPIO18B_IN(GND),
	.MMUART0_RI_MGPIO21B_IN(GND),
	.MMUART0_RTS_USBC_DATA5_MGPIO17B_IN(GND),
	.MMUART0_RXD_USBC_STP_MGPIO28B_IN(MMUART_0_RXD_PAD_Y),
	.MMUART0_SCK_USBC_NXT_MGPIO29B_IN(GND),
	.MMUART0_TXD_USBC_DIR_MGPIO27B_IN(GND),
	.MMUART1_CTS_MGPIO13B_IN(GND),
	.MMUART1_DCD_MGPIO16B_IN(GND),
	.MMUART1_DSR_MGPIO14B_IN(GND),
	.MMUART1_DTR_MGPIO12B_IN(GND),
	.MMUART1_RI_MGPIO15B_IN(GND),
	.MMUART1_RTS_MGPIO11B_IN(GND),
	.MMUART1_RXD_USBC_DATA3_MGPIO26B_IN(GND),
	.MMUART1_SCK_USBC_DATA4_MGPIO25B_IN(GND),
	.MMUART1_TXD_USBC_DATA2_MGPIO24B_IN(GND),
	.RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN(GND),
	.RGMII_MDC_RMII_MDC_IN(GND),
	.RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN(GND),
	.RGMII_RX_CLK_IN(GND),
	.RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN(GND),
	.RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN(GND),
	.RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN(GND),
	.RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN(GND),
	.RGMII_RXD3_USBB_DATA4_IN(GND),
	.RGMII_TX_CLK_IN(GND),
	.RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN(GND),
	.RGMII_TXD0_RMII_TXD0_USBB_DIR_IN(GND),
	.RGMII_TXD1_RMII_TXD1_USBB_STP_IN(GND),
	.RGMII_TXD2_USBB_DATA5_IN(GND),
	.RGMII_TXD3_USBB_DATA6_IN(GND),
	.SPI0_SCK_USBA_XCLK_IN(GND),
	.SPI0_SDI_USBA_DIR_MGPIO5A_IN(GND),
	.SPI0_SDO_USBA_STP_MGPIO6A_IN(GND),
	.SPI0_SS0_USBA_NXT_MGPIO7A_IN(GND),
	.SPI0_SS1_USBA_DATA5_MGPIO8A_IN(GND),
	.SPI0_SS2_USBA_DATA6_MGPIO9A_IN(GND),
	.SPI0_SS3_USBA_DATA7_MGPIO10A_IN(GND),
	.SPI0_SS4_MGPIO19A_IN(GND),
	.SPI0_SS5_MGPIO20A_IN(GND),
	.SPI0_SS6_MGPIO21A_IN(GND),
	.SPI0_SS7_MGPIO22A_IN(GND),
	.SPI1_SCK_IN(GND),
	.SPI1_SDI_MGPIO11A_IN(GND),
	.SPI1_SDO_MGPIO12A_IN(GND),
	.SPI1_SS0_MGPIO13A_IN(GND),
	.SPI1_SS1_MGPIO14A_IN(GND),
	.SPI1_SS2_MGPIO15A_IN(GND),
	.SPI1_SS3_MGPIO16A_IN(GND),
	.SPI1_SS4_MGPIO17A_IN(GND),
	.SPI1_SS5_MGPIO18A_IN(GND),
	.SPI1_SS6_MGPIO23A_IN(GND),
	.SPI1_SS7_MGPIO24A_IN(GND),
	.USBC_XCLK_IN(GND),
	.USBD_DATA0_IN(GND),
	.USBD_DATA1_IN(GND),
	.USBD_DATA2_IN(GND),
	.USBD_DATA3_IN(GND),
	.USBD_DATA4_IN(GND),
	.USBD_DATA5_IN(GND),
	.USBD_DATA6_IN(GND),
	.USBD_DATA7_MGPIO23B_IN(GND),
	.USBD_DIR_IN(GND),
	.USBD_NXT_IN(GND),
	.USBD_STP_IN(GND),
	.USBD_XCLK_IN(GND),
	.CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT(CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT),
	.CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT(CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT),
	.CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT(CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT),
	.DRAM_ADDR(DRAM_ADDR[15:0]),
	.DRAM_BA(DRAM_BA[2:0]),
	.DRAM_CASN(DRAM_CASN),
	.DRAM_CKE(DRAM_CKE),
	.DRAM_CLK(DRAM_CLK),
	.DRAM_CSN(DRAM_CSN),
	.DRAM_DM_RDQS_OUT(DRAM_DM_RDQS_OUT[4:0]),
	.DRAM_DQ_OUT(DRAM_DQ_OUT[35:0]),
	.DRAM_DQS_OUT(DRAM_DQS_OUT[4:0]),
	.DRAM_FIFO_WE_OUT(DRAM_FIFO_WE_OUT[2:0]),
	.DRAM_ODT(DRAM_ODT),
	.DRAM_RASN(DRAM_RASN),
	.DRAM_RSTN(DRAM_RSTN),
	.DRAM_WEN(DRAM_WEN),
	.I2C0_SCL_USBC_DATA1_MGPIO31B_OUT(I2C0_SCL_USBC_DATA1_MGPIO31B_OUT),
	.I2C0_SDA_USBC_DATA0_MGPIO30B_OUT(I2C0_SDA_USBC_DATA0_MGPIO30B_OUT),
	.I2C1_SCL_USBA_DATA4_MGPIO1A_OUT(I2C1_SCL_USBA_DATA4_MGPIO1A_OUT),
	.I2C1_SDA_USBA_DATA3_MGPIO0A_OUT(I2C1_SDA_USBA_DATA3_MGPIO0A_OUT),
	.MGPIO0B_OUT(MGPIO0B_OUT),
	.MGPIO10B_OUT(MGPIO10B_OUT),
	.MGPIO1B_OUT(MGPIO1B_OUT),
	.MGPIO25A_OUT(MGPIO25A_OUT),
	.MGPIO26A_OUT(MGPIO26A_OUT),
	.MGPIO27A_OUT(MGPIO27A_OUT),
	.MGPIO28A_OUT(MGPIO28A_OUT),
	.MGPIO29A_OUT(MGPIO29A_OUT),
	.MGPIO2B_OUT(MGPIO2B_OUT),
	.MGPIO30A_OUT(MGPIO30A_OUT),
	.MGPIO31A_OUT(MGPIO31A_OUT),
	.MGPIO3B_OUT(MGPIO3B_OUT),
	.MGPIO4B_OUT(MGPIO4B_OUT),
	.MGPIO5B_OUT(MGPIO5B_OUT),
	.MGPIO6B_OUT(MGPIO6B_OUT),
	.MGPIO7B_OUT(MGPIO7B_OUT),
	.MGPIO8B_OUT(MGPIO8B_OUT),
	.MGPIO9B_OUT(MGPIO9B_OUT),
	.MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT(MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT),
	.MMUART0_DCD_MGPIO22B_OUT(MMUART0_DCD_MGPIO22B_OUT),
	.MMUART0_DSR_MGPIO20B_OUT(MMUART0_DSR_MGPIO20B_OUT),
	.MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT(MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT),
	.MMUART0_RI_MGPIO21B_OUT(MMUART0_RI_MGPIO21B_OUT),
	.MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT(MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT),
	.MMUART0_RXD_USBC_STP_MGPIO28B_OUT(MMUART0_RXD_USBC_STP_MGPIO28B_OUT),
	.MMUART0_SCK_USBC_NXT_MGPIO29B_OUT(MMUART0_SCK_USBC_NXT_MGPIO29B_OUT),
	.MMUART0_TXD_USBC_DIR_MGPIO27B_OUT(MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OUT),
	.MMUART1_CTS_MGPIO13B_OUT(MMUART1_CTS_MGPIO13B_OUT),
	.MMUART1_DCD_MGPIO16B_OUT(MMUART1_DCD_MGPIO16B_OUT),
	.MMUART1_DSR_MGPIO14B_OUT(MMUART1_DSR_MGPIO14B_OUT),
	.MMUART1_DTR_MGPIO12B_OUT(MMUART1_DTR_MGPIO12B_OUT),
	.MMUART1_RI_MGPIO15B_OUT(MMUART1_RI_MGPIO15B_OUT),
	.MMUART1_RTS_MGPIO11B_OUT(MMUART1_RTS_MGPIO11B_OUT),
	.MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT(MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT),
	.MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT(MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT),
	.MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT(MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT),
	.RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT(RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT),
	.RGMII_MDC_RMII_MDC_OUT(RGMII_MDC_RMII_MDC_OUT),
	.RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT(RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT),
	.RGMII_RX_CLK_OUT(RGMII_RX_CLK_OUT),
	.RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT(RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT),
	.RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT(RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT),
	.RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT(RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT),
	.RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT(RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT),
	.RGMII_RXD3_USBB_DATA4_OUT(RGMII_RXD3_USBB_DATA4_OUT),
	.RGMII_TX_CLK_OUT(RGMII_TX_CLK_OUT),
	.RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT(RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT),
	.RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT(RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT),
	.RGMII_TXD1_RMII_TXD1_USBB_STP_OUT(RGMII_TXD1_RMII_TXD1_USBB_STP_OUT),
	.RGMII_TXD2_USBB_DATA5_OUT(RGMII_TXD2_USBB_DATA5_OUT),
	.RGMII_TXD3_USBB_DATA6_OUT(RGMII_TXD3_USBB_DATA6_OUT),
	.SPI0_SCK_USBA_XCLK_OUT(SPI0_SCK_USBA_XCLK_OUT),
	.SPI0_SDI_USBA_DIR_MGPIO5A_OUT(SPI0_SDI_USBA_DIR_MGPIO5A_OUT),
	.SPI0_SDO_USBA_STP_MGPIO6A_OUT(SPI0_SDO_USBA_STP_MGPIO6A_OUT),
	.SPI0_SS0_USBA_NXT_MGPIO7A_OUT(SPI0_SS0_USBA_NXT_MGPIO7A_OUT),
	.SPI0_SS1_USBA_DATA5_MGPIO8A_OUT(SPI0_SS1_USBA_DATA5_MGPIO8A_OUT),
	.SPI0_SS2_USBA_DATA6_MGPIO9A_OUT(SPI0_SS2_USBA_DATA6_MGPIO9A_OUT),
	.SPI0_SS3_USBA_DATA7_MGPIO10A_OUT(SPI0_SS3_USBA_DATA7_MGPIO10A_OUT),
	.SPI0_SS4_MGPIO19A_OUT(SPI0_SS4_MGPIO19A_OUT),
	.SPI0_SS5_MGPIO20A_OUT(SPI0_SS5_MGPIO20A_OUT),
	.SPI0_SS6_MGPIO21A_OUT(SPI0_SS6_MGPIO21A_OUT),
	.SPI0_SS7_MGPIO22A_OUT(SPI0_SS7_MGPIO22A_OUT),
	.SPI1_SCK_OUT(SPI1_SCK_OUT),
	.SPI1_SDI_MGPIO11A_OUT(SPI1_SDI_MGPIO11A_OUT),
	.SPI1_SDO_MGPIO12A_OUT(SPI1_SDO_MGPIO12A_OUT),
	.SPI1_SS0_MGPIO13A_OUT(SPI1_SS0_MGPIO13A_OUT),
	.SPI1_SS1_MGPIO14A_OUT(SPI1_SS1_MGPIO14A_OUT),
	.SPI1_SS2_MGPIO15A_OUT(SPI1_SS2_MGPIO15A_OUT),
	.SPI1_SS3_MGPIO16A_OUT(SPI1_SS3_MGPIO16A_OUT),
	.SPI1_SS4_MGPIO17A_OUT(SPI1_SS4_MGPIO17A_OUT),
	.SPI1_SS5_MGPIO18A_OUT(SPI1_SS5_MGPIO18A_OUT),
	.SPI1_SS6_MGPIO23A_OUT(SPI1_SS6_MGPIO23A_OUT),
	.SPI1_SS7_MGPIO24A_OUT(SPI1_SS7_MGPIO24A_OUT),
	.USBC_XCLK_OUT(USBC_XCLK_OUT),
	.USBD_DATA0_OUT(USBD_DATA0_OUT),
	.USBD_DATA1_OUT(USBD_DATA1_OUT),
	.USBD_DATA2_OUT(USBD_DATA2_OUT),
	.USBD_DATA3_OUT(USBD_DATA3_OUT),
	.USBD_DATA4_OUT(USBD_DATA4_OUT),
	.USBD_DATA5_OUT(USBD_DATA5_OUT),
	.USBD_DATA6_OUT(USBD_DATA6_OUT),
	.USBD_DATA7_MGPIO23B_OUT(USBD_DATA7_MGPIO23B_OUT),
	.USBD_DIR_OUT(USBD_DIR_OUT),
	.USBD_NXT_OUT(USBD_NXT_OUT),
	.USBD_STP_OUT(USBD_STP_OUT),
	.USBD_XCLK_OUT(USBD_XCLK_OUT),
	.CAN_RXBUS_USBA_DATA1_MGPIO3A_OE(CAN_RXBUS_USBA_DATA1_MGPIO3A_OE),
	.CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE(CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE),
	.CAN_TXBUS_USBA_DATA0_MGPIO2A_OE(CAN_TXBUS_USBA_DATA0_MGPIO2A_OE),
	.DM_OE(DM_OE[4:0]),
	.DRAM_DQ_OE(DRAM_DQ_OE[35:0]),
	.DRAM_DQS_OE(DRAM_DQS_OE[4:0]),
	.I2C0_SCL_USBC_DATA1_MGPIO31B_OE(I2C0_SCL_USBC_DATA1_MGPIO31B_OE),
	.I2C0_SDA_USBC_DATA0_MGPIO30B_OE(I2C0_SDA_USBC_DATA0_MGPIO30B_OE),
	.I2C1_SCL_USBA_DATA4_MGPIO1A_OE(I2C1_SCL_USBA_DATA4_MGPIO1A_OE),
	.I2C1_SDA_USBA_DATA3_MGPIO0A_OE(I2C1_SDA_USBA_DATA3_MGPIO0A_OE),
	.MGPIO0B_OE(MGPIO0B_OE),
	.MGPIO10B_OE(MGPIO10B_OE),
	.MGPIO1B_OE(MGPIO1B_OE),
	.MGPIO25A_OE(MGPIO25A_OE),
	.MGPIO26A_OE(MGPIO26A_OE),
	.MGPIO27A_OE(MGPIO27A_OE),
	.MGPIO28A_OE(MGPIO28A_OE),
	.MGPIO29A_OE(MGPIO29A_OE),
	.MGPIO2B_OE(MGPIO2B_OE),
	.MGPIO30A_OE(MGPIO30A_OE),
	.MGPIO31A_OE(MGPIO31A_OE),
	.MGPIO3B_OE(MGPIO3B_OE),
	.MGPIO4B_OE(MGPIO4B_OE),
	.MGPIO5B_OE(MGPIO5B_OE),
	.MGPIO6B_OE(MGPIO6B_OE),
	.MGPIO7B_OE(MGPIO7B_OE),
	.MGPIO8B_OE(MGPIO8B_OE),
	.MGPIO9B_OE(MGPIO9B_OE),
	.MMUART0_CTS_USBC_DATA7_MGPIO19B_OE(MMUART0_CTS_USBC_DATA7_MGPIO19B_OE),
	.MMUART0_DCD_MGPIO22B_OE(MMUART0_DCD_MGPIO22B_OE),
	.MMUART0_DSR_MGPIO20B_OE(MMUART0_DSR_MGPIO20B_OE),
	.MMUART0_DTR_USBC_DATA6_MGPIO18B_OE(MMUART0_DTR_USBC_DATA6_MGPIO18B_OE),
	.MMUART0_RI_MGPIO21B_OE(MMUART0_RI_MGPIO21B_OE),
	.MMUART0_RTS_USBC_DATA5_MGPIO17B_OE(MMUART0_RTS_USBC_DATA5_MGPIO17B_OE),
	.MMUART0_RXD_USBC_STP_MGPIO28B_OE(MMUART0_RXD_USBC_STP_MGPIO28B_OE),
	.MMUART0_SCK_USBC_NXT_MGPIO29B_OE(MMUART0_SCK_USBC_NXT_MGPIO29B_OE),
	.MMUART0_TXD_USBC_DIR_MGPIO27B_OE(MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OE),
	.MMUART1_CTS_MGPIO13B_OE(MMUART1_CTS_MGPIO13B_OE),
	.MMUART1_DCD_MGPIO16B_OE(MMUART1_DCD_MGPIO16B_OE),
	.MMUART1_DSR_MGPIO14B_OE(MMUART1_DSR_MGPIO14B_OE),
	.MMUART1_DTR_MGPIO12B_OE(MMUART1_DTR_MGPIO12B_OE),
	.MMUART1_RI_MGPIO15B_OE(MMUART1_RI_MGPIO15B_OE),
	.MMUART1_RTS_MGPIO11B_OE(MMUART1_RTS_MGPIO11B_OE),
	.MMUART1_RXD_USBC_DATA3_MGPIO26B_OE(MMUART1_RXD_USBC_DATA3_MGPIO26B_OE),
	.MMUART1_SCK_USBC_DATA4_MGPIO25B_OE(MMUART1_SCK_USBC_DATA4_MGPIO25B_OE),
	.MMUART1_TXD_USBC_DATA2_MGPIO24B_OE(MMUART1_TXD_USBC_DATA2_MGPIO24B_OE),
	.RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE(RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE),
	.RGMII_MDC_RMII_MDC_OE(RGMII_MDC_RMII_MDC_OE),
	.RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE(RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE),
	.RGMII_RX_CLK_OE(RGMII_RX_CLK_OE),
	.RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE(RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE),
	.RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE(RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE),
	.RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE(RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE),
	.RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE(RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE),
	.RGMII_RXD3_USBB_DATA4_OE(RGMII_RXD3_USBB_DATA4_OE),
	.RGMII_TX_CLK_OE(RGMII_TX_CLK_OE),
	.RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE(RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE),
	.RGMII_TXD0_RMII_TXD0_USBB_DIR_OE(RGMII_TXD0_RMII_TXD0_USBB_DIR_OE),
	.RGMII_TXD1_RMII_TXD1_USBB_STP_OE(RGMII_TXD1_RMII_TXD1_USBB_STP_OE),
	.RGMII_TXD2_USBB_DATA5_OE(RGMII_TXD2_USBB_DATA5_OE),
	.RGMII_TXD3_USBB_DATA6_OE(RGMII_TXD3_USBB_DATA6_OE),
	.SPI0_SCK_USBA_XCLK_OE(SPI0_SCK_USBA_XCLK_OE),
	.SPI0_SDI_USBA_DIR_MGPIO5A_OE(SPI0_SDI_USBA_DIR_MGPIO5A_OE),
	.SPI0_SDO_USBA_STP_MGPIO6A_OE(SPI0_SDO_USBA_STP_MGPIO6A_OE),
	.SPI0_SS0_USBA_NXT_MGPIO7A_OE(SPI0_SS0_USBA_NXT_MGPIO7A_OE),
	.SPI0_SS1_USBA_DATA5_MGPIO8A_OE(SPI0_SS1_USBA_DATA5_MGPIO8A_OE),
	.SPI0_SS2_USBA_DATA6_MGPIO9A_OE(SPI0_SS2_USBA_DATA6_MGPIO9A_OE),
	.SPI0_SS3_USBA_DATA7_MGPIO10A_OE(SPI0_SS3_USBA_DATA7_MGPIO10A_OE),
	.SPI0_SS4_MGPIO19A_OE(SPI0_SS4_MGPIO19A_OE),
	.SPI0_SS5_MGPIO20A_OE(SPI0_SS5_MGPIO20A_OE),
	.SPI0_SS6_MGPIO21A_OE(SPI0_SS6_MGPIO21A_OE),
	.SPI0_SS7_MGPIO22A_OE(SPI0_SS7_MGPIO22A_OE),
	.SPI1_SCK_OE(SPI1_SCK_OE),
	.SPI1_SDI_MGPIO11A_OE(SPI1_SDI_MGPIO11A_OE),
	.SPI1_SDO_MGPIO12A_OE(SPI1_SDO_MGPIO12A_OE),
	.SPI1_SS0_MGPIO13A_OE(SPI1_SS0_MGPIO13A_OE),
	.SPI1_SS1_MGPIO14A_OE(SPI1_SS1_MGPIO14A_OE),
	.SPI1_SS2_MGPIO15A_OE(SPI1_SS2_MGPIO15A_OE),
	.SPI1_SS3_MGPIO16A_OE(SPI1_SS3_MGPIO16A_OE),
	.SPI1_SS4_MGPIO17A_OE(SPI1_SS4_MGPIO17A_OE),
	.SPI1_SS5_MGPIO18A_OE(SPI1_SS5_MGPIO18A_OE),
	.SPI1_SS6_MGPIO23A_OE(SPI1_SS6_MGPIO23A_OE),
	.SPI1_SS7_MGPIO24A_OE(SPI1_SS7_MGPIO24A_OE),
	.USBC_XCLK_OE(USBC_XCLK_OE),
	.USBD_DATA0_OE(USBD_DATA0_OE),
	.USBD_DATA1_OE(USBD_DATA1_OE),
	.USBD_DATA2_OE(USBD_DATA2_OE),
	.USBD_DATA3_OE(USBD_DATA3_OE),
	.USBD_DATA4_OE(USBD_DATA4_OE),
	.USBD_DATA5_OE(USBD_DATA5_OE),
	.USBD_DATA6_OE(USBD_DATA6_OE),
	.USBD_DATA7_MGPIO23B_OE(USBD_DATA7_MGPIO23B_OE),
	.USBD_DIR_OE(USBD_DIR_OE),
	.USBD_NXT_OE(USBD_NXT_OE),
	.USBD_STP_OE(USBD_STP_OE),
	.USBD_XCLK_OE(USBD_XCLK_OE)
);
defparam MSS_ADLIB_INST.INIT=1417'h00000000001B090000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007800000007800000000000000000000000000000003FFFFFFFD800000803C33C00000000709300000003FFFFE400000010000010000000000E11C000001FEDFDC010842108421000001FE34001FF8000000400000000020051007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
defparam MSS_ADLIB_INST.ACT_UBITS=56'hFFFFFFFFFFFFFF;
defparam MSS_ADLIB_INST.MEMORYFILE="ENVM_init.mem";
  GND GND_Z (
	.Y(GND)
);
  VCC VCC_Z (
	.Y(VCC)
);
endmodule /* Linker_Design_MSS */

module Linker_Design_OSC_0_OSC (
  OSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
)
;
output OSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC ;
wire OSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC ;
wire GND ;
wire VCC ;
// @9:23
  RCOSC_25_50MHZ I_RCOSC_25_50MHZ (
	.CLKOUT(OSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC)
);
defparam I_RCOSC_25_50MHZ.FREQUENCY=50.0;
  GND GND_Z (
	.Y(GND)
);
  VCC VCC_Z (
	.Y(VCC)
);
endmodule /* Linker_Design_OSC_0_OSC */

module Linker_Design (
  DEVRST_N,
  MMUART_0_RXD,
  MMUART_0_TXD
)
;
input DEVRST_N ;
input MMUART_0_RXD ;
output MMUART_0_TXD /* synthesis syn_tristate = 1 */ ;
wire DEVRST_N ;
wire MMUART_0_RXD ;
wire MMUART_0_TXD ;
wire [31:0] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR;
wire [1:0] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE;
wire [1:1] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS;
wire [31:0] Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA;
wire [15:0] CoreAHBLite_0_AHBmslave3_HADDR;
wire [1:0] CoreAHBLite_0_AHBmslave3_HSIZE;
wire [31:0] CoreAHBLite_0_AHBmslave3_HWDATA;
wire [1:1] \CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE ;
wire [31:0] CoreAHBLite_0_AHBmslave3_HRDATA_m;
wire [3:0] \CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState ;
wire [1:1] \CoreAHBLite_0.matrix4x16.M0GATEDHSIZE ;
wire [28:28] \CoreAHBLite_0.matrix4x16.masterstage_0.PREGATEDHADDR ;
wire [2:2] \CoreAHBLite_0.matrix4x16.masterstage_0.SADDRSEL_2 ;
wire [7:3] \CoreAHBLite_0.matrix4x16.masterstage_0.SADDRSEL_1 ;
wire [0:0] \CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.MASTERADDRINPROG_i_a2_c ;
wire [0:0] \CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.MASTERADDRINPROG_i_a2_d_c_c ;
wire [0:0] \CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.MASTERADDRINPROG_i_a2_0_0_0_0 ;
wire FCCC_0_GL0_0 ;
wire Linker_Design_MSS_0_MSS_RESET_N_M2F ;
wire Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE ;
wire GND ;
wire CoreAHBLite_0_AHBmslave3_HWRITE ;
wire OSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC ;
wire FCCC_0_LOCK ;
wire SYSRESET_0_POWER_ON_RESET_N ;
wire VCC ;
wire \CoreAHBLite_0.matrix4x16.masterstage_0.masterRegAddrSel  ;
wire \CoreAHBLite_0.matrix4x16.masterstage_0.regHTRANS  ;
wire \CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.N_152  ;
wire \CoreAHBLite_0.matrix4x16.M0GATEDHWRITE  ;
wire \CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.N_156  ;
wire \CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_pre24  ;
wire \CoreAHBLite_0.matrix4x16.slavestage_3.HTRANS_0  ;
wire CoreAHBLite_0_AHBmslave3_HREADY ;
wire \CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv_i_0  ;
wire \CoreAHBLite_0.matrix4x16.masterstage_0.un1_HREADY_M_pre24_1_i_0  ;
// @22:634
  SYSRESET SYSRESET_0 (
	.DEVRST_N(DEVRST_N),
	.POWER_ON_RESET_N(SYSRESET_0_POWER_ON_RESET_N)
);
// @22:292
  CoreAHBLite_Z3 CoreAHBLite_0 (
	.regHSIZE(\CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE [1]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE[1:0]),
	.PREGATEDHADDR(\CoreAHBLite_0.matrix4x16.masterstage_0.PREGATEDHADDR [28]),
	.M0GATEDHSIZE(\CoreAHBLite_0.matrix4x16.M0GATEDHSIZE [1]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS[1]),
	.SADDRSEL_2(\CoreAHBLite_0.matrix4x16.masterstage_0.SADDRSEL_2 [2]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[0]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[1]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[2]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[3]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[4]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[5]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[6]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[7]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[8]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[9]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[10]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[11]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[12]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[13]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[14]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[15]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[28]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[30]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[31]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[29]),
	.arbRegSMCurrentState_3(\CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState [3]),
	.arbRegSMCurrentState_0(\CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState [0]),
	.SADDRSEL_1_4(\CoreAHBLite_0.matrix4x16.masterstage_0.SADDRSEL_1 [7]),
	.SADDRSEL_1_0(\CoreAHBLite_0.matrix4x16.masterstage_0.SADDRSEL_1 [3]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[31:0]),
	.CoreAHBLite_0_AHBmslave3_HWDATA(CoreAHBLite_0_AHBmslave3_HWDATA[31:0]),
	.CoreAHBLite_0_AHBmslave3_HADDR(CoreAHBLite_0_AHBmslave3_HADDR[15:0]),
	.MASTERADDRINPROG_i_a2_d_c_c(\CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.MASTERADDRINPROG_i_a2_d_c_c [0]),
	.MASTERADDRINPROG_i_a2_c(\CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.MASTERADDRINPROG_i_a2_c [0]),
	.MASTERADDRINPROG_i_a2_0_0_0_0(\CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.MASTERADDRINPROG_i_a2_0_0_0_0 [0]),
	.CoreAHBLite_0_AHBmslave3_HSIZE(CoreAHBLite_0_AHBmslave3_HSIZE[1:0]),
	.Linker_Design_MSS_0_MSS_RESET_N_M2F(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.FCCC_0_GL0_0(FCCC_0_GL0_0),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE),
	.regHTRANS(\CoreAHBLite_0.matrix4x16.masterstage_0.regHTRANS ),
	.masterRegAddrSel(\CoreAHBLite_0.matrix4x16.masterstage_0.masterRegAddrSel ),
	.M0GATEDHWRITE(\CoreAHBLite_0.matrix4x16.M0GATEDHWRITE ),
	.HREADY_M_pre24(\CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_pre24 ),
	.N_156(\CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.N_156 ),
	.CoreAHBLite_0_AHBmslave3_HREADY(CoreAHBLite_0_AHBmslave3_HREADY),
	.un1_HREADY_M_pre24_1_i_0(\CoreAHBLite_0.matrix4x16.masterstage_0.un1_HREADY_M_pre24_1_i_0 ),
	.HREADY_M_iv_i_0(\CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv_i_0 ),
	.CoreAHBLite_0_AHBmslave3_HWRITE(CoreAHBLite_0_AHBmslave3_HWRITE),
	.N_152(\CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.N_152 ),
	.HTRANS_0(\CoreAHBLite_0.matrix4x16.slavestage_3.HTRANS_0 )
);
// @22:573
  Linker_Design_COREAHBLSRAM_0_COREAHBLSRAM_19s_32s_32s_16384s_512s_0s COREAHBLSRAM_0 (
	.CoreAHBLite_0_AHBmslave3_HADDR(CoreAHBLite_0_AHBmslave3_HADDR[15:0]),
	.CoreAHBLite_0_AHBmslave3_HSIZE(CoreAHBLite_0_AHBmslave3_HSIZE[1:0]),
	.arbRegSMCurrentState_0(\CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState [0]),
	.arbRegSMCurrentState_3(\CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState [3]),
	.CoreAHBLite_0_AHBmslave3_HRDATA_m(CoreAHBLite_0_AHBmslave3_HRDATA_m[31:0]),
	.SADDRSEL_2(\CoreAHBLite_0.matrix4x16.masterstage_0.SADDRSEL_2 [2]),
	.PREGATEDHADDR(\CoreAHBLite_0.matrix4x16.masterstage_0.PREGATEDHADDR [28]),
	.M0GATEDHSIZE(\CoreAHBLite_0.matrix4x16.M0GATEDHSIZE [1]),
	.MASTERADDRINPROG_i_a2_0_0_0_0(\CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.MASTERADDRINPROG_i_a2_0_0_0_0 [0]),
	.MASTERADDRINPROG_i_a2_d_c_c(\CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.MASTERADDRINPROG_i_a2_d_c_c [0]),
	.SADDRSEL_1_4(\CoreAHBLite_0.matrix4x16.masterstage_0.SADDRSEL_1 [7]),
	.SADDRSEL_1_0(\CoreAHBLite_0.matrix4x16.masterstage_0.SADDRSEL_1 [3]),
	.MASTERADDRINPROG_i_a2_c(\CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.MASTERADDRINPROG_i_a2_c [0]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE[1]),
	.regHSIZE(\CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE [1]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[31]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[28]),
	.CoreAHBLite_0_AHBmslave3_HWDATA(CoreAHBLite_0_AHBmslave3_HWDATA[31:0]),
	.Linker_Design_MSS_0_MSS_RESET_N_M2F(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.FCCC_0_GL0_0(FCCC_0_GL0_0),
	.CoreAHBLite_0_AHBmslave3_HWRITE(CoreAHBLite_0_AHBmslave3_HWRITE),
	.CoreAHBLite_0_AHBmslave3_HREADY(CoreAHBLite_0_AHBmslave3_HREADY),
	.N_152(\CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.N_152 ),
	.HTRANS_0(\CoreAHBLite_0.matrix4x16.slavestage_3.HTRANS_0 ),
	.HREADY_M_pre24(\CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_pre24 ),
	.N_156(\CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.N_156 ),
	.M0GATEDHWRITE(\CoreAHBLite_0.matrix4x16.M0GATEDHWRITE ),
	.masterRegAddrSel(\CoreAHBLite_0.matrix4x16.masterstage_0.masterRegAddrSel ),
	.regHTRANS(\CoreAHBLite_0.matrix4x16.masterstage_0.regHTRANS )
);
// @22:592
  Linker_Design_FCCC_0_FCCC FCCC_0 (
	.FCCC_0_GL0_0(FCCC_0_GL0_0),
	.FCCC_0_LOCK(FCCC_0_LOCK),
	.OSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC(OSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC)
);
// @22:601
  Linker_Design_MSS Linker_Design_MSS_0 (
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_0(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[0]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_1(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[1]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_2(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[2]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_3(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[3]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_4(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[4]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_5(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[5]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_6(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[6]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_7(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[7]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_8(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[8]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_9(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[9]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_10(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[10]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_11(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[11]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_12(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[12]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_13(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[13]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_14(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[14]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_15(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[15]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_28(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[28]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_29(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[29]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_30(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[30]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR_31(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HADDR[31]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HSIZE[1:0]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HTRANS[1]),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWDATA[31:0]),
	.CoreAHBLite_0_AHBmslave3_HRDATA_m(CoreAHBLite_0_AHBmslave3_HRDATA_m[31:0]),
	.Linker_Design_MSS_0_MSS_RESET_N_M2F(Linker_Design_MSS_0_MSS_RESET_N_M2F),
	.MMUART_0_TXD(MMUART_0_TXD),
	.MMUART_0_RXD(MMUART_0_RXD),
	.Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE(Linker_Design_MSS_0_FIC_0_AHB_MASTER_HWRITE),
	.FCCC_0_GL0_0(FCCC_0_GL0_0),
	.HREADY_M_iv_i_0(\CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv_i_0 ),
	.un1_HREADY_M_pre24_1_i_0(\CoreAHBLite_0.matrix4x16.masterstage_0.un1_HREADY_M_pre24_1_i_0 ),
	.FCCC_0_LOCK(FCCC_0_LOCK),
	.SYSRESET_0_POWER_ON_RESET_N(SYSRESET_0_POWER_ON_RESET_N)
);
// @22:621
  Linker_Design_OSC_0_OSC OSC_0 (
	.OSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC(OSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC)
);
  GND GND_Z (
	.Y(GND)
);
  VCC VCC_Z (
	.Y(VCC)
);
endmodule /* Linker_Design */

