# Actel Physical design constraints file

# Version: v11.3 11.3.0.112

# Design Name:  

# Input Netlist Format: EDIF 

# Family: SmartFusion2 , Die: M2S050T , Package: 896 FBGA , Speed grade: STD 

# Date generated: Fri Apr 04 11:20:15 2014 


#
# IO banks setting
#

set_iobank Bank1 -vcci 2.50 -fixed no
set_iobank Bank4 -vcci 3.30 -fixed yes

#
# Local clock constraints
#


#
# Region constraints
#


#
# I/O constraints
#

set_io DEVRST_N -DIRECTION INPUT -pinname AC27
set_io MMUART_0_RXD -DIRECTION INPUT -pinname L23 -fixed yes
set_io MMUART_0_TXD -DIRECTION OUTPUT -pinname H27 -fixed yes

#
# Core cell constraints
#

