

##### START OF TIMING REPORT #####[
# Timing Report written on Thu Apr 03 16:14:15 2014
#


Top view:               Linker_Design
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    E:\Ranjith\Linker_Design\synthesis\synthesis_1\Linker_Design_fsm.sdc
                       
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: 0.457

                                                     Requested     Estimated     Requested     Estimated               Clock        Clock              
Starting Clock                                       Frequency     Frequency     Period        Period        Slack     Type         Group              
-------------------------------------------------------------------------------------------------------------------------------------------------------
Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     116.4 MHz     10.000        8.589         1.411     inferred     Inferred_clkgroup_0
System                                               100.0 MHz     895.2 MHz     10.000        1.117         8.883     system       system_clkgroup    
=======================================================================================================================================================



Clock Relationships
*******************

Clocks                                                                                              |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                          Ending                                            |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                            System                                            |  0.000       0.782  |  No paths    -      |  No paths    -      |  No paths    -    
System                                            Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock  |  0.000       1.211  |  No paths    -      |  No paths    -      |  No paths    -    
Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock  System                                            |  0.000       0.868  |  No paths    -      |  No paths    -      |  No paths    -    
Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock  Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock  |  0.000       0.457  |  No paths    -      |  No paths    -      |  No paths    -    
==========================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                                                 Starting                                                                                           Arrival          
Instance                                                                         Reference                                            Type     Pin     Net                          Time        Slack
                                                                                 Clock                                                                                                               
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[6]      Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       arbRegSMCurrentState[6]      0.061       0.680
CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[10]     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       arbRegSMCurrentState[10]     0.061       0.680
CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[14]     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       arbRegSMCurrentState[14]     0.061       0.680
CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[0]                               Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       regHADDR[0]                  0.061       0.680
CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[1]                               Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       regHADDR[1]                  0.061       0.680
CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[2]                               Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       regHADDR[2]                  0.061       0.680
CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[3]                               Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       regHADDR[3]                  0.061       0.680
CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[4]                               Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       regHADDR[4]                  0.061       0.680
CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[5]                               Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       regHADDR[5]                  0.061       0.680
CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[6]                               Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       regHADDR[6]                  0.061       0.680
=====================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                           Starting                                                                                                    Required          
Instance                                   Reference                                            Type     Pin     Net                                   Time         Slack
                                           Clock                                                                                                                         
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
COREAHBLSRAM_0.U_AHBLSramIf.HADDR_d[0]     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      D       CoreAHBLite_0_AHBmslave3_HADDR[0]     0.179        0.457
COREAHBLSRAM_0.U_AHBLSramIf.HADDR_d[1]     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      D       CoreAHBLite_0_AHBmslave3_HADDR[1]     0.179        0.457
COREAHBLSRAM_0.U_AHBLSramIf.HADDR_d[2]     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      D       CoreAHBLite_0_AHBmslave3_HADDR[2]     0.179        0.457
COREAHBLSRAM_0.U_AHBLSramIf.HADDR_d[3]     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      D       CoreAHBLite_0_AHBmslave3_HADDR[3]     0.179        0.457
COREAHBLSRAM_0.U_AHBLSramIf.HADDR_d[4]     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      D       CoreAHBLite_0_AHBmslave3_HADDR[4]     0.179        0.457
COREAHBLSRAM_0.U_AHBLSramIf.HADDR_d[5]     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      D       CoreAHBLite_0_AHBmslave3_HADDR[5]     0.179        0.457
COREAHBLSRAM_0.U_AHBLSramIf.HADDR_d[6]     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      D       CoreAHBLite_0_AHBmslave3_HADDR[6]     0.179        0.457
COREAHBLSRAM_0.U_AHBLSramIf.HADDR_d[7]     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      D       CoreAHBLite_0_AHBmslave3_HADDR[7]     0.179        0.457
COREAHBLSRAM_0.U_AHBLSramIf.HADDR_d[8]     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      D       CoreAHBLite_0_AHBmslave3_HADDR[8]     0.179        0.457
COREAHBLSRAM_0.U_AHBLSramIf.HADDR_d[9]     Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock     SLE      D       CoreAHBLite_0_AHBmslave3_HADDR[9]     0.179        0.457
=========================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Propagation time:                        0.636
    + Clock delay at starting point:         0.000 (ideal)
    - Requested Period:                      0.000
    - Hold time:                             0.179
    - Clock delay at ending point:           0.000 (ideal)
    = Slack (critical) :                     0.457

    Number of logic level(s):                1
    Starting point:                          CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[6] / Q
    Ending point:                            CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[5] / D
    The start point is clocked by            Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            Linker_Design_FCCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK

Instance / Net                                                                              Pin      Pin               Arrival     No. of    
Name                                                                               Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------
CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[6]        SLE      Q        Out     0.061     0.061       -         
arbRegSMCurrentState[6]                                                            Net      -        -       0.409     -           1         
CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState_ns[5]     CFG4     A        In      -         0.471       -         
CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState_ns[5]     CFG4     Y        Out     0.054     0.525       -         
arbRegSMCurrentState_ns[5]                                                         Net      -        -       0.111     -           1         
CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[5]        SLE      D        In      -         0.636       -         
=============================================================================================================================================




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                       Starting                                                                                           Arrival          
Instance                                               Reference     Type               Pin           Net                                                 Time        Slack
                                                       Clock                                                                                                               
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
OSC_0.I_RCOSC_25_50MHZ                                 System        RCOSC_25_50MHZ     CLKOUT        OSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     0.000       1.117
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.block6     System        RAM1K18            A_DOUT[0]     readData6[0]                                        0.000       1.761
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block6     System        RAM1K18            A_DOUT[0]     readData6[0]                                        0.000       1.761
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.block6     System        RAM1K18            A_DOUT[0]     readData6[0]                                        0.000       1.761
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.block6     System        RAM1K18            A_DOUT[0]     readData6[0]                                        0.000       1.761
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.block6     System        RAM1K18            A_DOUT[0]     readData6[0]                                        0.000       1.761
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block6     System        RAM1K18            A_DOUT[0]     readData6[0]                                        0.000       1.761
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_0.block6     System        RAM1K18            A_DOUT[1]     readData6[1]                                        0.000       1.761
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_2.block6     System        RAM1K18            A_DOUT[1]     readData6[1]                                        0.000       1.761
COREAHBLSRAM_0.U_SramCtrlIf.genblk1\.byte_1.block6     System        RAM1K18            A_DOUT[1]     readData6[1]                                        0.000       1.761
===========================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                 Starting                                                                                      Required          
Instance                                         Reference     Type     Pin                Net                                                 Time         Slack
                                                 Clock                                                                                                           
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
FCCC_0.CCC_INST                                  System        CCC      RCOSC_25_50MHZ     OSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     0.000        0.782
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[0]     System        SLE      D                  ram_rdata[0]                                        0.179        1.211
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[1]     System        SLE      D                  ram_rdata[1]                                        0.179        1.211
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[2]     System        SLE      D                  ram_rdata[2]                                        0.179        1.211
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[3]     System        SLE      D                  ram_rdata[3]                                        0.179        1.211
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[4]     System        SLE      D                  ram_rdata[4]                                        0.179        1.211
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[5]     System        SLE      D                  ram_rdata[5]                                        0.179        1.211
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[6]     System        SLE      D                  ram_rdata[6]                                        0.179        1.211
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[7]     System        SLE      D                  ram_rdata[7]                                        0.179        1.211
COREAHBLSRAM_0.U_SramCtrlIf.sramahb_rdata[8]     System        SLE      D                  ram_rdata[8]                                        0.179        1.211
=================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Propagation time:                        0.782
    + Clock delay at starting point:         0.000 (ideal)
-0.000
    - Requested Period:                      0.000
    - Hold time:                             0.000
    - Clock delay at ending point:           0.000 (ideal)
0.000
    = Slack (non-critical) :                 0.782

    Number of logic level(s):                0
    Starting point:                          OSC_0.I_RCOSC_25_50MHZ / CLKOUT
    Ending point:                            FCCC_0.CCC_INST / RCOSC_25_50MHZ
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                         Pin                Pin               Arrival     No. of    
Name                                                Type               Name               Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------
OSC_0.I_RCOSC_25_50MHZ                              RCOSC_25_50MHZ     CLKOUT             Out     0.000     0.000       -         
OSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     Net                -                  -       0.782     -           1         
FCCC_0.CCC_INST                                     CCC                RCOSC_25_50MHZ     In      -         0.782       -         
==================================================================================================================================



##### END OF TIMING REPORT #####]

