#--  Synopsys, Inc.
#--  Version F-2012.03M-SP2-SF2 
#--  Project file D:\Appsnotes\2012\RAM_initilization\FROM_MSS\Posted_design\M2S_AC392_DF\FABRIC_SRAM_INIT\synthesis\run_options.txt
#--  Written on Wed Feb 27 12:19:24 2013


#project files
add_file -verilog "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/Actel/SgCore/CCC/2.0.005/ccc_comps.v"
add_file -verilog "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/work/Top/CCC_0/Top_CCC_0_CCC.v"
add_file -verilog "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/work/FABRIC_SRAM_INIT_MSS/FABRIC_SRAM_INIT_MSS_tmp_syn.v"
add_file -verilog "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/work/FABRIC_SRAM_INIT_MSS/FABRIC_SRAM_INIT_MSS.v"
add_file -verilog "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/work/FABRIC_SRAM_INIT/FABRIC_SRAM_INIT.v"
add_file -verilog "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/Actel/SgCore/OSC/0.0.502/osc_comps.v"
add_file -verilog "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/work/Top/OSC_0/Top_OSC_0_OSC.v"
add_file -verilog "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/hdl/mem_apb_wrp.v"
add_file -verilog "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/hdl/mux_blk.v"
add_file -verilog "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/work/RAM_with_wrapper/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM.v"
add_file -verilog "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/work/RAM_with_wrapper/RAM_with_wrapper.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/Actel/DirectCore/CoreAHBLite/4.0.9/rtl/vlog/core_obfuscated/coreahblite_addrdec.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/Actel/DirectCore/CoreAHBLite/4.0.9/rtl/vlog/core_obfuscated/coreahblite_defaultslavesm.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/Actel/DirectCore/CoreAHBLite/4.0.9/rtl/vlog/core_obfuscated/coreahblite_masterstage.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/Actel/DirectCore/CoreAHBLite/4.0.9/rtl/vlog/core_obfuscated/coreahblite_slavearbiter.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/Actel/DirectCore/CoreAHBLite/4.0.9/rtl/vlog/core_obfuscated/coreahblite_slavestage.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/Actel/DirectCore/CoreAHBLite/4.0.9/rtl/vlog/core_obfuscated/coreahblite_matrix2x16.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/Actel/DirectCore/CoreAHBLite/4.0.9/rtl/vlog/core_obfuscated/coreahblite.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/Actel/DirectCore/COREAHBTOAPB3/3.0.4/rtl/vlog/core_obfuscated/coreahbtoapb3_ahbtoapbsm.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/Actel/DirectCore/COREAHBTOAPB3/3.0.4/rtl/vlog/core_obfuscated/coreahbtoapb3_penablescheduler.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/Actel/DirectCore/COREAHBTOAPB3/3.0.4/rtl/vlog/core_obfuscated/coreahbtoapb3_apbaddrdata.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/Actel/DirectCore/COREAHBTOAPB3/3.0.4/rtl/vlog/core_obfuscated/coreahbtoapb3.v"
add_file -verilog -lib COREAPB3_LIB "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/Actel/DirectCore/CoreAPB3/4.0.5/rtl/vlog/core_obfuscated/coreapb3_muxptob3.v"
add_file -verilog -lib COREAPB3_LIB "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/Actel/DirectCore/CoreAPB3/4.0.5/rtl/vlog/core_obfuscated/coreapb3_iaddr_reg.v"
add_file -verilog -lib COREAPB3_LIB "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/Actel/DirectCore/CoreAPB3/4.0.5/rtl/vlog/core_obfuscated/coreapb3.v"
add_file -verilog "D:/Appsnotes/2012/RAM_initilization/FROM_MSS/Posted_design/M2S_AC392_DF/FABRIC_SRAM_INIT/component/work/Top/Top.v"


#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology SmartFusion2
set_option -part M2S050T
set_option -package FBGA896
set_option -speed_grade STD
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "Top"

# mapper_options
set_option -frequency 100.000
set_option -write_verilog 0
set_option -write_vhdl 0

# Actel G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 5
set_option -disable_io_insertion 0
set_option -opcond COMWC
set_option -retiming 0
set_option -report_path 0
set_option -update_models_cp 0
set_option -preserve_registers 0

# NFilter
set_option -popfeed 0
set_option -constprop 0
set_option -createhierarchy 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./Top.edn"
impl -active "synthesis"
