library verilog;
use verilog.vl_types.all;
entity CLK_GEN is
    generic(
        CLK_PERIOD      : integer := 10000;
        DUTY_CYCLE      : integer := 50;
        TCLK_HIGH       : vl_notype;
        TCLK_LOW        : vl_notype
    );
    port(
        CLK             : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of CLK_PERIOD : constant is 1;
    attribute mti_svvh_generic_type of DUTY_CYCLE : constant is 1;
    attribute mti_svvh_generic_type of TCLK_HIGH : constant is 3;
    attribute mti_svvh_generic_type of TCLK_LOW : constant is 3;
end CLK_GEN;
