//for testing the read and writes to SRAM from simple user interface in simulation

`timescale 1 ns/100 ps
module user_rd_wr(
       rd_enable_user,
       wr_enable_user
    );

output  rd_enable_user;
output  wr_enable_user;

reg rd_enable_user;
reg wr_enable_user;

 
initial
begin
        rd_enable_user = 1'b0;
        wr_enable_user = 1'b0;
	#64000
        rd_enable_user = 1'b1;
        wr_enable_user = 1'b0;
    #8000       
		rd_enable_user = 1'b0;
		wr_enable_user = 1'b1;
    #8000       
		rd_enable_user = 1'b1;
		wr_enable_user = 1'b0;
end
   
endmodule