library verilog;
use verilog.vl_types.all;
entity CAHBLTIIl is
    port(
        HCLK            : in     vl_logic;
        HRESETN         : in     vl_logic;
        CAHBLTlIl       : in     vl_logic;
        CAHBLTOll       : out    vl_logic;
        CAHBLTIll       : out    vl_logic
    );
end CAHBLTIIl;
