library verilog;
use verilog.vl_types.all;
entity CAHBLTO1lI is
    port(
        HCLK            : in     vl_logic;
        HRESETN         : in     vl_logic;
        CAHBLTI1lI      : in     vl_logic;
        CAHBLTIl1       : in     vl_logic;
        CAHBLTl1lI      : out    vl_logic;
        CAHBLTlO1       : out    vl_logic_vector(31 downto 0);
        CAHBLTII1       : out    vl_logic_vector(2 downto 0);
        CAHBLTlI1       : out    vl_logic;
        CAHBLTOl1       : out    vl_logic;
        CAHBLTOO0I      : out    vl_logic_vector(31 downto 0);
        CAHBLTIO0I      : out    vl_logic;
        CAHBLTOI1       : out    vl_logic;
        CAHBLTI1l       : in     vl_logic_vector(1 downto 0);
        CAHBLTlO0I      : in     vl_logic_vector(1 downto 0);
        CAHBLTOI0I      : in     vl_logic_vector(1 downto 0);
        CAHBLTII0I      : out    vl_logic_vector(1 downto 0);
        CAHBLTlI0I      : out    vl_logic_vector(1 downto 0);
        CAHBLTOl0I      : out    vl_logic_vector(1 downto 0);
        CAHBLTIl0I      : in     vl_logic_vector(31 downto 0);
        CAHBLTOO0       : in     vl_logic;
        CAHBLTll0I      : in     vl_logic_vector(2 downto 0);
        CAHBLTO00I      : in     vl_logic;
        CAHBLTI00I      : in     vl_logic;
        CAHBLTl00I      : in     vl_logic_vector(31 downto 0);
        CAHBLTIO0       : in     vl_logic;
        CAHBLTO10I      : in     vl_logic_vector(2 downto 0);
        CAHBLTI10I      : in     vl_logic;
        CAHBLTl10I      : in     vl_logic;
        HWDATA_M0       : in     vl_logic_vector(31 downto 0);
        HWDATA_M1       : in     vl_logic_vector(31 downto 0)
    );
end CAHBLTO1lI;
