library verilog;
use verilog.vl_types.all;
entity mem_apb_wrp is
    generic(
        DATA_WIDTH      : integer := 8;
        ADDR_WIDTH      : integer := 8
    );
    port(
        PCLK            : in     vl_logic;
        PENABLE         : in     vl_logic;
        PSEL            : in     vl_logic;
        PRESETN         : in     vl_logic;
        PWRITE          : in     vl_logic;
        PREADY          : out    vl_logic;
        PSLVERR         : out    vl_logic;
        PADDR           : in     vl_logic_vector;
        PWDATA          : in     vl_logic_vector;
        PRDATA          : out    vl_logic_vector;
        rd_enable       : out    vl_logic;
        wr_enable       : out    vl_logic;
        wclk            : out    vl_logic;
        rclk            : out    vl_logic;
        raddr           : out    vl_logic_vector;
        waddr           : out    vl_logic_vector;
        mem_data_in     : out    vl_logic_vector;
        mem_data_out    : in     vl_logic_vector;
        INT_OUT         : out    vl_logic;
        SEL             : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of DATA_WIDTH : constant is 1;
    attribute mti_svvh_generic_type of ADDR_WIDTH : constant is 1;
end mem_apb_wrp;
