// Actel Corporation Proprietary and Confidential
// Copyright 2010 Actel Corporation.  All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
// Revision Information:
// 10Feb10              Production Release Version 3.1
// SVN Revision Information:
// SVN $Revision: 15830 $
// SVN $Date: 2011-09-02 07:10:38 -0700 (Fri, 02 Sep 2011) $
`timescale 1ns/1ps
module
CAHBLTO
#
(
parameter
[
0
:
0
]
MEMSPACE
=
0
,
parameter
[
15
:
0
]
CAHBLTI
=
0
,
parameter
[
16
:
0
]
CAHBLTl
=
(
2
**
17
)
-
1
)
(
input
[
31
:
0
]
CAHBLTOI,
input
CAHBLTII,
output
wire
[
16
:
0
]
CAHBLTlI,
output
wire
[
31
:
0
]
CAHBLTOl
)
;
localparam
CAHBLTIl
=
16
'b
0000000000000001
;
localparam
CAHBLTll
=
16
'b
0000000000000010
;
localparam
CAHBLTO0
=
16
'b
0000000000000100
;
localparam
CAHBLTI0
=
16
'b
0000000000001000
;
localparam
CAHBLTl0
=
16
'b
0000000000010000
;
localparam
CAHBLTO1
=
16
'b
0000000000100000
;
localparam
CAHBLTI1
=
16
'b
0000000001000000
;
localparam
CAHBLTl1
=
16
'b
0000000010000000
;
localparam
CAHBLTOOI
=
16
'b
0000000100000000
;
localparam
CAHBLTIOI
=
16
'b
0000001000000000
;
localparam
CAHBLTlOI
=
16
'b
0000010000000000
;
localparam
CAHBLTOII
=
16
'b
0000100000000000
;
localparam
CAHBLTIII
=
16
'b
0001000000000000
;
localparam
CAHBLTlII
=
16
'b
0010000000000000
;
localparam
CAHBLTOlI
=
16
'b
0100000000000000
;
localparam
CAHBLTIlI
=
16
'b
1000000000000000
;
localparam
CAHBLTllI
=
16
'b
0000000000000000
;
generate
begin
:
CAHBLTO0I
reg
[
15
:
0
]
CAHBLTI0I
;
reg
[
15
:
0
]
CAHBLTl0I
;
reg
CAHBLTO1I
;
reg
[
31
:
0
]
CAHBLTI1I
;
wire
[
16
:
0
]
CAHBLTl1I
;
if
(
MEMSPACE
==
0
)
begin
:
CAHBLTOOl
wire
[
3
:
0
]
CAHBLTIOl
;
assign
CAHBLTIOl
=
CAHBLTOI
[
31
:
28
]
;
always
@(*)
begin
CAHBLTI1I
[
31
:
0
]
=
CAHBLTOI
[
31
:
0
]
;
case
(
CAHBLTIOl
)
4
'h
0
:
begin
if
(
CAHBLTII
==
1
'b
0
)
CAHBLTI0I
[
15
:
0
]
=
CAHBLTIl
;
else
begin
CAHBLTI1I
[
28
]
=
1
'b
1
;
CAHBLTI0I
[
15
:
0
]
=
CAHBLTll
;
end
end
4
'h
1
:
begin
if
(
CAHBLTII
==
1
'b
0
)
CAHBLTI0I
[
15
:
0
]
=
CAHBLTll
;
else
begin
CAHBLTI1I
[
28
]
=
1
'b
0
;
CAHBLTI0I
[
15
:
0
]
=
CAHBLTIl
;
end
end
4
'h
2
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTO0
;
4
'h
3
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTI0
;
4
'h
4
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTl0
;
4
'h
5
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTO1
;
4
'h
6
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTI1
;
4
'h
7
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTl1
;
4
'h
8
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTOOI
;
4
'h
9
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTIOI
;
4
'h
A
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTlOI
;
4
'h
B
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTOII
;
4
'h
C
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTIII
;
4
'h
D
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTlII
;
4
'h
E
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTOlI
;
4
'h
F
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTIlI
;
endcase
CAHBLTl0I
=
CAHBLTI0I
&
~
CAHBLTI
;
CAHBLTO1I
=
|
(
CAHBLTI0I
&
CAHBLTI
)
;
end
end
else
begin
:
CAHBLTlOl
wire
[
3
:
0
]
CAHBLTOIl
;
assign
CAHBLTOIl
=
CAHBLTOI
[
27
:
24
]
;
always
@(*)
begin
CAHBLTI1I
[
31
:
0
]
=
CAHBLTOI
[
31
:
0
]
;
case
(
CAHBLTOIl
)
4
'h
0
:
begin
if
(
CAHBLTII
==
1
'b
0
)
CAHBLTI0I
[
15
:
0
]
=
CAHBLTIl
;
else
begin
CAHBLTI1I
[
24
]
=
1
'b
1
;
CAHBLTI0I
[
15
:
0
]
=
CAHBLTll
;
end
end
4
'h
1
:
begin
if
(
CAHBLTII
==
1
'b
0
)
CAHBLTI0I
[
15
:
0
]
=
CAHBLTll
;
else
begin
CAHBLTI1I
[
24
]
=
1
'b
0
;
CAHBLTI0I
[
15
:
0
]
=
CAHBLTIl
;
end
end
4
'h
2
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTO0
;
4
'h
3
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTI0
;
4
'h
4
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTl0
;
4
'h
5
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTO1
;
4
'h
6
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTI1
;
4
'h
7
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTl1
;
4
'h
8
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTOOI
;
4
'h
9
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTIOI
;
4
'h
A
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTlOI
;
4
'h
B
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTOII
;
4
'h
C
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTIII
;
4
'h
D
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTlII
;
4
'h
E
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTOlI
;
4
'h
F
:
CAHBLTI0I
[
15
:
0
]
=
CAHBLTIlI
;
endcase
CAHBLTl0I
=
CAHBLTI0I
&
~
CAHBLTI
;
CAHBLTO1I
=
|
(
CAHBLTI0I
&
CAHBLTI
)
;
end
end
assign
CAHBLTl1I
[
16
:
0
]
=
{
CAHBLTO1I
,
CAHBLTl0I
[
15
:
0
]
}
;
assign
CAHBLTOl
[
31
:
0
]
=
CAHBLTI1I
[
31
:
0
]
;
assign
CAHBLTlI
[
16
:
0
]
=
CAHBLTl1I
[
16
:
0
]
;
end
endgenerate
endmodule
