
module CCC ( 
  Y0,
  Y1,
  Y2,
  Y3,
  PRDATA,
  LOCK,
  BUSY,
  CLK0,
  CLK1,
  CLK2,
  CLK3,
  NGMUX0_SEL,
  NGMUX1_SEL,
  NGMUX2_SEL,
  NGMUX3_SEL,
  NGMUX0_HOLD_N,
  NGMUX1_HOLD_N,
  NGMUX2_HOLD_N,
  NGMUX3_HOLD_N,
  NGMUX0_ARST_N,
  NGMUX1_ARST_N,
  NGMUX2_ARST_N,
  NGMUX3_ARST_N,
  PLL_BYPASS_N,
  PLL_ARST_N,
  PLL_POWERDOWN_N,
  GPD0_ARST_N,
  GPD1_ARST_N,
  GPD2_ARST_N,
  GPD3_ARST_N,
  PRESET_N,
  PCLK,
  PSEL,
  PENABLE,
  PWRITE,
  PADDR,
  PWDATA,
  CLK0_PAD,
  CLK1_PAD,
  CLK2_PAD,
  CLK3_PAD,
  GL0,
  GL1,
  GL2,
  GL3,
  RCOSC_25_50MHZ,
  RCOSC_1MHZ,
  XTLOSC );

/* synthesis syn_black_box */
/* synthesis syn_noprune=1 */

output Y0;
output Y1;
output Y2;
output Y3;
output [7:0] PRDATA;
output LOCK;
output BUSY;

input  CLK0;
input  CLK1;
input  CLK2;
input  CLK3;
input  NGMUX0_SEL;
input  NGMUX1_SEL;
input  NGMUX2_SEL;
input  NGMUX3_SEL;
input  NGMUX0_HOLD_N;
input  NGMUX1_HOLD_N;
input  NGMUX2_HOLD_N;
input  NGMUX3_HOLD_N;
input  NGMUX0_ARST_N;
input  NGMUX1_ARST_N;
input  NGMUX2_ARST_N;
input  NGMUX3_ARST_N;
input  PLL_BYPASS_N;
input  PLL_ARST_N;
input  PLL_POWERDOWN_N;
input  GPD0_ARST_N;
input  GPD1_ARST_N;
input  GPD2_ARST_N;
input  GPD3_ARST_N;
input  PRESET_N;
input  PCLK;
input  PSEL;
input  PENABLE;
input  PWRITE;
input  [7:2] PADDR;
input  [7:0] PWDATA;


input CLK0_PAD;
input CLK1_PAD;
input CLK2_PAD;
input CLK3_PAD;
output GL0;
output GL1;
output GL2;
output GL3;
input RCOSC_25_50MHZ;
input RCOSC_1MHZ;
input XTLOSC;

parameter INIT         = 212'h0;
parameter VCOFREQUENCY = "0000.000";

endmodule
