library verilog;
use verilog.vl_types.all;
entity CAPB3O is
    generic(
        APB_DWIDTH      : vl_logic_vector(5 downto 0) := (Hi1, Hi0, Hi0, Hi0, Hi0, Hi0);
        MADDR_BITS      : vl_logic_vector(5 downto 0) := (Hi1, Hi0, Hi0, Hi0, Hi0, Hi0)
    );
    port(
        PCLK            : in     vl_logic;
        PRESETN         : in     vl_logic;
        PENABLE         : in     vl_logic;
        PSEL            : in     vl_logic;
        PADDR           : in     vl_logic_vector(31 downto 0);
        PWRITE          : in     vl_logic;
        PWDATA          : in     vl_logic_vector(31 downto 0);
        PRDATA          : out    vl_logic_vector(31 downto 0);
        CAPB3I          : out    vl_logic_vector(31 downto 0)
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of APB_DWIDTH : constant is 2;
    attribute mti_svvh_generic_type of MADDR_BITS : constant is 2;
end CAPB3O;
