library verilog;
use verilog.vl_types.all;
entity RAM_with_wrapper is
    port(
        PADDR           : in     vl_logic_vector(7 downto 0);
        PCLK            : in     vl_logic;
        PENABLE         : in     vl_logic;
        PRESETN         : in     vl_logic;
        PSEL            : in     vl_logic;
        PWDATA          : in     vl_logic_vector(7 downto 0);
        PWRITE          : in     vl_logic;
        raddr_user      : in     vl_logic_vector(5 downto 0);
        rclk_user       : in     vl_logic;
        rd_enable_user  : in     vl_logic;
        waddr_user      : in     vl_logic_vector(5 downto 0);
        wclk_user       : in     vl_logic;
        wdata_user      : in     vl_logic_vector(7 downto 0);
        wr_enable_user  : in     vl_logic;
        INT_OUT         : out    vl_logic;
        PRDATA          : out    vl_logic_vector(7 downto 0);
        PREADY          : out    vl_logic;
        PSLVERR         : out    vl_logic;
        SEL             : out    vl_logic;
        rdata_user      : out    vl_logic_vector(7 downto 0)
    );
end RAM_with_wrapper;
