library verilog;
use verilog.vl_types.all;
entity mux_blk is
    generic(
        DATA_WIDTH      : integer := 8;
        ADDR_WIDTH      : integer := 8
    );
    port(
        rd_enable_user  : in     vl_logic;
        wr_enable_user  : in     vl_logic;
        wclk_user       : in     vl_logic;
        rclk_user       : in     vl_logic;
        raddr_user      : in     vl_logic_vector;
        waddr_user      : in     vl_logic_vector;
        wdata_user      : in     vl_logic_vector;
        rdata_user      : out    vl_logic_vector;
        rd_enable_init  : in     vl_logic;
        wr_enable_init  : in     vl_logic;
        wclk_init       : in     vl_logic;
        rclk_init       : in     vl_logic;
        raddr_init      : in     vl_logic_vector;
        waddr_init      : in     vl_logic_vector;
        mem_data_in_init: in     vl_logic_vector;
        mem_data_out_init: out    vl_logic_vector;
        rd_en           : out    vl_logic;
        wr_en           : out    vl_logic;
        wclk            : out    vl_logic;
        rclk            : out    vl_logic;
        raddr           : out    vl_logic_vector;
        waddr           : out    vl_logic_vector;
        wdata           : out    vl_logic_vector;
        rdata           : in     vl_logic_vector;
        sel             : in     vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of DATA_WIDTH : constant is 1;
    attribute mti_svvh_generic_type of ADDR_WIDTH : constant is 1;
end mux_blk;
