//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Wed Feb 27 12:09:11 2013
// Version: v11.0BetaSP1 10.9.3.17
//////////////////////////////////////////////////////////////////////

`timescale 1 ns/100 ps

// FABRIC_SRAM_INIT
module FABRIC_SRAM_INIT(
    // Inputs
    FIC_0_AHB_M_HRDATA,
    FIC_0_AHB_M_HREADY,
    FIC_0_AHB_M_HRESP,
    MCCC_CLK_BASE,
    MCCC_CLK_BASE_PLL_LOCK,
    MMUART_0_RXD_F2M,
    MSS_INT_F2M,
    MSS_RESET_N_F2M,
    // Outputs
    FIC_0_AHB_M_HADDR,
    FIC_0_AHB_M_HSIZE,
    FIC_0_AHB_M_HTRANS,
    FIC_0_AHB_M_HWDATA,
    FIC_0_AHB_M_HWRITE,
    MCCC_MPLL_LOCK,
    MMUART_0_TXD_M2F,
    MSS_RESET_N_M2F
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input  [31:0] FIC_0_AHB_M_HRDATA;
input         FIC_0_AHB_M_HREADY;
input         FIC_0_AHB_M_HRESP;
input         MCCC_CLK_BASE;
input         MCCC_CLK_BASE_PLL_LOCK;
input         MMUART_0_RXD_F2M;
input  [15:0] MSS_INT_F2M;
input         MSS_RESET_N_F2M;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [31:0] FIC_0_AHB_M_HADDR;
output [1:0]  FIC_0_AHB_M_HSIZE;
output [1:0]  FIC_0_AHB_M_HTRANS;
output [31:0] FIC_0_AHB_M_HWDATA;
output        FIC_0_AHB_M_HWRITE;
output        MCCC_MPLL_LOCK;
output        MMUART_0_TXD_M2F;
output        MSS_RESET_N_M2F;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire   [31:0] FIC_0_AHB_MASTER_HADDR;
wire   [31:0] FIC_0_AHB_M_HRDATA;
wire          FIC_0_AHB_M_HREADY;
wire          FIC_0_AHB_M_HRESP;
wire   [1:0]  FIC_0_AHB_MASTER_HSIZE;
wire   [1:0]  FIC_0_AHB_MASTER_HTRANS;
wire   [31:0] FIC_0_AHB_MASTER_HWDATA;
wire          FIC_0_AHB_MASTER_HWRITE;
wire          MCCC_CLK_BASE;
wire          MCCC_CLK_BASE_PLL_LOCK;
wire          MCCC_MPLL_LOCK_net_0;
wire          MMUART_0_RXD_F2M;
wire          MMUART_0_TXD_M2F_net_0;
wire   [15:0] MSS_INT_F2M;
wire          MSS_RESET_N_F2M;
wire          MSS_RESET_N_M2F_net_0;
wire          MMUART_0_TXD_M2F_net_1;
wire          MSS_RESET_N_M2F_net_1;
wire          FIC_0_AHB_MASTER_HWRITE_net_0;
wire          MCCC_MPLL_LOCK_net_1;
wire   [31:0] FIC_0_AHB_MASTER_HADDR_net_0;
wire   [1:0]  FIC_0_AHB_MASTER_HTRANS_net_0;
wire   [1:0]  FIC_0_AHB_MASTER_HSIZE_net_0;
wire   [31:0] FIC_0_AHB_MASTER_HWDATA_net_0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign MMUART_0_TXD_M2F_net_1        = MMUART_0_TXD_M2F_net_0;
assign MMUART_0_TXD_M2F              = MMUART_0_TXD_M2F_net_1;
assign MSS_RESET_N_M2F_net_1         = MSS_RESET_N_M2F_net_0;
assign MSS_RESET_N_M2F               = MSS_RESET_N_M2F_net_1;
assign FIC_0_AHB_MASTER_HWRITE_net_0 = FIC_0_AHB_MASTER_HWRITE;
assign FIC_0_AHB_M_HWRITE            = FIC_0_AHB_MASTER_HWRITE_net_0;
assign MCCC_MPLL_LOCK_net_1          = MCCC_MPLL_LOCK_net_0;
assign MCCC_MPLL_LOCK                = MCCC_MPLL_LOCK_net_1;
assign FIC_0_AHB_MASTER_HADDR_net_0  = FIC_0_AHB_MASTER_HADDR;
assign FIC_0_AHB_M_HADDR[31:0]       = FIC_0_AHB_MASTER_HADDR_net_0;
assign FIC_0_AHB_MASTER_HTRANS_net_0 = FIC_0_AHB_MASTER_HTRANS;
assign FIC_0_AHB_M_HTRANS[1:0]       = FIC_0_AHB_MASTER_HTRANS_net_0;
assign FIC_0_AHB_MASTER_HSIZE_net_0  = FIC_0_AHB_MASTER_HSIZE;
assign FIC_0_AHB_M_HSIZE[1:0]        = FIC_0_AHB_MASTER_HSIZE_net_0;
assign FIC_0_AHB_MASTER_HWDATA_net_0 = FIC_0_AHB_MASTER_HWDATA;
assign FIC_0_AHB_M_HWDATA[31:0]      = FIC_0_AHB_MASTER_HWDATA_net_0;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------FABRIC_SRAM_INIT_MSS
FABRIC_SRAM_INIT_MSS FABRIC_SRAM_INIT_MSS_0(
        // Inputs
        .MCCC_CLK_BASE          ( MCCC_CLK_BASE ),
        .MMUART_0_RXD_F2M       ( MMUART_0_RXD_F2M ),
        .FIC_0_AHB_M_HREADY     ( FIC_0_AHB_M_HREADY ),
        .FIC_0_AHB_M_HRESP      ( FIC_0_AHB_M_HRESP ),
        .MSS_RESET_N_F2M        ( MSS_RESET_N_F2M ),
        .MCCC_CLK_BASE_PLL_LOCK ( MCCC_CLK_BASE_PLL_LOCK ),
        .FIC_0_AHB_M_HRDATA     ( FIC_0_AHB_M_HRDATA ),
        .MSS_INT_F2M            ( MSS_INT_F2M ),
        // Outputs
        .MMUART_0_TXD_M2F       ( MMUART_0_TXD_M2F_net_0 ),
        .FIC_0_AHB_M_HWRITE     ( FIC_0_AHB_MASTER_HWRITE ),
        .MSS_RESET_N_M2F        ( MSS_RESET_N_M2F_net_0 ),
        .MCCC_MPLL_LOCK         ( MCCC_MPLL_LOCK_net_0 ),
        .FIC_0_AHB_M_HADDR      ( FIC_0_AHB_MASTER_HADDR ),
        .FIC_0_AHB_M_HWDATA     ( FIC_0_AHB_MASTER_HWDATA ),
        .FIC_0_AHB_M_HSIZE      ( FIC_0_AHB_MASTER_HSIZE ),
        .FIC_0_AHB_M_HTRANS     ( FIC_0_AHB_MASTER_HTRANS ) 
        );


endmodule
