library verilog;
use verilog.vl_types.all;
entity CAHBLTO is
    generic(
        MEMSPACE        : vl_logic_vector(0 downto 0) := (others => Hi0);
        CAHBLTI         : vl_logic_vector(15 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
        CAHBLTl         : vl_logic_vector(16 downto 0) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1)
    );
    port(
        CAHBLTOI        : in     vl_logic_vector(31 downto 0);
        CAHBLTII        : in     vl_logic;
        CAHBLTlI        : out    vl_logic_vector(16 downto 0);
        CAHBLTOl        : out    vl_logic_vector(31 downto 0)
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of MEMSPACE : constant is 2;
    attribute mti_svvh_generic_type of CAHBLTI : constant is 2;
    attribute mti_svvh_generic_type of CAHBLTl : constant is 2;
end CAHBLTO;
