//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Wed Feb 27 12:13:58 2013
// Version: v11.0BetaSP1 10.9.3.17
//////////////////////////////////////////////////////////////////////

`timescale 1 ns/100 ps

// Top
module Top(
    // Inputs
    DEVRST_N,
    MMUART_0_RXD_F2M,
    raddr_user,
    rclk_user,
    rd_enable_user,
    waddr_user,
    wclk_user,
    wdata_user,
    wr_enable_user,
    // Outputs
    LOCK,
    MCCC_MPLL_LOCK,
    MMUART_0_TXD_M2F,
    SEL,
    rdata_user
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input        DEVRST_N;
input        MMUART_0_RXD_F2M;
input  [5:0] raddr_user;
input        rclk_user;
input        rd_enable_user;
input  [5:0] waddr_user;
input        wclk_user;
input  [7:0] wdata_user;
input        wr_enable_user;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output       LOCK;
output       MCCC_MPLL_LOCK;
output       MMUART_0_TXD_M2F;
output       SEL;
output [7:0] rdata_user;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire          CCC_0_GL0;
wire   [31:0] CoreAHBLite_0_AHBmslave3_HADDR;
wire   [2:0]  CoreAHBLite_0_AHBmslave3_HBURST;
wire          CoreAHBLite_0_AHBmslave3_HMASTLOCK;
wire   [3:0]  CoreAHBLite_0_AHBmslave3_HPROT;
wire   [31:0] CoreAHBLite_0_AHBmslave3_HRDATA;
wire          CoreAHBLite_0_AHBmslave3_HREADY;
wire          CoreAHBLite_0_AHBmslave3_HREADYOUT;
wire   [1:0]  CoreAHBLite_0_AHBmslave3_HRESP;
wire          CoreAHBLite_0_AHBmslave3_HSELx;
wire   [2:0]  CoreAHBLite_0_AHBmslave3_HSIZE;
wire   [1:0]  CoreAHBLite_0_AHBmslave3_HTRANS;
wire   [31:0] CoreAHBLite_0_AHBmslave3_HWDATA;
wire          CoreAHBLite_0_AHBmslave3_HWRITE;
wire   [31:0] COREAHBTOAPB3_0_APBmaster_PADDR;
wire          COREAHBTOAPB3_0_APBmaster_PENABLE;
wire   [31:0] COREAHBTOAPB3_0_APBmaster_PRDATA;
wire          COREAHBTOAPB3_0_APBmaster_PREADY;
wire          COREAHBTOAPB3_0_APBmaster_PSELx;
wire          COREAHBTOAPB3_0_APBmaster_PSLVERR;
wire   [31:0] COREAHBTOAPB3_0_APBmaster_PWDATA;
wire          COREAHBTOAPB3_0_APBmaster_PWRITE;
wire          CoreAPB3_0_APBmslave0_PENABLE;
wire          CoreAPB3_0_APBmslave0_PREADY;
wire          CoreAPB3_0_APBmslave0_PSELx;
wire          CoreAPB3_0_APBmslave0_PSLVERR;
wire          CoreAPB3_0_APBmslave0_PWRITE;
wire          DEVRST_N;
wire   [31:0] FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HADDR;
wire   [31:0] FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HRDATA;
wire          FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HREADY;
wire   [1:0]  FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HTRANS;
wire   [31:0] FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HWDATA;
wire          FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HWRITE;
wire          FABRIC_SRAM_INIT_0_MSS_RESET_N_M2F;
wire          LOCK_net_0;
wire          MCCC_MPLL_LOCK_net_0;
wire          MMUART_0_RXD_F2M;
wire          MMUART_0_TXD_M2F_net_0;
wire          OSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;
wire   [5:0]  raddr_user;
wire          RAM_with_wrapper_0_INT_OUT;
wire          rclk_user;
wire          rd_enable_user;
wire   [7:0]  rdata_user_net_0;
wire          SEL_net_0;
wire          SYSRESET_0_POWER_ON_RESET_N;
wire   [5:0]  waddr_user;
wire          wclk_user;
wire   [7:0]  wdata_user;
wire          wr_enable_user;
wire          SEL_net_1;
wire          MCCC_MPLL_LOCK_net_1;
wire          MMUART_0_TXD_M2F_net_1;
wire          LOCK_net_1;
wire   [7:0]  rdata_user_net_1;
wire   [15:0] MSS_INT_F2M_net_0;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire   [15:1] MSS_INT_F2M_const_net_0;
wire          GND_net;
wire   [7:2]  PADDR_const_net_0;
wire   [7:0]  PWDATA_const_net_0;
wire          VCC_net;
wire   [31:0] IADDR_const_net_0;
wire   [2:0]  HBURST_M0_const_net_0;
wire   [3:0]  HPROT_M0_const_net_0;
wire   [31:0] HADDR_M1_const_net_0;
wire   [1:0]  HTRANS_M1_const_net_0;
wire   [2:0]  HSIZE_M1_const_net_0;
wire   [2:0]  HBURST_M1_const_net_0;
wire   [3:0]  HPROT_M1_const_net_0;
wire   [31:0] HWDATA_M1_const_net_0;
wire   [31:0] HRDATA_S0_const_net_0;
wire   [1:0]  HRESP_S0_const_net_0;
wire   [31:0] HRDATA_S1_const_net_0;
wire   [1:0]  HRESP_S1_const_net_0;
wire   [31:0] HRDATA_S2_const_net_0;
wire   [1:0]  HRESP_S2_const_net_0;
wire   [31:0] HRDATA_S4_const_net_0;
wire   [1:0]  HRESP_S4_const_net_0;
wire   [31:0] HRDATA_S5_const_net_0;
wire   [1:0]  HRESP_S5_const_net_0;
wire   [31:0] HRDATA_S6_const_net_0;
wire   [1:0]  HRESP_S6_const_net_0;
wire   [31:0] HRDATA_S7_const_net_0;
wire   [1:0]  HRESP_S7_const_net_0;
wire   [31:0] HRDATA_S8_const_net_0;
wire   [1:0]  HRESP_S8_const_net_0;
wire   [31:0] HRDATA_S9_const_net_0;
wire   [1:0]  HRESP_S9_const_net_0;
wire   [31:0] HRDATA_S10_const_net_0;
wire   [1:0]  HRESP_S10_const_net_0;
wire   [31:0] HRDATA_S11_const_net_0;
wire   [1:0]  HRESP_S11_const_net_0;
wire   [31:0] HRDATA_S12_const_net_0;
wire   [1:0]  HRESP_S12_const_net_0;
wire   [31:0] HRDATA_S13_const_net_0;
wire   [1:0]  HRESP_S13_const_net_0;
wire   [31:0] HRDATA_S14_const_net_0;
wire   [1:0]  HRESP_S14_const_net_0;
wire   [31:0] HRDATA_S15_const_net_0;
wire   [1:0]  HRESP_S15_const_net_0;
wire   [31:0] HRDATA_S16_const_net_0;
wire   [1:0]  HRESP_S16_const_net_0;
wire   [31:0] PRDATAS1_const_net_0;
wire   [31:0] PRDATAS2_const_net_0;
wire   [31:0] PRDATAS3_const_net_0;
wire   [31:0] PRDATAS4_const_net_0;
wire   [31:0] PRDATAS5_const_net_0;
wire   [31:0] PRDATAS6_const_net_0;
wire   [31:0] PRDATAS7_const_net_0;
wire   [31:0] PRDATAS8_const_net_0;
wire   [31:0] PRDATAS9_const_net_0;
wire   [31:0] PRDATAS10_const_net_0;
wire   [31:0] PRDATAS11_const_net_0;
wire   [31:0] PRDATAS12_const_net_0;
wire   [31:0] PRDATAS13_const_net_0;
wire   [31:0] PRDATAS14_const_net_0;
wire   [31:0] PRDATAS15_const_net_0;
wire   [31:0] PRDATAS16_const_net_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign MSS_INT_F2M_const_net_0 = 15'h0000;
assign GND_net                 = 1'b0;
assign PADDR_const_net_0       = 6'h00;
assign PWDATA_const_net_0      = 8'h00;
assign VCC_net                 = 1'b1;
assign IADDR_const_net_0       = 32'h00000000;
assign HBURST_M0_const_net_0   = 3'h0;
assign HPROT_M0_const_net_0    = 4'h0;
assign HADDR_M1_const_net_0    = 32'h00000000;
assign HTRANS_M1_const_net_0   = 2'h0;
assign HSIZE_M1_const_net_0    = 3'h0;
assign HBURST_M1_const_net_0   = 3'h0;
assign HPROT_M1_const_net_0    = 4'h0;
assign HWDATA_M1_const_net_0   = 32'h00000000;
assign HRDATA_S0_const_net_0   = 32'h00000000;
assign HRESP_S0_const_net_0    = 2'h0;
assign HRDATA_S1_const_net_0   = 32'h00000000;
assign HRESP_S1_const_net_0    = 2'h0;
assign HRDATA_S2_const_net_0   = 32'h00000000;
assign HRESP_S2_const_net_0    = 2'h0;
assign HRDATA_S4_const_net_0   = 32'h00000000;
assign HRESP_S4_const_net_0    = 2'h0;
assign HRDATA_S5_const_net_0   = 32'h00000000;
assign HRESP_S5_const_net_0    = 2'h0;
assign HRDATA_S6_const_net_0   = 32'h00000000;
assign HRESP_S6_const_net_0    = 2'h0;
assign HRDATA_S7_const_net_0   = 32'h00000000;
assign HRESP_S7_const_net_0    = 2'h0;
assign HRDATA_S8_const_net_0   = 32'h00000000;
assign HRESP_S8_const_net_0    = 2'h0;
assign HRDATA_S9_const_net_0   = 32'h00000000;
assign HRESP_S9_const_net_0    = 2'h0;
assign HRDATA_S10_const_net_0  = 32'h00000000;
assign HRESP_S10_const_net_0   = 2'h0;
assign HRDATA_S11_const_net_0  = 32'h00000000;
assign HRESP_S11_const_net_0   = 2'h0;
assign HRDATA_S12_const_net_0  = 32'h00000000;
assign HRESP_S12_const_net_0   = 2'h0;
assign HRDATA_S13_const_net_0  = 32'h00000000;
assign HRESP_S13_const_net_0   = 2'h0;
assign HRDATA_S14_const_net_0  = 32'h00000000;
assign HRESP_S14_const_net_0   = 2'h0;
assign HRDATA_S15_const_net_0  = 32'h00000000;
assign HRESP_S15_const_net_0   = 2'h0;
assign HRDATA_S16_const_net_0  = 32'h00000000;
assign HRESP_S16_const_net_0   = 2'h0;
assign PRDATAS1_const_net_0    = 32'h00000000;
assign PRDATAS2_const_net_0    = 32'h00000000;
assign PRDATAS3_const_net_0    = 32'h00000000;
assign PRDATAS4_const_net_0    = 32'h00000000;
assign PRDATAS5_const_net_0    = 32'h00000000;
assign PRDATAS6_const_net_0    = 32'h00000000;
assign PRDATAS7_const_net_0    = 32'h00000000;
assign PRDATAS8_const_net_0    = 32'h00000000;
assign PRDATAS9_const_net_0    = 32'h00000000;
assign PRDATAS10_const_net_0   = 32'h00000000;
assign PRDATAS11_const_net_0   = 32'h00000000;
assign PRDATAS12_const_net_0   = 32'h00000000;
assign PRDATAS13_const_net_0   = 32'h00000000;
assign PRDATAS14_const_net_0   = 32'h00000000;
assign PRDATAS15_const_net_0   = 32'h00000000;
assign PRDATAS16_const_net_0   = 32'h00000000;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign SEL_net_1              = SEL_net_0;
assign SEL                    = SEL_net_1;
assign MCCC_MPLL_LOCK_net_1   = MCCC_MPLL_LOCK_net_0;
assign MCCC_MPLL_LOCK         = MCCC_MPLL_LOCK_net_1;
assign MMUART_0_TXD_M2F_net_1 = MMUART_0_TXD_M2F_net_0;
assign MMUART_0_TXD_M2F       = MMUART_0_TXD_M2F_net_1;
assign LOCK_net_1             = LOCK_net_0;
assign LOCK                   = LOCK_net_1;
assign rdata_user_net_1       = rdata_user_net_0;
assign rdata_user[7:0]        = rdata_user_net_1;
//--------------------------------------------------------------------
// Concatenation assignments
//--------------------------------------------------------------------
assign MSS_INT_F2M_net_0 = { 15'h0000 , RAM_with_wrapper_0_INT_OUT };
//--------------------------------------------------------------------
// Bus Interface Nets - Unequal Pin Widths
//--------------------------------------------------------------------
wire   [31:0] CoreAPB3_0_APBmslave0_PADDR;
wire   [7:0]  CoreAPB3_0_APBmslave0_PADDR_0_7to0;
wire   [7:0]  CoreAPB3_0_APBmslave0_PADDR_0;
assign CoreAPB3_0_APBmslave0_PADDR_0_7to0 = CoreAPB3_0_APBmslave0_PADDR[7:0];
assign CoreAPB3_0_APBmslave0_PADDR_0 = { CoreAPB3_0_APBmslave0_PADDR_0_7to0 };

wire   [31:8] CoreAPB3_0_APBmslave0_PRDATA_0_31to8;
wire   [7:0]  CoreAPB3_0_APBmslave0_PRDATA_0_7to0;
wire   [31:0] CoreAPB3_0_APBmslave0_PRDATA_0;
wire   [7:0]  CoreAPB3_0_APBmslave0_PRDATA;
assign CoreAPB3_0_APBmslave0_PRDATA_0_31to8 = 24'h0;
assign CoreAPB3_0_APBmslave0_PRDATA_0_7to0 = CoreAPB3_0_APBmslave0_PRDATA[7:0];
assign CoreAPB3_0_APBmslave0_PRDATA_0 = { CoreAPB3_0_APBmslave0_PRDATA_0_31to8, CoreAPB3_0_APBmslave0_PRDATA_0_7to0 };

wire   [31:0] CoreAPB3_0_APBmslave0_PWDATA;
wire   [7:0]  CoreAPB3_0_APBmslave0_PWDATA_0_7to0;
wire   [7:0]  CoreAPB3_0_APBmslave0_PWDATA_0;
assign CoreAPB3_0_APBmslave0_PWDATA_0_7to0 = CoreAPB3_0_APBmslave0_PWDATA[7:0];
assign CoreAPB3_0_APBmslave0_PWDATA_0 = { CoreAPB3_0_APBmslave0_PWDATA_0_7to0 };

wire   [0:0]  FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HRESP_0_0to0;
wire          FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HRESP_0;
wire   [1:0]  FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HRESP;
assign FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HRESP_0_0to0 = FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HRESP[0:0];
assign FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HRESP_0 = { FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HRESP_0_0to0 };

wire   [1:0]  FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HSIZE;
wire   [2:2]  FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HSIZE_0_2to2;
wire   [1:0]  FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HSIZE_0_1to0;
wire   [2:0]  FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HSIZE_0;
assign FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HSIZE_0_2to2 = 1'b0;
assign FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HSIZE_0_1to0 = FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HSIZE[1:0];
assign FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HSIZE_0 = { FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HSIZE_0_2to2, FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HSIZE_0_1to0 };

//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------Top_CCC_0_CCC   -   Actel:SgCore:CCC:2.0.005
Top_CCC_0_CCC CCC_0(
        // Inputs
        .RCOSC_25_50MHZ ( OSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC ),
        // Outputs
        .GL0            ( CCC_0_GL0 ),
        .LOCK           ( LOCK_net_0 ) 
        );

//--------CoreAHBLite   -   Actel:DirectCore:CoreAHBLite:4.0.9
CoreAHBLite #( 
        .FAMILY             ( 19 ),
        .M0_AHBSLOT0ENABLE  ( 0 ),
        .M0_AHBSLOT1ENABLE  ( 0 ),
        .M0_AHBSLOT2ENABLE  ( 0 ),
        .M0_AHBSLOT3ENABLE  ( 1 ),
        .M0_AHBSLOT4ENABLE  ( 0 ),
        .M0_AHBSLOT5ENABLE  ( 0 ),
        .M0_AHBSLOT6ENABLE  ( 0 ),
        .M0_AHBSLOT7ENABLE  ( 0 ),
        .M0_AHBSLOT8ENABLE  ( 0 ),
        .M0_AHBSLOT9ENABLE  ( 0 ),
        .M0_AHBSLOT10ENABLE ( 0 ),
        .M0_AHBSLOT11ENABLE ( 0 ),
        .M0_AHBSLOT12ENABLE ( 0 ),
        .M0_AHBSLOT13ENABLE ( 0 ),
        .M0_AHBSLOT14ENABLE ( 0 ),
        .M0_AHBSLOT15ENABLE ( 0 ),
        .M0_AHBSLOT16ENABLE ( 0 ),
        .M1_AHBSLOT0ENABLE  ( 0 ),
        .M1_AHBSLOT1ENABLE  ( 0 ),
        .M1_AHBSLOT2ENABLE  ( 0 ),
        .M1_AHBSLOT3ENABLE  ( 0 ),
        .M1_AHBSLOT4ENABLE  ( 0 ),
        .M1_AHBSLOT5ENABLE  ( 0 ),
        .M1_AHBSLOT6ENABLE  ( 0 ),
        .M1_AHBSLOT7ENABLE  ( 0 ),
        .M1_AHBSLOT8ENABLE  ( 0 ),
        .M1_AHBSLOT9ENABLE  ( 0 ),
        .M1_AHBSLOT10ENABLE ( 0 ),
        .M1_AHBSLOT11ENABLE ( 0 ),
        .M1_AHBSLOT12ENABLE ( 0 ),
        .M1_AHBSLOT13ENABLE ( 0 ),
        .M1_AHBSLOT14ENABLE ( 0 ),
        .M1_AHBSLOT15ENABLE ( 0 ),
        .M1_AHBSLOT16ENABLE ( 0 ),
        .MEMSPACE           ( 0 ),
        .SC_0               ( 0 ),
        .SC_1               ( 0 ),
        .SC_2               ( 0 ),
        .SC_3               ( 0 ),
        .SC_4               ( 0 ),
        .SC_5               ( 0 ),
        .SC_6               ( 0 ),
        .SC_7               ( 0 ),
        .SC_8               ( 0 ),
        .SC_9               ( 0 ),
        .SC_10              ( 0 ),
        .SC_11              ( 0 ),
        .SC_12              ( 0 ),
        .SC_13              ( 0 ),
        .SC_14              ( 0 ),
        .SC_15              ( 0 ) )
CoreAHBLite_0(
        // Inputs
        .HCLK          ( CCC_0_GL0 ),
        .HRESETN       ( FABRIC_SRAM_INIT_0_MSS_RESET_N_M2F ),
        .REMAP_M0      ( GND_net ), // tied to 1'b0 from definition
        .HMASTLOCK_M0  ( GND_net ), // tied to 1'b0 from definition
        .HWRITE_M0     ( FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HWRITE ),
        .HMASTLOCK_M1  ( GND_net ), // tied to 1'b0 from definition
        .HWRITE_M1     ( GND_net ), // tied to 1'b0 from definition
        .HREADYOUT_S0  ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S1  ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S2  ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S3  ( CoreAHBLite_0_AHBmslave3_HREADYOUT ),
        .HREADYOUT_S4  ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S5  ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S6  ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S7  ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S8  ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S9  ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S10 ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S11 ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S12 ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S13 ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S14 ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S15 ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S16 ( VCC_net ), // tied to 1'b1 from definition
        .HADDR_M0      ( FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HADDR ),
        .HSIZE_M0      ( FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HSIZE_0 ),
        .HTRANS_M0     ( FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HTRANS ),
        .HWDATA_M0     ( FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HWDATA ),
        .HBURST_M0     ( HBURST_M0_const_net_0 ), // tied to 3'h0 from definition
        .HPROT_M0      ( HPROT_M0_const_net_0 ), // tied to 4'h0 from definition
        .HADDR_M1      ( HADDR_M1_const_net_0 ), // tied to 32'h00000000 from definition
        .HSIZE_M1      ( HSIZE_M1_const_net_0 ), // tied to 3'h0 from definition
        .HTRANS_M1     ( HTRANS_M1_const_net_0 ), // tied to 2'h0 from definition
        .HWDATA_M1     ( HWDATA_M1_const_net_0 ), // tied to 32'h00000000 from definition
        .HBURST_M1     ( HBURST_M1_const_net_0 ), // tied to 3'h0 from definition
        .HPROT_M1      ( HPROT_M1_const_net_0 ), // tied to 4'h0 from definition
        .HRDATA_S0     ( HRDATA_S0_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S0      ( HRESP_S0_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S1     ( HRDATA_S1_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S1      ( HRESP_S1_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S2     ( HRDATA_S2_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S2      ( HRESP_S2_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S3     ( CoreAHBLite_0_AHBmslave3_HRDATA ),
        .HRESP_S3      ( CoreAHBLite_0_AHBmslave3_HRESP ),
        .HRDATA_S4     ( HRDATA_S4_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S4      ( HRESP_S4_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S5     ( HRDATA_S5_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S5      ( HRESP_S5_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S6     ( HRDATA_S6_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S6      ( HRESP_S6_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S7     ( HRDATA_S7_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S7      ( HRESP_S7_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S8     ( HRDATA_S8_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S8      ( HRESP_S8_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S9     ( HRDATA_S9_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S9      ( HRESP_S9_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S10    ( HRDATA_S10_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S10     ( HRESP_S10_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S11    ( HRDATA_S11_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S11     ( HRESP_S11_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S12    ( HRDATA_S12_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S12     ( HRESP_S12_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S13    ( HRDATA_S13_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S13     ( HRESP_S13_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S14    ( HRDATA_S14_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S14     ( HRESP_S14_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S15    ( HRDATA_S15_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S15     ( HRESP_S15_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S16    ( HRDATA_S16_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S16     ( HRESP_S16_const_net_0 ), // tied to 2'h0 from definition
        // Outputs
        .HREADY_M0     ( FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HREADY ),
        .HREADY_M1     (  ),
        .HSEL_S0       (  ),
        .HWRITE_S0     (  ),
        .HREADY_S0     (  ),
        .HMASTLOCK_S0  (  ),
        .HSEL_S1       (  ),
        .HWRITE_S1     (  ),
        .HREADY_S1     (  ),
        .HMASTLOCK_S1  (  ),
        .HSEL_S2       (  ),
        .HWRITE_S2     (  ),
        .HREADY_S2     (  ),
        .HMASTLOCK_S2  (  ),
        .HSEL_S3       ( CoreAHBLite_0_AHBmslave3_HSELx ),
        .HWRITE_S3     ( CoreAHBLite_0_AHBmslave3_HWRITE ),
        .HREADY_S3     ( CoreAHBLite_0_AHBmslave3_HREADY ),
        .HMASTLOCK_S3  ( CoreAHBLite_0_AHBmslave3_HMASTLOCK ),
        .HSEL_S4       (  ),
        .HWRITE_S4     (  ),
        .HREADY_S4     (  ),
        .HMASTLOCK_S4  (  ),
        .HSEL_S5       (  ),
        .HWRITE_S5     (  ),
        .HREADY_S5     (  ),
        .HMASTLOCK_S5  (  ),
        .HSEL_S6       (  ),
        .HWRITE_S6     (  ),
        .HREADY_S6     (  ),
        .HMASTLOCK_S6  (  ),
        .HSEL_S7       (  ),
        .HWRITE_S7     (  ),
        .HREADY_S7     (  ),
        .HMASTLOCK_S7  (  ),
        .HSEL_S8       (  ),
        .HWRITE_S8     (  ),
        .HREADY_S8     (  ),
        .HMASTLOCK_S8  (  ),
        .HSEL_S9       (  ),
        .HWRITE_S9     (  ),
        .HREADY_S9     (  ),
        .HMASTLOCK_S9  (  ),
        .HSEL_S10      (  ),
        .HWRITE_S10    (  ),
        .HREADY_S10    (  ),
        .HMASTLOCK_S10 (  ),
        .HSEL_S11      (  ),
        .HWRITE_S11    (  ),
        .HREADY_S11    (  ),
        .HMASTLOCK_S11 (  ),
        .HSEL_S12      (  ),
        .HWRITE_S12    (  ),
        .HREADY_S12    (  ),
        .HMASTLOCK_S12 (  ),
        .HSEL_S13      (  ),
        .HWRITE_S13    (  ),
        .HREADY_S13    (  ),
        .HMASTLOCK_S13 (  ),
        .HSEL_S14      (  ),
        .HWRITE_S14    (  ),
        .HREADY_S14    (  ),
        .HMASTLOCK_S14 (  ),
        .HSEL_S15      (  ),
        .HWRITE_S15    (  ),
        .HREADY_S15    (  ),
        .HMASTLOCK_S15 (  ),
        .HSEL_S16      (  ),
        .HWRITE_S16    (  ),
        .HREADY_S16    (  ),
        .HMASTLOCK_S16 (  ),
        .HRESP_M0      ( FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HRESP ),
        .HRDATA_M0     ( FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HRDATA ),
        .HRESP_M1      (  ),
        .HRDATA_M1     (  ),
        .HADDR_S0      (  ),
        .HSIZE_S0      (  ),
        .HTRANS_S0     (  ),
        .HWDATA_S0     (  ),
        .HBURST_S0     (  ),
        .HPROT_S0      (  ),
        .HADDR_S1      (  ),
        .HSIZE_S1      (  ),
        .HTRANS_S1     (  ),
        .HWDATA_S1     (  ),
        .HBURST_S1     (  ),
        .HPROT_S1      (  ),
        .HADDR_S2      (  ),
        .HSIZE_S2      (  ),
        .HTRANS_S2     (  ),
        .HWDATA_S2     (  ),
        .HBURST_S2     (  ),
        .HPROT_S2      (  ),
        .HADDR_S3      ( CoreAHBLite_0_AHBmslave3_HADDR ),
        .HSIZE_S3      ( CoreAHBLite_0_AHBmslave3_HSIZE ),
        .HTRANS_S3     ( CoreAHBLite_0_AHBmslave3_HTRANS ),
        .HWDATA_S3     ( CoreAHBLite_0_AHBmslave3_HWDATA ),
        .HBURST_S3     ( CoreAHBLite_0_AHBmslave3_HBURST ),
        .HPROT_S3      ( CoreAHBLite_0_AHBmslave3_HPROT ),
        .HADDR_S4      (  ),
        .HSIZE_S4      (  ),
        .HTRANS_S4     (  ),
        .HWDATA_S4     (  ),
        .HBURST_S4     (  ),
        .HPROT_S4      (  ),
        .HADDR_S5      (  ),
        .HSIZE_S5      (  ),
        .HTRANS_S5     (  ),
        .HWDATA_S5     (  ),
        .HBURST_S5     (  ),
        .HPROT_S5      (  ),
        .HADDR_S6      (  ),
        .HSIZE_S6      (  ),
        .HTRANS_S6     (  ),
        .HWDATA_S6     (  ),
        .HBURST_S6     (  ),
        .HPROT_S6      (  ),
        .HADDR_S7      (  ),
        .HSIZE_S7      (  ),
        .HTRANS_S7     (  ),
        .HWDATA_S7     (  ),
        .HBURST_S7     (  ),
        .HPROT_S7      (  ),
        .HADDR_S8      (  ),
        .HSIZE_S8      (  ),
        .HTRANS_S8     (  ),
        .HWDATA_S8     (  ),
        .HBURST_S8     (  ),
        .HPROT_S8      (  ),
        .HADDR_S9      (  ),
        .HSIZE_S9      (  ),
        .HTRANS_S9     (  ),
        .HWDATA_S9     (  ),
        .HBURST_S9     (  ),
        .HPROT_S9      (  ),
        .HADDR_S10     (  ),
        .HSIZE_S10     (  ),
        .HTRANS_S10    (  ),
        .HWDATA_S10    (  ),
        .HBURST_S10    (  ),
        .HPROT_S10     (  ),
        .HADDR_S11     (  ),
        .HSIZE_S11     (  ),
        .HTRANS_S11    (  ),
        .HWDATA_S11    (  ),
        .HBURST_S11    (  ),
        .HPROT_S11     (  ),
        .HADDR_S12     (  ),
        .HSIZE_S12     (  ),
        .HTRANS_S12    (  ),
        .HWDATA_S12    (  ),
        .HBURST_S12    (  ),
        .HPROT_S12     (  ),
        .HADDR_S13     (  ),
        .HSIZE_S13     (  ),
        .HTRANS_S13    (  ),
        .HWDATA_S13    (  ),
        .HBURST_S13    (  ),
        .HPROT_S13     (  ),
        .HADDR_S14     (  ),
        .HSIZE_S14     (  ),
        .HTRANS_S14    (  ),
        .HWDATA_S14    (  ),
        .HBURST_S14    (  ),
        .HPROT_S14     (  ),
        .HADDR_S15     (  ),
        .HSIZE_S15     (  ),
        .HTRANS_S15    (  ),
        .HWDATA_S15    (  ),
        .HBURST_S15    (  ),
        .HPROT_S15     (  ),
        .HADDR_S16     (  ),
        .HSIZE_S16     (  ),
        .HTRANS_S16    (  ),
        .HWDATA_S16    (  ),
        .HBURST_S16    (  ),
        .HPROT_S16     (  ) 
        );

//--------COREAHBTOAPB3   -   Actel:DirectCore:COREAHBTOAPB3:3.0.4
COREAHBTOAPB3 #( 
        .FAMILY ( 19 ) )
COREAHBTOAPB3_0(
        // Inputs
        .HCLK      ( CCC_0_GL0 ),
        .HRESETN   ( FABRIC_SRAM_INIT_0_MSS_RESET_N_M2F ),
        .HWRITE    ( CoreAHBLite_0_AHBmslave3_HWRITE ),
        .HSEL      ( CoreAHBLite_0_AHBmslave3_HSELx ),
        .HREADY    ( CoreAHBLite_0_AHBmslave3_HREADY ),
        .PREADY    ( COREAHBTOAPB3_0_APBmaster_PREADY ),
        .PSLVERR   ( COREAHBTOAPB3_0_APBmaster_PSLVERR ),
        .HADDR     ( CoreAHBLite_0_AHBmslave3_HADDR ),
        .HTRANS    ( CoreAHBLite_0_AHBmslave3_HTRANS ),
        .HWDATA    ( CoreAHBLite_0_AHBmslave3_HWDATA ),
        .PRDATA    ( COREAHBTOAPB3_0_APBmaster_PRDATA ),
        // Outputs
        .HREADYOUT ( CoreAHBLite_0_AHBmslave3_HREADYOUT ),
        .PENABLE   ( COREAHBTOAPB3_0_APBmaster_PENABLE ),
        .PWRITE    ( COREAHBTOAPB3_0_APBmaster_PWRITE ),
        .PSEL      ( COREAHBTOAPB3_0_APBmaster_PSELx ),
        .HRDATA    ( CoreAHBLite_0_AHBmslave3_HRDATA ),
        .HRESP     ( CoreAHBLite_0_AHBmslave3_HRESP ),
        .PWDATA    ( COREAHBTOAPB3_0_APBmaster_PWDATA ),
        .PADDR     ( COREAHBTOAPB3_0_APBmaster_PADDR ) 
        );

//--------CoreAPB3   -   Actel:DirectCore:CoreAPB3:4.0.5
CoreAPB3 #( 
        .APB_DWIDTH      ( 32 ),
        .APBSLOT0ENABLE  ( 1 ),
        .APBSLOT1ENABLE  ( 0 ),
        .APBSLOT2ENABLE  ( 0 ),
        .APBSLOT3ENABLE  ( 0 ),
        .APBSLOT4ENABLE  ( 0 ),
        .APBSLOT5ENABLE  ( 0 ),
        .APBSLOT6ENABLE  ( 0 ),
        .APBSLOT7ENABLE  ( 0 ),
        .APBSLOT8ENABLE  ( 0 ),
        .APBSLOT9ENABLE  ( 0 ),
        .APBSLOT10ENABLE ( 0 ),
        .APBSLOT11ENABLE ( 0 ),
        .APBSLOT12ENABLE ( 0 ),
        .APBSLOT13ENABLE ( 0 ),
        .APBSLOT14ENABLE ( 0 ),
        .APBSLOT15ENABLE ( 0 ),
        .IADDR_OPTION    ( 0 ),
        .MADDR_BITS      ( 28 ),
        .SC_0            ( 0 ),
        .SC_1            ( 0 ),
        .SC_2            ( 0 ),
        .SC_3            ( 0 ),
        .SC_4            ( 0 ),
        .SC_5            ( 0 ),
        .SC_6            ( 0 ),
        .SC_7            ( 0 ),
        .SC_8            ( 0 ),
        .SC_9            ( 0 ),
        .SC_10           ( 0 ),
        .SC_11           ( 0 ),
        .SC_12           ( 0 ),
        .SC_13           ( 0 ),
        .SC_14           ( 0 ),
        .SC_15           ( 0 ),
        .UPR_NIBBLE_POSN ( 6 ) )
CoreAPB3_0(
        // Inputs
        .PRESETN    ( GND_net ), // tied to 1'b0 from definition
        .PCLK       ( GND_net ), // tied to 1'b0 from definition
        .PWRITE     ( COREAHBTOAPB3_0_APBmaster_PWRITE ),
        .PENABLE    ( COREAHBTOAPB3_0_APBmaster_PENABLE ),
        .PSEL       ( COREAHBTOAPB3_0_APBmaster_PSELx ),
        .PREADYS0   ( CoreAPB3_0_APBmslave0_PREADY ),
        .PSLVERRS0  ( CoreAPB3_0_APBmslave0_PSLVERR ),
        .PREADYS1   ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS1  ( GND_net ), // tied to 1'b0 from definition
        .PREADYS2   ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS2  ( GND_net ), // tied to 1'b0 from definition
        .PREADYS3   ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS3  ( GND_net ), // tied to 1'b0 from definition
        .PREADYS4   ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS4  ( GND_net ), // tied to 1'b0 from definition
        .PREADYS5   ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS5  ( GND_net ), // tied to 1'b0 from definition
        .PREADYS6   ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS6  ( GND_net ), // tied to 1'b0 from definition
        .PREADYS7   ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS7  ( GND_net ), // tied to 1'b0 from definition
        .PREADYS8   ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS8  ( GND_net ), // tied to 1'b0 from definition
        .PREADYS9   ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS9  ( GND_net ), // tied to 1'b0 from definition
        .PREADYS10  ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS10 ( GND_net ), // tied to 1'b0 from definition
        .PREADYS11  ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS11 ( GND_net ), // tied to 1'b0 from definition
        .PREADYS12  ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS12 ( GND_net ), // tied to 1'b0 from definition
        .PREADYS13  ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS13 ( GND_net ), // tied to 1'b0 from definition
        .PREADYS14  ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS14 ( GND_net ), // tied to 1'b0 from definition
        .PREADYS15  ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS15 ( GND_net ), // tied to 1'b0 from definition
        .PREADYS16  ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS16 ( GND_net ), // tied to 1'b0 from definition
        .PADDR      ( COREAHBTOAPB3_0_APBmaster_PADDR ),
        .PWDATA     ( COREAHBTOAPB3_0_APBmaster_PWDATA ),
        .PRDATAS0   ( CoreAPB3_0_APBmslave0_PRDATA_0 ),
        .PRDATAS1   ( PRDATAS1_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS2   ( PRDATAS2_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS3   ( PRDATAS3_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS4   ( PRDATAS4_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS5   ( PRDATAS5_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS6   ( PRDATAS6_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS7   ( PRDATAS7_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS8   ( PRDATAS8_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS9   ( PRDATAS9_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS10  ( PRDATAS10_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS11  ( PRDATAS11_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS12  ( PRDATAS12_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS13  ( PRDATAS13_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS14  ( PRDATAS14_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS15  ( PRDATAS15_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS16  ( PRDATAS16_const_net_0 ), // tied to 32'h00000000 from definition
        .IADDR      ( IADDR_const_net_0 ), // tied to 32'h00000000 from definition
        // Outputs
        .PREADY     ( COREAHBTOAPB3_0_APBmaster_PREADY ),
        .PSLVERR    ( COREAHBTOAPB3_0_APBmaster_PSLVERR ),
        .PWRITES    ( CoreAPB3_0_APBmslave0_PWRITE ),
        .PENABLES   ( CoreAPB3_0_APBmslave0_PENABLE ),
        .PSELS0     ( CoreAPB3_0_APBmslave0_PSELx ),
        .PSELS1     (  ),
        .PSELS2     (  ),
        .PSELS3     (  ),
        .PSELS4     (  ),
        .PSELS5     (  ),
        .PSELS6     (  ),
        .PSELS7     (  ),
        .PSELS8     (  ),
        .PSELS9     (  ),
        .PSELS10    (  ),
        .PSELS11    (  ),
        .PSELS12    (  ),
        .PSELS13    (  ),
        .PSELS14    (  ),
        .PSELS15    (  ),
        .PSELS16    (  ),
        .PRDATA     ( COREAHBTOAPB3_0_APBmaster_PRDATA ),
        .PADDRS     ( CoreAPB3_0_APBmslave0_PADDR ),
        .PWDATAS    ( CoreAPB3_0_APBmslave0_PWDATA ) 
        );

//--------FABRIC_SRAM_INIT
FABRIC_SRAM_INIT FABRIC_SRAM_INIT_0(
        // Inputs
        .MCCC_CLK_BASE_PLL_LOCK ( LOCK_net_0 ),
        .MCCC_CLK_BASE          ( CCC_0_GL0 ),
        .MMUART_0_RXD_F2M       ( MMUART_0_RXD_F2M ),
        .FIC_0_AHB_M_HREADY     ( FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HREADY ),
        .FIC_0_AHB_M_HRESP      ( FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HRESP_0 ),
        .MSS_RESET_N_F2M        ( SYSRESET_0_POWER_ON_RESET_N ),
        .MSS_INT_F2M            ( MSS_INT_F2M_net_0 ),
        .FIC_0_AHB_M_HRDATA     ( FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HRDATA ),
        // Outputs
        .MMUART_0_TXD_M2F       ( MMUART_0_TXD_M2F_net_0 ),
        .MSS_RESET_N_M2F        ( FABRIC_SRAM_INIT_0_MSS_RESET_N_M2F ),
        .FIC_0_AHB_M_HWRITE     ( FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HWRITE ),
        .MCCC_MPLL_LOCK         ( MCCC_MPLL_LOCK_net_0 ),
        .FIC_0_AHB_M_HADDR      ( FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HADDR ),
        .FIC_0_AHB_M_HTRANS     ( FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HTRANS ),
        .FIC_0_AHB_M_HSIZE      ( FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HSIZE ),
        .FIC_0_AHB_M_HWDATA     ( FABRIC_SRAM_INIT_0_FIC_0_AHB_MASTER_HWDATA ) 
        );

//--------Top_OSC_0_OSC   -   Actel:SgCore:OSC:0.0.502
Top_OSC_0_OSC OSC_0(
        // Inputs
        .XTL                ( GND_net ), // tied to 1'b0 from definition
        // Outputs
        .RCOSC_25_50MHZ_MSS (  ),
        .RCOSC_25_50MHZ_CCC ( OSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC ),
        .RCOSC_25_50MHZ_O2F (  ),
        .RCOSC_1MHZ_MSS     (  ),
        .RCOSC_1MHZ_CCC     (  ),
        .RCOSC_1MHZ_O2F     (  ),
        .XTLOSC_MSS         (  ),
        .XTLOSC_CCC         (  ),
        .XTLOSC_O2F         (  ) 
        );

//--------RAM_with_wrapper
RAM_with_wrapper RAM_with_wrapper_0(
        // Inputs
        .wr_enable_user ( wr_enable_user ),
        .rclk_user      ( rclk_user ),
        .rd_enable_user ( rd_enable_user ),
        .wclk_user      ( wclk_user ),
        .PRESETN        ( FABRIC_SRAM_INIT_0_MSS_RESET_N_M2F ),
        .PCLK           ( CCC_0_GL0 ),
        .PENABLE        ( CoreAPB3_0_APBmslave0_PENABLE ),
        .PWRITE         ( CoreAPB3_0_APBmslave0_PWRITE ),
        .PSEL           ( CoreAPB3_0_APBmslave0_PSELx ),
        .raddr_user     ( raddr_user ),
        .wdata_user     ( wdata_user ),
        .waddr_user     ( waddr_user ),
        .PADDR          ( CoreAPB3_0_APBmslave0_PADDR_0 ),
        .PWDATA         ( CoreAPB3_0_APBmslave0_PWDATA_0 ),
        // Outputs
        .INT_OUT        ( RAM_with_wrapper_0_INT_OUT ),
        .SEL            ( SEL_net_0 ),
        .PREADY         ( CoreAPB3_0_APBmslave0_PREADY ),
        .PSLVERR        ( CoreAPB3_0_APBmslave0_PSLVERR ),
        .PRDATA         ( CoreAPB3_0_APBmslave0_PRDATA ),
        .rdata_user     ( rdata_user_net_0 ) 
        );

//--------SYSRESET
SYSRESET SYSRESET_0(
        // Inputs
        .DEVRST_N         ( DEVRST_N ),
        // Outputs
        .POWER_ON_RESET_N ( SYSRESET_0_POWER_ON_RESET_N ) 
        );


endmodule
