library verilog;
use verilog.vl_types.all;
entity my_cnt8 is
    port(
        Clock           : in     vl_logic;
        Q               : out    vl_logic_vector(7 downto 0);
        Aclr            : in     vl_logic;
        Enable          : in     vl_logic
    );
end my_cnt8;
