//for generating the address to access the SRAM from simple user interface in simulation
 
module my_cnt6 (Clock, Q, Aclr, Enable);

  input Clock;
  output [5:0] Q;
  input Aclr;
  input Enable;

  reg [5:0] Qaux;

  always @(posedge Clock or negedge Aclr)
  begin

    if (!Aclr)
      Qaux <= 6'b000000;
    else if (Enable)
      Qaux <= Qaux + 1;

  end

  assign Q = Qaux;

endmodule