library verilog;
use verilog.vl_types.all;
entity Top is
    port(
        DEVRST_N        : in     vl_logic;
        MMUART_0_RXD_F2M: in     vl_logic;
        raddr_user      : in     vl_logic_vector(5 downto 0);
        rclk_user       : in     vl_logic;
        rd_enable_user  : in     vl_logic;
        waddr_user      : in     vl_logic_vector(5 downto 0);
        wclk_user       : in     vl_logic;
        wdata_user      : in     vl_logic_vector(7 downto 0);
        wr_enable_user  : in     vl_logic;
        LOCK            : out    vl_logic;
        MCCC_MPLL_LOCK  : out    vl_logic;
        MMUART_0_TXD_M2F: out    vl_logic;
        SEL             : out    vl_logic;
        rdata_user      : out    vl_logic_vector(7 downto 0)
    );
end Top;
