// Actel Corporation Proprietary and Confidential
// Copyright 2010 Actel Corporation.  All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
// Revision Information:
// 10Feb10              Production Release Version 3.1
// SVN Revision Information:
// SVN $Revision: 11955 $
// SVN $Date: 2010-01-30 23:35:13 +0000 (Sat, 30 Jan 2010) $
`timescale 1ns/1ps
module
CAHBLTO1lI
(
input
HCLK,
input
HRESETN,
input
CAHBLTI1lI,
input
CAHBLTIl1,
output
reg
CAHBLTl1lI,
output
reg
[
31
:
0
]
CAHBLTlO1,
output
reg
[
2
:
0
]
CAHBLTII1,
output
wire
CAHBLTlI1,
output
reg
CAHBLTOl1,
output
reg
[
31
:
0
]
CAHBLTOO0I,
output
wire
CAHBLTIO0I,
output
reg
CAHBLTOI1,
input
[
1
:
0
]
CAHBLTI1l,
input
[
1
:
0
]
CAHBLTlO0I,
input
[
1
:
0
]
CAHBLTOI0I,
output
reg
[
1
:
0
]
CAHBLTII0I,
output
reg
[
1
:
0
]
CAHBLTlI0I,
output
reg
[
1
:
0
]
CAHBLTOl0I,
input
[
31
:
0
]
CAHBLTIl0I,
input
CAHBLTOO0,
input
[
2
:
0
]
CAHBLTll0I,
input
CAHBLTO00I,
input
CAHBLTI00I,
input
[
31
:
0
]
CAHBLTl00I,
input
CAHBLTIO0,
input
[
2
:
0
]
CAHBLTO10I,
input
CAHBLTI10I,
input
CAHBLTl10I,
input
[
31
:
0
]
HWDATA_M0,
input
[
31
:
0
]
HWDATA_M1
)
;
localparam
CAHBLTOO1I
=
1
'b
0
;
localparam
CAHBLTI10
=
2
'b
00
;
wire
[
1
:
0
]
CAHBLTIO1I
;
reg
[
1
:
0
]
CAHBLTlO1I
;
reg
CAHBLTOI1I
;
wire
CAHBLTII1I
;
reg
CAHBLTlI1I
;
always
@
(
posedge
HCLK
or
negedge
HRESETN
)
begin
if
(
!
HRESETN
)
CAHBLTlO1I
<=
CAHBLTI10
;
else
if
(
CAHBLTIO0I
)
CAHBLTlO1I
<=
CAHBLTIO1I
;
end
CAHBLTO1l
CAHBLTOl1I
(
.HCLK
(
HCLK
)
,
.HRESETN
(
HRESETN
)
,
.CAHBLTI1l
(
CAHBLTI1l
)
,
.CAHBLTl1l
(
CAHBLTIO0I
)
,
.CAHBLTOO0
(
CAHBLTOO0
)
,
.CAHBLTIO0
(
CAHBLTIO0
)
,
.CAHBLTlO0
(
CAHBLTIO1I
)
)
;
always
@(*)
begin
casez
(
CAHBLTIO1I
)
2
'b
?1
:
begin
CAHBLTl1lI
=
1
'b
1
;
CAHBLTlI1I
=
CAHBLTO00I
;
CAHBLTII1
=
CAHBLTll0I
;
CAHBLTOl1
=
CAHBLTI00I
;
CAHBLTlO1
=
CAHBLTIl0I
;
CAHBLTOI1
=
CAHBLTOO0
;
CAHBLTOI1I
=
CAHBLTOI0I
[
0
]
;
end
2
'b
1?
:
begin
CAHBLTl1lI
=
1
'b
1
;
CAHBLTlI1I
=
CAHBLTI10I
;
CAHBLTII1
=
CAHBLTO10I
;
CAHBLTOl1
=
CAHBLTl10I
;
CAHBLTlO1
=
CAHBLTl00I
;
CAHBLTOI1
=
CAHBLTIO0
;
CAHBLTOI1I
=
CAHBLTOI0I
[
1
]
;
end
default
:
begin
CAHBLTl1lI
=
1
'b
0
;
CAHBLTlI1I
=
CAHBLTOO1I
;
CAHBLTII1
=
2
'b
00
;
CAHBLTOl1
=
1
'b
0
;
CAHBLTlO1
=
32
'h
0
;
CAHBLTOI1
=
1
'b
0
;
CAHBLTOI1I
=
1
'b
1
;
end
endcase
end
assign
CAHBLTII1I
=
|
(
CAHBLTIO1I
&
CAHBLTlO0I
)
;
assign
CAHBLTlI1
=
CAHBLTlI1I
&&
(
CAHBLTOI1I
||
CAHBLTII1I
)
;
assign
CAHBLTIO0I
=
CAHBLTI1lI
;
always
@(*)
begin
casez
(
CAHBLTlO1I
)
2
'b
?1
:
begin
CAHBLTOO0I
=
HWDATA_M0
;
end
2
'b
1?
:
begin
CAHBLTOO0I
=
HWDATA_M1
;
end
default
:
begin
CAHBLTOO0I
=
32
'h
0
;
end
endcase
end
always
@(*)
begin
CAHBLTOl0I
=
2
'b
00
;
casez
(
CAHBLTlO1I
)
2
'b
?1
:
begin
CAHBLTOl0I
[
0
]
=
CAHBLTIl1
;
end
2
'b
1?
:
begin
CAHBLTOl0I
[
1
]
=
CAHBLTIl1
;
end
default
:
begin
CAHBLTOl0I
=
2
'b
00
;
end
endcase
end
always
@(*)
begin
if
(
CAHBLTI1l
[
0
]
&&
!
CAHBLTIO1I
[
0
]
)
CAHBLTII0I
[
0
]
=
1
'b
0
;
else
if
(
CAHBLTI1l
[
0
]
&&
CAHBLTIO1I
[
0
]
)
CAHBLTII0I
[
0
]
=
CAHBLTI1lI
;
else
CAHBLTII0I
[
0
]
=
1
'b
1
;
end
always
@(*)
begin
if
(
CAHBLTI1l
[
1
]
&&
!
CAHBLTIO1I
[
1
]
)
CAHBLTII0I
[
1
]
=
1
'b
0
;
else
if
(
CAHBLTI1l
[
1
]
&&
CAHBLTIO1I
[
1
]
)
CAHBLTII0I
[
1
]
=
CAHBLTI1lI
;
else
CAHBLTII0I
[
1
]
=
1
'b
1
;
end
always
@(*)
begin
if
(
CAHBLTlO0I
[
0
]
&&
!
CAHBLTlO1I
[
0
]
)
CAHBLTlI0I
[
0
]
=
1
'b
0
;
else
if
(
CAHBLTlO0I
[
0
]
&&
CAHBLTlO1I
[
0
]
)
CAHBLTlI0I
[
0
]
=
CAHBLTI1lI
;
else
CAHBLTlI0I
[
0
]
=
1
'b
1
;
end
always
@(*)
begin
if
(
CAHBLTlO0I
[
1
]
&&
!
CAHBLTlO1I
[
1
]
)
CAHBLTlI0I
[
1
]
=
1
'b
0
;
else
if
(
CAHBLTlO0I
[
1
]
&&
CAHBLTlO1I
[
1
]
)
CAHBLTlI0I
[
1
]
=
CAHBLTI1lI
;
else
CAHBLTlI0I
[
1
]
=
1
'b
1
;
end
endmodule
