library verilog;
use verilog.vl_types.all;
entity CAPB3l is
    port(
        CAPB3OI         : in     vl_logic_vector(16 downto 0);
        PRDATAS0        : in     vl_logic_vector(31 downto 0);
        PRDATAS1        : in     vl_logic_vector(31 downto 0);
        PRDATAS2        : in     vl_logic_vector(31 downto 0);
        PRDATAS3        : in     vl_logic_vector(31 downto 0);
        PRDATAS4        : in     vl_logic_vector(31 downto 0);
        PRDATAS5        : in     vl_logic_vector(31 downto 0);
        PRDATAS6        : in     vl_logic_vector(31 downto 0);
        PRDATAS7        : in     vl_logic_vector(31 downto 0);
        PRDATAS8        : in     vl_logic_vector(31 downto 0);
        PRDATAS9        : in     vl_logic_vector(31 downto 0);
        PRDATAS10       : in     vl_logic_vector(31 downto 0);
        PRDATAS11       : in     vl_logic_vector(31 downto 0);
        PRDATAS12       : in     vl_logic_vector(31 downto 0);
        PRDATAS13       : in     vl_logic_vector(31 downto 0);
        PRDATAS14       : in     vl_logic_vector(31 downto 0);
        PRDATAS15       : in     vl_logic_vector(31 downto 0);
        PRDATAS16       : in     vl_logic_vector(31 downto 0);
        CAPB3II         : in     vl_logic_vector(16 downto 0);
        CAPB3lI         : in     vl_logic_vector(16 downto 0);
        PREADY          : out    vl_logic;
        PSLVERR         : out    vl_logic;
        PRDATA          : out    vl_logic_vector(31 downto 0)
    );
end CAPB3l;
