library verilog;
use verilog.vl_types.all;
entity RESET_GEN is
    generic(
        DELAY           : integer := 1000;
        LOGIC_LEVEL     : integer := 0
    );
    port(
        RESET           : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of DELAY : constant is 1;
    attribute mti_svvh_generic_type of LOGIC_LEVEL : constant is 1;
end RESET_GEN;
