library verilog;
use verilog.vl_types.all;
entity RAM_with_wrapper_SRAM_64x8_0_TPSRAM is
    port(
        WD              : in     vl_logic_vector(7 downto 0);
        RD              : out    vl_logic_vector(7 downto 0);
        WADDR           : in     vl_logic_vector(5 downto 0);
        RADDR           : in     vl_logic_vector(5 downto 0);
        WEN             : in     vl_logic;
        REN             : in     vl_logic;
        ARST_N          : in     vl_logic;
        WCLK            : in     vl_logic;
        RCLK            : in     vl_logic
    );
end RAM_with_wrapper_SRAM_64x8_0_TPSRAM;
