library verilog;
use verilog.vl_types.all;
entity Top_OSC_0_OSC is
    port(
        XTL             : in     vl_logic;
        RCOSC_25_50MHZ_MSS: out    vl_logic;
        RCOSC_25_50MHZ_CCC: out    vl_logic;
        RCOSC_25_50MHZ_O2F: out    vl_logic;
        RCOSC_1MHZ_MSS  : out    vl_logic;
        RCOSC_1MHZ_CCC  : out    vl_logic;
        RCOSC_1MHZ_O2F  : out    vl_logic;
        XTLOSC_MSS      : out    vl_logic;
        XTLOSC_CCC      : out    vl_logic;
        XTLOSC_O2F      : out    vl_logic
    );
end Top_OSC_0_OSC;
