library verilog;
use verilog.vl_types.all;
entity FABRIC_SRAM_INIT_MSS is
    port(
        FIC_0_AHB_M_HRDATA: in     vl_logic_vector(31 downto 0);
        FIC_0_AHB_M_HREADY: in     vl_logic;
        FIC_0_AHB_M_HRESP: in     vl_logic;
        MCCC_CLK_BASE   : in     vl_logic;
        MCCC_CLK_BASE_PLL_LOCK: in     vl_logic;
        MMUART_0_RXD_F2M: in     vl_logic;
        MSS_INT_F2M     : in     vl_logic_vector(15 downto 0);
        MSS_RESET_N_F2M : in     vl_logic;
        FIC_0_AHB_M_HADDR: out    vl_logic_vector(31 downto 0);
        FIC_0_AHB_M_HSIZE: out    vl_logic_vector(1 downto 0);
        FIC_0_AHB_M_HTRANS: out    vl_logic_vector(1 downto 0);
        FIC_0_AHB_M_HWDATA: out    vl_logic_vector(31 downto 0);
        FIC_0_AHB_M_HWRITE: out    vl_logic;
        MCCC_MPLL_LOCK  : out    vl_logic;
        MMUART_0_TXD_M2F: out    vl_logic;
        MSS_RESET_N_M2F : out    vl_logic
    );
end FABRIC_SRAM_INIT_MSS;
