library verilog;
use verilog.vl_types.all;
entity CAHBLTIO1 is
    generic(
        MEMSPACE        : vl_logic_vector(0 downto 0) := (others => Hi0);
        CAHBLTI         : vl_logic_vector(15 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
        CAHBLTl         : vl_logic_vector(16 downto 0) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1)
    );
    port(
        HCLK            : in     vl_logic;
        HRESETN         : in     vl_logic;
        CAHBLTlO1       : in     vl_logic_vector(31 downto 0);
        CAHBLTOI1       : in     vl_logic;
        CAHBLTII1       : in     vl_logic_vector(2 downto 0);
        CAHBLTlI1       : in     vl_logic;
        CAHBLTOl1       : in     vl_logic;
        CAHBLTIl1       : out    vl_logic;
        CAHBLTll1       : out    vl_logic_vector(31 downto 0);
        CAHBLTO01       : out    vl_logic;
        CAHBLTII        : in     vl_logic;
        CAHBLTI01       : in     vl_logic_vector(16 downto 0);
        CAHBLTl01       : in     vl_logic_vector(16 downto 0);
        CAHBLTO11       : in     vl_logic_vector(16 downto 0);
        CAHBLTI11       : out    vl_logic_vector(31 downto 0);
        CAHBLTl11       : out    vl_logic;
        CAHBLTOOOI      : out    vl_logic_vector(2 downto 0);
        CAHBLTIOOI      : out    vl_logic;
        CAHBLTlOOI      : out    vl_logic;
        CAHBLTOIOI      : out    vl_logic_vector(16 downto 0);
        CAHBLTIIOI      : out    vl_logic_vector(16 downto 0);
        CAHBLTlIOI      : out    vl_logic;
        HRDATA_S0       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S0    : in     vl_logic;
        HRDATA_S1       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S1    : in     vl_logic;
        HRDATA_S2       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S2    : in     vl_logic;
        HRDATA_S3       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S3    : in     vl_logic;
        HRDATA_S4       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S4    : in     vl_logic;
        HRDATA_S5       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S5    : in     vl_logic;
        HRDATA_S6       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S6    : in     vl_logic;
        HRDATA_S7       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S7    : in     vl_logic;
        HRDATA_S8       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S8    : in     vl_logic;
        HRDATA_S9       : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S9    : in     vl_logic;
        HRDATA_S10      : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S10   : in     vl_logic;
        HRDATA_S11      : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S11   : in     vl_logic;
        HRDATA_S12      : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S12   : in     vl_logic;
        HRDATA_S13      : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S13   : in     vl_logic;
        HRDATA_S14      : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S14   : in     vl_logic;
        HRDATA_S15      : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S15   : in     vl_logic;
        HRDATA_S16      : in     vl_logic_vector(31 downto 0);
        HREADYOUT_S16   : in     vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of MEMSPACE : constant is 2;
    attribute mti_svvh_generic_type of CAHBLTI : constant is 2;
    attribute mti_svvh_generic_type of CAHBLTl : constant is 2;
end CAHBLTIO1;
