library verilog;
use verilog.vl_types.all;
entity my_testbench is
    port(
        MMUART_0_RXD_F2M: in     vl_logic;
        LOCK            : out    vl_logic;
        MCCC_MPLL_LOCK  : out    vl_logic;
        MMUART_0_TXD_M2F: out    vl_logic;
        rdata_user      : out    vl_logic_vector(7 downto 0)
    );
end my_testbench;
