library verilog;
use verilog.vl_types.all;
entity CAHBLTO1l is
    port(
        HCLK            : in     vl_logic;
        HRESETN         : in     vl_logic;
        CAHBLTI1l       : in     vl_logic_vector(1 downto 0);
        CAHBLTl1l       : in     vl_logic;
        CAHBLTOO0       : in     vl_logic;
        CAHBLTIO0       : in     vl_logic;
        CAHBLTlO0       : out    vl_logic_vector(1 downto 0)
    );
end CAHBLTO1l;
