#Build: Synplify Pro D-2009.12A, Build 040R, Jan 20 2010
#install: C:\Actel\Libero_v9.0\Synopsys\synplify_D200912A
#OS: Windows XP 5.1
#Hostname: WXP-CAE-01

#Implementation: synthesis

#Fri Aug 20 18:00:22 2010

$ Start of Compile
#Fri Aug 20 18:00:22 2010

Synopsys VHDL Compiler, version comp475rc, Build 060R, built Jan 15 2010
Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved

@N:CD720 : std.vhd(123) | Setting time resolution to ns
Top entity isn't set yet!
VHDL syntax check successful!
File D:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\bin\c_vhdl.exe changed - recompiling
File D:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\lib\vhd\location.map changed - recompiling
File D:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\lib\vhd\std.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\MuxP2B.vhd changed - recompiling
File D:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\lib\vhd\std1164.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\work\PHY_MDIO\PHY_MDIO.vhd changed - recompiling
File D:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\lib\proasic\fusion.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreAHB2APB\1.1.101\rtl\vhdl\o\CoreAHB2APB.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\COREI2C\6.0.104\rtl\vhdl\core_obfuscated\corei2creal.vhd changed - recompiling
File D:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\lib\vhd\numeric.vhd changed - recompiling
File D:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\lib\vhd\unsigned.vhd changed - recompiling
File D:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\lib\vhd\arith.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreAhbSram\1.4.104\rtl\vhdl\o\ahbwrapper_sram.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreAhbSram\1.4.104\rtl\vhdl\o\sramctrl.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreAhbSram\1.4.104\rtl\vhdl\o\Sram_512to8192x8_fusion.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\smartgen\PLL_sys\PLL_sys.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CortexM1Top\3.0.102\CortexM1Integration\M1AFS1500\0_16_0_1_0008_0004_2_1\timingshell\vhdl\arm_synplify.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CortexM1Top\3.0.102\rtl\vhdl\o\uj_jtag.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CORE10100_AHBAPB\3.3.111\rtl\vhdl\core_obfuscated\utility.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CORE10100_AHBAPB\3.3.111\rtl\vhdl\core_obfuscated\rfifo.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CORE10100_AHBAPB\3.3.111\rtl\vhdl\core_obfuscated\rstc.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CORE10100_AHBAPB\3.3.111\rtl\vhdl\core_obfuscated\corecomps.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CORE10100_AHBAPB\3.3.111\rtl\vhdl\core_obfuscated\ramblocks_fusion.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core_obfuscated\coreahblite_addrdec.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core_obfuscated\coreahblite_defaultslavesm.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core_obfuscated\coreahblite_slavearbiter.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core_obfuscated\coreahblite_initcfg_awrap.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreAhbNvm\1.4.110\rtl\vhdl\core_obfuscated\coreahbnvm_ahbwrapper.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreAhbNvm\1.4.110\rtl\vhdl\core_obfuscated\coreahbnvm_nvmctrl.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\COREAI\3.0.119\rtl\vhdl\core_obf\coreai.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio_pkg.vhd changed - recompiling
File D:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\lib\vhd\misc.vhd changed - recompiling
File D:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\lib\vhd\std_textio.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreMemCtrl\2.0.105\rtl\vhdl\core_obfuscated\corememctrl.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreUARTapb\4.1.113\rtl\vhdl\core_obfuscated\Clock_gen.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreUARTapb\4.1.113\rtl\vhdl\core_obfuscated\Tx_async.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreUARTapb\4.1.113\rtl\vhdl\core_obfuscated\Rx_async.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreUARTapb\4.1.113\rtl\vhdl\core_obfuscated\fifo_256x8_fusion.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\COREAI\3.0.119\rtl\vhdl\core_obf\components.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\COREI2C\6.0.104\rtl\vhdl\core_obfuscated\corei2c.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\work\I2C_0\I2C_0.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\hdl\I2C_TOP.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreAhbSram\1.4.104\rtl\vhdl\o\ahbsramif.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreAhbSram\1.4.104\rtl\vhdl\o\sram.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreAhbSram\1.4.104\rtl\vhdl\o\coreahbsram.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CortexM1Top\3.0.102\rtl\vhdl\o\ResetSync_fusion.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CortexM1Top\3.0.102\rtl\vhdl\o\CortexM1Top_fusion.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CORE10100_AHBAPB\3.3.111\rtl\vhdl\core_obfuscated\dma.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CORE10100_AHBAPB\3.3.111\rtl\vhdl\core_obfuscated\tlsm.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CORE10100_AHBAPB\3.3.111\rtl\vhdl\core_obfuscated\tfifo.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CORE10100_AHBAPB\3.3.111\rtl\vhdl\core_obfuscated\tc.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CORE10100_AHBAPB\3.3.111\rtl\vhdl\core_obfuscated\bd.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CORE10100_AHBAPB\3.3.111\rtl\vhdl\core_obfuscated\rc.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CORE10100_AHBAPB\3.3.111\rtl\vhdl\core_obfuscated\rlsm.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CORE10100_AHBAPB\3.3.111\rtl\vhdl\core_obfuscated\csr.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CORE10100_AHBAPB\3.3.111\rtl\vhdl\core_obfuscated\mac.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CORE10100_AHBAPB\3.3.111\rtl\vhdl\core_obfuscated\dualram.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CORE10100_AHBAPB\3.3.111\rtl\vhdl\amba_obfuscated\core10100_ahbapb.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core_obfuscated\coreahblite_masterstage.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core_obfuscated\coreahblite_slavestage.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core_obfuscated\coreahblite_initcfg.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core_obfuscated\coreahblite_matrix2x16.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core_obfuscated\coreahblite.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreAhbNvm\1.4.110\rtl\vhdl\core_obfuscated\coreahbnvm_ahbnvmif.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreAhbNvm\1.4.110\rtl\vhdl\core_obfuscated\coreahbnvm.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreUARTapb\4.1.113\rtl\vhdl\core_obfuscated\CoreUART.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\Actel\DirectCore\CoreUARTapb\4.1.113\rtl\vhdl\core_obfuscated\CoreUARTapb.vhd changed - recompiling
File D:\DATA\Libero_Projects\M1Webserver_HW_Final\Fusion_M1webserver_HW\component\work\M1webserver_TOP\M1webserver_TOP.vhd changed - recompiling
@N:CD630 : M1webserver_TOP.vhd(23) | Synthesizing work.m1webserver_top.def_arch 
@W:CD277 : M1webserver_TOP.vhd(1070) | Port direction mismatch between component and entity
@N:CD630 : fusion.vhd(3156) | Synthesizing fusion.clkint.syn_black_box 
Post processing for fusion.clkint.syn_black_box
@N:CD630 : CoreUARTapb.vhd(12) | Synthesizing coreuartapb_lib.coreuartapb.cuartl0 
@N:CD364 : CoreUARTapb.vhd(195) | Removed redundant assignment
@N:CD364 : CoreUARTapb.vhd(214) | Removed redundant assignment
@N:CD630 : CoreUART.vhd(12) | Synthesizing coreuartapb_lib.coreuart.cuartl0 
@W:CD604 : CoreUART.vhd(349) | OTHERS clause is not synthesized 
@N:CD364 : CoreUART.vhd(387) | Removed redundant assignment
@N:CD630 : fifo_256x8_fusion.vhd(11) | Synthesizing coreuartapb_lib.cuartooi.cuartl0 
@W:CD638 : fifo_256x8_fusion.vhd(44) | Signal afull is undriven 
@W:CD638 : fifo_256x8_fusion.vhd(54) | Signal cuartl1il is undriven 
@N:CD630 : fifo_256x8_fusion.vhd(86) | Synthesizing coreuartapb_lib.cuartioli.cuartl0 
@W:CD638 : fifo_256x8_fusion.vhd(135) | Signal cuartoili is undriven 
@N:CD630 : fusion.vhd(3492) | Synthesizing fusion.fifo4k18.syn_black_box 
Post processing for fusion.fifo4k18.syn_black_box
@N:CD630 : fusion.vhd(2117) | Synthesizing fusion.inv.syn_black_box 
Post processing for fusion.inv.syn_black_box
@N:CD630 : fusion.vhd(1899) | Synthesizing fusion.gnd.syn_black_box 
Post processing for fusion.gnd.syn_black_box
@N:CD630 : fusion.vhd(3019) | Synthesizing fusion.vcc.syn_black_box 
Post processing for fusion.vcc.syn_black_box
Post processing for coreuartapb_lib.cuartioli.cuartl0
@W:CL240 : fifo_256x8_fusion.vhd(135) | CUARTOILI is not assigned a value (floating) - a simulation mismatch is possible 
Post processing for coreuartapb_lib.cuartooi.cuartl0
@N:CD630 : Rx_async.vhd(12) | Synthesizing coreuartapb_lib.cuarti0.cuartl0 
@N:CD233 : Rx_async.vhd(37) | Using sequential encoding for type cuarto0li
@N:CD364 : Rx_async.vhd(178) | Removed redundant assignment
@W:CD604 : Rx_async.vhd(231) | OTHERS clause is not synthesized 
@W:CD604 : Rx_async.vhd(309) | OTHERS clause is not synthesized 
Post processing for coreuartapb_lib.cuarti0.cuartl0
@N:CL177 : Rx_async.vhd(321) | Sharing sequential element CUARTLO0I.
@W:CL190 : Rx_async.vhd(321) | Optimizing register bit CUARTIOIi to a constant 0
@W:CL169 : Rx_async.vhd(321) | Pruning Register CUARTIOIi  
@N:CD630 : Tx_async.vhd(12) | Synthesizing coreuartapb_lib.cuartiil.cuartl0 
@N:CD364 : Tx_async.vhd(241) | Removed redundant assignment
Post processing for coreuartapb_lib.cuartiil.cuartl0
@N:CD630 : Clock_gen.vhd(12) | Synthesizing coreuartapb_lib.cuarto.cuartol 
Post processing for coreuartapb_lib.cuarto.cuartol
Post processing for coreuartapb_lib.coreuart.cuartl0
Post processing for coreuartapb_lib.coreuartapb.cuartl0
@N:CD630 : coregpio.vhd(13) | Synthesizing coregpio_lib.coregpio.cgpioo 
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@N:CD364 : coregpio.vhd(516) | Removed redundant assignment
@N:CD364 : coregpio.vhd(536) | Removed redundant assignment
@N:CD364 : coregpio.vhd(556) | Removed redundant assignment
@N:CD364 : coregpio.vhd(592) | Removed redundant assignment
@N:CD364 : coregpio.vhd(595) | Removed redundant assignment
@W:CD434 : coregpio.vhd(909) | Signal paddr in the sensitivity list is not used in the process
Post processing for coregpio_lib.coregpio.cgpioo
@N:CD630 : CortexM1Top_fusion.vhd(34) | Synthesizing work.cortexm1top.cortexm1top_i 
@W:CD275 : CortexM1Top_fusion.vhd(144) | Component declarations with different initial values are not supported.  Port a of component clkint may have been given a different initial value in two different component declarations
@N:CD630 : ResetSync_fusion.vhd(12) | Synthesizing work.resetsync.cortexm1top_i 
@N:CD630 : uj_jtag.vhd(5) | Synthesizing work.uj_jtag.cortexm1top_i10 
@W:CD638 : uj_jtag.vhd(66) | Signal cortexm1top_ilol is undriven 
@W:CD638 : uj_jtag.vhd(68) | Signal cortexm1top_oiol is undriven 
@W:CD638 : uj_jtag.vhd(70) | Signal cortexm1top_liol is undriven 
@W:CD638 : uj_jtag.vhd(72) | Signal cortexm1top_iiol is undriven 
Post processing for work.uj_jtag.cortexm1top_i10
@N:CD630 : fusion.vhd(4364) | Synthesizing fusion.ujtag.syn_black_box 
Post processing for fusion.ujtag.syn_black_box
Post processing for work.resetsync.cortexm1top_i
@N:CD630 : arm_synplify.vhd(126) | Synthesizing work.cortexm1integration.synplify_timing_shell 
Post processing for work.cortexm1integration.synplify_timing_shell
Post processing for work.cortexm1top.cortexm1top_i
@N:CD630 : PLL_sys.vhd(8) | Synthesizing work.pll_sys.def_arch 
@N:CD630 : fusion.vhd(4214) | Synthesizing fusion.pll.syn_black_box 
Post processing for fusion.pll.syn_black_box
@N:CD630 : fusion.vhd(406) | Synthesizing fusion.pllint.syn_black_box 
Post processing for fusion.pllint.syn_black_box
Post processing for work.pll_sys.def_arch
@N:CD630 : coreahbnvm.vhd(15) | Synthesizing coreahbnvm_lib.coreahbnvm.cahbnvmoil0 
@N:CD630 : fusion.vhd(4477) | Synthesizing fusion.nvm.syn_black_box 
Post processing for fusion.nvm.syn_black_box
@N:CD630 : coreahbnvm_ahbnvmif.vhd(14) | Synthesizing coreahbnvm_lib.cahbnvmii0i.cahbnvml00i 
@N:CD630 : coreahbnvm_nvmctrl.vhd(14) | Synthesizing coreahbnvm_lib.cahbnvmlo0.cahbnvmioll 
@W:CG296 : coreahbnvm_nvmctrl.vhd(510) | Incomplete sensitivity list - assuming completeness
@W:CG290 : coreahbnvm_nvmctrl.vhd(743) | Referenced variable cahbnvmi1ii is not in sensitivity list
@W:CG290 : coreahbnvm_nvmctrl.vhd(543) | Referenced variable cahbnvmooi is not in sensitivity list
@W:CG290 : coreahbnvm_nvmctrl.vhd(542) | Referenced variable cahbnvmi1l is not in sensitivity list
@W:CG290 : coreahbnvm_nvmctrl.vhd(541) | Referenced variable cahbnvmiil is not in sensitivity list
Post processing for coreahbnvm_lib.cahbnvmlo0.cahbnvmioll
@W:CL260 : coreahbnvm_nvmctrl.vhd(868) | Pruning Register bit 20 of CAHBNVMLiii(20 downto 0)  
@W:CL260 : coreahbnvm_nvmctrl.vhd(868) | Pruning Register bit 17 of CAHBNVMLiii(20 downto 0)  
@W:CL260 : coreahbnvm_nvmctrl.vhd(868) | Pruning Register bit 16 of CAHBNVMLiii(20 downto 0)  
@W:CL260 : coreahbnvm_nvmctrl.vhd(868) | Pruning Register bit 15 of CAHBNVMLiii(20 downto 0)  
@W:CL260 : coreahbnvm_nvmctrl.vhd(868) | Pruning Register bit 14 of CAHBNVMLiii(20 downto 0)  
@W:CL260 : coreahbnvm_nvmctrl.vhd(868) | Pruning Register bit 13 of CAHBNVMLiii(20 downto 0)  
@W:CL260 : coreahbnvm_nvmctrl.vhd(868) | Pruning Register bit 12 of CAHBNVMLiii(20 downto 0)  
@W:CL260 : coreahbnvm_nvmctrl.vhd(868) | Pruning Register bit 11 of CAHBNVMLiii(20 downto 0)  
@W:CL260 : coreahbnvm_nvmctrl.vhd(868) | Pruning Register bit 10 of CAHBNVMLiii(20 downto 0)  
@W:CL260 : coreahbnvm_nvmctrl.vhd(868) | Pruning Register bit 9 of CAHBNVMLiii(20 downto 0)  
@W:CL260 : coreahbnvm_nvmctrl.vhd(868) | Pruning Register bit 8 of CAHBNVMLiii(20 downto 0)  
@W:CL260 : coreahbnvm_nvmctrl.vhd(868) | Pruning Register bit 7 of CAHBNVMLiii(20 downto 0)  
@W:CL260 : coreahbnvm_nvmctrl.vhd(868) | Pruning Register bit 6 of CAHBNVMLiii(20 downto 0)  
@W:CL260 : coreahbnvm_nvmctrl.vhd(868) | Pruning Register bit 5 of CAHBNVMLiii(20 downto 0)  
@W:CL260 : coreahbnvm_nvmctrl.vhd(868) | Pruning Register bit 4 of CAHBNVMLiii(20 downto 0)  
@W:CL260 : coreahbnvm_nvmctrl.vhd(868) | Pruning Register bit 3 of CAHBNVMLiii(20 downto 0)  
@W:CL260 : coreahbnvm_nvmctrl.vhd(868) | Pruning Register bit 2 of CAHBNVMLiii(20 downto 0)  
@W:CL260 : coreahbnvm_nvmctrl.vhd(868) | Pruning Register bit 1 of CAHBNVMLiii(20 downto 0)  
@W:CL260 : coreahbnvm_nvmctrl.vhd(868) | Pruning Register bit 0 of CAHBNVMLiii(20 downto 0)  
@N:CD630 : coreahbnvm_ahbwrapper.vhd(14) | Synthesizing coreahbnvm_lib.cahbnvmo.cahbnvmii 
Post processing for coreahbnvm_lib.cahbnvmo.cahbnvmii
Post processing for coreahbnvm_lib.cahbnvmii0i.cahbnvml00i
Post processing for coreahbnvm_lib.coreahbnvm.cahbnvmoil0
@N:CD630 : coreahbsram.vhd(3) | Synthesizing work.coreahbsram.coreahbsram_oi 
@N:CD630 : sram.vhd(3) | Synthesizing work.coreahbsram_oii.coreahbsram_oi 
@N:CD630 : Sram_512to8192x8_fusion.vhd(4) | Synthesizing work.coreahbsram_oo0.coreahbsram_oi 
@W:CD434 : Sram_512to8192x8_fusion.vhd(284) | Signal coreahbsram_i0ll in the sensitivity list is not used in the process
@W:CD434 : Sram_512to8192x8_fusion.vhd(284) | Signal coreahbsram_o1ll in the sensitivity list is not used in the process
@W:CD434 : Sram_512to8192x8_fusion.vhd(284) | Signal coreahbsram_l1ll in the sensitivity list is not used in the process
@W:CD434 : Sram_512to8192x8_fusion.vhd(284) | Signal coreahbsram_i1ll in the sensitivity list is not used in the process
@W:CD434 : Sram_512to8192x8_fusion.vhd(284) | Signal coreahbsram_ooil in the sensitivity list is not used in the process
@W:CD434 : Sram_512to8192x8_fusion.vhd(284) | Signal coreahbsram_loil in the sensitivity list is not used in the process
@W:CD434 : Sram_512to8192x8_fusion.vhd(284) | Signal coreahbsram_ioil in the sensitivity list is not used in the process
@W:CD434 : Sram_512to8192x8_fusion.vhd(284) | Signal coreahbsram_olil in the sensitivity list is not used in the process
@W:CD434 : Sram_512to8192x8_fusion.vhd(284) | Signal coreahbsram_llil in the sensitivity list is not used in the process
@W:CD434 : Sram_512to8192x8_fusion.vhd(284) | Signal coreahbsram_ilil in the sensitivity list is not used in the process
@W:CD434 : Sram_512to8192x8_fusion.vhd(284) | Signal coreahbsram_oiil in the sensitivity list is not used in the process
@W:CD434 : Sram_512to8192x8_fusion.vhd(284) | Signal coreahbsram_liil in the sensitivity list is not used in the process
@N:CD630 : fusion.vhd(3182) | Synthesizing fusion.ram4k9.syn_black_box 
Post processing for fusion.ram4k9.syn_black_box
Post processing for work.coreahbsram_oo0.coreahbsram_oi
@W:CL168 : Sram_512to8192x8_fusion.vhd(8192) | Pruning instance COreAhbSrAM_I1oi - not in use ... 
@W:CL168 : Sram_512to8192x8_fusion.vhd(8116) | Pruning instance CoreAhbSRAM_L1OI - not in use ... 
@W:CL168 : Sram_512to8192x8_fusion.vhd(8040) | Pruning instance CoreAhbSram_O1OI - not in use ... 
@W:CL168 : Sram_512to8192x8_fusion.vhd(7964) | Pruning instance COreAhbSram_i0OI - not in use ... 
@W:CL168 : Sram_512to8192x8_fusion.vhd(7888) | Pruning instance COReAhbSram_l0OI - not in use ... 
@W:CL168 : Sram_512to8192x8_fusion.vhd(7812) | Pruning instance COReAhbSram_o0OI - not in use ... 
@W:CL168 : Sram_512to8192x8_fusion.vhd(7736) | Pruning instance COREAhbSram_iioi - not in use ... 
@W:CL168 : Sram_512to8192x8_fusion.vhd(7660) | Pruning instance COREAhbSram_lioI - not in use ... 
@W:CL168 : Sram_512to8192x8_fusion.vhd(7584) | Pruning instance COREAHbSram_oioi - not in use ... 
@W:CL168 : Sram_512to8192x8_fusion.vhd(7508) | Pruning instance CoreAhbSrAM_ILOI - not in use ... 
@W:CL168 : Sram_512to8192x8_fusion.vhd(7432) | Pruning instance COREAhbSram_LLOI - not in use ... 
@W:CL168 : Sram_512to8192x8_fusion.vhd(7356) | Pruning instance COREAhbSram_olOI - not in use ... 
@W:CL169 : Sram_512to8192x8_fusion.vhd(278) | Pruning Register CoreAhbSram_IO1(12 downto 9)  
Post processing for work.coreahbsram_oii.coreahbsram_oi
@N:CD630 : ahbsramif.vhd(3) | Synthesizing work.coreahbsram_o.coreahbsram_oi 
@N:CD630 : sramctrl.vhd(3) | Synthesizing work.coreahbsram_l1.coreahbsram_oi 
@N:CD233 : sramctrl.vhd(24) | Using sequential encoding for type coreahbsram_ll0
@W:CD604 : sramctrl.vhd(87) | OTHERS clause is not synthesized 
Post processing for work.coreahbsram_l1.coreahbsram_oi
@W:CL260 : sramctrl.vhd(101) | Pruning Register bit 2 of COREAHBSram_l10(2 downto 0)  
@N:CD630 : ahbwrapper_sram.vhd(3) | Synthesizing work.coreahbsram_li.coreahbsram_oi 
@N:CD364 : ahbwrapper_sram.vhd(77) | Removed redundant assignment
@N:CD364 : ahbwrapper_sram.vhd(78) | Removed redundant assignment
@N:CD364 : ahbwrapper_sram.vhd(115) | Removed redundant assignment
@W:CD638 : ahbwrapper_sram.vhd(52) | Signal coreahbsram_ooi is undriven 
@W:CD638 : ahbwrapper_sram.vhd(54) | Signal coreahbsram_loi is undriven 
@W:CD638 : ahbwrapper_sram.vhd(56) | Signal coreahbsram_ioi is undriven 
Post processing for work.coreahbsram_li.coreahbsram_oi
Post processing for work.coreahbsram_o.coreahbsram_oi
Post processing for work.coreahbsram.coreahbsram_oi
@N:CD630 : I2C_TOP.vhd(9) | Synthesizing work.i2c_top.i2c_top_arc 
@N:CD630 : I2C_0.vhd(10) | Synthesizing work.i2c_0.def_arch 
@N:CD630 : corei2c.vhd(13) | Synthesizing corei2c_lib.corei2c.rtl 
@W:CD638 : corei2c.vhd(132) | Signal ci2cl1 is undriven 
@N:CD630 : corei2creal.vhd(13) | Synthesizing corei2c_lib.corei2creal.rtl 
@N:CD231 : corei2creal.vhd(124) | Using onehot encoding for type ci2cloil (ci2cioil="1000000")
@N:CD231 : corei2creal.vhd(120) | Using onehot encoding for type ci2clill (ci2ciill="10000000")
@N:CD231 : corei2creal.vhd(116) | Using onehot encoding for type ci2ci1ol (ci2cooll="1000000")
@N:CD232 : corei2creal.vhd(112) | Using gray code encoding for type ci2ci10
@W:CD434 : corei2creal.vhd(1082) | Signal ci2coo1l in the sensitivity list is not used in the process
@W:CD638 : corei2creal.vhd(186) | Signal ci2coi1l is undriven 
@W:CD638 : corei2creal.vhd(188) | Signal ci2cli1l is undriven 
@W:CD638 : corei2creal.vhd(192) | Signal ci2co01l is undriven 
@W:CD638 : corei2creal.vhd(196) | Signal ci2ci01l is undriven 
@W:CD638 : corei2creal.vhd(198) | Signal ci2co11l is undriven 
@W:CD638 : corei2creal.vhd(200) | Signal ci2cl11l is undriven 
@W:CD638 : corei2creal.vhd(220) | Signal ci2ciioi is undriven 
@W:CD638 : corei2creal.vhd(222) | Signal ci2co0oi is undriven 
@W:CD638 : corei2creal.vhd(224) | Signal ci2cl0oi is undriven 
@W:CD638 : corei2creal.vhd(226) | Signal ci2ci0oi is undriven 
Post processing for corei2c_lib.corei2creal.rtl
@W:CL190 : corei2creal.vhd(1384) | Optimizing register bit CI2Ciloi to a constant 1
@W:CL169 : corei2creal.vhd(1384) | Pruning Register CI2Ciloi  
Post processing for corei2c_lib.corei2c.rtl
@W:CL169 : corei2c.vhd(168) | Pruning Register CI2Ci0  
@W:CL169 : corei2c.vhd(168) | Pruning Register CI2Cl0  
@W:CL169 : corei2c.vhd(151) | Pruning Register CI2Co0(12 downto 0)  
Post processing for work.i2c_0.def_arch
@W:CL168 : I2C_0.vhd(82) | Pruning instance 	VCC - not in use ... 
Post processing for work.i2c_top.i2c_top_arc
@N:CD630 : CoreAHB2APB.vhd(3) | Synthesizing work.coreahb2apb.coreahb2apb_o 
Post processing for work.coreahb2apb.coreahb2apb_o
@N:CD630 : coreahblite.vhd(14) | Synthesizing coreahblite_lib.coreahblite.cahbltiiilll 
@N:CD630 : coreahblite_matrix2x16.vhd(14) | Synthesizing coreahblite_lib.cahblti000.cahblti100 
@N:CD630 : coreahblite_initcfg.vhd(14) | Synthesizing coreahblite_lib.cahbltoil0.cahblti0l0 
@N:CD630 : coreahblite_initcfg_awrap.vhd(14) | Synthesizing coreahblite_lib.cahbltol1i.cahblto01i 
Post processing for coreahblite_lib.cahbltol1i.cahblto01i
@W:CL169 : coreahblite_initcfg_awrap.vhd(118) | Pruning Register CAHBLToiO0  
@N:CD630 : coreahblite_slavearbiter.vhd(14) | Synthesizing coreahblite_lib.cahbltil1.cahblti01 
@W:CD604 : coreahblite_slavearbiter.vhd(167) | OTHERS clause is not synthesized 
Post processing for coreahblite_lib.cahbltil1.cahblti01
Post processing for coreahblite_lib.cahbltoil0.cahblti0l0
@N:CD630 : coreahblite_slavestage.vhd(14) | Synthesizing coreahblite_lib.cahbltliii.cahbltl00i 
Post processing for coreahblite_lib.cahbltliii.cahbltl00i
@N:CD630 : coreahblite_masterstage.vhd(14) | Synthesizing coreahblite_lib.cahbltl0ol.cahbltoiil 
@W:CD434 : coreahblite_masterstage.vhd(430) | Signal hrdata_shg in the sensitivity list is not used in the process
@W:CD434 : coreahblite_masterstage.vhd(430) | Signal hreadyout_shg in the sensitivity list is not used in the process
@W:CD434 : coreahblite_masterstage.vhd(430) | Signal cahbltlill in the sensitivity list is not used in the process
@W:CD434 : coreahblite_masterstage.vhd(430) | Signal cahbltiill in the sensitivity list is not used in the process
@W:CD434 : coreahblite_masterstage.vhd(430) | Signal cahbltilil in the sensitivity list is not used in the process
@W:CD604 : coreahblite_masterstage.vhd(911) | OTHERS clause is not synthesized 
@N:CD630 : coreahblite_defaultslavesm.vhd(14) | Synthesizing coreahblite_lib.cahblti00.cahbltoo1 
@W:CD604 : coreahblite_defaultslavesm.vhd(49) | OTHERS clause is not synthesized 
Post processing for coreahblite_lib.cahblti00.cahbltoo1
@N:CD630 : coreahblite_addrdec.vhd(14) | Synthesizing coreahblite_lib.cahblto.cahblto0 
Post processing for coreahblite_lib.cahblto.cahblto0
Post processing for coreahblite_lib.cahbltl0ol.cahbltoiil
@N:CL177 : coreahblite_masterstage.vhd(917) | Sharing sequential element CAHBLTLO0L.
Post processing for coreahblite_lib.cahblti000.cahblti100
Post processing for coreahblite_lib.coreahblite.cahbltiiilll
@N:CD630 : PHY_MDIO.vhd(8) | Synthesizing work.phy_mdio.def_arch 
@N:CD630 : fusion.vhd(424) | Synthesizing fusion.bibuf.syn_black_box 
Post processing for fusion.bibuf.syn_black_box
Post processing for work.phy_mdio.def_arch
@W:CL168 : PHY_MDIO.vhd(55) | Pruning instance 	GND - not in use ... 
@W:CL168 : PHY_MDIO.vhd(49) | Pruning instance 	VCC - not in use ... 
@N:CD630 : coreai.vhd(15) | Synthesizing coreai_lib.coreai.caio 
@N:CD630 : fusion.vhd(4037) | Synthesizing fusion.ab.syn_black_box 
Post processing for fusion.ab.syn_black_box
@N:CD630 : fusion.vhd(1912) | Synthesizing fusion.inbuf_a.syn_black_box 
Post processing for fusion.inbuf_a.syn_black_box
Post processing for coreai_lib.coreai.caio
@N:CD630 : corememctrl.vhd(21) | Synthesizing corememctrl_lib.corememctrl.corememctrl_o 
@W:CD434 : corememctrl.vhd(323) | Signal corememctrl_iool in the sensitivity list is not used in the process
@W:CD434 : corememctrl.vhd(343) | Signal corememctrl_oo1 in the sensitivity list is not used in the process
@W:CD434 : corememctrl.vhd(826) | Signal corememctrl_iool in the sensitivity list is not used in the process
@W:CD604 : corememctrl.vhd(880) | OTHERS clause is not synthesized 
@W:CD604 : corememctrl.vhd(889) | OTHERS clause is not synthesized 
@W:CD604 : corememctrl.vhd(942) | OTHERS clause is not synthesized 
@W:CD604 : corememctrl.vhd(951) | OTHERS clause is not synthesized 
@W:CD434 : corememctrl.vhd(909) | Signal corememctrl_il1 in the sensitivity list is not used in the process
@W:CD434 : corememctrl.vhd(909) | Signal corememctrl_ii0 in the sensitivity list is not used in the process
@W:CD434 : corememctrl.vhd(967) | Signal corememctrl_ll0 in the sensitivity list is not used in the process
@W:CD434 : corememctrl.vhd(967) | Signal corememctrl_l00 in the sensitivity list is not used in the process
Post processing for corememctrl_lib.corememctrl.corememctrl_o
@W:CL169 : corememctrl.vhd(963) | Pruning Register coREMEMCTRL_l00(31 downto 0)  
@W:CL169 : corememctrl.vhd(903) | Pruning Register COREmemctrl_ii0(15 downto 0)  
@W:CL169 : corememctrl.vhd(772) | Pruning Register corEMEMCTRL_iool  
@W:CL169 : corememctrl.vhd(279) | Pruning Register corememctrL_L10(1 downto 0)  
@N:CD630 : core10100_ahbapb.vhd(14) | Synthesizing core10100_ahbapb_lib.core10100_ahbapb.cmaciol 
@N:CD233 : core10100_ahbapb.vhd(146) | Using sequential encoding for type cmaco1110l
@W:CD638 : core10100_ahbapb.vhd(158) | Signal cmaciloo1l is undriven 
@W:CD638 : core10100_ahbapb.vhd(160) | Signal cmacoioo1l is undriven 
@N:CD630 : dualram.vhd(12) | Synthesizing core10100_ahbapb_lib.dualram.cmaciol 
@W:CD638 : dualram.vhd(265) | Signal cmacoll10l is undriven 
@N:CD630 : ramblocks_fusion.vhd(361) | Synthesizing core10100_ahbapb_lib.cmaci1ll0.cmaciol 
Post processing for core10100_ahbapb_lib.cmaci1ll0.cmaciol
Post processing for core10100_ahbapb_lib.dualram.cmaciol
@N:CD630 : dualram.vhd(12) | Synthesizing core10100_ahbapb_lib.dualram.cmaciol 
@W:CD638 : dualram.vhd(265) | Signal cmacoll10l is undriven 
@N:CD630 : ramblocks_fusion.vhd(9411) | Synthesizing core10100_ahbapb_lib.cmacl11l0.cmaciol 
Post processing for core10100_ahbapb_lib.cmacl11l0.cmaciol
Post processing for core10100_ahbapb_lib.dualram.cmaciol
@N:CD630 : dualram.vhd(12) | Synthesizing core10100_ahbapb_lib.dualram.cmaciol 
@W:CD638 : dualram.vhd(265) | Signal cmacoll10l is undriven 
@N:CD630 : ramblocks_fusion.vhd(9883) | Synthesizing core10100_ahbapb_lib.cmacoooi0.cmaciol 
Post processing for core10100_ahbapb_lib.cmacoooi0.cmaciol
Post processing for core10100_ahbapb_lib.dualram.cmaciol
@N:CD630 : mac.vhd(13) | Synthesizing core10100_ahbapb_lib.mac.cmaciol 
@N:CD630 : rstc.vhd(11) | Synthesizing core10100_ahbapb_lib.cmaclll0.cmaciol 
Post processing for core10100_ahbapb_lib.cmaclll0.cmaciol
@N:CD630 : csr.vhd(13) | Synthesizing core10100_ahbapb_lib.cmaci0oi.cmaciol 
@N:CD233 : utility.vhd(127) | Using sequential encoding for type cmacoli1
@W:CD434 : csr.vhd(421) | Signal csraddr in the sensitivity list is not used in the process
@W:CD434 : csr.vhd(421) | Signal cmaco0l0 in the sensitivity list is not used in the process
@W:CD434 : csr.vhd(421) | Signal cmaci0l0 in the sensitivity list is not used in the process
@W:CD434 : csr.vhd(947) | Signal csraddr in the sensitivity list is not used in the process
@W:CD434 : csr.vhd(947) | Signal cmaco0l0 in the sensitivity list is not used in the process
Post processing for core10100_ahbapb_lib.cmaci0oi.cmaciol
@W:CL169 : csr.vhd(631) | Pruning Register CMACoi01  
@W:CL169 : csr.vhd(482) | Pruning Register CMACL0LOL  
@W:CL169 : csr.vhd(482) | Pruning Register CMACO0lol  
@W:CL170 : csr.vhd(1705) | Pruning bit <15> of CMACilLOL(15 downto 0) - not in use ... 
@N:CD630 : rlsm.vhd(14) | Synthesizing core10100_ahbapb_lib.cmacl1o0.cmaciol 
@N:CD231 : utility.vhd(131) | Using onehot encoding for type cmaci0oli (cmaciloii="10000000000")
@W:CD434 : rlsm.vhd(302) | Signal cmacll0li in the sensitivity list is not used in the process
@W:CD434 : rlsm.vhd(302) | Signal cmaci00li in the sensitivity list is not used in the process
@W:CD434 : rlsm.vhd(366) | Signal cmacioili in the sensitivity list is not used in the process
@N:CD364 : rlsm.vhd(684) | Removed redundant assignment
Post processing for core10100_ahbapb_lib.cmacl1o0.cmaciol
@W:CL170 : rlsm.vhd(200) | Pruning bit <1> of CMACi0ili(13 downto 0) - not in use ... 
@W:CL170 : rlsm.vhd(200) | Pruning bit <0> of CMACi0ili(13 downto 0) - not in use ... 
@W:CL169 : rlsm.vhd(499) | Pruning Register CMACl1oli(cmaciloii)  
@N:CD630 : rfifo.vhd(14) | Synthesizing core10100_ahbapb_lib.cmacli1i.cmaciol 
Post processing for core10100_ahbapb_lib.cmacli1i.cmaciol
@N:CD630 : rc.vhd(15) | Synthesizing core10100_ahbapb_lib.cmaci00i.cmaciol 
@N:CD231 : utility.vhd(137) | Using onehot encoding for type cmacllo1l (cmacil01l="1000000000")
@N:CD231 : utility.vhd(139) | Using onehot encoding for type cmaco0l1l (cmaci0ooi="100000")
@W:CD434 : rc.vhd(212) | Signal cmacoio1l in the sensitivity list is not used in the process
@W:CD434 : rc.vhd(212) | Signal cmaclio1l in the sensitivity list is not used in the process
Post processing for core10100_ahbapb_lib.cmaci00i.cmaciol
@W:CL260 : rc.vhd(492) | Pruning Register bit 3 of CMACoio1L(3 downto 0)  
@N:CD630 : bd.vhd(14) | Synthesizing core10100_ahbapb_lib.cmaco.cmaciol 
Post processing for core10100_ahbapb_lib.cmaco.cmaciol
@N:CD630 : tc.vhd(14) | Synthesizing core10100_ahbapb_lib.cmacoioi.cmaciol 
@N:CD231 : utility.vhd(143) | Using onehot encoding for type cmacll0ii (cmacl11ii="1000000000")
Post processing for core10100_ahbapb_lib.cmacoioi.cmaciol
@N:CD630 : tfifo.vhd(16) | Synthesizing core10100_ahbapb_lib.cmacl11.cmaciol 
Post processing for core10100_ahbapb_lib.cmacl11.cmaciol
@N:CD630 : tlsm.vhd(13) | Synthesizing core10100_ahbapb_lib.cmacil0l.cmaciol 
@N:CD231 : utility.vhd(131) | Using onehot encoding for type cmaci0oli (cmaciloii="10000000000")
@N:CD231 : utility.vhd(133) | Using onehot encoding for type cmaclo01i (cmaclioo0="1000000")
@W:CD434 : tlsm.vhd(653) | Signal cmacoo11i in the sensitivity list is not used in the process
@W:CD434 : tlsm.vhd(843) | Signal cmaciil0l in the sensitivity list is not used in the process
@W:CD434 : tlsm.vhd(957) | Signal cmaci111i in the sensitivity list is not used in the process
Post processing for core10100_ahbapb_lib.cmacil0l.cmaciol
@W:CL170 : tlsm.vhd(681) | Pruning bit <1> of CMACL1O1l(11 downto 0) - not in use ... 
@W:CL170 : tlsm.vhd(681) | Pruning bit <0> of CMACL1O1l(11 downto 0) - not in use ... 
@W:CL169 : tlsm.vhd(346) | Pruning Register CMACl1oli(cmaciloii)  
@W:CL190 : tlsm.vhd(711) | Optimizing register bit CMACl111i(3) to a constant 1
@W:CL190 : tlsm.vhd(742) | Optimizing register bit CMAClioi(0) to a constant 1
@W:CL190 : tlsm.vhd(1036) | Optimizing register bit CMACoiol(0) to a constant 1
@W:CL260 : tlsm.vhd(742) | Pruning Register bit 0 of CMAClioi(3 downto 0)  
@W:CL260 : tlsm.vhd(1036) | Pruning Register bit 0 of CMACoiol(3 downto 0)  
@W:CL260 : tlsm.vhd(711) | Pruning Register bit 3 of CMACl111i(3 downto 0)  
@N:CD630 : dma.vhd(14) | Synthesizing core10100_ahbapb_lib.cmaclo0.cmaciol 
@N:CD233 : utility.vhd(125) | Using sequential encoding for type cmaclooil
@N:CD364 : dma.vhd(188) | Removed redundant assignment
Post processing for core10100_ahbapb_lib.cmaclo0.cmaciol
Post processing for core10100_ahbapb_lib.mac.cmaciol
Post processing for core10100_ahbapb_lib.core10100_ahbapb.cmaciol
@N:CD630 : CoreAPB.vhd(3) | Synthesizing work.coreapb.coreapb_o 
@N:CD630 : MuxP2B.vhd(3) | Synthesizing work.coreapb_l.coreapb_li0 
@W:CD604 : MuxP2B.vhd(144) | OTHERS clause is not synthesized 
Post processing for work.coreapb_l.coreapb_li0
Post processing for work.coreapb.coreapb_o
Post processing for work.m1webserver_top.def_arch
@N:CL201 : dma.vhd(168) | Trying to extract state machine for register CMACiooil
Extracted state machine for register CMACiooil
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@W:CL159 : dma.vhd(20) | Input CMACol0 is unused
@W:CL159 : dma.vhd(21) | Input CMACll0 is unused
@W:CL159 : dma.vhd(22) | Input CMACil0 is unused
@W:CL159 : dma.vhd(23) | Input CMACoI0 is unused
@W:CL159 : dma.vhd(24) | Input CMACli0 is unused
@W:CL159 : dma.vhd(25) | Input CMACii0 is unused
@W:CL159 : dma.vhd(26) | Input CMACo00 is unused
@W:CL159 : dma.vhd(27) | Input CMACl00 is unused
@W:CL260 : tlsm.vhd(346) | Pruning Register bit 0 of CMACl1oli(0 to 9)  
@W:CL260 : tlsm.vhd(346) | Pruning Register bit 1 of CMACl1oli(0 to 9)  
@W:CL260 : tlsm.vhd(346) | Pruning Register bit 2 of CMACl1oli(0 to 9)  
@W:CL260 : tlsm.vhd(346) | Pruning Register bit 3 of CMACl1oli(0 to 9)  
@W:CL260 : tlsm.vhd(346) | Pruning Register bit 4 of CMACl1oli(0 to 9)  
@W:CL260 : tlsm.vhd(346) | Pruning Register bit 9 of CMACl1oli(0 to 9)  
@W:CL190 : tlsm.vhd(1023) | Optimizing register bit CMACo111i(3) to a constant 0
@W:CL260 : tlsm.vhd(1023) | Pruning Register bit 3 of CMACo111i(3 downto 0)  
@N:CL201 : tlsm.vhd(421) | Trying to extract state machine for register CMACio01i
Extracted state machine for register CMACio01i
State machine has 7 reachable states with original encodings of:
   0000001
   0000010
   0000100
   0001000
   0010000
   0100000
   1000000
@N:CL201 : tlsm.vhd(346) | Trying to extract state machine for register CMACO1oli
Extracted state machine for register CMACO1oli
State machine has 9 reachable states with original encodings of:
   00000000001
   00000000100
   00000001000
   00000010000
   00000100000
   00001000000
   00010000000
   00100000000
   10000000000
@W:CL260 : tc.vhd(768) | Pruning Register bit 31 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 30 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 29 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 28 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 27 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 26 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 25 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 24 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 23 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 22 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 21 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 20 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 19 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 18 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 17 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 16 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 15 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 14 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 13 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 12 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 11 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 10 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 9 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 8 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 6 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 5 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 4 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 3 of CMACI1iii(31 downto 0)  
@W:CL260 : tc.vhd(768) | Pruning Register bit 2 of CMACI1iii(31 downto 0)  
@W:CL189 : tc.vhd(456) | Register bit CMACli0ii(6) is always 0, optimizing ...
@W:CL260 : tc.vhd(456) | Pruning Register bit 6 of CMACli0ii(6 downto 0)  
@W:CL260 : tc.vhd(456) | Pruning Register bit 5 of CMACli0ii(6 downto 0)  
@W:CL260 : tc.vhd(456) | Pruning Register bit 4 of CMACli0ii(6 downto 0)  
@W:CL260 : tc.vhd(161) | Pruning Register bit 8 of CMAClliii(8 downto 0)  
@N:CL201 : tc.vhd(353) | Trying to extract state machine for register CMACil0II
Extracted state machine for register CMACil0II
State machine has 9 reachable states with original encodings of:
   0000000001
   0000000010
   0000000100
   0000001000
   0000010000
   0000100000
   0010000000
   0100000000
   1000000000
@N:CL177 : tc.vhd(854) | Sharing sequential element CMACio0ii.
@N:CL201 : rc.vhd(929) | Trying to extract state machine for register CMACL0L1L
Extracted state machine for register CMACL0L1L
State machine has 6 reachable states with original encodings of:
   000001
   000010
   000100
   001000
   010000
   100000
@N:CL201 : rc.vhd(461) | Trying to extract state machine for register CMACilo1l
Extracted state machine for register CMACilo1l
State machine has 10 reachable states with original encodings of:
   0000000001
   0000000010
   0000000100
   0000001000
   0000010000
   0000100000
   0001000000
   0010000000
   0100000000
   1000000000
@N:CL134 : rfifo.vhd(113) | Found RAM CMAColioi, depth=4, width=23
@W:CL260 : rlsm.vhd(499) | Pruning Register bit 0 of CMACl1oli(0 to 9)  
@W:CL260 : rlsm.vhd(499) | Pruning Register bit 1 of CMACl1oli(0 to 9)  
@W:CL260 : rlsm.vhd(499) | Pruning Register bit 2 of CMACl1oli(0 to 9)  
@W:CL190 : rlsm.vhd(743) | Optimizing register bit CMACo1ili(0) to a constant 0
@W:CL190 : rlsm.vhd(743) | Optimizing register bit CMACo1ili(1) to a constant 0
@W:CL260 : rlsm.vhd(743) | Pruning Register bit 1 of CMACo1ili(13 downto 0)  
@W:CL260 : rlsm.vhd(743) | Pruning Register bit 0 of CMACo1ili(13 downto 0)  
@N:CL201 : rlsm.vhd(499) | Trying to extract state machine for register CMACo1oli
Extracted state machine for register CMACo1oli
State machine has 11 reachable states with original encodings of:
   00000000001
   00000000010
   00000000100
   00000001000
   00000010000
   00000100000
   00001000000
   00010000000
   00100000000
   01000000000
   10000000000
@W:CL159 : rlsm.vhd(19) | Input CMACo10I is unused
@N:CL201 : csr.vhd(1439) | Trying to extract state machine for register CMACo1i1
Extracted state machine for register CMACo1i1
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@N:CL201 : csr.vhd(1340) | Trying to extract state machine for register CMACLli1
Extracted state machine for register CMACLli1
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@W:CL246 : csr.vhd(24) | Input port bits 1 to 0 of csraddr(7 downto 0) are unused 
@W:CL247 : csr.vhd(67) | Input port bit 15 of cmacoiii(15 downto 0) is unused 
@W:CL159 : rstc.vhd(12) | Input CLKDMA is unused
@W:CL159 : rstc.vhd(14) | Input CLKT is unused
@W:CL159 : rstc.vhd(15) | Input CLKR is unused
@W:CL159 : core10100_ahbapb.vhd(36) | Input HRESP is unused
@N:CL201 : corememctrl.vhd(772) | Trying to extract state machine for register corememctrl_O0I
Extracted state machine for register corememctrl_O0I
State machine has 6 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
@W:CL247 : corememctrl.vhd(37) | Input port bit 0 of htrans(1 downto 0) is unused 
@W:CL247 : coreai.vhd(106) | Input port bit 6 of paddr(6 downto 0) is unused 
@W:CL246 : coreai.vhd(106) | Input port bits 1 to 0 of paddr(6 downto 0) are unused 
@W:CL246 : coreai.vhd(110) | Input port bits 31 to 16 of pwdata(31 downto 0) are unused 
@W:CL159 : coreai.vhd(116) | Input GNdref is unused
@W:CL159 : coreai.vhd(117) | Input aV9 is unused
@W:CL159 : coreai.vhd(118) | Input Av8 is unused
@W:CL159 : coreai.vhd(119) | Input av7 is unused
@W:CL159 : coreai.vhd(120) | Input AV6 is unused
@W:CL159 : coreai.vhd(121) | Input AV5 is unused
@W:CL159 : coreai.vhd(122) | Input AV4 is unused
@W:CL159 : coreai.vhd(123) | Input av3 is unused
@W:CL159 : coreai.vhd(124) | Input AV2 is unused
@W:CL159 : coreai.vhd(125) | Input AV1 is unused
@W:CL159 : coreai.vhd(126) | Input AV0 is unused
@W:CL159 : coreai.vhd(127) | Input AC9 is unused
@W:CL159 : coreai.vhd(128) | Input ac8 is unused
@W:CL159 : coreai.vhd(129) | Input AC7 is unused
@W:CL159 : coreai.vhd(130) | Input AC6 is unused
@W:CL159 : coreai.vhd(131) | Input ac5 is unused
@W:CL159 : coreai.vhd(133) | Input ac3 is unused
@W:CL159 : coreai.vhd(134) | Input ac2 is unused
@W:CL159 : coreai.vhd(135) | Input AC1 is unused
@W:CL159 : coreai.vhd(136) | Input ac0 is unused
@W:CL159 : coreai.vhd(137) | Input AT9 is unused
@W:CL159 : coreai.vhd(138) | Input AT8 is unused
@W:CL159 : coreai.vhd(139) | Input AT7 is unused
@W:CL159 : coreai.vhd(140) | Input AT6 is unused
@W:CL159 : coreai.vhd(141) | Input AT5 is unused
@W:CL159 : coreai.vhd(142) | Input at4 is unused
@W:CL159 : coreai.vhd(143) | Input at3 is unused
@W:CL159 : coreai.vhd(145) | Input at1 is unused
@W:CL159 : coreai.vhd(146) | Input AT0 is unused
@W:CL159 : coreai.vhd(147) | Input ATREturn4 is unused
@W:CL159 : coreai.vhd(148) | Input atRETURN3 is unused
@W:CL159 : coreai.vhd(149) | Input atreturn2 is unused
@W:CL159 : coreai.vhd(151) | Input atreturn0 is unused
@W:CL159 : coreai.vhd(182) | Input Hd_gdon9 is unused
@W:CL159 : coreai.vhd(183) | Input HD_GDON8 is unused
@W:CL159 : coreai.vhd(184) | Input hd_gdon7 is unused
@W:CL159 : coreai.vhd(185) | Input HD_GDON6 is unused
@W:CL159 : coreai.vhd(186) | Input hd_gdon5 is unused
@W:CL159 : coreai.vhd(187) | Input hD_GDON4 is unused
@W:CL159 : coreai.vhd(188) | Input HD_GDon3 is unused
@W:CL159 : coreai.vhd(189) | Input HD_GDon2 is unused
@W:CL159 : coreai.vhd(190) | Input hd_gdoN1 is unused
@W:CL159 : coreai.vhd(191) | Input hd_gDON0 is unused
@W:CL159 : coreai.vhd(202) | Input HD_ADCRESET is unused
@W:CL159 : coreai.vhd(203) | Input hd_pwrdwn is unused
@W:CL159 : coreai.vhd(204) | Input HD_Varefsel is unused
@W:CL159 : coreai.vhd(205) | Input HD_MODE is unused
@W:CL159 : coreai.vhd(206) | Input HD_TVC is unused
@W:CL159 : coreai.vhd(207) | Input HD_STC is unused
@W:CL159 : coreai.vhd(208) | Input HD_adcstart is unused
@W:CL159 : coreai.vhd(209) | Input HD_CHNUMBER is unused
@W:CL159 : coreai.vhd(210) | Input HD_CMSTB9 is unused
@W:CL159 : coreai.vhd(211) | Input HD_CMSTB8 is unused
@W:CL159 : coreai.vhd(212) | Input hd_cmstb7 is unused
@W:CL159 : coreai.vhd(213) | Input hd_cmSTB6 is unused
@W:CL159 : coreai.vhd(214) | Input HD_CMSTb5 is unused
@W:CL159 : coreai.vhd(215) | Input hd_cmstb4 is unused
@W:CL159 : coreai.vhd(216) | Input hd_cmstb3 is unused
@W:CL159 : coreai.vhd(217) | Input HD_Cmstb2 is unused
@W:CL159 : coreai.vhd(218) | Input hd_cmstb1 is unused
@W:CL159 : coreai.vhd(219) | Input hd_cmstb0 is unused
@W:CL159 : coreai.vhd(220) | Input Hd_tmstbint is unused
@W:CL159 : coreai.vhd(221) | Input HD_TMSTB9 is unused
@W:CL159 : coreai.vhd(222) | Input hd_TMSTB8 is unused
@W:CL159 : coreai.vhd(223) | Input hd_tmstb7 is unused
@W:CL159 : coreai.vhd(224) | Input HD_TMSTB6 is unused
@W:CL159 : coreai.vhd(225) | Input Hd_tmstb5 is unused
@W:CL159 : coreai.vhd(226) | Input HD_TMSTB4 is unused
@W:CL159 : coreai.vhd(227) | Input Hd_tmstb3 is unused
@W:CL159 : coreai.vhd(228) | Input hd_tmsTB2 is unused
@W:CL159 : coreai.vhd(229) | Input hd_tmsTB1 is unused
@W:CL159 : coreai.vhd(230) | Input HD_TMSTB0 is unused
@W:CL159 : coreai.vhd(237) | Input RTCCLK is unused
@W:CL247 : coreahblite_masterstage.vhd(29) | Input port bit 16 of cahbltllll(16 downto 0) is unused 
@W:CL247 : coreahblite_masterstage.vhd(30) | Input port bit 16 of cahbltilll(16 downto 0) is unused 
@W:CL159 : coreahblite_masterstage.vhd(32) | Input CAHBLTLILL is unused
@W:CL159 : coreahblite_masterstage.vhd(33) | Input CAHBLTIIll is unused
@W:CL159 : coreahblite_masterstage.vhd(77) | Input HRDATA_SHG is unused
@W:CL159 : coreahblite_masterstage.vhd(78) | Input HREADYOUT_SHG is unused
@W:CL159 : coreahblite_masterstage.vhd(79) | Input CAHBLTILIL is unused
@N:CL201 : coreahblite_slavearbiter.vhd(173) | Trying to extract state machine for register CAHBLTo0ol
Extracted state machine for register CAHBLTo0ol
State machine has 8 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
   111
@W:CL246 : coreahblite_initcfg_awrap.vhd(17) | Input port bits 31 to 12 of cahblti0ol(31 downto 0) are unused 
@W:CL247 : coreahblite_initcfg_awrap.vhd(21) | Input port bit 0 of cahblti1ol(1 downto 0) is unused 
@W:CL159 : coreahblite_initcfg.vhd(20) | Input CAHBLTo0l0 is unused
@W:CL159 : coreahblite_initcfg.vhd(21) | Input CAHBLTL0L0 is unused
@W:CL159 : coreahblite_matrix2x16.vhd(216) | Input HRDATA_SHG is unused
@W:CL159 : coreahblite_matrix2x16.vhd(217) | Input HREADYOUT_SHG is unused
@W:CL159 : coreahblite_matrix2x16.vhd(218) | Input HRESP_SHG is unused
@W:CL247 : coreahblite.vhd(89) | Input port bit 0 of htrans_m0(1 downto 0) is unused 
@W:CL247 : coreahblite.vhd(100) | Input port bit 0 of htrans_m1(1 downto 0) is unused 
@W:CL247 : coreahblite.vhd(110) | Input port bit 1 of hresp_s0(1 downto 0) is unused 
@W:CL247 : coreahblite.vhd(123) | Input port bit 1 of hresp_s1(1 downto 0) is unused 
@W:CL247 : coreahblite.vhd(136) | Input port bit 1 of hresp_s2(1 downto 0) is unused 
@W:CL247 : coreahblite.vhd(149) | Input port bit 1 of hresp_s3(1 downto 0) is unused 
@W:CL247 : coreahblite.vhd(162) | Input port bit 1 of hresp_s4(1 downto 0) is unused 
@W:CL247 : coreahblite.vhd(175) | Input port bit 1 of hresp_s5(1 downto 0) is unused 
@W:CL247 : coreahblite.vhd(188) | Input port bit 1 of hresp_s6(1 downto 0) is unused 
@W:CL247 : coreahblite.vhd(201) | Input port bit 1 of hresp_s7(1 downto 0) is unused 
@W:CL247 : coreahblite.vhd(214) | Input port bit 1 of hresp_s8(1 downto 0) is unused 
@W:CL247 : coreahblite.vhd(227) | Input port bit 1 of hresp_s9(1 downto 0) is unused 
@W:CL247 : coreahblite.vhd(240) | Input port bit 1 of hresp_s10(1 downto 0) is unused 
@W:CL247 : coreahblite.vhd(253) | Input port bit 1 of hresp_s11(1 downto 0) is unused 
@W:CL247 : coreahblite.vhd(266) | Input port bit 1 of hresp_s12(1 downto 0) is unused 
@W:CL247 : coreahblite.vhd(279) | Input port bit 1 of hresp_s13(1 downto 0) is unused 
@W:CL247 : coreahblite.vhd(292) | Input port bit 1 of hresp_s14(1 downto 0) is unused 
@W:CL247 : coreahblite.vhd(305) | Input port bit 1 of hresp_s15(1 downto 0) is unused 
@W:CL247 : coreahblite.vhd(318) | Input port bit 1 of hresp_shg(1 downto 0) is unused 
@W:CL159 : coreahblite.vhd(92) | Input HBURST_M0 is unused
@W:CL159 : coreahblite.vhd(93) | Input HPROT_M0 is unused
@W:CL159 : coreahblite.vhd(103) | Input HBURST_M1 is unused
@W:CL159 : coreahblite.vhd(104) | Input HPROT_M1 is unused
@N:CL201 : CoreAHB2APB.vhd(299) | Trying to extract state machine for register COREAHB2APB_o0i
Extracted state machine for register COREAHB2APB_o0i
State machine has 8 reachable states with original encodings of:
   0000
   0001
   0100
   1001
   1010
   1011
   1110
   1111
@W:CL247 : CoreAHB2APB.vhd(7) | Input port bit 0 of htrans(1 downto 0) is unused 
@N:CL201 : corei2creal.vhd(1644) | Trying to extract state machine for register CI2Col0L
Extracted state machine for register CI2Col0L
State machine has 7 reachable states with original encodings of:
   0000001
   0000010
   0000100
   0001000
   0010000
   0100000
   1000000
@N:CL201 : corei2creal.vhd(1514) | Trying to extract state machine for register CI2Cli0l
Extracted state machine for register CI2Cli0l
State machine has 7 reachable states with original encodings of:
   0000001
   0000010
   0000100
   0001000
   0010000
   0100000
   1000000
@N:CL201 : corei2creal.vhd(1051) | Trying to extract state machine for register CI2CiL0L
Extracted state machine for register CI2CiL0L
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
@W:CL159 : corei2creal.vhd(30) | Input pulSE_215us is unused
@W:CL159 : corei2creal.vhd(33) | Input serADR1APb0 is unused
@W:CL159 : corei2creal.vhd(47) | Input smbaleRT_NI is unused
@W:CL159 : corei2creal.vhd(49) | Input Smbsus_nI is unused
@W:CL159 : corei2c.vhd(30) | Input bclk is unused
@W:CL247 : ahbwrapper_sram.vhd(8) | Input port bit 0 of htrans(1 downto 0) is unused 
@N:CL201 : sramctrl.vhd(93) | Trying to extract state machine for register COReAhbSram_l00
Extracted state machine for register COReAhbSram_l00
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@W:CL247 : sramctrl.vhd(11) | Input port bit 2 of coreahbsram_o1(2 downto 0) is unused 
@W:CL246 : Sram_512to8192x8_fusion.vhd(8) | Input port bits 12 to 11 of coreahbsram_iii(12 downto 0) are unused 
@W:CL246 : Sram_512to8192x8_fusion.vhd(11) | Input port bits 12 to 11 of coreahbsram_o0i(12 downto 0) are unused 
@N:CL201 : coreahbnvm_ahbwrapper.vhd(159) | Trying to extract state machine for register CAHBNVMi1i
Extracted state machine for register CAHBNVMi1i
State machine has 3 reachable states with original encodings of:
   001
   010
   100
@W:CL247 : coreahbnvm_ahbwrapper.vhd(19) | Input port bit 0 of htrans(1 downto 0) is unused 
@N:CL201 : coreahbnvm_nvmctrl.vhd(771) | Trying to extract state machine for register CAHBNVMio0i
Extracted state machine for register CAHBNVMio0i
State machine has 27 reachable states with original encodings of:
   000000000000000000000000001
   000000000000000000000000010
   000000000000000000000000100
   000000000000000000000001000
   000000000000000000000010000
   000000000000000000000100000
   000000000000000000001000000
   000000000000000000010000000
   000000000000000000100000000
   000000000000000001000000000
   000000000000000010000000000
   000000000000000100000000000
   000000000000001000000000000
   000000000000010000000000000
   000000000000100000000000000
   000000000001000000000000000
   000000000010000000000000000
   000000000100000000000000000
   000000001000000000000000000
   000000010000000000000000000
   000000100000000000000000000
   000001000000000000000000000
   000010000000000000000000000
   000100000000000000000000000
   001000000000000000000000000
   010000000000000000000000000
   100000000000000000000000000
@W:CL159 : coreahbnvm_nvmctrl.vhd(17) | Input HWRITE is unused
@W:CL159 : coreahbnvm_nvmctrl.vhd(21) | Input CAHBNVMol is unused
@W:CL159 : ResetSync_fusion.vhd(26) | Input RV_NTRST is unused
@W:CL159 : ResetSync_fusion.vhd(27) | Input RV_TDI is unused
@W:CL159 : ResetSync_fusion.vhd(28) | Input RV_TMS is unused
@W:CL159 : ResetSync_fusion.vhd(29) | Input RV_TCK is unused
@W:CL159 : ResetSync_fusion.vhd(32) | Input RV_NSRST_IN is unused
@W:CL159 : ResetSync_fusion.vhd(33) | Input RV_DBGRQ is unused
@W:CL247 : CortexM1Top_fusion.vhd(89) | Input port bit 1 of hresp(1 downto 0) is unused 
@W:CL159 : CortexM1Top_fusion.vhd(45) | Input PORESETN is unused
@N:CL134 : coregpio.vhd(479) | Found RAM CGPIOOI, depth=32, width=8
@N:CL201 : Tx_async.vhd(108) | Trying to extract state machine for register CUARTOI1I
Extracted state machine for register CUARTOI1I
State machine has 7 reachable states with original encodings of:
   00000000000000000000000000000000
   00000000000000000000000000000001
   00000000000000000000000000000010
   00000000000000000000000000000011
   00000000000000000000000000000100
   00000000000000000000000000000101
   00000000000000000000000000000110
@W:CL159 : Tx_async.vhd(16) | Input CUARTO0L is unused
@W:CL159 : Tx_async.vhd(17) | Input CUARTl0l is unused
@W:CL190 : Rx_async.vhd(192) | Optimizing register bit CUARTLLII to a constant 0
@W:CL169 : Rx_async.vhd(192) | Pruning Register CUARTLLII  
@W:CL190 : Rx_async.vhd(152) | Optimizing register bit CUARTl0ii to a constant 0
@W:CL169 : Rx_async.vhd(152) | Pruning Register CUARTl0ii  
@N:CL201 : Rx_async.vhd(192) | Trying to extract state machine for register CUARTo11
Extracted state machine for register CUARTo11
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@W:CL159 : Rx_async.vhd(19) | Input CUARTO1 is unused
@N:CL201 : CoreUART.vhd(325) | Trying to extract state machine for register CUARTo11
Extracted state machine for register CUARTo11
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W:CL246 : CoreUARTapb.vhd(22) | Input port bits 1 to 0 of paddr(4 downto 0) are unused 
@END
Process took 0h:00m:08s realtime, 0h:00m:08s cputime
# Fri Aug 20 18:00:33 2010

###########################################################]
Synopsys Actel Technology Mapper, Version map500act, Build 058R, Built Jan 18 2010 09:16:23
Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved
Product Version D-2009.12A
Reading constraint file: E:\sathish\Fusion_M1webserver_Demo\constraint\M1Webserver_HW_v3_1.sdc
Adding property syn_global_buffers, value 12 to view:work.M1webserver_TOP(def_arch)
@N:MF249 :  | Running in 32-bit mode. 
@N:MF258 :  | Gated clock conversion disabled  

Automatic dissolve during optimization of view:core10100_ahbapb_lib.core10100_Ahbapb(cmaciol) of CMACi0110L(DUALRamZ0)
Automatic dissolve during optimization of view:core10100_ahbapb_lib.core10100_Ahbapb(cmaciol) of CMACl0110l(DUALRamZ1)
Automatic dissolve during optimization of view:core10100_ahbapb_lib.core10100_Ahbapb(cmaciol) of CMACLI110L\.CMACII110L(DUALRamZ2)
Automatic dissolve during optimization of view:work.i2c_top(i2c_top_arc) of I2CINT0(I2C_0)
Automatic dissolve during optimization of view:work.M1webserver_TOP(def_arch) of CoreAHBLite_0(CoreAHBLITE)
Automatic dissolve during optimization of view:work.M1webserver_TOP(def_arch) of CoreAPB_0(COREAPB)
@W:MO129 : coregpio.vhd(319) | Sequential instance CGPIOiOI.0.CGPIOI1[0] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.1.CGPIOI1[1] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.2.CGPIOI1[2] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.3.CGPIOI1[3] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.6.CGPIOI1[6] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.7.CGPIOI1[7] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.8.CGPIOI1[8] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.9.CGPIOI1[9] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.10.CGPIOI1[10] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.11.CGPIOI1[11] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.12.CGPIOI1[12] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.13.CGPIOI1[13] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.14.CGPIOI1[14] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.15.CGPIOI1[15] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.16.CGPIOI1[16] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.17.CGPIOI1[17] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.18.CGPIOI1[18] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.19.CGPIOI1[19] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.20.CGPIOI1[20] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.21.CGPIOI1[21] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.22.CGPIOI1[22] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.23.CGPIOI1[23] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.24.CGPIOI1[24] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.25.CGPIOI1[25] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.26.CGPIOI1[26] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.27.CGPIOI1[27] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.28.CGPIOI1[28] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.29.CGPIOI1[29] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.30.CGPIOI1[30] has been reduced to a combinational gate by constant propagation
@W:MO129 : coregpio.vhd(388) | Sequential instance CGPIOiOI.31.CGPIOI1[31] has been reduced to a combinational gate by constant propagation
Automatic dissolve at startup in view:core10100_ahbapb_lib.MAC(cmaciol) of CMACl000l(CMACLLL0)
Automatic dissolve at startup in view:core10100_ahbapb_lib.core10100_Ahbapb(cmaciol) of CMACi0110L.CMACL1010L\.CMACi1010l(CMACI1LL0)
Automatic dissolve at startup in view:core10100_ahbapb_lib.core10100_Ahbapb(cmaciol) of CMACl0110l.CMACi0010l\.CMACo1010l(CMACL11L0)
Automatic dissolve at startup in view:core10100_ahbapb_lib.core10100_Ahbapb(cmaciol) of CMACLI110L\.CMACII110L.CMACoii10l\.CMACLii10l(CMACoooi0)
Automatic dissolve at startup in view:coreahblite_lib.CAHBLTl0OL(cahbltoiil) of CAHBLToiii(CAHBLTi00)
Automatic dissolve at startup in view:coreahblite_lib.CAHBLTl0OL(cahbltoiil) of CAHBLTILii(CAHBLTO_CAHBLTILii)
@N:BN116 : coreahblite_masterstage.vhd(415) | Removing sequential instance CAHBLTl0li of view:PrimLib.dffre(prim) because there are no references to its outputs 
Automatic dissolve at startup in view:coreahblite_lib.CAHBLTl0OL_CAHBLTllLLLL(cahbltoiil) of CAHBLToiii(CAHBLTi00)
Automatic dissolve at startup in view:coreahblite_lib.CAHBLTl0OL_CAHBLTllLLLL(cahbltoiil) of CAHBLTILii(CAHBLTO_CAHBLTILii)
@N:BN116 : coreahblite_masterstage.vhd(415) | Removing sequential instance CAHBLTl0li of view:PrimLib.dffre(prim) because there are no references to its outputs 
Automatic dissolve at startup in view:coreahblite_lib.CAHBLToil0(cahblti0l0) of CAHBLTl000(CAHBLTol1I)
@N:BN116 : coreahblite_initcfg.vhd(231) | Removing sequential instance CAHBLTo10i[1:0] of view:PrimLib.dffre(prim) because there are no references to its outputs 
@N:BN115 : coreahblite_initcfg.vhd(152) | Removing instance CAHBLTio00 of view:coreahblite_lib.CAHBLTIL1_CAHBLTio00(cahblti01) because there are no references to its outputs 
Automatic dissolve at startup in view:coreahblite_lib.CAHBLTi000(cahblti100) of CAHBLTLIILLl(CAHBLToil0)
Automatic dissolve at startup in view:work.i2c_top(i2c_top_arc) of I2CINT0.COREI2C_0(corei2C)
Automatic dissolve at startup in view:work.CoreAhbSRAm_oii(coreahbsram_oi) of Sram_byte0(CoreAhbSram_OO0)
Automatic dissolve at startup in view:work.CoreAhbSRAm_oii(coreahbsram_oi) of SRAM_byte1(CoreAhbSram_OO0)
Automatic dissolve at startup in view:work.CoreAhbSRAm_oii(coreahbsram_oi) of Sram_bYTE2(CoreAhbSram_OO0)
Automatic dissolve at startup in view:work.CoreAhbSRAm_oii(coreahbsram_oi) of Sram_bYTE3(CoreAhbSram_OO0)
Automatic dissolve at startup in view:work.COREAhbSram(coreahbsram_oi) of COREAHBSRam_i1i(CoreAhbSRAm_oii)
Automatic dissolve at startup in view:coreuartapb_lib.CUARTooi(cuartl0) of CUARToLLI(CUARTioli)
Automatic dissolve at startup in view:coreuartapb_lib.COREUART(cuartl0) of CUARTO0Ol\.CUARTl0ol(CUARTooi)
Automatic dissolve at startup in view:coreuartapb_lib.COREUART(cuartl0) of CUARTliol\.CUARTIIOL(CUARTooi)
Automatic dissolve at startup in view:work.M1webserver_TOP(def_arch) of PLL_sys_0(PLL_sys)
Automatic dissolve at startup in view:work.M1webserver_TOP(def_arch) of i2c_top_0(i2c_top)
Automatic dissolve at startup in view:work.M1webserver_TOP(def_arch) of PHY_MDIO_0(PHY_MDIO)
Automatic dissolve at startup in view:work.M1webserver_TOP(def_arch) of CORE10100_AHBAPB_0(core10100_Ahbapb)
@N:BN116 : core10100_ahbapb.vhd(191) | Removing sequential instance CORE10100_AHBAPB_0.hbusrEQ of view:PrimLib.dffre(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_slavestage.vhd(90) | Removing sequential instance CAHBLTO10i[1:0] of view:PrimLib.dffre(prim) because there are no references to its outputs 
@W:BN132 : resetsync_fusion.vhd(385) | Removing sequential instance CortexM1Top_0.RS.CortexM1ToP_LIL,  because it is equivalent to instance CortexM1Top_0.RS.CorteXM1TOP_oll
@W:BN132 : resetsync_fusion.vhd(366) | Removing sequential instance CortexM1Top_0.RS.CORtexM1Top_llL,  because it is equivalent to instance CortexM1Top_0.RS.WDOGRESN
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.8.CGPIOI1I.CGPIOOLL[8],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.8.CGPIOI1I.CGPIOlll[8]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.18.CGPIOI1I.CGPIOOLL[18],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.18.CGPIOI1I.CGPIOlll[18]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.6.CGPIOI1I.CGPIOOLL[6],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.6.CGPIOI1I.CGPIOlll[6]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.24.CGPIOI1I.CGPIOOLL[24],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.24.CGPIOI1I.CGPIOlll[24]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.0.CGPIOI1I.CGPIOOLL[0],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.0.CGPIOI1I.CGPIOlll[0]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.19.CGPIOI1I.CGPIOOLL[19],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.19.CGPIOI1I.CGPIOlll[19]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.10.CGPIOI1I.CGPIOOLL[10],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.10.CGPIOI1I.CGPIOIOL[10]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.15.CGPIOI1I.CGPIOOLL[15],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.15.CGPIOI1I.CGPIOlll[15]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.28.CGPIOI1I.CGPIOOLL[28],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.28.CGPIOI1I.CGPIOIOL[28]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.9.CGPIOI1I.CGPIOOLL[9],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.9.CGPIOI1I.CGPIOlll[9]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.16.CGPIOI1I.CGPIOOLL[16],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.16.CGPIOI1I.CGPIOlll[16]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.3.CGPIOI1I.CGPIOOLL[3],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.3.CGPIOI1I.CGPIOIOL[3]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.31.CGPIOI1I.CGPIOOLL[31],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.31.CGPIOI1I.CGPIOIOL[31]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.26.CGPIOI1I.CGPIOOLL[26],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.26.CGPIOI1I.CGPIOIOL[26]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.17.CGPIOI1I.CGPIOOLL[17],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.17.CGPIOI1I.CGPIOIOL[17]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.2.CGPIOI1I.CGPIOOLL[2],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.2.CGPIOI1I.CGPIOIOL[2]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.22.CGPIOI1I.CGPIOOLL[22],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.22.CGPIOI1I.CGPIOIOL[22]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.21.CGPIOI1I.CGPIOOLL[21],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.21.CGPIOI1I.CGPIOIOL[21]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.11.CGPIOI1I.CGPIOOLL[11],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.11.CGPIOI1I.CGPIOIOL[11]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.1.CGPIOI1I.CGPIOOLL[1],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.1.CGPIOI1I.CGPIOIOL[1]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.23.CGPIOI1I.CGPIOOLL[23],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.23.CGPIOI1I.CGPIOIOL[23]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.27.CGPIOI1I.CGPIOOLL[27],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.27.CGPIOI1I.CGPIOIOL[27]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.7.CGPIOI1I.CGPIOOLL[7],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.7.CGPIOI1I.CGPIOlll[7]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.25.CGPIOI1I.CGPIOOLL[25],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.25.CGPIOI1I.CGPIOIOL[25]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.12.CGPIOI1I.CGPIOOLL[12],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.12.CGPIOI1I.CGPIOIOL[12]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.20.CGPIOI1I.CGPIOOLL[20],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.20.CGPIOI1I.CGPIOIOL[20]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.29.CGPIOI1I.CGPIOOLL[29],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.29.CGPIOI1I.CGPIOIOL[29]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.13.CGPIOI1I.CGPIOOLL[13],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.13.CGPIOI1I.CGPIOIOL[13]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.14.CGPIOI1I.CGPIOOLL[14],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.14.CGPIOI1I.CGPIOIOL[14]
@W:BN132 : coregpio.vhd(548) | Removing sequential instance CoreGPIO_0.CGPIOiOI.30.CGPIOI1I.CGPIOOLL[30],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.30.CGPIOI1I.CGPIOIOL[30]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.24.CGPIOI1I.CGPIOlll[24],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.24.CGPIOI1I.CGPIOIOL[24]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.0.CGPIOI1I.CGPIOlll[0],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.0.CGPIOI1I.CGPIOIOL[0]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.18.CGPIOI1I.CGPIOlll[18],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.18.CGPIOI1I.CGPIOIOL[18]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.3.CGPIOI1I.CGPIOlll[3],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.3.CGPIOI1I.CGPIOIOL[3]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.6.CGPIOI1I.CGPIOlll[6],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.6.CGPIOI1I.CGPIOIOL[6]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.15.CGPIOI1I.CGPIOlll[15],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.15.CGPIOI1I.CGPIOIOL[15]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.8.CGPIOI1I.CGPIOlll[8],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.8.CGPIOI1I.CGPIOIOL[8]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.9.CGPIOI1I.CGPIOlll[9],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.9.CGPIOI1I.CGPIOIOL[9]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.16.CGPIOI1I.CGPIOlll[16],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.16.CGPIOI1I.CGPIOIOL[16]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.10.CGPIOI1I.CGPIOlll[10],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.10.CGPIOI1I.CGPIOIOL[10]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.28.CGPIOI1I.CGPIOlll[28],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.28.CGPIOI1I.CGPIOIOL[28]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.31.CGPIOI1I.CGPIOlll[31],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.31.CGPIOI1I.CGPIOIOL[31]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.26.CGPIOI1I.CGPIOlll[26],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.26.CGPIOI1I.CGPIOIOL[26]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.17.CGPIOI1I.CGPIOlll[17],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.17.CGPIOI1I.CGPIOIOL[17]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.11.CGPIOI1I.CGPIOlll[11],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.11.CGPIOI1I.CGPIOIOL[11]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.1.CGPIOI1I.CGPIOlll[1],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.1.CGPIOI1I.CGPIOIOL[1]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.21.CGPIOI1I.CGPIOlll[21],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.21.CGPIOI1I.CGPIOIOL[21]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.23.CGPIOI1I.CGPIOlll[23],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.23.CGPIOI1I.CGPIOIOL[23]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.22.CGPIOI1I.CGPIOlll[22],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.22.CGPIOI1I.CGPIOIOL[22]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.27.CGPIOI1I.CGPIOlll[27],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.27.CGPIOI1I.CGPIOIOL[27]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.7.CGPIOI1I.CGPIOlll[7],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.7.CGPIOI1I.CGPIOIOL[7]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.20.CGPIOI1I.CGPIOlll[20],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.20.CGPIOI1I.CGPIOIOL[20]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.29.CGPIOI1I.CGPIOlll[29],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.29.CGPIOI1I.CGPIOIOL[29]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.13.CGPIOI1I.CGPIOlll[13],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.13.CGPIOI1I.CGPIOIOL[13]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.25.CGPIOI1I.CGPIOlll[25],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.25.CGPIOI1I.CGPIOIOL[25]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.14.CGPIOI1I.CGPIOlll[14],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.14.CGPIOI1I.CGPIOIOL[14]
@W:BN132 : coregpio.vhd(528) | Removing sequential instance CoreGPIO_0.CGPIOiOI.30.CGPIOI1I.CGPIOlll[30],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.30.CGPIOI1I.CGPIOIOL[30]
@W:BN132 : coregpio.vhd(508) | Removing sequential instance CoreGPIO_0.CGPIOiOI.2.CGPIOI1I.CGPIOIOL[2],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.2.CGPIOI1I.CGPIOlll[2]
@W:BN132 : coregpio.vhd(508) | Removing sequential instance CoreGPIO_0.CGPIOiOI.12.CGPIOI1I.CGPIOIOL[12],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.12.CGPIOI1I.CGPIOlll[12]
@W:BN132 : coregpio.vhd(508) | Removing sequential instance CoreGPIO_0.CGPIOiOI.19.CGPIOI1I.CGPIOIOL[19],  because it is equivalent to instance CoreGPIO_0.CGPIOiOI.19.CGPIOI1I.CGPIOlll[19]

Available hyper_sources - for debug and ip models
	None Found

@W:MO161 : coregpio.vhd(528) | Register bit CGPIOiOI\.19\.CGPIOI1I\.CGPIOlll[19] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(528) | Register bit CGPIOiOI\.12\.CGPIOI1I\.CGPIOlll[12] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(528) | Register bit CGPIOiOI\.2\.CGPIOI1I\.CGPIOlll[2] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.31\.CGPIOI1I\.CGPIOIOL[31] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.30\.CGPIOI1I\.CGPIOIOL[30] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.29\.CGPIOI1I\.CGPIOIOL[29] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.28\.CGPIOI1I\.CGPIOIOL[28] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.27\.CGPIOI1I\.CGPIOIOL[27] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.26\.CGPIOI1I\.CGPIOIOL[26] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.25\.CGPIOI1I\.CGPIOIOL[25] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.24\.CGPIOI1I\.CGPIOIOL[24] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.23\.CGPIOI1I\.CGPIOIOL[23] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.22\.CGPIOI1I\.CGPIOIOL[22] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.21\.CGPIOI1I\.CGPIOIOL[21] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.20\.CGPIOI1I\.CGPIOIOL[20] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.18\.CGPIOI1I\.CGPIOIOL[18] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.17\.CGPIOI1I\.CGPIOIOL[17] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.16\.CGPIOI1I\.CGPIOIOL[16] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.15\.CGPIOI1I\.CGPIOIOL[15] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.14\.CGPIOI1I\.CGPIOIOL[14] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.13\.CGPIOI1I\.CGPIOIOL[13] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.11\.CGPIOI1I\.CGPIOIOL[11] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.10\.CGPIOI1I\.CGPIOIOL[10] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.9\.CGPIOI1I\.CGPIOIOL[9] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.8\.CGPIOI1I\.CGPIOIOL[8] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.7\.CGPIOI1I\.CGPIOIOL[7] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.6\.CGPIOI1I\.CGPIOIOL[6] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.3\.CGPIOI1I\.CGPIOIOL[3] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.1\.CGPIOI1I\.CGPIOIOL[1] is always 0, optimizing ...
@W:MO161 : coregpio.vhd(508) | Register bit CGPIOiOI\.0\.CGPIOI1I\.CGPIOIOL[0] is always 0, optimizing ...
Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 70MB peak: 72MB)

@N:MF176 :  | Default generator successful  
@N: : dma.vhd(279) | Found counter in view:core10100_ahbapb_lib.CMAClo0(cmaciol) inst CMACilOIL[14:0]
Encoding state machine core10100_ahbapb_lib.CMAClo0(cmaciol)-CMACiooil[0:2]
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
@N:MF238 : dma.vhd(329) | Found 30 bit incrementor, 'un5_cmaco0oil[29:0]'
@N: : tlsm.vhd(1390) | Found counter in view:core10100_ahbapb_lib.CMACil0l(cmaciol) inst CMAClloo0[5:0]
Encoding state machine core10100_ahbapb_lib.CMACil0l(cmaciol)-CMACO1oli[0:8]
original code -> new code
   00000000001 -> 000000001
   00000000100 -> 000000010
   00000001000 -> 000000100
   00000010000 -> 000001000
   00000100000 -> 000010000
   00001000000 -> 000100000
   00010000000 -> 001000000
   00100000000 -> 010000000
   10000000000 -> 100000000
Encoding state machine core10100_ahbapb_lib.CMACil0l(cmaciol)-CMACio01i[0:6]
original code -> new code
   0000001 -> 0000001
   0000010 -> 0000010
   0000100 -> 0000100
   0001000 -> 0001000
   0010000 -> 0010000
   0100000 -> 0100000
   1000000 -> 1000000
@N:MF176 :  | Default generator successful  
@N:MF176 :  | Default generator successful  
@N:MF179 : tlsm.vhd(1151) | Found 9 bit by 9 bit '<' comparator, 'CMACl10li\.un1_cmacll0li_1'
@N:MF179 : tlsm.vhd(1156) | Found 10 bit by 10 bit '<' comparator, 'CMACl10li\.un2_cmacoo0l'
@N:MF179 : tlsm.vhd(1146) | Found 10 bit by 10 bit '<' comparator, 'CMACl10li\.un1_cmacll0li'
@N:MF176 :  | Default generator successful  
@N:MF238 : tfifo.vhd(376) | Found 9 bit incrementor, 'un2_cmacoi10l[8:0]'
@N:MF179 : tfifo.vhd(509) | Found 9 bit by 9 bit '<' comparator, 'CMACioi1i\.un1_CMACoi10I'
@N:MF179 : tfifo.vhd(486) | Found 9 bit by 9 bit '<' comparator, 'CMACooI1I\.un1_CMACiooi'
@N: : tc.vhd(524) | Found counter in view:core10100_ahbapb_lib.CMACoioi(cmaciol) inst CMACoIO1L[3:0]
Encoding state machine core10100_ahbapb_lib.CMACoioi(cmaciol)-CMACil0II[0:8]
original code -> new code
   0000000001 -> 000000001
   0000000010 -> 000000010
   0000000100 -> 000000100
   0000001000 -> 000001000
   0000010000 -> 000010000
   0000100000 -> 000100000
   0010000000 -> 001000000
   0100000000 -> 010000000
   1000000000 -> 100000000
@N:MF239 : tc.vhd(909) | Found 8 bit decrementor, 'un5_cmaci1ool[7:0]'
@N: : bd.vhd(120) | Found counter in view:core10100_ahbapb_lib.CMACo(cmaciol) inst CMACI0L[8:0]
@N: : bd.vhd(142) | Found counter in view:core10100_ahbapb_lib.CMACo(cmaciol) inst CMACl0l[9:0]
@N: : bd.vhd(186) | Found counter in view:core10100_ahbapb_lib.CMACo(cmaciol) inst CMACO0L[3:0]
@N: : rc.vhd(1022) | Found counter in view:core10100_ahbapb_lib.CMACi00I(cmaciol) inst CMACioI1L[2:0]
@N: : rc.vhd(709) | Found counter in view:core10100_ahbapb_lib.CMACi00I(cmaciol) inst CMACLLL1l[13:0]
@N: : rc.vhd(1142) | Found counter in view:core10100_ahbapb_lib.CMACi00I(cmaciol) inst CMACo0i1l[15:0]
@N: : rc.vhd(1109) | Found counter in view:core10100_ahbapb_lib.CMACi00I(cmaciol) inst CMAClii1l[10:0]
@N: : rc.vhd(285) | Found counter in view:core10100_ahbapb_lib.CMACi00I(cmaciol) inst CMACOI10L[9:0]
@N: : rc.vhd(492) | Found counter in view:core10100_ahbapb_lib.CMACi00I(cmaciol) inst CMACoio1L[2:0]
Encoding state machine core10100_ahbapb_lib.CMACi00I(cmaciol)-CMACL0L1L[0:5]
original code -> new code
   000001 -> 000001
   000010 -> 000010
   000100 -> 000100
   001000 -> 001000
   010000 -> 010000
   100000 -> 100000
@N:BN116 : rc.vhd(1007) | Removing sequential instance CMACl1l1l of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(1007) | Boundary register CMACl1l1l has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(1007) | Removing sequential instance CMACo1l1l of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(1007) | Boundary register CMACo1l1l has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(980) | Removing sequential instance CMACooi1l of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(980) | Boundary register CMACooi1l has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(980) | Removing sequential instance CMACLLI1l[15:0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(980) | Boundary register CMACLLI1l[15:0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
Encoding state machine core10100_ahbapb_lib.CMACi00I(cmaciol)-CMACilo1l[0:9]
original code -> new code
   0000000001 -> 0000000001
   0000000010 -> 0000000010
   0000000100 -> 0000000100
   0000001000 -> 0000001000
   0000010000 -> 0000010000
   0000100000 -> 0000100000
   0001000000 -> 0001000000
   0010000000 -> 0010000000
   0100000000 -> 0100000000
   1000000000 -> 1000000000
@N:MF239 : rc.vhd(1091) | Found 8 bit decrementor, 'un5_cmacioool[7:0]'
@N:MF238 : rc.vhd(1029) | Found 6 bit incrementor, 'un14_cmacoli1l[5:0]'
@W:MO161 : rc.vhd(429) | Register bit CMACL0L1L[0] is always 0, optimizing ...
@N:BN116 : rc.vhd(980) | Removing sequential instance CMACi1l1l[3] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(980) | Boundary register CMACi1l1l[3] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(980) | Removing sequential instance CMACi1l1l[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(980) | Boundary register CMACi1l1l[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(980) | Removing sequential instance CMACi1l1l[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(980) | Boundary register CMACi1l1l[1] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(980) | Removing sequential instance CMACi1l1l[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(980) | Boundary register CMACi1l1l[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:MF135 : rfifo.vhd(113) | Found RAM, 'CMAColioi[22:0]', 4 words by 23 bits 
@N:MF135 : rfifo.vhd(113) | Found RAM, 'CMAColioi[22:0]', 4 words by 23 bits 
@N:BN116 : rfifo.vhd(113) | Removing sequential instance CMAColioi[22:0] of view:PrimLib.ram1(prim) because there are no references to its outputs 
@N:MF184 : rfifo.vhd(295) | Found 10 by 10 bit subtractor, 'CMACILOoi\.CMACiooi_2_0_0[9:0]'
@N:MF176 :  | Default generator successful  
@N:MF238 : rfifo.vhd(235) | Found 10 bit incrementor, 'un3_cmacl1ioi[9:0]'
@N: : rlsm.vhd(743) | Found counter in view:core10100_ahbapb_lib.CMACL1O0(cmaciol) inst CMACo1ili[13:2]
Encoding state machine core10100_ahbapb_lib.CMACL1O0(cmaciol)-CMACo1oli[0:10]
original code -> new code
   00000000001 -> 00000000001
   00000000010 -> 00000000010
   00000000100 -> 00000000100
   00000001000 -> 00000001000
   00000010000 -> 00000010000
   00000100000 -> 00000100000
   00001000000 -> 00001000000
   00010000000 -> 00010000000
   00100000000 -> 00100000000
   01000000000 -> 01000000000
   10000000000 -> 10000000000
@N:MF176 :  | Default generator successful  
@N:MF239 : rlsm.vhd(542) | Found 9 bit decrementor, 'un10_cmacl1o1l[8:0]'
@N:MF176 :  | Default generator successful  
@N:MF179 : rlsm.vhd(236) | Found 12 bit by 12 bit '<' comparator, 'CMACL10LI\.un1_CMACi0ili_1'
@N:MF179 : rlsm.vhd(753) | Found 14 bit by 14 bit '<' comparator, 'CMACOILIi\.un1_CMACo1ili'
@N:MF179 : rlsm.vhd(211) | Found 12 bit by 12 bit '<' comparator, 'CMACL10LI\.un1_CMACi0ili'
@N:MF238 : rlsm.vhd(236) | Found 6 bit incrementor, 'un2_cmacoo0l[9:15]'
@N:MF179 : rlsm.vhd(241) | Found 9 bit by 9 bit '<' comparator, 'CMACL10LI\.un2_cmacoo0l'
@N:BN116 : rlsm.vhd(200) | Removing sequential instance CMACi1ILI[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : rlsm.vhd(200) | Removing sequential instance CMACi1ILI[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N: : csr.vhd(1734) | Found counter in view:core10100_ahbapb_lib.CMACI0oi(cmaciol) inst CMACIILOl[15:0]
@N: : csr.vhd(1191) | Found counter in view:core10100_ahbapb_lib.CMACI0oi(cmaciol) inst CMACo0OOL[7:0]
@N: : csr.vhd(1487) | Found counter in view:core10100_ahbapb_lib.CMACI0oi(cmaciol) inst CMACilool[3:0]
@N: : csr.vhd(1487) | Found counter in view:core10100_ahbapb_lib.CMACI0oi(cmaciol) inst CMACoIOOL[2:0]
@N: : csr.vhd(1191) | Found counter in view:core10100_ahbapb_lib.CMACI0oi(cmaciol) inst CMACL0Ool[2:0]
@N: : csr.vhd(1522) | Found counter in view:core10100_ahbapb_lib.CMACI0oi(cmaciol) inst CMACiooOL[3:0]
@N: : csr.vhd(1228) | Found counter in view:core10100_ahbapb_lib.CMACI0oi(cmaciol) inst CMACI1Ool[3:0]
@N: : csr.vhd(1156) | Found counter in view:core10100_ahbapb_lib.CMACI0oi(cmaciol) inst CMACloi1[2:0]
Encoding state machine core10100_ahbapb_lib.CMACI0oi(cmaciol)-CMACo1i1[0:2]
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine core10100_ahbapb_lib.CMACI0oi(cmaciol)-CMACLli1[0:2]
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine corememctrl_lib.COREMEMCtrl(corememctrl_o)-corememctrl_O0I[0:5]
original code -> new code
   0000 -> 000001
   0001 -> 000010
   0010 -> 000100
   0011 -> 001000
   0100 -> 010000
   0101 -> 100000
@W:MO161 : coreahblite_masterstage.vhd(405) | Register bit CAHBLTIO1L[16] is always 0, optimizing ...
@W:MO161 : coreahblite_masterstage.vhd(405) | Register bit CAHBLTIO1L[16] is always 0, optimizing ...
@W:MO161 : coreahblite_masterstage.vhd(346) | Register bit CAHBLToi0l[2] is always 0, optimizing ...
@W:MO161 : coreahblite_masterstage.vhd(346) | Register bit CAHBLToi0l[0] is always 0, optimizing ...
Encoding state machine coreahblite_lib.CAHBLTIL1_CAHBLTIO1I_0_CAHBLTIO1I(cahblti01)-CAHBLTo0ol[0:7]
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
@W:MO161 : coreahblite_slavearbiter.vhd(160) | Register bit CAHBLTo0ol[0] is always 0, optimizing ...
Encoding state machine coreahblite_lib.CAHBLTIL1_CAHBLTIO1I_0_CAHBLTIO1I_0(cahblti01)-CAHBLTo0ol[0:7]
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
@W:MO161 : coreahblite_slavearbiter.vhd(160) | Register bit CAHBLTo0ol[0] is always 0, optimizing ...
Encoding state machine coreahblite_lib.CAHBLTIL1_CAHBLTIO1I_0_CAHBLTIO1I_1_CAHBLTIO1I(cahblti01)-CAHBLTo0ol[0:7]
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
@W:MO161 : coreahblite_slavearbiter.vhd(160) | Register bit CAHBLTo0ol[0] is always 0, optimizing ...
Encoding state machine coreahblite_lib.CAHBLTIL1_CAHBLTIO1I_CAHBLTIO1I_0(cahblti01)-CAHBLTo0ol[0:7]
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
@W:MO129 : coreahblite_slavearbiter.vhd(109) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTiilllL.CAHBLTIO1I.CAHBLTo0ol[6] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(116) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTiilllL.CAHBLTIO1I.CAHBLTo0ol[5] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(138) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTiilllL.CAHBLTIO1I.CAHBLTo0ol[1] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(160) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTiilllL.CAHBLTIO1I.CAHBLTo0ol[0] has been reduced to a combinational gate by constant propagation
Encoding state machine coreahblite_lib.CAHBLTIL1_CAHBLTIO1I_CAHBLTIO1I_1(cahblti01)-CAHBLTo0ol[0:7]
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
@W:MO129 : coreahblite_slavearbiter.vhd(109) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTo0llll.CAHBLTIO1I.CAHBLTo0ol[6] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(116) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTo0llll.CAHBLTIO1I.CAHBLTo0ol[5] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(138) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTo0llll.CAHBLTIO1I.CAHBLTo0ol[1] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(160) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTo0llll.CAHBLTIO1I.CAHBLTo0ol[0] has been reduced to a combinational gate by constant propagation
Encoding state machine coreahblite_lib.CAHBLTIL1_CAHBLTIO1I_CAHBLTIO1I_2(cahblti01)-CAHBLTo0ol[0:7]
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
@W:MO129 : coreahblite_slavearbiter.vhd(109) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTL0llll.CAHBLTIO1I.CAHBLTo0ol[6] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(116) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTL0llll.CAHBLTIO1I.CAHBLTo0ol[5] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(138) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTL0llll.CAHBLTIO1I.CAHBLTo0ol[1] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(160) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTL0llll.CAHBLTIO1I.CAHBLTo0ol[0] has been reduced to a combinational gate by constant propagation
Encoding state machine coreahblite_lib.CAHBLTIL1_CAHBLTIO1I_CAHBLTIO1I_3(cahblti01)-CAHBLTo0ol[0:7]
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
@W:MO129 : coreahblite_slavearbiter.vhd(109) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTi0llll.CAHBLTIO1I.CAHBLTo0ol[6] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(116) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTi0llll.CAHBLTIO1I.CAHBLTo0ol[5] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(138) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTi0llll.CAHBLTIO1I.CAHBLTo0ol[1] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(160) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTi0llll.CAHBLTIO1I.CAHBLTo0ol[0] has been reduced to a combinational gate by constant propagation
Encoding state machine coreahblite_lib.CAHBLTIL1_CAHBLTIO1I_CAHBLTIO1I_4(cahblti01)-CAHBLTo0ol[0:7]
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
@W:MO129 : coreahblite_slavearbiter.vhd(109) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTo1llll.CAHBLTIO1I.CAHBLTo0ol[6] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(116) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTo1llll.CAHBLTIO1I.CAHBLTo0ol[5] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(138) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTo1llll.CAHBLTIO1I.CAHBLTo0ol[1] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(160) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTo1llll.CAHBLTIO1I.CAHBLTo0ol[0] has been reduced to a combinational gate by constant propagation
Encoding state machine coreahblite_lib.CAHBLTIL1_CAHBLTIO1I_CAHBLTIO1I_5(cahblti01)-CAHBLTo0ol[0:7]
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
@W:MO129 : coreahblite_slavearbiter.vhd(109) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTL1llll.CAHBLTIO1I.CAHBLTo0ol[6] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(116) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTL1llll.CAHBLTIO1I.CAHBLTo0ol[5] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(138) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTL1llll.CAHBLTIO1I.CAHBLTo0ol[1] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(160) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTL1llll.CAHBLTIO1I.CAHBLTo0ol[0] has been reduced to a combinational gate by constant propagation
Encoding state machine coreahblite_lib.CAHBLTIL1_CAHBLTIO1I_CAHBLTIO1I_6(cahblti01)-CAHBLTo0ol[0:7]
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
@W:MO129 : coreahblite_slavearbiter.vhd(109) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTI1LLll.CAHBLTIO1I.CAHBLTo0ol[6] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(116) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTI1LLll.CAHBLTIO1I.CAHBLTo0ol[5] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(138) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTI1LLll.CAHBLTIO1I.CAHBLTo0ol[1] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(160) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTI1LLll.CAHBLTIO1I.CAHBLTo0ol[0] has been reduced to a combinational gate by constant propagation
Encoding state machine coreahblite_lib.CAHBLTIL1_CAHBLTIO1I_CAHBLTIO1I_7(cahblti01)-CAHBLTo0ol[0:7]
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
@W:MO129 : coreahblite_slavearbiter.vhd(109) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTooilll.CAHBLTIO1I.CAHBLTo0ol[6] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(116) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTooilll.CAHBLTIO1I.CAHBLTo0ol[5] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(138) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTooilll.CAHBLTIO1I.CAHBLTo0ol[1] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(160) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTooilll.CAHBLTIO1I.CAHBLTo0ol[0] has been reduced to a combinational gate by constant propagation
Encoding state machine coreahblite_lib.CAHBLTIL1_CAHBLTIO1I_CAHBLTIO1I_8(cahblti01)-CAHBLTo0ol[0:7]
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
@W:MO129 : coreahblite_slavearbiter.vhd(109) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTlOILLL.CAHBLTIO1I.CAHBLTo0ol[6] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(116) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTlOILLL.CAHBLTIO1I.CAHBLTo0ol[5] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(138) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTlOILLL.CAHBLTIO1I.CAHBLTo0ol[1] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(160) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTlOILLL.CAHBLTIO1I.CAHBLTo0ol[0] has been reduced to a combinational gate by constant propagation
Encoding state machine coreahblite_lib.CAHBLTIL1_CAHBLTIO1I_0_CAHBLTIO1I_1_CAHBLTIO1I_0(cahblti01)-CAHBLTo0ol[0:7]
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
@W:MO161 : coreahblite_slavearbiter.vhd(160) | Register bit CAHBLTo0ol[0] is always 0, optimizing ...
Encoding state machine coreahblite_lib.CAHBLTIL1_CAHBLTIO1I_CAHBLTIO1I_9(cahblti01)-CAHBLTo0ol[0:7]
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
@W:MO129 : coreahblite_slavearbiter.vhd(109) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolilll.CAHBLTIO1I.CAHBLTo0ol[6] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(116) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolilll.CAHBLTIO1I.CAHBLTo0ol[5] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(138) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolilll.CAHBLTIO1I.CAHBLTo0ol[1] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(160) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolilll.CAHBLTIO1I.CAHBLTo0ol[0] has been reduced to a combinational gate by constant propagation
Encoding state machine coreahblite_lib.CAHBLTIL1_CAHBLTIO1I_CAHBLTIO1I_10(cahblti01)-CAHBLTo0ol[0:7]
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
@W:MO129 : coreahblite_slavearbiter.vhd(109) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllilll.CAHBLTIO1I.CAHBLTo0ol[6] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(116) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllilll.CAHBLTIO1I.CAHBLTo0ol[5] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(138) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllilll.CAHBLTIO1I.CAHBLTo0ol[1] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(160) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllilll.CAHBLTIO1I.CAHBLTo0ol[0] has been reduced to a combinational gate by constant propagation
Encoding state machine coreahblite_lib.CAHBLTIL1_CAHBLTIO1I_CAHBLTIO1I_11(cahblti01)-CAHBLTo0ol[0:7]
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
@W:MO129 : coreahblite_slavearbiter.vhd(109) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTilILLL.CAHBLTIO1I.CAHBLTo0ol[6] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(116) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTilILLL.CAHBLTIO1I.CAHBLTo0ol[5] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(138) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTilILLL.CAHBLTIO1I.CAHBLTo0ol[1] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(160) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTilILLL.CAHBLTIO1I.CAHBLTo0ol[0] has been reduced to a combinational gate by constant propagation
Encoding state machine coreahblite_lib.CAHBLTIL1_CAHBLTIO1I_CAHBLTIO1I(cahblti01)-CAHBLTo0ol[0:7]
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
@N:BN116 : coreahblite_slavearbiter.vhd(145) | Removing sequential instance CAHBLTo0ol[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_slavearbiter.vhd(123) | Removing sequential instance CAHBLTo0ol[3] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_slavearbiter.vhd(83) | Removing sequential instance CAHBLTo0ol[4] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_slavearbiter.vhd(57) | Removing sequential instance CAHBLTo0ol[7] of view:PrimLib.dffs(prim) because there are no references to its outputs 
@W:MO129 : coreahblite_slavearbiter.vhd(109) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTOIIlll.CAHBLTIO1I.CAHBLTo0ol[6] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(116) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTOIIlll.CAHBLTIO1I.CAHBLTo0ol[5] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(138) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTOIIlll.CAHBLTIO1I.CAHBLTo0ol[1] has been reduced to a combinational gate by constant propagation
@W:MO129 : coreahblite_slavearbiter.vhd(160) | Sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTOIIlll.CAHBLTIO1I.CAHBLTo0ol[0] has been reduced to a combinational gate by constant propagation
Encoding state machine work.COREAHB2APB(coreahb2apb_o)-COREAHB2APB_o0i[0:7]
original code -> new code
   0000 -> 00000001
   0001 -> 00000010
   0100 -> 00000100
   1001 -> 00001000
   1010 -> 00010000
   1011 -> 00100000
   1110 -> 01000000
   1111 -> 10000000
@N: : corei2creal.vhd(835) | Found counter in view:corei2c_lib.cOREI2creal(rtl) inst CI2CoilI[3:0]
@N: : corei2creal.vhd(919) | Found counter in view:corei2c_lib.cOREI2creal(rtl) inst CI2CiiLI[3:0]
@N: : corei2creal.vhd(770) | Found counter in view:corei2c_lib.cOREI2creal(rtl) inst CI2CIoii[3:0]
@N:MO106 : corei2creal.vhd(496) | Found ROM, 'CI2CII0I\.CI2CIL1l_30[4:0]', 28 words by 5 bits 
Encoding state machine corei2c_lib.cOREI2creal(rtl)-CI2CiL0L[0:7]
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine corei2c_lib.cOREI2creal(rtl)-CI2Col0L[0:6]
original code -> new code
   0000001 -> 0000001
   0000010 -> 0000010
   0000100 -> 0000100
   0001000 -> 0001000
   0010000 -> 0010000
   0100000 -> 0100000
   1000000 -> 1000000
Encoding state machine corei2c_lib.cOREI2creal(rtl)-CI2Cli0l[0:6]
original code -> new code
   0000001 -> 0000001
   0000010 -> 0000010
   0000100 -> 0000100
   0001000 -> 0001000
   0010000 -> 0010000
   0100000 -> 0100000
   1000000 -> 1000000
@N:MF176 :  | Default generator successful  
Encoding state machine work.CoreAhbSram_L1(coreahbsram_oi)-COReAhbSram_l00[0:2]
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine coreahbnvm_lib.CAHBNVMo(cahbnvmii)-CAHBNVMi1i[0:2]
original code -> new code
   001 -> 00
   010 -> 01
   100 -> 10
@N: : coreahbnvm_nvmctrl.vhd(931) | Found counter in view:coreahbnvm_lib.CAHBNVMlo0(cahbnvmioll) inst CAHBNVMILII[7:0]
Encoding state machine coreahbnvm_lib.CAHBNVMlo0(cahbnvmioll)-CAHBNVMio0i[0:26]
original code -> new code
   000000000000000000000000001 -> 00000
   000000000000000000000000010 -> 00001
   000000000000000000000000100 -> 00011
   000000000000000000000001000 -> 00010
   000000000000000000000010000 -> 00110
   000000000000000000000100000 -> 00111
   000000000000000000001000000 -> 00101
   000000000000000000010000000 -> 00100
   000000000000000000100000000 -> 01100
   000000000000000001000000000 -> 01101
   000000000000000010000000000 -> 01111
   000000000000000100000000000 -> 01110
   000000000000001000000000000 -> 01010
   000000000000010000000000000 -> 01011
   000000000000100000000000000 -> 01001
   000000000001000000000000000 -> 01000
   000000000010000000000000000 -> 11000
   000000000100000000000000000 -> 11001
   000000001000000000000000000 -> 11011
   000000010000000000000000000 -> 11010
   000000100000000000000000000 -> 11110
   000001000000000000000000000 -> 11111
   000010000000000000000000000 -> 11101
   000100000000000000000000000 -> 11100
   001000000000000000000000000 -> 10100
   010000000000000000000000000 -> 10101
   100000000000000000000000000 -> 10111
@N:MF239 : uj_jtag.vhd(93) | Found 6 bit decrementor, 'un22_cortexm1top_l0ol[5:0]'
@N:MF135 : coregpio.vhd(479) | Found RAM, 'CGPIOOI[7:0]', 32 words by 8 bits 
@N:MF135 : coregpio.vhd(479) | Found RAM, 'CGPIOOI[7:0]', 32 words by 8 bits 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CGPIOOI[7:0] of view:PrimLib.ram1(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CGPIOOI_1[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CGPIOOI_2[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CGPIOOI_3[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CGPIOOI_6[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CGPIOOI_7[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CGPIOOI_0[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
Encoding state machine coreuartapb_lib.COREUART(cuartl0)-CUARTo11[0:3]
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N: : clock_gen.vhd(34) | Found counter in view:coreuartapb_lib.CUARTo(cuartol) inst CUARTLL[12:0]
@N: : clock_gen.vhd(50) | Found counter in view:coreuartapb_lib.CUARTo(cuartol) inst CUARTLI[3:0]
@N: : tx_async.vhd(193) | Found counter in view:coreuartapb_lib.CUARTiil(cuartl0) inst CUARTo01i[3:0]
Encoding state machine coreuartapb_lib.CUARTiil(cuartl0)-CUARTOI1I[0:6]
original code -> new code
   00000000000000000000000000000000 -> 0000001
   00000000000000000000000000000001 -> 0000010
   00000000000000000000000000000010 -> 0000100
   00000000000000000000000000000011 -> 0001000
   00000000000000000000000000000100 -> 0010000
   00000000000000000000000000000101 -> 0100000
   00000000000000000000000000000110 -> 1000000
@N: : rx_async.vhd(241) | Found counter in view:coreuartapb_lib.CUARTi0(cuartl0) inst CUARTLOII[3:0]
@N: : rx_async.vhd(137) | Found counter in view:coreuartapb_lib.CUARTi0(cuartl0) inst CUARTO1Li[3:0]
Encoding state machine coreuartapb_lib.CUARTi0(cuartl0)-CUARTo11[0:2]
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Automatic dissolve during optimization of view:core10100_ahbapb_lib.CMACli1i(cmaciol) of un2_cmacliioi_1(PM_M1webserver_TOP_ADDC__0_2_M1AFS1500_FBGA256_-1)
Automatic dissolve during optimization of view:corememctrl_lib.COREMEMCtrl(corememctrl_o) of corememctrL_O1I_2_1(PM_M1webserver_TOP_ADD__2_2_M1AFS1500_FBGA256_-1)
Automatic dissolve during optimization of view:coreai_lib.COREAI(caio) of un3_cailoli_0_1(PM_M1webserver_TOP_ADDC__0_2_M1AFS1500_FBGA256_-1)
Automatic dissolve during optimization of view:coreahbnvm_lib.CAHBNVMII0I(cahbnvml00i) of CAHBNVMLOl0(CAHBNVMo)
Automatic dissolve during optimization of view:coreahbnvm_lib.COREAHBNVM(cahbnvmoil0) of CAHBNVMLil0(CAHBNVMII0I)
Automatic dissolve during optimization of view:work.M1webserver_TOP(def_arch) of CoreAhbNvm_0(COREAHBNVM)
Finished factoring (Time elapsed 0h:00m:09s; Memory used current: 95MB peak: 95MB)

@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_31[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_31[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_31[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_16[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_16[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_16[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_17[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_17[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_17[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_18[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_18[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_18[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_19[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_19[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_19[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_20[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_20[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_20[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_21[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_21[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_21[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_22[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_22[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_22[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_23[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_23[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_23[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_24[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_24[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_24[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_25[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_25[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_25[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_26[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_26[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_26[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_27[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_27[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_27[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_28[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_28[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_28[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_29[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_29[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_29[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_30[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_30[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_30[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_4[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_4[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_5[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_5[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_6[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_6[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_7[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_7[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_8[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_8[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_8[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_9[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_9[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_9[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_10[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_10[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_10[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_11[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_11[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_11[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_12[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_12[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_12[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_13[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_13[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_13[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_14[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_14[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_14[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_15[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_15[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coregpio.vhd(479) | Removing sequential instance CoreGPIO_0.CGPIOOI_15[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : sramctrl.vhd(101) | Removing sequential instance CoreAhbSram_0.COREAHBSram_l1i.CoREAHBSRAm_lol.COREAHBSram_i10[14] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : sramctrl.vhd(101) | Removing sequential instance CoreAhbSram_0.COREAHBSram_l1i.CoREAHBSRAm_lol.COREAHBSram_i10[13] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : ahbwrapper_sram.vhd(71) | Removing sequential instance CoreAhbSram_0.COREAHBSram_l1i.COREAhbSram_ooL.CoreAhbSraM_I0L[2] of view:PrimLib.dff(prim) because there are no references to its outputs 
@N:BN116 : ahbwrapper_sram.vhd(71) | Removing sequential instance CoreAhbSram_0.COREAHBSram_l1i.COREAhbSram_ooL.CoREAHBSRAm_l0l[14] of view:PrimLib.dff(prim) because there are no references to its outputs 
@N:BN116 : ahbwrapper_sram.vhd(71) | Removing sequential instance CoreAhbSram_0.COREAHBSram_l1i.COREAhbSram_ooL.CoREAHBSRAm_l0l[13] of view:PrimLib.dff(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(219) | Removing sequential instance CoreAHB2APB_0.COREAHB2APB_ili[23] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(219) | Removing sequential instance CoreAHB2APB_0.COREAHB2APB_ili[22] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(219) | Removing sequential instance CoreAHB2APB_0.COREAHB2APB_ili[21] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(219) | Removing sequential instance CoreAHB2APB_0.COREAHB2APB_ili[20] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(219) | Removing sequential instance CoreAHB2APB_0.COREAHB2APB_ili[19] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(219) | Removing sequential instance CoreAHB2APB_0.COREAHB2APB_ili[18] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(219) | Removing sequential instance CoreAHB2APB_0.COREAHB2APB_ili[17] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(219) | Removing sequential instance CoreAHB2APB_0.COREAHB2APB_ili[16] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(219) | Removing sequential instance CoreAHB2APB_0.COREAHB2APB_ili[15] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(219) | Removing sequential instance CoreAHB2APB_0.COREAHB2APB_ili[14] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(219) | Removing sequential instance CoreAHB2APB_0.COREAHB2APB_ili[13] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(219) | Removing sequential instance CoreAHB2APB_0.COREAHB2APB_ili[12] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(219) | Removing sequential instance CoreAHB2APB_0.COREAHB2APB_ili[11] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(219) | Removing sequential instance CoreAHB2APB_0.COREAHB2APB_ili[10] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(219) | Removing sequential instance CoreAHB2APB_0.COREAHB2APB_ili[9] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(499) | Removing sequential instance CoreAHB2APB_0.PADDR[23] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(499) | Removing sequential instance CoreAHB2APB_0.PADDR[22] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(499) | Removing sequential instance CoreAHB2APB_0.PADDR[21] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(499) | Removing sequential instance CoreAHB2APB_0.PADDR[20] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(499) | Removing sequential instance CoreAHB2APB_0.PADDR[19] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(499) | Removing sequential instance CoreAHB2APB_0.PADDR[18] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(499) | Removing sequential instance CoreAHB2APB_0.PADDR[17] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(499) | Removing sequential instance CoreAHB2APB_0.PADDR[16] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(499) | Removing sequential instance CoreAHB2APB_0.PADDR[15] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(499) | Removing sequential instance CoreAHB2APB_0.PADDR[14] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(499) | Removing sequential instance CoreAHB2APB_0.PADDR[13] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(499) | Removing sequential instance CoreAHB2APB_0.PADDR[12] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(499) | Removing sequential instance CoreAHB2APB_0.PADDR[11] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(499) | Removing sequential instance CoreAHB2APB_0.PADDR[10] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahb2apb.vhd(499) | Removing sequential instance CoreAHB2APB_0.PADDR[9] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_initcfg_awrap.vhd(118) | Removing sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTLIILLl.CAHBLTl000.CAHBLTl1O0[15] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_initcfg_awrap.vhd(118) | Removing sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTLIILLl.CAHBLTl000.CAHBLTl1O0[14] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_initcfg_awrap.vhd(118) | Removing sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTLIILLl.CAHBLTl000.CAHBLTl1O0[13] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_initcfg_awrap.vhd(118) | Removing sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTLIILLl.CAHBLTl000.CAHBLTl1O0[12] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_initcfg_awrap.vhd(118) | Removing sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTLIILLl.CAHBLTl000.CAHBLTl1O0[11] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_initcfg_awrap.vhd(118) | Removing sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTLIILLl.CAHBLTl000.CAHBLTl1O0[10] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_initcfg_awrap.vhd(118) | Removing sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTLIILLl.CAHBLTl000.CAHBLTl1O0[9] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_initcfg_awrap.vhd(118) | Removing sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTLIILLl.CAHBLTl000.CAHBLTl1O0[8] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_initcfg_awrap.vhd(118) | Removing sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTLIILLl.CAHBLTl000.CAHBLTl1O0[7] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_initcfg_awrap.vhd(118) | Removing sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTLIILLl.CAHBLTl000.CAHBLTl1O0[6] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_initcfg_awrap.vhd(118) | Removing sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTLIILLl.CAHBLTl000.CAHBLTl1O0[5] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_initcfg_awrap.vhd(118) | Removing sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTLIILLl.CAHBLTl000.CAHBLTl1O0[4] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_initcfg_awrap.vhd(118) | Removing sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTLIILLl.CAHBLTl000.CAHBLTl1O0[3] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_initcfg_awrap.vhd(118) | Removing sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTLIILLl.CAHBLTl000.CAHBLTl1O0[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_initcfg_awrap.vhd(118) | Removing sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTLIILLl.CAHBLTl000.CAHBLTl1O0[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_initcfg_awrap.vhd(118) | Removing sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTLIILLl.CAHBLTl000.CAHBLTl1O0[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_masterstage.vhd(346) | Removing sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTll0l[23] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_masterstage.vhd(346) | Removing sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTll0l[22] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_masterstage.vhd(346) | Removing sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTll0l[21] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_masterstage.vhd(346) | Removing sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l[23] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_masterstage.vhd(346) | Removing sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l[22] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : coreahblite_masterstage.vhd(346) | Removing sequential instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l[21] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : corememctrl.vhd(279) | Removing sequential instance CoreMemCtrl_0.corememctrl_O10[27] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : corememctrl.vhd(279) | Removing sequential instance CoreMemCtrl_0.corememctrl_O10[26] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : corememctrl.vhd(279) | Removing sequential instance CoreMemCtrl_0.corememctrl_O10[25] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : corememctrl.vhd(279) | Removing sequential instance CoreMemCtrl_0.corememctrl_O10[24] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : corememctrl.vhd(279) | Removing sequential instance CoreMemCtrl_0.corememctrl_O10[23] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : corememctrl.vhd(279) | Removing sequential instance CoreMemCtrl_0.corememctrl_O10[22] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : corememctrl.vhd(279) | Removing sequential instance CoreMemCtrl_0.corememctrl_O10[21] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : corememctrl.vhd(279) | Removing sequential instance CoreMemCtrl_0.corememctrl_O10[20] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : corememctrl.vhd(772) | Removing sequential instance CoreMemCtrl_0.COREMEmctrl_il1 of view:PrimLib.dffs(prim) because there are no references to its outputs 
@N:BN116 : corememctrl.vhd(790) | Removing sequential instance CoreMemCtrl_0.Corememctrl_LI1 of view:PrimLib.dffs(prim) because there are no references to its outputs 
@N:BN116 : corememctrl.vhd(790) | Removing sequential instance CoreMemCtrl_0.COREMEMctrl_o01 of view:PrimLib.dffs(prim) because there are no references to its outputs 
@N:BN116 : ramblocks_fusion.vhd(9997) | Removing sequential instance CORE10100_AHBAPB_0.CMACLI110L\.CMACII110L.CMACoii10l\.CMACLii10l.CMACi0ll0 of view:fusion.RAM4K9(prim) because there are no references to its outputs 
@N:BN116 : ramblocks_fusion.vhd(9921) | Removing sequential instance CORE10100_AHBAPB_0.CMACLI110L\.CMACII110L.CMACoii10l\.CMACLii10l.CMACl0ll0 of view:fusion.RAM4K9(prim) because there are no references to its outputs 
@N:BN116 : csr.vhd(1349) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACo000L.TPS of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : csr.vhd(1448) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACo000L.RPS of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : rc.vhd(1142) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACoiii[15] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(1142) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACoiii[15] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[47] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[47] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[46] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[46] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[45] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[45] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[44] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[44] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[43] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[43] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[42] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[42] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[41] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[41] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[40] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[40] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[39] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[39] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[38] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[38] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[37] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[37] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[36] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[36] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[35] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[35] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[34] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[34] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[33] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[33] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[32] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[32] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[31] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[31] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[30] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[30] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[29] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[29] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[28] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[28] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[27] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[27] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[26] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[26] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[25] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[25] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[24] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[24] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[23] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[23] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[22] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[22] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[21] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[21] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[20] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[20] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[19] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[19] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[18] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[18] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[17] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[17] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[16] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[16] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[15] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[15] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[14] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[14] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[13] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[13] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[12] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[12] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[11] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[11] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[10] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[10] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[9] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[9] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[8] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[8] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[7] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[7] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[6] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[6] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[5] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[5] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[4] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[4] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[3] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[3] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(939) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(939) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLOI1l[1] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : rc.vhd(1053) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.MATCHEN of view:PrimLib.dffr(prim) because there are no references to its outputs 
@A:BN291 : rc.vhd(1053) | Boundary register CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.MATCHEN has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : tlsm.vhd(1390) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMAClloo0[5] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : tlsm.vhd(1390) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMAClloo0[4] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : tlsm.vhd(1390) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMAClloo0[3] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : tlsm.vhd(1390) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMAClloo0[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : tlsm.vhd(1390) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMAClloo0[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : tlsm.vhd(1390) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMAClloo0[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : tlsm.vhd(1403) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMAColoo0 of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN132 : coreuart.vhd(305) | Removing sequential instance CoreUARTapb_0.CUARTLOil.CUARTol0,  because it is equivalent to instance CoreUARTapb_0.CUARTLOil.CUARTOI0
@W:BN132 : coreuart.vhd(315) | Removing sequential instance CoreUARTapb_0.CUARTLOil.CUARTLI0,  because it is equivalent to instance CoreUARTapb_0.CUARTLOil.CUARTll0
@W:BN132 : tlsm.vhd(1439) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACi0i1L,  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMAClo00L.CMACi0i1l
@W:BN132 : rfifo.vhd(303) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACI0I1L,  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACi0i1l
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[0],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[0]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[1],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[1]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[2],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[2]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[3],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[3]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[4],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[4]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[5],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[5]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[6],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[6]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[7],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[7]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[8],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[8]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[9],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[9]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[10],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[10]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[11],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[11]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[12],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[12]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[13],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[13]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[14],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[14]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[15],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[15]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[16],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[16]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[17],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[17]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[18],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[18]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[19],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[19]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[20],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[20]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[21],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[21]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[22],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[22]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[23],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[23]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[24],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[24]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[25],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[25]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[26],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[26]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[27],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[27]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[28],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[28]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[29],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[29]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[30],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[30]
@W:BN132 : tlsm.vhd(1076) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLLili[31],  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLLILI[31]
@W:BN132 : rlsm.vhd(200) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACl00lI,  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMAClo00L.CMACL00li
Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:10s; Memory used current: 96MB peak: 98MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:15s; Memory used current: 100MB peak: 108MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:16s; Memory used current: 102MB peak: 108MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:19s; Memory used current: 103MB peak: 108MB)

@W:BN132 : tlsm.vhd(1140) | Removing sequential instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACL00Li,  because it is equivalent to instance CORE10100_AHBAPB_0.CMACiioo1l.CMAClo00L.CMACL00li
Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:20s; Memory used current: 101MB peak: 108MB)

Finished preparing to map (Time elapsed 0h:00m:25s; Memory used current: 130MB peak: 131MB)


High Fanout Net Report
**********************

Driver Instance / Pin Name                                                              Fanout, notes                     
--------------------------------------------------------------------------------------------------------------------------
CoreAHB2APB_0.PENABLE / Q                                                               32                                
CoreMemCtrl_0.COREMEMCtrl_i00 / Q                                                       32                                
CoreAHB2APB_0.PWDATA[0] / Q                                                             57                                
CoreAHB2APB_0.PWDATA[1] / Q                                                             58                                
CoreAHB2APB_0.PWDATA[2] / Q                                                             57                                
CoreAHB2APB_0.PWDATA[3] / Q                                                             83                                
CoreAHB2APB_0.PWDATA[4] / Q                                                             51                                
CoreAHB2APB_0.PWDATA[5] / Q                                                             86                                
CoreAHB2APB_0.PWDATA[6] / Q                                                             84                                
CoreAHB2APB_0.PWDATA[7] / Q                                                             83                                
CoreAHB2APB_0.PADDR[2] / Q                                                              139                               
CoreAHB2APB_0.PADDR[3] / Q                                                              87                                
CoreAHB2APB_0.PADDR[4] / Q                                                              57                                
CoreAHB2APB_0.PADDR[5] / Q                                                              27                                
CoreAHB2APB_0.PADDR[6] / Q                                                              48                                
i2c_top_0.I2CINT0.COREI2C_0.CI2CO0l.0.ui2C.CI2CoL1L[3] / Q                              32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACI1I0L.CMACOIOil / Q                                   37                                
CoreAhbNvm_0.CAHBNVMLil0.CAHBNVMLOl0.CAHBNVMi1i[0] / Q                                  36                                
CoreAhbNvm_0.CAHBNVMLil0.CAHBNVMLOl0.CAHBNVMi1i_ns_0_a3[0] / Y                          26                                
CoreUARTapb_0.CUARTLOil.CUARTLLol.CUARTil / Q                                           25                                
CortexM1Top_0.RS.Dbg_uj.UJ / URSTB                                                      26 : 25 asynchronous set/reset    
CoreAhbNvm_0.CAHBNVMLil0.CAHBNVMILL0.CAHBNVMLiii[18] / Q                                32                                
CoreAhbNvm_0.CAHBNVMLil0.CAHBNVMILL0.CAHBNVMio0i[1] / Q                                 27                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTO10i[0] / Q                               33                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTO10i[1] / Q                               65                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTlillll.CAHBLTO10i[0] / Q                               33                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTlillll.CAHBLTO10i[1] / Q                               65                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLToILLLL.CAHBLTO10i[1] / Q                               34                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTilllll.CAHBLTO10i[0] / Q                               33                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTilllll.CAHBLTO10i[1] / Q                               65                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTo00l / Q                                  34                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTo00l / Q                                  39                                
CoreMemCtrl_0.corememctrL_IO0 / Q                                                       32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACio0li / Q                                   37                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACo0lli / Q                                   35                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACi11LI.un1_cmacio1l_i_o2_i_o4 / Y            37                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi[0] / Q                                48                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi[1] / Q                                27                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACilo1l[9] / Q                                61                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACilo1l[0] / Q                                40                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACoIO1L[2] / Q                                31                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACil0II[7] / Q                                40                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACil0II[5] / Q                                42                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.RE / Q                                          32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMAClo00L.CMACLIIOI[0] / Q                                88                                
CORE10100_AHBAPB_0.CMACiioo1l.CMAClo00L.CMACl000I[0] / Q                                48                                
CORE10100_AHBAPB_0.CMACiioo1l.CMAClo00L.CMACL0ioi[0] / Q                                43                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLl01i / Q                                   51                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACo0lli / Q                                   34                                
CortexM1Top_0.COrtexM1Top_I0 / Y                                                        1059 : 1036 asynchronous set/reset
CORE10100_AHBAPB_0.CMACiioo1l.CMACI1I0L.CMACll0il.un11_cmaclolil / Y                    32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACI1I0L.CMACILIIL.un41_cmacoooil_0_o4 / Y               76                                
CORE10100_AHBAPB_0.DATAACK / Y                                                          39                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.un1_cmaci0lli31_0_0 / Y                         32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACOLLii.un8_cmacl1oli_0_a2_0_a2 / Y           32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.un1_CMACi1lLI_2_0_0_o2 / Y                      32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACI0lli_1_sqmuxa_1_0_a2 / Y                   32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.N_1067_i_0_a2 / Y                               32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACI0lli_2_sqmuxa_0_a2 / Y                     32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.N_1075_2_i_i_a2 / Y                             52                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLL1L_0_sqmuxa / Y                           33                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLL1L_1_sqmuxa / Y                           32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLL1L_2_sqmuxa_0_a2 / Y                      34                                
CORE10100_AHBAPB_0.CMACiioo1l.CMAClo00L.CMACio00i_0_1_sqmuxa / Y                        48                                
CORE10100_AHBAPB_0.CMACiioo1l.CMAClo00L.CMACio00i_0_0_sqmuxa / Y                        48                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_cmaci0lli31_i / Y                           32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACiolii.un38_cmaco0lli / Y                    32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACI1lli_1_0 / Y                           32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMAClolii.un13_cmaco0lli_0_a2 / Y               32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACI0LLI_1_sqmuxa_1_i / Y                      32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACI0LLI_2_sqmuxa_i / Y                        32                                
CoreGPIO_0.un1_paddr_1_0_a2_0_a2 / Y                                                    32                                
CoreMemCtrl_0.un1_corememctrl_iiol / Y                                                  25                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTol0l_0_a2 / Y                             35                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTol0l / Y                                  32                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTilllll.CAHBLTIO1I.CAHBLTl01_f0_0_o3[1] / Y             51                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLToILLLL.CAHBLTIO1I.CAHBLTl01_f0_0_o3[1] / Y             33                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLToILLLL.CAHBLTl1ol_sn_m1_0_0 / Y                        26                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTlillll.CAHBLTIO1I.CAHBLTl01_f0_0_o3[1] / Y             35                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTl01_f0_0_o3[1] / Y             37                                
CoreAhbSram_0.COREAHBSram_l1i.COREAhbSram_ooL.HREADY / Y                                51                                
CoreGPIO_0.CGPIOiOI.14.CGPIOI1I.CGPIOii_147_0_o2[14] / Y                                38                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTl0ll_i_m4 / Y                             83                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTo1ll / Y                                  27                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTilllll.CAHBLTIO1I.CAHBLTl01_iv_0[0] / Y                27                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACi11LI.un21_cmaco1oli_i_a2 / Y               40                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACo000L.CMACol0oL.CMACol0oL.un3_cmacil01_0_a2 / Y       34                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACL111l.un1_CMACilo1l_0_a3_0_a2_0_a2 / Y      32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.cmaci0io0_0_sqmuxa_0_a2_0_a2 / Y                32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.cmaci0io0_0_0_a2[31] / Y                        27                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.cmaci0io0_0_0_i_o2[47] / Y                      35                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACo1iO0.CMACo1iO0.un26_cmacil11i_0_a2 / Y     54                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.cmaci0io0_2_sqmuxa_0_a2_0_a2 / Y                31                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.N_1257_i_0_o2 / Y                               59                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.cmaciiio0_2_0_o2[15] / Y                        33                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.cmaciiio0_i_a3_0_0_a2[0] / Y                    25                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTlOLLs_iv_0_a2[31] / Y                     34                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTlOLLs_iv_0_a2_0[31] / Y                   34                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTlOLLs_iv_0_a2_2[31] / Y                   34                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTlOLLs_iv_0_a2_1[31] / Y                   34                                
CoreAPB_0.COREAPB_oi0.PRDATAs_0_iv_0_a2[31] / Y                                         32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACo000L.CMACLIiol.un35_csrrw_0_a2 / Y                   32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACo000L.CMACi1iol.un65_csrrw_0_a2 / Y                   33                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACo000L.CMACo01ol.un162_csrrw_0_a2 / Y                  33                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACo000L.CMACOL1Ol.un134_csrrw_0_a2 / Y                  33                                
CoreAHB2APB_0.COREAHB2APB_o0i_ns_i_o6_0[1] / Y                                          36                                
CoreGPIO_0.CGPIOo0_0_sqmuxa_i_i_a2 / Y                                                  32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACl0oii.un54_cmaco10l_i_0_o2 / Y              34                                
CoreAPB_0.COREAPB_oi0.PRDATAs_0_iv_0_a2_0[31] / Y                                       32                                
CoreGPIO_0.CGPIOo0_0_sqmuxa_i_i_a2_0 / Y                                                33                                
CoreAHB2APB_0.un1_coreahb2apb_l10_i / Y                                                 26                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.cahbltooii110_0_a2 / Y                          34                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.cahbltooii112_0_a2 / Y                          34                                
CoreMemCtrl_0.HRDATA_1_iv_0_i_o3_0[23] / Y                                              28                                
CoreMemCtrl_0.HRDATA_1_iv_0_i_o3_1[31] / Y                                              28                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.cahbltooii122_0_a2 / Y                          34                                
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.cahbltooii111_0_a2 / Y                          34                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACi0oII.un62_cmaco1oli_i / Y                  31                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMAColliI.un58_cmaco1oli_i / Y                  32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACo000L.un1_cmacoilol / Y                               32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACo000L.CMACI0L1_198_e / Y                              34                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACo000L.CMACiio1_0_sqmuxa_i / Y                         29                                
CoreAhbSram_0.COREAHBSram_l1i.CoREAHBSRAm_lol.HRDATA_1_iv_i_o3_0[23] / Y                28                                
CoreAhbSram_0.COREAHBSram_l1i.CoREAHBSRAm_lol.HRDATA_1_iv_i_o3_0[31] / Y                28                                
CoreAhbSram_0.COREAHBSram_l1i.CoREAHBSRAm_lol.CoreAhbSram_OL_1_iv_i_a3[1] / Y           34                                
CoreAhbNvm_0.CAHBNVMLil0.CAHBNVMILL0.CAHBNVMOIIi_sn_m2_0_a2 / Y                         25                                
CoreMemCtrl_0.HRDATA_1_iv_0_i_a3_1[7] / Y                                               25                                
CoreMemCtrl_0.HRDATA_1_iv_0_i_a3_5[23] / Y                                              25                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACl111l.un1_cmacl00ii / Y                     32                                
CoreGPIO_0.CGPIOL1_iv_0_o2_1[4] / Y                                                     33                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACi11LI.un1_cmaco1oli_inv_0_a2_0_a2 / Y       32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACo000L.CMACo1i0_182_e / Y                              32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACo000L.CMACi0i0_150_e / Y                              31                                
CoreMemCtrl_0.cOREMEMCTRl_oi0_0_0[9] / Y                                                32                                
CoreMemCtrl_0.corememCTRL_OL1 / Q                                                       32                                
CORE10100_AHBAPB_0.CMACiioo1l.CMACl000l.un1_CORE10100_AHBAPB_0_2_i_i / Y                1843 : 1843 asynchronous set/reset
==========================================================================================================================

@N:FP130 :  | Promoting Net un1_CORE10100_AHBAPB_0_2_i_i on CLKINT  I_1264  
@N:FP130 :  | Promoting Net \\CoreAPB_0_APBmslave0_PADDR_\[2\]\\ on CLKINT  I_1265  
@N:FP130 :  | Promoting Net CORE10100_AHBAPB_0.CMACiioo1l.CMAClo00L.CMACLIIOI[0] on CLKINT  I_1266  
@N:FP130 :  | Promoting Net \\CoreAPB_0_APBmslave0_PADDR_\[3\]\\ on CLKINT  I_1267  
Replicating Sequential Instance CoreMemCtrl_0.corememCTRL_OL1, fanout 32 segments 2
Replicating Combinational Instance CoreMemCtrl_0.cOREMEMCTRl_oi0_0_0[9], fanout 32 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACo000L.CMACi0i0_150_e, fanout 31 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACo000L.CMACo1i0_182_e, fanout 32 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACi11LI.un1_cmaco1oli_inv_0_a2_0_a2, fanout 32 segments 2
Replicating Combinational Instance CoreGPIO_0.CGPIOL1_iv_0_o2_1[4], fanout 33 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACl111l.un1_cmacl00ii, fanout 32 segments 2
Replicating Combinational Instance CoreMemCtrl_0.HRDATA_1_iv_0_i_a3_5[23], fanout 25 segments 2
Replicating Combinational Instance CoreMemCtrl_0.HRDATA_1_iv_0_i_a3_1[7], fanout 25 segments 2
Replicating Combinational Instance CoreAhbNvm_0.CAHBNVMLil0.CAHBNVMILL0.CAHBNVMOIIi_sn_m2_0_a2, fanout 25 segments 2
Replicating Combinational Instance CoreAhbSram_0.COREAHBSram_l1i.CoREAHBSRAm_lol.CoreAhbSram_OL_1_iv_i_a3[1], fanout 34 segments 2
Replicating Combinational Instance CoreAhbSram_0.COREAHBSram_l1i.CoREAHBSRAm_lol.HRDATA_1_iv_i_o3_0[31], fanout 28 segments 2
Replicating Combinational Instance CoreAhbSram_0.COREAHBSram_l1i.CoREAHBSRAm_lol.HRDATA_1_iv_i_o3_0[23], fanout 28 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACo000L.CMACiio1_0_sqmuxa_i, fanout 29 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACo000L.CMACI0L1_198_e, fanout 34 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACo000L.un1_cmacoilol, fanout 32 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMAColliI.un58_cmaco1oli_i, fanout 32 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACi0oII.un62_cmaco1oli_i, fanout 31 segments 2
Replicating Combinational Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.cahbltooii111_0_a2, fanout 34 segments 2
Replicating Combinational Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.cahbltooii122_0_a2, fanout 34 segments 2
Replicating Combinational Instance CoreMemCtrl_0.HRDATA_1_iv_0_i_o3_1[31], fanout 28 segments 2
Replicating Combinational Instance CoreMemCtrl_0.HRDATA_1_iv_0_i_o3_0[23], fanout 28 segments 2
Replicating Combinational Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.cahbltooii112_0_a2, fanout 34 segments 2
Replicating Combinational Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.cahbltooii110_0_a2, fanout 34 segments 2
Replicating Combinational Instance CoreAHB2APB_0.un1_coreahb2apb_l10_i, fanout 26 segments 2
Replicating Combinational Instance CoreGPIO_0.CGPIOo0_0_sqmuxa_i_i_a2_0, fanout 33 segments 2
Replicating Combinational Instance CoreAPB_0.COREAPB_oi0.PRDATAs_0_iv_0_a2_0[31], fanout 32 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACl0oii.un54_cmaco10l_i_0_o2, fanout 34 segments 2
Replicating Combinational Instance CoreGPIO_0.CGPIOo0_0_sqmuxa_i_i_a2, fanout 32 segments 2
Replicating Combinational Instance CoreAHB2APB_0.COREAHB2APB_o0i_ns_i_o6_0[1], fanout 36 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACo000L.CMACOL1Ol.un134_csrrw_0_a2, fanout 34 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACo000L.CMACo01ol.un162_csrrw_0_a2, fanout 33 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACo000L.CMACi1iol.un65_csrrw_0_a2, fanout 33 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACo000L.CMACLIiol.un35_csrrw_0_a2, fanout 32 segments 2
Replicating Combinational Instance CoreAPB_0.COREAPB_oi0.PRDATAs_0_iv_0_a2[31], fanout 32 segments 2
Replicating Combinational Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTlOLLs_iv_0_a2_1[31], fanout 34 segments 2
Replicating Combinational Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTlOLLs_iv_0_a2_2[31], fanout 34 segments 2
Replicating Combinational Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTlOLLs_iv_0_a2_0[31], fanout 34 segments 2
Replicating Combinational Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTlOLLs_iv_0_a2[31], fanout 34 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.cmaciiio0_i_a3_0_0_a2[0], fanout 25 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.cmaciiio0_2_0_o2[15], fanout 33 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.N_1257_i_0_o2, fanout 59 segments 3
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.cmaci0io0_2_sqmuxa_0_a2_0_a2, fanout 31 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACo1iO0.CMACo1iO0.un26_cmacil11i_0_a2, fanout 56 segments 3
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.cmaci0io0_0_0_i_o2[47], fanout 35 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.cmaci0io0_0_0_a2[31], fanout 27 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.cmaci0io0_0_sqmuxa_0_a2_0_a2, fanout 32 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACL111l.un1_CMACilo1l_0_a3_0_a2_0_a2, fanout 32 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACo000L.CMACol0oL.CMACol0oL.un3_cmacil01_0_a2, fanout 34 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACi11LI.un21_cmaco1oli_i_a2, fanout 41 segments 2
Replicating Combinational Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTilllll.CAHBLTIO1I.CAHBLTl01_iv_0[0], fanout 27 segments 2
Replicating Combinational Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTo1ll, fanout 27 segments 2
Replicating Combinational Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTl0ll_i_m4, fanout 83 segments 4
Replicating Combinational Instance CoreGPIO_0.CGPIOiOI.14.CGPIOI1I.CGPIOii_147_0_o2[14], fanout 38 segments 2
Replicating Combinational Instance CoreAhbSram_0.COREAHBSram_l1i.COREAhbSram_ooL.HREADY, fanout 51 segments 3
Replicating Combinational Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTl01_f0_0_o3[1], fanout 37 segments 2
Replicating Combinational Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTlillll.CAHBLTIO1I.CAHBLTl01_f0_0_o3[1], fanout 35 segments 2
Replicating Combinational Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLToILLLL.CAHBLTl1ol_sn_m1_0_0, fanout 26 segments 2
Replicating Combinational Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLToILLLL.CAHBLTIO1I.CAHBLTl01_f0_0_o3[1], fanout 34 segments 2
Replicating Combinational Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTilllll.CAHBLTIO1I.CAHBLTl01_f0_0_o3[1], fanout 51 segments 3
Replicating Combinational Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTol0l, fanout 32 segments 2
Replicating Combinational Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTol0l_0_a2, fanout 35 segments 2
Replicating Combinational Instance CoreMemCtrl_0.un1_corememctrl_iiol, fanout 25 segments 2
Replicating Combinational Instance CoreGPIO_0.un1_paddr_1_0_a2_0_a2, fanout 32 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACI0LLI_2_sqmuxa_i, fanout 32 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACI0LLI_1_sqmuxa_1_i, fanout 32 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMAClolii.un13_cmaco0lli_0_a2, fanout 32 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACI1lli_1_0, fanout 32 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACiolii.un38_cmaco0lli, fanout 32 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_cmaci0lli31_i, fanout 32 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMAClo00L.CMACio00i_0_0_sqmuxa, fanout 48 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMAClo00L.CMACio00i_0_1_sqmuxa, fanout 48 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLL1L_2_sqmuxa_0_a2, fanout 34 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLL1L_1_sqmuxa, fanout 32 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLL1L_0_sqmuxa, fanout 33 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.N_1075_2_i_i_a2, fanout 52 segments 3
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACI0lli_2_sqmuxa_0_a2, fanout 32 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.N_1067_i_0_a2, fanout 32 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACI0lli_1_sqmuxa_1_0_a2, fanout 32 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.un1_CMACi1lLI_2_0_0_o2, fanout 32 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACOLLii.un8_cmacl1oli_0_a2_0_a2, fanout 32 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.un1_cmaci0lli31_0_0, fanout 32 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.DATAACK, fanout 39 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACI1I0L.CMACILIIL.un41_cmacoooil_0_o4, fanout 76 segments 4
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACI1I0L.CMACll0il.un11_cmaclolil, fanout 32 segments 2
Replicating Sequential Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACo0lli, fanout 35 segments 2
Replicating Sequential Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACLl01i, fanout 53 segments 3
Replicating Sequential Instance CORE10100_AHBAPB_0.CMACiioo1l.CMAClo00L.CMACL0ioi[0], fanout 43 segments 2
Replicating Sequential Instance CORE10100_AHBAPB_0.CMACiioo1l.CMAClo00L.CMACl000I[0], fanout 48 segments 2
Replicating Sequential Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.RE, fanout 32 segments 2
Replicating Sequential Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACil0II[5], fanout 42 segments 2
Replicating Sequential Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACil0II[7], fanout 41 segments 2
Replicating Sequential Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACoIO1L[2], fanout 31 segments 2
Replicating Sequential Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACilo1l[0], fanout 40 segments 2
Replicating Sequential Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACilo1l[9], fanout 61 segments 3
Replicating Sequential Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi[1], fanout 27 segments 2
Replicating Sequential Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi[0], fanout 48 segments 2
Replicating Combinational Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACi11LI.un1_cmacio1l_i_o2_i_o4, fanout 38 segments 2
Replicating Sequential Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACo0lli, fanout 36 segments 2
Replicating Sequential Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACio0li, fanout 37 segments 2
Replicating Sequential Instance CoreMemCtrl_0.corememctrL_IO0, fanout 32 segments 2
Replicating Sequential Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTo00l, fanout 42 segments 2
Replicating Sequential Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTo00l, fanout 36 segments 2
Replicating Sequential Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTilllll.CAHBLTO10i[1], fanout 65 segments 3
Replicating Sequential Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTilllll.CAHBLTO10i[0], fanout 33 segments 2
Replicating Sequential Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLToILLLL.CAHBLTO10i[1], fanout 35 segments 2
Replicating Sequential Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTlillll.CAHBLTO10i[1], fanout 65 segments 3
Replicating Sequential Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTlillll.CAHBLTO10i[0], fanout 33 segments 2
Replicating Sequential Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTO10i[1], fanout 65 segments 3
Replicating Sequential Instance CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTO10i[0], fanout 33 segments 2
Replicating Sequential Instance CoreAhbNvm_0.CAHBNVMLil0.CAHBNVMILL0.CAHBNVMio0i[1], fanout 27 segments 2
Replicating Sequential Instance CoreAhbNvm_0.CAHBNVMLil0.CAHBNVMILL0.CAHBNVMLiii[18], fanout 32 segments 2
Buffering CortexM1Top_0.URSTB, fanout 26 segments 2
Replicating Sequential Instance CoreUARTapb_0.CUARTLOil.CUARTLLol.CUARTil, fanout 25 segments 2
Replicating Combinational Instance CoreAhbNvm_0.CAHBNVMLil0.CAHBNVMLOl0.CAHBNVMi1i_ns_0_a3[0], fanout 26 segments 2
Replicating Sequential Instance CoreAhbNvm_0.CAHBNVMLil0.CAHBNVMLOl0.CAHBNVMi1i[0], fanout 36 segments 2
Replicating Sequential Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACI1I0L.CMACOIOil, fanout 37 segments 2
Replicating Sequential Instance i2c_top_0.I2CINT0.COREI2C_0.CI2CO0l.0.ui2C.CI2CoL1L[3], fanout 32 segments 2
Replicating Sequential Instance CoreAHB2APB_0.PADDR[6], fanout 50 segments 3
Replicating Sequential Instance CoreAHB2APB_0.PADDR[5], fanout 29 segments 2
Replicating Sequential Instance CoreAHB2APB_0.PADDR[4], fanout 58 segments 3
Replicating Sequential Instance CoreAHB2APB_0.PWDATA[7], fanout 83 segments 4
Replicating Sequential Instance CoreAHB2APB_0.PWDATA[6], fanout 84 segments 4
Replicating Sequential Instance CoreAHB2APB_0.PWDATA[5], fanout 86 segments 4
Replicating Sequential Instance CoreAHB2APB_0.PWDATA[4], fanout 51 segments 3
Replicating Sequential Instance CoreAHB2APB_0.PWDATA[3], fanout 83 segments 4
Replicating Sequential Instance CoreAHB2APB_0.PWDATA[2], fanout 57 segments 3
Replicating Sequential Instance CoreAHB2APB_0.PWDATA[1], fanout 58 segments 3
Replicating Sequential Instance CoreAHB2APB_0.PWDATA[0], fanout 57 segments 3
Replicating Sequential Instance CoreMemCtrl_0.COREMEMCtrl_i00, fanout 35 segments 2
Replicating Sequential Instance CoreAHB2APB_0.PENABLE, fanout 35 segments 2
Replicating Combinational Instance CoreAHB2APB_0.COREAHB2APB_o0i_ns_i_o6_0[1], fanout 34 segments 2
Replicating Sequential Instance CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACo111i[1], fanout 25 segments 2
Finished technology mapping (Time elapsed 0h:00m:29s; Memory used current: 130MB peak: 157MB)

@A:BN291 : resetsync_fusion.vhd(344) | Boundary register CortexM1Top_0.RS.CORTEXM1Top_iol has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A:BN291 : resetsync_fusion.vhd(344) | Boundary register CortexM1Top_0.RS.SYSRESETN has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:30s; Memory used current: 130MB peak: 157MB)


Added 1 Buffers
Added 160 Cells via replication
	Added 64 Sequential Cells via replication
	Added 96 Combinational Cells via replication
Finished restoring hierarchy (Time elapsed 0h:00m:30s; Memory used current: 133MB peak: 157MB)

Writing Analyst data base E:\sathish\Fusion_M1webserver_Demo\synthesis\M1webserver_TOP.srm
Finished Writing Netlist Databases (Time elapsed 0h:00m:33s; Memory used current: 127MB peak: 157MB)

Writing EDIF Netlist and constraint files
D-2009.12A
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:34s; Memory used current: 131MB peak: 157MB)

@W:MT420 :  | Found inferred clock M1webserver_TOP|TCK with period 16.67ns. A user-defined clock should be declared on object "p:TCK" 

@W:MT420 :  | Found inferred clock M1webserver_TOP|CLKT with period 16.67ns. A user-defined clock should be declared on object "p:CLKT" 

@W:MT420 :  | Found inferred clock M1webserver_TOP|CLKR with period 16.67ns. A user-defined clock should be declared on object "p:CLKR" 

@W:MT420 :  | Found inferred clock M1webserver_TOP|PLL_sys_0.net_0_inferred_clock with period 16.67ns. A user-defined clock should be declared on object "n:net_0" 

@W:MT420 :  | Found inferred clock ResetSYNC|UDRCK_inferred_clock with period 16.67ns. A user-defined clock should be declared on object "n:CortexM1Top_0.RS.UDRCK" 

@W:MT420 :  | Found inferred clock COREAI|CAIloli_inferred_clock[2] with period 16.67ns. A user-defined clock should be declared on object "n:COREAI_0.CAIloli[2]" 

@W:MT246 : cortexm1top_fusion.vhd(247) | Blackbox CortexM1Integration is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 


##### START OF TIMING REPORT #####[
# Timing Report written on Fri Aug 20 18:01:13 2010
#


Top view:               M1webserver_TOP
Library name:           fusion
Operating conditions:   COMWC-1 ( T = 70.0, V = 1.42, P = 1.48, tree_type = balanced_tree )
Requested Frequency:    60.0 MHz
Wire load mode:         top
Wire load model:        fusion
Paths requested:        5
Constraint File(s):    E:\sathish\Fusion_M1webserver_Demo\constraint\M1Webserver_HW_v3_1.sdc
                       
@N:MT320 :  | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. 

@N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.. 



Performance Summary 
*******************


Worst slack in design: -12.996

                                                   Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock                                     Frequency     Frequency     Period        Period        Slack       Type         Group              
-------------------------------------------------------------------------------------------------------------------------------------------------------
COREAI|CAIloli_inferred_clock[2]                   60.0 MHz      34.0 MHz      16.667        29.372        -12.706     inferred     Inferred_clkgroup_4
M1webserver_TOP|CLKR                               60.0 MHz      64.9 MHz      16.667        15.417        1.249       inferred     Inferred_clkgroup_1
M1webserver_TOP|CLKT                               60.0 MHz      81.1 MHz      16.667        12.328        4.339       inferred     Inferred_clkgroup_0
M1webserver_TOP|PLL_sys_0.net_0_inferred_clock     60.0 MHz      33.7 MHz      16.667        29.663        -12.996     inferred     Inferred_clkgroup_5
M1webserver_TOP|TCK                                60.0 MHz      172.1 MHz     16.667        5.811         10.856      inferred     Inferred_clkgroup_2
ResetSYNC|UDRCK_inferred_clock                     60.0 MHz      60.0 MHz      16.667        16.677        -0.005      inferred     Inferred_clkgroup_3
=======================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                                          |    rise  to  rise     |    fall  to  fall    |    rise  to  fall    |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                        Ending                                          |  constraint  slack    |  constraint  slack   |  constraint  slack   |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
M1webserver_TOP|CLKT                            M1webserver_TOP|CLKT                            |  16.667      4.339    |  No paths    -       |  No paths    -       |  No paths    -    
M1webserver_TOP|CLKT                            M1webserver_TOP|PLL_sys_0.net_0_inferred_clock  |  Diff grp    -        |  No paths    -       |  No paths    -       |  No paths    -    
M1webserver_TOP|CLKR                            M1webserver_TOP|CLKR                            |  16.667      1.249    |  No paths    -       |  No paths    -       |  No paths    -    
M1webserver_TOP|CLKR                            M1webserver_TOP|PLL_sys_0.net_0_inferred_clock  |  Diff grp    -        |  No paths    -       |  No paths    -       |  No paths    -    
M1webserver_TOP|TCK                             M1webserver_TOP|TCK                             |  No paths    -        |  16.667      False   |  No paths    -       |  No paths    -    
M1webserver_TOP|TCK                             ResetSYNC|UDRCK_inferred_clock                  |  No paths    -        |  No paths    -       |  No paths    -       |  Diff grp    -    
ResetSYNC|UDRCK_inferred_clock                  M1webserver_TOP|TCK                             |  No paths    -        |  No paths    -       |  Diff grp    -       |  No paths    -    
ResetSYNC|UDRCK_inferred_clock                  ResetSYNC|UDRCK_inferred_clock                  |  16.667      1.713    |  16.667      False   |  8.333       -0.005  |  No paths    -    
COREAI|CAIloli_inferred_clock[2]                COREAI|CAIloli_inferred_clock[2]                |  16.667      False    |  No paths    -       |  No paths    -       |  No paths    -    
COREAI|CAIloli_inferred_clock[2]                M1webserver_TOP|PLL_sys_0.net_0_inferred_clock  |  Diff grp    -        |  No paths    -       |  No paths    -       |  No paths    -    
M1webserver_TOP|PLL_sys_0.net_0_inferred_clock  M1webserver_TOP|CLKT                            |  Diff grp    -        |  No paths    -       |  No paths    -       |  No paths    -    
M1webserver_TOP|PLL_sys_0.net_0_inferred_clock  M1webserver_TOP|CLKR                            |  Diff grp    -        |  No paths    -       |  No paths    -       |  No paths    -    
M1webserver_TOP|PLL_sys_0.net_0_inferred_clock  COREAI|CAIloli_inferred_clock[2]                |  Diff grp    -        |  No paths    -       |  No paths    -       |  No paths    -    
M1webserver_TOP|PLL_sys_0.net_0_inferred_clock  M1webserver_TOP|PLL_sys_0.net_0_inferred_clock  |  16.667      -12.996  |  16.667      14.105  |  8.333       4.296   |  8.333       6.652
==========================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: COREAI|CAIloli_inferred_clock[2]
====================================



Starting Points with Worst Slack
********************************

                     Starting                                                                     Arrival            
Instance             Reference                            Type     Pin             Net            Time        Slack  
                     Clock                                                                                           
---------------------------------------------------------------------------------------------------------------------
COREAI_0.CAII000     COREAI|CAIloli_inferred_clock[2]     AB       ACMRDATA[2]     CAIoiii[2]     22.481      -12.706
COREAI_0.CAII000     COREAI|CAIloli_inferred_clock[2]     AB       ACMRDATA[5]     CAIoiii[5]     22.037      -11.675
COREAI_0.CAII000     COREAI|CAIloli_inferred_clock[2]     AB       ACMRDATA[7]     CAIoiii[7]     20.410      -10.143
COREAI_0.CAII000     COREAI|CAIloli_inferred_clock[2]     AB       ACMRDATA[3]     CAIoiii[3]     20.706      -9.814 
COREAI_0.CAII000     COREAI|CAIloli_inferred_clock[2]     AB       ACMRDATA[4]     CAIoiii[4]     19.966      -9.767 
COREAI_0.CAII000     COREAI|CAIloli_inferred_clock[2]     AB       ACMRDATA[0]     CAIoiii[0]     20.262      -9.261 
COREAI_0.CAII000     COREAI|CAIloli_inferred_clock[2]     AB       ACMRDATA[1]     CAIoiii[1]     19.227      -8.380 
COREAI_0.CAII000     COREAI|CAIloli_inferred_clock[2]     AB       ACMRDATA[6]     CAIoiii[6]     20.706      -8.099 
=====================================================================================================================


Ending Points with Worst Slack
******************************

                     Starting                                                                                                             Required            
Instance             Reference                            Type                    Pin           Net                                       Time         Slack  
                     Clock                                                                                                                                    
--------------------------------------------------------------------------------------------------------------------------------------------------------------
CortexM1Top_0.M1     COREAI|CAIloli_inferred_clock[2]     CortexM1Integration     HRDATA[2]     Z\\CortexM1Top_0_AHBmaster_HRDATA_\[2\]\\ 16.667       -12.706
CortexM1Top_0.M1     COREAI|CAIloli_inferred_clock[2]     CortexM1Integration     HRDATA[5]     Z\\CortexM1Top_0_AHBmaster_HRDATA_\[5\]\\ 16.667       -11.675
CortexM1Top_0.M1     COREAI|CAIloli_inferred_clock[2]     CortexM1Integration     HRDATA[7]     Z\\CortexM1Top_0_AHBmaster_HRDATA_\[7\]\\ 16.667       -10.143
CortexM1Top_0.M1     COREAI|CAIloli_inferred_clock[2]     CortexM1Integration     HRDATA[3]     Z\\CortexM1Top_0_AHBmaster_HRDATA_\[3\]\\ 16.667       -9.814 
CortexM1Top_0.M1     COREAI|CAIloli_inferred_clock[2]     CortexM1Integration     HRDATA[4]     Z\\CortexM1Top_0_AHBmaster_HRDATA_\[4\]\\ 16.667       -9.767 
CortexM1Top_0.M1     COREAI|CAIloli_inferred_clock[2]     CortexM1Integration     HRDATA[0]     Z\\CortexM1Top_0_AHBmaster_HRDATA_\[0\]\\ 16.667       -9.261 
CortexM1Top_0.M1     COREAI|CAIloli_inferred_clock[2]     CortexM1Integration     HRDATA[1]     Z\\CortexM1Top_0_AHBmaster_HRDATA_\[1\]\\ 16.667       -8.380 
CortexM1Top_0.M1     COREAI|CAIloli_inferred_clock[2]     CortexM1Integration     HRDATA[6]     Z\\CortexM1Top_0_AHBmaster_HRDATA_\[6\]\\ 16.667       -8.099 
==============================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      16.667
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         16.667

    - Propagation time:                      29.372
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -12.706

    Number of logic level(s):                9
    Starting point:                          COREAI_0.CAII000 / ACMRDATA[2]
    Ending point:                            CortexM1Top_0.M1 / HRDATA[2]
    The start point is clocked by            COREAI|CAIloli_inferred_clock[2] [rising] on pin ACMCLK
    The end   point is clocked by            System [rising]

Instance / Net                                                                              Pin             Pin                Arrival     No. of    
Name                                                                Type                    Name            Dir     Delay      Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------
COREAI_0.CAII000                                                    AB                      ACMRDATA[2]     Out     22.481     22.481      -         
CAIoiii[2]                                                          Net                     -               -       0.274      -           1         
COREAI_0.CAII000_RNIU9MP_0                                          OR2B                    B               In      -          22.754      -         
COREAI_0.CAII000_RNIU9MP_0                                          OR2B                    Y               Out     0.439      23.194      -         
CAIoiii_m[2]                                                        Net                     -               -       0.274      -           1         
COREAI_0.CAIoLL0\.2\.CAIill0\.CAIlil0\.CAIOOOI_RNIRA4D2[2]          NOR3C                   C               In      -          23.467      -         
COREAI_0.CAIoLL0\.2\.CAIill0\.CAIlil0\.CAIOOOI_RNIRA4D2[2]          NOR3C                   Y               Out     0.546      24.013      -         
CAIl11_1_iv_2[2]                                                    Net                     -               -       0.274      -           1         
COREAI_0.CAII000_RNIPKQ63                                           AOI1B                   C               In      -          24.286      -         
COREAI_0.CAII000_RNIPKQ63                                           AOI1B                   Y               Out     0.345      24.631      -         
CAIl11_1_iv_5[2]                                                    Net                     -               -       0.274      -           1         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a4_0[2]                          AO1                     B               In      -          24.905      -         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a4_0[2]                          AO1                     Y               Out     0.509      25.413      -         
N_85                                                                Net                     -               -       0.274      -           1         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNI2EI4K[0]                 NOR3C                   A               In      -          25.687      -         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNI2EI4K[0]                 NOR3C                   Y               Out     0.395      26.082      -         
PRDATAs_iv_0_2[2]                                                   Net                     -               -       0.274      -           1         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNIT1FLT1[0]                AO1C                    C               In      -          26.355      -         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNIT1FLT1[0]                AO1C                    Y               Out     0.538      26.894      -         
Z\\CoreAHB2APB_0_APBmaster_PRDATA_\[2\]\\                           Net                     -               -       0.328      -           2         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTIO1L_RNIF6FCV1[1]     OR2B                    B               In      -          27.222      -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTIO1L_RNIF6FCV1[1]     OR2B                    Y               Out     0.439      27.661      -         
N_190                                                               Net                     -               -       0.274      -           1         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTIO1L_RNIJFPA52[0]     AOI1B                   C               In      -          27.935      -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTIO1L_RNIJFPA52[0]     AOI1B                   Y               Out     0.345      28.279      -         
CAHBLTlOLLs_iv_0_0[2]                                               Net                     -               -       0.274      -           1         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTIO1L_RNIRUD8C2[0]     OR3C                    C               In      -          28.553      -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTIO1L_RNIRUD8C2[0]     OR3C                    Y               Out     0.546      29.099      -         
Z\\CortexM1Top_0_AHBmaster_HRDATA_\[2\]\\                           Net                     -               -       0.274      -           1         
CortexM1Top_0.M1                                                    CortexM1Integration     HRDATA[2]       In      -          29.372      -         
=====================================================================================================================================================
Total path delay (propagation time + setup) of 29.372 is 26.581(90.5%) logic and 2.791(9.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      16.667
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         16.667

    - Propagation time:                      28.341
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -11.675

    Number of logic level(s):                7
    Starting point:                          COREAI_0.CAII000 / ACMRDATA[5]
    Ending point:                            CortexM1Top_0.M1 / HRDATA[5]
    The start point is clocked by            COREAI|CAIloli_inferred_clock[2] [rising] on pin ACMCLK
    The end   point is clocked by            System [rising]

Instance / Net                                                                              Pin             Pin                Arrival     No. of    
Name                                                                Type                    Name            Dir     Delay      Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------
COREAI_0.CAII000                                                    AB                      ACMRDATA[5]     Out     22.037     22.037      -         
CAIoiii[5]                                                          Net                     -               -       0.274      -           1         
COREAI_0.CAII000_RNISNRH1                                           AOI1B                   B               In      -          22.311      -         
COREAI_0.CAII000_RNISNRH1                                           AOI1B                   Y               Out     0.775      23.086      -         
CAIl11_1_0_iv_1[5]                                                  Net                     -               -       0.274      -           1         
COREAI_0.CAII000_RNIB72F5                                           OR3C                    B               In      -          23.359      -         
COREAI_0.CAII000_RNIB72F5                                           OR3C                    Y               Out     0.531      23.890      -         
Z\\CoreAPB_0_APBmslave6_PRDATA_\[5\]\\                              Net                     -               -       0.274      -           1         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNI8AOU9[0]                 OA1A                    A               In      -          24.164      -         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNI8AOU9[0]                 OA1A                    Y               Out     0.794      24.958      -         
PRDATAs_iv_0_1[5]                                                   Net                     -               -       0.274      -           1         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNIH5D5I[0]                 OA1A                    C               In      -          25.231      -         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNIH5D5I[0]                 OA1A                    Y               Out     0.339      25.570      -         
PRDATAs_iv_0_2[5]                                                   Net                     -               -       0.274      -           1         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNIC0L4T1[0]                AO1C                    C               In      -          25.844      -         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNIC0L4T1[0]                AO1C                    Y               Out     0.558      26.401      -         
Z\\CoreAHB2APB_0_APBmaster_PRDATA_\[5\]\\                           Net                     -               -       0.328      -           2         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTIO1L_RNIU4LRU1[1]     OR2B                    B               In      -          26.729      -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTIO1L_RNIU4LRU1[1]     OR2B                    Y               Out     0.534      27.263      -         
N_104                                                               Net                     -               -       0.274      -           1         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTIO1L_RNI613LB2[0]     OR3C                    B               In      -          27.537      -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTIO1L_RNI613LB2[0]     OR3C                    Y               Out     0.531      28.068      -         
Z\\CortexM1Top_0_AHBmaster_HRDATA_\[5\]\\                           Net                     -               -       0.274      -           1         
CortexM1Top_0.M1                                                    CortexM1Integration     HRDATA[5]       In      -          28.341      -         
=====================================================================================================================================================
Total path delay (propagation time + setup) of 28.341 is 26.098(92.1%) logic and 2.244(7.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      16.667
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         16.667

    - Propagation time:                      26.809
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -10.143

    Number of logic level(s):                8
    Starting point:                          COREAI_0.CAII000 / ACMRDATA[7]
    Ending point:                            CortexM1Top_0.M1 / HRDATA[7]
    The start point is clocked by            COREAI|CAIloli_inferred_clock[2] [rising] on pin ACMCLK
    The end   point is clocked by            System [rising]

Instance / Net                                                                              Pin             Pin                Arrival     No. of    
Name                                                                Type                    Name            Dir     Delay      Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------
COREAI_0.CAII000                                                    AB                      ACMRDATA[7]     Out     20.410     20.410      -         
CAIoiii[7]                                                          Net                     -               -       0.274      -           1         
COREAI_0.CAII000_RNIU9MP_3                                          OR2B                    B               In      -          20.684      -         
COREAI_0.CAII000_RNIU9MP_3                                          OR2B                    Y               Out     0.534      21.218      -         
N_111                                                               Net                     -               -       0.274      -           1         
COREAI_0.CAIIILI_RNI7F9I1[7]                                        OA1A                    C               In      -          21.491      -         
COREAI_0.CAIIILI_RNI7F9I1[7]                                        OA1A                    Y               Out     0.339      21.830      -         
CAIl11_1_0_iv_0_0[7]                                                Net                     -               -       0.274      -           1         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a4_0[7]                          AO1                     B               In      -          22.104      -         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a4_0[7]                          AO1                     Y               Out     0.482      22.586      -         
N_120                                                               Net                     -               -       0.274      -           1         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNIFAKR8[0]                 NOR3C                   C               In      -          22.859      -         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNIFAKR8[0]                 NOR3C                   Y               Out     0.566      23.426      -         
PRDATAs_iv_0_1[7]                                                   Net                     -               -       0.274      -           1         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNI7NHTG[0]                 OA1A                    C               In      -          23.699      -         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNI7NHTG[0]                 OA1A                    Y               Out     0.339      24.038      -         
PRDATAs_iv_0_2[7]                                                   Net                     -               -       0.274      -           1         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNI9D6IQ1[0]                AO1C                    C               In      -          24.311      -         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNI9D6IQ1[0]                AO1C                    Y               Out     0.558      24.869      -         
Z\\CoreAHB2APB_0_APBmaster_PRDATA_\[7\]\\                           Net                     -               -       0.328      -           2         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTIO1L_RNIRH69S1[1]     OR2B                    B               In      -          25.197      -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTIO1L_RNIRH69S1[1]     OR2B                    Y               Out     0.534      25.731      -         
N_96                                                                Net                     -               -       0.274      -           1         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTIO1L_RNIQD7O82[0]     OR3C                    B               In      -          26.005      -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTIO1L_RNIQD7O82[0]     OR3C                    Y               Out     0.531      26.536      -         
Z\\CortexM1Top_0_AHBmaster_HRDATA_\[7\]\\                           Net                     -               -       0.274      -           1         
CortexM1Top_0.M1                                                    CortexM1Integration     HRDATA[7]       In      -          26.809      -         
=====================================================================================================================================================
Total path delay (propagation time + setup) of 26.809 is 24.292(90.6%) logic and 2.517(9.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      16.667
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         16.667

    - Propagation time:                      26.481
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -9.814

    Number of logic level(s):                7
    Starting point:                          COREAI_0.CAII000 / ACMRDATA[3]
    Ending point:                            CortexM1Top_0.M1 / HRDATA[3]
    The start point is clocked by            COREAI|CAIloli_inferred_clock[2] [rising] on pin ACMCLK
    The end   point is clocked by            System [rising]

Instance / Net                                                                              Pin             Pin                Arrival     No. of    
Name                                                                Type                    Name            Dir     Delay      Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------
COREAI_0.CAII000                                                    AB                      ACMRDATA[3]     Out     20.706     20.706      -         
CAIoiii[3]                                                          Net                     -               -       0.274      -           1         
COREAI_0.CAII000_RNIU9MP_1                                          OR2B                    B               In      -          20.980      -         
COREAI_0.CAII000_RNIU9MP_1                                          OR2B                    Y               Out     0.534      21.513      -         
CAIoiii_m[3]                                                        Net                     -               -       0.274      -           1         
COREAI_0.CAII000_RNIG9DE2                                           NOR3C                   A               In      -          21.787      -         
COREAI_0.CAII000_RNIG9DE2                                           NOR3C                   Y               Out     0.447      22.234      -         
CAIl11_1_0_iv_4[3]                                                  Net                     -               -       0.274      -           1         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a4_0[3]                          AO1                     B               In      -          22.507      -         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a4_0[3]                          AO1                     Y               Out     0.482      22.989      -         
N_92                                                                Net                     -               -       0.274      -           1         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNIOGDUH[0]                 NOR3C                   A               In      -          23.263      -         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNIOGDUH[0]                 NOR3C                   Y               Out     0.447      23.709      -         
PRDATAs_iv_0_2[3]                                                   Net                     -               -       0.274      -           1         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNI78LPR1[0]                AO1C                    C               In      -          23.983      -         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNI78LPR1[0]                AO1C                    Y               Out     0.558      24.541      -         
Z\\CoreAHB2APB_0_APBmaster_PRDATA_\[3\]\\                           Net                     -               -       0.328      -           2         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTIO1L_RNIPCLGT1[1]     OR2B                    B               In      -          24.869      -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTIO1L_RNIPCLGT1[1]     OR2B                    Y               Out     0.534      25.403      -         
N_112                                                               Net                     -               -       0.274      -           1         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTIO1L_RNIA9KCA2[0]     OR3C                    B               In      -          25.676      -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTIO1L_RNIA9KCA2[0]     OR3C                    Y               Out     0.531      26.207      -         
Z\\CortexM1Top_0_AHBmaster_HRDATA_\[3\]\\                           Net                     -               -       0.274      -           1         
CortexM1Top_0.M1                                                    CortexM1Integration     HRDATA[3]       In      -          26.481      -         
=====================================================================================================================================================
Total path delay (propagation time + setup) of 26.481 is 24.237(91.5%) logic and 2.244(8.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      16.667
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         16.667

    - Propagation time:                      26.433
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -9.767

    Number of logic level(s):                8
    Starting point:                          COREAI_0.CAII000 / ACMRDATA[4]
    Ending point:                            CortexM1Top_0.M1 / HRDATA[4]
    The start point is clocked by            COREAI|CAIloli_inferred_clock[2] [rising] on pin ACMCLK
    The end   point is clocked by            System [rising]

Instance / Net                                                                              Pin             Pin                Arrival     No. of    
Name                                                                Type                    Name            Dir     Delay      Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------
COREAI_0.CAII000                                                    AB                      ACMRDATA[4]     Out     19.966     19.966      -         
CAIoiii[4]                                                          Net                     -               -       0.274      -           1         
COREAI_0.CAII000_RNIU9MP_2                                          OR2B                    B               In      -          20.240      -         
COREAI_0.CAII000_RNIU9MP_2                                          OR2B                    Y               Out     0.534      20.774      -         
N_123                                                               Net                     -               -       0.274      -           1         
COREAI_0.CAIIILI_RNI4F9I1[4]                                        OA1A                    C               In      -          21.047      -         
COREAI_0.CAIIILI_RNI4F9I1[4]                                        OA1A                    Y               Out     0.339      21.386      -         
CAIl11_1_0_iv_0_1[4]                                                Net                     -               -       0.274      -           1         
COREAI_0.CAII01l_RNINS103[4]                                        NOR3C                   C               In      -          21.660      -         
COREAI_0.CAII01l_RNINS103[4]                                        NOR3C                   Y               Out     0.566      22.226      -         
CAIl11_1_0_iv_0_4[4]                                                Net                     -               -       0.274      -           1         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a4_0[4]                          AO1                     A               In      -          22.500      -         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a4_0[4]                          AO1                     Y               Out     0.442      22.942      -         
N_99                                                                Net                     -               -       0.274      -           1         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNICHCJI[0]                 NOR3C                   A               In      -          23.215      -         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNICHCJI[0]                 NOR3C                   Y               Out     0.447      23.662      -         
PRDATAs_iv_0_2[4]                                                   Net                     -               -       0.274      -           1         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNI9HDKT1[0]                AO1C                    C               In      -          23.936      -         
CoreAPB_0.COREAPB_oi0.PRDATAs_iv_0_a2_1_RNI9HDKT1[0]                AO1C                    Y               Out     0.558      24.493      -         
Z\\CoreAHB2APB_0_APBmaster_PRDATA_\[4\]\\                           Net                     -               -       0.328      -           2         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTIO1L_RNIRLDBV1[1]     OR2B                    B               In      -          24.822      -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTIO1L_RNIRLDBV1[1]     OR2B                    Y               Out     0.534      25.355      -         
N_1120                                                              Net                     -               -       0.274      -           1         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTIO1L_RNIUDR4C2[0]     OR3C                    B               In      -          25.629      -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTIO1L_RNIUDR4C2[0]     OR3C                    Y               Out     0.531      26.160      -         
Z\\CortexM1Top_0_AHBmaster_HRDATA_\[4\]\\                           Net                     -               -       0.274      -           1         
CortexM1Top_0.M1                                                    CortexM1Integration     HRDATA[4]       In      -          26.433      -         
=====================================================================================================================================================
Total path delay (propagation time + setup) of 26.433 is 23.916(90.5%) logic and 2.517(9.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: M1webserver_TOP|CLKR
====================================



Starting Points with Worst Slack
********************************

                                                         Starting                                                     Arrival          
Instance                                                 Reference                Type       Pin     Net              Time        Slack
                                                         Clock                                                                         
---------------------------------------------------------------------------------------------------------------------------------------
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACi1ioi[3]     M1webserver_TOP|CLKR     DFN1C0     Q       TRADDR[3]        0.627       1.249
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACi1ioi[5]     M1webserver_TOP|CLKR     DFN1C0     Q       TRADDR[5]        0.627       1.283
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACi1ioi[0]     M1webserver_TOP|CLKR     DFN1C0     Q       TRADDR[0]        0.627       1.437
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACi1ioi[2]     M1webserver_TOP|CLKR     DFN1C0     Q       TRADDR[2]        0.627       1.640
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACi1ioi[4]     M1webserver_TOP|CLKR     DFN1C0     Q       TRADDR[4]        0.627       1.663
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACi1ioi[8]     M1webserver_TOP|CLKR     DFN1C0     Q       TRADDR[8]        0.627       1.900
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACoiiii[3]     M1webserver_TOP|CLKR     DFN1C0     Q       CMACoiiii[3]     0.627       2.004
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACoiiii[5]     M1webserver_TOP|CLKR     DFN1C0     Q       CMACoiiii[5]     0.627       2.027
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACi1ioi[6]     M1webserver_TOP|CLKR     DFN1C0     Q       TRADDR[6]        0.627       2.083
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACi1ioi[7]     M1webserver_TOP|CLKR     DFN1C0     Q       TRADDR[7]        0.627       2.117
=======================================================================================================================================


Ending Points with Worst Slack
******************************

                                                         Starting                                                         Required          
Instance                                                 Reference                Type       Pin     Net                  Time         Slack
                                                         Clock                                                                              
--------------------------------------------------------------------------------------------------------------------------------------------
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACi1ioi[7]     M1webserver_TOP|CLKR     DFN1C0     D       CMACi1ioi_RNO[7]     16.208       1.249
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACi1ioi[6]     M1webserver_TOP|CLKR     DFN1C0     D       N_230                16.208       1.487
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACi1ioi[5]     M1webserver_TOP|CLKR     DFN1C0     D       N_228                16.208       1.542
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACi1ioi[8]     M1webserver_TOP|CLKR     DFN1C0     D       N_130                16.208       1.993
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACi1ioi[4]     M1webserver_TOP|CLKR     DFN1C0     D       N_226                16.208       2.231
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACi1ioi[3]     M1webserver_TOP|CLKR     DFN1C0     D       N_224                16.208       2.965
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACi1ioi[2]     M1webserver_TOP|CLKR     DFN1C0     D       N_222                16.208       3.654
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACi1ioi[1]     M1webserver_TOP|CLKR     DFN1C0     D       N_220                16.208       4.756
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACl1o1l[5]     M1webserver_TOP|CLKR     DFN1P0     D       N_193                16.208       5.124
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACl1o1l[6]     M1webserver_TOP|CLKR     DFN1P0     D       CMACl1o1l_6[6]       16.208       5.150
============================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      16.667
    - Setup time:                            0.458
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         16.208

    - Propagation time:                      14.959
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 1.249

    Number of logic level(s):                14
    Starting point:                          CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACi1ioi[3] / Q
    Ending point:                            CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACi1ioi[7] / D
    The start point is clocked by            M1webserver_TOP|CLKR [rising] on pin CLK
    The end   point is clocked by            M1webserver_TOP|CLKR [rising] on pin CLK

Instance / Net                                                                 Pin      Pin               Arrival     No. of    
Name                                                                Type       Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACi1ioi[3]                DFN1C0     Q        Out     0.627     0.627       -         
TRADDR[3]                                                           Net        -        -       1.454     -           10        
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACoiiii_RNI07IC[3]        XNOR2      A        In      -         2.081       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACoiiii_RNI07IC[3]        XNOR2      Y        Out     0.347     2.428       -         
N_314_i_i                                                           Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACoiiii_RNIU54P[2]        XA1A       C        In      -         2.702       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACoiiii_RNIU54P[2]        XA1A       Y        Out     0.606     3.308       -         
un20_cmaci1ioi_NE_2                                                 Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACoiiii_RNI249I1[1]       NOR3C      C        In      -         3.582       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACoiiii_RNI249I1[1]       NOR3C      Y        Out     0.546     4.128       -         
un20_cmaci1ioi_NE_5                                                 Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACoiiii_RNII76H3[1]       NOR2B      B        In      -         4.401       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACoiiii_RNII76H3[1]       NOR2B      Y        Out     0.534     4.935       -         
un20_cmaci1ioi_NE                                                   Net        -        -       0.328     -           2         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACoIO1L_0_RNIARM14[2]     OR2        B        In      -         5.263       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACoIO1L_0_RNIARM14[2]     OR2        Y        Out     0.550     5.814       -         
N_264                                                               Net        -        -       0.686     -           3         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACil0II_RNII68D4[1]       NOR2       B        In      -         6.500       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACil0II_RNII68D4[1]       NOR2       Y        Out     0.550     7.050       -         
CMACil0II_RNII68D4[1]                                               Net        -        -       0.686     -           3         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACo01ii_RNI6AFG4          NOR2A      A        In      -         7.736       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACo01ii_RNI6AFG4          NOR2A      Y        Out     0.439     8.175       -         
N_207                                                               Net        -        -       0.328     -           2         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.un1_CMACi1ioi.I_1           AND2       B        In      -         8.504       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.un1_CMACi1ioi.I_1           AND2       Y        Out     0.439     8.943       -         
DWACT_ADD_CI_0_TMP[0]                                               Net        -        -       0.328     -           2         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.un1_CMACi1ioi.I_40          NOR2B      A        In      -         9.271       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.un1_CMACi1ioi.I_40          NOR2B      Y        Out     0.415     9.687       -         
DWACT_ADD_CI_0_g_array_1[0]                                         Net        -        -       0.686     -           3         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.un1_CMACi1ioi.I_44          NOR2B      A        In      -         10.373      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.un1_CMACi1ioi.I_44          NOR2B      Y        Out     0.415     10.789      -         
DWACT_ADD_CI_0_g_array_2[0]                                         Net        -        -       1.007     -           4         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.un1_CMACi1ioi.I_43          NOR2B      A        In      -         11.796      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.un1_CMACi1ioi.I_43          NOR2B      Y        Out     0.415     12.211      -         
DWACT_ADD_CI_0_g_array_11[0]                                        Net        -        -       0.328     -           2         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.un1_CMACi1ioi.I_50          NOR2B      A        In      -         12.540      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.un1_CMACi1ioi.I_50          NOR2B      Y        Out     0.415     12.955      -         
DWACT_ADD_CI_0_g_array_12_2[0]                                      Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.un1_CMACi1ioi.I_38          XOR2       B        In      -         13.229      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.un1_CMACi1ioi.I_38          XOR2       Y        Out     0.797     14.026      -         
I_38_1                                                              Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACi1ioi_RNO[7]            AO1C       B        In      -         14.299      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACi1ioi_RNO[7]            AO1C       Y        Out     0.386     14.685      -         
CMACi1ioi_RNO[7]                                                    Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACio00l.CMACi1ioi[7]                DFN1C0     D        In      -         14.959      -         
================================================================================================================================
Total path delay (propagation time + setup) of 15.417 is 7.942(51.5%) logic and 7.475(48.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: M1webserver_TOP|CLKT
====================================



Starting Points with Worst Slack
********************************

                                                         Starting                                                       Arrival          
Instance                                                 Reference                Type         Pin     Net              Time        Slack
                                                         Clock                                                                           
-----------------------------------------------------------------------------------------------------------------------------------------
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l[1]     M1webserver_TOP|CLKT     DFN1E0C0     Q       CMACLLL1l[1]     0.627       4.339
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l[2]     M1webserver_TOP|CLKT     DFN1E0C0     Q       CMACLLL1l[2]     0.627       4.368
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l[0]     M1webserver_TOP|CLKT     DFN1E0C0     Q       CMACLLL1l[0]     0.494       4.460
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACl110l        M1webserver_TOP|CLKT     DFN1P0       Q       CMACl110l        0.627       5.252
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACo0i1l[0]     M1webserver_TOP|CLKT     DFN1E1C0     Q       CMACo0i1l[0]     0.627       5.292
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACoio1L[0]     M1webserver_TOP|CLKT     DFN1C0       Q       CMACoio1L[0]     0.627       5.304
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACo0i1l[1]     M1webserver_TOP|CLKT     DFN1E1C0     Q       CMACo0i1l[1]     0.494       5.361
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l[3]     M1webserver_TOP|CLKT     DFN1E0C0     Q       CMACLLL1l[3]     0.627       5.556
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACo0i1l[2]     M1webserver_TOP|CLKT     DFN1E1C0     Q       CMACo0i1l[2]     0.627       5.737
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACilo1l[0]     M1webserver_TOP|CLKT     DFN1C0       Q       CMACilo1l[0]     0.627       5.744
=========================================================================================================================================


Ending Points with Worst Slack
******************************

                                                          Starting                                                           Required          
Instance                                                  Reference                Type         Pin     Net                  Time         Slack
                                                          Clock                                                                                
-----------------------------------------------------------------------------------------------------------------------------------------------
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l[13]     M1webserver_TOP|CLKT     DFN1E0C0     D       CMACLLL1l_n13        16.179       4.339
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l[12]     M1webserver_TOP|CLKT     DFN1E0C0     D       CMACLLL1l_n12        16.179       5.050
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACL1o1l[5]      M1webserver_TOP|CLKT     DFN1C0       D       CMACL1o1l_RNO[5]     16.208       5.252
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACL1o1l[6]      M1webserver_TOP|CLKT     DFN1C0       D       CMACL1o1l_12[6]      16.208       5.255
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACo0i1l[12]     M1webserver_TOP|CLKT     DFN1E1C0     D       CMACo0i1l_n12        16.238       5.292
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLi10l[7]      M1webserver_TOP|CLKT     DFN1C0       D       I_39                 16.208       5.744
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLi10l[9]      M1webserver_TOP|CLKT     DFN1C0       D       I_40                 16.208       5.744
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l[11]     M1webserver_TOP|CLKT     DFN1E0C0     D       CMACLLL1l_n11        16.179       5.817
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACo0i1l[11]     M1webserver_TOP|CLKT     DFN1E1C0     D       CMACo0i1l_n11        16.238       6.003
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACL1o1l[4]      M1webserver_TOP|CLKT     DFN1C0       D       CMACL1o1l_RNO[4]     16.208       6.008
===============================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      16.667
    - Setup time:                            0.488
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         16.179

    - Propagation time:                      11.840
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 4.339

    Number of logic level(s):                10
    Starting point:                          CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l[1] / Q
    Ending point:                            CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l[13] / D
    The start point is clocked by            M1webserver_TOP|CLKT [rising] on pin CLK
    The end   point is clocked by            M1webserver_TOP|CLKT [rising] on pin CLK

Instance / Net                                                                  Pin      Pin               Arrival     No. of    
Name                                                               Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l[1]               DFN1E0C0     Q        Out     0.627     0.627       -         
CMACLLL1l[1]                                                       Net          -        -       1.089     -           5         
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l_RNI2QVM_0[0]     NOR3C        C        In      -         1.716       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l_RNI2QVM_0[0]     NOR3C        Y        Out     0.546     2.261       -         
N_291                                                              Net          -        -       0.686     -           3         
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l_RNIQALU[3]       OR2B         A        In      -         2.947       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l_RNIQALU[3]       OR2B         Y        Out     0.438     3.385       -         
N_294                                                              Net          -        -       1.007     -           4         
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l_RNIJVA61[4]      NOR2A        B        In      -         4.392       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l_RNIJVA61[4]      NOR2A        Y        Out     0.328     4.721       -         
N_297                                                              Net          -        -       0.686     -           3         
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l_RNI8LML1[6]      NOR3C        B        In      -         5.407       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l_RNI8LML1[6]      NOR3C        Y        Out     0.516     5.923       -         
N_301                                                              Net          -        -       1.007     -           4         
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l_RNI1R252[8]      NOR3C        B        In      -         6.930       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l_RNI1R252[8]      NOR3C        Y        Out     0.516     7.446       -         
N_304                                                              Net          -        -       0.686     -           3         
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l_RNIV3PC2[9]      OR2B         A        In      -         8.133       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l_RNIV3PC2[9]      OR2B         Y        Out     0.438     8.570       -         
N_307                                                              Net          -        -       0.328     -           2         
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l_RNI7DFD2[10]     NOR2A        B        In      -         8.899       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l_RNI7DFD2[10]     NOR2A        Y        Out     0.328     9.227       -         
N_316                                                              Net          -        -       0.328     -           2         
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l_RNIGM5E2[11]     OR2B         A        In      -         9.555       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l_RNIGM5E2[11]     OR2B         Y        Out     0.438     9.993       -         
N_327                                                              Net          -        -       0.328     -           2         
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l_RNO_0[13]        OR2A         B        In      -         10.321      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l_RNO_0[13]        OR2A         Y        Out     0.438     10.759      -         
N_354                                                              Net          -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l_RNO[13]          XA1C         B        In      -         11.033      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l_RNO[13]          XA1C         Y        Out     0.534     11.567      -         
CMACLLL1l_n13                                                      Net          -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACoi00l.CMACLLL1l[13]              DFN1E0C0     D        In      -         11.840      -         
=================================================================================================================================
Total path delay (propagation time + setup) of 12.328 is 5.634(45.7%) logic and 6.694(54.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: M1webserver_TOP|PLL_sys_0.net_0_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                           Starting                                                                                    Arrival            
Instance                                                   Reference                                          Type         Pin     Net                 Time        Slack  
                                                           Clock                                                                                                          
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0[1]     M1webserver_TOP|PLL_sys_0.net_0_inferred_clock     DFN1C0       Q       CMACl0ioi_0[1]      0.627       -12.996
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0[0]     M1webserver_TOP|PLL_sys_0.net_0_inferred_clock     DFN1C0       Q       CMACl0ioi_0[0]      0.627       -12.671
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTIO1L[8]      M1webserver_TOP|PLL_sys_0.net_0_inferred_clock     DFN1E0C0     Q       CAHBLTI0I0I[8]      0.627       -12.591
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTIO1L[4]      M1webserver_TOP|PLL_sys_0.net_0_inferred_clock     DFN1E0C0     Q       CAHBLTI0I0I[4]      0.627       -12.567
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTIO1L[5]      M1webserver_TOP|PLL_sys_0.net_0_inferred_clock     DFN1E0C0     Q       CAHBLTI0I0I[5]      0.627       -12.506
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTIO1L[3]      M1webserver_TOP|PLL_sys_0.net_0_inferred_clock     DFN1E0C0     Q       CAHBLTI0I0I[3]      0.627       -12.483
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTIO1L[15]     M1webserver_TOP|PLL_sys_0.net_0_inferred_clock     DFN1E0C0     Q       CAHBLTI0I0I[15]     0.627       -12.472
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTIO1L[14]     M1webserver_TOP|PLL_sys_0.net_0_inferred_clock     DFN1E0C0     Q       CAHBLTI0I0I[14]     0.627       -12.448
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTIO1L[6]      M1webserver_TOP|PLL_sys_0.net_0_inferred_clock     DFN1E0C0     Q       CAHBLTI0I0I[6]      0.627       -12.388
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTllLLLL.CAHBLTIO1L[9]      M1webserver_TOP|PLL_sys_0.net_0_inferred_clock     DFN1E0C0     Q       CAHBLTI0I0I[9]      0.627       -12.379
==========================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                          Starting                                                                                    Required            
Instance                                                  Reference                                          Type         Pin     Net                 Time         Slack  
                                                          Clock                                                                                                           
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACi0ili[12]     M1webserver_TOP|PLL_sys_0.net_0_inferred_clock     DFN1C0       D       CMACi0ili_2[12]     16.208       -12.996
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACi0ili[13]     M1webserver_TOP|PLL_sys_0.net_0_inferred_clock     DFN1C0       D       CMACi0ili_2[13]     16.208       -11.978
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACi0ili[10]     M1webserver_TOP|PLL_sys_0.net_0_inferred_clock     DFN1C0       D       CMACi0ili_2[10]     16.179       -11.910
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACi0ili[11]     M1webserver_TOP|PLL_sys_0.net_0_inferred_clock     DFN1C0       D       CMACi0ili_2[11]     16.179       -11.695
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACi0ili[8]      M1webserver_TOP|PLL_sys_0.net_0_inferred_clock     DFN1C0       D       CMACi0ili_2[8]      16.179       -11.671
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACL011i[32]     M1webserver_TOP|PLL_sys_0.net_0_inferred_clock     DFN1E1C0     D       cmaci0io0[32]       16.238       -11.423
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACL011i[34]     M1webserver_TOP|PLL_sys_0.net_0_inferred_clock     DFN1E1C0     D       cmaci0io0[34]       16.238       -11.423
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACL011i[35]     M1webserver_TOP|PLL_sys_0.net_0_inferred_clock     DFN1E1C0     D       cmaci0io0[35]       16.238       -11.423
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACL011i[39]     M1webserver_TOP|PLL_sys_0.net_0_inferred_clock     DFN1E1C0     D       cmaci0io0[39]       16.238       -11.423
CORE10100_AHBAPB_0.CMACiioo1l.CMACoo00l.CMACL011i[38]     M1webserver_TOP|PLL_sys_0.net_0_inferred_clock     DFN1E1C0     D       cmaci0io0[38]       16.208       -11.365
==========================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      16.667
    - Setup time:                            0.458
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         16.208

    - Propagation time:                      29.204
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -12.996

    Number of logic level(s):                23
    Starting point:                          CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0[1] / Q
    Ending point:                            CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACi0ili[12] / D
    The start point is clocked by            M1webserver_TOP|PLL_sys_0.net_0_inferred_clock [rising] on pin CLK
    The end   point is clocked by            M1webserver_TOP|PLL_sys_0.net_0_inferred_clock [rising] on pin CLK

Instance / Net                                                                                            Pin      Pin               Arrival     No. of    
Name                                                                                           Type       Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0[1]                                         DFN1C0     Q        Out     0.627     0.627       -         
CMACl0ioi_0[1]                                                                                 Net        -        -       1.772     -           14        
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMAColioirff_2_RNIMK14                                 NOR2B      B        In      -         2.399       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMAColioirff_2_RNIMK14                                 NOR2B      Y        Out     0.534     2.933       -         
CMAColioiria_2_0                                                                               Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0_RNIRLS8[0]                                 AO1D       A        In      -         3.206       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0_RNIRLS8[0]                                 AO1D       Y        Out     0.408     3.615       -         
CMAColioiror_1                                                                                 Net        -        -       2.074     -           23        
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0_RNIJRKO1[0]                                AOI1       A        In      -         5.688       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0_RNIJRKO1[0]                                AOI1       Y        Out     0.516     6.204       -         
CMACl1i0l[2]                                                                                   Net        -        -       1.007     -           4         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_79                        OR2A       B        In      -         7.211       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_79                        OR2A       Y        Out     0.550     7.761       -         
N_13_1                                                                                         Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_83                        OA1A       C        In      -         8.035       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_83                        OA1A       Y        Out     0.345     8.380       -         
N_17_2                                                                                         Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_87                        OA1        C        In      -         8.653       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_87                        OA1        Y        Out     0.566     9.220       -         
N_21_0                                                                                         Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_88                        OA1        A        In      -         9.493       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_88                        OA1        Y        Out     0.623     10.116      -         
DWACT_CMPLE_PO2_DWACT_COMP0_E_0[2]                                                             Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_95                        AO1        B        In      -         10.390      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_95                        AO1        Y        Out     0.509     10.898      -         
DWACT_COMP0_E_2[2]                                                                             Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_100                       AO1        B        In      -         11.172      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_100                       AO1        Y        Out     0.509     11.681      -         
un1_CMACo1ili                                                                                  Net        -        -       1.395     -           8         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMAClo0lI_RNIEKEQF2                                    AOI1B      B        In      -         13.075      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMAClo0lI_RNIEKEQF2                                    AOI1B      Y        Out     0.775     13.850      -         
un8_cmacoo0li_1_0                                                                              Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMAClo0lI_RNI4DHPE4                                    AO1B       C        In      -         14.124      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMAClo0lI_RNI4DHPE4                                    AO1B       Y        Out     0.558     14.681      -         
CMACO1L0L                                                                                      Net        -        -       2.099     -           24        
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_1                                      AND2       B        In      -         16.780      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_1                                      AND2       Y        Out     0.534     17.314      -         
DWACT_ADD_CI_0_TMP[0]                                                                          Net        -        -       0.328     -           2         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_51                                     NOR2B      A        In      -         17.642      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_51                                     NOR2B      Y        Out     0.438     18.080      -         
DWACT_ADD_CI_0_g_array_1[0]                                                                    Net        -        -       0.686     -           3         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_60                                     NOR2B      A        In      -         18.766      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_60                                     NOR2B      Y        Out     0.438     19.204      -         
DWACT_ADD_CI_0_g_array_2[0]                                                                    Net        -        -       1.007     -           4         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_50                                     XOR2       B        In      -         20.211      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_50                                     XOR2       Y        Out     0.797     21.008      -         
I_50                                                                                           Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACio0li_RNIR3DOF4                                    OR2A       A        In      -         21.282      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACio0li_RNIR3DOF4                                    OR2A       Y        Out     0.457     21.739      -         
CMACl1ili_i_0[6]                                                                               Net        -        -       1.007     -           4         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I4_P0N        NOR2       B        In      -         22.746      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I4_P0N        NOR2       Y        Out     0.550     23.296      -         
N174                                                                                           Net        -        -       0.328     -           2         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I23_Y         OA1C       C        In      -         23.624      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I23_Y         OA1C       Y        Out     0.414     24.038      -         
N207                                                                                           Net        -        -       1.007     -           4         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I42_un1_Y     NOR2B      B        In      -         25.046      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I42_un1_Y     NOR2B      Y        Out     0.534     25.579      -         
I42_un1_Y                                                                                      Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I42_Y         OR2        B        In      -         25.853      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I42_Y         OR2        Y        Out     0.550     26.403      -         
N229                                                                                           Net        -        -       0.328     -           2         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I65_Y_2_tz    OR2        A        In      -         26.732      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I65_Y_2_tz    OR2        Y        Out     0.432     27.163      -         
ADD_12x12_fast_I65_Y_2_tz                                                                      Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I65_Y_2       OR3C       A        In      -         27.437      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I65_Y_2       OR3C       Y        Out     0.395     27.832      -         
ADD_12x12_fast_I65_Y_2                                                                         Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I84_Y_0       AX1E       A        In      -         28.105      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I84_Y_0       AX1E       Y        Out     0.825     28.930      -         
CMACi0ili_2[12]                                                                                Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACi0ili[12]                                          DFN1C0     D        In      -         29.204      -         
===========================================================================================================================================================
Total path delay (propagation time + setup) of 29.662 is 13.341(45.0%) logic and 16.322(55.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      16.667
    - Setup time:                            0.458
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         16.208

    - Propagation time:                      29.149
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -12.941

    Number of logic level(s):                23
    Starting point:                          CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0[1] / Q
    Ending point:                            CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACi0ili[12] / D
    The start point is clocked by            M1webserver_TOP|PLL_sys_0.net_0_inferred_clock [rising] on pin CLK
    The end   point is clocked by            M1webserver_TOP|PLL_sys_0.net_0_inferred_clock [rising] on pin CLK

Instance / Net                                                                                            Pin      Pin               Arrival     No. of    
Name                                                                                           Type       Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0[1]                                         DFN1C0     Q        Out     0.627     0.627       -         
CMACl0ioi_0[1]                                                                                 Net        -        -       1.772     -           14        
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMAColioirff_3_RNINK14                                 NOR2B      B        In      -         2.399       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMAColioirff_3_RNINK14                                 NOR2B      Y        Out     0.534     2.933       -         
CMAColioiria_3_0                                                                               Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0_RNITLS8[0]                                 OAI1       A        In      -         3.206       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0_RNITLS8[0]                                 OAI1       Y        Out     0.328     3.535       -         
CMAColioiror_0                                                                                 Net        -        -       2.074     -           23        
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0_RNIJRKO1[0]                                AOI1       B        In      -         5.608       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0_RNIJRKO1[0]                                AOI1       Y        Out     0.541     6.149       -         
CMACl1i0l[2]                                                                                   Net        -        -       1.007     -           4         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_79                        OR2A       B        In      -         7.157       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_79                        OR2A       Y        Out     0.550     7.707       -         
N_13_1                                                                                         Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_83                        OA1A       C        In      -         7.980       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_83                        OA1A       Y        Out     0.345     8.325       -         
N_17_2                                                                                         Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_87                        OA1        C        In      -         8.599       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_87                        OA1        Y        Out     0.566     9.165       -         
N_21_0                                                                                         Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_88                        OA1        A        In      -         9.439       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_88                        OA1        Y        Out     0.623     10.061      -         
DWACT_CMPLE_PO2_DWACT_COMP0_E_0[2]                                                             Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_95                        AO1        B        In      -         10.335      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_95                        AO1        Y        Out     0.509     10.844      -         
DWACT_COMP0_E_2[2]                                                                             Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_100                       AO1        B        In      -         11.117      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_100                       AO1        Y        Out     0.509     11.626      -         
un1_CMACo1ili                                                                                  Net        -        -       1.395     -           8         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMAClo0lI_RNIEKEQF2                                    AOI1B      B        In      -         13.021      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMAClo0lI_RNIEKEQF2                                    AOI1B      Y        Out     0.775     13.795      -         
un8_cmacoo0li_1_0                                                                              Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMAClo0lI_RNI4DHPE4                                    AO1B       C        In      -         14.069      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMAClo0lI_RNI4DHPE4                                    AO1B       Y        Out     0.558     14.627      -         
CMACO1L0L                                                                                      Net        -        -       2.099     -           24        
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_1                                      AND2       B        In      -         16.725      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_1                                      AND2       Y        Out     0.534     17.259      -         
DWACT_ADD_CI_0_TMP[0]                                                                          Net        -        -       0.328     -           2         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_51                                     NOR2B      A        In      -         17.587      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_51                                     NOR2B      Y        Out     0.438     18.025      -         
DWACT_ADD_CI_0_g_array_1[0]                                                                    Net        -        -       0.686     -           3         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_60                                     NOR2B      A        In      -         18.711      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_60                                     NOR2B      Y        Out     0.438     19.149      -         
DWACT_ADD_CI_0_g_array_2[0]                                                                    Net        -        -       1.007     -           4         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_50                                     XOR2       B        In      -         20.156      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_50                                     XOR2       Y        Out     0.797     20.953      -         
I_50                                                                                           Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACio0li_RNIR3DOF4                                    OR2A       A        In      -         21.227      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACio0li_RNIR3DOF4                                    OR2A       Y        Out     0.457     21.684      -         
CMACl1ili_i_0[6]                                                                               Net        -        -       1.007     -           4         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I4_P0N        NOR2       B        In      -         22.691      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I4_P0N        NOR2       Y        Out     0.550     23.241      -         
N174                                                                                           Net        -        -       0.328     -           2         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I23_Y         OA1C       C        In      -         23.570      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I23_Y         OA1C       Y        Out     0.414     23.984      -         
N207                                                                                           Net        -        -       1.007     -           4         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I42_un1_Y     NOR2B      B        In      -         24.991      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I42_un1_Y     NOR2B      Y        Out     0.534     25.525      -         
I42_un1_Y                                                                                      Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I42_Y         OR2        B        In      -         25.798      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I42_Y         OR2        Y        Out     0.550     26.349      -         
N229                                                                                           Net        -        -       0.328     -           2         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I65_Y_2_tz    OR2        A        In      -         26.677      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I65_Y_2_tz    OR2        Y        Out     0.432     27.109      -         
ADD_12x12_fast_I65_Y_2_tz                                                                      Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I65_Y_2       OR3C       A        In      -         27.382      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I65_Y_2       OR3C       Y        Out     0.395     27.777      -         
ADD_12x12_fast_I65_Y_2                                                                         Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I84_Y_0       AX1E       A        In      -         28.051      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I84_Y_0       AX1E       Y        Out     0.825     28.876      -         
CMACi0ili_2[12]                                                                                Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACi0ili[12]                                          DFN1C0     D        In      -         29.149      -         
===========================================================================================================================================================
Total path delay (propagation time + setup) of 29.608 is 13.286(44.9%) logic and 16.322(55.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      16.667
    - Setup time:                            0.458
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         16.208

    - Propagation time:                      29.034
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -12.826

    Number of logic level(s):                23
    Starting point:                          CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0[1] / Q
    Ending point:                            CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACi0ili[12] / D
    The start point is clocked by            M1webserver_TOP|PLL_sys_0.net_0_inferred_clock [rising] on pin CLK
    The end   point is clocked by            M1webserver_TOP|PLL_sys_0.net_0_inferred_clock [rising] on pin CLK

Instance / Net                                                                                            Pin      Pin               Arrival     No. of    
Name                                                                                           Type       Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0[1]                                         DFN1C0     Q        Out     0.627     0.627       -         
CMACl0ioi_0[1]                                                                                 Net        -        -       1.772     -           14        
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMAColioirff_0_RNIKK14                                 NOR2A      B        In      -         2.399       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMAColioirff_0_RNIKK14                                 NOR2A      Y        Out     0.346     2.745       -         
CMAColioiria_0_0                                                                               Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0_RNIRLS8[0]                                 AO1D       B        In      -         3.018       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0_RNIRLS8[0]                                 AO1D       Y        Out     0.541     3.560       -         
CMAColioiror_1                                                                                 Net        -        -       2.074     -           23        
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0_RNIJRKO1[0]                                AOI1       A        In      -         5.633       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0_RNIJRKO1[0]                                AOI1       Y        Out     0.775     6.408       -         
CMACl1i0l[2]                                                                                   Net        -        -       1.007     -           4         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_79                        OR2A       B        In      -         7.415       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_79                        OR2A       Y        Out     0.438     7.853       -         
N_13_1                                                                                         Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_83                        OA1A       C        In      -         8.127       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_83                        OA1A       Y        Out     0.339     8.465       -         
N_17_2                                                                                         Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_87                        OA1        C        In      -         8.739       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_87                        OA1        Y        Out     0.566     9.305       -         
N_21_0                                                                                         Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_88                        OA1        A        In      -         9.579       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_88                        OA1        Y        Out     0.837     10.416      -         
DWACT_CMPLE_PO2_DWACT_COMP0_E_0[2]                                                             Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_95                        AO1        B        In      -         10.690      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_95                        AO1        Y        Out     0.482     11.172      -         
DWACT_COMP0_E_2[2]                                                                             Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_100                       AO1        B        In      -         11.445      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_100                       AO1        Y        Out     0.482     11.927      -         
un1_CMACo1ili                                                                                  Net        -        -       1.395     -           8         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMAClo0lI_RNIEKEQF2                                    AOI1B      B        In      -         13.322      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMAClo0lI_RNIEKEQF2                                    AOI1B      Y        Out     0.516     13.838      -         
un8_cmacoo0li_1_0                                                                              Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMAClo0lI_RNI4DHPE4                                    AO1B       C        In      -         14.112      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMAClo0lI_RNI4DHPE4                                    AO1B       Y        Out     0.538     14.650      -         
CMACO1L0L                                                                                      Net        -        -       2.099     -           24        
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_1                                      AND2       B        In      -         16.749      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_1                                      AND2       Y        Out     0.439     17.188      -         
DWACT_ADD_CI_0_TMP[0]                                                                          Net        -        -       0.328     -           2         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_51                                     NOR2B      A        In      -         17.516      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_51                                     NOR2B      Y        Out     0.415     17.932      -         
DWACT_ADD_CI_0_g_array_1[0]                                                                    Net        -        -       0.686     -           3         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_60                                     NOR2B      A        In      -         18.618      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_60                                     NOR2B      Y        Out     0.415     19.034      -         
DWACT_ADD_CI_0_g_array_2[0]                                                                    Net        -        -       1.007     -           4         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_50                                     XOR2       B        In      -         20.041      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_50                                     XOR2       Y        Out     0.797     20.838      -         
I_50                                                                                           Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACio0li_RNIR3DOF4                                    OR2A       A        In      -         21.111      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACio0li_RNIR3DOF4                                    OR2A       Y        Out     0.457     21.569      -         
CMACl1ili_i_0[6]                                                                               Net        -        -       1.007     -           4         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I4_P0N        NOR2       B        In      -         22.576      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I4_P0N        NOR2       Y        Out     0.550     23.126      -         
N174                                                                                           Net        -        -       0.328     -           2         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I23_Y         OA1C       C        In      -         23.454      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I23_Y         OA1C       Y        Out     0.414     23.868      -         
N207                                                                                           Net        -        -       1.007     -           4         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I42_un1_Y     NOR2B      B        In      -         24.875      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I42_un1_Y     NOR2B      Y        Out     0.534     25.409      -         
I42_un1_Y                                                                                      Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I42_Y         OR2        B        In      -         25.683      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I42_Y         OR2        Y        Out     0.550     26.233      -         
N229                                                                                           Net        -        -       0.328     -           2         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I65_Y_2_tz    OR2        A        In      -         26.561      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I65_Y_2_tz    OR2        Y        Out     0.432     26.993      -         
ADD_12x12_fast_I65_Y_2_tz                                                                      Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I65_Y_2       OR3C       A        In      -         27.267      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I65_Y_2       OR3C       Y        Out     0.395     27.662      -         
ADD_12x12_fast_I65_Y_2                                                                         Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I84_Y_0       AX1E       A        In      -         27.935      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I84_Y_0       AX1E       Y        Out     0.825     28.760      -         
CMACi0ili_2[12]                                                                                Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACi0ili[12]                                          DFN1C0     D        In      -         29.034      -         
===========================================================================================================================================================
Total path delay (propagation time + setup) of 29.492 is 13.170(44.7%) logic and 16.322(55.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      16.667
    - Setup time:                            0.458
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         16.208

    - Propagation time:                      29.028
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -12.820

    Number of logic level(s):                23
    Starting point:                          CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0[1] / Q
    Ending point:                            CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACi0ili[12] / D
    The start point is clocked by            M1webserver_TOP|PLL_sys_0.net_0_inferred_clock [rising] on pin CLK
    The end   point is clocked by            M1webserver_TOP|PLL_sys_0.net_0_inferred_clock [rising] on pin CLK

Instance / Net                                                                                            Pin      Pin               Arrival     No. of    
Name                                                                                           Type       Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0[1]                                         DFN1C0     Q        Out     0.627     0.627       -         
CMACl0ioi_0[1]                                                                                 Net        -        -       1.772     -           14        
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMAColioirff_1_RNILK14                                 NOR2A      B        In      -         2.399       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMAColioirff_1_RNILK14                                 NOR2A      Y        Out     0.346     2.745       -         
CMAColioiria_1_0                                                                               Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0_RNITLS8[0]                                 OAI1       B        In      -         3.018       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0_RNITLS8[0]                                 OAI1       Y        Out     0.518     3.536       -         
CMAColioiror_0                                                                                 Net        -        -       2.074     -           23        
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0_RNIJRKO1[0]                                AOI1       B        In      -         5.610       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0_RNIJRKO1[0]                                AOI1       Y        Out     0.793     6.402       -         
CMACl1i0l[2]                                                                                   Net        -        -       1.007     -           4         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_79                        OR2A       B        In      -         7.410       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_79                        OR2A       Y        Out     0.438     7.847       -         
N_13_1                                                                                         Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_83                        OA1A       C        In      -         8.121       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_83                        OA1A       Y        Out     0.339     8.459       -         
N_17_2                                                                                         Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_87                        OA1        C        In      -         8.733       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_87                        OA1        Y        Out     0.566     9.299       -         
N_21_0                                                                                         Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_88                        OA1        A        In      -         9.573       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_88                        OA1        Y        Out     0.837     10.410      -         
DWACT_CMPLE_PO2_DWACT_COMP0_E_0[2]                                                             Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_95                        AO1        B        In      -         10.684      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_95                        AO1        Y        Out     0.482     11.166      -         
DWACT_COMP0_E_2[2]                                                                             Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_100                       AO1        B        In      -         11.439      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_100                       AO1        Y        Out     0.482     11.922      -         
un1_CMACo1ili                                                                                  Net        -        -       1.395     -           8         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMAClo0lI_RNIEKEQF2                                    AOI1B      B        In      -         13.316      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMAClo0lI_RNIEKEQF2                                    AOI1B      Y        Out     0.516     13.832      -         
un8_cmacoo0li_1_0                                                                              Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMAClo0lI_RNI4DHPE4                                    AO1B       C        In      -         14.106      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMAClo0lI_RNI4DHPE4                                    AO1B       Y        Out     0.538     14.644      -         
CMACO1L0L                                                                                      Net        -        -       2.099     -           24        
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_1                                      AND2       B        In      -         16.743      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_1                                      AND2       Y        Out     0.439     17.182      -         
DWACT_ADD_CI_0_TMP[0]                                                                          Net        -        -       0.328     -           2         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_51                                     NOR2B      A        In      -         17.510      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_51                                     NOR2B      Y        Out     0.415     17.926      -         
DWACT_ADD_CI_0_g_array_1[0]                                                                    Net        -        -       0.686     -           3         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_60                                     NOR2B      A        In      -         18.612      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_60                                     NOR2B      Y        Out     0.415     19.028      -         
DWACT_ADD_CI_0_g_array_2[0]                                                                    Net        -        -       1.007     -           4         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_50                                     XOR2       B        In      -         20.035      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_50                                     XOR2       Y        Out     0.797     20.832      -         
I_50                                                                                           Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACio0li_RNIR3DOF4                                    OR2A       A        In      -         21.106      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACio0li_RNIR3DOF4                                    OR2A       Y        Out     0.457     21.563      -         
CMACl1ili_i_0[6]                                                                               Net        -        -       1.007     -           4         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I4_P0N        NOR2       B        In      -         22.570      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I4_P0N        NOR2       Y        Out     0.550     23.120      -         
N174                                                                                           Net        -        -       0.328     -           2         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I23_Y         OA1C       C        In      -         23.448      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I23_Y         OA1C       Y        Out     0.414     23.862      -         
N207                                                                                           Net        -        -       1.007     -           4         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I42_un1_Y     NOR2B      B        In      -         24.869      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I42_un1_Y     NOR2B      Y        Out     0.534     25.403      -         
I42_un1_Y                                                                                      Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I42_Y         OR2        B        In      -         25.677      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I42_Y         OR2        Y        Out     0.550     26.227      -         
N229                                                                                           Net        -        -       0.328     -           2         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I65_Y_2_tz    OR2        A        In      -         26.555      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I65_Y_2_tz    OR2        Y        Out     0.432     26.987      -         
ADD_12x12_fast_I65_Y_2_tz                                                                      Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I65_Y_2       OR3C       A        In      -         27.261      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I65_Y_2       OR3C       Y        Out     0.395     27.656      -         
ADD_12x12_fast_I65_Y_2                                                                         Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I84_Y_0       AX1E       A        In      -         27.929      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I84_Y_0       AX1E       Y        Out     0.825     28.754      -         
CMACi0ili_2[12]                                                                                Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACi0ili[12]                                          DFN1C0     D        In      -         29.028      -         
===========================================================================================================================================================
Total path delay (propagation time + setup) of 29.486 is 13.164(44.6%) logic and 16.322(55.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      16.667
    - Setup time:                            0.458
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         16.208

    - Propagation time:                      28.929
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -12.721

    Number of logic level(s):                23
    Starting point:                          CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0[1] / Q
    Ending point:                            CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACi0ili[12] / D
    The start point is clocked by            M1webserver_TOP|PLL_sys_0.net_0_inferred_clock [rising] on pin CLK
    The end   point is clocked by            M1webserver_TOP|PLL_sys_0.net_0_inferred_clock [rising] on pin CLK

Instance / Net                                                                                            Pin      Pin               Arrival     No. of    
Name                                                                                           Type       Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0[1]                                         DFN1C0     Q        Out     0.627     0.627       -         
CMACl0ioi_0[1]                                                                                 Net        -        -       1.772     -           14        
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMAColioirff_2_RNIMK14                                 NOR2B      B        In      -         2.399       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMAColioirff_2_RNIMK14                                 NOR2B      Y        Out     0.534     2.933       -         
CMAColioiria_2_0                                                                               Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0_RNIRLS8[0]                                 AO1D       A        In      -         3.206       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0_RNIRLS8[0]                                 AO1D       Y        Out     0.408     3.615       -         
CMAColioiror_1                                                                                 Net        -        -       2.074     -           23        
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0_RNIJRKO1[0]                                AOI1       A        In      -         5.688       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACLI00l.CMACl0ioi_0_RNIJRKO1[0]                                AOI1       Y        Out     0.516     6.204       -         
CMACl1i0l[2]                                                                                   Net        -        -       1.007     -           4         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_79                        OR2A       B        In      -         7.211       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_79                        OR2A       Y        Out     0.550     7.761       -         
N_13_1                                                                                         Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_83                        OA1A       C        In      -         8.035       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_83                        OA1A       Y        Out     0.345     8.380       -         
N_17_2                                                                                         Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_87                        OA1        C        In      -         8.653       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_87                        OA1        Y        Out     0.566     9.220       -         
N_21_0                                                                                         Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_88                        OA1        A        In      -         9.493       -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_88                        OA1        Y        Out     0.623     10.116      -         
DWACT_CMPLE_PO2_DWACT_COMP0_E_0[2]                                                             Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_95                        AO1        B        In      -         10.390      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_95                        AO1        Y        Out     0.509     10.898      -         
DWACT_COMP0_E_2[2]                                                                             Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_100                       AO1        B        In      -         11.172      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACOILIi\.un1_CMACo1ili_0.I_100                       AO1        Y        Out     0.509     11.681      -         
un1_CMACo1ili                                                                                  Net        -        -       1.395     -           8         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLILII\.CMACLILII\.un8_cmacoo0li_m1_e               OR2A       B        In      -         13.075      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACLILII\.CMACLILII\.un8_cmacoo0li_m1_e               OR2A       Y        Out     0.550     13.625      -         
un8_cmacoo0li_m1_e                                                                             Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMAClo0lI_RNI4DHPE4                                    AO1B       B        In      -         13.899      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMAClo0lI_RNI4DHPE4                                    AO1B       Y        Out     0.507     14.406      -         
CMACO1L0L                                                                                      Net        -        -       2.099     -           24        
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_1                                      AND2       B        In      -         16.505      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_1                                      AND2       Y        Out     0.534     17.039      -         
DWACT_ADD_CI_0_TMP[0]                                                                          Net        -        -       0.328     -           2         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_51                                     NOR2B      A        In      -         17.367      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_51                                     NOR2B      Y        Out     0.438     17.805      -         
DWACT_ADD_CI_0_g_array_1[0]                                                                    Net        -        -       0.686     -           3         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_60                                     NOR2B      A        In      -         18.491      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_60                                     NOR2B      Y        Out     0.438     18.929      -         
DWACT_ADD_CI_0_g_array_2[0]                                                                    Net        -        -       1.007     -           4         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_50                                     XOR2       B        In      -         19.936      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.un1_CMACo1ili.I_50                                     XOR2       Y        Out     0.797     20.733      -         
I_50                                                                                           Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACio0li_RNIR3DOF4                                    OR2A       A        In      -         21.007      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACio0li_RNIR3DOF4                                    OR2A       Y        Out     0.457     21.464      -         
CMACl1ili_i_0[6]                                                                               Net        -        -       1.007     -           4         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I4_P0N        NOR2       B        In      -         22.471      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I4_P0N        NOR2       Y        Out     0.550     23.021      -         
N174                                                                                           Net        -        -       0.328     -           2         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I23_Y         OA1C       C        In      -         23.349      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I23_Y         OA1C       Y        Out     0.414     23.763      -         
N207                                                                                           Net        -        -       1.007     -           4         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I42_un1_Y     NOR2B      B        In      -         24.770      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I42_un1_Y     NOR2B      Y        Out     0.534     25.304      -         
I42_un1_Y                                                                                      Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I42_Y         OR2        B        In      -         25.578      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I42_Y         OR2        Y        Out     0.550     26.128      -         
N229                                                                                           Net        -        -       0.328     -           2         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I65_Y_2_tz    OR2        A        In      -         26.456      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I65_Y_2_tz    OR2        Y        Out     0.432     26.888      -         
ADD_12x12_fast_I65_Y_2_tz                                                                      Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I65_Y_2       OR3C       A        In      -         27.162      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I65_Y_2       OR3C       Y        Out     0.395     27.557      -         
ADD_12x12_fast_I65_Y_2                                                                         Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I84_Y_0       AX1E       A        In      -         27.830      -         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACL10LI\.CMACi0ili_2_22.ADD_12x12_fast_I84_Y_0       AX1E       Y        Out     0.825     28.655      -         
CMACi0ili_2[12]                                                                                Net        -        -       0.274     -           1         
CORE10100_AHBAPB_0.CMACiioo1l.CMACiI00L.CMACi0ili[12]                                          DFN1C0     D        In      -         28.929      -         
===========================================================================================================================================================
Total path delay (propagation time + setup) of 29.387 is 13.065(44.5%) logic and 16.322(55.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: M1webserver_TOP|TCK
====================================



Starting Points with Worst Slack
********************************

                               Starting                                              Arrival           
Instance                       Reference               Type      Pin       Net       Time        Slack 
                               Clock                                                                   
-------------------------------------------------------------------------------------------------------
CortexM1Top_0.RS.Dbg_uj\.UJ    M1webserver_TOP|TCK     UJTAG     URSTB     URSTB     1.881       10.856
=======================================================================================================


Ending Points with Worst Slack
******************************

                     Starting                                                              Required           
Instance             Reference               Type                    Pin       Net         Time         Slack 
                     Clock                                                                                    
--------------------------------------------------------------------------------------------------------------
CortexM1Top_0.M1     M1webserver_TOP|TCK     CortexM1Integration     nTRST     URSTB_0     16.667       10.856
==============================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      16.667
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         16.667

    - Propagation time:                      5.811
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 10.856

    Number of logic level(s):                1
    Starting point:                          CortexM1Top_0.RS.Dbg_uj\.UJ / URSTB
    Ending point:                            CortexM1Top_0.M1 / nTRST
    The start point is clocked by            M1webserver_TOP|TCK [falling] on pin TCK
    The end   point is clocked by            System [falling]

Instance / Net                                                 Pin       Pin               Arrival     No. of    
Name                                   Type                    Name      Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------
CortexM1Top_0.RS.Dbg_uj\.UJ            UJTAG                   URSTB     Out     1.881     1.881       -         
URSTB                                  Net                     -         -       1.772     -           14        
CortexM1Top_0.RS.Dbg_uj\.UJ_RNIODC4    BUFF                    A         In      -         3.653       -         
CortexM1Top_0.RS.Dbg_uj\.UJ_RNIODC4    BUFF                    Y         Out     0.424     4.077       -         
URSTB_0                                Net                     -         -       1.733     -           13        
CortexM1Top_0.M1                       CortexM1Integration     nTRST     In      -         5.811       -         
=================================================================================================================
Total path delay (propagation time + setup) of 5.811 is 2.306(39.7%) logic and 3.505(60.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: ResetSYNC|UDRCK_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                       Starting                                                                        Arrival           
Instance                                               Reference                          Type         Pin     Net                     Time        Slack 
                                                       Clock                                                                                             
---------------------------------------------------------------------------------------------------------------------------------------------------------
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol[0]    ResetSYNC|UDRCK_inferred_clock     DFN1C0       Q       CORTEXM1Top_o0ol[0]     0.627       -0.005
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol[1]    ResetSYNC|UDRCK_inferred_clock     DFN1C0       Q       CORTEXM1Top_o0ol[1]     0.627       0.212 
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol[2]    ResetSYNC|UDRCK_inferred_clock     DFN1C0       Q       CORTEXM1Top_o0ol[2]     0.627       0.696 
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count[1]               ResetSYNC|UDRCK_inferred_clock     DFN1E0C0     Q       Count[1]                0.627       1.260 
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count[2]               ResetSYNC|UDRCK_inferred_clock     DFN1E0C0     Q       Count[2]                0.627       1.316 
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count[0]               ResetSYNC|UDRCK_inferred_clock     DFN1E0C0     Q       Count[0]                0.627       1.452 
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol[3]    ResetSYNC|UDRCK_inferred_clock     DFN1C0       Q       CORTEXM1Top_o0ol[3]     0.627       2.063 
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count[3]               ResetSYNC|UDRCK_inferred_clock     DFN1E0C0     Q       Count[3]                0.627       2.091 
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count[4]               ResetSYNC|UDRCK_inferred_clock     DFN1E0C0     Q       Count[4]                0.627       2.585 
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count[5]               ResetSYNC|UDRCK_inferred_clock     DFN1E0C0     Q       Count[5]                0.627       3.568 
=========================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                       Starting                                                                           Required           
Instance                                               Reference                          Type         Pin     Net                        Time         Slack 
                                                       Clock                                                                                                 
-------------------------------------------------------------------------------------------------------------------------------------------------------------
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTExM1Top_l1ol       ResetSYNC|UDRCK_inferred_clock     DFN0C0       D       CORTExM1Top_l1ol_RNO       7.727        -0.005
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol[2]    ResetSYNC|UDRCK_inferred_clock     DFN1C0       D       CORTEXM1Top_o0ol_26[2]     16.208       1.713 
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol[1]    ResetSYNC|UDRCK_inferred_clock     DFN1C0       D       CORTEXM1Top_o0ol_26[1]     16.208       2.425 
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol[0]    ResetSYNC|UDRCK_inferred_clock     DFN1C0       D       CORTEXM1Top_o0ol_26[0]     16.208       2.705 
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol[3]    ResetSYNC|UDRCK_inferred_clock     DFN1C0       D       CORTEXM1Top_o0ol_26[3]     16.208       2.705 
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol[4]    ResetSYNC|UDRCK_inferred_clock     DFN1E1C0     E       N_149                      16.297       3.476 
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol[4]    ResetSYNC|UDRCK_inferred_clock     DFN1E1C0     D       N_57                       16.238       4.255 
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTexM1Top_ooLL       ResetSYNC|UDRCK_inferred_clock     DFN0C0       D       CORTEXM1Top_o0ol_i[3]      7.727        4.584 
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count[5]               ResetSYNC|UDRCK_inferred_clock     DFN1E0C0     D       Count_9[5]                 16.179       5.984 
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count[0]               ResetSYNC|UDRCK_inferred_clock     DFN1E0C0     D       Count_9[0]                 16.179       5.999 
=============================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      8.333
    - Setup time:                            0.606
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.727

    - Propagation time:                      7.732
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.005

    Number of logic level(s):                5
    Starting point:                          CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol[0] / Q
    Ending point:                            CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTExM1Top_l1ol / D
    The start point is clocked by            ResetSYNC|UDRCK_inferred_clock [rising] on pin CLK
    The end   point is clocked by            ResetSYNC|UDRCK_inferred_clock [falling] on pin CLK

Instance / Net                                                            Pin      Pin               Arrival     No. of    
Name                                                           Type       Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol[0]            DFN1C0     Q        Out     0.627     0.627       -         
CORTEXM1Top_o0ol[0]                                            Net        -        -       1.420     -           9         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol_RNI71L2[1]    OR2B       B        In      -         2.047       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol_RNI71L2[1]    OR2B       Y        Out     0.534     2.581       -         
un4_cortexm1top_l0ol_1                                         Net        -        -       0.686     -           3         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol_RNISNV3[2]    NOR2A      B        In      -         3.267       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol_RNISNV3[2]    NOR2A      Y        Out     0.328     3.595       -         
un4_cortexm1top_l0ol                                           Net        -        -       1.395     -           8         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count_RNINBQG[0]               MX2B       S        In      -         4.990       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count_RNINBQG[0]               MX2B       Y        Out     0.337     5.327       -         
CORTExM1Top_l0ol[0]                                            Net        -        -       0.686     -           3         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count_RNID1281[0]              NOR2       B        In      -         6.013       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count_RNID1281[0]              NOR2       Y        Out     0.550     6.564       -         
un1_cortexm1top_i0ol_2                                         Net        -        -       0.328     -           2         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTExM1Top_l1ol_RNO           NOR3C      C        In      -         6.892       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTExM1Top_l1ol_RNO           NOR3C      Y        Out     0.566     7.458       -         
CORTExM1Top_l1ol_RNO                                           Net        -        -       0.274     -           1         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTExM1Top_l1ol               DFN0C0     D        In      -         7.732       -         
===========================================================================================================================
Total path delay (propagation time + setup) of 8.338 is 3.549(42.6%) logic and 4.789(57.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      8.333
    - Setup time:                            0.606
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.727

    - Propagation time:                      7.614
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 0.113

    Number of logic level(s):                5
    Starting point:                          CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol[0] / Q
    Ending point:                            CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTExM1Top_l1ol / D
    The start point is clocked by            ResetSYNC|UDRCK_inferred_clock [rising] on pin CLK
    The end   point is clocked by            ResetSYNC|UDRCK_inferred_clock [falling] on pin CLK

Instance / Net                                                            Pin      Pin               Arrival     No. of    
Name                                                           Type       Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol[0]            DFN1C0     Q        Out     0.627     0.627       -         
CORTEXM1Top_o0ol[0]                                            Net        -        -       1.420     -           9         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol_RNI71L2[1]    OR2B       B        In      -         2.047       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol_RNI71L2[1]    OR2B       Y        Out     0.534     2.581       -         
un4_cortexm1top_l0ol_1                                         Net        -        -       0.686     -           3         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol_RNISNV3[2]    NOR2A      B        In      -         3.267       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol_RNISNV3[2]    NOR2A      Y        Out     0.328     3.595       -         
un4_cortexm1top_l0ol                                           Net        -        -       1.395     -           8         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count_RNIML7N[2]               MX2        S        In      -         4.990       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count_RNIML7N[2]               MX2        Y        Out     0.337     5.327       -         
CORTExM1Top_l0ol[1]                                            Net        -        -       0.686     -           3         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count_RNID1281[0]              NOR2       A        In      -         6.013       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count_RNID1281[0]              NOR2       Y        Out     0.432     6.445       -         
un1_cortexm1top_i0ol_2                                         Net        -        -       0.328     -           2         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTExM1Top_l1ol_RNO           NOR3C      C        In      -         6.774       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTExM1Top_l1ol_RNO           NOR3C      Y        Out     0.566     7.340       -         
CORTExM1Top_l1ol_RNO                                           Net        -        -       0.274     -           1         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTExM1Top_l1ol               DFN0C0     D        In      -         7.614       -         
===========================================================================================================================
Total path delay (propagation time + setup) of 8.220 is 3.431(41.7%) logic and 4.789(58.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      8.333
    - Setup time:                            0.606
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.727

    - Propagation time:                      7.515
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 0.213

    Number of logic level(s):                5
    Starting point:                          CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol[1] / Q
    Ending point:                            CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTExM1Top_l1ol / D
    The start point is clocked by            ResetSYNC|UDRCK_inferred_clock [rising] on pin CLK
    The end   point is clocked by            ResetSYNC|UDRCK_inferred_clock [falling] on pin CLK

Instance / Net                                                            Pin      Pin               Arrival     No. of    
Name                                                           Type       Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol[1]            DFN1C0     Q        Out     0.627     0.627       -         
CORTEXM1Top_o0ol[1]                                            Net        -        -       1.299     -           7         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol_RNI71L2[1]    OR2B       A        In      -         1.926       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol_RNI71L2[1]    OR2B       Y        Out     0.438     2.363       -         
un4_cortexm1top_l0ol_1                                         Net        -        -       0.686     -           3         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol_RNISNV3[2]    NOR2A      B        In      -         3.050       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol_RNISNV3[2]    NOR2A      Y        Out     0.328     3.378       -         
un4_cortexm1top_l0ol                                           Net        -        -       1.395     -           8         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count_RNINBQG[0]               MX2B       S        In      -         4.773       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count_RNINBQG[0]               MX2B       Y        Out     0.337     5.110       -         
CORTExM1Top_l0ol[0]                                            Net        -        -       0.686     -           3         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count_RNID1281[0]              NOR2       B        In      -         5.796       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count_RNID1281[0]              NOR2       Y        Out     0.550     6.346       -         
un1_cortexm1top_i0ol_2                                         Net        -        -       0.328     -           2         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTExM1Top_l1ol_RNO           NOR3C      C        In      -         6.675       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTExM1Top_l1ol_RNO           NOR3C      Y        Out     0.566     7.241       -         
CORTExM1Top_l1ol_RNO                                           Net        -        -       0.274     -           1         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTExM1Top_l1ol               DFN0C0     D        In      -         7.515       -         
===========================================================================================================================
Total path delay (propagation time + setup) of 8.121 is 3.453(42.5%) logic and 4.668(57.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      8.333
    - Setup time:                            0.606
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.727

    - Propagation time:                      7.396
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 0.331

    Number of logic level(s):                5
    Starting point:                          CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol[1] / Q
    Ending point:                            CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTExM1Top_l1ol / D
    The start point is clocked by            ResetSYNC|UDRCK_inferred_clock [rising] on pin CLK
    The end   point is clocked by            ResetSYNC|UDRCK_inferred_clock [falling] on pin CLK

Instance / Net                                                            Pin      Pin               Arrival     No. of    
Name                                                           Type       Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol[1]            DFN1C0     Q        Out     0.627     0.627       -         
CORTEXM1Top_o0ol[1]                                            Net        -        -       1.299     -           7         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol_RNI71L2[1]    OR2B       A        In      -         1.926       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol_RNI71L2[1]    OR2B       Y        Out     0.438     2.363       -         
un4_cortexm1top_l0ol_1                                         Net        -        -       0.686     -           3         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol_RNISNV3[2]    NOR2A      B        In      -         3.050       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol_RNISNV3[2]    NOR2A      Y        Out     0.328     3.378       -         
un4_cortexm1top_l0ol                                           Net        -        -       1.395     -           8         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count_RNIML7N[2]               MX2        S        In      -         4.773       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count_RNIML7N[2]               MX2        Y        Out     0.337     5.110       -         
CORTExM1Top_l0ol[1]                                            Net        -        -       0.686     -           3         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count_RNID1281[0]              NOR2       A        In      -         5.796       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count_RNID1281[0]              NOR2       Y        Out     0.432     6.228       -         
un1_cortexm1top_i0ol_2                                         Net        -        -       0.328     -           2         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTExM1Top_l1ol_RNO           NOR3C      C        In      -         6.556       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTExM1Top_l1ol_RNO           NOR3C      Y        Out     0.566     7.123       -         
CORTExM1Top_l1ol_RNO                                           Net        -        -       0.274     -           1         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTExM1Top_l1ol               DFN0C0     D        In      -         7.396       -         
===========================================================================================================================
Total path delay (propagation time + setup) of 8.002 is 3.335(41.7%) logic and 4.668(58.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      8.333
    - Setup time:                            0.606
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.727

    - Propagation time:                      7.254
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 0.473

    Number of logic level(s):                5
    Starting point:                          CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol[0] / Q
    Ending point:                            CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTExM1Top_l1ol / D
    The start point is clocked by            ResetSYNC|UDRCK_inferred_clock [rising] on pin CLK
    The end   point is clocked by            ResetSYNC|UDRCK_inferred_clock [falling] on pin CLK

Instance / Net                                                             Pin      Pin               Arrival     No. of    
Name                                                            Type       Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol[0]             DFN1C0     Q        Out     0.627     0.627       -         
CORTEXM1Top_o0ol[0]                                             Net        -        -       1.420     -           9         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol_RNI71L2[1]     OR2B       B        In      -         2.047       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol_RNI71L2[1]     OR2B       Y        Out     0.534     2.581       -         
un4_cortexm1top_l0ol_1                                          Net        -        -       0.686     -           3         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol_RNISNV3[2]     NOR2A      B        In      -         3.267       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol_RNISNV3[2]     NOR2A      Y        Out     0.328     3.595       -         
un4_cortexm1top_l0ol                                            Net        -        -       1.395     -           8         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count_RNID4D51[4]               MX2        S        In      -         4.990       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.Count_RNID4D51[4]               MX2        Y        Out     0.337     5.327       -         
CORTExM1Top_l0ol[3]                                             Net        -        -       0.328     -           2         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol_RNIK0KL2[3]    NOR2       B        In      -         5.656       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTEXM1Top_o0ol_RNIK0KL2[3]    NOR2       Y        Out     0.550     6.206       -         
un1_cortexm1top_i0ol_0                                          Net        -        -       0.328     -           2         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTExM1Top_l1ol_RNO            NOR3C      A        In      -         6.534       -         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTExM1Top_l1ol_RNO            NOR3C      Y        Out     0.447     6.981       -         
CORTExM1Top_l1ol_RNO                                            Net        -        -       0.274     -           1         
CortexM1Top_0.RS.Dbg_uj\.Ujjtag.CORTExM1Top_l1ol                DFN0C0     D        In      -         7.254       -         
============================================================================================================================
Total path delay (propagation time + setup) of 7.860 is 3.429(43.6%) logic and 4.431(56.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                     Starting                                                                                      Arrival           
Instance             Reference     Type                    Pin           Net                                       Time        Slack 
                     Clock                                                                                                           
-------------------------------------------------------------------------------------------------------------------------------------
CortexM1Top_0.M1     System        CortexM1Integration     HADDR[30]     Z\\CortexM1Top_0_AHBmaster_HADDR_\[30\]\\ 0.000       -4.226
CortexM1Top_0.M1     System        CortexM1Integration     HADDR[28]     Z\\CortexM1Top_0_AHBmaster_HADDR_\[28\]\\ 0.000       -4.167
CortexM1Top_0.M1     System        CortexM1Integration     HADDR[29]     Z\\CortexM1Top_0_AHBmaster_HADDR_\[29\]\\ 0.000       -4.103
CortexM1Top_0.M1     System        CortexM1Integration     HADDR[31]     Z\\CortexM1Top_0_AHBmaster_HADDR_\[31\]\\ 0.000       -3.894
CortexM1Top_0.M1     System        CortexM1Integration     HTRANS[1]     Z\\CortexM1Top_0_AHBmaster_HTRANS_\[1\]\\ 0.000       -3.642
CortexM1Top_0.M1     System        CortexM1Integration     HMASTLOCK     CortexM1Top_0_AHBmaster_HLOCK             0.000       -2.298
CortexM1Top_0.M1     System        CortexM1Integration     HWRITE        CortexM1Top_0_AHBmaster_HWRITE            0.000       7.208 
CortexM1Top_0.M1     System        CortexM1Integration     HADDR[27]     Z\\CortexM1Top_0_AHBmaster_HADDR_\[27\]\\ 0.000       8.675 
CortexM1Top_0.M1     System        CortexM1Integration     HADDR[24]     Z\\CortexM1Top_0_AHBmaster_HADDR_\[24\]\\ 0.000       9.086 
CortexM1Top_0.M1     System        CortexM1Integration     HADDR[26]     Z\\CortexM1Top_0_AHBmaster_HADDR_\[26\]\\ 0.000       9.263 
=====================================================================================================================================


Ending Points with Worst Slack
******************************

                                   Starting                                                 Required           
Instance                           Reference     Type         Pin     Net                   Time         Slack 
                                   Clock                                                                       
---------------------------------------------------------------------------------------------------------------
CoreAHB2APB_0.COREAHB2APB_i1ol     System        DFN1E0C0     D       COReAHB2APB_l11       16.208       -4.226
CoreAHB2APB_0.CoreAHB2APB_ILOL     System        DFN1E0C0     D       CoreAHB2APB_LL1       16.208       -4.226
CoreMemCtrl_0.coREMEMCTRL_i01      System        DFN1P0       D       COREmemctrl_o11_1     16.208       -4.167
CoreAHB2APB_0.COREAHB2APB_i0ol     System        DFN1E0C0     D       CoreAHB2APB_l01       16.208       -4.034
CoreAHB2APB_0.COREAHB2APB_iiOL     System        DFN1E0C0     D       CorEAHB2APB_li1       16.208       -4.034
CoreAHB2APB_0.COREAHB2APB_liol     System        DFN1E0C0     D       COreAHB2APB_OI1       16.208       -4.034
CoreAHB2APB_0.COREAHB2APB_loll     System        DFN1E0C0     D       CoreAHB2APB_oool      16.208       -4.034
CoreAHB2APB_0.COREAHB2APB_oiol     System        DFN1E0C0     D       CoreAHB2APB_IL1       16.208       -4.034
CoreAHB2APB_0.COREAHB2APB_olol     System        DFN1E0C0     D       CoreAHB2APB_IO1       16.208       -4.034
CoreAHB2APB_0.COreAHB2APB_iOOL     System        DFN1E0C0     D       CoreAHB2APB_LO1       16.208       -4.034
===============================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      16.667
    - Setup time:                            0.458
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         16.208

    - Propagation time:                      20.435
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -4.226

    Number of logic level(s):                14
    Starting point:                          CortexM1Top_0.M1 / HADDR[30]
    Ending point:                            CoreAHB2APB_0.COREAHB2APB_i1ol / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            M1webserver_TOP|PLL_sys_0.net_0_inferred_clock [rising] on pin CLK

Instance / Net                                                                                                 Pin           Pin               Arrival     No. of    
Name                                                                                   Type                    Name          Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
CortexM1Top_0.M1                                                                       CortexM1Integration     HADDR[30]     Out     0.000     0.000       -         
Z\\CortexM1Top_0_AHBmaster_HADDR_\[30\]\\                                              Net                     -             -       0.328     -           2         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIGMG8[30]                         MX2                     A             In      -         0.328       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIGMG8[30]                         MX2                     Y             Out     0.492     0.821       -         
CAHBLTio0i[30]                                                                         Net                     -             -       1.454     -           10        
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTILii.CAHBLTol0\.cahbltl1i13_0_a2_0_a4    OR2A                    A             In      -         2.275       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTILii.CAHBLTol0\.cahbltl1i13_0_a2_0_a4    OR2A                    Y             Out     0.396     2.671       -         
N_78                                                                                   Net                     -             -       1.007     -           4         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIV7KP_4[28]                       NOR2                    B             In      -         3.678       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIV7KP_4[28]                       NOR2                    Y             Out     0.438     4.116       -         
CAHBLTi1ll_0_a2_0[12]                                                                  Net                     -             -       0.274     -           1         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIVKH41_1[28]                      NOR2A                   A             In      -         4.390       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIVKH41_1[28]                      NOR2A                   Y             Out     0.534     4.923       -         
CAHBLTili0i[12]                                                                        Net                     -             -       1.420     -           9         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNI0TR81[3]              NOR2B                   B             In      -         6.343       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNI0TR81[3]              NOR2B                   Y             Out     0.534     6.877       -         
N_95                                                                                   Net                     -             -       0.274     -           1         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNIPP1A1[1]              NOR2                    A             In      -         7.151       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNIPP1A1[1]              NOR2                    Y             Out     0.432     7.582       -         
N_75                                                                                   Net                     -             -       0.328     -           2         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNIP8JL4[6]              OR3A                    A             In      -         7.911       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNIP8JL4[6]              OR3A                    Y             Out     0.447     8.357       -         
CAHBLTL01[0]                                                                           Net                     -             -       2.099     -           24        
CoreAHB2APB_0.COREAHB2APB_i0i_RNISC1V9                                                 XAI1                    A             In      -         10.456      -         
CoreAHB2APB_0.COREAHB2APB_i0i_RNISC1V9                                                 XAI1                    Y             Out     0.532     10.989      -         
N_353                                                                                  Net                     -             -       1.810     -           15        
CoreAHB2APB_0.COREAHB2APB_i0i_RNI7VM6U                                                 AO1D                    C             In      -         12.799      -         
CoreAHB2APB_0.COREAHB2APB_i0i_RNI7VM6U                                                 AO1D                    Y             Out     0.538     13.337      -         
un4_coreahb2apb_oli_0                                                                  Net                     -             -       0.274     -           1         
CoreAHB2APB_0.COREAHB2APB_i0i_RNI33FK82                                                NOR2                    A             In      -         13.611      -         
CoreAHB2APB_0.COREAHB2APB_i0i_RNI33FK82                                                NOR2                    Y             Out     0.432     14.043      -         
un4_coreahb2apb_oli                                                                    Net                     -             -       1.420     -           9         
CoreAHB2APB_0.COREAHB2APB_i0i_RNI074TS2                                                NOR2A                   A             In      -         15.462      -         
CoreAHB2APB_0.COREAHB2APB_i0i_RNI074TS2                                                NOR2A                   Y             Out     0.439     15.902      -         
N_334                                                                                  Net                     -             -       0.328     -           2         
CoreAHB2APB_0.COREAHB2APB_o0i_RNIGFUTS2[4]                                             OR3                     C             In      -         16.230      -         
CoreAHB2APB_0.COREAHB2APB_o0i_RNIGFUTS2[4]                                             OR3                     Y             Out     0.581     16.811      -         
N_345                                                                                  Net                     -             -       0.328     -           2         
CoreAHB2APB_0.COREAHB2APB_o0i_RNIDG6VS2_0[4]                                           OR2A                    A             In      -         17.139      -         
CoreAHB2APB_0.COREAHB2APB_o0i_RNIDG6VS2_0[4]                                           OR2A                    Y             Out     0.457     17.596      -         
N_331                                                                                  Net                     -             -       1.926     -           18        
CoreAHB2APB_0.COREAHB2APB_i1ol_RNO                                                     NOR3                    C             In      -         19.522      -         
CoreAHB2APB_0.COREAHB2APB_i1ol_RNO                                                     NOR3                    Y             Out     0.639     20.161      -         
COReAHB2APB_l11                                                                        Net                     -             -       0.274     -           1         
CoreAHB2APB_0.COREAHB2APB_i1ol                                                         DFN1E0C0                D             In      -         20.435      -         
=====================================================================================================================================================================
Total path delay (propagation time + setup) of 20.893 is 7.350(35.2%) logic and 13.543(64.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      16.667
    - Setup time:                            0.458
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         16.208

    - Propagation time:                      20.435
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -4.226

    Number of logic level(s):                14
    Starting point:                          CortexM1Top_0.M1 / HADDR[30]
    Ending point:                            CoreAHB2APB_0.CoreAHB2APB_ILOL / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            M1webserver_TOP|PLL_sys_0.net_0_inferred_clock [rising] on pin CLK

Instance / Net                                                                                                 Pin           Pin               Arrival     No. of    
Name                                                                                   Type                    Name          Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
CortexM1Top_0.M1                                                                       CortexM1Integration     HADDR[30]     Out     0.000     0.000       -         
Z\\CortexM1Top_0_AHBmaster_HADDR_\[30\]\\                                              Net                     -             -       0.328     -           2         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIGMG8[30]                         MX2                     A             In      -         0.328       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIGMG8[30]                         MX2                     Y             Out     0.492     0.821       -         
CAHBLTio0i[30]                                                                         Net                     -             -       1.454     -           10        
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTILii.CAHBLTol0\.cahbltl1i13_0_a2_0_a4    OR2A                    A             In      -         2.275       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTILii.CAHBLTol0\.cahbltl1i13_0_a2_0_a4    OR2A                    Y             Out     0.396     2.671       -         
N_78                                                                                   Net                     -             -       1.007     -           4         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIV7KP_4[28]                       NOR2                    B             In      -         3.678       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIV7KP_4[28]                       NOR2                    Y             Out     0.438     4.116       -         
CAHBLTi1ll_0_a2_0[12]                                                                  Net                     -             -       0.274     -           1         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIVKH41_1[28]                      NOR2A                   A             In      -         4.390       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIVKH41_1[28]                      NOR2A                   Y             Out     0.534     4.923       -         
CAHBLTili0i[12]                                                                        Net                     -             -       1.420     -           9         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNI0TR81[3]              NOR2B                   B             In      -         6.343       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNI0TR81[3]              NOR2B                   Y             Out     0.534     6.877       -         
N_95                                                                                   Net                     -             -       0.274     -           1         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNIPP1A1[1]              NOR2                    A             In      -         7.151       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNIPP1A1[1]              NOR2                    Y             Out     0.432     7.582       -         
N_75                                                                                   Net                     -             -       0.328     -           2         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNIP8JL4[6]              OR3A                    A             In      -         7.911       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNIP8JL4[6]              OR3A                    Y             Out     0.447     8.357       -         
CAHBLTL01[0]                                                                           Net                     -             -       2.099     -           24        
CoreAHB2APB_0.COREAHB2APB_i0i_RNISC1V9                                                 XAI1                    A             In      -         10.456      -         
CoreAHB2APB_0.COREAHB2APB_i0i_RNISC1V9                                                 XAI1                    Y             Out     0.532     10.989      -         
N_353                                                                                  Net                     -             -       1.810     -           15        
CoreAHB2APB_0.COREAHB2APB_i0i_RNI7VM6U                                                 AO1D                    C             In      -         12.799      -         
CoreAHB2APB_0.COREAHB2APB_i0i_RNI7VM6U                                                 AO1D                    Y             Out     0.538     13.337      -         
un4_coreahb2apb_oli_0                                                                  Net                     -             -       0.274     -           1         
CoreAHB2APB_0.COREAHB2APB_i0i_RNI33FK82                                                NOR2                    A             In      -         13.611      -         
CoreAHB2APB_0.COREAHB2APB_i0i_RNI33FK82                                                NOR2                    Y             Out     0.432     14.043      -         
un4_coreahb2apb_oli                                                                    Net                     -             -       1.420     -           9         
CoreAHB2APB_0.COREAHB2APB_i0i_RNI074TS2                                                NOR2A                   A             In      -         15.462      -         
CoreAHB2APB_0.COREAHB2APB_i0i_RNI074TS2                                                NOR2A                   Y             Out     0.439     15.902      -         
N_334                                                                                  Net                     -             -       0.328     -           2         
CoreAHB2APB_0.COREAHB2APB_o0i_RNIGFUTS2[4]                                             OR3                     C             In      -         16.230      -         
CoreAHB2APB_0.COREAHB2APB_o0i_RNIGFUTS2[4]                                             OR3                     Y             Out     0.581     16.811      -         
N_345                                                                                  Net                     -             -       0.328     -           2         
CoreAHB2APB_0.COREAHB2APB_o0i_RNIDG6VS2_0[4]                                           OR2A                    A             In      -         17.139      -         
CoreAHB2APB_0.COREAHB2APB_o0i_RNIDG6VS2_0[4]                                           OR2A                    Y             Out     0.457     17.596      -         
N_331                                                                                  Net                     -             -       1.926     -           18        
CoreAHB2APB_0.CoreAHB2APB_ILOL_RNO                                                     NOR3                    C             In      -         19.522      -         
CoreAHB2APB_0.CoreAHB2APB_ILOL_RNO                                                     NOR3                    Y             Out     0.639     20.161      -         
CoreAHB2APB_LL1                                                                        Net                     -             -       0.274     -           1         
CoreAHB2APB_0.CoreAHB2APB_ILOL                                                         DFN1E0C0                D             In      -         20.435      -         
=====================================================================================================================================================================
Total path delay (propagation time + setup) of 20.893 is 7.350(35.2%) logic and 13.543(64.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      16.667
    - Setup time:                            0.458
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         16.208

    - Propagation time:                      20.375
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -4.167

    Number of logic level(s):                13
    Starting point:                          CortexM1Top_0.M1 / HADDR[28]
    Ending point:                            CoreMemCtrl_0.coREMEMCTRL_i01 / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            M1webserver_TOP|PLL_sys_0.net_0_inferred_clock [rising] on pin CLK

Instance / Net                                                                                          Pin           Pin               Arrival     No. of    
Name                                                                            Type                    Name          Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------
CortexM1Top_0.M1                                                                CortexM1Integration     HADDR[28]     Out     0.000     0.000       -         
Z\\CortexM1Top_0_AHBmaster_HADDR_\[28\]\\                                       Net                     -             -       0.328     -           2         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNINMH8[28]                  MX2                     A             In      -         0.328       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNINMH8[28]                  MX2                     Y             Out     0.492     0.821       -         
CAHBLTio0i[28]                                                                  Net                     -             -       1.926     -           18        
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTli0L_RNIN3FJ                      OR3B                    B             In      -         2.747       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTli0L_RNIN3FJ                      OR3B                    Y             Out     0.516     3.263       -         
N_319                                                                           Net                     -             -       1.007     -           4         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTli0L_RNIVKH41_3                   NOR2                    A             In      -         4.270       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTli0L_RNIVKH41_3                   NOR2                    Y             Out     0.309     4.579       -         
CAHBLTili0i[1]                                                                  Net                     -             -       1.420     -           9         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLToILLLL.CAHBLTIO1I.CAHBLTl01_iv_0_a3_0_0[0]     OR2A                    A             In      -         5.999       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLToILLLL.CAHBLTIO1I.CAHBLTl01_iv_0_a3_0_0[0]     OR2A                    Y             Out     0.396     6.395       -         
CAHBLTl01_iv_0_a3_0_0[0]                                                        Net                     -             -       0.274     -           1         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLToILLLL.CAHBLTIO1I.CAHBLTo0ol_RNIS9C53[6]       OA1B                    B             In      -         6.669       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLToILLLL.CAHBLTIO1I.CAHBLTo0ol_RNIS9C53[6]       OA1B                    Y             Out     0.837     7.506       -         
N_76                                                                            Net                     -             -       0.328     -           2         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLToILLLL.CAHBLTIO1I.CAHBLTo0ol_RNIR88D4[1]       OR2B                    A             In      -         7.834       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLToILLLL.CAHBLTIO1I.CAHBLTo0ol_RNIR88D4[1]       OR2B                    Y             Out     0.415     8.249       -         
CAHBLTL01[0]                                                                    Net                     -             -       1.420     -           9         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLToILLLL.CAHBLTIO1I.CAHBLTo0ol_RNIL6SC9_0[1]     XOR2                    B             In      -         9.669       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLToILLLL.CAHBLTIO1I.CAHBLTo0ol_RNIL6SC9_0[1]     XOR2                    Y             Out     0.534     10.203      -         
CAHBLTl1ol_sn_N_2                                                               Net                     -             -       1.810     -           15        
CoreMemCtrl_0.COREMEMCtrl_i00_0_RNI9RGD9                                        OR2B                    B             In      -         12.014      -         
CoreMemCtrl_0.COREMEMCtrl_i00_0_RNI9RGD9                                        OR2B                    Y             Out     0.534     12.547      -         
un1_corememctrl_iiol_0                                                          Net                     -             -       1.733     -           13        
CoreMemCtrl_0.COREMEMCtrl_i00_0_RNI4DKF61                                       NOR3                    C             In      -         14.281      -         
CoreMemCtrl_0.COREMEMCtrl_i00_0_RNI4DKF61                                       NOR3                    Y             Out     0.581     14.862      -         
un3_corememctrl_iiol                                                            Net                     -             -       1.395     -           8         
CoreMemCtrl_0.COREMEMCtrl_i00_0_RNIC7RFL1_0                                     NOR2A                   A             In      -         16.257      -         
CoreMemCtrl_0.COREMEMCtrl_i00_0_RNIC7RFL1_0                                     NOR2A                   Y             Out     0.534     16.791      -         
N_313_1                                                                         Net                     -             -       1.007     -           4         
CoreMemCtrl_0.coREMEMCTRL_i01_RNO_4                                             NOR2                    B             In      -         17.798      -         
CoreMemCtrl_0.coREMEMCTRL_i01_RNO_4                                             NOR2                    Y             Out     0.550     18.348      -         
COREmemctrl_o11_m                                                               Net                     -             -       0.274     -           1         
CoreMemCtrl_0.coREMEMCTRL_i01_RNO_0                                             OA1C                    C             In      -         18.622      -         
CoreMemCtrl_0.coREMEMCTRL_i01_RNO_0                                             OA1C                    Y             Out     0.414     19.036      -         
N_11                                                                            Net                     -             -       0.274     -           1         
CoreMemCtrl_0.coREMEMCTRL_i01_RNO                                               OA1C                    A             In      -         19.309      -         
CoreMemCtrl_0.coREMEMCTRL_i01_RNO                                               OA1C                    Y             Out     0.793     20.102      -         
COREmemctrl_o11_1                                                               Net                     -             -       0.274     -           1         
CoreMemCtrl_0.coREMEMCTRL_i01                                                   DFN1P0                  D             In      -         20.375      -         
==============================================================================================================================================================
Total path delay (propagation time + setup) of 20.834 is 7.365(35.4%) logic and 13.469(64.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      16.667
    - Setup time:                            0.458
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         16.208

    - Propagation time:                      20.312
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -4.103

    Number of logic level(s):                14
    Starting point:                          CortexM1Top_0.M1 / HADDR[29]
    Ending point:                            CoreAHB2APB_0.COREAHB2APB_i1ol / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            M1webserver_TOP|PLL_sys_0.net_0_inferred_clock [rising] on pin CLK

Instance / Net                                                                                                 Pin           Pin               Arrival     No. of    
Name                                                                                   Type                    Name          Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
CortexM1Top_0.M1                                                                       CortexM1Integration     HADDR[29]     Out     0.000     0.000       -         
Z\\CortexM1Top_0_AHBmaster_HADDR_\[29\]\\                                              Net                     -             -       0.328     -           2         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIOQH8[29]                         MX2                     A             In      -         0.328       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIOQH8[29]                         MX2                     Y             Out     0.484     0.812       -         
CAHBLTio0i[29]                                                                         Net                     -             -       1.299     -           7         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTILii.CAHBLTol0\.cahbltl1i13_0_a2_0_a4    OR2A                    B             In      -         2.111       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTILii.CAHBLTol0\.cahbltl1i13_0_a2_0_a4    OR2A                    Y             Out     0.438     2.548       -         
N_78                                                                                   Net                     -             -       1.007     -           4         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIV7KP_4[28]                       NOR2                    B             In      -         3.555       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIV7KP_4[28]                       NOR2                    Y             Out     0.438     3.993       -         
CAHBLTi1ll_0_a2_0[12]                                                                  Net                     -             -       0.274     -           1         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIVKH41_1[28]                      NOR2A                   A             In      -         4.267       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIVKH41_1[28]                      NOR2A                   Y             Out     0.534     4.801       -         
CAHBLTili0i[12]                                                                        Net                     -             -       1.420     -           9         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNI0TR81[3]              NOR2B                   B             In      -         6.220       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNI0TR81[3]              NOR2B                   Y             Out     0.534     6.754       -         
N_95                                                                                   Net                     -             -       0.274     -           1         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNIPP1A1[1]              NOR2                    A             In      -         7.028       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNIPP1A1[1]              NOR2                    Y             Out     0.432     7.460       -         
N_75                                                                                   Net                     -             -       0.328     -           2         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNIP8JL4[6]              OR3A                    A             In      -         7.788       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNIP8JL4[6]              OR3A                    Y             Out     0.447     8.235       -         
CAHBLTL01[0]                                                                           Net                     -             -       2.099     -           24        
CoreAHB2APB_0.COREAHB2APB_i0i_RNISC1V9                                                 XAI1                    A             In      -         10.333      -         
CoreAHB2APB_0.COREAHB2APB_i0i_RNISC1V9                                                 XAI1                    Y             Out     0.532     10.866      -         
N_353                                                                                  Net                     -             -       1.810     -           15        
CoreAHB2APB_0.COREAHB2APB_i0i_RNI7VM6U                                                 AO1D                    C             In      -         12.676      -         
CoreAHB2APB_0.COREAHB2APB_i0i_RNI7VM6U                                                 AO1D                    Y             Out     0.538     13.214      -         
un4_coreahb2apb_oli_0                                                                  Net                     -             -       0.274     -           1         
CoreAHB2APB_0.COREAHB2APB_i0i_RNI33FK82                                                NOR2                    A             In      -         13.488      -         
CoreAHB2APB_0.COREAHB2APB_i0i_RNI33FK82                                                NOR2                    Y             Out     0.432     13.920      -         
un4_coreahb2apb_oli                                                                    Net                     -             -       1.420     -           9         
CoreAHB2APB_0.COREAHB2APB_i0i_RNI074TS2                                                NOR2A                   A             In      -         15.339      -         
CoreAHB2APB_0.COREAHB2APB_i0i_RNI074TS2                                                NOR2A                   Y             Out     0.439     15.779      -         
N_334                                                                                  Net                     -             -       0.328     -           2         
CoreAHB2APB_0.COREAHB2APB_o0i_RNIGFUTS2[4]                                             OR3                     C             In      -         16.107      -         
CoreAHB2APB_0.COREAHB2APB_o0i_RNIGFUTS2[4]                                             OR3                     Y             Out     0.581     16.688      -         
N_345                                                                                  Net                     -             -       0.328     -           2         
CoreAHB2APB_0.COREAHB2APB_o0i_RNIDG6VS2_0[4]                                           OR2A                    A             In      -         17.017      -         
CoreAHB2APB_0.COREAHB2APB_o0i_RNIDG6VS2_0[4]                                           OR2A                    Y             Out     0.457     17.474      -         
N_331                                                                                  Net                     -             -       1.926     -           18        
CoreAHB2APB_0.COREAHB2APB_i1ol_RNO                                                     NOR3                    C             In      -         19.399      -         
CoreAHB2APB_0.COREAHB2APB_i1ol_RNO                                                     NOR3                    Y             Out     0.639     20.038      -         
COReAHB2APB_l11                                                                        Net                     -             -       0.274     -           1         
CoreAHB2APB_0.COREAHB2APB_i1ol                                                         DFN1E0C0                D             In      -         20.312      -         
=====================================================================================================================================================================
Total path delay (propagation time + setup) of 20.770 is 7.382(35.5%) logic and 13.388(64.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      16.667
    - Setup time:                            0.458
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         16.208

    - Propagation time:                      20.312
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -4.103

    Number of logic level(s):                14
    Starting point:                          CortexM1Top_0.M1 / HADDR[29]
    Ending point:                            CoreAHB2APB_0.CoreAHB2APB_ILOL / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            M1webserver_TOP|PLL_sys_0.net_0_inferred_clock [rising] on pin CLK

Instance / Net                                                                                                 Pin           Pin               Arrival     No. of    
Name                                                                                   Type                    Name          Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
CortexM1Top_0.M1                                                                       CortexM1Integration     HADDR[29]     Out     0.000     0.000       -         
Z\\CortexM1Top_0_AHBmaster_HADDR_\[29\]\\                                              Net                     -             -       0.328     -           2         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIOQH8[29]                         MX2                     A             In      -         0.328       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIOQH8[29]                         MX2                     Y             Out     0.484     0.812       -         
CAHBLTio0i[29]                                                                         Net                     -             -       1.299     -           7         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTILii.CAHBLTol0\.cahbltl1i13_0_a2_0_a4    OR2A                    B             In      -         2.111       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTILii.CAHBLTol0\.cahbltl1i13_0_a2_0_a4    OR2A                    Y             Out     0.438     2.548       -         
N_78                                                                                   Net                     -             -       1.007     -           4         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIV7KP_4[28]                       NOR2                    B             In      -         3.555       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIV7KP_4[28]                       NOR2                    Y             Out     0.438     3.993       -         
CAHBLTi1ll_0_a2_0[12]                                                                  Net                     -             -       0.274     -           1         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIVKH41_1[28]                      NOR2A                   A             In      -         4.267       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTolllll.CAHBLTll0l_RNIVKH41_1[28]                      NOR2A                   Y             Out     0.534     4.801       -         
CAHBLTili0i[12]                                                                        Net                     -             -       1.420     -           9         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNI0TR81[3]              NOR2B                   B             In      -         6.220       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNI0TR81[3]              NOR2B                   Y             Out     0.534     6.754       -         
N_95                                                                                   Net                     -             -       0.274     -           1         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNIPP1A1[1]              NOR2                    A             In      -         7.028       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNIPP1A1[1]              NOR2                    Y             Out     0.432     7.460       -         
N_75                                                                                   Net                     -             -       0.328     -           2         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNIP8JL4[6]              OR3A                    A             In      -         7.788       -         
CoreAHBLite_0.CAHBLTLLO1LL.CAHBLTioilll.CAHBLTIO1I.CAHBLTo0ol_RNIP8JL4[6]              OR3A                    Y             Out     0.447     8.235       -         
CAHBLTL01[0]                                                                           Net                     -             -       2.099     -           24        
CoreAHB2APB_0.COREAHB2APB_i0i_RNISC1V9                                                 XAI1                    A             In      -         10.333      -         
CoreAHB2APB_0.COREAHB2APB_i0i_RNISC1V9                                                 XAI1                    Y             Out     0.532     10.866      -         
N_353                                                                                  Net                     -             -       1.810     -           15        
CoreAHB2APB_0.COREAHB2APB_i0i_RNI7VM6U                                                 AO1D                    C             In      -         12.676      -         
CoreAHB2APB_0.COREAHB2APB_i0i_RNI7VM6U                                                 AO1D                    Y             Out     0.538     13.214      -         
un4_coreahb2apb_oli_0                                                                  Net                     -             -       0.274     -           1         
CoreAHB2APB_0.COREAHB2APB_i0i_RNI33FK82                                                NOR2                    A             In      -         13.488      -         
CoreAHB2APB_0.COREAHB2APB_i0i_RNI33FK82                                                NOR2                    Y             Out     0.432     13.920      -         
un4_coreahb2apb_oli                                                                    Net                     -             -       1.420     -           9         
CoreAHB2APB_0.COREAHB2APB_i0i_RNI074TS2                                                NOR2A                   A             In      -         15.339      -         
CoreAHB2APB_0.COREAHB2APB_i0i_RNI074TS2                                                NOR2A                   Y             Out     0.439     15.779      -         
N_334                                                                                  Net                     -             -       0.328     -           2         
CoreAHB2APB_0.COREAHB2APB_o0i_RNIGFUTS2[4]                                             OR3                     C             In      -         16.107      -         
CoreAHB2APB_0.COREAHB2APB_o0i_RNIGFUTS2[4]                                             OR3                     Y             Out     0.581     16.688      -         
N_345                                                                                  Net                     -             -       0.328     -           2         
CoreAHB2APB_0.COREAHB2APB_o0i_RNIDG6VS2_0[4]                                           OR2A                    A             In      -         17.017      -         
CoreAHB2APB_0.COREAHB2APB_o0i_RNIDG6VS2_0[4]                                           OR2A                    Y             Out     0.457     17.474      -         
N_331                                                                                  Net                     -             -       1.926     -           18        
CoreAHB2APB_0.CoreAHB2APB_ILOL_RNO                                                     NOR3                    C             In      -         19.399      -         
CoreAHB2APB_0.CoreAHB2APB_ILOL_RNO                                                     NOR3                    Y             Out     0.639     20.038      -         
CoreAHB2APB_LL1                                                                        Net                     -             -       0.274     -           1         
CoreAHB2APB_0.CoreAHB2APB_ILOL                                                         DFN1E0C0                D             In      -         20.312      -         
=====================================================================================================================================================================
Total path delay (propagation time + setup) of 20.770 is 7.382(35.5%) logic and 13.388(64.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Target Part: M1AFS1500_FBGA256_-1
Report for cell M1webserver_TOP.def_arch
  Core Cell usage:
              cell count     area count*area
              AND2    78      1.0       78.0
             AND2A    11      1.0       11.0
              AND3    74      1.0       74.0
             AND3A     1      1.0        1.0
               AO1   169      1.0      169.0
              AO13     6      1.0        6.0
              AO15     1      1.0        1.0
              AO16     1      1.0        1.0
              AO18     4      1.0        4.0
              AO1A   111      1.0      111.0
              AO1B   141      1.0      141.0
              AO1C   131      1.0      131.0
              AO1D    70      1.0       70.0
              AOI1    82      1.0       82.0
             AOI1A    18      1.0       18.0
             AOI1B   322      1.0      322.0
              AOI5     2      1.0        2.0
               AX1     5      1.0        5.0
              AX1A    15      1.0       15.0
              AX1B    23      1.0       23.0
              AX1C    20      1.0       20.0
              AX1D    30      1.0       30.0
              AX1E    17      1.0       17.0
             AXOI5     2      1.0        2.0
             AXOI7     3      1.0        3.0
              BUFF     1      1.0        1.0
            CLKINT    10      0.0        0.0
   CortexM1Integration     1      0.0        0.0
               GND    92      0.0        0.0
               INV    50      1.0       50.0
              MAJ3     5      1.0        5.0
              MIN3     3      1.0        3.0
               MX2   894      1.0      894.0
              MX2A    12      1.0       12.0
              MX2B    36      1.0       36.0
              MX2C   515      1.0      515.0
             NAND2    30      1.0       30.0
              NOR2   412      1.0      412.0
             NOR2A   495      1.0      495.0
             NOR2B   414      1.0      414.0
              NOR3   135      1.0      135.0
             NOR3A   147      1.0      147.0
             NOR3B   232      1.0      232.0
             NOR3C   304      1.0      304.0
               OA1    76      1.0       76.0
              OA1A   163      1.0      163.0
              OA1B    57      1.0       57.0
              OA1C    57      1.0       57.0
              OAI1    87      1.0       87.0
               OR2   355      1.0      355.0
              OR2A   590      1.0      590.0
              OR2B   812      1.0      812.0
               OR3   118      1.0      118.0
              OR3A   201      1.0      201.0
              OR3B   161      1.0      161.0
              OR3C   277      1.0      277.0
               PLL     1      0.0        0.0
            PLLINT     1      0.0        0.0
               VCC    92      0.0        0.0
               XA1    18      1.0       18.0
              XA1A    23      1.0       23.0
              XA1B   174      1.0      174.0
              XA1C    28      1.0       28.0
              XAI1     6      1.0        6.0
             XAI1A     3      1.0        3.0
             XNOR2   139      1.0      139.0
             XNOR3     6      1.0        6.0
               XO1    54      1.0       54.0
              XO1A    29      1.0       29.0
              XOR2   368      1.0      368.0
              XOR3    13      1.0       13.0
              ZOR3     1      1.0        1.0


            DFI1C1     1      1.0        1.0
            DFI1P0     1      1.0        1.0
            DFI1P1     1      1.0        1.0
            DFN0C0     5      1.0        5.0
            DFN0P0     3      1.0        3.0
              DFN1    17      1.0       17.0
            DFN1C0   823      1.0      823.0
          DFN1E0C0   370      1.0      370.0
          DFN1E0P0   241      1.0      241.0
            DFN1E1   364      1.0      364.0
          DFN1E1C0  1023      1.0     1023.0
          DFN1E1P0   275      1.0      275.0
            DFN1P0   238      1.0      238.0
          FIFO4K18     2      0.0        0.0
               NVM     2      0.0        0.0
            RAM4K9    28      0.0        0.0
                   -----          ----------
             TOTAL 12429             12200.0


  IO Cell usage:
              cell count
                AB     1
             BIBUF    35
             INBUF    15
           INBUF_A     3
            OUTBUF    36
           TRIBUFF     4
             UJTAG     1
                   -----
             TOTAL    95


Core Cells         : 12200 of 38400 (32%)
IO Cells           : 95 of 252 (38%)

  RAM/ROM Usage Summary
Block Rams : 28 of 60 (46%)

Mapper successful!
Process took 0h:00m:37s realtime, 0h:00m:35s cputime
# Fri Aug 20 18:01:14 2010

###########################################################]