m255
K3
13
cModel Technology
Z0 dD:\DATA\Libero_Projects\M1Webserver_HW_v1\simulation
Pcomponents
Z1 DPx4 ieee 14 std_logic_1164 0 22 GH1=`jDDBJ=`LM;:Ak`kf2
Z2 w1280393952
8D:/DATA/Libero_Projects/M1Webserver_HW_v1/component/Actel/DirectCore/CoreGPIO/3.0.120/rtl/vhdl/core/components.vhd
FD:/DATA/Libero_Projects/M1Webserver_HW_v1/component/Actel/DirectCore/CoreGPIO/3.0.120/rtl/vhdl/core/components.vhd
l0
L8
Vi]QgP^0f`SF0l>fCR;En41
!s100 R>Yzc5j0]9[MokK6cebWS3
Z3 OW;C;6.5d;42
31
Z4 Mx1 4 ieee 14 std_logic_1164
Z5 o-93 -explicit -work COREGPIO_LIB -O0
Ecoregpio
R2
Z6 DPx3 std 6 textio 0 22 m2KQDRRhmF833<<DjYdL70
Z7 DPx8 synopsys 10 attributes 0 22 2Q8I4L@H0S1aHEXkjUYDC1
Z8 DPx4 ieee 14 std_logic_misc 0 22 D2f;@P3IKJA9T^H8HI[9K0
Z9 DPx4 work 12 coregpio_pkg 0 22 FibRXa6d3`h=VQSmEz[CY2
Z10 DPx4 ieee 11 numeric_std 0 22 =NSdli^?T5OD8;4F<blj<3
Z11 DPx4 ieee 15 std_logic_arith 0 22 GJbAT?7@hRQU9IQ702DT]2
Z12 DPx4 ieee 18 std_logic_unsigned 0 22 hEMVMlaNCR^<OOoVNV;m90
R1
Z13 8D:/DATA/Libero_Projects/M1Webserver_HW_v1/component/Actel/DirectCore/CoreGPIO/3.0.120/rtl/vhdl/core/coregpio.vhd
Z14 FD:/DATA/Libero_Projects/M1Webserver_HW_v1/component/Actel/DirectCore/CoreGPIO/3.0.120/rtl/vhdl/core/coregpio.vhd
l0
L29
Vm2_3ZNz>;6o<a9YI05I[72
R3
31
R5
!s100 h=[0>McK^R@VAd;^aEN2<2
Artl
R6
R7
R8
R9
R10
R11
R12
R1
DEx4 work 8 coregpio 0 22 m2_3ZNz>;6o<a9YI05I[72
l367
L184
VdTg;4[PlJWT=hP[TnoSZ;3
!s100 h3<QCRX2^UaIS>3VizV^62
R3
31
Mx8 4 ieee 14 std_logic_1164
Mx7 4 ieee 18 std_logic_unsigned
Mx6 4 ieee 15 std_logic_arith
Mx5 4 ieee 11 numeric_std
Mx4 4 work 12 coregpio_pkg
Z15 Mx3 4 ieee 14 std_logic_misc
Z16 Mx2 8 synopsys 10 attributes
Z17 Mx1 3 std 6 textio
R5
Pcoregpio_pkg
R6
R7
R8
R12
R11
R1
R2
Z18 8D:/DATA/Libero_Projects/M1Webserver_HW_v1/component/Actel/DirectCore/CoreGPIO/3.0.120/rtl/vhdl/core/coregpio_pkg.vhd
Z19 FD:/DATA/Libero_Projects/M1Webserver_HW_v1/component/Actel/DirectCore/CoreGPIO/3.0.120/rtl/vhdl/core/coregpio_pkg.vhd
l0
L36
VFibRXa6d3`h=VQSmEz[CY2
R3
31
b1
Z20 Mx6 4 ieee 14 std_logic_1164
Z21 Mx5 4 ieee 15 std_logic_arith
Z22 Mx4 4 ieee 18 std_logic_unsigned
R15
R16
R17
R5
!s100 IgFjZWgnCoG60@@1k96X:1
Bbody
DBx4 work 12 coregpio_pkg 0 22 FibRXa6d3`h=VQSmEz[CY2
R6
R7
R8
R12
R11
R1
l0
L63
VCbnO[?4E5jhaGgH:@efJY1
R3
31
R20
R21
R22
R15
R16
R17
R5
nbody
!s100 oBRbBlf?:05aM>=3felAH0
