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                            Global Usage Report
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Product: Designer
Release: v10.1 SP1
Version: 10.1.1.6
Date: Mon Nov 19 10:32:35 2012
Design Name: SF_Zi1  Family: SmartFusion  Die: A2F500M3G  Package: 484 FBGA
Design State: Post-Layout

The following nets have been routed to a chip global resource:

    Fanout            Name
    ----------------------
    158               Net   : FAB_CLK
                      Driver: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1
    109               Net   : TRSTB_c
                      Driver: COREABC_0/RSTSYNC2_RNIS3FD/U_CLKSRC/U_GL
    73                Net   : COREABC_0/SMADDR[0]
                      Driver: COREABC_0/SMADDR_RNI7GG6[0]/U_CLKSRC/U_GL
    80                Net   : COREABC_0/SMADDR[1]
                      Driver: COREABC_0/SMADDR_RNI8GG6[1]/U_CLKSRC/U_GL




