********************************************************************
                            Global Net Report
********************************************************************
  
Product: Designer
Release: v10.1 SP1
Version: 10.1.1.6
Date: Mon Nov 19 10:32:34 2012
Design Name: SF_Zi1  Family: SmartFusion  Die: A2F500M3G  Package: 484 FBGA


Automatic Global Net Placement Result:
Status: Global net placement completed successfully


Global Nets Information:

        |-----------------------------------------------------|
        |Global Nets         |Loads                           |
        |-----------------------------------------------------|
        |Name                |Core      |IO        |RAM       |
        |-----------------------------------------------------|
        |COREABC_0/SMADDR[0] |       73 |        0 |        0 |
        |-----------------------------------------------------|
        |COREABC_0/SMADDR[1] |       80 |        0 |        0 |
        |-----------------------------------------------------|
        |FAB_CLK             |      156 |        0 |       32 |
        |-----------------------------------------------------|
        |TRSTB_c             |      107 |        1 |       32 |
        |-----------------------------------------------------|

Nets Sharing Loads:

        |-------------------------------------------|
        |Global Net          |Shares Loads With ... |
        |-------------------------------------------|
        |COREABC_0/SMADDR[0] |COREABC_0/SMADDR[1]   |
        |-------------------------------------------|
        |COREABC_0/SMADDR[1] |COREABC_0/SMADDR[0]   |
        |-------------------------------------------|
        |FAB_CLK             |TRSTB_c               |
        |-------------------------------------------|
        |TRSTB_c             |FAB_CLK               |
        |-------------------------------------------|

Summary of Global Net Placement:

        |------------------------------------------------------------------------|
        |Global Net          |Assignment          |Violation                     |
        |------------------------------------------------------------------------|
        |COREABC_0/SMADDR[0] |MIDDLE_RIGHT        |                              |
        |------------------------------------------------------------------------|
        |COREABC_0/SMADDR[1] |MIDDLE_RIGHT        |                              |
        |------------------------------------------------------------------------|
        |FAB_CLK             |MIDDLE_LEFT         |                              |
        |------------------------------------------------------------------------|
        |TRSTB_c             |MIDDLE_RIGHT        |                              |
        |------------------------------------------------------------------------|
