@W: MO111 :"c:\libero 10.1\lpf_ac382_df\a2f200\zeroization\component\work\sf_zi1_mss\mss_ccc_0\sf_zi1_mss_tmp_mss_ccc_0_mss_ccc.v":64:7:64:18|Tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\libero 10.1\lpf_ac382_df\a2f200\zeroization\component\work\sf_zi1_mss\mss_ccc_0\sf_zi1_mss_tmp_mss_ccc_0_mss_ccc.v":63:7:63:20|Tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\libero 10.1\lpf_ac382_df\a2f200\zeroization\component\work\sf_zi1_mss\mss_ccc_0\sf_zi1_mss_tmp_mss_ccc_0_mss_ccc.v":62:7:62:18|Tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO129 :"c:\libero 10.1\lpf_ac382_df\a2f200\zeroization\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Sequential instance COREABC_0.UROM.INSTR_SLOT[1] reduced to a combinational gate by constant propagation
@W: MT420 |Found inferred clock SF_Zi1_MSS|MSS_ADLIB_INST_EMCCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:SF_Zi1_MSS_0.MSS_ADLIB_INST_EMCCLK"
