Timing Report Min Delay Analysis

SmartTime Version v10.0 SP2
Actel Corporation - Actel Designer Software Release v10.0 SP2 (Version 10.0.20.2)
Copyright (c) 1989-2012
Date: Mon Jul 30 14:47:22 2012


Design: SF_Zi1
Family: SmartFusion
Die: A2F200M3F
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                35.856
Frequency (MHz):            27.889
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        -0.197
External Hold (ns):         1.979
Min Clock-To-Out (ns):      6.987
Max Clock-To-Out (ns):      14.702

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        -5.434
External Hold (ns):         4.176
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               SF_Zi1_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      7.328
Max Clock-To-Out (ns):      13.284

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        COREABC_0/RSTSYNC1:CLK
  To:                          COREABC_0/RSTSYNC2:D
  Delay (ns):                  0.399
  Slack (ns):                  0.382
  Arrival (ns):                4.720
  Required (ns):               4.338
  Hold (ns):                   0.000

Path 2
  From:                        COREABC_0/STBFLAG:CLK
  To:                          COREABC_0/STD_ACCUM_NEG:E
  Delay (ns):                  0.422
  Slack (ns):                  0.403
  Arrival (ns):                4.757
  Required (ns):               4.354
  Hold (ns):                   0.000

Path 3
  From:                        COREABC_0/STBFLAG:CLK
  To:                          COREABC_0/STD_ACCUM_ZERO:E
  Delay (ns):                  0.422
  Slack (ns):                  0.403
  Arrival (ns):                4.757
  Required (ns):               4.354
  Hold (ns):                   0.000

Path 4
  From:                        COREABC_0/STBRAM:CLK
  To:                          COREABC_0/URAM.UR/UG3.UR_xhdl12/Ram256x16_R0C0:REN
  Delay (ns):                  0.524
  Slack (ns):                  0.429
  Arrival (ns):                4.920
  Required (ns):               4.491
  Hold (ns):                   0.000

Path 5
  From:                        iap_0/currentState[0]:CLK
  To:                          iap_0/currentState[0]:D
  Delay (ns):                  0.703
  Slack (ns):                  0.618
  Arrival (ns):                5.682
  Required (ns):               5.064
  Hold (ns):                   0.000


Expanded Path 1
  From: COREABC_0/RSTSYNC1:CLK
  To: COREABC_0/RSTSYNC2:D
  data arrival time                              4.720
  data required time                         -   4.338
  slack                                          0.382
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.286          net: FAB_CLK
  4.321                        COREABC_0/RSTSYNC1:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.570                        COREABC_0/RSTSYNC1:Q (r)
               +     0.150          net: COREABC_0/RSTSYNC1
  4.720                        COREABC_0/RSTSYNC2:D (r)
                                    
  4.720                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.303          net: FAB_CLK
  4.338                        COREABC_0/RSTSYNC2:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.338                        COREABC_0/RSTSYNC2:D
                                    
  4.338                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        TDO
  To:                          iap_0/datareg[15]:D
  Delay (ns):                  2.414
  Slack (ns):
  Arrival (ns):                2.414
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          1.979


Expanded Path 1
  From: TDO
  To: iap_0/datareg[15]:D
  data arrival time                              2.414
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TDO (f)
               +     0.000          net: TDO
  0.000                        TDO_pad/U0/U0:PAD (f)
               +     0.277          cell: ADLIB:IOPAD_IN
  0.277                        TDO_pad/U0/U0:Y (f)
               +     0.000          net: TDO_pad/U0/NET1
  0.277                        TDO_pad/U0/U1:YIN (f)
               +     0.017          cell: ADLIB:IOIN_IB
  0.294                        TDO_pad/U0/U1:Y (f)
               +     1.277          net: TDO_c
  1.571                        iap_0/datareg_RNO_0[15]:A (f)
               +     0.274          cell: ADLIB:NOR2A
  1.845                        iap_0/datareg_RNO_0[15]:Y (f)
               +     0.152          net: iap_0/datareg_17_1_a2_0_0[15]
  1.997                        iap_0/datareg_RNO[15]:A (f)
               +     0.269          cell: ADLIB:MX2B
  2.266                        iap_0/datareg_RNO[15]:Y (f)
               +     0.148          net: iap_0/datareg_17[15]
  2.414                        iap_0/datareg[15]:D (f)
                                    
  2.414                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  N/C
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.358          net: FAB_CLK
  N/C                          iap_0/datareg[15]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1E1
  N/C                          iap_0/datareg[15]:D


END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        COREABC_0/RSTSYNC2:CLK
  To:                          TRSTB
  Delay (ns):                  2.664
  Slack (ns):
  Arrival (ns):                6.987
  Required (ns):
  Clock to Out (ns):           6.987

Path 2
  From:                        COREABC_0/IO_OUT[7]:CLK
  To:                          IO_OUT[7]
  Delay (ns):                  2.867
  Slack (ns):
  Arrival (ns):                7.197
  Required (ns):
  Clock to Out (ns):           7.197

Path 3
  From:                        COREABC_0/IO_OUT[5]:CLK
  To:                          IO_OUT[5]
  Delay (ns):                  2.893
  Slack (ns):
  Arrival (ns):                7.237
  Required (ns):
  Clock to Out (ns):           7.237

Path 4
  From:                        COREABC_0/IO_OUT[1]:CLK
  To:                          IO_OUT[1]
  Delay (ns):                  2.948
  Slack (ns):
  Arrival (ns):                7.303
  Required (ns):
  Clock to Out (ns):           7.303

Path 5
  From:                        COREABC_0/IO_OUT[0]:CLK
  To:                          IO_OUT[0]
  Delay (ns):                  2.983
  Slack (ns):
  Arrival (ns):                7.338
  Required (ns):
  Clock to Out (ns):           7.338


Expanded Path 1
  From: COREABC_0/RSTSYNC2:CLK
  To: TRSTB
  data arrival time                              6.987
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.288          net: FAB_CLK
  4.323                        COREABC_0/RSTSYNC2:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.572                        COREABC_0/RSTSYNC2:Q (r)
               +     0.420          net: COREABC_0/RSTSYNC2
  4.992                        COREABC_0/RSTSYNC2_RNIS3FD/U_CLKSRC:A (r)
               +     0.329          cell: ADLIB:CLKSRC
  5.321                        COREABC_0/RSTSYNC2_RNIS3FD/U_CLKSRC:Y (r)
               +     0.299          net: TRSTB_c
  5.620                        TRSTB_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  5.899                        TRSTB_pad/U0/U1:DOUT (r)
               +     0.000          net: TRSTB_pad/U0/NET1
  5.899                        TRSTB_pad/U0/U0:D (r)
               +     1.088          cell: ADLIB:IOPAD_TRI
  6.987                        TRSTB_pad/U0/U0:PAD (r)
               +     0.000          net: TRSTB
  6.987                        TRSTB (r)
                                    
  6.987                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  N/C
                                    
  N/C                          TRSTB (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        COREABC_0/RSTSYNC2:CLK
  To:                          iap_0/currentState[2]:PRE
  Delay (ns):                  1.303
  Slack (ns):                  0.434
  Arrival (ns):                5.626
  Required (ns):               5.192
  Removal (ns):                0.000
  Skew (ns):                   -0.869

Path 2
  From:                        COREABC_0/RSTSYNC2:CLK
  To:                          iap_0/currentState[0]:PRE
  Delay (ns):                  1.302
  Slack (ns):                  0.561
  Arrival (ns):                5.625
  Required (ns):               5.064
  Removal (ns):                0.000
  Skew (ns):                   -0.741

Path 3
  From:                        COREABC_0/RSTSYNC2:CLK
  To:                          iap_0/currentState[1]:PRE
  Delay (ns):                  1.303
  Slack (ns):                  0.615
  Arrival (ns):                5.626
  Required (ns):               5.011
  Removal (ns):                0.000
  Skew (ns):                   -0.688

Path 4
  From:                        COREABC_0/RSTSYNC2:CLK
  To:                          iap_0/currentState[3]:PRE
  Delay (ns):                  1.302
  Slack (ns):                  0.848
  Arrival (ns):                5.625
  Required (ns):               4.777
  Removal (ns):                0.000
  Skew (ns):                   -0.454

Path 5
  From:                        COREABC_0/RSTSYNC2:CLK
  To:                          COREABC_0/URAM.UR/UG3.UR_xhdl12/Ram256x16_R0C0:RESET
  Delay (ns):                  1.415
  Slack (ns):                  1.071
  Arrival (ns):                5.738
  Required (ns):               4.667
  Removal (ns):                0.170
  Skew (ns):                   -0.174


Expanded Path 1
  From: COREABC_0/RSTSYNC2:CLK
  To: iap_0/currentState[2]:PRE
  data arrival time                              5.626
  data required time                         -   5.192
  slack                                          0.434
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.288          net: FAB_CLK
  4.323                        COREABC_0/RSTSYNC2:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.572                        COREABC_0/RSTSYNC2:Q (r)
               +     0.420          net: COREABC_0/RSTSYNC2
  4.992                        COREABC_0/RSTSYNC2_RNIS3FD/U_CLKSRC:A (r)
               +     0.329          cell: ADLIB:CLKSRC
  5.321                        COREABC_0/RSTSYNC2_RNIS3FD/U_CLKSRC:Y (r)
               +     0.305          net: TRSTB_c
  5.626                        iap_0/currentState[2]:PRE (r)
                                    
  5.626                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.299          net: FAB_CLK
  4.334                        iap_0/tckEn_RNIFJOL:B (r)
               +     0.221          cell: ADLIB:OR2A
  4.555                        iap_0/tckEn_RNIFJOL:Y (r)
               +     0.637          net: TCK_c
  5.192                        iap_0/currentState[2]:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1P0
  5.192                        iap_0/currentState[2]:PRE
                                    
  5.192                        data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

Path 1
  From:                        NSYSRESET
  To:                          COREABC_0/RSTSYNC2:CLR
  Delay (ns):                  0.574
  Slack (ns):
  Arrival (ns):                0.574
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       3.805

Path 2
  From:                        NSYSRESET
  To:                          COREABC_0/RSTSYNC1:CLR
  Delay (ns):                  0.572
  Slack (ns):
  Arrival (ns):                0.572
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       3.805


Expanded Path 1
  From: NSYSRESET
  To: COREABC_0/RSTSYNC2:CLR
  data arrival time                              0.574
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        NSYSRESET (r)
               +     0.000          net: NSYSRESET
  0.000                        NSYSRESET_pad/U0/U0:PAD (r)
               +     0.391          cell: ADLIB:IOPAD_IN
  0.391                        NSYSRESET_pad/U0/U0:Y (r)
               +     0.000          net: NSYSRESET_pad/U0/NET1
  0.391                        NSYSRESET_pad/U0/U1:YIN (r)
               +     0.018          cell: ADLIB:IOIN_IB
  0.409                        NSYSRESET_pad/U0/U1:Y (r)
               +     0.165          net: NSYSRESET_c
  0.574                        COREABC_0/RSTSYNC2:CLR (r)
                                    
  0.574                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  N/C
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.344          net: FAB_CLK
  N/C                          COREABC_0/RSTSYNC2:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C0
  N/C                          COREABC_0/RSTSYNC2:CLR


END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin SF_Zi1_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          SF_Zi1_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.277
  Slack (ns):
  Arrival (ns):                0.277
  Required (ns):
  Hold (ns):                   1.358
  External Hold (ns):          4.176


Expanded Path 1
  From: MSS_RESET_N
  To: SF_Zi1_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.277
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        SF_Zi1_MSS_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.277          cell: ADLIB:IOPAD_IN
  0.277                        SF_Zi1_MSS_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: SF_Zi1_MSS_0/MSS_RESET_0_MSS_RESET_N_Y
  0.277                        SF_Zi1_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.277                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  N/C
               +     0.371          net: SF_Zi1_MSS_0/GLA0
  N/C                          SF_Zi1_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.358          Library hold time: ADLIB:MSS_APB_IP
  N/C                          SF_Zi1_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain SF_Zi1_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          TCK
  Delay (ns):                  7.328
  Slack (ns):
  Arrival (ns):                7.328
  Required (ns):
  Clock to Out (ns):           7.328


Expanded Path 1
  From: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: TCK
  data arrival time                              7.328
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        SF_Zi1_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT
               +     0.000          Clock source
  0.000                        SF_Zi1_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT (r)
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/N_CLKA_RCOSC
  0.000                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     4.035          cell: ADLIB:MSS_CCC_IP
  4.035                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.299          net: FAB_CLK
  4.334                        iap_0/tckEn_RNIFJOL:B (r)
               +     0.221          cell: ADLIB:OR2A
  4.555                        iap_0/tckEn_RNIFJOL:Y (r)
               +     1.428          net: TCK_c
  5.983                        TCK_pad/U0/U1:D (r)
               +     0.257          cell: ADLIB:IOTRI_OB_EB
  6.240                        TCK_pad/U0/U1:DOUT (r)
               +     0.000          net: TCK_pad/U0/NET1
  6.240                        TCK_pad/U0/U0:D (r)
               +     1.088          cell: ADLIB:IOPAD_TRI
  7.328                        TCK_pad/U0/U0:PAD (r)
               +     0.000          net: TCK
  7.328                        TCK (r)
                                    
  7.328                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT
               +     0.000          Clock source
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT (r)
                                    
  N/C                          TCK (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

