Timing Report Max Delay Analysis

SmartTime Version v10.0 SP2
Actel Corporation - Actel Designer Software Release v10.0 SP2 (Version 10.0.20.2)
Copyright (c) 1989-2012
Date: Mon Jul 30 14:47:22 2012


Design: SF_Zi1
Family: SmartFusion
Die: A2F200M3F
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                35.856
Frequency (MHz):            27.889
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        -0.197
External Hold (ns):         1.979
Min Clock-To-Out (ns):      6.987
Max Clock-To-Out (ns):      14.702

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        -5.434
External Hold (ns):         4.176
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               SF_Zi1_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      7.328
Max Clock-To-Out (ns):      13.284

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        iap_0/TMS:CLK
  To:                          iap_0/tckCnt[7]:D
  Delay (ns):                  16.428
  Slack (ns):                  7.072
  Arrival (ns):                23.276
  Required (ns):               30.348
  Setup (ns):                  0.490
  Minimum Period (ns):         35.856

Path 2
  From:                        iap_0/TMS:CLK
  To:                          iap_0/tckCnt[5]:D
  Delay (ns):                  15.669
  Slack (ns):                  7.848
  Arrival (ns):                22.517
  Required (ns):               30.365
  Setup (ns):                  0.490
  Minimum Period (ns):         34.304

Path 3
  From:                        iap_0/TMS:CLK
  To:                          iap_0/tckCnt[6]:D
  Delay (ns):                  15.637
  Slack (ns):                  7.861
  Arrival (ns):                22.485
  Required (ns):               30.346
  Setup (ns):                  0.490
  Minimum Period (ns):         34.278

Path 4
  From:                        iap_0/TMS:CLK
  To:                          iap_0/tckCnt[4]:D
  Delay (ns):                  15.350
  Slack (ns):                  8.159
  Arrival (ns):                22.198
  Required (ns):               30.357
  Setup (ns):                  0.490
  Minimum Period (ns):         33.682

Path 5
  From:                        iap_0/TMS:CLK
  To:                          iap_0/tckCnt[3]:D
  Delay (ns):                  13.103
  Slack (ns):                  10.374
  Arrival (ns):                19.951
  Required (ns):               30.325
  Setup (ns):                  0.522
  Minimum Period (ns):         29.252


Expanded Path 1
  From: iap_0/TMS:CLK
  To: iap_0/tckCnt[7]:D
  data required time                             30.348
  data arrival time                          -   23.276
  slack                                          7.072
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (f)
               +     5.249          Clock generation
  5.249
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (f)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (f)
               +     0.611          net: FAB_CLK
  5.860                        iap_0/tckEn_RNIFJOL:B (f)
               +     0.588          cell: ADLIB:OR2A
  6.448                        iap_0/tckEn_RNIFJOL:Y (f)
               +     0.400          net: TCK_c
  6.848                        iap_0/TMS:CLK (f)
               +     0.528          cell: ADLIB:DFN0E0P0
  7.376                        iap_0/TMS:Q (r)
               +     0.832          net: TMS_c
  8.208                        iap_0/TMS_RNIMUIK:B (r)
               +     0.538          cell: ADLIB:NOR2
  8.746                        iap_0/TMS_RNIMUIK:Y (f)
               +     0.348          net: iap_0/N_707
  9.094                        iap_0/TMS_RNI5KBA3:B (f)
               +     0.543          cell: ADLIB:AO1B
  9.637                        iap_0/TMS_RNI5KBA3:Y (f)
               +     0.369          net: iap_0/currentState_ns[0]
  10.006                       iap_0/targetState_RNIINGH3[0]:B (f)
               +     0.899          cell: ADLIB:XNOR2
  10.905                       iap_0/targetState_RNIINGH3[0]:Y (f)
               +     0.314          net: iap_0/tckEn14_0_i
  11.219                       iap_0/targetState_RNINTCB9[0]:C (f)
               +     0.620          cell: ADLIB:NOR3C
  11.839                       iap_0/targetState_RNINTCB9[0]:Y (f)
               +     0.291          net: iap_0/tckEn14_NE_1
  12.130                       iap_0/state_RNIH1VQE_0[1]:A (f)
               +     0.457          cell: ADLIB:AO1B
  12.587                       iap_0/state_RNIH1VQE_0[1]:Y (f)
               +     0.935          net: iap_0/N_188
  13.522                       iap_0/state_RNI4507Q[1]:C (f)
               +     0.620          cell: ADLIB:NOR3C
  14.142                       iap_0/state_RNI4507Q[1]:Y (f)
               +     0.640          net: iap_0/state_RNI4507Q[1]
  14.782                       iap_0/un1_tckCnt_I_12:B (f)
               +     0.853          cell: ADLIB:XOR2
  15.635                       iap_0/un1_tckCnt_I_12:Y (r)
               +     0.294          net: iap_0/DWACT_ADD_CI_0_pog_array_0[0]
  15.929                       iap_0/un1_tckCnt_I_35:A (r)
               +     0.473          cell: ADLIB:AO1
  16.402                       iap_0/un1_tckCnt_I_35:Y (r)
               +     0.930          net: iap_0/DWACT_ADD_CI_0_g_array_1[0]
  17.332                       iap_0/un1_tckCnt_I_36:B (r)
               +     0.516          cell: ADLIB:AO1
  17.848                       iap_0/un1_tckCnt_I_36:Y (r)
               +     0.715          net: iap_0/DWACT_ADD_CI_0_g_array_2[0]
  18.563                       iap_0/un1_tckCnt_I_39:B (r)
               +     0.516          cell: ADLIB:AO1
  19.079                       iap_0/un1_tckCnt_I_39:Y (r)
               +     0.403          net: iap_0/DWACT_ADD_CI_0_g_array_11[0]
  19.482                       iap_0/un1_tckCnt_I_45:B (r)
               +     0.516          cell: ADLIB:AO1
  19.998                       iap_0/un1_tckCnt_I_45:Y (r)
               +     0.306          net: iap_0/DWACT_ADD_CI_0_g_array_12_2[0]
  20.304                       iap_0/un1_tckCnt_I_34:C (r)
               +     0.897          cell: ADLIB:XOR3
  21.201                       iap_0/un1_tckCnt_I_34:Y (f)
               +     0.296          net: iap_0/I_34
  21.497                       iap_0/tckCnt_RNO_0[7]:B (f)
               +     0.571          cell: ADLIB:OR2B
  22.068                       iap_0/tckCnt_RNO_0[7]:Y (r)
               +     0.306          net: iap_0/N_78
  22.374                       iap_0/tckCnt_RNO[7]:C (r)
               +     0.596          cell: ADLIB:AO1B
  22.970                       iap_0/tckCnt_RNO[7]:Y (f)
               +     0.306          net: iap_0/tckCnt_15[7]
  23.276                       iap_0/tckCnt[7]:D (f)
                                    
  23.276                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_ccc_gla1
               +     0.000          Clock source
  25.000                       SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  30.249
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  30.249                       SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  30.249                       SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.589          net: FAB_CLK
  30.838                       iap_0/tckCnt[7]:CLK (r)
               -     0.490          Library setup time: ADLIB:DFN1
  30.348                       iap_0/tckCnt[7]:D
                                    
  30.348                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        TDO
  To:                          iap_0/datareg[15]:D
  Delay (ns):                  5.171
  Slack (ns):
  Arrival (ns):                5.171
  Required (ns):
  Setup (ns):                  0.490
  External Setup (ns):         -0.197


Expanded Path 1
  From: TDO
  To: iap_0/datareg[15]:D
  data required time                             N/C
  data arrival time                          -   5.171
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TDO (r)
               +     0.000          net: TDO
  0.000                        TDO_pad/U0/U0:PAD (r)
               +     0.935          cell: ADLIB:IOPAD_IN
  0.935                        TDO_pad/U0/U0:Y (r)
               +     0.000          net: TDO_pad/U0/NET1
  0.935                        TDO_pad/U0/U1:YIN (r)
               +     0.039          cell: ADLIB:IOIN_IB
  0.974                        TDO_pad/U0/U1:Y (r)
               +     2.451          net: TDO_c
  3.425                        iap_0/datareg_RNO_0[15]:A (r)
               +     0.538          cell: ADLIB:NOR2A
  3.963                        iap_0/datareg_RNO_0[15]:Y (r)
               +     0.296          net: iap_0/datareg_17_1_a2_0_0[15]
  4.259                        iap_0/datareg_RNO[15]:A (r)
               +     0.606          cell: ADLIB:MX2B
  4.865                        iap_0/datareg_RNO[15]:Y (r)
               +     0.306          net: iap_0/datareg_17[15]
  5.171                        iap_0/datareg[15]:D (r)
                                    
  5.171                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  N/C
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.609          net: FAB_CLK
  N/C                          iap_0/datareg[15]:CLK (r)
               -     0.490          Library setup time: ADLIB:DFN1E1
  N/C                          iap_0/datareg[15]:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        iap_0/TDI:CLK
  To:                          TDI
  Delay (ns):                  7.020
  Slack (ns):
  Arrival (ns):                14.702
  Required (ns):
  Clock to Out (ns):           14.702

Path 2
  From:                        iap_0/TMS:CLK
  To:                          TMS
  Delay (ns):                  7.521
  Slack (ns):
  Arrival (ns):                14.369
  Required (ns):
  Clock to Out (ns):           14.369

Path 3
  From:                        iap_0/tckEn:CLK
  To:                          TCK
  Delay (ns):                  8.147
  Slack (ns):
  Arrival (ns):                13.999
  Required (ns):
  Clock to Out (ns):           13.999

Path 4
  From:                        COREABC_0/IO_OUT[4]:CLK
  To:                          IO_OUT[4]
  Delay (ns):                  7.905
  Slack (ns):
  Arrival (ns):                13.794
  Required (ns):
  Clock to Out (ns):           13.794

Path 5
  From:                        COREABC_0/IO_OUT[2]:CLK
  To:                          IO_OUT[2]
  Delay (ns):                  7.544
  Slack (ns):
  Arrival (ns):                13.444
  Required (ns):
  Clock to Out (ns):           13.444


Expanded Path 1
  From: iap_0/TDI:CLK
  To: TDI
  data required time                             N/C
  data arrival time                          -   14.702
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (f)
               +     5.249          Clock generation
  5.249
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (f)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (f)
               +     0.611          net: FAB_CLK
  5.860                        iap_0/tckEn_RNIFJOL:B (f)
               +     0.588          cell: ADLIB:OR2A
  6.448                        iap_0/tckEn_RNIFJOL:Y (f)
               +     1.234          net: TCK_c
  7.682                        iap_0/TDI:CLK (f)
               +     0.671          cell: ADLIB:DFN0E1P0
  8.353                        iap_0/TDI:Q (f)
               +     2.568          net: TDI_c
  10.921                       TDI_pad/U0/U1:D (f)
               +     0.530          cell: ADLIB:IOTRI_OB_EB
  11.451                       TDI_pad/U0/U1:DOUT (f)
               +     0.000          net: TDI_pad/U0/NET1
  11.451                       TDI_pad/U0/U0:D (f)
               +     3.251          cell: ADLIB:IOPAD_TRI
  14.702                       TDI_pad/U0/U0:PAD (f)
               +     0.000          net: TDI
  14.702                       TDI (f)
                                    
  14.702                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  N/C
                                    
  N/C                          TDI (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        COREABC_0/RSTSYNC2:CLK
  To:                          iap_0/TMS:PRE
  Delay (ns):                  2.663
  Slack (ns):                  23.081
  Arrival (ns):                8.496
  Required (ns):               31.577
  Recovery (ns):               0.271
  Minimum Period (ns):         3.838
  Skew (ns):                   -1.015

Path 2
  From:                        COREABC_0/RSTSYNC2:CLK
  To:                          iap_0/TDI:PRE
  Delay (ns):                  2.667
  Slack (ns):                  23.911
  Arrival (ns):                8.500
  Required (ns):               32.411
  Recovery (ns):               0.271
  Minimum Period (ns):         2.178
  Skew (ns):                   -1.849

Path 3
  From:                        COREABC_0/RSTSYNC2:CLK
  To:                          COREABC_0/URAM.UR/UG3.UR_xhdl12/Ram256x16_R0C0:RESET
  Delay (ns):                  2.930
  Slack (ns):                  45.557
  Arrival (ns):                8.763
  Required (ns):               54.320
  Recovery (ns):               1.780
  Minimum Period (ns):         4.443
  Skew (ns):                   -0.267

Path 4
  From:                        COREABC_0/RSTSYNC2:CLK
  To:                          iap_0/state[4]:PRE
  Delay (ns):                  2.701
  Slack (ns):                  47.047
  Arrival (ns):                8.534
  Required (ns):               55.581
  Recovery (ns):               0.271
  Minimum Period (ns):         2.953
  Skew (ns):                   -0.019

Path 5
  From:                        COREABC_0/RSTSYNC2:CLK
  To:                          COREABC_0/SMADDR[0]:PRE
  Delay (ns):                  2.694
  Slack (ns):                  47.048
  Arrival (ns):                8.527
  Required (ns):               55.575
  Recovery (ns):               0.271
  Minimum Period (ns):         2.952
  Skew (ns):                   -0.013


Expanded Path 1
  From: COREABC_0/RSTSYNC2:CLK
  To: iap_0/TMS:PRE
  data required time                             31.577
  data arrival time                          -   8.496
  slack                                          23.081
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.584          net: FAB_CLK
  5.833                        COREABC_0/RSTSYNC2:CLK (r)
               +     0.528          cell: ADLIB:DFN1C0
  6.361                        COREABC_0/RSTSYNC2:Q (r)
               +     0.854          net: COREABC_0/RSTSYNC2
  7.215                        COREABC_0/RSTSYNC2_RNIS3FD/U_CLKSRC:A (r)
               +     0.699          cell: ADLIB:CLKSRC
  7.914                        COREABC_0/RSTSYNC2_RNIS3FD/U_CLKSRC:Y (r)
               +     0.582          net: TRSTB_c
  8.496                        iap_0/TMS:PRE (r)
                                    
  8.496                        data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_ccc_gla1
               +     0.000          Clock source
  25.000                       SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (f)
               +     5.249          Clock generation
  30.249
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  30.249                       SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (f)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  30.249                       SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (f)
               +     0.611          net: FAB_CLK
  30.860                       iap_0/tckEn_RNIFJOL:B (f)
               +     0.588          cell: ADLIB:OR2A
  31.448                       iap_0/tckEn_RNIFJOL:Y (f)
               +     0.400          net: TCK_c
  31.848                       iap_0/TMS:CLK (f)
               -     0.271          Library recovery time: ADLIB:DFN0E0P0
  31.577                       iap_0/TMS:PRE
                                    
  31.577                       data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

Path 1
  From:                        NSYSRESET
  To:                          COREABC_0/RSTSYNC2:CLR
  Delay (ns):                  1.310
  Slack (ns):
  Arrival (ns):                1.310
  Required (ns):
  Recovery (ns):               0.271
  External Recovery (ns):      -4.252

Path 2
  From:                        NSYSRESET
  To:                          COREABC_0/RSTSYNC1:CLR
  Delay (ns):                  1.305
  Slack (ns):
  Arrival (ns):                1.305
  Required (ns):
  Recovery (ns):               0.271
  External Recovery (ns):      -4.253


Expanded Path 1
  From: NSYSRESET
  To: COREABC_0/RSTSYNC2:CLR
  data required time                             N/C
  data arrival time                          -   1.310
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        NSYSRESET (r)
               +     0.000          net: NSYSRESET
  0.000                        NSYSRESET_pad/U0/U0:PAD (r)
               +     0.935          cell: ADLIB:IOPAD_IN
  0.935                        NSYSRESET_pad/U0/U0:Y (r)
               +     0.000          net: NSYSRESET_pad/U0/NET1
  0.935                        NSYSRESET_pad/U0/U1:YIN (r)
               +     0.039          cell: ADLIB:IOIN_IB
  0.974                        NSYSRESET_pad/U0/U1:Y (r)
               +     0.336          net: NSYSRESET_c
  1.310                        COREABC_0/RSTSYNC2:CLR (r)
                                    
  1.310                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  N/C
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.584          net: FAB_CLK
  N/C                          COREABC_0/RSTSYNC2:CLK (r)
               -     0.271          Library recovery time: ADLIB:DFN1C0
  N/C                          COREABC_0/RSTSYNC2:CLR


END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin SF_Zi1_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          SF_Zi1_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.937
  Slack (ns):
  Arrival (ns):                0.937
  Required (ns):
  Setup (ns):                  -2.196
  External Setup (ns):         -5.434


Expanded Path 1
  From: MSS_RESET_N
  To: SF_Zi1_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.937
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        SF_Zi1_MSS_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.937          cell: ADLIB:IOPAD_IN
  0.937                        SF_Zi1_MSS_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: SF_Zi1_MSS_0/MSS_RESET_0_MSS_RESET_N_Y
  0.937                        SF_Zi1_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.937                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  N/C
               +     0.630          net: SF_Zi1_MSS_0/GLA0
  N/C                          SF_Zi1_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -2.196          Library setup time: ADLIB:MSS_APB_IP
  N/C                          SF_Zi1_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain SF_Zi1_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          TCK
  Delay (ns):                  13.284
  Slack (ns):
  Arrival (ns):                13.284
  Required (ns):
  Clock to Out (ns):           13.284


Expanded Path 1
  From: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: TCK
  data required time                             N/C
  data arrival time                          -   13.284
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        SF_Zi1_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT
               +     0.000          Clock source
  0.000                        SF_Zi1_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT (r)
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/N_CLKA_RCOSC
  0.000                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     5.249          cell: ADLIB:MSS_CCC_IP
  5.249                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (f)
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (f)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (f)
               +     0.611          net: FAB_CLK
  5.860                        iap_0/tckEn_RNIFJOL:B (f)
               +     0.588          cell: ADLIB:OR2A
  6.448                        iap_0/tckEn_RNIFJOL:Y (f)
               +     3.055          net: TCK_c
  9.503                        TCK_pad/U0/U1:D (f)
               +     0.530          cell: ADLIB:IOTRI_OB_EB
  10.033                       TCK_pad/U0/U1:DOUT (f)
               +     0.000          net: TCK_pad/U0/NET1
  10.033                       TCK_pad/U0/U0:D (f)
               +     3.251          cell: ADLIB:IOPAD_TRI
  13.284                       TCK_pad/U0/U0:PAD (f)
               +     0.000          net: TCK
  13.284                       TCK (f)
                                    
  13.284                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT
               +     0.000          Clock source
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT (r)
                                    
  N/C                          TCK (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

