Synopsys Actel Technology Mapper, Version map201109rcp1, Build 024R, Built Sep 28 2011 11:20:53
Copyright (C) 1994-2011, Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
Product Version F-2011.09M

Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 
@N: MF547 |Generated clock conversion disabled 

Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)


Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)



Starting Optimization and Mapping (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 56MB)

@W: MO111 :"c:\libero 10.1\lpf_ac382_df\a2f200\zeroization\component\work\sf_zi1_mss\mss_ccc_0\sf_zi1_mss_tmp_mss_ccc_0_mss_ccc.v":64:7:64:18|Tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\libero 10.1\lpf_ac382_df\a2f200\zeroization\component\work\sf_zi1_mss\mss_ccc_0\sf_zi1_mss_tmp_mss_ccc_0_mss_ccc.v":63:7:63:20|Tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\libero 10.1\lpf_ac382_df\a2f200\zeroization\component\work\sf_zi1_mss\mss_ccc_0\sf_zi1_mss_tmp_mss_ccc_0_mss_ccc.v":62:7:62:18|Tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC) 

Available hyper_sources - for debug and ip models
	None Found


Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB)

@N:"c:\libero 10.1\lpf_ac382_df\a2f200\zeroization\hdl\iap.v":316:0:316:5|Found counter in view:work.iap_Z2(verilog) inst drLength[7:0]
Encoding state machine work.iap_Z2(verilog)-state[4:0]
original code -> new code
   000 -> 00001
   001 -> 00010
   010 -> 00100
   011 -> 01000
   100 -> 10000
Encoding state machine work.iap_Z2(verilog)-currentState[15:0]
original code -> new code
   0000 -> 0000
   0001 -> 0001
   0010 -> 0010
   0011 -> 0011
   0100 -> 0100
   0101 -> 0101
   0110 -> 0110
   0111 -> 0111
   1000 -> 1000
   1001 -> 1001
   1010 -> 1010
   1011 -> 1011
   1100 -> 1100
   1101 -> 1101
   1110 -> 1110
   1111 -> 1111
@N: MO106 :"c:\libero 10.1\lpf_ac382_df\a2f200\zeroization\component\work\sf_zi1\coreabc_0\rtl\vlog\core\instructions.v":148:4:148:7|Found ROM, 'UROM\.UROM.INS[57:0]', 524 words by 58 bits 
Encoding state machine work.SF_Zi1_COREABC_0_COREABC_Z3(verilog)-ICYCLE[3:0]
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N: MF176 |Default generator successful 
@N: MF176 |Default generator successful 
@N: MF176 |Default generator successful 
@N: MF238 :"c:\libero 10.1\lpf_ac382_df\a2f200\zeroization\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":985:35:985:61|Found 4-bit incrementor, 'un2_STKPTRP1[3:0]'
@N: MF238 :"c:\libero 10.1\lpf_ac382_df\a2f200\zeroization\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":253:34:253:42|Found 10-bit incrementor, 'un1_SMADDR[9:0]'
@W: MO129 :"c:\libero 10.1\lpf_ac382_df\a2f200\zeroization\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Sequential instance COREABC_0.UROM.INSTR_SLOT[1] reduced to a combinational gate by constant propagation

Finished factoring (Time elapsed 0h:00m:03s; Memory used current: 77MB peak: 79MB)

@N: BN362 :"c:\libero 10.1\lpf_ac382_df\a2f200\zeroization\hdl\iap.v":316:0:316:5|Removing sequential instance iap_0.MOSI of view:PrimLib.dff(prim) in hierarchy view:work.SF_Zi1(verilog) because there are no references to its outputs 
@N: BN362 :"c:\libero 10.1\lpf_ac382_df\a2f200\zeroization\hdl\iap.v":316:0:316:5|Removing sequential instance iap_0.SS[0] of view:PrimLib.dffs(prim) in hierarchy view:work.SF_Zi1(verilog) because there are no references to its outputs 
@N: BN362 :"c:\libero 10.1\lpf_ac382_df\a2f200\zeroization\hdl\iap.v":316:0:316:5|Removing sequential instance iap_0.sckEn of view:PrimLib.dffr(prim) in hierarchy view:work.SF_Zi1(verilog) because there are no references to its outputs 

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:03s; Memory used current: 70MB peak: 79MB)


Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 79MB)


Starting Early Timing Optimization (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 79MB)


Finished Early Timing Optimization (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 79MB)


Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:04s; Memory used current: 66MB peak: 79MB)


Finished preparing to map (Time elapsed 0h:00m:05s; Memory used current: 78MB peak: 79MB)


High Fanout Net Report
**********************

Driver Instance / Pin Name                 Fanout, notes                 
-------------------------------------------------------------------------
COREABC_0.SMADDR[0] / Q                    70                            
COREABC_0.SMADDR[1] / Q                    81                            
COREABC_0.SMADDR[2] / Q                    53                            
COREABC_0.SMADDR[3] / Q                    56                            
COREABC_0.SMADDR[4] / Q                    62                            
COREABC_0.SMADDR[5] / Q                    51                            
COREABC_0.SMADDR[6] / Q                    35                            
COREABC_0.SMADDR[7] / Q                    31                            
COREABC_0.SMADDR[8] / Q                    40                            
COREABC_0.SMADDR[9] / Q                    56                            
COREABC_0.UROM.INSTR_SCMD[0] / Q           30                            
COREABC_0.RSTSYNC2 / Q                     96 : 84 asynchronous set/reset
COREABC_0.UROM.UROM.INS_0_o2_0[2] / Y      51                            
COREABC_0.UROM.UROM.INS_i_o2[27] / Y       42                            
COREABC_0.UROM.UROM.INS_0_o2_1[0] / Y      33                            
COREABC_0.UROM.UROM.INS_0_o2[31] / Y       25                            
COREABC_0.UROM.UROM.INS_i_o3_1[1] / Y      35                            
COREABC_0.UROM.UROM.INS_0_a3_5[0] / Y      37                            
COREABC_0.UROM.UROM.INS_0_o2_3[2] / Y      29                            
COREABC_0.UROM.UROM.INS_0_o2_1[2] / Y      28                            
COREABC_0.UROM.UROM.INS_i_o2_0[1] / Y      26                            
COREABC_0.UROM.UROM.INS_i_a3_0[1] / Y      25                            
COREABC_0.UROM.UROM.INS_0_a3_4[0] / Y      42                            
COREABC_0.UROM.UROM.INS_i_a3_1[1] / Y      35                            
COREABC_0.UROM.UROM.INS_0_o2_0[4] / Y      27                            
COREABC_0.UROM.UROM.INS_0_a3_3[0] / Y      27                            
COREABC_0.UROM.UROM.INS_0_a3_1[0] / Y      31                            
COREABC_0.UROM.UROM.INS_0_o2_0[15] / Y     44                            
COREABC_0.UROM.UROM.INS_0_a3_2[0] / Y      33                            
COREABC_0.UROM.UROM.INS_0_a3_0[0] / Y      33                            
=========================================================================

@N: FP130 |Promoting Net TRSTB_c on CLKINT  I_378 
@N: FP130 |Promoting Net COREABC_0.SMADDR[1] on CLKINT  I_379 
@N: FP130 |Promoting Net COREABC_0.SMADDR[0] on CLKINT  I_380 
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_a3_0[0], fanout 33 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_a3_2[0], fanout 33 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_o2_0[15], fanout 44 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_a3_1[0], fanout 31 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_a3_3[0], fanout 27 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_o2_0[4], fanout 27 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_i_a3_1[1], fanout 35 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_a3_4[0], fanout 42 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_i_a3_0[1], fanout 25 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_i_o2_0[1], fanout 26 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_o2_1[2], fanout 28 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_o2_3[2], fanout 29 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_a3_5[0], fanout 37 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_i_o3_1[1], fanout 35 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_o2[31], fanout 25 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_o2_1[0], fanout 33 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_i_o2[27], fanout 43 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_o2_0[2], fanout 52 segments 3
Replicating Sequential Instance COREABC_0.UROM.INSTR_SCMD[0], fanout 30 segments 2
Replicating Sequential Instance COREABC_0.SMADDR[9], fanout 58 segments 3
Replicating Sequential Instance COREABC_0.SMADDR[8], fanout 43 segments 2
Replicating Sequential Instance COREABC_0.SMADDR[7], fanout 33 segments 2
Replicating Sequential Instance COREABC_0.SMADDR[6], fanout 35 segments 2
Replicating Sequential Instance COREABC_0.SMADDR[5], fanout 53 segments 3
Replicating Sequential Instance COREABC_0.SMADDR[4], fanout 65 segments 3
Replicating Sequential Instance COREABC_0.SMADDR[3], fanout 59 segments 3
Replicating Sequential Instance COREABC_0.SMADDR[2], fanout 55 segments 3

Finished technology mapping (Time elapsed 0h:00m:06s; Memory used current: 86MB peak: 113MB)


Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:06s; Memory used current: 86MB peak: 113MB)


Added 0 Buffers
Added 33 Cells via replication
	Added 14 Sequential Cells via replication
	Added 19 Combinational Cells via replication

Finished restoring hierarchy (Time elapsed 0h:00m:06s; Memory used current: 86MB peak: 113MB)

Writing Analyst data base C:\Libero 10.1\LPF_AC382_DF\A2F200\zeroization\synthesis\SF_Zi1.srm

Finished Writing Netlist Databases (Time elapsed 0h:00m:06s; Memory used current: 85MB peak: 113MB)

Writing EDIF Netlist and constraint files
F-2011.09M

Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:06s; Memory used current: 86MB peak: 113MB)

@W: MT420 |Found inferred clock SF_Zi1_MSS|MSS_ADLIB_INST_EMCCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:SF_Zi1_MSS_0.MSS_ADLIB_INST_EMCCLK"

Found clock FAB_CLK with period 50.00ns 
Found clock FCLK with period 50.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Mon Jul 30 14:45:14 2012
#


Top view:               SF_Zi1
Library name:           smartfusion
Operating conditions:   COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree )
Requested Frequency:    20.0 MHz
Wire load mode:         top
Wire load model:        smartfusion
Paths requested:        5
Constraint File(s):    C:\Libero 10.1\LPF_AC382_DF\A2F200\zeroization\component\work\SF_Zi1_MSS\mss_tshell_syn.sdc
                       
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: 3.956

                   Requested     Estimated     Requested     Estimated               Clock        Clock      
Starting Clock     Frequency     Frequency     Period        Period        Slack     Type         Group      
-------------------------------------------------------------------------------------------------------------
FAB_CLK            20.0 MHz      23.8 MHz      50.000        42.088        3.956     declared     clk_group_0
FCLK               20.0 MHz      NA            50.000        NA            NA        declared     clk_group_0
=============================================================================================================





Clock Relationships
*******************

Clocks             |    rise  to  rise    |    fall  to  fall    |    rise  to  fall    |    fall  to  rise 
------------------------------------------------------------------------------------------------------------
Starting  Ending   |  constraint  slack   |  constraint  slack   |  constraint  slack   |  constraint  slack
------------------------------------------------------------------------------------------------------------
FAB_CLK   FAB_CLK  |  50.000      17.487  |  50.000      46.712  |  25.000      12.612  |  25.000      3.956
============================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: FAB_CLK
====================================



Starting Points with Worst Slack
********************************

                          Starting                                               Arrival           
Instance                  Reference     Type         Pin     Net                 Time        Slack 
                          Clock                                                                    
---------------------------------------------------------------------------------------------------
iap_0.TMS                 FAB_CLK       DFN0E0P0     Q       TMS_c               0.653       3.956 
iap_0.currentState[2]     FAB_CLK       DFN1P0       Q       currentState[2]     0.580       12.612
iap_0.currentState[0]     FAB_CLK       DFN1P0       Q       currentState[0]     0.580       12.722
iap_0.currentState[1]     FAB_CLK       DFN1P0       Q       currentState[1]     0.737       13.565
iap_0.currentState[3]     FAB_CLK       DFN1P0       Q       currentState[3]     0.737       13.624
iap_0.targetState[3]      FAB_CLK       DFN1E0       Q       targetState[3]      0.737       13.964
iap_0.targetState[1]      FAB_CLK       DFN1E0       Q       targetState[1]      0.737       14.034
iap_0.targetState[0]      FAB_CLK       DFN1E0       Q       targetState[0]      0.737       14.696
iap_0.targetState[2]      FAB_CLK       DFN1E0       Q       targetState[2]      0.737       15.084
iap_0.tckCnt[6]           FAB_CLK       DFN1         Q       tckCnt[6]           0.737       15.633
===================================================================================================


Ending Points with Worst Slack
******************************

                    Starting                                                  Required           
Instance            Reference     Type         Pin     Net                    Time         Slack 
                    Clock                                                                        
-------------------------------------------------------------------------------------------------
iap_0.tckCnt[7]     FAB_CLK       DFN1         D       tckCnt_15[7]           24.461       3.956 
iap_0.tckCnt[6]     FAB_CLK       DFN1         D       tckCnt_15[6]           24.461       4.844 
iap_0.tckCnt[5]     FAB_CLK       DFN1         D       tckCnt_15[5]           24.461       4.908 
iap_0.tckCnt[4]     FAB_CLK       DFN1         D       tckCnt_15[4]           24.461       5.788 
iap_0.tckCnt[3]     FAB_CLK       DFN1         D       tckCnt_15[3]           24.461       6.273 
iap_0.tckCnt[0]     FAB_CLK       DFN1         D       tckCnt_15[0]           24.461       7.108 
iap_0.tckCnt[2]     FAB_CLK       DFN1         D       tckCnt_15[2]           24.461       7.161 
iap_0.tckCnt[1]     FAB_CLK       DFN1         D       tckCnt_15[1]           24.461       7.286 
iap_0.TMS           FAB_CLK       DFN0E0P0     D       N_4                    24.288       12.612
iap_0.tckEn         FAB_CLK       DFN1E1C0     E       un1_tckEn_0_sqmuxa     24.566       13.978
=================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      25.000
    - Setup time:                            0.539
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         24.461

    - Propagation time:                      20.505
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     3.956

    Number of logic level(s):                15
    Starting point:                          iap_0.TMS / Q
    Ending point:                            iap_0.tckCnt[7] / D
    The start point is clocked by            FAB_CLK [falling] on pin CLK
    The end   point is clocked by            FAB_CLK [rising] on pin CLK

Instance / Net                                  Pin      Pin               Arrival     No. of    
Name                               Type         Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------
iap_0.TMS                          DFN0E0P0     Q        Out     0.653     0.653       -         
TMS_c                              Net          -        -       1.526     -           7         
iap_0.TMS_RNIMUIK                  NOR2         B        In      -         2.179       -         
iap_0.TMS_RNIMUIK                  NOR2         Y        Out     0.646     2.826       -         
N_707                              Net          -        -       0.386     -           2         
iap_0.currentState_RNI73K11[0]     OR2B         B        In      -         3.212       -         
iap_0.currentState_RNI73K11[0]     OR2B         Y        Out     0.516     3.728       -         
N_712                              Net          -        -       0.322     -           1         
iap_0.TMS_RNI5KBA3                 OR2B         B        In      -         4.049       -         
iap_0.TMS_RNI5KBA3                 OR2B         Y        Out     0.627     4.677       -         
currentState_ns[0]                 Net          -        -       0.386     -           2         
iap_0.targetState_RNIINGH3[0]      XNOR2        B        In      -         5.063       -         
iap_0.targetState_RNIINGH3[0]      XNOR2        Y        Out     0.937     5.999       -         
tckEn14_0_i                        Net          -        -       0.322     -           1         
iap_0.targetState_RNINTCB9[0]      NOR3C        C        In      -         6.321       -         
iap_0.targetState_RNINTCB9[0]      NOR3C        Y        Out     0.666     6.986       -         
tckEn14_NE_1                       Net          -        -       0.806     -           3         
iap_0.state_RNIH1VQE_0[1]          AO1B         A        In      -         7.793       -         
iap_0.state_RNIH1VQE_0[1]          AO1B         Y        Out     0.469     8.262       -         
N_188                              Net          -        -       0.322     -           1         
iap_0.state_RNI4507Q[1]            NOR3C        C        In      -         8.583       -         
iap_0.state_RNI4507Q[1]            NOR3C        Y        Out     0.666     9.249       -         
state_RNI4507Q[1]                  Net          -        -       2.409     -           22        
iap_0.un1_tckCnt.I_12              XOR2         B        In      -         11.658      -         
iap_0.un1_tckCnt.I_12              XOR2         Y        Out     0.937     12.595      -         
DWACT_ADD_CI_0_pog_array_0[0]      Net          -        -       0.322     -           1         
iap_0.un1_tckCnt.I_35              AO1          A        In      -         12.916      -         
iap_0.un1_tckCnt.I_35              AO1          Y        Out     0.520     13.436      -         
DWACT_ADD_CI_0_g_array_1[0]        Net          -        -       0.806     -           3         
iap_0.un1_tckCnt.I_36              AO1          B        In      -         14.242      -         
iap_0.un1_tckCnt.I_36              AO1          Y        Out     0.567     14.809      -         
DWACT_ADD_CI_0_g_array_2[0]        Net          -        -       0.806     -           3         
iap_0.un1_tckCnt.I_39              AO1          B        In      -         15.615      -         
iap_0.un1_tckCnt.I_39              AO1          Y        Out     0.567     16.182      -         
DWACT_ADD_CI_0_g_array_11[0]       Net          -        -       0.386     -           2         
iap_0.un1_tckCnt.I_45              AO1          B        In      -         16.567      -         
iap_0.un1_tckCnt.I_45              AO1          Y        Out     0.567     17.134      -         
DWACT_ADD_CI_0_g_array_12_2[0]     Net          -        -       0.322     -           1         
iap_0.un1_tckCnt.I_34              XOR2         B        In      -         17.455      -         
iap_0.un1_tckCnt.I_34              XOR2         Y        Out     0.937     18.392      -         
I_34                               Net          -        -       0.322     -           1         
iap_0.tckCnt_RNO_0[7]              OR2B         B        In      -         18.714      -         
iap_0.tckCnt_RNO_0[7]              OR2B         Y        Out     0.516     19.230      -         
N_78                               Net          -        -       0.322     -           1         
iap_0.tckCnt_RNO[7]                AO1B         C        In      -         19.551      -         
iap_0.tckCnt_RNO[7]                AO1B         Y        Out     0.633     20.184      -         
tckCnt_15[7]                       Net          -        -       0.322     -           1         
iap_0.tckCnt[7]                    DFN1         D        In      -         20.505      -         
=================================================================================================
Total path delay (propagation time + setup) of 21.044 is 10.960(52.1%) logic and 10.084(47.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Target Part: A2F200M3F_FBGA484_STD
Report for cell SF_Zi1.verilog
  Core Cell usage:
              cell count     area count*area
              AND2    48      1.0       48.0
              AND3     9      1.0        9.0
               AO1    21      1.0       21.0
              AO13     8      1.0        8.0
              AO18     2      1.0        2.0
              AO1A     8      1.0        8.0
              AO1B    15      1.0       15.0
              AO1C    24      1.0       24.0
              AO1D    27      1.0       27.0
              AOI1    12      1.0       12.0
             AOI1B   110      1.0      110.0
              AX1B     3      1.0        3.0
              AX1C     3      1.0        3.0
            CLKINT     3      0.0        0.0
               GND    10      0.0        0.0
               INV     2      1.0        2.0
              MAJ3    18      1.0       18.0
            MAJ3XI     1      1.0        1.0
              MIN3     1      1.0        1.0
             MIN3X     1      1.0        1.0
           MSS_CCC     1      0.0        0.0
               MX2    66      1.0       66.0
              MX2A     4      1.0        4.0
              MX2B    21      1.0       21.0
              MX2C     9      1.0        9.0
             NAND2    22      1.0       22.0
              NOR2   195      1.0      195.0
             NOR2A   148      1.0      148.0
             NOR2B   101      1.0      101.0
              NOR3    17      1.0       17.0
             NOR3A    35      1.0       35.0
             NOR3B    47      1.0       47.0
             NOR3C   235      1.0      235.0
               OA1    23      1.0       23.0
              OA1A    78      1.0       78.0
              OA1B    11      1.0       11.0
              OA1C    13      1.0       13.0
              OAI1    28      1.0       28.0
               OR2   164      1.0      164.0
              OR2A   227      1.0      227.0
              OR2B   177      1.0      177.0
               OR3    89      1.0       89.0
              OR3A    90      1.0       90.0
              OR3B    75      1.0       75.0
              OR3C   110      1.0      110.0
             RCOSC     1      0.0        0.0
               VCC    10      0.0        0.0
               XA1     1      1.0        1.0
              XA1A     3      1.0        3.0
              XA1B     2      1.0        2.0
              XAI1    17      1.0       17.0
             XAI1A     2      1.0        2.0
             XNOR2    19      1.0       19.0
             XNOR3    15      1.0       15.0
              XO1A     5      1.0        5.0
              XOR2    52      1.0       52.0
              XOR3    12      1.0       12.0
              ZOR3     2      1.0        2.0


          DFN0E0P0     1      1.0        1.0
          DFN0E1P0     1      1.0        1.0
              DFN1    42      1.0       42.0
            DFN1C0    11      1.0       11.0
            DFN1E0     4      1.0        4.0
          DFN1E0C0    17      1.0       17.0
            DFN1E1    16      1.0       16.0
          DFN1E1C0    34      1.0       34.0
            DFN1P0    35      1.0       35.0
           MSS_APB     1      0.0        0.0
         RAM512X18     1      0.0        0.0
                   -----          ----------
             TOTAL  2616              2589.0


  IO Cell usage:
              cell count
             INBUF     2
         INBUF_MSS     2
            OUTBUF    12
        OUTBUF_MSS     1
                   -----
             TOTAL    17


Core Cells         : 2589 of 4608 (56%)
IO Cells           : 17

  RAM/ROM Usage Summary
Block Rams : 1 of 8 (12%)

Mapper successful!

At Mapper Exit (Time elapsed 0h:00m:06s; Memory used current: 28MB peak: 113MB)

Process took 0h:00m:07s realtime, 0h:00m:06s cputime
# Mon Jul 30 14:45:14 2012

###########################################################]
