#Build: Synplify Pro E-2010.09A-1, Build 006R, Oct  6 2010
#install: F:\Microsemi\Libero_v9.1\Synopsys\synplify_E201009A-1
#OS:  6.1
#Hostname: W7-DONTHUS

#Implementation: synthesis

#Thu Jan 05 16:53:02 2012

$ Start of Compile
#Thu Jan 05 16:53:02 2012

Synopsys Verilog Compiler, version comp520rcp1, Build 028R, built Sep 23 2010
@N|Running in 32-bit mode
Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved

@I::"F:\Microsemi\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\smartfusion.v"
@I::"F:\Microsemi\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\vlog\hypermods.v"
@I::"F:\zeroization\SF_Zi1\hdl\IAP.v"
@I::"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ram256x16_smartfusion.v"
@I::"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ram256x8_rtl.v"
@I::"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ramblocks.v"
@I::"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\acmtable.v"
@I::"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\instructions.v"
@I:"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\instructions.v":"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\support.v"
@I::"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\iram512x9_smartfusion.v"
@N: CG334 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\iram512x9_smartfusion.v":62:17:62:29|Read directive translate_off 
@N: CG333 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\iram512x9_smartfusion.v":63:17:63:28|Read directive translate_on 
@I::"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\instructram.v"
@I::"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\instructnvm_bb.v"
@I::"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\debugblk.v"
@N: CG334 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\debugblk.v":68:17:68:29|Read directive translate_off 
@N: CG333 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\debugblk.v":745:17:745:28|Read directive translate_on 
@I::"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v"
@N: CG334 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":949:21:949:33|Read directive translate_off 
@N: CG333 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":951:21:951:32|Read directive translate_on 
@N: CG334 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":1326:17:1326:29|Read directive translate_off 
@N: CG333 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":1369:17:1369:28|Read directive translate_on 
@I::"F:\zeroization\SF_Zi1\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v"
@I::"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v"
@I::"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\mss_tshell.v"
@I::"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\SF_Zi1_MSS.v"
@I::"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3_muxptob3.v"
@I::"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v"
@I::"F:\zeroization\SF_Zi1\component\work\SF_Zi1\SF_Zi1.v"
Verilog syntax check successful!
Selecting top level module SF_Zi1
@W: CG775 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":30:7:30:14|Found Component CoreAPB3 in library COREAPB3_LIB
@N: CG364 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3_muxptob3.v":30:7:30:23|Synthesizing module COREAPB3_MUXPTOB3

@N: CG364 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":30:7:30:14|Synthesizing module CoreAPB3

	APB_DWIDTH=6'b100000
	RANGESIZE=21'b000000000000100000000
	IADDR_ENABLE=1'b0
	APBSLOT0ENABLE=1'b1
	APBSLOT1ENABLE=1'b0
	APBSLOT2ENABLE=1'b0
	APBSLOT3ENABLE=1'b0
	APBSLOT4ENABLE=1'b0
	APBSLOT5ENABLE=1'b0
	APBSLOT6ENABLE=1'b0
	APBSLOT7ENABLE=1'b0
	APBSLOT8ENABLE=1'b0
	APBSLOT9ENABLE=1'b0
	APBSLOT10ENABLE=1'b0
	APBSLOT11ENABLE=1'b0
	APBSLOT12ENABLE=1'b0
	APBSLOT13ENABLE=1'b0
	APBSLOT14ENABLE=1'b0
	APBSLOT15ENABLE=1'b0
	RANGEBITS=32'b00000000000000000000000000001000
	RANGEBITS_LT16=32'b00000000000000000000000000001000
	IADDR_31_24_8B_A=8'b00001100
	IADDR_23_16_8B_A=8'b00001000
	IADDR_15_8_8B_A=8'b00000100
	IADDR_7_0_8B_A=8'b00000000
	IADDR_31_16_16B_A=8'b00000100
	IADDR_15_0_16B_A=8'b00000000
	IADDR_31_0_32B_A=8'b00000000
	SL0=16'b0000000000000001
	SL1=16'b0000000000000000
	SL2=16'b0000000000000000
	SL3=16'b0000000000000000
	SL4=16'b0000000000000000
	SL5=16'b0000000000000000
	SL6=16'b0000000000000000
	SL7=16'b0000000000000000
	SL8=16'b0000000000000000
	SL9=16'b0000000000000000
	SL10=16'b0000000000000000
	SL11=16'b0000000000000000
	SL12=16'b0000000000000000
	SL13=16'b0000000000000000
	SL14=16'b0000000000000000
	SL15=16'b0000000000000000
   Generated name = CoreAPB3_Z1

@N: CG364 :"F:\Microsemi\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\smartfusion.v":1814:7:1814:9|Synthesizing module VCC

@N: CG364 :"F:\zeroization\SF_Zi1\hdl\IAP.v":30:7:30:9|Synthesizing module iap

	SPISLAVES=32'b00000000000000000000000000000001
	dwidth=32'b00000000000000000000000000010000
	JTAG_TEST_LOGIC_RESET=4'b1111
	JTAG_RUN_TEST_IDLE=4'b1100
	JTAG_SELECT_DR=4'b0111
	JTAG_CAPTURE_DR=4'b0110
	JTAG_SHIFT_DR=4'b0010
	JTAG_EXIT1_DR=4'b0001
	JTAG_PAUSE_DR=4'b0011
	JTAG_EXIT2_DR=4'b0000
	JTAG_UPDATE_DR=4'b0101
	JTAG_SELECT_IR=4'b0100
	JTAG_CAPTURE_IR=4'b1110
	JTAG_SHIFT_IR=4'b1010
	JTAG_EXIT1_IR=4'b1001
	JTAG_PAUSE_IR=4'b1011
	JTAG_EXIT2_IR=4'b1000
	JTAG_UPDATE_IR=4'b1101
	IAP_IR=6'b0000xx
	IAP_DR2=6'b0001xx
	IAP_DR3=6'b0010xx
	IAP_DR5=6'b0011xx
	IAP_DR26=6'b0100xx
	IAP_DR16=6'b0101xx
	IAP_DR=6'b0110xx
	IAP_DR_LENGTH=6'b0111xx
	IAP_TAP_NEW_STATE=6'b1000xx
	IAP_TAP_CONTROL=6'b1001xx
	IAP_SPI_SS=6'b1010xx
	IAP_SPI_TRANSFER=6'b1011xx
	IAP_SPI_DATA=6'b1100xx
	IDLE=3'b100
	MOVE=3'b001
	SCAN=3'b010
	SPI_TRANSFER=3'b011
	SPI_COMMAND=3'b000
   Generated name = iap_Z2

@A:"F:\zeroization\SF_Zi1\hdl\IAP.v":317:0:317:5|Feedback mux created for signal tckCnt[7:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area
@A:"F:\zeroization\SF_Zi1\hdl\IAP.v":317:0:317:5|Feedback mux created for signal targetState[3:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area
@A:"F:\zeroization\SF_Zi1\hdl\IAP.v":317:0:317:5|Feedback mux created for signal datareg[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area
@A:"F:\zeroization\SF_Zi1\hdl\IAP.v":317:0:317:5|Feedback mux created for signal MOSI. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area
@N: CG364 :"F:\Microsemi\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\smartfusion.v":1133:7:1133:9|Synthesizing module GND

@N: CG364 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":46:7:46:30|Synthesizing module SF_Zi1_COREABC_0_COREABC

	FAMILY=32'b00000000000000000000000000010010
	APB_AWIDTH=32'b00000000000000000000000000010000
	APB_DWIDTH=32'b00000000000000000000000000100000
	APB_SDEPTH=32'b00000000000000000000000000000010
	ICWIDTH=32'b00000000000000000000000000010000
	ZRWIDTH=32'b00000000000000000000000000010000
	IFWIDTH=32'b00000000000000000000000000000000
	IIWIDTH=32'b00000000000000000000000000000001
	IOWIDTH=32'b00000000000000000000000000001000
	STWIDTH=32'b00000000000000000000000000000100
	EN_RAM=32'b00000000000000000000000000000001
	EN_AND=32'b00000000000000000000000000000001
	EN_XOR=32'b00000000000000000000000000000001
	EN_OR=32'b00000000000000000000000000000001
	EN_ADD=32'b00000000000000000000000000000001
	EN_INC=32'b00000000000000000000000000000001
	EN_SHL=32'b00000000000000000000000000000001
	EN_SHR=32'b00000000000000000000000000000001
	EN_CALL=32'b00000000000000000000000000000001
	EN_PUSH=32'b00000000000000000000000000000001
	EN_MULT=32'b00000000000000000000000000000000
	EN_ACM=32'b00000000000000000000000000000000
	EN_DATAM=32'b00000000000000000000000000000010
	EN_INT=32'b00000000000000000000000000000000
	EN_IOREAD=32'b00000000000000000000000000000001
	EN_IOWRT=32'b00000000000000000000000000000001
	EN_ALURAM=32'b00000000000000000000000000000000
	EN_INDIRECT=32'b00000000000000000000000000000000
	ISRADDR=32'b00000000000000000000000000000001
	DEBUG=32'b00000000000000000000000000000001
	INSMODE=32'b00000000000000000000000000000000
	INITWIDTH=32'b00000000000000000000000000001011
	TESTMODE=32'b00000000000000000000000000000000
	ACT_CALIBRATIONDATA=32'b00000000000000000000000000000001
	IMEM_APB_ACCESS=32'b00000000000000000000000000000000
	UNIQ_STRING_LENGTH=32'b00000000000000000000000000010000
	MAX_NVMDWIDTH=32'b00000000000000000000000000100000
	BLANK=32'b11111111111111111111111111111111
	iNOP=32'b00000000000000000000000100000000
	iLOAD=32'b00000000000000000000001000000000
	iINCB=32'b00000000000000000000001100000000
	iAND=32'b00000000000000000000010000000000
	iOR=32'b00000000000000000000010100000000
	iXOR=32'b00000000000000000000011000000000
	iADD=32'b00000000000000000000011100000000
	iSUB=32'b00000000000000000000100000000000
	iSHL0=32'b00000000000000000000100100000000
	iSHL1=32'b00000000000000000000101000000000
	iSHLE=32'b00000000000000000000101100000000
	iROL=32'b00000000000000000000110000000000
	iSHR0=32'b00000000000000000000110100000000
	iSHR1=32'b00000000000000000000111000000000
	iSHRE=32'b00000000000000000000111100000000
	iROR=32'b00000000000000000001000000000000
	iCMP=32'b00000000000000000001000100000000
	iCMPLEQ=32'b00000000000000000001001000000000
	iBITCLR=32'b00000000000000000001001100000000
	iBITSET=32'b00000000000000000001010000000000
	iBITTST=32'b00000000000000000001010100000000
	iAPBREAD=32'b00000000000000000001011000000000
	iAPBWRT=32'b00000000000000000001011100000000
	iLOADZ=32'b00000000000000000001100000000000
	iDECZ=32'b00000000000000000001100100000000
	iINCZ=32'b00000000000000000001101000000000
	iIOWRT=32'b00000000000000000001101100000000
	iRAMREAD=32'b00000000000000000001110000000000
	iRAMWRT=32'b00000000000000000001110100000000
	iPUSH=32'b00000000000000000001111000000000
	iPOP=32'b00000000000000000001111100000000
	iIOREAD=32'b00000000000000000010000000000000
	iUSER=32'b00000000000000000010000100000000
	iJUMPB=32'b00000000000000000010001000000000
	iCALLB=32'b00000000000000000010001100000000
	iRETURNB=32'b00000000000000000010010000000000
	iRETISRB=32'b00000000000000000010010100000000
	iWAITB=32'b00000000000000000010011000000000
	iHALTB=32'b00000000000000000010011000000000
	iMULT=32'b00000000000000000010011100000000
	iDEC=32'b00000000000000000010100000000000
	iAPBREADZ=32'b00000000000000000010100100000000
	iAPBWRTZ=32'b00000000000000000010101000000000
	iADDZ=32'b00000000000000000010101100000000
	iSUBZ=32'b00000000000000000010110000000000
	iDAT=32'b00000000000000000000000000001010
	iDAT8=32'b00000000000000000000000000001011
	iDAT16=32'b00000000000000000000000000001100
	iDAT32=32'b00000000000000000000000000001101
	iACM=32'b00000000000000000000000000001110
	iACC=32'b00000000000000000000000000001111
	iRAM=32'b00000000000000000000000000010000
	DAT=32'b00000000000000000000000000001010
	DAT8=32'b00000000000000000000000000001011
	DAT16=32'b00000000000000000000000000001100
	DAT32=32'b00000000000000000000000000001101
	ACM=32'b00000000000000000000000000001110
	ACC=32'b00000000000000000000000000001111
	RAM=32'b00000000000000000000000000010000
	iIFNOT=32'b00000000000000000000000000000000
	iNOTIF=32'b00000000000000000000000000000000
	iIF=32'b00000000000000000000000000000001
	iUNTIL=32'b00000000000000000000000000000000
	iNOTUNTIL=32'b00000000000000000000000000000001
	iUNTILNOT=32'b00000000000000000000000000000001
	iWHILE=32'b00000000000000000000000000000001
	iZZERO=8'b00001000
	iNEGATIVE=8'b00000100
	iZERO=8'b00000010
	iLTE_ZERO=8'b00000110
	iALWAYS=8'b00000001
	iINPUT0=12'b000000010000
	iINPUT1=12'b000000100000
	iINPUT2=12'b000001000000
	iINPUT3=12'b000010000000
	iINPUT4=12'b000100000000
	iINPUT5=12'b001000000000
	iINPUT6=12'b010000000000
	iINPUT7=12'b100000000000
	iINPUT8=16'b0001000000000000
	iINPUT9=16'b0010000000000000
	iINPUT10=16'b0100000000000000
	iINPUT11=16'b1000000000000000
	iINPUT12=20'b00010000000000000000
	iINPUT13=20'b00100000000000000000
	iINPUT14=20'b01000000000000000000
	iINPUT15=20'b10000000000000000000
	iINPUT16=24'b000100000000000000000000
	iINPUT17=24'b001000000000000000000000
	iINPUT18=24'b010000000000000000000000
	iINPUT19=24'b100000000000000000000000
	iINPUT20=28'b0001000000000000000000000000
	iINPUT21=28'b0010000000000000000000000000
	iINPUT22=28'b0100000000000000000000000000
	iINPUT23=28'b1000000000000000000000000000
	iINPUT24=32'b00010000000000000000000000000000
	iINPUT25=32'b00100000000000000000000000000000
	iINPUT26=32'b01000000000000000000000000000000
	iINPUT27=32'b10000000000000000000000000000000
	iANYINPUT=32'b01111111111111111111111111110000
	ALWAYS=8'b00000001
	ZZERO=8'b00001000
	NEGATIVE=8'b00000100
	ZERO=8'b00000010
	LTE_ZERO=8'b00000110
	INPUT0=12'b000000010000
	INPUT1=12'b000000100000
	INPUT2=12'b000001000000
	INPUT3=12'b000010000000
	INPUT4=12'b000100000000
	INPUT5=12'b001000000000
	INPUT6=12'b010000000000
	INPUT7=12'b100000000000
	INPUT8=16'b0001000000000000
	INPUT9=16'b0010000000000000
	INPUT10=16'b0011000000000000
	INPUT11=16'b1000000000000000
	INPUT12=20'b00010000000000000000
	INPUT13=20'b00100000000000000000
	INPUT14=20'b01000000000000000000
	INPUT15=20'b10000000000000000000
	INPUT16=24'b000100000000000000000000
	INPUT17=24'b001000000000000000000000
	INPUT18=24'b001100000000000000000000
	INPUT19=24'b100000000000000000000000
	INPUT20=28'b0001000000000000000000000000
	INPUT21=28'b0010000000000000000000000000
	INPUT22=28'b0100000000000000000000000000
	INPUT23=28'b1000000000000000000000000000
	INPUT24=32'b00010000000000000000000000000000
	INPUT25=32'b00100000000000000000000000000000
	INPUT26=32'b01000000000000000000000000000000
	INPUT27=32'b01000000000000000000000000000000
	ANYINPUT=32'b01111111111111111111111111110000
	iLOADLOOP=32'b00000000000000000001100000000000
	iDECLOOP=32'b00000000000000000001100100000000
	iINCLOOP=32'b00000000000000000001101000000000
	iLOOPZ=32'b00000000000000000000000000001000
	LOOPZ=32'b00000000000000000000000000001000
	EN_USER=32'b00000000000000000000000000000000
	IWWIDTH=32'b00000000000000000000000000111010
	IRWIDTH=32'b00000000000000000000000000100000
	ICDEPTH=32'b00000000000000010000000000000000
	APB_SWIDTH=32'b00000000000000000000000000000001
	RAMWIDTH=32'b00000000000000000000000000110111
	CYCLE0=2'b00
	CYCLE1=2'b01
	CYCLE2=2'b10
	CYCLE3=2'b11
   Generated name = SF_Zi1_COREABC_0_COREABC_Z3

@N: CG364 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ramblocks.v":25:7:25:32|Synthesizing module SF_Zi1_COREABC_0_RAMBLOCKS

	DWIDTH=32'b00000000000000000000000000100000
	FAMILY=32'b00000000000000000000000000010010
   Generated name = SF_Zi1_COREABC_0_RAMBLOCKS_32s_18s

@N: CG364 :"F:\Microsemi\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\smartfusion.v":2207:7:2207:15|Synthesizing module RAM512X18

@N: CG364 :"F:\Microsemi\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\smartfusion.v":1253:7:1253:9|Synthesizing module INV

@N: CG364 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ram256x16_smartfusion.v":25:7:25:32|Synthesizing module SF_Zi1_COREABC_0_RAM256X16

@W: CG360 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ramblocks.v":38:23:38:25|No assignment to wire RDW

@W: CG360 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ramblocks.v":44:15:44:18|No assignment to wire RDYY

@W: CG360 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ramblocks.v":49:15:49:18|No assignment to wire RD32

@W: CG360 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ramblocks.v":50:15:50:18|No assignment to wire WD32

@N: CG364 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\instructions.v":26:7:26:35|Synthesizing module SF_Zi1_COREABC_0_INSTRUCTIONS

	AWIDTH=32'b00000000000000000000000000010000
	DWIDTH=32'b00000000000000000000000000100000
	SWIDTH=32'b00000000000000000000000000000001
	ICWIDTH=32'b00000000000000000000000000010000
	IIWIDTH=32'b00000000000000000000000000000001
	IFWIDTH=32'b00000000000000000000000000000000
	IWWIDTH=32'b00000000000000000000000000111010
	EN_MULT=32'b00000000000000000000000000000000
	EN_INC=32'b00000000000000000000000000000001
	TESTMODE=32'b00000000000000000000000000000000
	BLANK=32'b11111111111111111111111111111111
	iNOP=32'b00000000000000000000000100000000
	iLOAD=32'b00000000000000000000001000000000
	iINCB=32'b00000000000000000000001100000000
	iAND=32'b00000000000000000000010000000000
	iOR=32'b00000000000000000000010100000000
	iXOR=32'b00000000000000000000011000000000
	iADD=32'b00000000000000000000011100000000
	iSUB=32'b00000000000000000000100000000000
	iSHL0=32'b00000000000000000000100100000000
	iSHL1=32'b00000000000000000000101000000000
	iSHLE=32'b00000000000000000000101100000000
	iROL=32'b00000000000000000000110000000000
	iSHR0=32'b00000000000000000000110100000000
	iSHR1=32'b00000000000000000000111000000000
	iSHRE=32'b00000000000000000000111100000000
	iROR=32'b00000000000000000001000000000000
	iCMP=32'b00000000000000000001000100000000
	iCMPLEQ=32'b00000000000000000001001000000000
	iBITCLR=32'b00000000000000000001001100000000
	iBITSET=32'b00000000000000000001010000000000
	iBITTST=32'b00000000000000000001010100000000
	iAPBREAD=32'b00000000000000000001011000000000
	iAPBWRT=32'b00000000000000000001011100000000
	iLOADZ=32'b00000000000000000001100000000000
	iDECZ=32'b00000000000000000001100100000000
	iINCZ=32'b00000000000000000001101000000000
	iIOWRT=32'b00000000000000000001101100000000
	iRAMREAD=32'b00000000000000000001110000000000
	iRAMWRT=32'b00000000000000000001110100000000
	iPUSH=32'b00000000000000000001111000000000
	iPOP=32'b00000000000000000001111100000000
	iIOREAD=32'b00000000000000000010000000000000
	iUSER=32'b00000000000000000010000100000000
	iJUMPB=32'b00000000000000000010001000000000
	iCALLB=32'b00000000000000000010001100000000
	iRETURNB=32'b00000000000000000010010000000000
	iRETISRB=32'b00000000000000000010010100000000
	iWAITB=32'b00000000000000000010011000000000
	iHALTB=32'b00000000000000000010011000000000
	iMULT=32'b00000000000000000010011100000000
	iDEC=32'b00000000000000000010100000000000
	iAPBREADZ=32'b00000000000000000010100100000000
	iAPBWRTZ=32'b00000000000000000010101000000000
	iADDZ=32'b00000000000000000010101100000000
	iSUBZ=32'b00000000000000000010110000000000
	iDAT=32'b00000000000000000000000000001010
	iDAT8=32'b00000000000000000000000000001011
	iDAT16=32'b00000000000000000000000000001100
	iDAT32=32'b00000000000000000000000000001101
	iACM=32'b00000000000000000000000000001110
	iACC=32'b00000000000000000000000000001111
	iRAM=32'b00000000000000000000000000010000
	DAT=32'b00000000000000000000000000001010
	DAT8=32'b00000000000000000000000000001011
	DAT16=32'b00000000000000000000000000001100
	DAT32=32'b00000000000000000000000000001101
	ACM=32'b00000000000000000000000000001110
	ACC=32'b00000000000000000000000000001111
	RAM=32'b00000000000000000000000000010000
	iIFNOT=32'b00000000000000000000000000000000
	iNOTIF=32'b00000000000000000000000000000000
	iIF=32'b00000000000000000000000000000001
	iUNTIL=32'b00000000000000000000000000000000
	iNOTUNTIL=32'b00000000000000000000000000000001
	iUNTILNOT=32'b00000000000000000000000000000001
	iWHILE=32'b00000000000000000000000000000001
	iZZERO=8'b00001000
	iNEGATIVE=8'b00000100
	iZERO=8'b00000010
	iLTE_ZERO=8'b00000110
	iALWAYS=8'b00000001
	iINPUT0=12'b000000010000
	iINPUT1=12'b000000100000
	iINPUT2=12'b000001000000
	iINPUT3=12'b000010000000
	iINPUT4=12'b000100000000
	iINPUT5=12'b001000000000
	iINPUT6=12'b010000000000
	iINPUT7=12'b100000000000
	iINPUT8=16'b0001000000000000
	iINPUT9=16'b0010000000000000
	iINPUT10=16'b0100000000000000
	iINPUT11=16'b1000000000000000
	iINPUT12=20'b00010000000000000000
	iINPUT13=20'b00100000000000000000
	iINPUT14=20'b01000000000000000000
	iINPUT15=20'b10000000000000000000
	iINPUT16=24'b000100000000000000000000
	iINPUT17=24'b001000000000000000000000
	iINPUT18=24'b010000000000000000000000
	iINPUT19=24'b100000000000000000000000
	iINPUT20=28'b0001000000000000000000000000
	iINPUT21=28'b0010000000000000000000000000
	iINPUT22=28'b0100000000000000000000000000
	iINPUT23=28'b1000000000000000000000000000
	iINPUT24=32'b00010000000000000000000000000000
	iINPUT25=32'b00100000000000000000000000000000
	iINPUT26=32'b01000000000000000000000000000000
	iINPUT27=32'b10000000000000000000000000000000
	iANYINPUT=32'b01111111111111111111111111110000
	ALWAYS=8'b00000001
	ZZERO=8'b00001000
	NEGATIVE=8'b00000100
	ZERO=8'b00000010
	LTE_ZERO=8'b00000110
	INPUT0=12'b000000010000
	INPUT1=12'b000000100000
	INPUT2=12'b000001000000
	INPUT3=12'b000010000000
	INPUT4=12'b000100000000
	INPUT5=12'b001000000000
	INPUT6=12'b010000000000
	INPUT7=12'b100000000000
	INPUT8=16'b0001000000000000
	INPUT9=16'b0010000000000000
	INPUT10=16'b0011000000000000
	INPUT11=16'b1000000000000000
	INPUT12=20'b00010000000000000000
	INPUT13=20'b00100000000000000000
	INPUT14=20'b01000000000000000000
	INPUT15=20'b10000000000000000000
	INPUT16=24'b000100000000000000000000
	INPUT17=24'b001000000000000000000000
	INPUT18=24'b001100000000000000000000
	INPUT19=24'b100000000000000000000000
	INPUT20=28'b0001000000000000000000000000
	INPUT21=28'b0010000000000000000000000000
	INPUT22=28'b0100000000000000000000000000
	INPUT23=28'b1000000000000000000000000000
	INPUT24=32'b00010000000000000000000000000000
	INPUT25=32'b00100000000000000000000000000000
	INPUT26=32'b01000000000000000000000000000000
	INPUT27=32'b01000000000000000000000000000000
	ANYINPUT=32'b01111111111111111111111111110000
	iLOADLOOP=32'b00000000000000000001100000000000
	iDECLOOP=32'b00000000000000000001100100000000
	iINCLOOP=32'b00000000000000000001101000000000
	iLOOPZ=32'b00000000000000000000000000001000
	LOOPZ=32'b00000000000000000000000000001000
	EN_USER=32'b00000000000000000000000000000000
	AW=32'b00000000000000000000000000010000
	DW=32'b00000000000000000000000000100000
	SW=32'b00000000000000000000000000000001
	IW=32'b00000000000000000000000000010000
	FW=32'b00000000000000000000000000000101
	iJUMP=32'b00000000000000000010001000000000
	iCALL=32'b00000000000000000010001100000000
	iRETURN=32'b00000000000000000010010000000000
	iRETISR=32'b00000000000000000010010100000000
	iWAIT=32'b00000000000000000010011000000000
	iHALT=32'b00000000000000000010011000000000
	iINC=32'b00000000000000000000001100000000
	iACM_CTRLSTAT=8'b00000000
	iACM_ADDR_ADDR=8'b00000100
	iACM_DATA_ADDR=8'b00001000
	iADC_CTRL2_HI_ADDR=8'b00010000
	iADC_STAT_HI_ADDR=8'b00100000
	Sym_IAP_IR=32'b00000000000000000000000000000000
	Sym_IAP_DR2=32'b00000000000000000000000000000100
	Sym_IAP_DR5=32'b00000000000000000000000000001100
	Sym_IAP_DR16=32'b00000000000000000000000000010100
	Sym_IAP_DR26=32'b00000000000000000000000000010000
	Sym_IAP_DR=32'b00000000000000000000000000011000
	Sym_IAP_DR_LENGTH=32'b00000000000000000000000000011100
	Sym_IAP_TAP_NEW_STATE=32'b00000000000000000000000000100000
	Sym_ISC_ENABLE=32'b00000000000000000000000010000000
	Sym_ISC_PROGRAM=32'b00000000000000000000000010000011
	Sym_ISC_NOOP=32'b00000000000000000000000010000100
	Sym_ISC_ERASE=32'b00000000000000000000000010000101
	Sym_ISC_INCREMENT=32'b00000000000000000000000010000111
	Sym_ISC_DATA_SHIFT=32'b00000000000000000000000010001001
	Sym_ISC_VERIFY0=32'b00000000000000000000000010001101
	Sym_ISC_VERIFY1=32'b00000000000000000000000010001110
	Sym_numberofsdtiles=32'b00000000000000000000000000000110
	Sym_numberofmaprows=32'b00000000000000000000110101110100
	Sym_usec38=32'b00000000000000000000000001111111
	Sym_usec138=32'b00000000000000000000000111001100
	Sym_usec165=32'b00000000000000000000001000100110
	Sym_usec256=32'b00000000000000000000001101010101
	Sym_usec1500=32'b00000000000000000001001110000011
	Sym_sec1p5h=32'b00000000000000000000000001001100
	Sym_sec1p5l=32'b00000000000000000011011110111000
	Sym_usec20=32'b00000000000000000000000000101100
	Sym_usec100=32'b00000000000000000000000011011110
	Sym_usec200=32'b00000000000000000000000110111100
	Sym_usec264=32'b00000000000000000000001001001010
	Label_initialize=32'b00000000000000000000000000011001
	Label_do_idly1=32'b00000000000000000000000000100010
	Label_busyok=32'b00000000000000000000000000101101
	Label_enableok=32'b00000000000000000000000000111000
	Label_do_idly2=32'b00000000000000000000000000111010
	Label_do_bulk_program=32'b00000000000000000000000000111101
	Label_bulk_prog=32'b00000000000000000000000010001000
	Label_do_bfor1=32'b00000000000000000000000010010011
	Label_do_bdly1=32'b00000000000000000000000010010111
	Label_progwaitok=32'b00000000000000000000000010100000
	Label_bulk_prog_fail=32'b00000000000000000000000010100100
	Label_do_program_rlock=32'b00000000000000000000000010101000
	Label_do_prl1=32'b00000000000000000000000010101001
	Label_do_prl2=32'b00000000000000000000000010101011
	Label_rlock_ok=32'b00000000000000000000000010111100
	Label_do_erase_disturb=32'b00000000000000000000000010111101
	Label_do_eddly1=32'b00000000000000000000000011000100
	Label_do_eddone=32'b00000000000000000000000011001010
	Label_poll_program=32'b00000000000000000000000011001100
	Label_poll_pl1=32'b00000000000000000000000011001101
	Label_poll_pdly1=32'b00000000000000000000000011010001
	Label_poll_pdone=32'b00000000000000000000000011011011
	Label_do_exit=32'b00000000000000000000000011011100
	Label_do_exjmp=32'b00000000000000000000000011100100
	Label_do_exdly1=32'b00000000000000000000000011100101
	Label_do_exdly2=32'b00000000000000000000000011101010
	Label_do_array_verify_0_pass=32'b00000000000000000000000011101110
	Label_do_av0p_loop=32'b00000000000000000000000011110011
	Label_do_av0p_fail=32'b00000000000000000000000011111110
	Label_do_array_verify_0_fail=32'b00000000000000000000000100000010
	Label_do_av0f_loop=32'b00000000000000000000000100000111
	Label_do_av0f_fail=32'b00000000000000000000000100010010
	Label_exe_verify=32'b00000000000000000000000100010110
	Label_ev_dly=32'b00000000000000000000000100011011
	Label_readverstatus=32'b00000000000000000000000100100001
	Label_exe_verify_done=32'b00000000000000000000000100100111
   Generated name = SF_Zi1_COREABC_0_INSTRUCTIONS_Z4

@W: CG133 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":663:34:663:37|No assignment to MULT
@W: CG133 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":664:34:664:34|No assignment to A
@W: CG133 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":665:34:665:34|No assignment to B
@W: CG133 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":1295:16:1295:16|No assignment to b
@W: CG360 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":225:9:225:14|No assignment to wire DEBUG1

@W: CG360 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":226:9:226:14|No assignment to wire DEBUG2

@W: CG133 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":251:12:251:14|No assignment to iii
@W: CG133 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":252:25:252:33|No assignment to RAMDOUTXX
@W: CL169 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":998:4:998:9|Pruning Register GETINST 

@W: CL169 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":485:12:485:17|Pruning Register genblk19.UROM.upper_addr[7:0] 

@W: CL208 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":998:4:998:9|All reachable assignments to bit 16 of ZREGISTER[16:0] assign 0, register removed by optimization
@W: CL208 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":998:4:998:9|All reachable assignments to bit 4 of STKPTR[7:0] assign 1, register removed by optimization
@W: CL208 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":998:4:998:9|All reachable assignments to bit 5 of STKPTR[7:0] assign 1, register removed by optimization
@W: CL208 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":998:4:998:9|All reachable assignments to bit 6 of STKPTR[7:0] assign 1, register removed by optimization
@W: CL208 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":998:4:998:9|All reachable assignments to bit 7 of STKPTR[7:0] assign 1, register removed by optimization
@W: CL207 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":998:4:998:9|All reachable assignments to ISR assign 0, register removed by optimization
@W: CL207 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":998:4:998:9|All reachable assignments to DOISR assign 0, register removed by optimization
@W: CL207 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":785:4:785:9|All reachable assignments to ISR_ACCUM_ZERO assign 0, register removed by optimization
@W: CL207 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":785:4:785:9|All reachable assignments to ISR_ACCUM_NEG assign 0, register removed by optimization
@W: CL260 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":468:12:468:17|Pruning Register bit 1 of genblk19.UROM.INSTR_SLOT[1:0] 

@N: CG364 :"F:\zeroization\SF_Zi1\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v":23:7:23:15|Synthesizing module INBUF_MSS

@N: CG364 :"F:\zeroization\SF_Zi1\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v":37:7:37:16|Synthesizing module OUTBUF_MSS

@N: CG364 :"F:\zeroization\SF_Zi1\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v":151:7:151:13|Synthesizing module MSS_CCC

@N: CG364 :"F:\Microsemi\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\smartfusion.v":2566:7:2566:11|Synthesizing module RCOSC

@N: CG364 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":5:7:5:38|Synthesizing module SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC

@N: CG364 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\mss_tshell.v":1:7:1:13|Synthesizing module MSS_APB

@N: CG364 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\SF_Zi1_MSS.v":5:7:5:16|Synthesizing module SF_Zi1_MSS

@N: CG364 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\SF_Zi1.v":5:7:5:12|Synthesizing module SF_Zi1

@W: CL157 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":62:7:62:18|*Output RCOSC_CLKOUT has undriven bits - a simulation mismatch is possible 
@W: CL157 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":63:7:63:20|*Output MAINXIN_CLKOUT has undriven bits - a simulation mismatch is possible 
@W: CL157 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":64:7:64:18|*Output LPXIN_CLKOUT has undriven bits - a simulation mismatch is possible 
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":36:7:36:10|Input CLKA is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":37:7:37:14|Input CLKA_PAD is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":38:7:38:15|Input CLKA_PADP is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":39:7:39:15|Input CLKA_PADN is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":40:7:40:10|Input CLKB is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":41:7:41:14|Input CLKB_PAD is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":42:7:42:15|Input CLKB_PADP is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":43:7:43:15|Input CLKB_PADN is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":44:7:44:10|Input CLKC is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":45:7:45:14|Input CLKC_PAD is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":46:7:46:15|Input CLKC_PADP is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":47:7:47:15|Input CLKC_PADN is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":48:7:48:13|Input MAINXIN is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":49:7:49:11|Input LPXIN is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":50:7:50:13|Input MAC_CLK is unused
@N: CL201 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":998:4:998:9|Trying to extract state machine for register ICYCLE
Extracted state machine for register ICYCLE
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":134:10:134:18|Input PSLVERR_M is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":138:10:138:15|Input INTREQ is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":141:10:141:19|Input INITDATVAL is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":142:10:142:17|Input INITDONE is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":143:27:143:34|Input INITADDR is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":144:15:144:22|Input INITDATA is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":148:11:148:16|Input PSEL_S is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":149:11:149:19|Input PENABLE_S is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":150:11:150:18|Input PWRITE_S is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":151:28:151:34|Input PADDR_S is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":152:28:152:35|Input PWDATA_S is unused
@N: CL201 :"F:\zeroization\SF_Zi1\hdl\IAP.v":317:0:317:5|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 5 reachable states with original encodings of:
   000
   001
   010
   011
   100
@N: CL201 :"F:\zeroization\SF_Zi1\hdl\IAP.v":306:0:306:5|Trying to extract state machine for register currentState
Extracted state machine for register currentState
State machine has 16 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
   1011
   1100
   1101
   1110
   1111
@W: CL246 :"F:\zeroization\SF_Zi1\hdl\IAP.v":72:13:72:21|Input port bits 23 to 6 of APB_PADDR[23:0] are unused

@W: CL246 :"F:\zeroization\SF_Zi1\hdl\IAP.v":72:13:72:21|Input port bits 1 to 0 of APB_PADDR[23:0] are unused

@W: CL246 :"F:\zeroization\SF_Zi1\hdl\IAP.v":78:13:78:22|Input port bits 31 to 16 of APB_PWDATA[31:0] are unused

@W: CL159 :"F:\zeroization\SF_Zi1\hdl\IAP.v":58:6:58:9|Input CPHA is unused
@W: CL246 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":54:18:54:22|Input port bits 23 to 12 of PADDR[23:0] are unused

@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":52:13:52:19|Input PRESETN is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":53:13:53:16|Input PCLK is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":84:18:84:25|Input PRDATAS1 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":85:18:85:25|Input PRDATAS2 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":86:18:86:25|Input PRDATAS3 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":87:18:87:25|Input PRDATAS4 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":88:18:88:25|Input PRDATAS5 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":89:18:89:25|Input PRDATAS6 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":90:18:90:25|Input PRDATAS7 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":91:18:91:25|Input PRDATAS8 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":92:18:92:25|Input PRDATAS9 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":93:18:93:26|Input PRDATAS10 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":94:18:94:26|Input PRDATAS11 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":95:18:95:26|Input PRDATAS12 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":96:18:96:26|Input PRDATAS13 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":97:18:97:26|Input PRDATAS14 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":98:18:98:26|Input PRDATAS15 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":100:13:100:20|Input PREADYS1 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":101:13:101:20|Input PREADYS2 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":102:13:102:20|Input PREADYS3 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":103:13:103:20|Input PREADYS4 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":104:13:104:20|Input PREADYS5 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":105:13:105:20|Input PREADYS6 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":106:13:106:20|Input PREADYS7 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":107:13:107:20|Input PREADYS8 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":108:13:108:20|Input PREADYS9 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":109:13:109:21|Input PREADYS10 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":110:13:110:21|Input PREADYS11 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":111:13:111:21|Input PREADYS12 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":112:13:112:21|Input PREADYS13 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":113:13:113:21|Input PREADYS14 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":114:13:114:21|Input PREADYS15 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":116:13:116:21|Input PSLVERRS1 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":117:13:117:21|Input PSLVERRS2 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":118:13:118:21|Input PSLVERRS3 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":119:13:119:21|Input PSLVERRS4 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":120:13:120:21|Input PSLVERRS5 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":121:13:121:21|Input PSLVERRS6 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":122:13:122:21|Input PSLVERRS7 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":123:13:123:21|Input PSLVERRS8 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":124:13:124:21|Input PSLVERRS9 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":125:13:125:22|Input PSLVERRS10 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":126:13:126:22|Input PSLVERRS11 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":127:13:127:22|Input PSLVERRS12 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":128:13:128:22|Input PSLVERRS13 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":129:13:129:22|Input PSLVERRS14 is unused
@W: CL159 :"F:\zeroization\SF_Zi1\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":130:13:130:22|Input PSLVERRS15 is unused
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Jan 05 16:53:03 2012

###########################################################]
Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00
Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved
Product Version E-2010.09A-1
Reading constraint file: F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\mss_tshell_syn.sdc
@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 

@W: MO111 :"f:\zeroization\sf_zi1\component\work\sf_zi1_mss\mss_ccc_0\sf_zi1_mss_tmp_mss_ccc_0_mss_ccc.v":62:7:62:18|tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"f:\zeroization\sf_zi1\component\work\sf_zi1_mss\mss_ccc_0\sf_zi1_mss_tmp_mss_ccc_0_mss_ccc.v":63:7:63:20|tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"f:\zeroization\sf_zi1\component\work\sf_zi1_mss\mss_ccc_0\sf_zi1_mss_tmp_mss_ccc_0_mss_ccc.v":64:7:64:18|tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: BN132 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Removing sequential instance COREABC_0.genblk19.UROM.INSTR_SLOT[0],  because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_MUXC

Available hyper_sources - for debug and ip models
	None Found

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB)

@N:"f:\zeroization\sf_zi1\hdl\iap.v":317:0:317:5|Found counter in view:work.iap_Z2(verilog) inst drLength[7:0]
Encoding state machine work.iap_Z2(verilog)-state[4:0]
original code -> new code
   000 -> 00001
   001 -> 00010
   010 -> 00100
   011 -> 01000
   100 -> 10000
Encoding state machine work.iap_Z2(verilog)-currentState[15:0]
original code -> new code
   0000 -> 0000
   0001 -> 0001
   0010 -> 0010
   0011 -> 0011
   0100 -> 0100
   0101 -> 0101
   0110 -> 0110
   0111 -> 0111
   1000 -> 1000
   1001 -> 1001
   1010 -> 1010
   1011 -> 1011
   1100 -> 1100
   1101 -> 1101
   1110 -> 1110
   1111 -> 1111
@N: MF176 |Default generator successful 
@N: MO106 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\instructions.v":142:4:142:7|Found ROM, 'genblk19\.UROM\.UROM.doins[57:0]', 296 words by 58 bits 
Encoding state machine work.SF_Zi1_COREABC_0_COREABC_Z3(verilog)-ICYCLE[3:0]
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N: MF176 |Default generator successful 
@N: MF176 |Default generator successful 
@N: MF238 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":253:34:253:42|Found 16 bit incrementor, 'un1_SMADDR[15:0]'
@N: MF176 |Default generator successful 
@N: MF238 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":985:35:985:61|Found 4 bit incrementor, 'un1_STKPTRP1[3:0]'
@W: MO129 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Sequential instance COREABC_0.genblk19.UROM.INSTR_ADDR[9] has been reduced to a combinational gate by constant propagation
@W: MO129 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Sequential instance COREABC_0.genblk19.UROM.INSTR_ADDR[10] has been reduced to a combinational gate by constant propagation
@W: MO129 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Sequential instance COREABC_0.genblk19.UROM.INSTR_ADDR[11] has been reduced to a combinational gate by constant propagation
@W: MO129 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Sequential instance COREABC_0.genblk19.UROM.INSTR_ADDR[12] has been reduced to a combinational gate by constant propagation
@W: MO129 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Sequential instance COREABC_0.genblk19.UROM.INSTR_ADDR[13] has been reduced to a combinational gate by constant propagation
@W: MO129 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Sequential instance COREABC_0.genblk19.UROM.INSTR_ADDR[14] has been reduced to a combinational gate by constant propagation
@W: MO129 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Sequential instance COREABC_0.genblk19.UROM.INSTR_ADDR[15] has been reduced to a combinational gate by constant propagation
@W: BN132 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[31],  because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[30]
@W: BN132 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[30],  because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[29]
@W: BN132 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[29],  because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[28]
@W: BN132 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[28],  because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[27]
@W: BN132 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[27],  because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[26]
@W: BN132 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[26],  because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[25]
@W: BN132 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[25],  because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[24]
@W: BN132 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[24],  because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[23]
@W: BN132 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[23],  because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[22]
@W: BN132 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[22],  because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[21]
@W: BN132 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[21],  because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[20]
@W: BN132 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[20],  because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[19]
@W: BN132 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[19],  because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[18]
@W: BN132 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[18],  because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[17]
@W: BN132 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[17],  because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[16]
Finished factoring (Time elapsed 0h:00m:02s; Memory used current: 76MB peak: 77MB)

@N: BN116 :"f:\zeroization\sf_zi1\hdl\iap.v":317:0:317:5|Removing sequential instance iap_0.MOSI of view:PrimLib.dff(prim) because there are no references to its outputs 
@N: BN116 :"f:\zeroization\sf_zi1\hdl\iap.v":317:0:317:5|Removing sequential instance iap_0.SS[0] of view:PrimLib.dffs(prim) because there are no references to its outputs 
@N: BN116 :"f:\zeroization\sf_zi1\hdl\iap.v":317:0:317:5|Removing sequential instance iap_0.sckEn of view:PrimLib.dffr(prim) because there are no references to its outputs 
Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:02s; Memory used current: 76MB peak: 77MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:03s; Memory used current: 68MB peak: 79MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:03s; Memory used current: 69MB peak: 79MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:07s; Memory used current: 69MB peak: 79MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:07s; Memory used current: 69MB peak: 79MB)

Finished preparing to map (Time elapsed 0h:00m:07s; Memory used current: 73MB peak: 79MB)


High Fanout Net Report
**********************

Driver Instance / Pin Name                            Fanout, notes                   
--------------------------------------------------------------------------------------
iap_0.state[4] / Q                                    26                              
COREABC_0.SMADDR[0] / Q                               58                              
COREABC_0.SMADDR[1] / Q                               58                              
COREABC_0.SMADDR[2] / Q                               54                              
COREABC_0.SMADDR[3] / Q                               59                              
COREABC_0.SMADDR[4] / Q                               80                              
COREABC_0.SMADDR[5] / Q                               48                              
COREABC_0.genblk19.UROM.INSTR_SCMD[0] / Q             27                              
COREABC_0.genblk19.UROM.INSTR_DATA[16] / Q            32                              
COREABC_0.RSTSYNC2 / Q                                119 : 106 asynchronous set/reset
COREABC_0.genblk19.UROM.UROM.doins_i_a2_33[0] / Y     26                              
COREABC_0.genblk19.UROM.UROM.doins_i_o2_1[1] / Y      32                              
COREABC_0.genblk19.UROM.UROM.doins_i_a2_35[0] / Y     32                              
COREABC_0.genblk19.UROM.UROM.doins_0_o2[14] / Y       26                              
COREABC_0.genblk19.UROM.UROM.doins_i_o2[2] / Y        34                              
COREABC_0.genblk19.UROM.UROM.doins_i_a2_34[0] / Y     26                              
COREABC_0.genblk19.UROM.UROM.doins_i_o2_3[1] / Y      26                              
COREABC_0.genblk19.UROM.UROM.doins_i_a2_33[1] / Y     26                              
COREABC_0.genblk19.UROM.UROM.doins_i_o2_2[1] / Y      32                              
COREABC_0.genblk19.UROM.UROM.doins_0_o2[15] / Y       31                              
COREABC_0.genblk19.UROM.UROM.doins_i_o2_2[0] / Y      33                              
COREABC_0.genblk19.UROM.UROM.doins_0_o2_1[4] / Y      31                              
COREABC_0.genblk19.UROM.UROM.doins_i_a2_32[0] / Y     32                              
COREABC_0.un1_ACCUM_NEXT8_1 / Y                       32                              
COREABC_0.ALUOUT_2_sqmuxa / Y                         32                              
COREABC_0.ALUOUT_3_sqmuxa / Y                         32                              
COREABC_0.ALUOUT_5_sqmuxa / Y                         32                              
COREABC_0.ALUOUT_6_sqmuxa / Y                         32                              
COREABC_0.ALUOUT_7_sqmuxa / Y                         32                              
COREABC_0.to_logic_9[0] / Y                           35                              
COREABC_0.xhdl_31.MSEL[2] / Y                         40                              
COREABC_0.ALUOUT_1_sqmuxa / Y                         32                              
COREABC_0.ACCUMULATOR4 / Y                            32                              
COREABC_0.USE_ACC_1 / Y                               32                              
======================================================================================

@N: FP130 |Promoting Net TRSTB_c on CLKINT  I_430 
@N: FP130 |Promoting Net COREABC_0.SMADDR[4] on CLKINT  I_431 
@N: FP130 |Promoting Net COREABC_0.SMADDR[3] on CLKINT  I_432 
Replicating Combinational Instance COREABC_0.USE_ACC_1, fanout 32 segments 2
Replicating Combinational Instance COREABC_0.ACCUMULATOR4, fanout 32 segments 2
Replicating Combinational Instance COREABC_0.ALUOUT_1_sqmuxa, fanout 32 segments 2
Replicating Combinational Instance COREABC_0.xhdl_31.MSEL[2], fanout 40 segments 2
Replicating Combinational Instance COREABC_0.to_logic_9[0], fanout 35 segments 2
Replicating Combinational Instance COREABC_0.ALUOUT_7_sqmuxa, fanout 32 segments 2
Replicating Combinational Instance COREABC_0.ALUOUT_6_sqmuxa, fanout 32 segments 2
Replicating Combinational Instance COREABC_0.ALUOUT_5_sqmuxa, fanout 32 segments 2
Replicating Combinational Instance COREABC_0.ALUOUT_3_sqmuxa, fanout 32 segments 2
Replicating Combinational Instance COREABC_0.ALUOUT_2_sqmuxa, fanout 32 segments 2
Replicating Combinational Instance COREABC_0.un1_ACCUM_NEXT8_1, fanout 32 segments 2
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_i_a2_32[0], fanout 32 segments 2
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_0_o2_1[4], fanout 31 segments 2
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_i_o2_2[0], fanout 33 segments 2
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_0_o2[15], fanout 31 segments 2
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_i_o2_2[1], fanout 32 segments 2
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_i_a2_33[1], fanout 26 segments 2
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_i_o2_3[1], fanout 26 segments 2
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_i_a2_34[0], fanout 26 segments 2
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_i_o2[2], fanout 34 segments 2
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_0_o2[14], fanout 26 segments 2
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_i_a2_35[0], fanout 32 segments 2
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_i_o2_1[1], fanout 32 segments 2
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_i_a2_33[0], fanout 26 segments 2
Replicating Sequential Instance COREABC_0.genblk19.UROM.INSTR_DATA[16], fanout 32 segments 2
Replicating Sequential Instance COREABC_0.genblk19.UROM.INSTR_SCMD[0], fanout 29 segments 2
Replicating Sequential Instance COREABC_0.SMADDR[5], fanout 49 segments 3
Replicating Sequential Instance COREABC_0.SMADDR[2], fanout 58 segments 3
Replicating Sequential Instance COREABC_0.SMADDR[1], fanout 62 segments 3
Replicating Sequential Instance COREABC_0.SMADDR[0], fanout 59 segments 3
Replicating Sequential Instance iap_0.state[4], fanout 26 segments 2
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_i_a2_30[0], fanout 25 segments 2
Replicating Sequential Instance COREABC_0.SMADDR[6], fanout 25 segments 2
Finished technology mapping (Time elapsed 0h:00m:08s; Memory used current: 83MB peak: 85MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:08s; Memory used current: 83MB peak: 85MB)


Added 0 Buffers
Added 37 Cells via replication
	Added 12 Sequential Cells via replication
	Added 25 Combinational Cells via replication
Finished restoring hierarchy (Time elapsed 0h:00m:08s; Memory used current: 83MB peak: 85MB)

Writing Analyst data base F:\zeroization\SF_Zi1\synthesis\SF_Zi1.srm
Finished Writing Netlist Databases (Time elapsed 0h:00m:08s; Memory used current: 81MB peak: 85MB)

Writing EDIF Netlist and constraint files
E-2010.09A-1
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:08s; Memory used current: 84MB peak: 85MB)

@W: MT420 |Found inferred clock SF_Zi1_MSS|MSS_ADLIB_INST_EMCCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:SF_Zi1_MSS_0.MSS_ADLIB_INST_EMCCLK"

Found clock FAB_CLK with period 50.00ns 
Found clock FCLK with period 50.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Thu Jan 05 16:53:15 2012
#


Top view:               SF_Zi1
Library name:           smartfusion
Operating conditions:   COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree )
Requested Frequency:    20.0 MHz
Wire load mode:         top
Wire load model:        smartfusion
Paths requested:        5
Constraint File(s):    F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\mss_tshell_syn.sdc
                       
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: 6.260

                   Requested     Estimated     Requested     Estimated               Clock        Clock      
Starting Clock     Frequency     Frequency     Period        Period        Slack     Type         Group      
-------------------------------------------------------------------------------------------------------------
FAB_CLK            20.0 MHz      24.6 MHz      50.000        40.719        6.260     declared     clk_group_0
FCLK               20.0 MHz      NA            50.000        NA            NA        declared     clk_group_0
=============================================================================================================





Clock Relationships
*******************

Clocks             |    rise  to  rise   |    fall  to  fall    |    rise  to  fall    |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------
Starting  Ending   |  constraint  slack  |  constraint  slack   |  constraint  slack   |  constraint  slack
-----------------------------------------------------------------------------------------------------------
FAB_CLK   FAB_CLK  |  50.000      9.281  |  50.000      46.594  |  25.000      14.416  |  25.000      6.260
===========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: FAB_CLK
====================================



Starting Points with Worst Slack
********************************

                                                                        Starting                                                Arrival           
Instance                                                                Reference     Type          Pin     Net                 Time        Slack 
                                                                        Clock                                                                     
--------------------------------------------------------------------------------------------------------------------------------------------------
iap_0.TMS                                                               FAB_CLK       DFN0E0P0      Q       TMS_c               0.653       6.260 
COREABC_0.genblk19\.UROM\.INSTR_CMD[1]                                  FAB_CLK       DFN1          Q       INSTR_CMD[1]        0.580       9.281 
COREABC_0.genblk19\.UROM\.INSTR_CMD[0]                                  FAB_CLK       DFN1          Q       INSTR_CMD[0]        0.737       9.309 
COREABC_0.genblk19\.UROM\.INSTR_CMD[2]                                  FAB_CLK       DFN1          Q       INSTR_CMD[2]        0.737       10.937
COREABC_0.genblk19\.UROM\.INSTR_SCMD[1]                                 FAB_CLK       DFN1          Q       INSTR_SCMD[1]       0.737       11.399
COREABC_0.genblk19\.UROM\.INSTR_SCMD[2]                                 FAB_CLK       DFN1          Q       INSTR_SCMD[2]       0.737       11.620
iap_0.currentState[3]                                                   FAB_CLK       DFN1P0        Q       currentState[3]     0.737       14.416
COREABC_0.genblk15\.URAM\.UR.genblk4\.UG3\.UR_xhdl12.Ram256x16_R0C0     FAB_CLK       RAM512X18     RD2     RAMRDATA[2]         2.963       14.731
iap_0.targetState[3]                                                    FAB_CLK       DFN1E1        Q       targetState[3]      0.737       14.758
COREABC_0.genblk15\.URAM\.UR.genblk4\.UG3\.UR_xhdl12.Ram256x16_R0C0     FAB_CLK       RAM512X18     RD0     RAMRDATA[0]         2.963       14.828
==================================================================================================================================================


Ending Points with Worst Slack
******************************

                              Starting                                              Required           
Instance                      Reference     Type         Pin     Net                Time         Slack 
                              Clock                                                                    
-------------------------------------------------------------------------------------------------------
iap_0.tckCnt[4]               FAB_CLK       DFN1         D       tckCnt_15[4]       24.427       6.260 
iap_0.tckCnt[6]               FAB_CLK       DFN1         D       tckCnt_15[6]       24.461       7.237 
iap_0.tckCnt[7]               FAB_CLK       DFN1         D       tckCnt_15[7]       24.427       7.519 
iap_0.tckCnt[5]               FAB_CLK       DFN1         D       tckCnt_15[5]       24.427       7.534 
iap_0.tckCnt[3]               FAB_CLK       DFN1         D       tckCnt_15[3]       24.427       8.117 
iap_0.tckCnt[2]               FAB_CLK       DFN1         D       tckCnt_15[2]       24.427       8.766 
iap_0.tckCnt[0]               FAB_CLK       DFN1         D       tckCnt_15[0]       24.427       9.175 
COREABC_0.STD_ACCUM_ZERO      FAB_CLK       DFN1E1C0     D       tmp_4[0]           49.461       9.281 
iap_0.tckCnt[1]               FAB_CLK       DFN1         D       tckCnt_15[1]       24.427       9.903 
COREABC_0.ACCUMULATOR[31]     FAB_CLK       DFN1E1C0     D       ACCUM_NEXT[31]     49.461       10.312
=======================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      25.000
    - Setup time:                            0.573
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         24.427

    - Propagation time:                      18.166
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     6.260

    Number of logic level(s):                13
    Starting point:                          iap_0.TMS / Q
    Ending point:                            iap_0.tckCnt[4] / D
    The start point is clocked by            FAB_CLK [falling] on pin CLK
    The end   point is clocked by            FAB_CLK [rising] on pin CLK

Instance / Net                                            Pin      Pin               Arrival     No. of    
Name                                         Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------
iap_0.TMS                                    DFN0E0P0     Q        Out     0.653     0.653       -         
TMS_c                                        Net          -        -       2.037     -           13        
iap_0.currentState_RNIA3KH[3]                NOR3C        C        In      -         2.690       -         
iap_0.currentState_RNIA3KH[3]                NOR3C        Y        Out     0.641     3.332       -         
N_548                                        Net          -        -       0.386     -           2         
iap_0.currentState_RNIR7LM[0]                OR2B         B        In      -         3.717       -         
iap_0.currentState_RNIR7LM[0]                OR2B         Y        Out     0.627     4.345       -         
N_889                                        Net          -        -       0.322     -           1         
iap_0.currentState_RNIGNV32[0]               OAI1         C        In      -         4.666       -         
iap_0.currentState_RNIGNV32[0]               OAI1         Y        Out     0.655     5.322       -         
currentState_ns[1]                           Net          -        -       0.386     -           2         
iap_0.targetState_RNIUU4B2[1]                OR2A         A        In      -         5.707       -         
iap_0.targetState_RNIUU4B2[1]                OR2A         Y        Out     0.466     6.173       -         
N_402                                        Net          -        -       0.322     -           1         
iap_0.targetState_RNIA8G8A[1]                NOR3C        A        In      -         6.495       -         
iap_0.targetState_RNIA8G8A[1]                NOR3C        Y        Out     0.525     7.019       -         
tckEn14_NE_9                                 Net          -        -       0.386     -           2         
iap_0.state_RNI4IQJD[1]                      AO1B         A        In      -         7.405       -         
iap_0.state_RNI4IQJD[1]                      AO1B         Y        Out     0.469     7.874       -         
N_867                                        Net          -        -       0.322     -           1         
iap_0.state_RNI3BN5F[1]                      NOR2B        A        In      -         8.196       -         
iap_0.state_RNI3BN5F[1]                      NOR2B        Y        Out     0.488     8.684       -         
N_229                                        Net          -        -       0.386     -           2         
iap_0.state_RNIV755I[4]                      OR2B         B        In      -         9.070       -         
iap_0.state_RNIV755I[4]                      OR2B         Y        Out     0.516     9.586       -         
un1_tckEn20_2                                Net          -        -       2.127     -           15        
iap_0.un1_tckEn20_4.ADD_8x8_fast_I2_G0N      OR2A         B        In      -         11.713      -         
iap_0.un1_tckEn20_4.ADD_8x8_fast_I2_G0N      OR2A         Y        Out     0.646     12.360      -         
N122                                         Net          -        -       0.806     -           3         
iap_0.un1_tckEn20_4.ADD_8x8_fast_I14_Y       NOR2B        B        In      -         13.166      -         
iap_0.un1_tckEn20_4.ADD_8x8_fast_I14_Y       NOR2B        Y        Out     0.627     13.794      -         
I22_un1_Y                                    Net          -        -       0.386     -           2         
iap_0.un1_tckEn20_4.ADD_8x8_fast_I40_Y_0     AX1E         A        In      -         14.179      -         
iap_0.un1_tckEn20_4.ADD_8x8_fast_I40_Y_0     AX1E         Y        Out     0.970     15.149      -         
un1_tckEn20_4_i_0[4]                         Net          -        -       0.806     -           3         
iap_0.tckCnt_RNO_2[4]                        OA1          B        In      -         15.956      -         
iap_0.tckCnt_RNO_2[4]                        OA1          Y        Out     0.902     16.858      -         
tckCnt_15_iv_0_0_3[4]                        Net          -        -       0.322     -           1         
iap_0.tckCnt_RNO[4]                          OR3C         C        In      -         17.179      -         
iap_0.tckCnt_RNO[4]                          OR3C         Y        Out     0.666     17.845      -         
tckCnt_15[4]                                 Net          -        -       0.322     -           1         
iap_0.tckCnt[4]                              DFN1         D        In      -         18.166      -         
===========================================================================================================
Total path delay (propagation time + setup) of 18.740 is 9.426(50.3%) logic and 9.314(49.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Target Part: A2F200M3F_FBGA484_STD
Report for cell SF_Zi1.verilog
  Core Cell usage:
              cell count     area count*area
              AND2    36      1.0       36.0
              AND3    18      1.0       18.0
               AO1    16      1.0       16.0
              AO13    13      1.0       13.0
              AO16     1      1.0        1.0
              AO18    17      1.0       17.0
              AO1A     6      1.0        6.0
              AO1B    20      1.0       20.0
              AO1C    15      1.0       15.0
              AO1D    10      1.0       10.0
              AOI1     6      1.0        6.0
             AOI1B    93      1.0       93.0
              AOI5     1      1.0        1.0
               AX1     2      1.0        2.0
              AX1A     1      1.0        1.0
              AX1B     2      1.0        2.0
              AX1C     7      1.0        7.0
              AX1D     1      1.0        1.0
              AX1E     5      1.0        5.0
            CLKINT     3      0.0        0.0
               GND    10      0.0        0.0
               INV     3      1.0        3.0
              MAJ3    17      1.0       17.0
             MAJ3X     1      1.0        1.0
              MIN3     2      1.0        2.0
           MSS_CCC     1      0.0        0.0
               MX2   131      1.0      131.0
              MX2A    11      1.0       11.0
              MX2B    25      1.0       25.0
              MX2C    10      1.0       10.0
             NAND2    12      1.0       12.0
              NOR2   129      1.0      129.0
             NOR2A   113      1.0      113.0
             NOR2B   139      1.0      139.0
              NOR3    11      1.0       11.0
             NOR3A    28      1.0       28.0
             NOR3B    50      1.0       50.0
             NOR3C   190      1.0      190.0
               OA1    29      1.0       29.0
              OA1A    58      1.0       58.0
              OA1B     5      1.0        5.0
              OA1C    16      1.0       16.0
              OAI1    23      1.0       23.0
               OR2   175      1.0      175.0
              OR2A   191      1.0      191.0
              OR2B   195      1.0      195.0
               OR3    55      1.0       55.0
              OR3A    76      1.0       76.0
              OR3B    70      1.0       70.0
              OR3C    96      1.0       96.0
             RCOSC     1      0.0        0.0
               VCC    10      0.0        0.0
               XA1     1      1.0        1.0
              XA1A     2      1.0        2.0
              XA1B     1      1.0        1.0
              XA1C     3      1.0        3.0
              XAI1    48      1.0       48.0
             XAI1A     7      1.0        7.0
             XNOR2    29      1.0       29.0
             XNOR3    17      1.0       17.0
               XO1     2      1.0        2.0
              XO1A     2      1.0        2.0
              XOR2    64      1.0       64.0
              XOR3     4      1.0        4.0


          DFN0E0P0     1      1.0        1.0
          DFN0E1P0     1      1.0        1.0
              DFN1    43      1.0       43.0
            DFN1C0    11      1.0       11.0
          DFN1E0C0    17      1.0       17.0
            DFN1E1    20      1.0       20.0
          DFN1E1C0    50      1.0       50.0
            DFN1P0    38      1.0       38.0
           MSS_APB     1      0.0        0.0
         RAM512X18     2      0.0        0.0
                   -----          ----------
             TOTAL  2520              2492.0


  IO Cell usage:
              cell count
             INBUF     3
         INBUF_MSS     2
            OUTBUF    12
        OUTBUF_MSS     1
                   -----
             TOTAL    18


Core Cells         : 2492 of 4608 (54%)
IO Cells           : 18

  RAM/ROM Usage Summary
Block Rams : 2 of 8 (25%)

Mapper successful!
Process took 0h:00m:10s realtime, 0h:00m:09s cputime
# Thu Jan 05 16:53:15 2012

###########################################################]
