Synopsys Actel Technology Pre-mapping, Version mapact, Build 729R, Built Jun 20 2012 09:20:46
Copyright (C) 1994-2012, Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
Product Version F-2012.03M-SP1 

Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

Reading constraint file: C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\mss_tshell_syn.sdc
@L: C:\LPF_AC382_DF\A2F500\zeroization\synthesis\SF_Zi1_scck.rpt 
Printing clock  summary report in "C:\LPF_AC382_DF\A2F500\zeroization\synthesis\SF_Zi1_scck.rpt" file 
@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 
@N: MF547 |Generated clock conversion disabled 

Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)


Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)



Clock Summary
**************

Start       Requested     Requested     Clock        Clock          
Clock       Frequency     Period        Type         Group          
--------------------------------------------------------------------
System      1.0 MHz       1000.000      system       system_clkgroup
FAB_CLK     20.0 MHz      50.000        declared     clk_group_0    
FCLK        20.0 MHz      50.000        declared     clk_group_0    
====================================================================


Finished Pre Mapping Phase. (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 59MB)

@N: BN225 |Writing default property annotation file C:\LPF_AC382_DF\A2F500\zeroization\synthesis\SF_Zi1.sap.
Pre-mapping successful!

At Mapper Exit (Time elapsed 0h:00m:00s; Memory used current: 24MB peak: 59MB)

Process took 0h:00m:03s realtime, 0h:00m:01s cputime
# Mon Nov 19 10:28:45 2012

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