#Build: Synplify Pro F-2012.03M-SP1 , Build 084R, Jun 15 2012
#install: C:\Microsemi\Libero_v10.1\Synopsys\synplify_F201203MSP1
#OS: Windows 7 6.1
#Hostname: VW7-SHARMAT

#Implementation: synthesis

$ Start of Compile
#Mon Nov 19 10:28:33 2012

Synopsys Verilog Compiler, version comp201203rcp1, Build 084R, built Jun 15 2012
@N|Running in 32-bit mode
Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

@I::"C:\Microsemi\Libero_v10.1\Synopsys\synplify_F201203MSP1\lib\proasic\smartfusion.v"
@I::"C:\Microsemi\Libero_v10.1\Synopsys\synplify_F201203MSP1\lib\vlog\umr_capim.v"
@I::"C:\Microsemi\Libero_v10.1\Synopsys\synplify_F201203MSP1\lib\vlog\scemi_objects.v"
@I::"C:\Microsemi\Libero_v10.1\Synopsys\synplify_F201203MSP1\lib\vlog\scemi_pipes.svh"
@I::"C:\Microsemi\Libero_v10.1\Synopsys\synplify_F201203MSP1\lib\vlog\hypermods.v"
@I::"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ram256x16_smartfusion.v"
@I::"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ram256x8_rtl.v"
@I::"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ramblocks.v"
@I::"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\acmtable.v"
@I::"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\instructions.v"
@I:"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\instructions.v":"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\support.v"
@I::"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\iram512x9_smartfusion.v"
@N: CG334 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\iram512x9_smartfusion.v":62:17:62:29|Read directive translate_off 
@N: CG333 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\iram512x9_smartfusion.v":63:17:63:28|Read directive translate_on 
@I::"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\instructram.v"
@I::"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\instructnvm_bb.v"
@I::"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\debugblk.v"
@N: CG334 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\debugblk.v":68:17:68:29|Read directive translate_off 
@N: CG333 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\debugblk.v":745:17:745:28|Read directive translate_on 
@I::"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v"
@N: CG334 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":949:21:949:33|Read directive translate_off 
@N: CG333 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":951:21:951:32|Read directive translate_on 
@N: CG334 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":1326:17:1326:29|Read directive translate_off 
@N: CG333 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":1369:17:1369:28|Read directive translate_on 
@I::"C:\LPF_AC382_DF\A2F500\zeroization\hdl\IAP.v"
@I::"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v"
@I::"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v"
@I::"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\mss_tshell.v"
@I::"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\SF_Zi1_MSS.v"
@I::"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3_muxptob3.v"
@I::"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v"
@I::"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\SF_Zi1.v"
Verilog syntax check successful!
Selecting top level module SF_Zi1
@N: CG364 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":46:7:46:30|Synthesizing module SF_Zi1_COREABC_0_COREABC

	FAMILY=32'b00000000000000000000000000010010
	APB_AWIDTH=32'b00000000000000000000000000001010
	APB_DWIDTH=32'b00000000000000000000000000010000
	APB_SDEPTH=32'b00000000000000000000000000000011
	ICWIDTH=32'b00000000000000000000000000001010
	ZRWIDTH=32'b00000000000000000000000000010000
	IFWIDTH=32'b00000000000000000000000000000000
	IIWIDTH=32'b00000000000000000000000000001000
	IOWIDTH=32'b00000000000000000000000000001000
	STWIDTH=32'b00000000000000000000000000000100
	EN_RAM=32'b00000000000000000000000000000001
	EN_AND=32'b00000000000000000000000000000001
	EN_XOR=32'b00000000000000000000000000000001
	EN_OR=32'b00000000000000000000000000000001
	EN_ADD=32'b00000000000000000000000000000001
	EN_INC=32'b00000000000000000000000000000001
	EN_SHL=32'b00000000000000000000000000000001
	EN_SHR=32'b00000000000000000000000000000001
	EN_CALL=32'b00000000000000000000000000000001
	EN_PUSH=32'b00000000000000000000000000000001
	EN_MULT=32'b00000000000000000000000000000000
	EN_ACM=32'b00000000000000000000000000000000
	EN_DATAM=32'b00000000000000000000000000000010
	EN_INT=32'b00000000000000000000000000000000
	EN_IOREAD=32'b00000000000000000000000000000001
	EN_IOWRT=32'b00000000000000000000000000000001
	EN_ALURAM=32'b00000000000000000000000000000000
	EN_INDIRECT=32'b00000000000000000000000000000000
	ISRADDR=32'b00000000000000000000000000000001
	DEBUG=32'b00000000000000000000000000000001
	INSMODE=32'b00000000000000000000000000000000
	INITWIDTH=32'b00000000000000000000000000001011
	TESTMODE=32'b00000000000000000000000000000000
	ACT_CALIBRATIONDATA=32'b00000000000000000000000000000001
	IMEM_APB_ACCESS=32'b00000000000000000000000000000000
	UNIQ_STRING_LENGTH=32'b00000000000000000000000000010000
	MAX_NVMDWIDTH=32'b00000000000000000000000000100000
	BLANK=32'b11111111111111111111111111111111
	iNOP=32'b00000000000000000000000100000000
	iLOAD=32'b00000000000000000000001000000000
	iINCB=32'b00000000000000000000001100000000
	iAND=32'b00000000000000000000010000000000
	iOR=32'b00000000000000000000010100000000
	iXOR=32'b00000000000000000000011000000000
	iADD=32'b00000000000000000000011100000000
	iSUB=32'b00000000000000000000100000000000
	iSHL0=32'b00000000000000000000100100000000
	iSHL1=32'b00000000000000000000101000000000
	iSHLE=32'b00000000000000000000101100000000
	iROL=32'b00000000000000000000110000000000
	iSHR0=32'b00000000000000000000110100000000
	iSHR1=32'b00000000000000000000111000000000
	iSHRE=32'b00000000000000000000111100000000
	iROR=32'b00000000000000000001000000000000
	iCMP=32'b00000000000000000001000100000000
	iCMPLEQ=32'b00000000000000000001001000000000
	iBITCLR=32'b00000000000000000001001100000000
	iBITSET=32'b00000000000000000001010000000000
	iBITTST=32'b00000000000000000001010100000000
	iAPBREAD=32'b00000000000000000001011000000000
	iAPBWRT=32'b00000000000000000001011100000000
	iLOADZ=32'b00000000000000000001100000000000
	iDECZ=32'b00000000000000000001100100000000
	iINCZ=32'b00000000000000000001101000000000
	iIOWRT=32'b00000000000000000001101100000000
	iRAMREAD=32'b00000000000000000001110000000000
	iRAMWRT=32'b00000000000000000001110100000000
	iPUSH=32'b00000000000000000001111000000000
	iPOP=32'b00000000000000000001111100000000
	iIOREAD=32'b00000000000000000010000000000000
	iUSER=32'b00000000000000000010000100000000
	iJUMPB=32'b00000000000000000010001000000000
	iCALLB=32'b00000000000000000010001100000000
	iRETURNB=32'b00000000000000000010010000000000
	iRETISRB=32'b00000000000000000010010100000000
	iWAITB=32'b00000000000000000010011000000000
	iHALTB=32'b00000000000000000010011000000000
	iMULT=32'b00000000000000000010011100000000
	iDEC=32'b00000000000000000010100000000000
	iAPBREADZ=32'b00000000000000000010100100000000
	iAPBWRTZ=32'b00000000000000000010101000000000
	iADDZ=32'b00000000000000000010101100000000
	iSUBZ=32'b00000000000000000010110000000000
	iDAT=32'b00000000000000000000000000001010
	iDAT8=32'b00000000000000000000000000001011
	iDAT16=32'b00000000000000000000000000001100
	iDAT32=32'b00000000000000000000000000001101
	iACM=32'b00000000000000000000000000001110
	iACC=32'b00000000000000000000000000001111
	iRAM=32'b00000000000000000000000000010000
	DAT=32'b00000000000000000000000000001010
	DAT8=32'b00000000000000000000000000001011
	DAT16=32'b00000000000000000000000000001100
	DAT32=32'b00000000000000000000000000001101
	ACM=32'b00000000000000000000000000001110
	ACC=32'b00000000000000000000000000001111
	RAM=32'b00000000000000000000000000010000
	iIFNOT=32'b00000000000000000000000000000000
	iNOTIF=32'b00000000000000000000000000000000
	iIF=32'b00000000000000000000000000000001
	iUNTIL=32'b00000000000000000000000000000000
	iNOTUNTIL=32'b00000000000000000000000000000001
	iUNTILNOT=32'b00000000000000000000000000000001
	iWHILE=32'b00000000000000000000000000000001
	iZZERO=8'b00001000
	iNEGATIVE=8'b00000100
	iZERO=8'b00000010
	iLTE_ZERO=8'b00000110
	iALWAYS=8'b00000001
	iINPUT0=12'b000000010000
	iINPUT1=12'b000000100000
	iINPUT2=12'b000001000000
	iINPUT3=12'b000010000000
	iINPUT4=12'b000100000000
	iINPUT5=12'b001000000000
	iINPUT6=12'b010000000000
	iINPUT7=12'b100000000000
	iINPUT8=16'b0001000000000000
	iINPUT9=16'b0010000000000000
	iINPUT10=16'b0100000000000000
	iINPUT11=16'b1000000000000000
	iINPUT12=20'b00010000000000000000
	iINPUT13=20'b00100000000000000000
	iINPUT14=20'b01000000000000000000
	iINPUT15=20'b10000000000000000000
	iINPUT16=24'b000100000000000000000000
	iINPUT17=24'b001000000000000000000000
	iINPUT18=24'b010000000000000000000000
	iINPUT19=24'b100000000000000000000000
	iINPUT20=28'b0001000000000000000000000000
	iINPUT21=28'b0010000000000000000000000000
	iINPUT22=28'b0100000000000000000000000000
	iINPUT23=28'b1000000000000000000000000000
	iINPUT24=32'b00010000000000000000000000000000
	iINPUT25=32'b00100000000000000000000000000000
	iINPUT26=32'b01000000000000000000000000000000
	iINPUT27=32'b10000000000000000000000000000000
	iANYINPUT=32'b01111111111111111111111111110000
	ALWAYS=8'b00000001
	ZZERO=8'b00001000
	NEGATIVE=8'b00000100
	ZERO=8'b00000010
	LTE_ZERO=8'b00000110
	INPUT0=12'b000000010000
	INPUT1=12'b000000100000
	INPUT2=12'b000001000000
	INPUT3=12'b000010000000
	INPUT4=12'b000100000000
	INPUT5=12'b001000000000
	INPUT6=12'b010000000000
	INPUT7=12'b100000000000
	INPUT8=16'b0001000000000000
	INPUT9=16'b0010000000000000
	INPUT10=16'b0011000000000000
	INPUT11=16'b1000000000000000
	INPUT12=20'b00010000000000000000
	INPUT13=20'b00100000000000000000
	INPUT14=20'b01000000000000000000
	INPUT15=20'b10000000000000000000
	INPUT16=24'b000100000000000000000000
	INPUT17=24'b001000000000000000000000
	INPUT18=24'b001100000000000000000000
	INPUT19=24'b100000000000000000000000
	INPUT20=28'b0001000000000000000000000000
	INPUT21=28'b0010000000000000000000000000
	INPUT22=28'b0100000000000000000000000000
	INPUT23=28'b1000000000000000000000000000
	INPUT24=32'b00010000000000000000000000000000
	INPUT25=32'b00100000000000000000000000000000
	INPUT26=32'b01000000000000000000000000000000
	INPUT27=32'b01000000000000000000000000000000
	ANYINPUT=32'b01111111111111111111111111110000
	iLOADLOOP=32'b00000000000000000001100000000000
	iDECLOOP=32'b00000000000000000001100100000000
	iINCLOOP=32'b00000000000000000001101000000000
	iLOOPZ=32'b00000000000000000000000000001000
	LOOPZ=32'b00000000000000000000000000001000
	EN_USER=32'b00000000000000000000000000000000
	IWWIDTH=32'b00000000000000000000000000111010
	IRWIDTH=32'b00000000000000000000000000010000
	ICDEPTH=32'b00000000000000000000010000000000
	APB_SWIDTH=32'b00000000000000000000000000000010
	RAMWIDTH=32'b00000000000000000000000000100010
	CYCLE0=2'b00
	CYCLE1=2'b01
	CYCLE2=2'b10
	CYCLE3=2'b11
   Generated name = SF_Zi1_COREABC_0_COREABC_Z1

@N: CG364 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ramblocks.v":25:7:25:32|Synthesizing module SF_Zi1_COREABC_0_RAMBLOCKS

	DWIDTH=32'b00000000000000000000000000010000
	FAMILY=32'b00000000000000000000000000010010
   Generated name = SF_Zi1_COREABC_0_RAMBLOCKS_16s_18s

@N: CG364 :"C:\Microsemi\Libero_v10.1\Synopsys\synplify_F201203MSP1\lib\proasic\smartfusion.v":1868:7:1868:9|Synthesizing module VCC

@N: CG364 :"C:\Microsemi\Libero_v10.1\Synopsys\synplify_F201203MSP1\lib\proasic\smartfusion.v":1141:7:1141:9|Synthesizing module GND

@N: CG364 :"C:\Microsemi\Libero_v10.1\Synopsys\synplify_F201203MSP1\lib\proasic\smartfusion.v":2261:7:2261:15|Synthesizing module RAM512X18

@N: CG364 :"C:\Microsemi\Libero_v10.1\Synopsys\synplify_F201203MSP1\lib\proasic\smartfusion.v":1289:7:1289:9|Synthesizing module INV

@N: CG364 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ram256x16_smartfusion.v":25:7:25:32|Synthesizing module SF_Zi1_COREABC_0_RAM256X16

@W: CG360 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ramblocks.v":38:23:38:25|No assignment to wire RDW

@W: CG360 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ramblocks.v":42:15:42:17|No assignment to wire WDY

@W: CG360 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ramblocks.v":43:15:43:17|No assignment to wire RDY

@W: CG360 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ramblocks.v":44:15:44:18|No assignment to wire RDYY

@W: CG360 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ramblocks.v":49:15:49:18|No assignment to wire RD32

@W: CG360 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ramblocks.v":50:15:50:18|No assignment to wire WD32

@N: CG364 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\instructions.v":26:7:26:35|Synthesizing module SF_Zi1_COREABC_0_INSTRUCTIONS

	AWIDTH=32'b00000000000000000000000000001010
	DWIDTH=32'b00000000000000000000000000010000
	SWIDTH=32'b00000000000000000000000000000010
	ICWIDTH=32'b00000000000000000000000000001010
	IIWIDTH=32'b00000000000000000000000000001000
	IFWIDTH=32'b00000000000000000000000000000000
	IWWIDTH=32'b00000000000000000000000000111010
	EN_MULT=32'b00000000000000000000000000000000
	EN_INC=32'b00000000000000000000000000000001
	TESTMODE=32'b00000000000000000000000000000000
	BLANK=32'b11111111111111111111111111111111
	iNOP=32'b00000000000000000000000100000000
	iLOAD=32'b00000000000000000000001000000000
	iINCB=32'b00000000000000000000001100000000
	iAND=32'b00000000000000000000010000000000
	iOR=32'b00000000000000000000010100000000
	iXOR=32'b00000000000000000000011000000000
	iADD=32'b00000000000000000000011100000000
	iSUB=32'b00000000000000000000100000000000
	iSHL0=32'b00000000000000000000100100000000
	iSHL1=32'b00000000000000000000101000000000
	iSHLE=32'b00000000000000000000101100000000
	iROL=32'b00000000000000000000110000000000
	iSHR0=32'b00000000000000000000110100000000
	iSHR1=32'b00000000000000000000111000000000
	iSHRE=32'b00000000000000000000111100000000
	iROR=32'b00000000000000000001000000000000
	iCMP=32'b00000000000000000001000100000000
	iCMPLEQ=32'b00000000000000000001001000000000
	iBITCLR=32'b00000000000000000001001100000000
	iBITSET=32'b00000000000000000001010000000000
	iBITTST=32'b00000000000000000001010100000000
	iAPBREAD=32'b00000000000000000001011000000000
	iAPBWRT=32'b00000000000000000001011100000000
	iLOADZ=32'b00000000000000000001100000000000
	iDECZ=32'b00000000000000000001100100000000
	iINCZ=32'b00000000000000000001101000000000
	iIOWRT=32'b00000000000000000001101100000000
	iRAMREAD=32'b00000000000000000001110000000000
	iRAMWRT=32'b00000000000000000001110100000000
	iPUSH=32'b00000000000000000001111000000000
	iPOP=32'b00000000000000000001111100000000
	iIOREAD=32'b00000000000000000010000000000000
	iUSER=32'b00000000000000000010000100000000
	iJUMPB=32'b00000000000000000010001000000000
	iCALLB=32'b00000000000000000010001100000000
	iRETURNB=32'b00000000000000000010010000000000
	iRETISRB=32'b00000000000000000010010100000000
	iWAITB=32'b00000000000000000010011000000000
	iHALTB=32'b00000000000000000010011000000000
	iMULT=32'b00000000000000000010011100000000
	iDEC=32'b00000000000000000010100000000000
	iAPBREADZ=32'b00000000000000000010100100000000
	iAPBWRTZ=32'b00000000000000000010101000000000
	iADDZ=32'b00000000000000000010101100000000
	iSUBZ=32'b00000000000000000010110000000000
	iDAT=32'b00000000000000000000000000001010
	iDAT8=32'b00000000000000000000000000001011
	iDAT16=32'b00000000000000000000000000001100
	iDAT32=32'b00000000000000000000000000001101
	iACM=32'b00000000000000000000000000001110
	iACC=32'b00000000000000000000000000001111
	iRAM=32'b00000000000000000000000000010000
	DAT=32'b00000000000000000000000000001010
	DAT8=32'b00000000000000000000000000001011
	DAT16=32'b00000000000000000000000000001100
	DAT32=32'b00000000000000000000000000001101
	ACM=32'b00000000000000000000000000001110
	ACC=32'b00000000000000000000000000001111
	RAM=32'b00000000000000000000000000010000
	iIFNOT=32'b00000000000000000000000000000000
	iNOTIF=32'b00000000000000000000000000000000
	iIF=32'b00000000000000000000000000000001
	iUNTIL=32'b00000000000000000000000000000000
	iNOTUNTIL=32'b00000000000000000000000000000001
	iUNTILNOT=32'b00000000000000000000000000000001
	iWHILE=32'b00000000000000000000000000000001
	iZZERO=8'b00001000
	iNEGATIVE=8'b00000100
	iZERO=8'b00000010
	iLTE_ZERO=8'b00000110
	iALWAYS=8'b00000001
	iINPUT0=12'b000000010000
	iINPUT1=12'b000000100000
	iINPUT2=12'b000001000000
	iINPUT3=12'b000010000000
	iINPUT4=12'b000100000000
	iINPUT5=12'b001000000000
	iINPUT6=12'b010000000000
	iINPUT7=12'b100000000000
	iINPUT8=16'b0001000000000000
	iINPUT9=16'b0010000000000000
	iINPUT10=16'b0100000000000000
	iINPUT11=16'b1000000000000000
	iINPUT12=20'b00010000000000000000
	iINPUT13=20'b00100000000000000000
	iINPUT14=20'b01000000000000000000
	iINPUT15=20'b10000000000000000000
	iINPUT16=24'b000100000000000000000000
	iINPUT17=24'b001000000000000000000000
	iINPUT18=24'b010000000000000000000000
	iINPUT19=24'b100000000000000000000000
	iINPUT20=28'b0001000000000000000000000000
	iINPUT21=28'b0010000000000000000000000000
	iINPUT22=28'b0100000000000000000000000000
	iINPUT23=28'b1000000000000000000000000000
	iINPUT24=32'b00010000000000000000000000000000
	iINPUT25=32'b00100000000000000000000000000000
	iINPUT26=32'b01000000000000000000000000000000
	iINPUT27=32'b10000000000000000000000000000000
	iANYINPUT=32'b01111111111111111111111111110000
	ALWAYS=8'b00000001
	ZZERO=8'b00001000
	NEGATIVE=8'b00000100
	ZERO=8'b00000010
	LTE_ZERO=8'b00000110
	INPUT0=12'b000000010000
	INPUT1=12'b000000100000
	INPUT2=12'b000001000000
	INPUT3=12'b000010000000
	INPUT4=12'b000100000000
	INPUT5=12'b001000000000
	INPUT6=12'b010000000000
	INPUT7=12'b100000000000
	INPUT8=16'b0001000000000000
	INPUT9=16'b0010000000000000
	INPUT10=16'b0011000000000000
	INPUT11=16'b1000000000000000
	INPUT12=20'b00010000000000000000
	INPUT13=20'b00100000000000000000
	INPUT14=20'b01000000000000000000
	INPUT15=20'b10000000000000000000
	INPUT16=24'b000100000000000000000000
	INPUT17=24'b001000000000000000000000
	INPUT18=24'b001100000000000000000000
	INPUT19=24'b100000000000000000000000
	INPUT20=28'b0001000000000000000000000000
	INPUT21=28'b0010000000000000000000000000
	INPUT22=28'b0100000000000000000000000000
	INPUT23=28'b1000000000000000000000000000
	INPUT24=32'b00010000000000000000000000000000
	INPUT25=32'b00100000000000000000000000000000
	INPUT26=32'b01000000000000000000000000000000
	INPUT27=32'b01000000000000000000000000000000
	ANYINPUT=32'b01111111111111111111111111110000
	iLOADLOOP=32'b00000000000000000001100000000000
	iDECLOOP=32'b00000000000000000001100100000000
	iINCLOOP=32'b00000000000000000001101000000000
	iLOOPZ=32'b00000000000000000000000000001000
	LOOPZ=32'b00000000000000000000000000001000
	EN_USER=32'b00000000000000000000000000000000
	AW=32'b00000000000000000000000000001010
	DW=32'b00000000000000000000000000010000
	SW=32'b00000000000000000000000000000010
	IW=32'b00000000000000000000000000001010
	FW=32'b00000000000000000000000000001100
	iJUMP=32'b00000000000000000010001000000000
	iCALL=32'b00000000000000000010001100000000
	iRETURN=32'b00000000000000000010010000000000
	iRETISR=32'b00000000000000000010010100000000
	iWAIT=32'b00000000000000000010011000000000
	iHALT=32'b00000000000000000010011000000000
	iINC=32'b00000000000000000000001100000000
	iACM_CTRLSTAT=8'b00000000
	iACM_ADDR_ADDR=8'b00000100
	iACM_DATA_ADDR=8'b00001000
	iADC_CTRL2_HI_ADDR=8'b00010000
	iADC_STAT_HI_ADDR=8'b00100000
	Sym_IAP_IR=32'b00000000000000000000000000000000
	Sym_IAP_DR2=32'b00000000000000000000000000000100
	Sym_IAP_DR5=32'b00000000000000000000000000001100
	Sym_IAP_DR16=32'b00000000000000000000000000010100
	Sym_IAP_DR26=32'b00000000000000000000000000010000
	Sym_IAP_DR=32'b00000000000000000000000000011000
	Sym_IAP_DR_LENGTH=32'b00000000000000000000000000011100
	Sym_IAP_TAP_NEW_STATE=32'b00000000000000000000000000100000
	Sym_ISC_ENABLE=32'b00000000000000000000000010000000
	Sym_ISC_PROGRAM=32'b00000000000000000000000010000011
	Sym_ISC_NOOP=32'b00000000000000000000000010000100
	Sym_ISC_ERASE=32'b00000000000000000000000010000101
	Sym_ISC_INCREMENT=32'b00000000000000000000000010000111
	Sym_ISC_DATA_SHIFT=32'b00000000000000000000000010001001
	Sym_ISC_VERIFY0=32'b00000000000000000000000010001101
	Sym_ISC_VERIFY1=32'b00000000000000000000000010001110
	Sym_numberofsdtiles=32'b00000000000000000000000000000110
	Sym_numberofmaprows=32'b00000000000000000000110101110100
	Sym_usec38=32'b00000000000000000000000001111111
	Sym_usec138=32'b00000000000000000000000111001100
	Sym_usec165=32'b00000000000000000000001000100110
	Sym_usec256=32'b00000000000000000000001101010101
	Sym_usec1500=32'b00000000000000000001001110000011
	Sym_sec1p5h=32'b00000000000000000000000001001100
	Sym_sec1p5l=32'b00000000000000000011011110111000
	Sym_usec20=32'b00000000000000000000000000101100
	Sym_usec100=32'b00000000000000000000000011011110
	Sym_usec200=32'b00000000000000000000000110111100
	Sym_usec264=32'b00000000000000000000001001001010
	Label_initialize=32'b00000000000000000000000000011001
	Label_do_idly1=32'b00000000000000000000000000100010
	Label_busyok=32'b00000000000000000000000000101101
	Label_enableok=32'b00000000000000000000000000111000
	Label_do_idly2=32'b00000000000000000000000000111010
	Label_do_bulk_program=32'b00000000000000000000000000111101
	Label_bulk_prog=32'b00000000000000000000000010001000
	Label_do_bfor1=32'b00000000000000000000000010010011
	Label_do_bdly1=32'b00000000000000000000000010010111
	Label_progwaitok=32'b00000000000000000000000010100000
	Label_bulk_prog_fail=32'b00000000000000000000000010100100
	Label_do_program_rlock=32'b00000000000000000000000010101000
	Label_do_prl1=32'b00000000000000000000000010101001
	Label_do_prl2=32'b00000000000000000000000010101011
	Label_rlock_ok=32'b00000000000000000000000010111100
	Label_do_erase_disturb=32'b00000000000000000000000010111101
	Label_do_eddly1=32'b00000000000000000000000011000100
	Label_do_eddone=32'b00000000000000000000000011001010
	Label_do_enc_program_from=32'b00000000000000000000000011001100
	Label_init_aes=32'b00000000000000000000000110010101
	Label_iaes_dly=32'b00000000000000000000000110100001
	Label_epf_dly=32'b00000000000000000000000110100100
	Label_epf_dly1=32'b00000000000000000000000110100110
	Label_epf_error=32'b00000000000000000000000110101001
	Label_poll_program=32'b00000000000000000000000110101101
	Label_poll_pl1=32'b00000000000000000000000110101110
	Label_poll_pdly1=32'b00000000000000000000000110110010
	Label_poll_pdone=32'b00000000000000000000000110111100
	Label_do_exit=32'b00000000000000000000000110111101
	Label_do_exjmp=32'b00000000000000000000000111000101
	Label_do_exdly1=32'b00000000000000000000000111000110
	Label_do_exdly2=32'b00000000000000000000000111001011
	Label_do_array_verify_0_pass=32'b00000000000000000000000111001111
	Label_do_av0p_loop=32'b00000000000000000000000111010100
	Label_do_av0p_fail=32'b00000000000000000000000111011111
	Label_do_array_verify_0_fail=32'b00000000000000000000000111100011
	Label_do_av0f_loop=32'b00000000000000000000000111101000
	Label_do_av0f_fail=32'b00000000000000000000000111110011
	Label_exe_verify=32'b00000000000000000000000111110111
	Label_ev_dly=32'b00000000000000000000000111111100
	Label_readverstatus=32'b00000000000000000000001000000010
	Label_exe_verify_done=32'b00000000000000000000001000001000
   Generated name = SF_Zi1_COREABC_0_INSTRUCTIONS_Z2

@W: CG133 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":663:34:663:37|No assignment to MULT
@W: CG133 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":664:34:664:34|No assignment to A
@W: CG133 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":665:34:665:34|No assignment to B
@W: CG133 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":1295:16:1295:16|No assignment to b
@W: CG360 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":225:9:225:14|No assignment to wire DEBUG1

@W: CG360 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":226:9:226:14|No assignment to wire DEBUG2

@W: CG133 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":251:12:251:14|No assignment to iii
@W: CG133 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":252:25:252:33|No assignment to RAMDOUTXX
@W: CG134 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":256:14:256:21|No assignment to bit 10 of ins_addr
@W: CG134 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":256:14:256:21|No assignment to bit 11 of ins_addr
@W: CG134 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":256:14:256:21|No assignment to bit 12 of ins_addr
@W: CG134 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":256:14:256:21|No assignment to bit 13 of ins_addr
@W: CG134 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":256:14:256:21|No assignment to bit 14 of ins_addr
@W: CG134 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":256:14:256:21|No assignment to bit 15 of ins_addr
@W: CL169 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":998:4:998:9|Pruning register GETINST 

@W: CL169 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":485:12:485:17|Pruning register UROM.upper_addr[7:0] 

@W: CL208 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":998:4:998:9|All reachable assignments to bit 16 of ZREGISTER[16:0] assign 0, register removed by optimization.
@W: CL208 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":998:4:998:9|All reachable assignments to bit 4 of STKPTR[7:0] assign 1, register removed by optimization.
@W: CL208 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":998:4:998:9|All reachable assignments to bit 5 of STKPTR[7:0] assign 1, register removed by optimization.
@W: CL208 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":998:4:998:9|All reachable assignments to bit 6 of STKPTR[7:0] assign 1, register removed by optimization.
@W: CL208 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":998:4:998:9|All reachable assignments to bit 7 of STKPTR[7:0] assign 1, register removed by optimization.
@W: CL207 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":998:4:998:9|All reachable assignments to ISR assign 0, register removed by optimization.
@W: CL207 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":998:4:998:9|All reachable assignments to DOISR assign 0, register removed by optimization.
@W: CL207 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":785:4:785:9|All reachable assignments to ISR_ACCUM_ZERO assign 0, register removed by optimization.
@W: CL207 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":785:4:785:9|All reachable assignments to ISR_ACCUM_NEG assign 0, register removed by optimization.
@W: CL189 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":468:12:468:17|Register bit UROM.INSTR_SLOT[2] is always 0, optimizing ...
@W: CL260 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":468:12:468:17|Pruning register bit 2 of UROM.INSTR_SLOT[2:0] 

@W: CG775 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":30:7:30:14|Found Component CoreAPB3 in library COREAPB3_LIB
@N: CG364 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3_muxptob3.v":30:7:30:23|Synthesizing module COREAPB3_MUXPTOB3

@N: CG364 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":30:7:30:14|Synthesizing module CoreAPB3

	APB_DWIDTH=6'b010000
	RANGESIZE=21'b000000000010000000000
	IADDR_ENABLE=1'b0
	APBSLOT0ENABLE=1'b0
	APBSLOT1ENABLE=1'b1
	APBSLOT2ENABLE=1'b0
	APBSLOT3ENABLE=1'b0
	APBSLOT4ENABLE=1'b0
	APBSLOT5ENABLE=1'b0
	APBSLOT6ENABLE=1'b0
	APBSLOT7ENABLE=1'b0
	APBSLOT8ENABLE=1'b0
	APBSLOT9ENABLE=1'b0
	APBSLOT10ENABLE=1'b0
	APBSLOT11ENABLE=1'b0
	APBSLOT12ENABLE=1'b0
	APBSLOT13ENABLE=1'b0
	APBSLOT14ENABLE=1'b0
	APBSLOT15ENABLE=1'b0
	RANGEBITS=32'b00000000000000000000000000001010
	RANGEBITS_LT16=32'b00000000000000000000000000001010
	IADDR_31_24_8B_A=10'b0000001100
	IADDR_23_16_8B_A=10'b0000001000
	IADDR_15_8_8B_A=10'b0000000100
	IADDR_7_0_8B_A=10'b0000000000
	IADDR_31_16_16B_A=10'b0000000100
	IADDR_15_0_16B_A=10'b0000000000
	IADDR_31_0_32B_A=10'b0000000000
	SL0=16'b0000000000000000
	SL1=16'b0000000000000010
	SL2=16'b0000000000000000
	SL3=16'b0000000000000000
	SL4=16'b0000000000000000
	SL5=16'b0000000000000000
	SL6=16'b0000000000000000
	SL7=16'b0000000000000000
	SL8=16'b0000000000000000
	SL9=16'b0000000000000000
	SL10=16'b0000000000000000
	SL11=16'b0000000000000000
	SL12=16'b0000000000000000
	SL13=16'b0000000000000000
	SL14=16'b0000000000000000
	SL15=16'b0000000000000000
   Generated name = CoreAPB3_Z3

@N: CG364 :"C:\LPF_AC382_DF\A2F500\zeroization\hdl\IAP.v":29:7:29:9|Synthesizing module iap

	SPISLAVES=32'b00000000000000000000000000000001
	dwidth=32'b00000000000000000000000000010000
	JTAG_TEST_LOGIC_RESET=4'b1111
	JTAG_RUN_TEST_IDLE=4'b1100
	JTAG_SELECT_DR=4'b0111
	JTAG_CAPTURE_DR=4'b0110
	JTAG_SHIFT_DR=4'b0010
	JTAG_EXIT1_DR=4'b0001
	JTAG_PAUSE_DR=4'b0011
	JTAG_EXIT2_DR=4'b0000
	JTAG_UPDATE_DR=4'b0101
	JTAG_SELECT_IR=4'b0100
	JTAG_CAPTURE_IR=4'b1110
	JTAG_SHIFT_IR=4'b1010
	JTAG_EXIT1_IR=4'b1001
	JTAG_PAUSE_IR=4'b1011
	JTAG_EXIT2_IR=4'b1000
	JTAG_UPDATE_IR=4'b1101
	IAP_IR=6'b0000xx
	IAP_DR2=6'b0001xx
	IAP_DR3=6'b0010xx
	IAP_DR5=6'b0011xx
	IAP_DR26=6'b0100xx
	IAP_DR16=6'b0101xx
	IAP_DR=6'b0110xx
	IAP_DR_LENGTH=6'b0111xx
	IAP_TAP_NEW_STATE=6'b1000xx
	IAP_TAP_CONTROL=6'b1001xx
	IAP_SPI_SS=6'b1010xx
	IAP_SPI_TRANSFER=6'b1011xx
	IAP_SPI_DATA=6'b1100xx
	IDLE=3'b100
	MOVE=3'b001
	SCAN=3'b010
	SPI_TRANSFER=3'b011
	SPI_COMMAND=3'b000
   Generated name = iap_Z4

@A: CL282 :"C:\LPF_AC382_DF\A2F500\zeroization\hdl\IAP.v":316:0:316:5|Feedback mux created for signal tckCnt[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"C:\LPF_AC382_DF\A2F500\zeroization\hdl\IAP.v":316:0:316:5|Feedback mux created for signal targetState[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"C:\LPF_AC382_DF\A2F500\zeroization\hdl\IAP.v":316:0:316:5|Feedback mux created for signal datareg[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"C:\LPF_AC382_DF\A2F500\zeroization\hdl\IAP.v":316:0:316:5|Feedback mux created for signal MOSI -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@N: CG364 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v":23:7:23:15|Synthesizing module INBUF_MSS

@N: CG364 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v":37:7:37:16|Synthesizing module OUTBUF_MSS

@N: CG364 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v":151:7:151:13|Synthesizing module MSS_CCC

@N: CG364 :"C:\Microsemi\Libero_v10.1\Synopsys\synplify_F201203MSP1\lib\proasic\smartfusion.v":2620:7:2620:11|Synthesizing module RCOSC

@N: CG364 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":5:7:5:38|Synthesizing module SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC

@N: CG364 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\mss_tshell.v":1:7:1:13|Synthesizing module MSS_APB

@N: CG364 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\SF_Zi1_MSS.v":5:7:5:16|Synthesizing module SF_Zi1_MSS

@N: CG364 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\SF_Zi1.v":9:7:9:12|Synthesizing module SF_Zi1

@W: CL157 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":62:7:62:18|*Output RCOSC_CLKOUT has undriven bits -- simulation mismatch possible.
@W: CL157 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":63:7:63:20|*Output MAINXIN_CLKOUT has undriven bits -- simulation mismatch possible.
@W: CL157 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":64:7:64:18|*Output LPXIN_CLKOUT has undriven bits -- simulation mismatch possible.
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":36:7:36:10|Input CLKA is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":37:7:37:14|Input CLKA_PAD is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":38:7:38:15|Input CLKA_PADP is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":39:7:39:15|Input CLKA_PADN is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":40:7:40:10|Input CLKB is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":41:7:41:14|Input CLKB_PAD is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":42:7:42:15|Input CLKB_PADP is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":43:7:43:15|Input CLKB_PADN is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":44:7:44:10|Input CLKC is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":45:7:45:14|Input CLKC_PAD is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":46:7:46:15|Input CLKC_PADP is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":47:7:47:15|Input CLKC_PADN is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":48:7:48:13|Input MAINXIN is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":49:7:49:11|Input LPXIN is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v":50:7:50:13|Input MAC_CLK is unused
@N: CL201 :"C:\LPF_AC382_DF\A2F500\zeroization\hdl\IAP.v":316:0:316:5|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 5 reachable states with original encodings of:
   000
   001
   010
   011
   100
@N: CL201 :"C:\LPF_AC382_DF\A2F500\zeroization\hdl\IAP.v":305:0:305:5|Trying to extract state machine for register currentState
Extracted state machine for register currentState
State machine has 16 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
   1011
   1100
   1101
   1110
   1111
@W: CL246 :"C:\LPF_AC382_DF\A2F500\zeroization\hdl\IAP.v":71:13:71:21|Input port bits 23 to 6 of APB_PADDR[23:0] are unused

@W: CL246 :"C:\LPF_AC382_DF\A2F500\zeroization\hdl\IAP.v":71:13:71:21|Input port bits 1 to 0 of APB_PADDR[23:0] are unused

@W: CL246 :"C:\LPF_AC382_DF\A2F500\zeroization\hdl\IAP.v":77:13:77:22|Input port bits 31 to 16 of APB_PWDATA[31:0] are unused

@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\hdl\IAP.v":57:6:57:9|Input CPHA is unused
@W: CL246 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":54:18:54:22|Input port bits 23 to 14 of PADDR[23:0] are unused

@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":52:13:52:19|Input PRESETN is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":53:13:53:16|Input PCLK is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":83:18:83:25|Input PRDATAS0 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":85:18:85:25|Input PRDATAS2 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":86:18:86:25|Input PRDATAS3 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":87:18:87:25|Input PRDATAS4 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":88:18:88:25|Input PRDATAS5 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":89:18:89:25|Input PRDATAS6 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":90:18:90:25|Input PRDATAS7 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":91:18:91:25|Input PRDATAS8 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":92:18:92:25|Input PRDATAS9 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":93:18:93:26|Input PRDATAS10 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":94:18:94:26|Input PRDATAS11 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":95:18:95:26|Input PRDATAS12 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":96:18:96:26|Input PRDATAS13 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":97:18:97:26|Input PRDATAS14 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":98:18:98:26|Input PRDATAS15 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":99:13:99:20|Input PREADYS0 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":101:13:101:20|Input PREADYS2 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":102:13:102:20|Input PREADYS3 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":103:13:103:20|Input PREADYS4 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":104:13:104:20|Input PREADYS5 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":105:13:105:20|Input PREADYS6 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":106:13:106:20|Input PREADYS7 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":107:13:107:20|Input PREADYS8 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":108:13:108:20|Input PREADYS9 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":109:13:109:21|Input PREADYS10 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":110:13:110:21|Input PREADYS11 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":111:13:111:21|Input PREADYS12 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":112:13:112:21|Input PREADYS13 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":113:13:113:21|Input PREADYS14 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":114:13:114:21|Input PREADYS15 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":115:13:115:21|Input PSLVERRS0 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":117:13:117:21|Input PSLVERRS2 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":118:13:118:21|Input PSLVERRS3 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":119:13:119:21|Input PSLVERRS4 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":120:13:120:21|Input PSLVERRS5 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":121:13:121:21|Input PSLVERRS6 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":122:13:122:21|Input PSLVERRS7 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":123:13:123:21|Input PSLVERRS8 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":124:13:124:21|Input PSLVERRS9 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":125:13:125:22|Input PSLVERRS10 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":126:13:126:22|Input PSLVERRS11 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":127:13:127:22|Input PSLVERRS12 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":128:13:128:22|Input PSLVERRS13 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":129:13:129:22|Input PSLVERRS14 is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v":130:13:130:22|Input PSLVERRS15 is unused
@N: CL177 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":468:12:468:17|Sharing sequential element UROM.INSTR_MUXC.
@N: CL201 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":998:4:998:9|Trying to extract state machine for register ICYCLE
Extracted state machine for register ICYCLE
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":134:10:134:18|Input PSLVERR_M is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":138:10:138:15|Input INTREQ is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":141:10:141:19|Input INITDATVAL is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":142:10:142:17|Input INITDONE is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":143:27:143:34|Input INITADDR is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":144:15:144:22|Input INITDATA is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":148:11:148:16|Input PSEL_S is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":149:11:149:19|Input PENABLE_S is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":150:11:150:18|Input PWRITE_S is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":151:28:151:34|Input PADDR_S is unused
@W: CL159 :"C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v":152:28:152:35|Input PWDATA_S is unused
@END
Process took 0h:00m:04s realtime, 0h:00m:02s cputime
# Mon Nov 19 10:28:39 2012

###########################################################]
Premap Report

Synopsys Actel Technology Pre-mapping, Version mapact, Build 729R, Built Jun 20 2012 09:20:46
Copyright (C) 1994-2012, Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
Product Version F-2012.03M-SP1 

Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

Reading constraint file: C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\mss_tshell_syn.sdc
@L: C:\LPF_AC382_DF\A2F500\zeroization\synthesis\SF_Zi1_scck.rpt 
Printing clock  summary report in "C:\LPF_AC382_DF\A2F500\zeroization\synthesis\SF_Zi1_scck.rpt" file 
@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 
@N: MF547 |Generated clock conversion disabled 

Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)


Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)



Clock Summary
**************

Start       Requested     Requested     Clock        Clock          
Clock       Frequency     Period        Type         Group          
--------------------------------------------------------------------
System      1.0 MHz       1000.000      system       system_clkgroup
FAB_CLK     20.0 MHz      50.000        declared     clk_group_0    
FCLK        20.0 MHz      50.000        declared     clk_group_0    
====================================================================


Finished Pre Mapping Phase. (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 59MB)

@N: BN225 |Writing default property annotation file C:\LPF_AC382_DF\A2F500\zeroization\synthesis\SF_Zi1.sap.
Pre-mapping successful!

At Mapper Exit (Time elapsed 0h:00m:00s; Memory used current: 24MB peak: 59MB)

Process took 0h:00m:03s realtime, 0h:00m:01s cputime
# Mon Nov 19 10:28:45 2012

###########################################################]
Map & Optimize Report

Synopsys Actel Technology Mapper, Version mapact, Build 729R, Built Jun 20 2012 09:20:46
Copyright (C) 1994-2012, Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
Product Version F-2012.03M-SP1 

Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 
@N: MF547 |Generated clock conversion disabled 

Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)


Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)



Starting Optimization and Mapping (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB)

@W: MO111 :"c:\lpf_ac382_df\a2f500\zeroization\component\work\sf_zi1_mss\mss_ccc_0\sf_zi1_mss_tmp_mss_ccc_0_mss_ccc.v":64:7:64:18|Tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\lpf_ac382_df\a2f500\zeroization\component\work\sf_zi1_mss\mss_ccc_0\sf_zi1_mss_tmp_mss_ccc_0_mss_ccc.v":63:7:63:20|Tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\lpf_ac382_df\a2f500\zeroization\component\work\sf_zi1_mss\mss_ccc_0\sf_zi1_mss_tmp_mss_ccc_0_mss_ccc.v":62:7:62:18|Tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC) 

Available hyper_sources - for debug and ip models
	None Found


Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB)

@N: MO106 :"c:\lpf_ac382_df\a2f500\zeroization\component\work\sf_zi1\coreabc_0\rtl\vlog\core\instructions.v":148:4:148:7|Found ROM, 'UROM\.UROM.INS[57:0]', 521 words by 58 bits 
Encoding state machine ICYCLE[3:0] (netlist:statemachine)
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N: MF176 |Default generator successful 
@N: MF176 |Default generator successful 
@N: MF176 |Default generator successful 
@N: MF238 :"c:\lpf_ac382_df\a2f500\zeroization\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":985:35:985:61|Found 4-bit incrementor, 'un2_STKPTRP1[3:0]'
@N: MF238 :"c:\lpf_ac382_df\a2f500\zeroization\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":253:34:253:42|Found 10-bit incrementor, 'un1_SMADDR[9:0]'
@W: MO129 :"c:\lpf_ac382_df\a2f500\zeroization\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Sequential instance COREABC_0.UROM.INSTR_SLOT[1] reduced to a combinational gate by constant propagation
@N:"c:\lpf_ac382_df\a2f500\zeroization\hdl\iap.v":316:0:316:5|Found counter in view:work.iap_Z4(verilog) inst drLength[7:0]
Encoding state machine state[4:0] (netlist:statemachine)
original code -> new code
   000 -> 00001
   001 -> 00010
   010 -> 00100
   011 -> 01000
   100 -> 10000
Encoding state machine currentState[15:0] (netlist:statemachine)
original code -> new code
   0000 -> 0000
   0001 -> 0001
   0010 -> 0010
   0011 -> 0011
   0100 -> 0100
   0101 -> 0101
   0110 -> 0110
   0111 -> 0111
   1000 -> 1000
   1001 -> 1001
   1010 -> 1010
   1011 -> 1011
   1100 -> 1100
   1101 -> 1101
   1110 -> 1110
   1111 -> 1111

Finished factoring (Time elapsed 0h:00m:06s; Memory used current: 74MB peak: 74MB)

@N: BN362 :"c:\lpf_ac382_df\a2f500\zeroization\hdl\iap.v":316:0:316:5|Removing sequential instance iap_0.MOSI of view:PrimLib.dff(prim) in hierarchy view:work.SF_Zi1(verilog) because there are no references to its outputs 
@N: BN362 :"c:\lpf_ac382_df\a2f500\zeroization\hdl\iap.v":316:0:316:5|Removing sequential instance iap_0.SS[0] of view:PrimLib.dffs(prim) in hierarchy view:work.SF_Zi1(verilog) because there are no references to its outputs 
@N: BN362 :"c:\lpf_ac382_df\a2f500\zeroization\hdl\iap.v":316:0:316:5|Removing sequential instance iap_0.sckEn of view:PrimLib.dffr(prim) in hierarchy view:work.SF_Zi1(verilog) because there are no references to its outputs 

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:06s; Memory used current: 69MB peak: 75MB)


Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:07s; Memory used current: 65MB peak: 76MB)


Starting Early Timing Optimization (Time elapsed 0h:00m:07s; Memory used current: 66MB peak: 76MB)


Finished Early Timing Optimization (Time elapsed 0h:00m:08s; Memory used current: 67MB peak: 76MB)


Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:08s; Memory used current: 66MB peak: 76MB)


Finished preparing to map (Time elapsed 0h:00m:09s; Memory used current: 65MB peak: 76MB)


High Fanout Net Report
**********************

Driver Instance / Pin Name                 Fanout, notes                 
-------------------------------------------------------------------------
iap_0.un1_tckEn20_2_0_s / Y                32                            
COREABC_0.SMADDR[0] / Q                    69                            
COREABC_0.SMADDR[1] / Q                    76                            
COREABC_0.SMADDR[2] / Q                    56                            
COREABC_0.SMADDR[3] / Q                    46                            
COREABC_0.SMADDR[4] / Q                    50                            
COREABC_0.SMADDR[5] / Q                    55                            
COREABC_0.SMADDR[6] / Q                    44                            
COREABC_0.SMADDR[7] / Q                    45                            
COREABC_0.SMADDR[8] / Q                    46                            
COREABC_0.SMADDR[9] / Q                    52                            
COREABC_0.UROM.INSTR_SCMD[0] / Q           29                            
COREABC_0.RSTSYNC2 / Q                     96 : 84 asynchronous set/reset
COREABC_0.UROM.UROM.INS_0_o2[10] / Y       35                            
COREABC_0.UROM.UROM.INS_0_o2_1[2] / Y      30                            
COREABC_0.UROM.UROM.INS_0_o2_14[0] / Y     31                            
COREABC_0.UROM.UROM.INS_0_a2_34[0] / Y     28                            
COREABC_0.UROM.UROM.INS_0_o2[4] / Y        32                            
COREABC_0.UROM.UROM.INS_0_o2[15] / Y       36                            
COREABC_0.UROM.UROM.INS_0_o2_0[15] / Y     30                            
COREABC_0.UROM.UROM.INS_0_o2_0[4] / Y      28                            
COREABC_0.UROM.UROM.INS_i_o2[3] / Y        30                            
=========================================================================

@N: FP130 |Promoting Net TRSTB_c on CLKINT  I_494 
@N: FP130 |Promoting Net COREABC_0.SMADDR[1] on CLKINT  I_495 
@N: FP130 |Promoting Net COREABC_0.SMADDR[0] on CLKINT  I_496 
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_i_o2[3], fanout 30 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_o2_0[4], fanout 28 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_o2_0[15], fanout 30 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_o2[15], fanout 36 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_o2[4], fanout 32 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_a2_34[0], fanout 28 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_o2_14[0], fanout 31 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_o2_1[2], fanout 30 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_o2[10], fanout 35 segments 2
Replicating Sequential Instance COREABC_0.UROM.INSTR_SCMD[0], fanout 29 segments 2
Replicating Sequential Instance COREABC_0.SMADDR[9], fanout 52 segments 3
Replicating Sequential Instance COREABC_0.SMADDR[8], fanout 47 segments 2
Replicating Sequential Instance COREABC_0.SMADDR[7], fanout 46 segments 2
Replicating Sequential Instance COREABC_0.SMADDR[6], fanout 44 segments 2
Replicating Sequential Instance COREABC_0.SMADDR[5], fanout 56 segments 3
Replicating Sequential Instance COREABC_0.SMADDR[4], fanout 53 segments 3
Replicating Sequential Instance COREABC_0.SMADDR[3], fanout 49 segments 3
Replicating Sequential Instance COREABC_0.SMADDR[2], fanout 57 segments 3
Replicating Combinational Instance iap_0.un1_tckEn20_2_0_s, fanout 32 segments 2

Finished technology mapping (Time elapsed 0h:00m:11s; Memory used current: 76MB peak: 112MB)


Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:11s; Memory used current: 76MB peak: 112MB)


Added 0 Buffers
Added 24 Cells via replication
	Added 14 Sequential Cells via replication
	Added 10 Combinational Cells via replication

Finished restoring hierarchy (Time elapsed 0h:00m:11s; Memory used current: 76MB peak: 112MB)

Writing Analyst data base C:\LPF_AC382_DF\A2F500\zeroization\synthesis\SF_Zi1.srm

Finished Writing Netlist Databases (Time elapsed 0h:00m:12s; Memory used current: 74MB peak: 112MB)

Writing EDIF Netlist and constraint files
F-2012.03M-SP1 

Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:12s; Memory used current: 76MB peak: 112MB)

Found clock FAB_CLK with period 50.00ns 
Found clock FCLK with period 50.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Mon Nov 19 10:29:15 2012
#


Top view:               SF_Zi1
Library name:           smartfusion
Operating conditions:   COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree )
Requested Frequency:    20.0 MHz
Wire load mode:         top
Wire load model:        smartfusion
Paths requested:        5
Constraint File(s):    C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\mss_tshell_syn.sdc
                       
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: 4.169

                   Requested     Estimated     Requested     Estimated               Clock        Clock          
Starting Clock     Frequency     Frequency     Period        Period        Slack     Type         Group          
-----------------------------------------------------------------------------------------------------------------
FAB_CLK            20.0 MHz      24.4 MHz      50.000        41.045        4.477     declared     clk_group_0    
FCLK               20.0 MHz      NA            50.000        NA            NA        declared     clk_group_0    
System             100.0 MHz     171.5 MHz     10.000        5.831         4.169     system       system_clkgroup
=================================================================================================================





Clock Relationships
*******************

Clocks             |    rise  to  rise    |    fall  to  fall    |    rise  to  fall    |    fall  to  rise 
------------------------------------------------------------------------------------------------------------
Starting  Ending   |  constraint  slack   |  constraint  slack   |  constraint  slack   |  constraint  slack
------------------------------------------------------------------------------------------------------------
System    System   |  10.000      4.169   |  No paths    -       |  No paths    -       |  No paths    -    
FAB_CLK   FAB_CLK  |  50.000      14.315  |  50.000      46.712  |  25.000      12.421  |  25.000      4.477
============================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: FAB_CLK
====================================



Starting Points with Worst Slack
********************************

                                 Starting                                               Arrival           
Instance                         Reference     Type         Pin     Net                 Time        Slack 
                                 Clock                                                                    
----------------------------------------------------------------------------------------------------------
iap_0.TMS                        FAB_CLK       DFN0E0P0     Q       TMS_c               0.653       4.477 
iap_0.currentState[2]            FAB_CLK       DFN1P0       Q       currentState[2]     0.737       12.421
iap_0.currentState[1]            FAB_CLK       DFN1P0       Q       currentState[1]     0.737       12.541
iap_0.currentState[0]            FAB_CLK       DFN1P0       Q       currentState[0]     0.737       13.438
iap_0.currentState[3]            FAB_CLK       DFN1P0       Q       currentState[3]     0.737       13.546
iap_0.targetState[0]             FAB_CLK       DFN1E0       Q       targetState[0]      0.737       14.241
COREABC_0.UROM\.INSTR_CMD[1]     FAB_CLK       DFN1         Q       INSTR_CMD[1]        0.737       14.315
iap_0.targetState[3]             FAB_CLK       DFN1E0       Q       targetState[3]      0.737       14.317
iap_0.targetState[1]             FAB_CLK       DFN1E0       Q       targetState[1]      0.737       14.757
iap_0.targetState[2]             FAB_CLK       DFN1E0       Q       targetState[2]      0.737       15.143
==========================================================================================================


Ending Points with Worst Slack
******************************

                             Starting                                            Required           
Instance                     Reference     Type         Pin     Net              Time         Slack 
                             Clock                                                                  
----------------------------------------------------------------------------------------------------
iap_0.tckCnt[7]              FAB_CLK       DFN1         D       tckCnt_15[7]     24.461       4.477 
iap_0.tckCnt[6]              FAB_CLK       DFN1         D       tckCnt_15[6]     24.461       5.365 
iap_0.tckCnt[5]              FAB_CLK       DFN1         D       tckCnt_15[5]     24.461       5.430 
iap_0.tckCnt[4]              FAB_CLK       DFN1         D       tckCnt_15[4]     24.461       6.290 
iap_0.tckCnt[3]              FAB_CLK       DFN1         D       tckCnt_15[3]     24.461       6.775 
iap_0.tckCnt[2]              FAB_CLK       DFN1         D       tckCnt_15[2]     24.461       7.663 
iap_0.tckCnt[1]              FAB_CLK       DFN1         D       tckCnt_15[1]     24.461       9.557 
iap_0.tckCnt[0]              FAB_CLK       DFN1         D       tckCnt_15[0]     24.427       9.711 
iap_0.TMS                    FAB_CLK       DFN0E0P0     D       N_4              24.288       12.421
COREABC_0.STD_ACCUM_ZERO     FAB_CLK       DFN1E1C0     D       tmp_4[0]         49.496       14.315
====================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      25.000
    - Setup time:                            0.539
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         24.461

    - Propagation time:                      19.984
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 4.477

    Number of logic level(s):                15
    Starting point:                          iap_0.TMS / Q
    Ending point:                            iap_0.tckCnt[7] / D
    The start point is clocked by            FAB_CLK [falling] on pin CLK
    The end   point is clocked by            FAB_CLK [rising] on pin CLK

Instance / Net                                  Pin      Pin               Arrival     No. of    
Name                               Type         Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------
iap_0.TMS                          DFN0E0P0     Q        Out     0.653     0.653       -         
TMS_c                              Net          -        -       1.526     -           7         
iap_0.TMS_RNI83K11                 NOR2A        A        In      -         2.179       -         
iap_0.TMS_RNI83K11                 NOR2A        Y        Out     0.627     2.807       -         
N_721                              Net          -        -       0.322     -           1         
iap_0.TMS_RNI1B9G2                 OR2          B        In      -         3.128       -         
iap_0.TMS_RNI1B9G2                 OR2          Y        Out     0.646     3.775       -         
nextState_1_0_0_0[1]               Net          -        -       0.322     -           1         
iap_0.TMS_RNIJ0265                 OR2          B        In      -         4.096       -         
iap_0.TMS_RNIJ0265                 OR2          Y        Out     0.646     4.743       -         
currentState_ns[1]                 Net          -        -       0.386     -           2         
iap_0.targetState_RNI187D5[1]      XOR2         A        In      -         5.129       -         
iap_0.targetState_RNI187D5[1]      XOR2         Y        Out     0.488     5.617       -         
tckEn14_1                          Net          -        -       0.322     -           1         
iap_0.targetState_RNI2RMH8[0]      XO1          C        In      -         5.938       -         
iap_0.targetState_RNI2RMH8[0]      XO1          Y        Out     0.344     6.282       -         
tckEn14_NE_1                       Net          -        -       0.806     -           3         
iap_0.state_RNICOS0E_0[1]          OA1          B        In      -         7.089       -         
iap_0.state_RNICOS0E_0[1]          OA1          Y        Out     0.902     7.991       -         
N_188                              Net          -        -       0.386     -           2         
iap_0.state_RNIVRTCP_0[1]          NOR3         C        In      -         8.377       -         
iap_0.state_RNIVRTCP_0[1]          NOR3         Y        Out     0.683     9.060       -         
state_RNIVRTCP_0[1]                Net          -        -       2.172     -           16        
iap_0.un1_tckCnt.I_12              XOR2         B        In      -         11.232      -         
iap_0.un1_tckCnt.I_12              XOR2         Y        Out     0.937     12.169      -         
DWACT_ADD_CI_0_pog_array_0[0]      Net          -        -       0.322     -           1         
iap_0.un1_tckCnt.I_35              AO1          A        In      -         12.490      -         
iap_0.un1_tckCnt.I_35              AO1          Y        Out     0.520     13.010      -         
DWACT_ADD_CI_0_g_array_1[0]        Net          -        -       0.806     -           3         
iap_0.un1_tckCnt.I_36              AO1          B        In      -         13.816      -         
iap_0.un1_tckCnt.I_36              AO1          Y        Out     0.567     14.383      -         
DWACT_ADD_CI_0_g_array_2[0]        Net          -        -       0.806     -           3         
iap_0.un1_tckCnt.I_39              AO1          B        In      -         15.189      -         
iap_0.un1_tckCnt.I_39              AO1          Y        Out     0.567     15.756      -         
DWACT_ADD_CI_0_g_array_11[0]       Net          -        -       0.386     -           2         
iap_0.un1_tckCnt.I_45              AO1          B        In      -         16.142      -         
iap_0.un1_tckCnt.I_45              AO1          Y        Out     0.567     16.708      -         
DWACT_ADD_CI_0_g_array_12_2[0]     Net          -        -       0.322     -           1         
iap_0.un1_tckCnt.I_34              XOR2         B        In      -         17.030      -         
iap_0.un1_tckCnt.I_34              XOR2         Y        Out     0.937     17.966      -         
I_34                               Net          -        -       0.322     -           1         
iap_0.tckCnt_RNO_0[7]              OA1A         C        In      -         18.288      -         
iap_0.tckCnt_RNO_0[7]              OA1A         Y        Out     0.398     18.686      -         
N_78                               Net          -        -       0.322     -           1         
iap_0.tckCnt_RNO[7]                AO1          C        In      -         19.007      -         
iap_0.tckCnt_RNO[7]                AO1          Y        Out     0.655     19.663      -         
tckCnt_15[7]                       Net          -        -       0.322     -           1         
iap_0.tckCnt[7]                    DFN1         D        In      -         19.984      -         
=================================================================================================
Total path delay (propagation time + setup) of 20.523 is 10.676(52.0%) logic and 9.847(48.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                   Starting                                                       Arrival          
Instance                           Reference     Type        Pin        Net                       Time        Slack
                                   Clock                                                                           
-------------------------------------------------------------------------------------------------------------------
SF_Zi1_MSS_0.MSS_CCC_0.I_RCOSC     System        RCOSC       CLKOUT     N_CLKA_RCOSC              0.000       4.169
SF_Zi1_MSS_0.MSS_ADLIB_INST        System        MSS_APB     EMCCLK     MSS_ADLIB_INST_EMCCLK     0.000       9.678
===================================================================================================================


Ending Points with Worst Slack
******************************

                                Starting                                                           Required          
Instance                        Reference     Type        Pin           Net                        Time         Slack
                                Clock                                                                                
---------------------------------------------------------------------------------------------------------------------
SF_Zi1_MSS_0.MSS_ADLIB_INST     System        MSS_APB     PLLLOCK       MSS_ADLIB_INST_PLLLOCK     10.000       4.169
SF_Zi1_MSS_0.MSS_ADLIB_INST     System        MSS_APB     EMCCLKRTN     MSS_ADLIB_INST_EMCCLK      10.000       9.678
=====================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         10.000

    - Propagation time:                      5.831
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (critical) :                     4.169

    Number of logic level(s):                1
    Starting point:                          SF_Zi1_MSS_0.MSS_CCC_0.I_RCOSC / CLKOUT
    Ending point:                            SF_Zi1_MSS_0.MSS_ADLIB_INST / PLLLOCK
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                  Pin         Pin               Arrival     No. of    
Name                                Type        Name        Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------
SF_Zi1_MSS_0.MSS_CCC_0.I_RCOSC      RCOSC       CLKOUT      Out     0.000     0.000       -         
N_CLKA_RCOSC                        Net         -           -       0.322     -           1         
SF_Zi1_MSS_0.MSS_CCC_0.I_MSSCCC     MSS_CCC     CLKA        In      -         0.322       -         
SF_Zi1_MSS_0.MSS_CCC_0.I_MSSCCC     MSS_CCC     LOCKMSS     Out     5.188     5.509       -         
MSS_ADLIB_INST_PLLLOCK              Net         -           -       0.322     -           1         
SF_Zi1_MSS_0.MSS_ADLIB_INST         MSS_APB     PLLLOCK     In      -         5.831       -         
====================================================================================================
Total path delay (propagation time + setup) of 5.831 is 5.188(89.0%) logic and 0.643(11.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Target Part: A2F500M3G_FBGA484_STD
Report for cell SF_Zi1.verilog
  Core Cell usage:
              cell count     area count*area
              AND2    34      1.0       34.0
              AND3     9      1.0        9.0
               AO1   227      1.0      227.0
              AO1A    34      1.0       34.0
              AO1B     1      1.0        1.0
              AO1C     3      1.0        3.0
              AO1D     4      1.0        4.0
              AOI1     3      1.0        3.0
             AOI1B     5      1.0        5.0
              AOI5     1      1.0        1.0
              AX1A     1      1.0        1.0
              AX1C     3      1.0        3.0
              AX1D     4      1.0        4.0
            CLKINT     3      0.0        0.0
               GND     9      0.0        0.0
               INV     2      1.0        2.0
              MAJ3    29      1.0       29.0
             MAJ3X     1      1.0        1.0
             MIN3X     1      1.0        1.0
           MSS_APB     1      0.0        0.0
           MSS_CCC     1      0.0        0.0
               MX2    86      1.0       86.0
              MX2A    13      1.0       13.0
              MX2C     2      1.0        2.0
              NOR2    94      1.0       94.0
             NOR2A   277      1.0      277.0
             NOR2B   473      1.0      473.0
              NOR3    10      1.0       10.0
             NOR3A    79      1.0       79.0
             NOR3B   120      1.0      120.0
             NOR3C   120      1.0      120.0
               OA1    58      1.0       58.0
              OA1A    21      1.0       21.0
              OA1B    15      1.0       15.0
              OA1C    11      1.0       11.0
              OAI1     3      1.0        3.0
               OR2   174      1.0      174.0
              OR2A    41      1.0       41.0
              OR2B    19      1.0       19.0
               OR3   306      1.0      306.0
              OR3A     5      1.0        5.0
              OR3B     1      1.0        1.0
             RCOSC     1      0.0        0.0
               VCC     9      0.0        0.0
               XA1    24      1.0       24.0
              XA1A     2      1.0        2.0
              XA1B     2      1.0        2.0
             XAI1A     1      1.0        1.0
             XNOR2    13      1.0       13.0
             XNOR3     1      1.0        1.0
               XO1     3      1.0        3.0
              XOR2    63      1.0       63.0
              XOR3    21      1.0       21.0
              ZOR3     1      1.0        1.0


          DFN0E0P0     1      1.0        1.0
          DFN0E1P0     1      1.0        1.0
              DFN1    42      1.0       42.0
            DFN1C0    12      1.0       12.0
            DFN1E0     4      1.0        4.0
          DFN1E0C0    17      1.0       17.0
            DFN1E1    16      1.0       16.0
          DFN1E1C0    34      1.0       34.0
            DFN1P0    34      1.0       34.0
         RAM512X18     1      0.0        0.0
                   -----          ----------
             TOTAL  2607              2582.0


  IO Cell usage:
              cell count
             INBUF     2
         INBUF_MSS     2
            OUTBUF     8
        OUTBUF_MSS     1
                   -----
             TOTAL    13


Core Cells         : 2582 of 11520 (22%)
IO Cells           : 13

  RAM/ROM Usage Summary
Block Rams : 1 of 24 (4%)

Mapper successful!

At Mapper Exit (Time elapsed 0h:00m:13s; Memory used current: 27MB peak: 112MB)

Process took 0h:00m:30s realtime, 0h:00m:13s cputime
# Mon Nov 19 10:29:16 2012

###########################################################]
