Synopsys Actel Technology Mapper, Version mapact, Build 729R, Built Jun 20 2012 09:20:46
Copyright (C) 1994-2012, Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
Product Version F-2012.03M-SP1 

Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 
@N: MF547 |Generated clock conversion disabled 

Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)


Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)



Starting Optimization and Mapping (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB)

@W: MO111 :"c:\lpf_ac382_df\a2f500\zeroization\component\work\sf_zi1_mss\mss_ccc_0\sf_zi1_mss_tmp_mss_ccc_0_mss_ccc.v":64:7:64:18|Tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\lpf_ac382_df\a2f500\zeroization\component\work\sf_zi1_mss\mss_ccc_0\sf_zi1_mss_tmp_mss_ccc_0_mss_ccc.v":63:7:63:20|Tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\lpf_ac382_df\a2f500\zeroization\component\work\sf_zi1_mss\mss_ccc_0\sf_zi1_mss_tmp_mss_ccc_0_mss_ccc.v":62:7:62:18|Tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC) 

Available hyper_sources - for debug and ip models
	None Found


Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB)

@N: MO106 :"c:\lpf_ac382_df\a2f500\zeroization\component\work\sf_zi1\coreabc_0\rtl\vlog\core\instructions.v":148:4:148:7|Found ROM, 'UROM\.UROM.INS[57:0]', 521 words by 58 bits 
Encoding state machine ICYCLE[3:0] (netlist:statemachine)
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N: MF176 |Default generator successful 
@N: MF176 |Default generator successful 
@N: MF176 |Default generator successful 
@N: MF238 :"c:\lpf_ac382_df\a2f500\zeroization\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":985:35:985:61|Found 4-bit incrementor, 'un2_STKPTRP1[3:0]'
@N: MF238 :"c:\lpf_ac382_df\a2f500\zeroization\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":253:34:253:42|Found 10-bit incrementor, 'un1_SMADDR[9:0]'
@W: MO129 :"c:\lpf_ac382_df\a2f500\zeroization\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Sequential instance COREABC_0.UROM.INSTR_SLOT[1] reduced to a combinational gate by constant propagation
@N:"c:\lpf_ac382_df\a2f500\zeroization\hdl\iap.v":316:0:316:5|Found counter in view:work.iap_Z4(verilog) inst drLength[7:0]
Encoding state machine state[4:0] (netlist:statemachine)
original code -> new code
   000 -> 00001
   001 -> 00010
   010 -> 00100
   011 -> 01000
   100 -> 10000
Encoding state machine currentState[15:0] (netlist:statemachine)
original code -> new code
   0000 -> 0000
   0001 -> 0001
   0010 -> 0010
   0011 -> 0011
   0100 -> 0100
   0101 -> 0101
   0110 -> 0110
   0111 -> 0111
   1000 -> 1000
   1001 -> 1001
   1010 -> 1010
   1011 -> 1011
   1100 -> 1100
   1101 -> 1101
   1110 -> 1110
   1111 -> 1111

Finished factoring (Time elapsed 0h:00m:06s; Memory used current: 74MB peak: 74MB)

@N: BN362 :"c:\lpf_ac382_df\a2f500\zeroization\hdl\iap.v":316:0:316:5|Removing sequential instance iap_0.MOSI of view:PrimLib.dff(prim) in hierarchy view:work.SF_Zi1(verilog) because there are no references to its outputs 
@N: BN362 :"c:\lpf_ac382_df\a2f500\zeroization\hdl\iap.v":316:0:316:5|Removing sequential instance iap_0.SS[0] of view:PrimLib.dffs(prim) in hierarchy view:work.SF_Zi1(verilog) because there are no references to its outputs 
@N: BN362 :"c:\lpf_ac382_df\a2f500\zeroization\hdl\iap.v":316:0:316:5|Removing sequential instance iap_0.sckEn of view:PrimLib.dffr(prim) in hierarchy view:work.SF_Zi1(verilog) because there are no references to its outputs 

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:06s; Memory used current: 69MB peak: 75MB)


Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:07s; Memory used current: 65MB peak: 76MB)


Starting Early Timing Optimization (Time elapsed 0h:00m:07s; Memory used current: 66MB peak: 76MB)


Finished Early Timing Optimization (Time elapsed 0h:00m:08s; Memory used current: 67MB peak: 76MB)


Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:08s; Memory used current: 66MB peak: 76MB)


Finished preparing to map (Time elapsed 0h:00m:09s; Memory used current: 65MB peak: 76MB)


High Fanout Net Report
**********************

Driver Instance / Pin Name                 Fanout, notes                 
-------------------------------------------------------------------------
iap_0.un1_tckEn20_2_0_s / Y                32                            
COREABC_0.SMADDR[0] / Q                    69                            
COREABC_0.SMADDR[1] / Q                    76                            
COREABC_0.SMADDR[2] / Q                    56                            
COREABC_0.SMADDR[3] / Q                    46                            
COREABC_0.SMADDR[4] / Q                    50                            
COREABC_0.SMADDR[5] / Q                    55                            
COREABC_0.SMADDR[6] / Q                    44                            
COREABC_0.SMADDR[7] / Q                    45                            
COREABC_0.SMADDR[8] / Q                    46                            
COREABC_0.SMADDR[9] / Q                    52                            
COREABC_0.UROM.INSTR_SCMD[0] / Q           29                            
COREABC_0.RSTSYNC2 / Q                     96 : 84 asynchronous set/reset
COREABC_0.UROM.UROM.INS_0_o2[10] / Y       35                            
COREABC_0.UROM.UROM.INS_0_o2_1[2] / Y      30                            
COREABC_0.UROM.UROM.INS_0_o2_14[0] / Y     31                            
COREABC_0.UROM.UROM.INS_0_a2_34[0] / Y     28                            
COREABC_0.UROM.UROM.INS_0_o2[4] / Y        32                            
COREABC_0.UROM.UROM.INS_0_o2[15] / Y       36                            
COREABC_0.UROM.UROM.INS_0_o2_0[15] / Y     30                            
COREABC_0.UROM.UROM.INS_0_o2_0[4] / Y      28                            
COREABC_0.UROM.UROM.INS_i_o2[3] / Y        30                            
=========================================================================

@N: FP130 |Promoting Net TRSTB_c on CLKINT  I_494 
@N: FP130 |Promoting Net COREABC_0.SMADDR[1] on CLKINT  I_495 
@N: FP130 |Promoting Net COREABC_0.SMADDR[0] on CLKINT  I_496 
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_i_o2[3], fanout 30 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_o2_0[4], fanout 28 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_o2_0[15], fanout 30 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_o2[15], fanout 36 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_o2[4], fanout 32 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_a2_34[0], fanout 28 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_o2_14[0], fanout 31 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_o2_1[2], fanout 30 segments 2
Replicating Combinational Instance COREABC_0.UROM.UROM.INS_0_o2[10], fanout 35 segments 2
Replicating Sequential Instance COREABC_0.UROM.INSTR_SCMD[0], fanout 29 segments 2
Replicating Sequential Instance COREABC_0.SMADDR[9], fanout 52 segments 3
Replicating Sequential Instance COREABC_0.SMADDR[8], fanout 47 segments 2
Replicating Sequential Instance COREABC_0.SMADDR[7], fanout 46 segments 2
Replicating Sequential Instance COREABC_0.SMADDR[6], fanout 44 segments 2
Replicating Sequential Instance COREABC_0.SMADDR[5], fanout 56 segments 3
Replicating Sequential Instance COREABC_0.SMADDR[4], fanout 53 segments 3
Replicating Sequential Instance COREABC_0.SMADDR[3], fanout 49 segments 3
Replicating Sequential Instance COREABC_0.SMADDR[2], fanout 57 segments 3
Replicating Combinational Instance iap_0.un1_tckEn20_2_0_s, fanout 32 segments 2

Finished technology mapping (Time elapsed 0h:00m:11s; Memory used current: 76MB peak: 112MB)


Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:11s; Memory used current: 76MB peak: 112MB)


Added 0 Buffers
Added 24 Cells via replication
	Added 14 Sequential Cells via replication
	Added 10 Combinational Cells via replication

Finished restoring hierarchy (Time elapsed 0h:00m:11s; Memory used current: 76MB peak: 112MB)

Writing Analyst data base C:\LPF_AC382_DF\A2F500\zeroization\synthesis\SF_Zi1.srm

Finished Writing Netlist Databases (Time elapsed 0h:00m:12s; Memory used current: 74MB peak: 112MB)

Writing EDIF Netlist and constraint files
F-2012.03M-SP1 

Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:12s; Memory used current: 76MB peak: 112MB)

Found clock FAB_CLK with period 50.00ns 
Found clock FCLK with period 50.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Mon Nov 19 10:29:15 2012
#


Top view:               SF_Zi1
Library name:           smartfusion
Operating conditions:   COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree )
Requested Frequency:    20.0 MHz
Wire load mode:         top
Wire load model:        smartfusion
Paths requested:        5
Constraint File(s):    C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\mss_tshell_syn.sdc
                       
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: 4.169

                   Requested     Estimated     Requested     Estimated               Clock        Clock          
Starting Clock     Frequency     Frequency     Period        Period        Slack     Type         Group          
-----------------------------------------------------------------------------------------------------------------
FAB_CLK            20.0 MHz      24.4 MHz      50.000        41.045        4.477     declared     clk_group_0    
FCLK               20.0 MHz      NA            50.000        NA            NA        declared     clk_group_0    
System             100.0 MHz     171.5 MHz     10.000        5.831         4.169     system       system_clkgroup
=================================================================================================================





Clock Relationships
*******************

Clocks             |    rise  to  rise    |    fall  to  fall    |    rise  to  fall    |    fall  to  rise 
------------------------------------------------------------------------------------------------------------
Starting  Ending   |  constraint  slack   |  constraint  slack   |  constraint  slack   |  constraint  slack
------------------------------------------------------------------------------------------------------------
System    System   |  10.000      4.169   |  No paths    -       |  No paths    -       |  No paths    -    
FAB_CLK   FAB_CLK  |  50.000      14.315  |  50.000      46.712  |  25.000      12.421  |  25.000      4.477
============================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: FAB_CLK
====================================



Starting Points with Worst Slack
********************************

                                 Starting                                               Arrival           
Instance                         Reference     Type         Pin     Net                 Time        Slack 
                                 Clock                                                                    
----------------------------------------------------------------------------------------------------------
iap_0.TMS                        FAB_CLK       DFN0E0P0     Q       TMS_c               0.653       4.477 
iap_0.currentState[2]            FAB_CLK       DFN1P0       Q       currentState[2]     0.737       12.421
iap_0.currentState[1]            FAB_CLK       DFN1P0       Q       currentState[1]     0.737       12.541
iap_0.currentState[0]            FAB_CLK       DFN1P0       Q       currentState[0]     0.737       13.438
iap_0.currentState[3]            FAB_CLK       DFN1P0       Q       currentState[3]     0.737       13.546
iap_0.targetState[0]             FAB_CLK       DFN1E0       Q       targetState[0]      0.737       14.241
COREABC_0.UROM\.INSTR_CMD[1]     FAB_CLK       DFN1         Q       INSTR_CMD[1]        0.737       14.315
iap_0.targetState[3]             FAB_CLK       DFN1E0       Q       targetState[3]      0.737       14.317
iap_0.targetState[1]             FAB_CLK       DFN1E0       Q       targetState[1]      0.737       14.757
iap_0.targetState[2]             FAB_CLK       DFN1E0       Q       targetState[2]      0.737       15.143
==========================================================================================================


Ending Points with Worst Slack
******************************

                             Starting                                            Required           
Instance                     Reference     Type         Pin     Net              Time         Slack 
                             Clock                                                                  
----------------------------------------------------------------------------------------------------
iap_0.tckCnt[7]              FAB_CLK       DFN1         D       tckCnt_15[7]     24.461       4.477 
iap_0.tckCnt[6]              FAB_CLK       DFN1         D       tckCnt_15[6]     24.461       5.365 
iap_0.tckCnt[5]              FAB_CLK       DFN1         D       tckCnt_15[5]     24.461       5.430 
iap_0.tckCnt[4]              FAB_CLK       DFN1         D       tckCnt_15[4]     24.461       6.290 
iap_0.tckCnt[3]              FAB_CLK       DFN1         D       tckCnt_15[3]     24.461       6.775 
iap_0.tckCnt[2]              FAB_CLK       DFN1         D       tckCnt_15[2]     24.461       7.663 
iap_0.tckCnt[1]              FAB_CLK       DFN1         D       tckCnt_15[1]     24.461       9.557 
iap_0.tckCnt[0]              FAB_CLK       DFN1         D       tckCnt_15[0]     24.427       9.711 
iap_0.TMS                    FAB_CLK       DFN0E0P0     D       N_4              24.288       12.421
COREABC_0.STD_ACCUM_ZERO     FAB_CLK       DFN1E1C0     D       tmp_4[0]         49.496       14.315
====================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      25.000
    - Setup time:                            0.539
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         24.461

    - Propagation time:                      19.984
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 4.477

    Number of logic level(s):                15
    Starting point:                          iap_0.TMS / Q
    Ending point:                            iap_0.tckCnt[7] / D
    The start point is clocked by            FAB_CLK [falling] on pin CLK
    The end   point is clocked by            FAB_CLK [rising] on pin CLK

Instance / Net                                  Pin      Pin               Arrival     No. of    
Name                               Type         Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------
iap_0.TMS                          DFN0E0P0     Q        Out     0.653     0.653       -         
TMS_c                              Net          -        -       1.526     -           7         
iap_0.TMS_RNI83K11                 NOR2A        A        In      -         2.179       -         
iap_0.TMS_RNI83K11                 NOR2A        Y        Out     0.627     2.807       -         
N_721                              Net          -        -       0.322     -           1         
iap_0.TMS_RNI1B9G2                 OR2          B        In      -         3.128       -         
iap_0.TMS_RNI1B9G2                 OR2          Y        Out     0.646     3.775       -         
nextState_1_0_0_0[1]               Net          -        -       0.322     -           1         
iap_0.TMS_RNIJ0265                 OR2          B        In      -         4.096       -         
iap_0.TMS_RNIJ0265                 OR2          Y        Out     0.646     4.743       -         
currentState_ns[1]                 Net          -        -       0.386     -           2         
iap_0.targetState_RNI187D5[1]      XOR2         A        In      -         5.129       -         
iap_0.targetState_RNI187D5[1]      XOR2         Y        Out     0.488     5.617       -         
tckEn14_1                          Net          -        -       0.322     -           1         
iap_0.targetState_RNI2RMH8[0]      XO1          C        In      -         5.938       -         
iap_0.targetState_RNI2RMH8[0]      XO1          Y        Out     0.344     6.282       -         
tckEn14_NE_1                       Net          -        -       0.806     -           3         
iap_0.state_RNICOS0E_0[1]          OA1          B        In      -         7.089       -         
iap_0.state_RNICOS0E_0[1]          OA1          Y        Out     0.902     7.991       -         
N_188                              Net          -        -       0.386     -           2         
iap_0.state_RNIVRTCP_0[1]          NOR3         C        In      -         8.377       -         
iap_0.state_RNIVRTCP_0[1]          NOR3         Y        Out     0.683     9.060       -         
state_RNIVRTCP_0[1]                Net          -        -       2.172     -           16        
iap_0.un1_tckCnt.I_12              XOR2         B        In      -         11.232      -         
iap_0.un1_tckCnt.I_12              XOR2         Y        Out     0.937     12.169      -         
DWACT_ADD_CI_0_pog_array_0[0]      Net          -        -       0.322     -           1         
iap_0.un1_tckCnt.I_35              AO1          A        In      -         12.490      -         
iap_0.un1_tckCnt.I_35              AO1          Y        Out     0.520     13.010      -         
DWACT_ADD_CI_0_g_array_1[0]        Net          -        -       0.806     -           3         
iap_0.un1_tckCnt.I_36              AO1          B        In      -         13.816      -         
iap_0.un1_tckCnt.I_36              AO1          Y        Out     0.567     14.383      -         
DWACT_ADD_CI_0_g_array_2[0]        Net          -        -       0.806     -           3         
iap_0.un1_tckCnt.I_39              AO1          B        In      -         15.189      -         
iap_0.un1_tckCnt.I_39              AO1          Y        Out     0.567     15.756      -         
DWACT_ADD_CI_0_g_array_11[0]       Net          -        -       0.386     -           2         
iap_0.un1_tckCnt.I_45              AO1          B        In      -         16.142      -         
iap_0.un1_tckCnt.I_45              AO1          Y        Out     0.567     16.708      -         
DWACT_ADD_CI_0_g_array_12_2[0]     Net          -        -       0.322     -           1         
iap_0.un1_tckCnt.I_34              XOR2         B        In      -         17.030      -         
iap_0.un1_tckCnt.I_34              XOR2         Y        Out     0.937     17.966      -         
I_34                               Net          -        -       0.322     -           1         
iap_0.tckCnt_RNO_0[7]              OA1A         C        In      -         18.288      -         
iap_0.tckCnt_RNO_0[7]              OA1A         Y        Out     0.398     18.686      -         
N_78                               Net          -        -       0.322     -           1         
iap_0.tckCnt_RNO[7]                AO1          C        In      -         19.007      -         
iap_0.tckCnt_RNO[7]                AO1          Y        Out     0.655     19.663      -         
tckCnt_15[7]                       Net          -        -       0.322     -           1         
iap_0.tckCnt[7]                    DFN1         D        In      -         19.984      -         
=================================================================================================
Total path delay (propagation time + setup) of 20.523 is 10.676(52.0%) logic and 9.847(48.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                   Starting                                                       Arrival          
Instance                           Reference     Type        Pin        Net                       Time        Slack
                                   Clock                                                                           
-------------------------------------------------------------------------------------------------------------------
SF_Zi1_MSS_0.MSS_CCC_0.I_RCOSC     System        RCOSC       CLKOUT     N_CLKA_RCOSC              0.000       4.169
SF_Zi1_MSS_0.MSS_ADLIB_INST        System        MSS_APB     EMCCLK     MSS_ADLIB_INST_EMCCLK     0.000       9.678
===================================================================================================================


Ending Points with Worst Slack
******************************

                                Starting                                                           Required          
Instance                        Reference     Type        Pin           Net                        Time         Slack
                                Clock                                                                                
---------------------------------------------------------------------------------------------------------------------
SF_Zi1_MSS_0.MSS_ADLIB_INST     System        MSS_APB     PLLLOCK       MSS_ADLIB_INST_PLLLOCK     10.000       4.169
SF_Zi1_MSS_0.MSS_ADLIB_INST     System        MSS_APB     EMCCLKRTN     MSS_ADLIB_INST_EMCCLK      10.000       9.678
=====================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         10.000

    - Propagation time:                      5.831
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (critical) :                     4.169

    Number of logic level(s):                1
    Starting point:                          SF_Zi1_MSS_0.MSS_CCC_0.I_RCOSC / CLKOUT
    Ending point:                            SF_Zi1_MSS_0.MSS_ADLIB_INST / PLLLOCK
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                  Pin         Pin               Arrival     No. of    
Name                                Type        Name        Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------
SF_Zi1_MSS_0.MSS_CCC_0.I_RCOSC      RCOSC       CLKOUT      Out     0.000     0.000       -         
N_CLKA_RCOSC                        Net         -           -       0.322     -           1         
SF_Zi1_MSS_0.MSS_CCC_0.I_MSSCCC     MSS_CCC     CLKA        In      -         0.322       -         
SF_Zi1_MSS_0.MSS_CCC_0.I_MSSCCC     MSS_CCC     LOCKMSS     Out     5.188     5.509       -         
MSS_ADLIB_INST_PLLLOCK              Net         -           -       0.322     -           1         
SF_Zi1_MSS_0.MSS_ADLIB_INST         MSS_APB     PLLLOCK     In      -         5.831       -         
====================================================================================================
Total path delay (propagation time + setup) of 5.831 is 5.188(89.0%) logic and 0.643(11.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Target Part: A2F500M3G_FBGA484_STD
Report for cell SF_Zi1.verilog
  Core Cell usage:
              cell count     area count*area
              AND2    34      1.0       34.0
              AND3     9      1.0        9.0
               AO1   227      1.0      227.0
              AO1A    34      1.0       34.0
              AO1B     1      1.0        1.0
              AO1C     3      1.0        3.0
              AO1D     4      1.0        4.0
              AOI1     3      1.0        3.0
             AOI1B     5      1.0        5.0
              AOI5     1      1.0        1.0
              AX1A     1      1.0        1.0
              AX1C     3      1.0        3.0
              AX1D     4      1.0        4.0
            CLKINT     3      0.0        0.0
               GND     9      0.0        0.0
               INV     2      1.0        2.0
              MAJ3    29      1.0       29.0
             MAJ3X     1      1.0        1.0
             MIN3X     1      1.0        1.0
           MSS_APB     1      0.0        0.0
           MSS_CCC     1      0.0        0.0
               MX2    86      1.0       86.0
              MX2A    13      1.0       13.0
              MX2C     2      1.0        2.0
              NOR2    94      1.0       94.0
             NOR2A   277      1.0      277.0
             NOR2B   473      1.0      473.0
              NOR3    10      1.0       10.0
             NOR3A    79      1.0       79.0
             NOR3B   120      1.0      120.0
             NOR3C   120      1.0      120.0
               OA1    58      1.0       58.0
              OA1A    21      1.0       21.0
              OA1B    15      1.0       15.0
              OA1C    11      1.0       11.0
              OAI1     3      1.0        3.0
               OR2   174      1.0      174.0
              OR2A    41      1.0       41.0
              OR2B    19      1.0       19.0
               OR3   306      1.0      306.0
              OR3A     5      1.0        5.0
              OR3B     1      1.0        1.0
             RCOSC     1      0.0        0.0
               VCC     9      0.0        0.0
               XA1    24      1.0       24.0
              XA1A     2      1.0        2.0
              XA1B     2      1.0        2.0
             XAI1A     1      1.0        1.0
             XNOR2    13      1.0       13.0
             XNOR3     1      1.0        1.0
               XO1     3      1.0        3.0
              XOR2    63      1.0       63.0
              XOR3    21      1.0       21.0
              ZOR3     1      1.0        1.0


          DFN0E0P0     1      1.0        1.0
          DFN0E1P0     1      1.0        1.0
              DFN1    42      1.0       42.0
            DFN1C0    12      1.0       12.0
            DFN1E0     4      1.0        4.0
          DFN1E0C0    17      1.0       17.0
            DFN1E1    16      1.0       16.0
          DFN1E1C0    34      1.0       34.0
            DFN1P0    34      1.0       34.0
         RAM512X18     1      0.0        0.0
                   -----          ----------
             TOTAL  2607              2582.0


  IO Cell usage:
              cell count
             INBUF     2
         INBUF_MSS     2
            OUTBUF     8
        OUTBUF_MSS     1
                   -----
             TOTAL    13


Core Cells         : 2582 of 11520 (22%)
IO Cells           : 13

  RAM/ROM Usage Summary
Block Rams : 1 of 24 (4%)

Mapper successful!

At Mapper Exit (Time elapsed 0h:00m:13s; Memory used current: 27MB peak: 112MB)

Process took 0h:00m:30s realtime, 0h:00m:13s cputime
# Mon Nov 19 10:29:16 2012

###########################################################]
