

##### START OF TIMING REPORT #####[
# Timing Report written on Mon Feb 27 16:55:02 2012
#


Top view:               SF_Zi1
Operating conditions:   smartfusion.COMWC-2
Requested Frequency:    20.0 MHz
Wire load mode:         top
Wire load model:        smartfusion
Paths requested:        5
Constraint File(s):    C:\LPF_AC382_DF\A2F500\zeroization\component\work\SF_Zi1_MSS\mss_tshell_syn.sdc
                       
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: NA

                   Requested     Estimated     Requested     Estimated               Clock        Clock      
Starting Clock     Frequency     Frequency     Period        Period        Slack     Type         Group      
-------------------------------------------------------------------------------------------------------------
FAB_CLK            20.0 MHz      22.5 MHz      50.000        44.403        2.798     declared     clk_group_0
FCLK               20.0 MHz      NA            50.000        NA            NA        declared     clk_group_0
=============================================================================================================



Clock Relationships
*******************

Clocks             |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------
Starting  Ending   |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------
FAB_CLK   FAB_CLK  |  0.000       False  |  0.000       False  |  25.000      False  |  25.000      False
=========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]

