Actel Designer Software
Version: 10.0.9.37
Release: v10.0

Info: The design SF_Zi1.adb was last modified by software version 10.0.9.37.
Opened an existing Libero design SF_Zi1.adb.

The Execute Script command succeeded ( 00:00:25 )
***** Layout Variables *********************************************

Mode: TIMING_DRIVEN
Power-driven Layout: OFF
Incremental Placement: OFF
Incremental Route: OFF


Info: I/O Bank Assigner detected (1) out of (6) I/O Bank(s) with locked I/O technologies.

Running I/O Bank Assigner.

I/O Bank Assigner completed successfully.
 

Planning global net placement...


Global net placement completed successfully.


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Timing-driven Placer Started: Thu Jan 05 19:44:46 2012



Placer Finished: Thu Jan 05 19:45:09 2012

Total Placer CPU Time:     00:00:23



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Timing-driven Router 

Design: SF_Zi1                          Started: Thu Jan 05 19:45:13 2012



 

Iterative improvement...



Timing-driven Router completed successfully.



Design: SF_Zi1                          

Finished: Thu Jan 05 19:45:27 2012

Total CPU Time:     00:00:14            Total Elapsed Time: 00:00:14

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Loading the Timing data for the design.
Finished loading the Timing data.
TIMER: Max delay timing requirements have been met.
TIMER: Min delay timing requirements have been met.

The Layout command succeeded ( 00:00:50 )

The Export-map command succeeded ( 00:00:08 )
CHECKSUM: ADC2
Wrote to the file: F:\zeroization\SF_Zi1\designer\impl2\SF_Zi1.fdb

The Export command succeeded ( 00:00:11 )
Design saved to file F:\zeroization\SF_Zi1\designer\impl2\SF_Zi1.adb.
Design closed.

