// bp_glue.v

module bp_glue(NPORESET, NPBRESET, SYSCLK, NSYSRESET,DIVCLK, 
                TESTCLK,UIN, UOUT, RCGND,TESTPOINT
                );

input NPORESET;    //POR
input NPBRESET;    //PB Reset
output NSYSRESET;  //Modified reset output
input SYSCLK;
output DIVCLK;

output TESTCLK;
input  [2:0] UIN;  //unused inputs to support ribbon cable connections
output UOUT;       //unused output to support ribbon cable connections
output [3:0] RCGND; // GNDs to support Ribbon Cable
output TESTPOINT;

wire DIVCLK;

reg clkdiv2;
reg clkdiv4;
reg clkdiv8;
reg clkdiv16;


reg NSYSRESET;
reg [1:0] RESETSM;

//Reset controller
//System in reset until both POR and PBR are deasserted.
//pushing PBR will generate a NSYSRESET and the system will restart.

parameter
	s0 = 2'b00,  
	s1 = 2'b01,
	s2 = 2'b10,
	s3 = 2'b11;


//Suppoort for Ribbon Cable Connection
assign UOUT = UIN[0] | UIN[1] | UIN[2];
assign RCGND = 4'b0000;
assign TESTPOINT = 1'b0;


always @ (posedge DIVCLK or negedge NPORESET)
begin
		if (!NPORESET) 
			begin
				RESETSM <= s0;
				NSYSRESET <= 1'b0;
			end
		else
			case (RESETSM) 
				s0:
					if (NPBRESET == 1'b0) 
						begin
				            RESETSM <= s0;
				            NSYSRESET <= 1'b0;
						end
					else 
						begin
				            RESETSM <= s1;
				            NSYSRESET <= 1'b0;
						end
				s1:
					if (NPBRESET == 1'b0) 
						begin
				            RESETSM <= s2;
				            NSYSRESET <= 1'b0;
						end
					else 
						begin
				            RESETSM <= s1;
				            NSYSRESET <= 1'b0;
						end
				s2:
					if (NPBRESET == 1'b0) 
						begin
				            RESETSM <= s2;
				            NSYSRESET <= 1'b0;
						end
					else 
						begin
				            RESETSM <= s3;
				            NSYSRESET <= 1'b1;
						end
				s3:
					if (NPBRESET == 1'b0) 
						begin
				            RESETSM <= s2;
				            NSYSRESET <= 1'b0;
						end
					else 
						begin
				            RESETSM <= s3;
				            NSYSRESET <= 1'b1;
						end
		 	endcase
end



//48MHz clock divider
always @(posedge SYSCLK)
      begin
        clkdiv2 <= !clkdiv2;
      end
always @(posedge clkdiv2)
      begin
        clkdiv4 <= !clkdiv4;
      end
always @(posedge clkdiv4)
      begin
        clkdiv8 <= !clkdiv8;
      end
always @(posedge clkdiv8)
      begin
        clkdiv16 <= !clkdiv16;
      end


assign DIVCLK = clkdiv8;  //6MHz UTCK
assign TESTCLK = clkdiv8;

endmodule