KEY LIBERO "10.1"
KEY CAPTURE "10.1.1.6"
KEY DEFAULT_IMPORT_LOC "C:\Actelprj\JTAG_READID\stimulus"
KEY DEFAULT_OPEN_LOC ""
KEY ProjectID "3ef59fc7-90fe-4fc7-90fe-cfc790fecfc7"
KEY HDLTechnology "VERILOG"
KEY VendorTechnology_Family "SmartFusion"
KEY VendorTechnology_Die "IP6X5M2"
KEY VendorTechnology_Package "fg484"
KEY VendorTechnology_Speed "STD"
KEY VendorTechnology_DieVoltage "1.5"
KEY VendorTechnology_IO_DEFT_STD "LVTTL"
KEY VendorTechnology_OPCONR "COM"
KEY VendorTechnology_TEMPR "COM"
KEY VendorTechnology_VCCI_1.5_VOLTR "COM"
KEY VendorTechnology_VCCI_1.8_VOLTR "COM"
KEY VendorTechnology_VCCI_2.5_VOLTR "COM"
KEY VendorTechnology_VCCI_3.3_VOLTR "COM"
KEY VendorTechnology_VOLTR "COM"
KEY ProjectLocation "C:\LPF_AC382_DF\A2F500\zeroization"
KEY ProjectDescription ""
KEY SimulationType "VERILOG"
KEY Vendor "Actel"
KEY ActiveRoot "SF_Zi1::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
VALUE="Impl2",NUM=2
VALUE="Impl3",NUM=3
CURREV=3
ENDLIST
LIST LIBRARIES
MSS_BFM_LIB
COREAPB3_LIB
ENDLIST
LIST LIBRARY_MSS_BFM_LIB
ALIAS=..\component\Actel\SmartFusionMSS\MSS\2.5.106\mti\user_verilog\MSS_BFM_LIB
COMPILE_OPTION=REFRESH_AND_COMPILE
ENDLIST
LIST LIBRARY_COREAPB3_LIB
ALIAS=..\component\Actel\DirectCore\CoreAPB3\3.0.103\mti\user_vlog\COREAPB3_LIB
COMPILE_OPTION=REFRESH_AND_COMPILE
ENDLIST
LIST FileManager
VALUE "<project>\component\Actel\DirectCore\COREABC\3.3.100\COREABC.cxf,actgen_cxf"
STATE="utd"
TIME="1353301080"
SIZE="480"
PARENT="<project>\component\work\SF_Zi1\SF_Zi1.cxf"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\CoreAPB3.cxf,actgen_cxf"
STATE="utd"
TIME="1353301082"
SIZE="2975"
PARENT="<project>\component\work\SF_Zi1\SF_Zi1.cxf"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\coreparameters.v,tb_hdl"
STATE="utd"
TIME="1353301082"
SIZE="883"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\CoreAPB3.cxf"
IS_READONLY="TRUE"
IS_INCLUDED="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\mti\scripts\wave_user.do,do"
STATE="utd"
TIME="1346649905"
SIZE="912"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
STATE="utd"
TIME="1346649904"
SIZE="4636"
LIBRARY="COREAPB3_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
STATE="utd"
TIME="1346649904"
SIZE="9073"
LIBRARY="COREAPB3_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
STATE="utd"
TIME="1346649904"
SIZE="25129"
LIBRARY="COREAPB3_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
STATE="utd"
TIME="1346649904"
SIZE="36275"
LIBRARY="COREAPB3_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
STATE="utd"
TIME="1346649904"
SIZE="122456"
LIBRARY="COREAPB3_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v,hdl"
STATE="utd"
TIME="1346649907"
SIZE="16587"
LIBRARY="COREAPB3_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3_muxptob3.v,hdl"
STATE="utd"
TIME="1346649907"
SIZE="5459"
LIBRARY="COREAPB3_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\CoreAPB3.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\test\user\testbench.v,tb_hdl"
STATE="utd"
TIME="1346649904"
SIZE="16546"
LIBRARY="COREAPB3_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\CoreAPB3.cxf"
MODULE_UNDER_TEST="testbench"
SIMULATION_TIME="-all"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS\2.5.106\MSS.cxf,actgen_cxf"
STATE="utd"
TIME="1330337793"
SIZE="945"
PARENT="<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v,hdl"
STATE="utd"
TIME="1318330047"
SIZE="11243"
PARENT="<project>\component\Actel\SmartFusionMSS\MSS\2.5.106\MSS.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideSYNTHESIS"
TOOL_CONSTRAINT_USE="SYNPLIFY7_EXT"
END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_CCC\2.0.106\MSS_CCC.cxf,actgen_cxf"
STATE="utd"
TIME="1330337779"
SIZE="252"
PARENT="<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_CM3\1.0.200\MSS_CM3.cxf,actgen_cxf"
STATE="utd"
TIME="1330337779"
SIZE="252"
PARENT="<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_COM\1.0.200\MSS_COM.cxf,actgen_cxf"
STATE="utd"
TIME="1330337779"
SIZE="252"
PARENT="<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_DMA\1.0.101\MSS_DMA.cxf,actgen_cxf"
STATE="utd"
TIME="1330337779"
SIZE="252"
PARENT="<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_ENVM\2.3.102\MSS_ENVM.cxf,actgen_cxf"
STATE="utd"
TIME="1330337780"
SIZE="253"
PARENT="<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_FIO\1.0.203\MSS_FIO.cxf,actgen_cxf"
STATE="utd"
TIME="1330337780"
SIZE="252"
PARENT="<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_GPIO\1.0.101\MSS_GPIO.cxf,actgen_cxf"
STATE="utd"
TIME="1330337780"
SIZE="253"
PARENT="<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_INTR\1.0.101\MSS_INTR.cxf,actgen_cxf"
STATE="utd"
TIME="1330337780"
SIZE="253"
PARENT="<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_RESET\1.0.101\MSS_RESET.cxf,actgen_cxf"
STATE="utd"
TIME="1330337780"
SIZE="254"
PARENT="<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_RTC\1.0.100\MSS_RTC.cxf,actgen_cxf"
STATE="utd"
TIME="1330337780"
SIZE="252"
PARENT="<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_TIMER\1.0.100\MSS_TIMER.cxf,actgen_cxf"
STATE="utd"
TIME="1330337780"
SIZE="254"
PARENT="<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_UART\1.0.101\MSS_UART.cxf,actgen_cxf"
STATE="utd"
TIME="1330337780"
SIZE="253"
PARENT="<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_UFROM\1.0.100\MSS_UFROM.cxf,actgen_cxf"
STATE="utd"
TIME="1330337780"
SIZE="254"
PARENT="<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf"
ENDFILE
VALUE "<project>\component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf,actgen_cxf"
STATE="utd"
TIME="1330006603"
SIZE="2034"
ENDFILE
VALUE "<project>\component\work\DESIGN_IO\DESIGN_IO.cxf,actgen_cxf"
STATE="utd"
TIME="1325762545"
SIZE="413"
ENDFILE
VALUE "<project>\component\work\SF_Zi1\COREABC_0\CoreABC.log,log"
STATE="utd"
TIME="1353301079"
SIZE="3130"
PARENT="<project>\component\work\SF_Zi1\COREABC_0\SF_Zi1_COREABC_0_COREABC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1\COREABC_0\coreparameters_tgi.v,hdl"
STATE="utd"
TIME="1353301079"
SIZE="1710"
PARENT="<project>\component\work\SF_Zi1\COREABC_0\SF_Zi1_COREABC_0_COREABC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\acmtable.v,hdl"
STATE="utd"
TIME="1353301080"
SIZE="3361"
PARENT="<project>\component\work\SF_Zi1\COREABC_0\SF_Zi1_COREABC_0_COREABC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v,hdl"
STATE="utd"
TIME="1353301080"
SIZE="54402"
PARENT="<project>\component\work\SF_Zi1\COREABC_0\SF_Zi1_COREABC_0_COREABC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\debugblk.v,hdl"
STATE="utd"
TIME="1353301080"
SIZE="28050"
PARENT="<project>\component\work\SF_Zi1\COREABC_0\SF_Zi1_COREABC_0_COREABC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\instructions.v,hdl"
STATE="utd"
TIME="1353301080"
SIZE="165027"
PARENT="<project>\component\work\SF_Zi1\COREABC_0\SF_Zi1_COREABC_0_COREABC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\instructnvm_bb.v,hdl"
STATE="utd"
TIME="1353301080"
SIZE="2134"
PARENT="<project>\component\work\SF_Zi1\COREABC_0\SF_Zi1_COREABC_0_COREABC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\instructram.v,hdl"
STATE="utd"
TIME="1353301080"
SIZE="12031"
PARENT="<project>\component\work\SF_Zi1\COREABC_0\SF_Zi1_COREABC_0_COREABC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\iram512x9_smartfusion.v,hdl"
STATE="utd"
TIME="1353301080"
SIZE="3872"
PARENT="<project>\component\work\SF_Zi1\COREABC_0\SF_Zi1_COREABC_0_COREABC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ram256x16_smartfusion.v,hdl"
STATE="utd"
TIME="1353301080"
SIZE="2947"
PARENT="<project>\component\work\SF_Zi1\COREABC_0\SF_Zi1_COREABC_0_COREABC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ram256x8_rtl.v,hdl"
STATE="utd"
TIME="1353301080"
SIZE="1231"
PARENT="<project>\component\work\SF_Zi1\COREABC_0\SF_Zi1_COREABC_0_COREABC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ramblocks.v,hdl"
STATE="utd"
TIME="1353301080"
SIZE="7899"
PARENT="<project>\component\work\SF_Zi1\COREABC_0\SF_Zi1_COREABC_0_COREABC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\support.v,hdl"
STATE="utd"
TIME="1353301080"
SIZE="56274"
PARENT="<project>\component\work\SF_Zi1\COREABC_0\SF_Zi1_COREABC_0_COREABC.cxf"
IS_READONLY="TRUE"
IS_INCLUDED="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\test\apbmodel.v,tb_hdl"
STATE="utd"
TIME="1353301080"
SIZE="4831"
PARENT="<project>\component\work\SF_Zi1\COREABC_0\SF_Zi1_COREABC_0_COREABC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\test\testbench.v,tb_hdl"
STATE="utd"
TIME="1353301080"
SIZE="23644"
PARENT="<project>\component\work\SF_Zi1\COREABC_0\SF_Zi1_COREABC_0_COREABC.cxf"
MODULE_UNDER_TEST="TESTBENCH"
SIMULATION_TIME="-all"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\test\testsupport.v,tb_hdl"
STATE="utd"
TIME="1353301080"
SIZE="29934"
PARENT="<project>\component\work\SF_Zi1\COREABC_0\SF_Zi1_COREABC_0_COREABC.cxf"
IS_READONLY="TRUE"
IS_INCLUDED="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1\COREABC_0\SF_Zi1_COREABC_0_COREABC.cxf,actgen_cxf"
STATE="utd"
TIME="1353301080"
SIZE="3043"
PARENT="<project>\component\work\SF_Zi1\SF_Zi1.cxf"
ENDFILE
VALUE "<project>\component\work\SF_Zi1\SF_Zi1.cxf,actgen_cxf"
STATE="utd"
TIME="1353301092"
SIZE="4871"
ENDFILE
VALUE "<project>\component\work\SF_Zi1\SF_Zi1.pdc,pdc"
STATE="utd"
TIME="1353301077"
SIZE="1396"
PARENT="<project>\component\work\SF_Zi1\SF_Zi1.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideDESIGNER"
END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1\SF_Zi1.v,hdl"
STATE="utd"
TIME="1353301082"
SIZE="16530"
PARENT="<project>\component\work\SF_Zi1\SF_Zi1.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1\testbench.v,tb_hdl"
STATE="utd"
TIME="1353301087"
SIZE="1604"
PARENT="<project>\component\work\SF_Zi1\SF_Zi1.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.cxf,actgen_cxf"
STATE="utd"
TIME="1330337779"
SIZE="487"
PARENT="<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf"
ENDFILE
VALUE "<project>\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v,hdl"
STATE="utd"
TIME="1330337779"
SIZE="2840"
PARENT="<project>\component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1_MSS\MSS_ENVM_0\MSS_ENVM_0.efc,efc"
STATE="utd"
TIME="1330337780"
SIZE="15875"
PARENT="<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1_MSS\mss_tshell.v,hdl"
STATE="utd"
TIME="1330337780"
SIZE="12226"
PARENT="<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideSYNTHESIS"
TOOL_CONSTRAINT_USE="SYNPLIFY7_EXT"
END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1_MSS\mss_tshell_syn.sdc,sdc"
STATE="utd"
TIME="1330337780"
SIZE="190"
PARENT="<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideSYNTHESIS"
TOOL_CONSTRAINT_USE="SYNPLIFY7_EXT"
END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf,actgen_cxf"
STATE="utd"
TIME="1330337795"
SIZE="9250"
ENDFILE
VALUE "<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.pdc,pdc"
STATE="utd"
TIME="1330337774"
SIZE="1039"
PARENT="<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideDESIGNER"
END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.v,hdl"
STATE="utd"
TIME="1330337794"
SIZE="9315"
PARENT="<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\SF_Zi1_MSS\testbench.v,tb_hdl"
STATE="utd"
TIME="1330337794"
SIZE="1509"
PARENT="<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\designer\impl1\SF_Zi1.adb,adb"
STATE="ood"
TIME="1325773323"
SIZE="1487360"
ENDFILE
VALUE "<project>\designer\impl1\SF_Zi1.fdb,fdb"
STATE="ood"
TIME="1325773319"
SIZE="95202"
ENDFILE
VALUE "<project>\designer\impl1\SF_Zi1.ide_des,ide_des"
STATE="utd"
TIME="1330341848"
SIZE="1191"
ENDFILE
VALUE "<project>\designer\impl1\SF_Zi1_compile_log.rpt,log"
STATE="utd"
TIME="1325773030"
SIZE="30016"
ENDFILE
VALUE "<project>\designer\impl1\SF_Zi1_fp\projectData\SF_Zi1.pdb,pdb"
STATE="utd"
TIME="1325773515"
SIZE="103936"
ENDFILE
VALUE "<project>\designer\impl1\SF_Zi1_fp\SF_Zi1.pdb,pdb"
STATE="ood"
TIME="1325773477"
SIZE="103936"
ENDFILE
VALUE "<project>\designer\impl1\SF_Zi1_fp\SF_Zi1.pro,pro"
STATE="utd"
TIME="1325773515"
SIZE="1922"
ENDFILE
VALUE "<project>\designer\impl1\SF_Zi1_prgdata_log.rpt,log"
STATE="utd"
TIME="1330342042"
SIZE="753"
ENDFILE
VALUE "<project>\designer\impl3\SF_Zi1.adb,adb"
STATE="utd"
TIME="1330342041"
SIZE="2830848"
ENDFILE
VALUE "<project>\designer\impl3\SF_Zi1.fdb,fdb"
STATE="utd"
TIME="1330342041"
SIZE="154451"
ENDFILE
VALUE "<project>\designer\impl3\SF_Zi1.ide_des,ide_des"
STATE="utd"
TIME="1330342041"
SIZE="1196"
ENDFILE
VALUE "<project>\designer\impl3\SF_Zi1_compile_log.rpt,log"
STATE="utd"
TIME="1330341933"
SIZE="30278"
ENDFILE
VALUE "<project>\designer\impl3\SF_Zi1_fp\projectData\SF_Zi1.pdb,pdb"
STATE="utd"
TIME="1353301635"
SIZE="162816"
ENDFILE
VALUE "<project>\designer\impl3\SF_Zi1_fp\SF_Zi1.pdb,pdb"
STATE="utd"
TIME="1330342079"
SIZE="163328"
ENDFILE
VALUE "<project>\designer\impl3\SF_Zi1_fp\SF_Zi1.pro,pro"
STATE="utd"
TIME="1343639911"
SIZE="1997"
ENDFILE
VALUE "<project>\designer\impl3\SF_Zi1_placeroute_log.rpt,log"
STATE="utd"
TIME="1330342010"
SIZE="2530"
ENDFILE
VALUE "<project>\designer\impl3\SF_Zi1_verifytiming_log.rpt,log"
STATE="utd"
TIME="1330342020"
SIZE="1284"
ENDFILE
VALUE "<project>\hdl\bp_glue.v,hdl"
STATE="utd"
TIME="1268814232"
SIZE="2548"
ENDFILE
VALUE "<project>\hdl\IAP.v,hdl"
STATE="utd"
TIME="1325864821"
SIZE="10938"
ENDFILE
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
STATE="utd"
TIME="1346649905"
SIZE="1237"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\CoreAPB3.cxf"
ENDFILE
VALUE "<project>\simulation\CompileDssBfm.tcl,sim"
STATE="utd"
TIME="1318330038"
SIZE="41"
PARENT="<project>\component\Actel\SmartFusionMSS\MSS\2.5.106\MSS.cxf"
ENDFILE
VALUE "<project>\simulation\coreapb3_usertb_apb_master.bfm,sim"
STATE="utd"
TIME="1346649905"
SIZE="10524"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\CoreAPB3.cxf"
ENDFILE
VALUE "<project>\simulation\coreapb3_usertb_include.bfm,sim"
STATE="utd"
TIME="1346649905"
SIZE="3992"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\CoreAPB3.cxf"
ENDFILE
VALUE "<project>\simulation\subsystem.bfm,sim"
STATE="utd"
TIME="1353301084"
SIZE="834"
PARENT="<project>\component\work\SF_Zi1\SF_Zi1.cxf"
ENDFILE
VALUE "<project>\simulation\test.bfm,sim"
STATE="utd"
TIME="1330337779"
SIZE="5460"
PARENT="<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf"
ENDFILE
VALUE "<project>\simulation\user.bfm,sim"
STATE="utd"
TIME="1325762527"
SIZE="670"
PARENT="<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.cxf"
ENDFILE
VALUE "<project>\synthesis\SF_Zi1.edn,syn_edn"
STATE="utd"
TIME="1330341902"
SIZE="1287430"
ENDFILE
VALUE "<project>\synthesis\SF_Zi1.so,so"
STATE="utd"
TIME="1330341902"
SIZE="216"
ENDFILE
VALUE "<project>\synthesis\SF_Zi1_sdc.sdc,syn_sdc"
STATE="utd"
TIME="1330341902"
SIZE="511"
ENDFILE
VALUE "<project>\synthesis\SF_Zi1_syn.prj,prj"
STATE="utd"
TIME="1353300637"
SIZE="3670"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "SF_Zi1::work"
FILE "<project>\component\work\SF_Zi1\SF_Zi1.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\subsystem.bfm,sim"
VALUE "<project>\component\work\SF_Zi1\testbench.v,tb_hdl"
VALUE "<project>\component\work\SF_Zi1\SF_Zi1.pdc,pdc"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\work\SF_Zi1\testbench.v,tb_hdl"
ENDLIST
LIST SynthesisConstraints
VALUE "<project>\component\work\SF_Zi1_MSS\mss_tshell_syn.sdc,sdc"
ENDLIST
LIST ProjectState5.1
LIST Impl1
LiberoState=Post_Synthesis
ideSTIMULUS=StateSuccess
ideSYNTHESIS(<project>\synthesis\SF_Zi1.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
LiberoState=Post_Synthesis
ideSTIMULUS=StateSuccess
ideSYNTHESIS(<project>\synthesis\SF_Zi1.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl3
LiberoState=Post_Layout
ideSTIMULUS=StateSuccess
ideSYNTHESIS(<project>\synthesis\SF_Zi1.edn,syn_edn)=StateSuccess
ideDESIGNER(<project>\designer\impl3\SF_Zi1.adb,adb)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "SF_Zi1_COREABC_0_COREABC::work"
FILE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v,hdl"
LIST Other_Association
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\test\testsupport.v,tb_hdl"
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\test\apbmodel.v,tb_hdl"
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\test\testbench.v,tb_hdl"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\test\testsupport.v,tb_hdl"
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\test\apbmodel.v,tb_hdl"
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\test\testbench.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl3
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "SF_Zi1_MSS::work"
FILE "<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.v,hdl"
LIST Other_Association
VALUE "<project>\component\work\SF_Zi1_MSS\mss_tshell_syn.sdc,sdc"
VALUE "<project>\simulation\user.bfm,sim"
VALUE "<project>\simulation\test.bfm,sim"
VALUE "<project>\component\work\SF_Zi1_MSS\testbench.v,tb_hdl"
VALUE "<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.pdc,pdc"
VALUE "<project>\component\work\SF_Zi1_MSS\MSS_ENVM_0\MSS_ENVM_0.efc,efc"
VALUE "<project>\simulation\CompileDssBfm.tcl,sim"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\work\SF_Zi1_MSS\testbench.v,tb_hdl"
ENDLIST
LIST SynthesisConstraints
VALUE "<project>\component\work\SF_Zi1_MSS\mss_tshell_syn.sdc,sdc"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl3
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "CoreAPB3::COREAPB3_LIB"
FILE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
VALUE "<project>\simulation\coreapb3_usertb_include.bfm,sim"
VALUE "<project>\simulation\coreapb3_usertb_apb_master.bfm,sim"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\mti\scripts\wave_user.do,do"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\test\user\testbench.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl3
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
LIST SF_Zi1
VALUE "<project>\component\work\SF_Zi1\testbench.v,tb_hdl"
ENDLIST
LIST SF_Zi1_COREABC_0_COREABC
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\test\testsupport.v,tb_hdl"
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\test\apbmodel.v,tb_hdl"
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\test\testbench.v,tb_hdl"
ENDLIST
LIST SF_Zi1_MSS
VALUE "<project>\component\work\SF_Zi1_MSS\testbench.v,tb_hdl"
ENDLIST
LIST CoreAPB3
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\test\user\testbench.v,tb_hdl"
ENDLIST
ENDLIST
LIST Other_Association
LIST SF_Zi1
VALUE "<project>\simulation\subsystem.bfm,sim"
VALUE "<project>\component\work\SF_Zi1\testbench.v,tb_hdl"
VALUE "<project>\component\work\SF_Zi1\SF_Zi1.pdc,pdc"
ENDLIST
LIST SF_Zi1_COREABC_0_COREABC
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\test\testsupport.v,tb_hdl"
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\test\apbmodel.v,tb_hdl"
VALUE "<project>\component\work\SF_Zi1\COREABC_0\rtl\vlog\test\testbench.v,tb_hdl"
ENDLIST
LIST SF_Zi1_MSS
VALUE "<project>\component\work\SF_Zi1_MSS\mss_tshell_syn.sdc,sdc"
VALUE "<project>\simulation\user.bfm,sim"
VALUE "<project>\simulation\test.bfm,sim"
VALUE "<project>\component\work\SF_Zi1_MSS\testbench.v,tb_hdl"
VALUE "<project>\component\work\SF_Zi1_MSS\SF_Zi1_MSS.pdc,pdc"
VALUE "<project>\component\work\SF_Zi1_MSS\MSS_ENVM_0\MSS_ENVM_0.efc,efc"
VALUE "<project>\simulation\CompileDssBfm.tcl,sim"
ENDLIST
LIST CoreAPB3
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
VALUE "<project>\simulation\coreapb3_usertb_include.bfm,sim"
VALUE "<project>\simulation\coreapb3_usertb_apb_master.bfm,sim"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\3.0.103\mti\scripts\wave_user.do,do"
ENDLIST
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DumpVCD=false
VCDFileName=power.vcd
VHDL2008=false
Verilog2001=false
SystemVerilog=false
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=TRUE
AutoCheckConstraints=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
EnableViewDraw=FALSE
UpdateViewDrawIni=TRUE
GenerateHDLFromSchematic=TRUE
FlashProInputFile=fdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
NAME="SoftConsole1"
FUNCTION="SoftwareIDE"
TOOL="SoftConsole"
LOCATION="C:\Microsemi\Libero_v10.1\SoftConsole\Eclipse\eclipse.exe"
PARAM=""
BATCH=0
EndProfile
NAME="Synplify Pro AE"
FUNCTION="Synthesis"
TOOL="Synplify Pro AE"
LOCATION="C:\Microsemi\Libero_v10.1\Synopsys\synplify_F201203MSP1\bin\synplify_pro.exe"
PARAM="-licensetype synplifypro_actel -batch -log synplify.log"
BATCH=1
EndProfile
NAME="ModelSim AE"
FUNCTION="Simulation"
TOOL="ModelSim"
LOCATION="C:\Microsemi\Libero_v10.1\Model\win32acoem\modelsim.exe"
PARAM=""
BATCH=0
EndProfile
NAME="WFL"
FUNCTION="Stimulus"
TOOL="WFL"
LOCATION="syncad.exe"
PARAM="-p waveform"
BATCH=0
EndProfile
NAME="FlashPro"
FUNCTION="Program"
TOOL="FlashPro"
LOCATION="C:\Microsemi\Libero_v10.1\Designer\bin\FlashPro.exe"
PARAM=""
BATCH=0
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "SF_Zi1::work"
LIST Impl1
LiberoState=Post_Synthesis
ideSTIMULUS=StateSuccess
ideSYNTHESIS(<project>\synthesis\SF_Zi1.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
LiberoState=Post_Synthesis
ideSTIMULUS=StateSuccess
ideSYNTHESIS(<project>\synthesis\SF_Zi1.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl3
LiberoState=Post_Layout
ideSTIMULUS=StateSuccess
ideSYNTHESIS(<project>\synthesis\SF_Zi1.edn,syn_edn)=StateSuccess
ideDESIGNER(<project>\designer\impl3\SF_Zi1.adb,adb)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "SF_Zi1_COREABC_0_COREABC::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl3
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "SF_Zi1_MSS::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl3
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "CoreAPB3::COREAPB3_LIB"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl3
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
SmartDesign;SF_Zi1
Reports;Reports
ACTIVEVIEW;Reports
ENDLIST
LIST ModuleSubBlockList
LIST "BIBUF_MSS::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "BIBUF_OPEND_MSS::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "bp_glue::work","hdl\bp_glue.v","FALSE","FALSE"
ENDLIST
LIST "DESIGN_FIRMWARE::work","component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf","TRUE","FALSE"
SUBBLOCK "HAL::work","","FALSE","FALSE"
SUBBLOCK "MSS_GPIO_Driver::work","","FALSE","FALSE"
SUBBLOCK "MSS_IAP_Driver::work","","FALSE","FALSE"
SUBBLOCK "MSS_NVM_Driver::work","","FALSE","FALSE"
SUBBLOCK "MSS_PDMA_Driver::work","","FALSE","FALSE"
SUBBLOCK "MSS_RTC_Driver::work","","FALSE","FALSE"
SUBBLOCK "MSS_Timer_Driver::work","","FALSE","FALSE"
SUBBLOCK "MSS_UART_Driver::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion_CMSIS_PAL::work","","FALSE","FALSE"
ENDLIST
LIST "DESIGN_IO::work","component\work\DESIGN_IO\DESIGN_IO.cxf","TRUE","FALSE"
ENDLIST
LIST "HAL::work","","FALSE","FALSE"
ENDLIST
LIST "iap::work","hdl\IAP.v","FALSE","FALSE"
ENDLIST
LIST "INBUF_LVDS_MCCC::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "INBUF_LVPECL_MCCC::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "INBUF_MCCC::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "INBUF_MSS::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "MSS_ALL::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "MSS_APB::work","component\work\SF_Zi1_MSS\mss_tshell.v","FALSE","FALSE"
ENDLIST
LIST "MSS_CCC::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "MSS_GPIO_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_IAP_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_LPXTLOSC::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "MSS_NVM_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_PDMA_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_RTC_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_Timer_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_UART_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_XTLOSC::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "MSSINT::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "OUTBUF_MSS::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "SF_Zi1::work","component\work\SF_Zi1\SF_Zi1.v","TRUE","FALSE"
SUBBLOCK "SF_Zi1_COREABC_0_COREABC::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v","FALSE","FALSE"
SUBBLOCK "iap::work","hdl\IAP.v","FALSE","FALSE"
SUBBLOCK "SF_Zi1_MSS::work","component\work\SF_Zi1_MSS\SF_Zi1_MSS.v","TRUE","FALSE"
SUBBLOCK "CoreAPB3::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v","FALSE","FALSE"
ENDLIST
LIST "SF_Zi1_COREABC_0_ACMTABLE::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\core\acmtable.v","FALSE","FALSE"
ENDLIST
LIST "SF_Zi1_COREABC_0_COREABC::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v","FALSE","FALSE"
SUBBLOCK "SF_Zi1_COREABC_0_RAMBLOCKS::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ramblocks.v","FALSE","FALSE"
SUBBLOCK "SF_Zi1_COREABC_0_ACMTABLE::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\core\acmtable.v","FALSE","FALSE"
SUBBLOCK "SF_Zi1_COREABC_0_INSTRUCTIONS::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\core\instructions.v","FALSE","FALSE"
SUBBLOCK "SF_Zi1_COREABC_0_INSTRUCTRAM::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\core\instructram.v","FALSE","FALSE"
SUBBLOCK "SF_Zi1_COREABC_0_INSTRUCTNVM::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\core\instructnvm_bb.v","FALSE","FALSE"
SUBBLOCK "SF_Zi1_COREABC_0_DEBUGBLK::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\core\debugblk.v","FALSE","FALSE"
ENDLIST
LIST "SF_Zi1_COREABC_0_DEBUGBLK::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\core\debugblk.v","FALSE","FALSE"
ENDLIST
LIST "SF_Zi1_COREABC_0_INSTRUCTIONS::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\core\instructions.v","FALSE","FALSE"
ENDLIST
LIST "SF_Zi1_COREABC_0_INSTRUCTNVM::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\core\instructnvm_bb.v","FALSE","FALSE"
ENDLIST
LIST "SF_Zi1_COREABC_0_INSTRUCTRAM::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\core\instructram.v","FALSE","FALSE"
SUBBLOCK "SF_Zi1_COREABC_0_IRAM512X9::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\core\iram512x9_smartfusion.v","FALSE","FALSE"
ENDLIST
LIST "SF_Zi1_COREABC_0_IRAM512X9::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\core\iram512x9_smartfusion.v","FALSE","FALSE"
ENDLIST
LIST "SF_Zi1_COREABC_0_RAM256X16::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ram256x16_smartfusion.v","FALSE","FALSE"
ENDLIST
LIST "SF_Zi1_COREABC_0_RAM256X8::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ram256x8_rtl.v","FALSE","FALSE"
ENDLIST
LIST "SF_Zi1_COREABC_0_RAMBLOCKS::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ramblocks.v","FALSE","FALSE"
SUBBLOCK "SF_Zi1_COREABC_0_RAM256X16::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ram256x16_smartfusion.v","FALSE","FALSE"
SUBBLOCK "SF_Zi1_COREABC_0_RAM256X8::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\core\ram256x8_rtl.v","FALSE","FALSE"
ENDLIST
LIST "SF_Zi1_MSS::work","component\work\SF_Zi1_MSS\SF_Zi1_MSS.v","TRUE","FALSE"
SUBBLOCK "INBUF_MSS::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
SUBBLOCK "OUTBUF_MSS::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
SUBBLOCK "SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC::work","component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v","FALSE","FALSE"
SUBBLOCK "MSS_APB::work","component\work\SF_Zi1_MSS\mss_tshell.v","FALSE","FALSE"
ENDLIST
LIST "SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC::work","component\work\SF_Zi1_MSS\MSS_CCC_0\SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC.v","FALSE","FALSE"
SUBBLOCK "MSS_CCC::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "SmartFusion_CMSIS_PAL::work","","FALSE","FALSE"
ENDLIST
LIST "TRIBUFF_MSS::work","component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "SF_Zi1_COREABC_0_APBModel::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\test\apbmodel.v","FALSE","TRUE"
ENDLIST
LIST "TESTBENCH::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\test\testbench.v","FALSE","TRUE"
SUBBLOCK "SF_Zi1_COREABC_0_COREABC::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\core\coreabc.v","FALSE","FALSE"
SUBBLOCK "SF_Zi1_COREABC_0_APBModel::work","component\work\SF_Zi1\COREABC_0\rtl\vlog\test\apbmodel.v","FALSE","TRUE"
ENDLIST
LIST "testbench::work","component\work\SF_Zi1\testbench.v","FALSE","TRUE"
SUBBLOCK "SF_Zi1::work","component\work\SF_Zi1\SF_Zi1.v","TRUE","FALSE"
ENDLIST
LIST "testbench::work","component\work\SF_Zi1_MSS\testbench.v","FALSE","TRUE"
SUBBLOCK "SF_Zi1_MSS::work","component\work\SF_Zi1_MSS\SF_Zi1_MSS.v","TRUE","FALSE"
ENDLIST
LIST "CoreAPB3::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v","FALSE","FALSE"
SUBBLOCK "COREAPB3_MUXPTOB3::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3_muxptob3.v","FALSE","FALSE"
ENDLIST
LIST "COREAPB3_MUXPTOB3::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3_muxptob3.v","FALSE","FALSE"
ENDLIST
LIST "BFM_APB::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_apb.v","FALSE","TRUE"
SUBBLOCK "BFM_MAIN::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_main.v","FALSE","TRUE"
SUBBLOCK "BFMA1l1OII::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_ahbtoapb.v","FALSE","TRUE"
ENDLIST
LIST "BFM_APBSLAVE::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_apbslave.v","FALSE","TRUE"
SUBBLOCK "BFM_APBSLAVEEXT::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_apbslaveext.v","FALSE","TRUE"
ENDLIST
LIST "BFM_APBSLAVEEXT::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_apbslaveext.v","FALSE","TRUE"
ENDLIST
LIST "BFM_MAIN::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_main.v","FALSE","TRUE"
ENDLIST
LIST "BFMA1l1OII::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_ahbtoapb.v","FALSE","TRUE"
ENDLIST
LIST "testbench::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\test\user\testbench.v","FALSE","TRUE"
SUBBLOCK "CoreAPB3::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v","FALSE","FALSE"
SUBBLOCK "BFM_APB::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_apb.v","FALSE","TRUE"
SUBBLOCK "BFM_APBSLAVE::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\amba_bfm\bfm_apbslave.v","FALSE","TRUE"
ENDLIST
ENDLIST
LIST ActiveTestBenchList
LIST "SF_Zi1::work"
ACTIVETESTBENCH "","","FALSE"
ENDLIST
ENDLIST
