@N: CD630 :".\gentmp0a06908":4:7:4:9|Synthesizing work.top.gen 
@N: CD630 :"syng0a06908":1366:7:1366:9|Synthesizing work.inc.finc 
@W: CD638 :"syng0a06908":1387:9:1387:13|Signal carry is undriven 
@W: CD638 :"syng0a06908":1388:9:1388:12|Signal asup is undriven 
@W: CD638 :"syng0a06908":1388:15:1388:18|Signal ssup is undriven 
@N: CD630 :"syng0a06908":357:7:357:22|Synthesizing work.dwact_bl_fincdec.impl1 
@W: CD280 :"syng0a06908":369:12:369:14|Unbound component INV mapped to black box
@W: CD796 :"syng0a06908":474:9:474:9|Bit 5 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 6 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 7 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 8 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 9 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 10 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 11 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 12 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 13 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 14 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 15 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 16 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 17 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 18 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 19 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 20 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 21 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 22 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 23 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 24 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 25 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 26 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 27 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 28 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 29 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 30 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 31 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 32 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 33 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0a06908":474:9:474:9|Bit 34 of signal e is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@N: CD630 :"syng0a06908":191:7:191:20|Synthesizing work.dwact_tl_l2xor.impl1 
@W: CD280 :"syng0a06908":207:12:207:15|Unbound component AND3 mapped to black box
@W: CD280 :"syng0a06908":230:12:230:15|Unbound component XOR2 mapped to black box
@N: CD630 :"syng0a06908":230:12:230:15|Synthesizing work.xor2.syn_black_box 
Post processing for work.xor2.syn_black_box
@N: CD630 :"syng0a06908":207:12:207:15|Synthesizing work.and3.syn_black_box 
Post processing for work.and3.syn_black_box
Post processing for work.dwact_tl_l2xor.impl1
@N: CD630 :"syng0a06908":267:7:267:19|Synthesizing work.dwact_tl_and3.impl1 
Post processing for work.dwact_tl_and3.impl1
@N: CD630 :"syng0a06908":120:7:120:19|Synthesizing work.dwact_tl_and2.impl1 
@W: CD280 :"syng0a06908":137:10:137:13|Unbound component AND2 mapped to black box
@N: CD630 :"syng0a06908":137:10:137:13|Synthesizing work.and2.syn_black_box 
Post processing for work.and2.syn_black_box
Post processing for work.dwact_tl_and2.impl1
@N: CD630 :"syng0a06908":305:7:305:19|Synthesizing work.dwact_bl_xor2.impl1 
Post processing for work.dwact_bl_xor2.impl1
@N: CD630 :"syng0a06908":369:12:369:14|Synthesizing work.inv.syn_black_box 
Post processing for work.inv.syn_black_box
@N: CD630 :"syng0a06908":55:7:55:18|Synthesizing work.dwact_tl_vcc.impl1 
@W: CD280 :"syng0a06908":68:13:68:15|Unbound component VCC mapped to black box
@N: CD630 :"syng0a06908":68:13:68:15|Synthesizing work.vcc.syn_black_box 
Post processing for work.vcc.syn_black_box
Post processing for work.dwact_tl_vcc.impl1
Post processing for work.dwact_bl_fincdec.impl1
Post processing for work.inc.finc
Post processing for work.top.gen
