Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00
Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved
Product Version E-2010.09A-1
Reading constraint file: F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\mss_tshell_syn.sdc
@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 

@W: MO111 :"f:\zeroization\sf_zi1\component\work\sf_zi1_mss\mss_ccc_0\sf_zi1_mss_tmp_mss_ccc_0_mss_ccc.v":62:7:62:18|tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"f:\zeroization\sf_zi1\component\work\sf_zi1_mss\mss_ccc_0\sf_zi1_mss_tmp_mss_ccc_0_mss_ccc.v":63:7:63:20|tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"f:\zeroization\sf_zi1\component\work\sf_zi1_mss\mss_ccc_0\sf_zi1_mss_tmp_mss_ccc_0_mss_ccc.v":64:7:64:18|tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module SF_Zi1_MSS_tmp_MSS_CCC_0_MSS_CCC) 

Available hyper_sources - for debug and ip models
	None Found

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB)

@N:"f:\zeroization\sf_zi1\hdl\iap.v":317:0:317:5|Found counter in view:work.iap_Z2(verilog) inst drLength[7:0]
Encoding state machine work.iap_Z2(verilog)-state[4:0]
original code -> new code
   000 -> 00001
   001 -> 00010
   010 -> 00100
   011 -> 01000
   100 -> 10000
Encoding state machine work.iap_Z2(verilog)-currentState[15:0]
original code -> new code
   0000 -> 0000
   0001 -> 0001
   0010 -> 0010
   0011 -> 0011
   0100 -> 0100
   0101 -> 0101
   0110 -> 0110
   0111 -> 0111
   1000 -> 1000
   1001 -> 1001
   1010 -> 1010
   1011 -> 1011
   1100 -> 1100
   1101 -> 1101
   1110 -> 1110
   1111 -> 1111
@N: MF176 |Default generator successful 
@N: MO106 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\instructions.v":142:4:142:7|Found ROM, 'genblk19\.UROM\.UROM.doins[57:0]', 296 words by 58 bits 
Encoding state machine work.SF_Zi1_COREABC_0_COREABC_Z3(verilog)-ICYCLE[3:0]
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N: MF176 |Default generator successful 
@N: MF176 |Default generator successful 
@N: MF176 |Default generator successful 
@N: MF238 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":985:35:985:61|Found 4 bit incrementor, 'un1_STKPTRP1[3:0]'
@N: MF238 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":253:34:253:42|Found 9 bit incrementor, 'un1_SMADDR[8:0]'
@W: MO129 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Sequential instance COREABC_0.genblk19.UROM.INSTR_SLOT[1] has been reduced to a combinational gate by constant propagation
@W: MO129 :"f:\zeroization\sf_zi1\component\work\sf_zi1\coreabc_0\rtl\vlog\core\coreabc.v":468:12:468:17|Sequential instance COREABC_0.genblk19.UROM.INSTR_ADDR[9] has been reduced to a combinational gate by constant propagation
Finished factoring (Time elapsed 0h:00m:02s; Memory used current: 80MB peak: 81MB)

@N: BN116 :"f:\zeroization\sf_zi1\hdl\iap.v":317:0:317:5|Removing sequential instance iap_0.MOSI of view:PrimLib.dff(prim) because there are no references to its outputs 
@N: BN116 :"f:\zeroization\sf_zi1\hdl\iap.v":317:0:317:5|Removing sequential instance iap_0.SS[0] of view:PrimLib.dffs(prim) because there are no references to its outputs 
@N: BN116 :"f:\zeroization\sf_zi1\hdl\iap.v":317:0:317:5|Removing sequential instance iap_0.sckEn of view:PrimLib.dffr(prim) because there are no references to its outputs 
Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:02s; Memory used current: 79MB peak: 81MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:03s; Memory used current: 83MB peak: 84MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:03s; Memory used current: 84MB peak: 84MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:03s; Memory used current: 84MB peak: 85MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:03s; Memory used current: 84MB peak: 85MB)

Finished preparing to map (Time elapsed 0h:00m:04s; Memory used current: 71MB peak: 87MB)


High Fanout Net Report
**********************

Driver Instance / Pin Name                            Fanout, notes                 
------------------------------------------------------------------------------------
iap_0.state[4] / Q                                    33                            
COREABC_0.SMADDR[0] / Q                               60                            
COREABC_0.SMADDR[1] / Q                               59                            
COREABC_0.SMADDR[2] / Q                               62                            
COREABC_0.SMADDR[3] / Q                               61                            
COREABC_0.SMADDR[4] / Q                               62                            
COREABC_0.SMADDR[5] / Q                               45                            
COREABC_0.SMADDR[6] / Q                               30                            
COREABC_0.SMADDR[8] / Q                               28                            
COREABC_0.genblk19.UROM.INSTR_SCMD[0] / Q             27                            
COREABC_0.RSTSYNC2 / Q                                94 : 83 asynchronous set/reset
COREABC_0.genblk19.UROM.UROM.doins_i_o2_3[1] / Y      25                            
COREABC_0.genblk19.UROM.UROM.doins_0_a2_30[0] / Y     30                            
COREABC_0.genblk19.UROM.UROM.doins_i_o2_2[1] / Y      36                            
COREABC_0.genblk19.UROM.UROM.doins_0_o2_4[13] / Y     34                            
COREABC_0.genblk19.UROM.UROM.doins_0_o2[2] / Y        38                            
COREABC_0.genblk19.UROM.UROM.doins_0_a2_28[0] / Y     27                            
COREABC_0.genblk19.UROM.UROM.doins_0_o2[15] / Y       40                            
COREABC_0.genblk19.UROM.UROM.doins_0_o2_1[4] / Y      29                            
COREABC_0.genblk19.UROM.UROM.doins_i_a2_36[1] / Y     27                            
COREABC_0.genblk19.UROM.UROM.doins_i_o2_4[1] / Y      28                            
====================================================================================

@N: FP130 |Promoting Net TRSTB_c on CLKINT  I_461 
@N: FP130 |Promoting Net COREABC_0.SMADDR[2] on CLKINT  I_462 
@N: FP130 |Promoting Net COREABC_0.SMADDR[4] on CLKINT  I_463 
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_i_o2_4[1], fanout 28 segments 2
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_i_a2_36[1], fanout 27 segments 2
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_0_o2_1[4], fanout 29 segments 2
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_0_o2[15], fanout 40 segments 2
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_0_a2_28[0], fanout 27 segments 2
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_0_o2[2], fanout 38 segments 2
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_0_o2_4[13], fanout 34 segments 2
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_i_o2_2[1], fanout 36 segments 2
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_0_a2_30[0], fanout 30 segments 2
Replicating Combinational Instance COREABC_0.genblk19.UROM.UROM.doins_i_o2_3[1], fanout 25 segments 2
Replicating Sequential Instance COREABC_0.genblk19.UROM.INSTR_SCMD[0], fanout 27 segments 2
Replicating Sequential Instance COREABC_0.SMADDR[8], fanout 29 segments 2
Replicating Sequential Instance COREABC_0.SMADDR[6], fanout 31 segments 2
Replicating Sequential Instance COREABC_0.SMADDR[5], fanout 45 segments 2
Replicating Sequential Instance COREABC_0.SMADDR[3], fanout 65 segments 3
Replicating Sequential Instance COREABC_0.SMADDR[1], fanout 63 segments 3
Replicating Sequential Instance COREABC_0.SMADDR[0], fanout 60 segments 3
Replicating Sequential Instance iap_0.state[4], fanout 33 segments 2
Finished technology mapping (Time elapsed 0h:00m:04s; Memory used current: 84MB peak: 87MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:04s; Memory used current: 84MB peak: 87MB)


Added 0 Buffers
Added 21 Cells via replication
	Added 11 Sequential Cells via replication
	Added 10 Combinational Cells via replication
Finished restoring hierarchy (Time elapsed 0h:00m:04s; Memory used current: 84MB peak: 87MB)

Writing Analyst data base F:\zeroization\SF_Zi1\synthesis\SF_Zi1.srm
Finished Writing Netlist Databases (Time elapsed 0h:00m:04s; Memory used current: 83MB peak: 87MB)

Writing EDIF Netlist and constraint files
E-2010.09A-1
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:05s; Memory used current: 84MB peak: 87MB)

@W: MT420 |Found inferred clock SF_Zi1_MSS|MSS_ADLIB_INST_EMCCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:SF_Zi1_MSS_0.MSS_ADLIB_INST_EMCCLK"

Found clock FAB_CLK with period 50.00ns 
Found clock FCLK with period 50.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Thu Jan 05 19:36:32 2012
#


Top view:               SF_Zi1
Library name:           smartfusion
Operating conditions:   COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree )
Requested Frequency:    20.0 MHz
Wire load mode:         top
Wire load model:        smartfusion
Paths requested:        5
Constraint File(s):    F:\zeroization\SF_Zi1\component\work\SF_Zi1_MSS\mss_tshell_syn.sdc
                       
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: 5.801

                   Requested     Estimated     Requested     Estimated               Clock        Clock      
Starting Clock     Frequency     Frequency     Period        Period        Slack     Type         Group      
-------------------------------------------------------------------------------------------------------------
FAB_CLK            20.0 MHz      26.0 MHz      50.000        38.397        5.801     declared     clk_group_0
FCLK               20.0 MHz      NA            50.000        NA            NA        declared     clk_group_0
=============================================================================================================





Clock Relationships
*******************

Clocks             |    rise  to  rise    |    fall  to  fall    |    rise  to  fall    |    fall  to  rise 
------------------------------------------------------------------------------------------------------------
Starting  Ending   |  constraint  slack   |  constraint  slack   |  constraint  slack   |  constraint  slack
------------------------------------------------------------------------------------------------------------
FAB_CLK   FAB_CLK  |  50.000      18.829  |  50.000      46.712  |  25.000      14.169  |  25.000      5.801
============================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: FAB_CLK
====================================



Starting Points with Worst Slack
********************************

                          Starting                                               Arrival           
Instance                  Reference     Type         Pin     Net                 Time        Slack 
                          Clock                                                                    
---------------------------------------------------------------------------------------------------
iap_0.TMS                 FAB_CLK       DFN0E0P0     Q       TMS_c               0.653       5.801 
iap_0.targetState[2]      FAB_CLK       DFN1E1       Q       targetState[2]      0.737       14.169
iap_0.currentState[1]     FAB_CLK       DFN1P0       Q       currentState[1]     0.737       14.241
iap_0.currentState[0]     FAB_CLK       DFN1P0       Q       currentState[0]     0.737       14.270
iap_0.currentState[2]     FAB_CLK       DFN1P0       Q       currentState[2]     0.737       14.293
iap_0.currentState[3]     FAB_CLK       DFN1P0       Q       currentState[3]     0.737       14.296
iap_0.targetState[1]      FAB_CLK       DFN1E1       Q       targetState[1]      0.737       14.689
iap_0.targetState[3]      FAB_CLK       DFN1E1       Q       targetState[3]      0.737       14.745
iap_0.targetState[0]      FAB_CLK       DFN1E1       Q       targetState[0]      0.737       14.901
iap_0.tckCnt[3]           FAB_CLK       DFN1         Q       tckCnt[3]           0.737       15.513
===================================================================================================


Ending Points with Worst Slack
******************************

                    Starting                                          Required           
Instance            Reference     Type       Pin     Net              Time         Slack 
                    Clock                                                                
-----------------------------------------------------------------------------------------
iap_0.tckCnt[4]     FAB_CLK       DFN1       D       tckCnt_15[4]     24.427       5.801 
iap_0.tckCnt[5]     FAB_CLK       DFN1       D       tckCnt_15[5]     24.427       6.954 
iap_0.tckCnt[6]     FAB_CLK       DFN1       D       tckCnt_15[6]     24.427       6.954 
iap_0.tckCnt[3]     FAB_CLK       DFN1       D       tckCnt_15[3]     24.427       6.999 
iap_0.tckCnt[1]     FAB_CLK       DFN1       D       tckCnt_15[1]     24.427       7.836 
iap_0.tckCnt[2]     FAB_CLK       DFN1       D       tckCnt_15[2]     24.461       7.837 
iap_0.tckCnt[7]     FAB_CLK       DFN1       D       tckCnt_15[7]     24.461       7.878 
iap_0.tckCnt[0]     FAB_CLK       DFN1       D       tckCnt_15[0]     24.427       8.008 
iap_0.state[1]      FAB_CLK       DFN1C0     D       N_40             24.427       12.767
iap_0.state[4]      FAB_CLK       DFN1P0     D       N_193            24.461       13.320
=========================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      25.000
    - Setup time:                            0.573
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         24.427

    - Propagation time:                      18.625
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     5.801

    Number of logic level(s):                12
    Starting point:                          iap_0.TMS / Q
    Ending point:                            iap_0.tckCnt[4] / D
    The start point is clocked by            FAB_CLK [falling] on pin CLK
    The end   point is clocked by            FAB_CLK [rising] on pin CLK

Instance / Net                                            Pin      Pin               Arrival     No. of    
Name                                         Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------
iap_0.TMS                                    DFN0E0P0     Q        Out     0.653     0.653       -         
TMS_c                                        Net          -        -       2.037     -           13        
iap_0.TMS_RNIA3KH                            OR2A         A        In      -         2.690       -         
iap_0.TMS_RNIA3KH                            OR2A         Y        Out     0.466     3.156       -         
N_546                                        Net          -        -       0.386     -           2         
iap_0.currentState_RNIR7LM[0]                OR2A         B        In      -         3.542       -         
iap_0.currentState_RNIR7LM[0]                OR2A         Y        Out     0.514     4.056       -         
N_887                                        Net          -        -       0.322     -           1         
iap_0.currentState_RNIGNV32[0]               OAI1         C        In      -         4.378       -         
iap_0.currentState_RNIGNV32[0]               OAI1         Y        Out     0.655     5.033       -         
currentState_ns[1]                           Net          -        -       0.386     -           2         
iap_0.targetState_RNI2C674[1]                OA1A         A        In      -         5.419       -         
iap_0.targetState_RNI2C674[1]                OA1A         Y        Out     0.933     6.352       -         
tckEn14_NE_8                                 Net          -        -       0.322     -           1         
iap_0.targetState_RNIBMFHD[1]                OR3C         C        In      -         6.673       -         
iap_0.targetState_RNIBMFHD[1]                OR3C         Y        Out     0.666     7.339       -         
tckEn15                                      Net          -        -       0.386     -           2         
iap_0.state_RNIELQ6F[1]                      AOI1         A        In      -         7.725       -         
iap_0.state_RNIELQ6F[1]                      AOI1         Y        Out     0.911     8.636       -         
N_227                                        Net          -        -       0.386     -           2         
iap_0.state_RNID5H5I[1]                      OR2B         B        In      -         9.021       -         
iap_0.state_RNID5H5I[1]                      OR2B         Y        Out     0.516     9.537       -         
un1_tckEn20_2                                Net          -        -       2.127     -           15        
iap_0.un1_tckEn20_4.ADD_8x8_fast_I0_CO1      NOR2A        B        In      -         11.665      -         
iap_0.un1_tckEn20_4.ADD_8x8_fast_I0_CO1      NOR2A        Y        Out     0.407     12.071      -         
N116                                         Net          -        -       0.806     -           3         
iap_0.un1_tckEn20_4.ADD_8x8_fast_I18_Y       OR2          B        In      -         12.878      -         
iap_0.un1_tckEn20_4.ADD_8x8_fast_I18_Y       OR2          Y        Out     0.514     13.392      -         
N149                                         Net          -        -       1.184     -           4         
iap_0.un1_tckEn20_4.ADD_8x8_fast_I40_Y_0     AX1B         B        In      -         14.576      -         
iap_0.un1_tckEn20_4.ADD_8x8_fast_I40_Y_0     AX1B         Y        Out     1.001     15.577      -         
un1_tckEn20_4[4]                             Net          -        -       0.806     -           3         
iap_0.tckCnt_RNO_2[4]                        AOI1B        A        In      -         16.383      -         
iap_0.tckCnt_RNO_2[4]                        AOI1B        Y        Out     0.933     17.317      -         
tckCnt_15_iv_0_0_3[4]                        Net          -        -       0.322     -           1         
iap_0.tckCnt_RNO[4]                          OR3C         C        In      -         17.638      -         
iap_0.tckCnt_RNO[4]                          OR3C         Y        Out     0.666     18.304      -         
tckCnt_15[4]                                 Net          -        -       0.322     -           1         
iap_0.tckCnt[4]                              DFN1         D        In      -         18.625      -         
===========================================================================================================
Total path delay (propagation time + setup) of 19.199 is 9.409(49.0%) logic and 9.790(51.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Target Part: A2F200M3F_FBGA484_STD
Report for cell SF_Zi1.verilog
  Core Cell usage:
              cell count     area count*area
              AND2    26      1.0       26.0
              AND3     8      1.0        8.0
               AO1    11      1.0       11.0
              AO13     3      1.0        3.0
              AO16     1      1.0        1.0
              AO18     5      1.0        5.0
              AO1A     3      1.0        3.0
              AO1B    15      1.0       15.0
              AO1C    16      1.0       16.0
              AO1D    14      1.0       14.0
              AOI1     9      1.0        9.0
             AOI1B    97      1.0       97.0
              AOI5     1      1.0        1.0
              AX1A     1      1.0        1.0
              AX1B     4      1.0        4.0
              AX1C     2      1.0        2.0
              AX1D     1      1.0        1.0
              AX1E     2      1.0        2.0
              AXO1     1      1.0        1.0
            CLKINT     3      0.0        0.0
               GND    10      0.0        0.0
               INV     2      1.0        2.0
              MAJ3    21      1.0       21.0
             MAJ3X     1      1.0        1.0
              MIN3     2      1.0        2.0
           MSS_CCC     1      0.0        0.0
               MX2    79      1.0       79.0
              MX2A     4      1.0        4.0
              MX2B    21      1.0       21.0
              MX2C     5      1.0        5.0
             NAND2    17      1.0       17.0
              NOR2   148      1.0      148.0
             NOR2A   137      1.0      137.0
             NOR2B    99      1.0       99.0
              NOR3    13      1.0       13.0
             NOR3A    28      1.0       28.0
             NOR3B    37      1.0       37.0
             NOR3C   165      1.0      165.0
               OA1    18      1.0       18.0
              OA1A    51      1.0       51.0
              OA1B    11      1.0       11.0
              OA1C     7      1.0        7.0
              OAI1    30      1.0       30.0
               OR2    95      1.0       95.0
              OR2A   168      1.0      168.0
              OR2B   166      1.0      166.0
               OR3    43      1.0       43.0
              OR3A    82      1.0       82.0
              OR3B    68      1.0       68.0
              OR3C    64      1.0       64.0
             RCOSC     1      0.0        0.0
               VCC    10      0.0        0.0
              XA1A     2      1.0        2.0
              XA1B     1      1.0        1.0
              XA1C     1      1.0        1.0
              XAI1    26      1.0       26.0
             XAI1A     3      1.0        3.0
             XNOR2    14      1.0       14.0
             XNOR3    17      1.0       17.0
               XO1     1      1.0        1.0
              XOR2    53      1.0       53.0
              XOR3     3      1.0        3.0
              ZOR3     1      1.0        1.0


          DFN0E0P0     1      1.0        1.0
          DFN0E1P0     1      1.0        1.0
              DFN1    41      1.0       41.0
            DFN1C0    11      1.0       11.0
          DFN1E0C0    17      1.0       17.0
            DFN1E1    20      1.0       20.0
          DFN1E1C0    34      1.0       34.0
            DFN1P0    31      1.0       31.0
           MSS_APB     1      0.0        0.0
         RAM512X18     1      0.0        0.0
                   -----          ----------
             TOTAL  2107              2080.0


  IO Cell usage:
              cell count
             INBUF     1
         INBUF_MSS     2
            OUTBUF    12
        OUTBUF_MSS     1
                   -----
             TOTAL    16


Core Cells         : 2080 of 4608 (45%)
IO Cells           : 16

  RAM/ROM Usage Summary
Block Rams : 1 of 8 (12%)

Mapper successful!
Process took 0h:00m:05s realtime, 0h:00m:05s cputime
# Thu Jan 05 19:36:32 2012

###########################################################]
