Timing Report Max Delay Analysis

SmartTime Version v10.1 SP1
Actel Corporation - Actel Designer Software Release v10.1 SP1 (Version 10.1.1.6)
Copyright (c) 1989-2012
Date: Mon Nov 19 10:32:50 2012


Design: SF_Zi1
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                36.566
Frequency (MHz):            27.348
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        0.297
External Hold (ns):         1.724
Min Clock-To-Out (ns):      6.762
Max Clock-To-Out (ns):      13.790

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        -5.206
External Hold (ns):         4.012
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               SF_Zi1_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      6.723
Max Clock-To-Out (ns):      11.993

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        iap_0/TMS:CLK
  To:                          iap_0/tckCnt[7]:D
  Delay (ns):                  16.666
  Slack (ns):                  6.717
  Arrival (ns):                23.659
  Required (ns):               30.376
  Setup (ns):                  0.522
  Minimum Period (ns):         36.566

Path 2
  From:                        iap_0/TMS:CLK
  To:                          iap_0/tckCnt[6]:D
  Delay (ns):                  15.847
  Slack (ns):                  7.536
  Arrival (ns):                22.840
  Required (ns):               30.376
  Setup (ns):                  0.522
  Minimum Period (ns):         34.928

Path 3
  From:                        iap_0/TMS:CLK
  To:                          iap_0/tckCnt[5]:D
  Delay (ns):                  15.439
  Slack (ns):                  7.944
  Arrival (ns):                22.432
  Required (ns):               30.376
  Setup (ns):                  0.522
  Minimum Period (ns):         34.112

Path 4
  From:                        iap_0/TMS:CLK
  To:                          iap_0/tckCnt[3]:D
  Delay (ns):                  15.233
  Slack (ns):                  8.186
  Arrival (ns):                22.226
  Required (ns):               30.412
  Setup (ns):                  0.490
  Minimum Period (ns):         33.628

Path 5
  From:                        iap_0/TMS:CLK
  To:                          iap_0/tckCnt[4]:D
  Delay (ns):                  14.734
  Slack (ns):                  8.698
  Arrival (ns):                21.727
  Required (ns):               30.425
  Setup (ns):                  0.490
  Minimum Period (ns):         32.604


Expanded Path 1
  From: iap_0/TMS:CLK
  To: iap_0/tckCnt[7]:D
  data required time                             30.376
  data arrival time                          -   23.659
  slack                                          6.717
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (f)
               +     5.249          Clock generation
  5.249
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (f)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (f)
               +     0.680          net: FAB_CLK
  5.929                        iap_0/tckEn_RNIFJOL:B (f)
               +     0.588          cell: ADLIB:OR2A
  6.517                        iap_0/tckEn_RNIFJOL:Y (f)
               +     0.476          net: TCK_c
  6.993                        iap_0/TMS:CLK (f)
               +     0.671          cell: ADLIB:DFN0E0P0
  7.664                        iap_0/TMS:Q (f)
               +     1.252          net: TMS_c
  8.916                        iap_0/TMS_RNIMUIK:A (f)
               +     0.489          cell: ADLIB:OR2
  9.405                        iap_0/TMS_RNIMUIK:Y (f)
               +     0.360          net: iap_0/N_707
  9.765                        iap_0/currentState_RNI73K11[0]:B (f)
               +     0.445          cell: ADLIB:NOR2A
  10.210                       iap_0/currentState_RNI73K11[0]:Y (r)
               +     0.296          net: iap_0/N_712
  10.506                       iap_0/TMS_RNIKFAT2:C (r)
               +     0.698          cell: ADLIB:AO1
  11.204                       iap_0/TMS_RNIKFAT2:Y (r)
               +     0.369          net: iap_0/currentState_ns[0]
  11.573                       iap_0/targetState_RNI2RMH8[0]:B (r)
               +     0.582          cell: ADLIB:XO1
  12.155                       iap_0/targetState_RNI2RMH8[0]:Y (r)
               +     0.409          net: iap_0/tckEn14_NE_1
  12.564                       iap_0/state_RNICOS0E_0[1]:B (r)
               +     0.829          cell: ADLIB:OA1
  13.393                       iap_0/state_RNICOS0E_0[1]:Y (r)
               +     1.177          net: iap_0/N_188
  14.570                       iap_0/state_RNIVRTCP_0[1]:C (r)
               +     0.622          cell: ADLIB:NOR3
  15.192                       iap_0/state_RNIVRTCP_0[1]:Y (f)
               +     0.615          net: iap_0/state_RNIVRTCP_0[1]
  15.807                       iap_0/un1_tckCnt_I_15:B (f)
               +     0.853          cell: ADLIB:XOR2
  16.660                       iap_0/un1_tckCnt_I_15:Y (r)
               +     0.368          net: iap_0/DWACT_ADD_CI_0_pog_array_0_2[0]
  17.028                       iap_0/un1_tckCnt_I_47:B (r)
               +     0.470          cell: ADLIB:AND2
  17.498                       iap_0/un1_tckCnt_I_47:Y (r)
               +     0.590          net: iap_0/DWACT_ADD_CI_0_pog_array_1[0]
  18.088                       iap_0/un1_tckCnt_I_36:A (r)
               +     0.437          cell: ADLIB:AO1
  18.525                       iap_0/un1_tckCnt_I_36:Y (r)
               +     0.711          net: iap_0/DWACT_ADD_CI_0_g_array_2[0]
  19.236                       iap_0/un1_tckCnt_I_39:B (r)
               +     0.516          cell: ADLIB:AO1
  19.752                       iap_0/un1_tckCnt_I_39:Y (r)
               +     0.369          net: iap_0/DWACT_ADD_CI_0_g_array_11[0]
  20.121                       iap_0/un1_tckCnt_I_45:B (r)
               +     0.516          cell: ADLIB:AO1
  20.637                       iap_0/un1_tckCnt_I_45:Y (r)
               +     0.306          net: iap_0/DWACT_ADD_CI_0_g_array_12_2[0]
  20.943                       iap_0/un1_tckCnt_I_34:C (r)
               +     0.897          cell: ADLIB:XOR3
  21.840                       iap_0/un1_tckCnt_I_34:Y (f)
               +     0.282          net: iap_0/I_34
  22.122                       iap_0/tckCnt_RNO_0[7]:C (f)
               +     0.369          cell: ADLIB:OA1A
  22.491                       iap_0/tckCnt_RNO_0[7]:Y (f)
               +     0.296          net: iap_0/N_78
  22.787                       iap_0/tckCnt_RNO[7]:C (f)
               +     0.576          cell: ADLIB:AO1
  23.363                       iap_0/tckCnt_RNO[7]:Y (f)
               +     0.296          net: iap_0/tckCnt_15[7]
  23.659                       iap_0/tckCnt[7]:D (f)
                                    
  23.659                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_ccc_gla1
               +     0.000          Clock source
  25.000                       SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  30.249
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  30.249                       SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  30.249                       SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.649          net: FAB_CLK
  30.898                       iap_0/tckCnt[7]:CLK (r)
               -     0.522          Library setup time: ADLIB:DFN1
  30.376                       iap_0/tckCnt[7]:D
                                    
  30.376                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        TDO
  To:                          iap_0/datareg[15]:D
  Delay (ns):                  5.721
  Slack (ns):
  Arrival (ns):                5.721
  Required (ns):
  Setup (ns):                  0.490
  External Setup (ns):         0.297


Expanded Path 1
  From: TDO
  To: iap_0/datareg[15]:D
  data required time                             N/C
  data arrival time                          -   5.721
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        TDO (r)
               +     0.000          net: TDO
  0.000                        TDO_pad/U0/U0:PAD (r)
               +     0.935          cell: ADLIB:IOPAD_IN
  0.935                        TDO_pad/U0/U0:Y (r)
               +     0.000          net: TDO_pad/U0/NET1
  0.935                        TDO_pad/U0/U1:YIN (r)
               +     0.039          cell: ADLIB:IOIN_IB
  0.974                        TDO_pad/U0/U1:Y (r)
               +     2.017          net: TDO_c
  2.991                        iap_0/datareg_RNO_0[15]:A (r)
               +     0.538          cell: ADLIB:NOR2A
  3.529                        iap_0/datareg_RNO_0[15]:Y (r)
               +     1.280          net: iap_0/datareg_17_1_a2_0_0[15]
  4.809                        iap_0/datareg_RNO[15]:A (r)
               +     0.606          cell: ADLIB:MX2
  5.415                        iap_0/datareg_RNO[15]:Y (r)
               +     0.306          net: iap_0/datareg_17[15]
  5.721                        iap_0/datareg[15]:D (r)
                                    
  5.721                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  N/C
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.665          net: FAB_CLK
  N/C                          iap_0/datareg[15]:CLK (r)
               -     0.490          Library setup time: ADLIB:DFN1E1
  N/C                          iap_0/datareg[15]:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        iap_0/TDI:CLK
  To:                          TDI
  Delay (ns):                  6.822
  Slack (ns):
  Arrival (ns):                13.790
  Required (ns):
  Clock to Out (ns):           13.790

Path 2
  From:                        iap_0/tckEn:CLK
  To:                          TCK
  Delay (ns):                  7.580
  Slack (ns):
  Arrival (ns):                13.477
  Required (ns):
  Clock to Out (ns):           13.477

Path 3
  From:                        COREABC_0/RSTSYNC2:CLK
  To:                          TRSTB
  Delay (ns):                  7.136
  Slack (ns):
  Arrival (ns):                13.051
  Required (ns):
  Clock to Out (ns):           13.051

Path 4
  From:                        iap_0/TMS:CLK
  To:                          TMS
  Delay (ns):                  5.731
  Slack (ns):
  Arrival (ns):                12.724
  Required (ns):
  Clock to Out (ns):           12.724

Path 5
  From:                        COREABC_0/IO_OUT[0]:CLK
  To:                          IO_OUT[0]
  Delay (ns):                  6.703
  Slack (ns):
  Arrival (ns):                12.605
  Required (ns):
  Clock to Out (ns):           12.605


Expanded Path 1
  From: iap_0/TDI:CLK
  To: TDI
  data required time                             N/C
  data arrival time                          -   13.790
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (f)
               +     5.249          Clock generation
  5.249
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (f)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (f)
               +     0.680          net: FAB_CLK
  5.929                        iap_0/tckEn_RNIFJOL:B (f)
               +     0.588          cell: ADLIB:OR2A
  6.517                        iap_0/tckEn_RNIFJOL:Y (f)
               +     0.451          net: TCK_c
  6.968                        iap_0/TDI:CLK (f)
               +     0.671          cell: ADLIB:DFN0E1P0
  7.639                        iap_0/TDI:Q (f)
               +     2.370          net: TDI_c
  10.009                       TDI_pad/U0/U1:D (f)
               +     0.530          cell: ADLIB:IOTRI_OB_EB
  10.539                       TDI_pad/U0/U1:DOUT (f)
               +     0.000          net: TDI_pad/U0/NET1
  10.539                       TDI_pad/U0/U0:D (f)
               +     3.251          cell: ADLIB:IOPAD_TRI
  13.790                       TDI_pad/U0/U0:PAD (f)
               +     0.000          net: TDI
  13.790                       TDI (f)
                                    
  13.790                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  N/C
                                    
  N/C                          TDI (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        COREABC_0/RSTSYNC2:CLK
  To:                          iap_0/TDI:PRE
  Delay (ns):                  3.161
  Slack (ns):                  22.621
  Arrival (ns):                9.076
  Required (ns):               31.697
  Recovery (ns):               0.271
  Minimum Period (ns):         4.758
  Skew (ns):                   -1.053

Path 2
  From:                        COREABC_0/RSTSYNC2:CLK
  To:                          iap_0/TMS:PRE
  Delay (ns):                  3.182
  Slack (ns):                  22.625
  Arrival (ns):                9.097
  Required (ns):               31.722
  Recovery (ns):               0.271
  Minimum Period (ns):         4.750
  Skew (ns):                   -1.078

Path 3
  From:                        COREABC_0/RSTSYNC2:CLK
  To:                          COREABC_0/URAM.UR/UG3.UR_xhdl12/Ram256x16_R0C0:RESET
  Delay (ns):                  3.415
  Slack (ns):                  45.042
  Arrival (ns):                9.330
  Required (ns):               54.372
  Recovery (ns):               1.780
  Minimum Period (ns):         4.958
  Skew (ns):                   -0.237

Path 4
  From:                        COREABC_0/RSTSYNC2:CLK
  To:                          COREABC_0/SMADDR[2]:PRE
  Delay (ns):                  3.186
  Slack (ns):                  46.525
  Arrival (ns):                9.101
  Required (ns):               55.626
  Recovery (ns):               0.271
  Minimum Period (ns):         3.475
  Skew (ns):                   0.018

Path 5
  From:                        COREABC_0/RSTSYNC2:CLK
  To:                          COREABC_0/SMADDR[8]:PRE
  Delay (ns):                  3.186
  Slack (ns):                  46.525
  Arrival (ns):                9.101
  Required (ns):               55.626
  Recovery (ns):               0.271
  Minimum Period (ns):         3.475
  Skew (ns):                   0.018


Expanded Path 1
  From: COREABC_0/RSTSYNC2:CLK
  To: iap_0/TDI:PRE
  data required time                             31.697
  data arrival time                          -   9.076
  slack                                          22.621
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.666          net: FAB_CLK
  5.915                        COREABC_0/RSTSYNC2:CLK (r)
               +     0.528          cell: ADLIB:DFN1C0
  6.443                        COREABC_0/RSTSYNC2:Q (r)
               +     1.288          net: COREABC_0/RSTSYNC2
  7.731                        COREABC_0/RSTSYNC2_RNIS3FD/U_CLKSRC:A (r)
               +     0.699          cell: ADLIB:CLKSRC
  8.430                        COREABC_0/RSTSYNC2_RNIS3FD/U_CLKSRC:Y (r)
               +     0.646          net: TRSTB_c
  9.076                        iap_0/TDI:PRE (r)
                                    
  9.076                        data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_ccc_gla1
               +     0.000          Clock source
  25.000                       SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (f)
               +     5.249          Clock generation
  30.249
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  30.249                       SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (f)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  30.249                       SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (f)
               +     0.680          net: FAB_CLK
  30.929                       iap_0/tckEn_RNIFJOL:B (f)
               +     0.588          cell: ADLIB:OR2A
  31.517                       iap_0/tckEn_RNIFJOL:Y (f)
               +     0.451          net: TCK_c
  31.968                       iap_0/TDI:CLK (f)
               -     0.271          Library recovery time: ADLIB:DFN0E1P0
  31.697                       iap_0/TDI:PRE
                                    
  31.697                       data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

Path 1
  From:                        NSYSRESET
  To:                          COREABC_0/RSTSYNC2:CLR
  Delay (ns):                  1.310
  Slack (ns):
  Arrival (ns):                1.310
  Required (ns):
  Recovery (ns):               0.271
  External Recovery (ns):      -4.334

Path 2
  From:                        NSYSRESET
  To:                          COREABC_0/RSTSYNC1:CLR
  Delay (ns):                  1.305
  Slack (ns):
  Arrival (ns):                1.305
  Required (ns):
  Recovery (ns):               0.271
  External Recovery (ns):      -4.339


Expanded Path 1
  From: NSYSRESET
  To: COREABC_0/RSTSYNC2:CLR
  data required time                             N/C
  data arrival time                          -   1.310
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        NSYSRESET (r)
               +     0.000          net: NSYSRESET
  0.000                        NSYSRESET_pad/U0/U0:PAD (r)
               +     0.935          cell: ADLIB:IOPAD_IN
  0.935                        NSYSRESET_pad/U0/U0:Y (r)
               +     0.000          net: NSYSRESET_pad/U0/NET1
  0.935                        NSYSRESET_pad/U0/U1:YIN (r)
               +     0.039          cell: ADLIB:IOIN_IB
  0.974                        NSYSRESET_pad/U0/U1:Y (r)
               +     0.336          net: NSYSRESET_c
  1.310                        COREABC_0/RSTSYNC2:CLR (r)
                                    
  1.310                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  N/C
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.666          net: FAB_CLK
  N/C                          COREABC_0/RSTSYNC2:CLK (r)
               -     0.271          Library recovery time: ADLIB:DFN1C0
  N/C                          COREABC_0/RSTSYNC2:CLR


END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin SF_Zi1_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          SF_Zi1_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.937
  Slack (ns):
  Arrival (ns):                0.937
  Required (ns):
  Setup (ns):                  -2.139
  External Setup (ns):         -5.206


Expanded Path 1
  From: MSS_RESET_N
  To: SF_Zi1_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.937
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        SF_Zi1_MSS_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.937          cell: ADLIB:IOPAD_IN
  0.937                        SF_Zi1_MSS_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: SF_Zi1_MSS_0/MSS_RESET_0_MSS_RESET_N_Y
  0.937                        SF_Zi1_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.937                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  N/C
               +     0.459          net: SF_Zi1_MSS_0/GLA0
  N/C                          SF_Zi1_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -2.139          Library setup time: ADLIB:MSS_APB_IP
  N/C                          SF_Zi1_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain SF_Zi1_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          TCK
  Delay (ns):                  11.993
  Slack (ns):
  Arrival (ns):                11.993
  Required (ns):
  Clock to Out (ns):           11.993


Expanded Path 1
  From: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: TCK
  data required time                             N/C
  data arrival time                          -   11.993
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        SF_Zi1_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT
               +     0.000          Clock source
  0.000                        SF_Zi1_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT (r)
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/N_CLKA_RCOSC
  0.000                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     5.249          cell: ADLIB:MSS_CCC_IP
  5.249                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (f)
               +     0.000          net: SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (f)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        SF_Zi1_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (f)
               +     0.680          net: FAB_CLK
  5.929                        iap_0/tckEn_RNIFJOL:B (f)
               +     0.588          cell: ADLIB:OR2A
  6.517                        iap_0/tckEn_RNIFJOL:Y (f)
               +     1.695          net: TCK_c
  8.212                        TCK_pad/U0/U1:D (f)
               +     0.530          cell: ADLIB:IOTRI_OB_EB
  8.742                        TCK_pad/U0/U1:DOUT (f)
               +     0.000          net: TCK_pad/U0/NET1
  8.742                        TCK_pad/U0/U0:D (f)
               +     3.251          cell: ADLIB:IOPAD_TRI
  11.993                       TCK_pad/U0/U0:PAD (f)
               +     0.000          net: TCK
  11.993                       TCK (f)
                                    
  11.993                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT
               +     0.000          Clock source
  N/C                          SF_Zi1_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT (r)
                                    
  N/C                          TCK (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

