***************************************************************************
                               Status Report
                          Wed Jan 25 19:12:58 2012 ***************************************************************************

Product: Designer
Release: v10.0
Version: 10.0.9.37
File Name: C:\Documents and Settings\cherukupallyu\Desktop\POR_PPR_AGL1000_CNT\designer\impl3\top.adb
Design Name: top  Design State: compile
Last Saved: Wed Jan 25 19:12:48 2012

***** Device Data **************************************************

Family: IGLOO  Die: M1AGL1000V2  Package: 484 FBGA
Speed: STD  Voltage: 1.2

Restrict JTAG Pins: YES
Restrict Probe Pins: YES

Junction Temperature Range:   COM
Voltage Range:   COM

***** Import Variables *********************************************

Source File(s) Imported on Wed Jan 25 19:12:40 2012:
        C:\Documents and Settings\cherukupallyu\Desktop\POR_PPR_AGL1000_CNT\synthesis\top.edn


***** CAE Variables ************************************************

Back Annotation File: N/A


***** Bitstream Variables ******************************************

Bitstream File: N/A
     Lock Mode: OFF


***** Compile Variables ********************************************

Netlist PIN properties overwrite existing properties: 0

Compile Output:
=====================================================================
Parameters used to run compile:
===============================

Family      : IGLOO
Device      : M1AGL1000V2
Package     : 484 FBGA
Source      : C:\Documents and
Settings\cherukupallyu\Desktop\POR_PPR_AGL1000_CNT\synthesis\top.edn
Format      : EDIF
Topcell     : top
Speed grade : STD
Temp        : 0:25:70
Voltage     : 1.26:1.20:1.14

Keep Existing Physical Constraints : No
Keep Existing Timing Constraints   : Yes

pdc_abort_on_error                 : Yes
pdc_eco_display_unmatched_objects  : No
pdc_eco_max_warnings               : 10000

demote_globals                     : No
promote_globals                    : No
localclock_max_shared_instances    : 12
localclock_buffer_tree_max_fanout  : 12

combine_register                   : No
delete_buffer_tree                 : No

report_high_fanout_nets_limit      : 10

=====================================================================
Compile starts ...

Info: BLK007: No CoreConsole Database file imported for an M1 device.

Netlist Optimization Report
===========================

Optimized macros:
  - Dangling net drivers:   0
  - Buffers:                0
  - Inverters:              0
  - Tieoff:                 0
  - Logic combining:        1

    Total macros optimized  1

Warning: CMP503: Remapped 8 enable flip-flop(s) to a 2-tile implementation because the CLR/PRE
         pin on the enable flip-flop is not being driven by a global net.

There were 0 error(s) and 1 warning(s) in this design.
=====================================================================
Compile report:
===============

    CORE                       Used:     35  Total:  24576   (0.14%)
    IO (W/ clocks)             Used:      4  Total:    300   (1.33%)
    Differential IO            Used:      0  Total:     74   (0.00%)
    GLOBAL (Chip+Quadrant)     Used:      2  Total:     18   (11.11%)
    PLL                        Used:      0  Total:      1   (0.00%)
    RAM/FIFO                   Used:      0  Total:     32   (0.00%)
    Low Static ICC             Used:      0  Total:      1   (0.00%)
    FlashROM                   Used:      0  Total:      1   (0.00%)
    User JTAG                  Used:      0  Total:      1   (0.00%)

Global Information:

    Type            | Used   | Total
    ----------------|--------|--------------
    Chip global     | 2      | 6  (33.33%)*
    Quadrant global | 0      | 12 (0.00%)

    (*) Chip globals may be assigned to Quadrant globals using the Multi-View Navigator (MVN)
        or Physical Design Constraints (PDC).
        They may also be assigned to Quadrant globals automatically during Layout.

Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 24           | 24
    SEQ     | 11           | 11

I/O Function:

    Type                          | w/o register  | w/ register  | w/ DDR register
    ------------------------------|---------------|--------------|----------------
    Input I/O                     | 1             | 0            | 0
    Output I/O                    | 2             | 0            | 0
    Bidirectional I/O             | 1             | 0            | 0
    Differential Input I/O Pairs  | 0             | 0            | 0
    Differential Output I/O Pairs | 0             | 0            | 0

I/O Technology:

                                    |   Voltages    |             I/Os
    --------------------------------|-------|-------|-------|--------|--------------
    I/O Standard(s)                 | Vcci  | Vref  | Input | Output | Bidirectional
    --------------------------------|-------|-------|-------|--------|--------------
    LVCMOS33                        | 3.30v | N/A   | 0     | 0      | 1
    LVCMOS12                        | 1.20v | N/A   | 1     | 2      | 0

I/O Placement:

    Locked  :   0
    Placed  :   0
    UnPlaced:   4 ( 100.00% )

Net information report:
=======================

The following nets drive enable flip-flops that have been remapped to a 2-tile implementation:
    EffCnt  Type          Name
    --------------------------
    8       SET/RESET_NET Net   : DFN1C1_1_Q
                          Driver: DFN1C1_1

The following nets have been assigned to a chip global resource:
    Fanout  Type          Name
    --------------------------
    12      CLK_NET       Net   : CLK_out_c
                          Driver: CLKINT_1
                          Source: NETLIST
    2       SET/RESET_NET Net   : CLKINT_0_Y
                          Driver: CLKINT_0
                          Source: NETLIST

High fanout nets in the post compile netlist:
    Fanout  Type          Name
    --------------------------
    9       SET/RESET_NET Net   : DFN1C1_1_Q
                          Driver: DFN1C1_1
    8       INT_NET       Net   : mycounter_0/un5_count
                          Driver: mycounter_0/count_RNIRFEB[7]
    6       INT_NET       Net   : mycounter_0/count[3]
                          Driver: mycounter_0/count[3]/U1
    6       INT_NET       Net   : mycounter_0/count[0]
                          Driver: mycounter_0/count[0]/U1
    5       INT_NET       Net   : mycounter_0/count[4]
                          Driver: mycounter_0/count[4]/U1
    5       INT_NET       Net   : mycounter_0/count[6]
                          Driver: mycounter_0/count[6]/U1
    5       INT_NET       Net   : mycounter_0/count[1]
                          Driver: mycounter_0/count[1]/U1
    4       INT_NET       Net   : mycounter_0/count[5]
                          Driver: mycounter_0/count[5]/U1
    4       INT_NET       Net   : mycounter_0/DWACT_FINC_E[0]
                          Driver: mycounter_0/un8_count_G_2
    4       INT_NET       Net   : mycounter_0/count[2]
                          Driver: mycounter_0/count[2]/U1

Nets that are candidates for clock assignment and the resulting fanout:
    Fanout  Type          Name
    --------------------------
    9       SET/RESET_NET Net   : DFN1C1_1_Q
                          Driver: DFN1C1_1
    8       INT_NET       Net   : mycounter_0/un5_count
                          Driver: mycounter_0/count_RNIRFEB[7]
    6       INT_NET       Net   : mycounter_0/count[3]
                          Driver: mycounter_0/count[3]/U1
    6       INT_NET       Net   : mycounter_0/count[0]
                          Driver: mycounter_0/count[0]/U1
    5       INT_NET       Net   : mycounter_0/count[4]
                          Driver: mycounter_0/count[4]/U1
    5       INT_NET       Net   : mycounter_0/count[6]
                          Driver: mycounter_0/count[6]/U1
    5       INT_NET       Net   : mycounter_0/count[1]
                          Driver: mycounter_0/count[1]/U1
    4       INT_NET       Net   : mycounter_0/count[5]
                          Driver: mycounter_0/count[5]/U1
    4       INT_NET       Net   : mycounter_0/DWACT_FINC_E[0]
                          Driver: mycounter_0/un8_count_G_2
    4       INT_NET       Net   : mycounter_0/count[2]
                          Driver: mycounter_0/count[2]/U1
====================
Flash*Freeze report:
====================

The design does not use the Flash*Freeze feature.

====================


