Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Wed Jan 25 19:09:05 2012


Design: top
Family: IGLOO
Die: M1AGL1000V2
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               CLK
Period (ns):                10.626
Frequency (MHz):            94.109
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      4.342
Max Clock-To-Out (ns):      13.217

                            Input to Output
Min Delay (ns):             3.016
Max Delay (ns):             8.997

END SUMMARY
-----------------------------------------------------

Clock Domain CLK

SET Register to Register

Path 1
  From:                        mycounter_0/count[3]/U1:CLK
  To:                          mycounter_0/count[7]/U1:D
  Delay (ns):                  9.514
  Slack (ns):
  Arrival (ns):                14.799
  Required (ns):
  Setup (ns):                  1.112
  Minimum Period (ns):         10.626

Path 2
  From:                        mycounter_0/count[6]/U1:CLK
  To:                          mycounter_0/count[7]/U1:D
  Delay (ns):                  9.194
  Slack (ns):
  Arrival (ns):                14.479
  Required (ns):
  Setup (ns):                  1.112
  Minimum Period (ns):         10.306

Path 3
  From:                        mycounter_0/count[3]/U1:CLK
  To:                          mycounter_0/count[5]/U1:D
  Delay (ns):                  8.911
  Slack (ns):
  Arrival (ns):                14.196
  Required (ns):
  Setup (ns):                  1.169
  Minimum Period (ns):         10.080

Path 4
  From:                        mycounter_0/count[0]/U1:CLK
  To:                          mycounter_0/count[5]/U1:D
  Delay (ns):                  8.907
  Slack (ns):
  Arrival (ns):                14.192
  Required (ns):
  Setup (ns):                  1.112
  Minimum Period (ns):         10.019

Path 5
  From:                        mycounter_0/count[2]/U1:CLK
  To:                          mycounter_0/count[5]/U1:D
  Delay (ns):                  8.756
  Slack (ns):
  Arrival (ns):                14.041
  Required (ns):
  Setup (ns):                  1.112
  Minimum Period (ns):         9.868


Expanded Path 1
  From: mycounter_0/count[3]/U1:CLK
  To: mycounter_0/count[7]/U1:D
  data required time                             N/C
  data arrival time                          -   14.799
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        CLK
               +     0.000          Clock source
  0.000                        CLK (r)
               +     0.000          net: CLK
  0.000                        CLK_pad/U0/U0:PAD (r)
               +     0.978          cell: ADLIB:IOPAD_IN
  0.978                        CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  0.978                        CLK_pad/U0/U1:YIN (r)
               +     0.251          cell: ADLIB:IOIN_IB
  1.229                        CLK_pad/U0/U1:Y (r)
               +     0.656          net: CLK_c
  1.885                        CLKINT_1:A (r)
               +     1.982          cell: ADLIB:CLKINT
  3.867                        CLKINT_1:Y (r)
               +     1.418          net: CLK_out_c
  5.285                        mycounter_0/count[3]/U1:CLK (r)
               +     1.606          cell: ADLIB:DFN1C0
  6.891                        mycounter_0/count[3]/U1:Q (f)
               +     0.397          net: mycounter_0/count[3]
  7.288                        mycounter_0/un8_count_G_8_0_o2_1:B (f)
               +     1.473          cell: ADLIB:OR2B
  8.761                        mycounter_0/un8_count_G_8_0_o2_1:Y (r)
               +     0.377          net: mycounter_0/G_8_0_o2_1
  9.138                        mycounter_0/un8_count_G_8_0_o2_2:C (r)
               +     1.208          cell: ADLIB:OR3B
  10.346                       mycounter_0/un8_count_G_8_0_o2_2:Y (r)
               +     0.301          net: mycounter_0/G_8_0_o2_2
  10.647                       mycounter_0/un8_count_G_8_0_x2:A (r)
               +     2.201          cell: ADLIB:AX1
  12.848                       mycounter_0/un8_count_G_8_0_x2:Y (r)
               +     0.380          net: mycounter_0/G_8_0_x2
  13.228                       mycounter_0/count[7]/U0:A (r)
               +     1.194          cell: ADLIB:MX2
  14.422                       mycounter_0/count[7]/U0:Y (r)
               +     0.377          net: mycounter_0/count[7]/Y
  14.799                       mycounter_0/count[7]/U1:D (r)
                                    
  14.799                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK
               +     0.000          Clock source
  N/C                          CLK (r)
               +     0.000          net: CLK
  N/C                          CLK_pad/U0/U0:PAD (r)
               +     0.978          cell: ADLIB:IOPAD_IN
  N/C                          CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  N/C                          CLK_pad/U0/U1:YIN (r)
               +     0.251          cell: ADLIB:IOIN_IB
  N/C                          CLK_pad/U0/U1:Y (r)
               +     0.656          net: CLK_c
  N/C                          CLKINT_1:A (r)
               +     1.982          cell: ADLIB:CLKINT
  N/C                          CLKINT_1:Y (r)
               +     1.418          net: CLK_out_c
  N/C                          mycounter_0/count[7]/U1:CLK (r)
               -     1.112          Library setup time: ADLIB:DFN1C0
  N/C                          mycounter_0/count[7]/U1:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mycounter_0/count[6]/U1:CLK
  To:                          Resetn_out
  Delay (ns):                  7.932
  Slack (ns):
  Arrival (ns):                13.217
  Required (ns):
  Clock to Out (ns):           13.217


Expanded Path 1
  From: mycounter_0/count[6]/U1:CLK
  To: Resetn_out
  data required time                             N/C
  data arrival time                          -   13.217
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        CLK
               +     0.000          Clock source
  0.000                        CLK (r)
               +     0.000          net: CLK
  0.000                        CLK_pad/U0/U0:PAD (r)
               +     0.978          cell: ADLIB:IOPAD_IN
  0.978                        CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  0.978                        CLK_pad/U0/U1:YIN (r)
               +     0.251          cell: ADLIB:IOIN_IB
  1.229                        CLK_pad/U0/U1:Y (r)
               +     0.656          net: CLK_c
  1.885                        CLKINT_1:A (r)
               +     1.982          cell: ADLIB:CLKINT
  3.867                        CLKINT_1:Y (r)
               +     1.418          net: CLK_out_c
  5.285                        mycounter_0/count[6]/U1:CLK (r)
               +     1.606          cell: ADLIB:DFN1P0
  6.891                        mycounter_0/count[6]/U1:Q (f)
               +     1.177          net: mycounter_0/count[6]
  8.068                        mycounter_0/count_RNI81Q3[6]:A (f)
               +     1.219          cell: ADLIB:INV
  9.287                        mycounter_0/count_RNI81Q3[6]:Y (r)
               +     0.380          net: mycounter_0_count_i[6]
  9.667                        Resetn_out_pad/U0/U1:D (r)
               +     1.371          cell: ADLIB:IOTRI_OB_EB
  11.038                       Resetn_out_pad/U0/U1:DOUT (r)
               +     0.000          net: Resetn_out_pad/U0/NET1
  11.038                       Resetn_out_pad/U0/U0:D (r)
               +     2.179          cell: ADLIB:IOPAD_TRI
  13.217                       Resetn_out_pad/U0/U0:PAD (r)
               +     0.000          net: Resetn_out
  13.217                       Resetn_out (r)
                                    
  13.217                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK
               +     0.000          Clock source
  N/C                          CLK (r)
                                    
  N/C                          Resetn_out (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        DFN1C1_1:CLK
  To:                          mycounter_0/count[0]/U1:CLR
  Delay (ns):                  4.403
  Slack (ns):
  Arrival (ns):                9.646
  Required (ns):
  Recovery (ns):               0.235
  Minimum Period (ns):         4.596
  Skew (ns):                   -0.042

Path 2
  From:                        DFN1C1_1:CLK
  To:                          mycounter_0/count[2]/U1:CLR
  Delay (ns):                  3.579
  Slack (ns):
  Arrival (ns):                8.822
  Required (ns):
  Recovery (ns):               0.235
  Minimum Period (ns):         3.772
  Skew (ns):                   -0.042

Path 3
  From:                        DFN1C1_1:CLK
  To:                          mycounter_0/count[5]/U1:CLR
  Delay (ns):                  3.032
  Slack (ns):
  Arrival (ns):                8.275
  Required (ns):
  Recovery (ns):               0.235
  Minimum Period (ns):         3.225
  Skew (ns):                   -0.042

Path 4
  From:                        DFN1C1_1:CLK
  To:                          mycounter_0/count[1]/U1:CLR
  Delay (ns):                  2.801
  Slack (ns):
  Arrival (ns):                8.044
  Required (ns):
  Recovery (ns):               0.235
  Minimum Period (ns):         2.994
  Skew (ns):                   -0.042

Path 5
  From:                        DFN1C1_1:CLK
  To:                          mycounter_0/count[4]/U1:CLR
  Delay (ns):                  2.661
  Slack (ns):
  Arrival (ns):                7.904
  Required (ns):
  Recovery (ns):               0.235
  Minimum Period (ns):         2.854
  Skew (ns):                   -0.042


Expanded Path 1
  From: DFN1C1_1:CLK
  To: mycounter_0/count[0]/U1:CLR
  data required time                             N/C
  data arrival time                          -   9.646
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        CLK
               +     0.000          Clock source
  0.000                        CLK (r)
               +     0.000          net: CLK
  0.000                        CLK_pad/U0/U0:PAD (r)
               +     0.978          cell: ADLIB:IOPAD_IN
  0.978                        CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  0.978                        CLK_pad/U0/U1:YIN (r)
               +     0.251          cell: ADLIB:IOIN_IB
  1.229                        CLK_pad/U0/U1:Y (r)
               +     0.656          net: CLK_c
  1.885                        CLKINT_1:A (r)
               +     1.982          cell: ADLIB:CLKINT
  3.867                        CLKINT_1:Y (r)
               +     1.376          net: CLK_out_c
  5.243                        DFN1C1_1:CLK (r)
               +     1.049          cell: ADLIB:DFN1C1
  6.292                        DFN1C1_1:Q (r)
               +     3.354          net: DFN1C1_1_Q
  9.646                        mycounter_0/count[0]/U1:CLR (r)
                                    
  9.646                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK
               +     0.000          Clock source
  N/C                          CLK (r)
               +     0.000          net: CLK
  N/C                          CLK_pad/U0/U0:PAD (r)
               +     0.978          cell: ADLIB:IOPAD_IN
  N/C                          CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  N/C                          CLK_pad/U0/U1:YIN (r)
               +     0.251          cell: ADLIB:IOIN_IB
  N/C                          CLK_pad/U0/U1:Y (r)
               +     0.656          net: CLK_c
  N/C                          CLKINT_1:A (r)
               +     1.982          cell: ADLIB:CLKINT
  N/C                          CLKINT_1:Y (r)
               +     1.418          net: CLK_out_c
  N/C                          mycounter_0/count[0]/U1:CLK (r)
               -     0.235          Library recovery time: ADLIB:DFN1C0
  N/C                          mycounter_0/count[0]/U1:CLR


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

Path 1
  From:                        PAD
  To:                          DFN1C1_1:CLR
  Delay (ns):                  5.998
  Slack (ns):
  Arrival (ns):                5.998
  Required (ns):
  Recovery (ns):               0.241
  External Recovery (ns):      0.996

Path 2
  From:                        PAD
  To:                          DFN1C1_0:CLR
  Delay (ns):                  5.995
  Slack (ns):
  Arrival (ns):                5.995
  Required (ns):
  Recovery (ns):               0.241
  External Recovery (ns):      0.993


Expanded Path 1
  From: PAD
  To: DFN1C1_1:CLR
  data required time                             N/C
  data arrival time                          -   5.998
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        PAD (f)
               +     0.000          net: PAD
  0.000                        BIBUF_LVCMOS33_0/U0/U0:PAD (f)
               +     0.751          cell: ADLIB:IOPAD_BI
  0.751                        BIBUF_LVCMOS33_0/U0/U0:Y (f)
               +     0.000          net: BIBUF_LVCMOS33_0/U0/NET3
  0.751                        BIBUF_LVCMOS33_0/U0/U1:YIN (f)
               +     0.256          cell: ADLIB:IOBI_IB_OB_EB
  1.007                        BIBUF_LVCMOS33_0/U0/U1:Y (f)
               +     1.915          net: BIBUF_LVCMOS33_0_Y
  2.922                        CLKINT_0:A (f)
               +     1.832          cell: ADLIB:CLKINT
  4.754                        CLKINT_0:Y (f)
               +     1.244          net: CLKINT_0_Y
  5.998                        DFN1C1_1:CLR (f)
                                    
  5.998                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK
               +     0.000          Clock source
  N/C                          CLK (r)
               +     0.000          net: CLK
  N/C                          CLK_pad/U0/U0:PAD (r)
               +     0.978          cell: ADLIB:IOPAD_IN
  N/C                          CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  N/C                          CLK_pad/U0/U1:YIN (r)
               +     0.251          cell: ADLIB:IOIN_IB
  N/C                          CLK_pad/U0/U1:Y (r)
               +     0.656          net: CLK_c
  N/C                          CLKINT_1:A (r)
               +     1.982          cell: ADLIB:CLKINT
  N/C                          CLKINT_1:Y (r)
               +     1.376          net: CLK_out_c
  N/C                          DFN1C1_1:CLK (r)
               -     0.241          Library recovery time: ADLIB:DFN1C1
  N/C                          DFN1C1_1:CLR


END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

Path 1
  From:                        CLK
  To:                          CLK_out
  Delay (ns):                  8.997
  Slack (ns):
  Arrival (ns):                8.997
  Required (ns):


Expanded Path 1
  From: CLK
  To: CLK_out
  data required time                             N/C
  data arrival time                          -   8.997
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        CLK (f)
               +     0.000          net: CLK
  0.000                        CLK_pad/U0/U0:PAD (f)
               +     0.751          cell: ADLIB:IOPAD_IN
  0.751                        CLK_pad/U0/U0:Y (f)
               +     0.000          net: CLK_pad/U0/NET1
  0.751                        CLK_pad/U0/U1:YIN (f)
               +     0.256          cell: ADLIB:IOIN_IB
  1.007                        CLK_pad/U0/U1:Y (f)
               +     0.790          net: CLK_c
  1.797                        CLKINT_1:A (f)
               +     1.832          cell: ADLIB:CLKINT
  3.629                        CLKINT_1:Y (f)
               +     1.294          net: CLK_out_c
  4.923                        CLK_out_pad/U0/U1:D (f)
               +     1.402          cell: ADLIB:IOTRI_OB_EB
  6.325                        CLK_out_pad/U0/U1:DOUT (f)
               +     0.000          net: CLK_out_pad/U0/NET1
  6.325                        CLK_out_pad/U0/U0:D (f)
               +     2.672          cell: ADLIB:IOPAD_TRI
  8.997                        CLK_out_pad/U0/U0:PAD (f)
               +     0.000          net: CLK_out
  8.997                        CLK_out (f)
                                    
  8.997                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK (f)
                                    
  N/C                          CLK_out (f)
                                    
  N/C                          data required time


END SET Input to Output

----------------------------------------------------

Path set User Sets

