-- Version: 10.0 10.0.9.37

library ieee;
use ieee.std_logic_1164.all;
library igloo;
use igloo.all;

entity top is

    port( PAD        : inout std_logic := 'Z';
          CLK        : in    std_logic;
          CLK_out    : out   std_logic;
          Resetn_out : out   std_logic
        );

end top;

architecture DEF_ARCH of top is 

  component CLKINT
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component DFN1C1
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          CLR : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component BIBUF_LVCMOS33
    port( PAD : inout   std_logic;
          D   : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal BIBUF_LVCMOS33_0_Y, CLKINT_0_Y, CLKINT_1_Y, 
        DFN1C1_0_Q, DFN1C1_1_Q, GND_net, VCC_net : std_logic;

begin 

    CLK_out <= CLKINT_1_Y;

    CLKINT_1 : CLKINT
      port map(A => CLK, Y => CLKINT_1_Y);
    
    \VCC\ : VCC
      port map(Y => VCC_net);
    
    mycounter_0 : entity work.mycounter
      port map(CLK => CLKINT_1_Y, Resetn_in => DFN1C1_1_Q, 
        Resetn_out => Resetn_out);
    
    DFN1C1_0 : DFN1C1
      port map(D => VCC_net, CLK => CLKINT_1_Y, CLR => CLKINT_0_Y, 
        Q => DFN1C1_0_Q);
    
    CLKINT_0 : CLKINT
      port map(A => BIBUF_LVCMOS33_0_Y, Y => CLKINT_0_Y);
    
    BIBUF_LVCMOS33_0 : BIBUF_LVCMOS33
      port map(PAD => PAD, D => GND_net, E => VCC_net, Y => 
        BIBUF_LVCMOS33_0_Y);
    
    \GND\ : GND
      port map(Y => GND_net);
    
    DFN1C1_1 : DFN1C1
      port map(D => DFN1C1_0_Q, CLK => CLKINT_1_Y, CLR => 
        CLKINT_0_Y, Q => DFN1C1_1_Q);
    

end DEF_ARCH; 
