#--  Synopsys, Inc.
#--  Version F-2011.09M
#--  Project file D:\DATA\POR\Libero_SoC\POR_PPR_AGL1000_CNT\POR_PPR_AGL1000_CNT\synthesis\run_options.txt
#--  Written on Wed Jan 25 20:48:14 2012


#project files
add_file -vhdl -lib work "D:/DATA/POR/Libero_SoC/POR_PPR_AGL1000_CNT/POR_PPR_AGL1000_CNT/hdl/Counter.vhd"
add_file -vhdl -lib work "D:/DATA/POR/Libero_SoC/POR_PPR_AGL1000_CNT/POR_PPR_AGL1000_CNT/component/work/top/top.vhd"


#implementation: "synthesis"
impl -add synthesis -type fpga

#device options
set_option -technology IGLOO
set_option -part M1AGL1000V2
set_option -package FBGA484
set_option -speed_grade Std
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "work.top"

# mapper_options
set_option -frequency 100.000
set_option -write_verilog 0
set_option -write_vhdl 0

# Actel 500K
set_option -run_prop_extract 1
set_option -maxfan 24
set_option -maxfan_hard3 0
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -report_path 0
set_option -opcond COMWC
set_option -update_models_cp 0
set_option -preserve_registers 0

# Actel 500K
set_option -globalthreshold 50

# NFilter
set_option -popfeed 0
set_option -constprop 0
set_option -createhierarchy 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./top.edn"
impl -active "synthesis"
