`

    #Build: Synplify Pro F-2011.09M, Build 008R, Sep 30 2011
    #install: C:\Microsemi\Libero_v10.0\Synopsys\synplify_F201109M
    #OS: Windows XP 5.1
    #Hostname: WXPL-ODIGAS1

    $ Start of Compile
    #Wed Jan 25 20:48:15 2012

    Synopsys VHDL Compiler, version comp560rc, Build 042R, built Sep 19 2011
    @N: :  | Running in 32-bit mode
    Copyright (C) 1994-2011 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

    @N:CD720 : std.vhd(123) | Setting time resolution to ns
    @N: : top.vhd(8) | Top entity is set to top.
    VHDL syntax check successful!

    Compiler output is up to date.  No re-compile necessary

    @N:CD630 : top.vhd(8) | Synthesizing work.top.def_arch
    @N:CD630 : igloo.vhd(1398) | Synthesizing igloo.dfn1c1.syn_black_box
    Post processing for igloo.dfn1c1.syn_black_box
    @N:CD630 : igloo.vhd(1787) | Synthesizing igloo.gnd.syn_black_box
    Post processing for igloo.gnd.syn_black_box
    @N:CD630 : igloo.vhd(622) | Synthesizing igloo.bibuf_lvcmos33.syn_black_box
    Post processing for igloo.bibuf_lvcmos33.syn_black_box
    @N:CD630 : igloo.vhd(2858) | Synthesizing igloo.clkint.syn_black_box
    Post processing for igloo.clkint.syn_black_box
    @N:CD630 : Counter.vhd(27) | Synthesizing work.mycounter.mycounter_arch
    Post processing for work.mycounter.mycounter_arch
    @N:CD630 : igloo.vhd(2722) | Synthesizing igloo.vcc.syn_black_box
    Post processing for igloo.vcc.syn_black_box
    Post processing for work.top.def_arch
    @END
    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed Jan 25 20:48:15 2012

    ###########################################################]

`
@N: : | premap output is up to date. No run necessary. To force a re-synthesis, select [Resynthesize All] in menu [Run]. Click link to view previous log file. Premap Report Linked File: top_premap.srr Map & Optimize Report (contents appended below) @N: : top_fpga_mapper.srr | "D:\DATA\POR\Libero_SoC\POR_PPR_AGL1000_CNT\POR_PPR_AGL1000_CNT\synthesis\synlog\top_fpga_mapper.srr" Synopsys Actel Technology Mapper, Version map201109rcp1, Build 024R, Built Sep 28 2011 11:20:53 Copyright (C) 1994-2011, Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. Product Version F-2011.09M Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled @N:MF547 : | Generated clock conversion disabled Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) Starting Optimization and Mapping (Time elapsed 0h:00m:00s; Memory used current: 54MB peak: 56MB) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 54MB peak: 56MB) @N:MF238 : counter.vhd(47) | Found 8-bit incrementor, 'un8_count[7:0]' Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB) Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB) Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB) Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB) Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB) Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB) Writing Analyst data base D:\DATA\POR\Libero_SoC\POR_PPR_AGL1000_CNT\POR_PPR_AGL1000_CNT\synthesis\top.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB) Writing EDIF Netlist and constraint files F-2011.09M Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB) @W:MT420 : | Found inferred clock top|CLK with period 10.00ns. Please declare a user-defined clock on object "p:CLK" ##### START OF TIMING REPORT #####[ # Timing Report written on Wed Jan 25 20:48:17 2012 # Top view: top Library name: IGLOO_V2 Operating conditions: COMWCSTD ( T = 70.0, V = 1.14, P = 3.70, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: igloo Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: -4.070 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------- top|CLK 100.0 MHz 71.1 MHz 10.000 14.070 -4.070 inferred Inferred_clkgroup_0 ====================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------- top|CLK top|CLK | 10.000 -4.070 | No paths - | No paths - | No paths - ========================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: top|CLK ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------- mycounter_0.count[3] top|CLK DFN1E0C0 Q count[3] 1.771 -4.070 mycounter_0.count[0] top|CLK DFN1E0C0 Q count[0] 1.771 -3.627 mycounter_0.count[6] top|CLK DFN1E0P0 Q count[6] 1.771 -3.569 mycounter_0.count[1] top|CLK DFN1E0C0 Q count[1] 1.771 -2.971 mycounter_0.count[2] top|CLK DFN1E0C0 Q count[2] 1.771 -2.408 mycounter_0.count[4] top|CLK DFN1E0C0 Q count[4] 1.771 -1.159 mycounter_0.count[5] top|CLK DFN1E0C0 Q count[5] 1.771 -0.474 mycounter_0.count[7] top|CLK DFN1E0C0 Q count[7] 1.771 0.098 mycounter_0.count[8] top|CLK DFN1P0 Q count[8] 1.395 1.017 DFN1C1_0 top|CLK DFN1C1 Q DFN1C1_0_Q 1.771 6.079 ============================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------- mycounter_0.count[7] top|CLK DFN1E0C0 D G_8_0_x2 8.622 -4.070 mycounter_0.count[4] top|CLK DFN1E0C0 D G_1_i_x2 8.705 -3.627 mycounter_0.count[5] top|CLK DFN1E0C0 D G_0_0_x2 8.705 -3.627 mycounter_0.count[6] top|CLK DFN1E0P0 D G_5_0_x2 8.705 -3.627 mycounter_0.count[0] top|CLK DFN1E0C0 E un5_count 8.538 -1.138 mycounter_0.count[1] top|CLK DFN1E0C0 E un5_count 8.538 -1.138 mycounter_0.count[2] top|CLK DFN1E0C0 E un5_count 8.538 -1.138 mycounter_0.count[3] top|CLK DFN1E0C0 E un5_count 8.538 -1.138 mycounter_0.count[4] top|CLK DFN1E0C0 E un5_count 8.538 -1.138 mycounter_0.count[5] top|CLK DFN1E0C0 E un5_count 8.538 -1.138 ============================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 1.378 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.622 - Propagation time: 12.692 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -4.070 Number of logic level(s): 3 Starting point: mycounter_0.count[3] / Q Ending point: mycounter_0.count[7] / D The start point is clocked by top|CLK [rising] on pin CLK The end point is clocked by top|CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------- mycounter_0.count[3] DFN1E0C0 Q Out 1.771 1.771 - count[3] Net - - 3.074 - 5 mycounter_0.un8_count.G_8_0_o2_1 OR2B B In - 4.845 - mycounter_0.un8_count.G_8_0_o2_1 OR2B Y Out 1.508 6.352 - G_8_0_o2_1 Net - - 0.773 - 1 mycounter_0.un8_count.G_8_0_o2_2 OR3B C In - 7.125 - mycounter_0.un8_count.G_8_0_o2_2 OR3B Y Out 1.637 8.762 - G_8_0_o2_2 Net - - 0.773 - 1 mycounter_0.un8_count.G_8_0_x2 AX1 A In - 9.534 - mycounter_0.un8_count.G_8_0_x2 AX1 Y Out 2.385 11.919 - G_8_0_x2 Net - - 0.773 - 1 mycounter_0.count[7] DFN1E0C0 D In - 12.692 - =================================================================================================== Total path delay (propagation time + setup) of 14.070 is 8.678(61.7%) logic and 5.392(38.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 1.295 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.705 - Propagation time: 12.333 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -3.627 Number of logic level(s): 2 Starting point: mycounter_0.count[0] / Q Ending point: mycounter_0.count[5] / D The start point is clocked by top|CLK [rising] on pin CLK The end point is clocked by top|CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------- mycounter_0.count[0] DFN1E0C0 Q Out 1.771 1.771 - count[0] Net - - 3.074 - 5 mycounter_0.un8_count.G_2 NOR3C C In - 4.845 - mycounter_0.un8_count.G_2 NOR3C Y Out 1.541 6.386 - DWACT_FINC_E[0] Net - - 2.844 - 4 mycounter_0.un8_count.G_0_0_x2 AX1 B In - 9.230 - mycounter_0.un8_count.G_0_0_x2 AX1 Y Out 2.330 11.560 - G_0_0_x2 Net - - 0.773 - 1 mycounter_0.count[5] DFN1E0C0 D In - 12.333 - ================================================================================================= Total path delay (propagation time + setup) of 13.627 is 6.937(50.9%) logic and 6.690(49.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 1.295 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.705 - Propagation time: 12.333 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -3.627 Number of logic level(s): 2 Starting point: mycounter_0.count[0] / Q Ending point: mycounter_0.count[4] / D The start point is clocked by top|CLK [rising] on pin CLK The end point is clocked by top|CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------- mycounter_0.count[0] DFN1E0C0 Q Out 1.771 1.771 - count[0] Net - - 3.074 - 5 mycounter_0.un8_count.G_2 NOR3C C In - 4.845 - mycounter_0.un8_count.G_2 NOR3C Y Out 1.541 6.386 - DWACT_FINC_E[0] Net - - 2.844 - 4 mycounter_0.un8_count.G_1_i_x2 AX1C B In - 9.230 - mycounter_0.un8_count.G_1_i_x2 AX1C Y Out 2.330 11.560 - G_1_i_x2 Net - - 0.773 - 1 mycounter_0.count[4] DFN1E0C0 D In - 12.333 - ================================================================================================= Total path delay (propagation time + setup) of 13.627 is 6.937(50.9%) logic and 6.690(49.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 1.295 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.705 - Propagation time: 12.333 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -3.627 Number of logic level(s): 2 Starting point: mycounter_0.count[0] / Q Ending point: mycounter_0.count[6] / D The start point is clocked by top|CLK [rising] on pin CLK The end point is clocked by top|CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------- mycounter_0.count[0] DFN1E0C0 Q Out 1.771 1.771 - count[0] Net - - 3.074 - 5 mycounter_0.un8_count.G_2 NOR3C C In - 4.845 - mycounter_0.un8_count.G_2 NOR3C Y Out 1.541 6.386 - DWACT_FINC_E[0] Net - - 2.844 - 4 mycounter_0.un8_count.G_5_0_x2 AX1 B In - 9.230 - mycounter_0.un8_count.G_5_0_x2 AX1 Y Out 2.330 11.560 - G_5_0_x2 Net - - 0.773 - 1 mycounter_0.count[6] DFN1E0P0 D In - 12.333 - ================================================================================================= Total path delay (propagation time + setup) of 13.627 is 6.937(50.9%) logic and 6.690(49.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 1.295 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.705 - Propagation time: 12.333 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -3.627 Number of logic level(s): 2 Starting point: mycounter_0.count[0] / Q Ending point: mycounter_0.count[7] / D The start point is clocked by top|CLK [rising] on pin CLK The end point is clocked by top|CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------- mycounter_0.count[0] DFN1E0C0 Q Out 1.771 1.771 - count[0] Net - - 3.074 - 5 mycounter_0.un8_count.G_2 NOR3C C In - 4.845 - mycounter_0.un8_count.G_2 NOR3C Y Out 1.541 6.386 - DWACT_FINC_E[0] Net - - 2.844 - 4 mycounter_0.un8_count.G_8_0_x2 AX1 B In - 9.230 - mycounter_0.un8_count.G_8_0_x2 AX1 Y Out 2.330 11.560 - G_8_0_x2 Net - - 0.773 - 1 mycounter_0.count[7] DFN1E0C0 D In - 12.333 - ================================================================================================= Total path delay (propagation time + setup) of 13.627 is 6.937(50.9%) logic and 6.690(49.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: M1AGL1000V2_FBGA484_Std Report for cell top.def_arch Core Cell usage: cell count area count*area AND3 1 1.0 1.0 AX1 3 1.0 3.0 AX1C 1 1.0 1.0 CLKINT 2 0.0 0.0 GND 2 0.0 0.0 INV 2 1.0 2.0 NOR2B 1 1.0 1.0 NOR3C 1 1.0 1.0 OR2B 2 1.0 2.0 OR3B 2 1.0 2.0 OR3C 1 1.0 1.0 VCC 2 0.0 0.0 XOR2 3 1.0 3.0 DFN1C1 2 1.0 2.0 DFN1E0C0 7 1.0 7.0 DFN1E0P0 1 1.0 1.0 DFN1P0 1 1.0 1.0 ----- ---------- TOTAL 34 28.0 IO Cell usage: cell count BIBUF_LVCMOS33 1 INBUF 1 OUTBUF 2 ----- TOTAL 4 Core Cells : 28 of 24576 (0%) IO Cells : 4 RAM/ROM Usage Summary Block Rams : 0 of 32 (0%) Mapper successful! At Mapper Exit (Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 56MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Jan 25 20:48:17 2012 ###########################################################]