Timing Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Wed Jan 25 19:13:46 2012


Design: top
Family: IGLOO
Die: M1AGL1000V2
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               CLK
Period (ns):                10.639
Frequency (MHz):            93.994
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      4.996
Max Clock-To-Out (ns):      15.523

                            Input to Output
Min Delay (ns):             3.338
Max Delay (ns):             10.252

END SUMMARY
-----------------------------------------------------

Clock Domain CLK

SET Register to Register

Path 1
  From:                        mycounter_0/count[8]:CLK
  To:                          mycounter_0/count[8]:D
  Delay (ns):                  0.564
  Slack (ns):
  Arrival (ns):                2.493
  Required (ns):
  Hold (ns):                   0.000

Path 2
  From:                        DFN1C1_0:CLK
  To:                          DFN1C1_1:D
  Delay (ns):                  0.948
  Slack (ns):
  Arrival (ns):                2.874
  Required (ns):
  Hold (ns):                   0.000

Path 3
  From:                        mycounter_0/count[5]/U1:CLK
  To:                          mycounter_0/count[5]/U1:D
  Delay (ns):                  1.158
  Slack (ns):
  Arrival (ns):                3.095
  Required (ns):
  Hold (ns):                   0.000

Path 4
  From:                        mycounter_0/count[1]/U1:CLK
  To:                          mycounter_0/count[1]/U1:D
  Delay (ns):                  1.158
  Slack (ns):
  Arrival (ns):                3.095
  Required (ns):
  Hold (ns):                   0.000

Path 5
  From:                        mycounter_0/count[7]/U1:CLK
  To:                          mycounter_0/count[7]/U1:D
  Delay (ns):                  1.163
  Slack (ns):
  Arrival (ns):                3.092
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: mycounter_0/count[8]:CLK
  To: mycounter_0/count[8]:D
  data arrival time                              2.493
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        CLK
               +     0.000          Clock source
  0.000                        CLK (r)
               +     0.000          net: CLK
  0.000                        CLK_pad/U0/U0:PAD (r)
               +     0.545          cell: ADLIB:IOPAD_IN
  0.545                        CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  0.545                        CLK_pad/U0/U1:YIN (r)
               +     0.086          cell: ADLIB:IOIN_IB
  0.631                        CLK_pad/U0/U1:Y (r)
               +     0.110          net: CLK_c
  0.741                        CLKINT_1:A (r)
               +     0.646          cell: ADLIB:CLKINT
  1.387                        CLKINT_1:Y (r)
               +     0.542          net: CLK_out_c
  1.929                        mycounter_0/count[8]:CLK (r)
               +     0.358          cell: ADLIB:DFN1P0
  2.287                        mycounter_0/count[8]:Q (r)
               +     0.206          net: mycounter_0/count[8]
  2.493                        mycounter_0/count[8]:D (r)
                                    
  2.493                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK
               +     0.000          Clock source
  N/C                          CLK (r)
               +     0.000          net: CLK
  N/C                          CLK_pad/U0/U0:PAD (r)
               +     0.545          cell: ADLIB:IOPAD_IN
  N/C                          CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  N/C                          CLK_pad/U0/U1:YIN (r)
               +     0.086          cell: ADLIB:IOIN_IB
  N/C                          CLK_pad/U0/U1:Y (r)
               +     0.110          net: CLK_c
  N/C                          CLKINT_1:A (r)
               +     0.646          cell: ADLIB:CLKINT
  N/C                          CLKINT_1:Y (r)
               +     0.563          net: CLK_out_c
  N/C                          mycounter_0/count[8]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1P0
  N/C                          mycounter_0/count[8]:D


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mycounter_0/count[6]/U1:CLK
  To:                          Resetn_out
  Delay (ns):                  3.062
  Slack (ns):
  Arrival (ns):                4.996
  Required (ns):
  Clock to Out (ns):           4.996


Expanded Path 1
  From: mycounter_0/count[6]/U1:CLK
  To: Resetn_out
  data arrival time                              4.996
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        CLK
               +     0.000          Clock source
  0.000                        CLK (r)
               +     0.000          net: CLK
  0.000                        CLK_pad/U0/U0:PAD (r)
               +     0.545          cell: ADLIB:IOPAD_IN
  0.545                        CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  0.545                        CLK_pad/U0/U1:YIN (r)
               +     0.086          cell: ADLIB:IOIN_IB
  0.631                        CLK_pad/U0/U1:Y (r)
               +     0.110          net: CLK_c
  0.741                        CLKINT_1:A (r)
               +     0.646          cell: ADLIB:CLKINT
  1.387                        CLKINT_1:Y (r)
               +     0.547          net: CLK_out_c
  1.934                        mycounter_0/count[6]/U1:CLK (r)
               +     0.358          cell: ADLIB:DFN1P0
  2.292                        mycounter_0/count[6]/U1:Q (r)
               +     0.657          net: mycounter_0/count[6]
  2.949                        mycounter_0/count_RNI81Q3[6]:A (r)
               +     0.338          cell: ADLIB:INV
  3.287                        mycounter_0/count_RNI81Q3[6]:Y (f)
               +     0.109          net: mycounter_0_count_i[6]
  3.396                        Resetn_out_pad/U0/U1:D (f)
               +     0.457          cell: ADLIB:IOTRI_OB_EB
  3.853                        Resetn_out_pad/U0/U1:DOUT (f)
               +     0.000          net: Resetn_out_pad/U0/NET1
  3.853                        Resetn_out_pad/U0/U0:D (f)
               +     1.143          cell: ADLIB:IOPAD_TRI
  4.996                        Resetn_out_pad/U0/U0:PAD (f)
               +     0.000          net: Resetn_out
  4.996                        Resetn_out (f)
                                    
  4.996                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK
               +     0.000          Clock source
  N/C                          CLK (r)
                                    
  N/C                          Resetn_out (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        DFN1C1_1:CLK
  To:                          mycounter_0/count[2]/U1:CLR
  Delay (ns):                  1.079
  Slack (ns):
  Arrival (ns):                3.011
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.024

Path 2
  From:                        DFN1C1_1:CLK
  To:                          mycounter_0/count[1]/U1:CLR
  Delay (ns):                  1.190
  Slack (ns):
  Arrival (ns):                3.122
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.028

Path 3
  From:                        DFN1C1_1:CLK
  To:                          mycounter_0/count[3]/U1:CLR
  Delay (ns):                  1.197
  Slack (ns):
  Arrival (ns):                3.129
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.024

Path 4
  From:                        DFN1C1_1:CLK
  To:                          mycounter_0/count[8]:PRE
  Delay (ns):                  1.385
  Slack (ns):
  Arrival (ns):                3.317
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.018

Path 5
  From:                        DFN1C1_1:CLK
  To:                          mycounter_0/count[7]/U1:CLR
  Delay (ns):                  1.418
  Slack (ns):
  Arrival (ns):                3.350
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.018


Expanded Path 1
  From: DFN1C1_1:CLK
  To: mycounter_0/count[2]/U1:CLR
  data arrival time                              3.011
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        CLK
               +     0.000          Clock source
  0.000                        CLK (r)
               +     0.000          net: CLK
  0.000                        CLK_pad/U0/U0:PAD (r)
               +     0.545          cell: ADLIB:IOPAD_IN
  0.545                        CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  0.545                        CLK_pad/U0/U1:YIN (r)
               +     0.086          cell: ADLIB:IOIN_IB
  0.631                        CLK_pad/U0/U1:Y (r)
               +     0.110          net: CLK_c
  0.741                        CLKINT_1:A (r)
               +     0.646          cell: ADLIB:CLKINT
  1.387                        CLKINT_1:Y (r)
               +     0.545          net: CLK_out_c
  1.932                        DFN1C1_1:CLK (r)
               +     0.358          cell: ADLIB:DFN1C1
  2.290                        DFN1C1_1:Q (r)
               +     0.721          net: DFN1C1_1_Q
  3.011                        mycounter_0/count[2]/U1:CLR (r)
                                    
  3.011                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK
               +     0.000          Clock source
  N/C                          CLK (r)
               +     0.000          net: CLK
  N/C                          CLK_pad/U0/U0:PAD (r)
               +     0.545          cell: ADLIB:IOPAD_IN
  N/C                          CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  N/C                          CLK_pad/U0/U1:YIN (r)
               +     0.086          cell: ADLIB:IOIN_IB
  N/C                          CLK_pad/U0/U1:Y (r)
               +     0.110          net: CLK_c
  N/C                          CLKINT_1:A (r)
               +     0.646          cell: ADLIB:CLKINT
  N/C                          CLKINT_1:Y (r)
               +     0.569          net: CLK_out_c
  N/C                          mycounter_0/count[2]/U1:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C0
  N/C                          mycounter_0/count[2]/U1:CLR


END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

Path 1
  From:                        PAD
  To:                          DFN1C1_1:CLR
  Delay (ns):                  3.244
  Slack (ns):
  Arrival (ns):                3.244
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       -0.786

Path 2
  From:                        PAD
  To:                          DFN1C1_0:CLR
  Delay (ns):                  3.242
  Slack (ns):
  Arrival (ns):                3.242
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       -0.792


Expanded Path 1
  From: PAD
  To: DFN1C1_1:CLR
  data arrival time                              3.244
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        PAD (f)
               +     0.000          net: PAD
  0.000                        BIBUF_LVCMOS33_0/U0/U0:PAD (f)
               +     0.246          cell: ADLIB:IOPAD_BI
  0.246                        BIBUF_LVCMOS33_0/U0/U0:Y (f)
               +     0.000          net: BIBUF_LVCMOS33_0/U0/NET3
  0.246                        BIBUF_LVCMOS33_0/U0/U1:YIN (f)
               +     0.084          cell: ADLIB:IOBI_IB_OB_EB
  0.330                        BIBUF_LVCMOS33_0/U0/U1:Y (f)
               +     1.781          net: BIBUF_LVCMOS33_0_Y
  2.111                        CLKINT_0:A (f)
               +     0.625          cell: ADLIB:CLKINT
  2.736                        CLKINT_0:Y (f)
               +     0.508          net: CLKINT_0_Y
  3.244                        DFN1C1_1:CLR (f)
                                    
  3.244                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK
               +     0.000          Clock source
  N/C                          CLK (r)
               +     0.000          net: CLK
  N/C                          CLK_pad/U0/U0:PAD (r)
               +     0.702          cell: ADLIB:IOPAD_IN
  N/C                          CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  N/C                          CLK_pad/U0/U1:YIN (r)
               +     0.110          cell: ADLIB:IOIN_IB
  N/C                          CLK_pad/U0/U1:Y (r)
               +     0.142          net: CLK_c
  N/C                          CLKINT_1:A (r)
               +     0.831          cell: ADLIB:CLKINT
  N/C                          CLKINT_1:Y (r)
               +     0.673          net: CLK_out_c
  N/C                          DFN1C1_1:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C1
  N/C                          DFN1C1_1:CLR


END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

Path 1
  From:                        CLK
  To:                          CLK_out
  Delay (ns):                  3.338
  Slack (ns):
  Arrival (ns):                3.338
  Required (ns):


Expanded Path 1
  From: CLK
  To: CLK_out
  data arrival time                              3.338
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        CLK (f)
               +     0.000          net: CLK
  0.000                        CLK_pad/U0/U0:PAD (f)
               +     0.371          cell: ADLIB:IOPAD_IN
  0.371                        CLK_pad/U0/U0:Y (f)
               +     0.000          net: CLK_pad/U0/NET1
  0.371                        CLK_pad/U0/U1:YIN (f)
               +     0.084          cell: ADLIB:IOIN_IB
  0.455                        CLK_pad/U0/U1:Y (f)
               +     0.143          net: CLK_c
  0.598                        CLKINT_1:A (f)
               +     0.625          cell: ADLIB:CLKINT
  1.223                        CLKINT_1:Y (f)
               +     0.515          net: CLK_out_c
  1.738                        CLK_out_pad/U0/U1:D (f)
               +     0.457          cell: ADLIB:IOTRI_OB_EB
  2.195                        CLK_out_pad/U0/U1:DOUT (f)
               +     0.000          net: CLK_out_pad/U0/NET1
  2.195                        CLK_out_pad/U0/U0:D (f)
               +     1.143          cell: ADLIB:IOPAD_TRI
  3.338                        CLK_out_pad/U0/U0:PAD (f)
               +     0.000          net: CLK_out
  3.338                        CLK_out (f)
                                    
  3.338                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK (f)
                                    
  N/C                          CLK_out (f)
                                    
  N/C                          data required time


END SET Input to Output

----------------------------------------------------

Path set User Sets

