@N|Running in 32-bit mode
@N: CD720 :"C:\Microsemi\Libero_v10.0\Synopsys\synplify_F201109M\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"D:\DATA\POR\Libero_SoC\POR_PPR_AGL1000_CNT\POR_PPR_AGL1000_CNT\component\work\top\top.vhd":8:7:8:9|Top entity is set to top.
@N: CD630 :"D:\DATA\POR\Libero_SoC\POR_PPR_AGL1000_CNT\POR_PPR_AGL1000_CNT\component\work\top\top.vhd":8:7:8:9|Synthesizing work.top.def_arch 
@N: CD630 :"C:\Microsemi\Libero_v10.0\Synopsys\synplify_F201109M\lib\proasic\igloo.vhd":1398:10:1398:15|Synthesizing igloo.dfn1c1.syn_black_box 
@N: CD630 :"C:\Microsemi\Libero_v10.0\Synopsys\synplify_F201109M\lib\proasic\igloo.vhd":1787:10:1787:12|Synthesizing igloo.gnd.syn_black_box 
@N: CD630 :"C:\Microsemi\Libero_v10.0\Synopsys\synplify_F201109M\lib\proasic\igloo.vhd":622:10:622:23|Synthesizing igloo.bibuf_lvcmos33.syn_black_box 
@N: CD630 :"C:\Microsemi\Libero_v10.0\Synopsys\synplify_F201109M\lib\proasic\igloo.vhd":2858:10:2858:15|Synthesizing igloo.clkint.syn_black_box 
@N: CD630 :"D:\DATA\POR\Libero_SoC\POR_PPR_AGL1000_CNT\POR_PPR_AGL1000_CNT\hdl\Counter.vhd":27:7:27:15|Synthesizing work.mycounter.mycounter_arch 
@N: CD630 :"C:\Microsemi\Libero_v10.0\Synopsys\synplify_F201109M\lib\proasic\igloo.vhd":2722:10:2722:12|Synthesizing igloo.vcc.syn_black_box 

