Timing Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Wed Jan 25 19:09:05 2012


Design: top
Family: IGLOO
Die: M1AGL1000V2
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               CLK
Period (ns):                10.626
Frequency (MHz):            94.109
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      4.342
Max Clock-To-Out (ns):      13.217

                            Input to Output
Min Delay (ns):             3.016
Max Delay (ns):             8.997

END SUMMARY
-----------------------------------------------------

Clock Domain CLK

SET Register to Register

Path 1
  From:                        DFN1C1_0:CLK
  To:                          DFN1C1_1:D
  Delay (ns):                  0.510
  Slack (ns):
  Arrival (ns):                2.337
  Required (ns):
  Hold (ns):                   0.000

Path 2
  From:                        mycounter_0/count[8]:CLK
  To:                          mycounter_0/count[8]:D
  Delay (ns):                  0.563
  Slack (ns):
  Arrival (ns):                2.406
  Required (ns):
  Hold (ns):                   0.000

Path 3
  From:                        mycounter_0/count[4]/U1:CLK
  To:                          mycounter_0/count[4]/U1:D
  Delay (ns):                  1.158
  Slack (ns):
  Arrival (ns):                3.001
  Required (ns):
  Hold (ns):                   0.000

Path 4
  From:                        mycounter_0/count[1]/U1:CLK
  To:                          mycounter_0/count[1]/U1:D
  Delay (ns):                  1.158
  Slack (ns):
  Arrival (ns):                3.001
  Required (ns):
  Hold (ns):                   0.000

Path 5
  From:                        mycounter_0/count[3]/U1:CLK
  To:                          mycounter_0/count[3]/U1:D
  Delay (ns):                  1.164
  Slack (ns):
  Arrival (ns):                3.007
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: DFN1C1_0:CLK
  To: DFN1C1_1:D
  data arrival time                              2.337
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        CLK
               +     0.000          Clock source
  0.000                        CLK (r)
               +     0.000          net: CLK
  0.000                        CLK_pad/U0/U0:PAD (r)
               +     0.317          cell: ADLIB:IOPAD_IN
  0.317                        CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  0.317                        CLK_pad/U0/U1:YIN (r)
               +     0.086          cell: ADLIB:IOIN_IB
  0.403                        CLK_pad/U0/U1:Y (r)
               +     0.239          net: CLK_c
  0.642                        CLKINT_1:A (r)
               +     0.646          cell: ADLIB:CLKINT
  1.288                        CLKINT_1:Y (r)
               +     0.539          net: CLK_out_c
  1.827                        DFN1C1_0:CLK (r)
               +     0.358          cell: ADLIB:DFN1C1
  2.185                        DFN1C1_0:Q (r)
               +     0.152          net: DFN1C1_0_Q
  2.337                        DFN1C1_1:D (r)
                                    
  2.337                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK
               +     0.000          Clock source
  N/C                          CLK (r)
               +     0.000          net: CLK
  N/C                          CLK_pad/U0/U0:PAD (r)
               +     0.317          cell: ADLIB:IOPAD_IN
  N/C                          CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  N/C                          CLK_pad/U0/U1:YIN (r)
               +     0.086          cell: ADLIB:IOIN_IB
  N/C                          CLK_pad/U0/U1:Y (r)
               +     0.239          net: CLK_c
  N/C                          CLKINT_1:A (r)
               +     0.646          cell: ADLIB:CLKINT
  N/C                          CLKINT_1:Y (r)
               +     0.558          net: CLK_out_c
  N/C                          DFN1C1_1:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C1
  N/C                          DFN1C1_1:D


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mycounter_0/count[6]/U1:CLK
  To:                          Resetn_out
  Delay (ns):                  2.499
  Slack (ns):
  Arrival (ns):                4.342
  Required (ns):
  Clock to Out (ns):           4.342


Expanded Path 1
  From: mycounter_0/count[6]/U1:CLK
  To: Resetn_out
  data arrival time                              4.342
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        CLK
               +     0.000          Clock source
  0.000                        CLK (r)
               +     0.000          net: CLK
  0.000                        CLK_pad/U0/U0:PAD (r)
               +     0.317          cell: ADLIB:IOPAD_IN
  0.317                        CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  0.317                        CLK_pad/U0/U1:YIN (r)
               +     0.086          cell: ADLIB:IOIN_IB
  0.403                        CLK_pad/U0/U1:Y (r)
               +     0.239          net: CLK_c
  0.642                        CLKINT_1:A (r)
               +     0.646          cell: ADLIB:CLKINT
  1.288                        CLKINT_1:Y (r)
               +     0.555          net: CLK_out_c
  1.843                        mycounter_0/count[6]/U1:CLK (r)
               +     0.358          cell: ADLIB:DFN1P0
  2.201                        mycounter_0/count[6]/U1:Q (r)
               +     0.387          net: mycounter_0/count[6]
  2.588                        mycounter_0/count_RNI81Q3[6]:A (r)
               +     0.301          cell: ADLIB:INV
  2.889                        mycounter_0/count_RNI81Q3[6]:Y (f)
               +     0.109          net: mycounter_0_count_i[6]
  2.998                        Resetn_out_pad/U0/U1:D (f)
               +     0.457          cell: ADLIB:IOTRI_OB_EB
  3.455                        Resetn_out_pad/U0/U1:DOUT (f)
               +     0.000          net: Resetn_out_pad/U0/NET1
  3.455                        Resetn_out_pad/U0/U0:D (f)
               +     0.887          cell: ADLIB:IOPAD_TRI
  4.342                        Resetn_out_pad/U0/U0:PAD (f)
               +     0.000          net: Resetn_out
  4.342                        Resetn_out (f)
                                    
  4.342                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK
               +     0.000          Clock source
  N/C                          CLK (r)
                                    
  N/C                          Resetn_out (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        DFN1C1_1:CLK
  To:                          mycounter_0/count[7]/U1:CLR
  Delay (ns):                  0.907
  Slack (ns):
  Arrival (ns):                2.734
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.038

Path 2
  From:                        DFN1C1_1:CLK
  To:                          mycounter_0/count[6]/U1:PRE
  Delay (ns):                  0.907
  Slack (ns):
  Arrival (ns):                2.734
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.038

Path 3
  From:                        DFN1C1_1:CLK
  To:                          mycounter_0/count[8]:PRE
  Delay (ns):                  0.907
  Slack (ns):
  Arrival (ns):                2.734
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.038

Path 4
  From:                        DFN1C1_1:CLK
  To:                          mycounter_0/count[3]/U1:CLR
  Delay (ns):                  0.907
  Slack (ns):
  Arrival (ns):                2.734
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.038

Path 5
  From:                        DFN1C1_1:CLK
  To:                          mycounter_0/count[4]/U1:CLR
  Delay (ns):                  0.962
  Slack (ns):
  Arrival (ns):                2.789
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.038


Expanded Path 1
  From: DFN1C1_1:CLK
  To: mycounter_0/count[7]/U1:CLR
  data arrival time                              2.734
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        CLK
               +     0.000          Clock source
  0.000                        CLK (r)
               +     0.000          net: CLK
  0.000                        CLK_pad/U0/U0:PAD (r)
               +     0.317          cell: ADLIB:IOPAD_IN
  0.317                        CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  0.317                        CLK_pad/U0/U1:YIN (r)
               +     0.086          cell: ADLIB:IOIN_IB
  0.403                        CLK_pad/U0/U1:Y (r)
               +     0.239          net: CLK_c
  0.642                        CLKINT_1:A (r)
               +     0.646          cell: ADLIB:CLKINT
  1.288                        CLKINT_1:Y (r)
               +     0.539          net: CLK_out_c
  1.827                        DFN1C1_1:CLK (r)
               +     0.358          cell: ADLIB:DFN1C1
  2.185                        DFN1C1_1:Q (r)
               +     0.549          net: DFN1C1_1_Q
  2.734                        mycounter_0/count[7]/U1:CLR (r)
                                    
  2.734                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK
               +     0.000          Clock source
  N/C                          CLK (r)
               +     0.000          net: CLK
  N/C                          CLK_pad/U0/U0:PAD (r)
               +     0.317          cell: ADLIB:IOPAD_IN
  N/C                          CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  N/C                          CLK_pad/U0/U1:YIN (r)
               +     0.086          cell: ADLIB:IOIN_IB
  N/C                          CLK_pad/U0/U1:Y (r)
               +     0.239          net: CLK_c
  N/C                          CLKINT_1:A (r)
               +     0.646          cell: ADLIB:CLKINT
  N/C                          CLKINT_1:Y (r)
               +     0.577          net: CLK_out_c
  N/C                          mycounter_0/count[7]/U1:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C0
  N/C                          mycounter_0/count[7]/U1:CLR


END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

Path 1
  From:                        PAD
  To:                          DFN1C1_0:CLR
  Delay (ns):                  2.174
  Slack (ns):
  Arrival (ns):                2.174
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       0.145

Path 2
  From:                        PAD
  To:                          DFN1C1_1:CLR
  Delay (ns):                  2.175
  Slack (ns):
  Arrival (ns):                2.175
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       0.144


Expanded Path 1
  From: PAD
  To: DFN1C1_0:CLR
  data arrival time                              2.174
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        PAD (f)
               +     0.000          net: PAD
  0.000                        BIBUF_LVCMOS33_0/U0/U0:PAD (f)
               +     0.249          cell: ADLIB:IOPAD_BI
  0.249                        BIBUF_LVCMOS33_0/U0/U0:Y (f)
               +     0.000          net: BIBUF_LVCMOS33_0/U0/NET3
  0.249                        BIBUF_LVCMOS33_0/U0/U1:YIN (f)
               +     0.084          cell: ADLIB:IOBI_IB_OB_EB
  0.333                        BIBUF_LVCMOS33_0/U0/U1:Y (f)
               +     0.717          net: BIBUF_LVCMOS33_0_Y
  1.050                        CLKINT_0:A (f)
               +     0.625          cell: ADLIB:CLKINT
  1.675                        CLKINT_0:Y (f)
               +     0.499          net: CLKINT_0_Y
  2.174                        DFN1C1_0:CLR (f)
                                    
  2.174                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK
               +     0.000          Clock source
  N/C                          CLK (r)
               +     0.000          net: CLK
  N/C                          CLK_pad/U0/U0:PAD (r)
               +     0.407          cell: ADLIB:IOPAD_IN
  N/C                          CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  N/C                          CLK_pad/U0/U1:YIN (r)
               +     0.110          cell: ADLIB:IOIN_IB
  N/C                          CLK_pad/U0/U1:Y (r)
               +     0.307          net: CLK_c
  N/C                          CLKINT_1:A (r)
               +     0.831          cell: ADLIB:CLKINT
  N/C                          CLKINT_1:Y (r)
               +     0.664          net: CLK_out_c
  N/C                          DFN1C1_0:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C1
  N/C                          DFN1C1_0:CLR


END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

Path 1
  From:                        CLK
  To:                          CLK_out
  Delay (ns):                  3.016
  Slack (ns):
  Arrival (ns):                3.016
  Required (ns):


Expanded Path 1
  From: CLK
  To: CLK_out
  data arrival time                              3.016
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        CLK (r)
               +     0.000          net: CLK
  0.000                        CLK_pad/U0/U0:PAD (r)
               +     0.317          cell: ADLIB:IOPAD_IN
  0.317                        CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  0.317                        CLK_pad/U0/U1:YIN (r)
               +     0.086          cell: ADLIB:IOIN_IB
  0.403                        CLK_pad/U0/U1:Y (r)
               +     0.239          net: CLK_c
  0.642                        CLKINT_1:A (r)
               +     0.646          cell: ADLIB:CLKINT
  1.288                        CLKINT_1:Y (r)
               +     0.555          net: CLK_out_c
  1.843                        CLK_out_pad/U0/U1:D (r)
               +     0.468          cell: ADLIB:IOTRI_OB_EB
  2.311                        CLK_out_pad/U0/U1:DOUT (r)
               +     0.000          net: CLK_out_pad/U0/NET1
  2.311                        CLK_out_pad/U0/U0:D (r)
               +     0.705          cell: ADLIB:IOPAD_TRI
  3.016                        CLK_out_pad/U0/U0:PAD (r)
               +     0.000          net: CLK_out
  3.016                        CLK_out (r)
                                    
  3.016                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK (r)
                                    
  N/C                          CLK_out (r)
                                    
  N/C                          data required time


END SET Input to Output

----------------------------------------------------

Path set User Sets

