Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Wed Jan 25 19:13:46 2012


Design: top
Family: IGLOO
Die: M1AGL1000V2
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               CLK
Period (ns):                10.639
Frequency (MHz):            93.994
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      4.996
Max Clock-To-Out (ns):      15.523

                            Input to Output
Min Delay (ns):             3.338
Max Delay (ns):             10.252

END SUMMARY
-----------------------------------------------------

Clock Domain CLK

SET Register to Register

Path 1
  From:                        mycounter_0/count[3]/U1:CLK
  To:                          mycounter_0/count[7]/U1:D
  Delay (ns):                  9.514
  Slack (ns):
  Arrival (ns):                15.045
  Required (ns):
  Setup (ns):                  1.112
  Minimum Period (ns):         10.639

Path 2
  From:                        mycounter_0/count[0]/U1:CLK
  To:                          mycounter_0/count[7]/U1:D
  Delay (ns):                  9.254
  Slack (ns):
  Arrival (ns):                14.792
  Required (ns):
  Setup (ns):                  1.112
  Minimum Period (ns):         10.386

Path 3
  From:                        mycounter_0/count[0]/U1:CLK
  To:                          mycounter_0/count[6]/U1:D
  Delay (ns):                  9.240
  Slack (ns):
  Arrival (ns):                14.778
  Required (ns):
  Setup (ns):                  1.112
  Minimum Period (ns):         10.359

Path 4
  From:                        mycounter_0/count[6]/U1:CLK
  To:                          mycounter_0/count[7]/U1:D
  Delay (ns):                  9.194
  Slack (ns):
  Arrival (ns):                14.725
  Required (ns):
  Setup (ns):                  1.112
  Minimum Period (ns):         10.319

Path 5
  From:                        mycounter_0/count[5]/U1:CLK
  To:                          mycounter_0/count[7]/U1:D
  Delay (ns):                  9.068
  Slack (ns):
  Arrival (ns):                14.606
  Required (ns):
  Setup (ns):                  1.112
  Minimum Period (ns):         10.200


Expanded Path 1
  From: mycounter_0/count[3]/U1:CLK
  To: mycounter_0/count[7]/U1:D
  data required time                             N/C
  data arrival time                          -   15.045
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        CLK
               +     0.000          Clock source
  0.000                        CLK (r)
               +     0.000          net: CLK
  0.000                        CLK_pad/U0/U0:PAD (r)
               +     1.595          cell: ADLIB:IOPAD_IN
  1.595                        CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  1.595                        CLK_pad/U0/U1:YIN (r)
               +     0.251          cell: ADLIB:IOIN_IB
  1.846                        CLK_pad/U0/U1:Y (r)
               +     0.303          net: CLK_c
  2.149                        CLKINT_1:A (r)
               +     1.982          cell: ADLIB:CLKINT
  4.131                        CLKINT_1:Y (r)
               +     1.400          net: CLK_out_c
  5.531                        mycounter_0/count[3]/U1:CLK (r)
               +     1.606          cell: ADLIB:DFN1C0
  7.137                        mycounter_0/count[3]/U1:Q (f)
               +     0.397          net: mycounter_0/count[3]
  7.534                        mycounter_0/un8_count_G_8_0_o2_1:B (f)
               +     1.473          cell: ADLIB:OR2B
  9.007                        mycounter_0/un8_count_G_8_0_o2_1:Y (r)
               +     0.377          net: mycounter_0/G_8_0_o2_1
  9.384                        mycounter_0/un8_count_G_8_0_o2_2:C (r)
               +     1.208          cell: ADLIB:OR3B
  10.592                       mycounter_0/un8_count_G_8_0_o2_2:Y (r)
               +     0.301          net: mycounter_0/G_8_0_o2_2
  10.893                       mycounter_0/un8_count_G_8_0_x2:A (r)
               +     2.201          cell: ADLIB:AX1
  13.094                       mycounter_0/un8_count_G_8_0_x2:Y (r)
               +     0.380          net: mycounter_0/G_8_0_x2
  13.474                       mycounter_0/count[7]/U0:A (r)
               +     1.194          cell: ADLIB:MX2
  14.668                       mycounter_0/count[7]/U0:Y (r)
               +     0.377          net: mycounter_0/count[7]/Y
  15.045                       mycounter_0/count[7]/U1:D (r)
                                    
  15.045                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK
               +     0.000          Clock source
  N/C                          CLK (r)
               +     0.000          net: CLK
  N/C                          CLK_pad/U0/U0:PAD (r)
               +     1.595          cell: ADLIB:IOPAD_IN
  N/C                          CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  N/C                          CLK_pad/U0/U1:YIN (r)
               +     0.251          cell: ADLIB:IOIN_IB
  N/C                          CLK_pad/U0/U1:Y (r)
               +     0.303          net: CLK_c
  N/C                          CLKINT_1:A (r)
               +     1.982          cell: ADLIB:CLKINT
  N/C                          CLKINT_1:Y (r)
               +     1.387          net: CLK_out_c
  N/C                          mycounter_0/count[7]/U1:CLK (r)
               -     1.112          Library setup time: ADLIB:DFN1C0
  N/C                          mycounter_0/count[7]/U1:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mycounter_0/count[6]/U1:CLK
  To:                          Resetn_out
  Delay (ns):                  9.992
  Slack (ns):
  Arrival (ns):                15.523
  Required (ns):
  Clock to Out (ns):           15.523


Expanded Path 1
  From: mycounter_0/count[6]/U1:CLK
  To: Resetn_out
  data required time                             N/C
  data arrival time                          -   15.523
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        CLK
               +     0.000          Clock source
  0.000                        CLK (r)
               +     0.000          net: CLK
  0.000                        CLK_pad/U0/U0:PAD (r)
               +     1.595          cell: ADLIB:IOPAD_IN
  1.595                        CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  1.595                        CLK_pad/U0/U1:YIN (r)
               +     0.251          cell: ADLIB:IOIN_IB
  1.846                        CLK_pad/U0/U1:Y (r)
               +     0.303          net: CLK_c
  2.149                        CLKINT_1:A (r)
               +     1.982          cell: ADLIB:CLKINT
  4.131                        CLKINT_1:Y (r)
               +     1.400          net: CLK_out_c
  5.531                        mycounter_0/count[6]/U1:CLK (r)
               +     1.606          cell: ADLIB:DFN1P0
  7.137                        mycounter_0/count[6]/U1:Q (f)
               +     1.977          net: mycounter_0/count[6]
  9.114                        mycounter_0/count_RNI81Q3[6]:A (f)
               +     1.306          cell: ADLIB:INV
  10.420                       mycounter_0/count_RNI81Q3[6]:Y (r)
               +     0.377          net: mycounter_0_count_i[6]
  10.797                       Resetn_out_pad/U0/U1:D (r)
               +     1.371          cell: ADLIB:IOTRI_OB_EB
  12.168                       Resetn_out_pad/U0/U1:DOUT (r)
               +     0.000          net: Resetn_out_pad/U0/NET1
  12.168                       Resetn_out_pad/U0/U0:D (r)
               +     3.355          cell: ADLIB:IOPAD_TRI
  15.523                       Resetn_out_pad/U0/U0:PAD (r)
               +     0.000          net: Resetn_out
  15.523                       Resetn_out (r)
                                    
  15.523                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK
               +     0.000          Clock source
  N/C                          CLK (r)
                                    
  N/C                          Resetn_out (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        DFN1C1_1:CLK
  To:                          mycounter_0/count[0]/U1:CLR
  Delay (ns):                  6.202
  Slack (ns):
  Arrival (ns):                11.728
  Required (ns):
  Recovery (ns):               0.235
  Minimum Period (ns):         6.425
  Skew (ns):                   -0.012

Path 2
  From:                        DFN1C1_1:CLK
  To:                          mycounter_0/count[5]/U1:CLR
  Delay (ns):                  5.942
  Slack (ns):
  Arrival (ns):                11.468
  Required (ns):
  Recovery (ns):               0.235
  Minimum Period (ns):         6.165
  Skew (ns):                   -0.012

Path 3
  From:                        DFN1C1_1:CLK
  To:                          mycounter_0/count[4]/U1:CLR
  Delay (ns):                  5.068
  Slack (ns):
  Arrival (ns):                10.594
  Required (ns):
  Recovery (ns):               0.235
  Minimum Period (ns):         5.291
  Skew (ns):                   -0.012

Path 4
  From:                        DFN1C1_1:CLK
  To:                          mycounter_0/count[6]/U1:PRE
  Delay (ns):                  4.389
  Slack (ns):
  Arrival (ns):                9.915
  Required (ns):
  Recovery (ns):               0.235
  Minimum Period (ns):         4.619
  Skew (ns):                   -0.005

Path 5
  From:                        DFN1C1_1:CLK
  To:                          mycounter_0/count[7]/U1:CLR
  Delay (ns):                  3.882
  Slack (ns):
  Arrival (ns):                9.408
  Required (ns):
  Recovery (ns):               0.235
  Minimum Period (ns):         4.125
  Skew (ns):                   0.008


Expanded Path 1
  From: DFN1C1_1:CLK
  To: mycounter_0/count[0]/U1:CLR
  data required time                             N/C
  data arrival time                          -   11.728
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        CLK
               +     0.000          Clock source
  0.000                        CLK (r)
               +     0.000          net: CLK
  0.000                        CLK_pad/U0/U0:PAD (r)
               +     1.595          cell: ADLIB:IOPAD_IN
  1.595                        CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  1.595                        CLK_pad/U0/U1:YIN (r)
               +     0.251          cell: ADLIB:IOIN_IB
  1.846                        CLK_pad/U0/U1:Y (r)
               +     0.303          net: CLK_c
  2.149                        CLKINT_1:A (r)
               +     1.982          cell: ADLIB:CLKINT
  4.131                        CLKINT_1:Y (r)
               +     1.395          net: CLK_out_c
  5.526                        DFN1C1_1:CLK (r)
               +     1.049          cell: ADLIB:DFN1C1
  6.575                        DFN1C1_1:Q (r)
               +     5.153          net: DFN1C1_1_Q
  11.728                       mycounter_0/count[0]/U1:CLR (r)
                                    
  11.728                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK
               +     0.000          Clock source
  N/C                          CLK (r)
               +     0.000          net: CLK
  N/C                          CLK_pad/U0/U0:PAD (r)
               +     1.595          cell: ADLIB:IOPAD_IN
  N/C                          CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  N/C                          CLK_pad/U0/U1:YIN (r)
               +     0.251          cell: ADLIB:IOIN_IB
  N/C                          CLK_pad/U0/U1:Y (r)
               +     0.303          net: CLK_c
  N/C                          CLKINT_1:A (r)
               +     1.982          cell: ADLIB:CLKINT
  N/C                          CLKINT_1:Y (r)
               +     1.407          net: CLK_out_c
  N/C                          mycounter_0/count[0]/U1:CLK (r)
               -     0.235          Library recovery time: ADLIB:DFN1C0
  N/C                          mycounter_0/count[0]/U1:CLR


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

Path 1
  From:                        PAD
  To:                          DFN1C1_0:CLR
  Delay (ns):                  8.844
  Slack (ns):
  Arrival (ns):                8.844
  Required (ns):
  Recovery (ns):               0.241
  External Recovery (ns):      3.574

Path 2
  From:                        PAD
  To:                          DFN1C1_1:CLR
  Delay (ns):                  8.849
  Slack (ns):
  Arrival (ns):                8.849
  Required (ns):
  Recovery (ns):               0.241
  External Recovery (ns):      3.564


Expanded Path 1
  From: PAD
  To: DFN1C1_0:CLR
  data required time                             N/C
  data arrival time                          -   8.844
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        PAD (f)
               +     0.000          net: PAD
  0.000                        BIBUF_LVCMOS33_0/U0/U0:PAD (f)
               +     0.740          cell: ADLIB:IOPAD_BI
  0.740                        BIBUF_LVCMOS33_0/U0/U0:Y (f)
               +     0.000          net: BIBUF_LVCMOS33_0/U0/NET3
  0.740                        BIBUF_LVCMOS33_0/U0/U1:YIN (f)
               +     0.256          cell: ADLIB:IOBI_IB_OB_EB
  0.996                        BIBUF_LVCMOS33_0/U0/U1:Y (f)
               +     4.757          net: BIBUF_LVCMOS33_0_Y
  5.753                        CLKINT_0:A (f)
               +     1.832          cell: ADLIB:CLKINT
  7.585                        CLKINT_0:Y (f)
               +     1.259          net: CLKINT_0_Y
  8.844                        DFN1C1_0:CLR (f)
                                    
  8.844                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK
               +     0.000          Clock source
  N/C                          CLK (r)
               +     0.000          net: CLK
  N/C                          CLK_pad/U0/U0:PAD (r)
               +     1.595          cell: ADLIB:IOPAD_IN
  N/C                          CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  N/C                          CLK_pad/U0/U1:YIN (r)
               +     0.251          cell: ADLIB:IOIN_IB
  N/C                          CLK_pad/U0/U1:Y (r)
               +     0.303          net: CLK_c
  N/C                          CLKINT_1:A (r)
               +     1.982          cell: ADLIB:CLKINT
  N/C                          CLKINT_1:Y (r)
               +     1.380          net: CLK_out_c
  N/C                          DFN1C1_0:CLK (r)
               -     0.241          Library recovery time: ADLIB:DFN1C1
  N/C                          DFN1C1_0:CLR


END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

Path 1
  From:                        CLK
  To:                          CLK_out
  Delay (ns):                  10.252
  Slack (ns):
  Arrival (ns):                10.252
  Required (ns):


Expanded Path 1
  From: CLK
  To: CLK_out
  data required time                             N/C
  data arrival time                          -   10.252
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        CLK (r)
               +     0.000          net: CLK
  0.000                        CLK_pad/U0/U0:PAD (r)
               +     1.595          cell: ADLIB:IOPAD_IN
  1.595                        CLK_pad/U0/U0:Y (r)
               +     0.000          net: CLK_pad/U0/NET1
  1.595                        CLK_pad/U0/U1:YIN (r)
               +     0.251          cell: ADLIB:IOIN_IB
  1.846                        CLK_pad/U0/U1:Y (r)
               +     0.303          net: CLK_c
  2.149                        CLKINT_1:A (r)
               +     1.982          cell: ADLIB:CLKINT
  4.131                        CLKINT_1:Y (r)
               +     1.395          net: CLK_out_c
  5.526                        CLK_out_pad/U0/U1:D (r)
               +     1.371          cell: ADLIB:IOTRI_OB_EB
  6.897                        CLK_out_pad/U0/U1:DOUT (r)
               +     0.000          net: CLK_out_pad/U0/NET1
  6.897                        CLK_out_pad/U0/U0:D (r)
               +     3.355          cell: ADLIB:IOPAD_TRI
  10.252                       CLK_out_pad/U0/U0:PAD (r)
               +     0.000          net: CLK_out
  10.252                       CLK_out (r)
                                    
  10.252                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK (r)
                                    
  N/C                          CLK_out (r)
                                    
  N/C                          data required time


END SET Input to Output

----------------------------------------------------

Path set User Sets

