m255
K3
13
Z0 cModel Technology
Z1 dD:\Actelprj\Fusion_applications\Cory_test_case\simulation
Eanalog2
Z2 w1168198825
Z3 DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
Z4 FD:/Actelprj/Fusion_applications/Cory_test_case/smartgen/Analog2/Analog2.vhd
l0
L7
VR<QVX3VJNfDgKCZ=_jPE12
Z5 OE;C;6.1e;31
31
Z6 o-93 -explicit -work presynth
Z7 tGenerateLoopIterationMax 100000
Adef_arch
R3
DE work analog2 R<QVX3VJNfDgKCZ=_jPE12
l209
L28
V0AJ^Z1[;8CJM=@:AAK@TE3
R5
31
Z8 M1 ieee std_logic_1164
R6
R7
Eanalog2_assc_ram
R2
R3
Z9 FD:/Actelprj/Fusion_applications/Cory_test_case/smartgen/Analog2/Analog2_assc_ram.vhd
l0
L7
V34]WVJ68Y7J]QP6P>JTA72
R5
31
R6
R7
Adef_arch
R3
DE work analog2_assc_ram 34]WVJ68Y7J]QP6P>JTA72
l44
L17
VG3Vd01VleS`6KmLKHd0>:1
R5
31
R8
R6
R7
Eanalog2_assc_wrapper
R2
Z10 DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
R3
Z11 FD:/Actelprj/Fusion_applications/Cory_test_case/smartgen/Analog2/Analog2_assc_wrapper.vhd
l0
L115
V:FT=o>1OGIeKf4>KfNKGf1
R5
31
R6
R7
Adef_arch
R10
R3
DE work analog2_assc_wrapper :FT=o>1OGIeKf4>KfNKGf1
l242
L169
VcQIIG6bWnPbdoC`R>NdaU2
R5
31
Z12 M2 ieee std_logic_1164
Z13 M1 ieee numeric_std
R6
R7
Eanalog_proc1
Z14 w1168555398
R3
Z15 dD:\backup\Projects\Fusion_Projects\Design Example\throughput enhancement\Fusion_ADC_Throughput\simulation
Z16 8D:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/Analog_proc1/Analog_proc1.vhd
Z17 FD:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/Analog_proc1/Analog_proc1.vhd
l0
L7
V>JSde58efZCJJLL>VH=g83
Z18 OW;C;6.3c;37
31
Z19 o-93 -explicit -work presynth -O0
Adef_arch
R3
DE work analog_proc1 >JSde58efZCJJLL>VH=g83
l209
L28
VWOC?cV1@oF7Ni<;S>AicQ1
R18
31
R8
R19
Eanalog_proc1_assc_ram
R14
R3
R15
Z20 8D:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/Analog_proc1/Analog_proc1_assc_ram.vhd
Z21 FD:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/Analog_proc1/Analog_proc1_assc_ram.vhd
l0
L7
VP:1g?MT784C@8`Mc@309i1
R18
31
R19
Adef_arch
R3
DE work analog_proc1_assc_ram P:1g?MT784C@8`Mc@309i1
l44
L17
V:4>VgY]T[O341B6iKh6ZF1
R18
31
R8
R19
Eanalog_proc1_assc_wrapper
R14
R10
R3
R15
Z22 8D:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/Analog_proc1/Analog_proc1_assc_wrapper.vhd
Z23 FD:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/Analog_proc1/Analog_proc1_assc_wrapper.vhd
l0
L115
V13d;>z><G3=2[^^OE6kNm1
R18
31
R19
Adef_arch
R10
R3
DE work analog_proc1_assc_wrapper 13d;>z><G3=2[^^OE6kNm1
l242
L169
VAdkTUTod<dPm29h]844J13
R18
31
R12
R13
R19
Eassc
Z24 w1150886468
R10
R3
R15
Z25 8D:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/common/vhdl/assc.vhd
Z26 FD:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/common/vhdl/assc.vhd
l0
L347
V@_[bIb8h;fOheL;CgaNZ<3
R18
31
R19
Abehv
R10
R3
DE work assc @_[bIb8h;fOheL;CgaNZ<3
l407
L377
V1TmBM4T@1E_OeWHZz]8Ln0
R18
31
R12
R13
R19
Edxwqxgdccxc
Z27 w1150886464
R10
R3
R15
Z28 8D:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/common/vhdl/initcfg_xd.vhd
Z29 FD:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/common/vhdl/initcfg_xd.vhd
l0
L10
VBjeIDIdTj:R>BgdgdWYbl1
R18
31
R19
Acmvhvtvbzkh
R10
R3
DE work dxwqxgdccxc BjeIDIdTj:R>BgdgdWYbl1
l30
L17
Vc;CoRLl?fB1k4K]MUNlYD3
R18
31
R12
R13
R19
Effppvfwnggt
R27
R10
R3
R15
Z30 8D:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/common/vhdl/initcfg_xc.vhd
Z31 FD:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/common/vhdl/initcfg_xc.vhd
l0
L10
V2?T3^P2OBTEbBl7kLa]ZV1
R18
31
R19
Azgctkkxfnjk
R10
R3
DE work ffppvfwnggt 2?T3^P2OBTEbBl7kLa]ZV1
l81
L41
Vd[:gm<CekLZYe7k@kzP?40
R18
31
R12
R13
R19
Efmvgpwbdcxs
R24
R10
R3
R15
R25
R26
l0
L10
V^;oR03c;N;TL;k5:KO3@51
R18
31
R19
Atwzmfpzvmcf
R10
R3
DE work fmvgpwbdcxs ^;oR03c;N;TL;k5:KO3@51
l123
L39
V2AMbOo]VKIcER_DI<8f<a1
R18
31
R12
R13
R19
Egpbdjfttbjd
R27
R10
R3
R15
Z32 8D:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/common/vhdl/initcfg_xe.vhd
Z33 FD:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/common/vhdl/initcfg_xe.vhd
l0
L10
VcW^9CShP8ci]Q3<5g5hea0
R18
31
R19
Azsftcmnmkdb
R10
R3
DE work gpbdjfttbjd cW^9CShP8ci]Q3<5g5hea0
l18
L15
VCTA3gI[5X:Ga1fjeP;eLU1
R18
31
R12
R13
R19
Egrwzcnqmqzm
Z34 w1150886466
R10
R3
R15
Z35 8D:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/common/vhdl/initcfg.vhd
Z36 FD:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/common/vhdl/initcfg.vhd
l0
L10
VHmYN06B6[K5O4Di5GG<4e2
R18
31
R19
Amjtkskcsjhk
R10
R3
DE work grwzcnqmqzm HmYN06B6[K5O4Di5GG<4e2
l213
L142
VUj1hQ0<YPbd1g_LKaEoXC3
R18
31
R12
R13
R19
Einitcfg
R34
R10
R3
R15
R35
R36
l0
L585
V0D1:5dn?b5M09noa:m?RJ2
R18
31
R19
Abehavior
R10
R3
DE work initcfg 0D1:5dn?b5M09noa:m?RJ2
l850
L718
VEPK1RQN;=_7a0[OTY<D=h0
R18
31
R12
R13
R19
Einitcfg_xa
R27
R10
R3
R15
Z37 8D:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/common/vhdl/initcfg_xa.vhd
Z38 FD:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/common/vhdl/initcfg_xa.vhd
l0
L57
VcJHLT;B]MWmQgR8XjEBaZ2
R18
31
R19
Abehavior
R10
R3
DE work initcfg_xa cJHLT;B]MWmQgR8XjEBaZ2
l75
L66
VAcEO5dWmncMW<czmB:9bV0
R18
31
R12
R13
R19
Einitcfg_xb
R27
R10
R3
R15
Z39 8D:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/common/vhdl/initcfg_xb.vhd
Z40 FD:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/common/vhdl/initcfg_xb.vhd
l0
L71
V^lW]JJ4kEA0>d>9485@I_1
R18
31
R19
Abehavior
R10
R3
DE work initcfg_xb ^lW]JJ4kEA0>d>9485@I_1
l89
L79
VN1I<>P>?ZPke_1?9C6]2a3
R18
31
R12
R13
R19
Einitcfg_xc
R27
R10
R3
R15
R30
R31
l0
L155
VnY_fLbIC1g1=a_=SLgd713
R18
31
R19
Abehavior
R10
R3
DE work initcfg_xc nY_fLbIC1g1=a_=SLgd713
l211
L179
Vk_Kha8>UMJ9SO@Y@M9XPQ2
R18
31
R12
R13
R19
Einitcfg_xd
R27
R10
R3
R15
R28
R29
l0
L56
VLMi4PZXG[2lefUog:K<=H2
R18
31
R19
Abehavior
R10
R3
DE work initcfg_xd LMi4PZXG[2lefUog:K<=H2
l69
L62
V^4@mz`OX@AnM5?cf6NB;20
R18
31
R12
R13
R19
Einitcfg_xe
R27
R10
R3
R15
R32
R33
l0
L27
Vdz4;C6VFVCg=@WFGMmCR]2
R18
31
R19
Abehavior
R10
R3
DE work initcfg_xe dz4;C6VFVCg=@WFGMmCR]2
l35
L31
VA_iTPDIAN6c_E10;kIfRn0
R18
31
R12
R13
R19
Einitcfg_xf
R27
R10
R3
R15
Z41 8D:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/common/vhdl/initcfg_xf.vhd
Z42 FD:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/common/vhdl/initcfg_xf.vhd
l0
L37
VE<9EEa?zO<ejX_Ud__?iS3
R18
31
R19
Abehavior
R10
R3
DE work initcfg_xf E<9EEa?zO<ejX_Ud__?iS3
l47
L41
V1g2XJW:Rc7;6H=cLLeAUA1
R18
31
R12
R13
R19
Ejhmkpjjmdkx
R27
R10
R3
R15
R41
R42
l0
L10
VX@52IVSTb2>g[1bm3bI;41
R18
31
R19
Abmnqpbgpmvq
R10
R3
DE work jhmkpjjmdkx X@52IVSTb2>g[1bm3bI;41
l23
L15
VRM:YST7i@b=T8Vdc=FIN43
R18
31
R12
R13
R19
Envm_sysm
Z43 w1168555402
R3
R15
Z44 8D:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/NVM_sysm/NVM_sysm.vhd
Z45 FD:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/NVM_sysm/NVM_sysm.vhd
l0
L7
V721EmkTKkZdPW>MO>hM9l1
R18
31
R19
Adef_arch
R3
DE work nvm_sysm 721EmkTKkZdPW>MO>hM9l1
l142
L17
Vj095h9DO5_T3;T65K1Di<2
R18
31
R8
R19
Envm_sysm_init_wrapper
R43
R10
R3
R15
Z46 8D:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/NVM_sysm/NVM_sysm_init_wrapper.vhd
Z47 FD:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/smartgen/NVM_sysm/NVM_sysm_init_wrapper.vhd
l0
L127
V?VC]We5>_@D]I__gQGBz82
R18
31
R19
Adef_arch
R10
R3
DE work nvm_sysm_init_wrapper ?VC]We5>_@D]I__gQGBz82
l575
L187
VXFOCCIGeF[ek:M6Tc:SPF1
R18
31
R12
R13
R19
Estimulus
Z48 w1168569074
Z49 DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
Z50 DP ieee vital_timing OBWK>;kUYmkG<OChK2lhV1
Z51 DP fusion analog_io 30[hPIYIOGaU:iD_FYaHL0
Z52 DP ieee numeric_bit K1ChclJ;R]bj:<QN8`za13
Z53 DP ieee math_real zjAF7SKfg_RPI0GT^n1N`1
Z54 DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
Z55 DP ieee std_logic_textio 8YS?iX`WD1REQG`ZRYQGB2
Z56 DP std textio K]Z^fghZ6B=BjnK5NomDT3
Z57 DP syncad_vhdl_lib tbdefinitions PMU4]dAG[[aiNNb<^FQc11
R3
R15
Z58 8D:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/stimulus/Top_tbench.vhd
Z59 FD:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/stimulus/Top_tbench.vhd
l0
L45
VD1aFTYa14F4=F;XQLD[CH1
R18
31
R19
Astimulator
DE syncad_vhdl_lib tb_clock_minmax aM]9B9_YHE>hN00bcbDcf1
R49
R50
R51
R52
R53
R54
R55
R56
R57
R3
Z60 DE work stimulus D1aFTYa14F4=F;XQLD[CH1
l111
L74
V;f6<3l>G5eCe:f2AImWh^2
R18
31
Z61 M10 ieee std_logic_1164
Z62 M9 syncad_vhdl_lib tbdefinitions
Z63 M8 std textio
Z64 M7 ieee std_logic_textio
Z65 M6 ieee std_logic_arith
Z66 M5 ieee math_real
Z67 M4 ieee numeric_bit
Z68 M3 fusion analog_io
Z69 M2 ieee vital_timing
Z70 M1 ieee std_logic_unsigned
R19
Estnpfdkggvx
R27
R10
R3
R15
R37
R38
l0
L11
VRPiWP1<Oz9ZXSiJIbV4Z`1
R18
31
R19
Azkzbcmxmrjf
R10
R3
DE work stnpfdkggvx RPiWP1<Oz9ZXSiJIbV4Z`1
l30
L21
VUDiRMGAEBE7@4bVYJf?ck3
R18
31
R12
R13
R19
Etestbench
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R3
R15
R58
R59
l0
L1697
V8OakGgC6dmfFaLYgHEBn>0
R18
31
R19
Atbgeneratedcode
Z71 DE work top ET==VCLA1LS[FYcbD8f^13
R60
R49
R50
R51
R52
R53
R54
R55
R56
R57
R3
DE work testbench 8OakGgC6dmfFaLYgHEBn>0
l1727
L1699
VBP@T_XSi2dRB7fTAC5G0I2
R18
31
R61
R62
R63
R64
R65
R66
R67
R68
R69
R70
R19
Etop
Z72 w1201748957
R54
R49
R3
R15
Z73 8D:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/hdl/Top.vhd
Z74 FD:/backup/Projects/Fusion_Projects/Design Example/throughput enhancement/Fusion_ADC_Throughput/hdl/Top.vhd
l0
L7
VET==VCLA1LS[FYcbD8f^13
R18
31
R19
Artl
R54
R49
R3
R71
l94
L18
V:NQ@RCYj`8^^dKGbVn:[K2
R18
31
Z75 M3 ieee std_logic_1164
M2 ieee std_logic_unsigned
Z76 M1 ieee std_logic_arith
R19
Ewbsfnwwctpn
R27
R10
R3
R15
R39
R40
l0
L11
VczQVUaA6@^?;lKTFP_hz[0
R18
31
R19
Ammwvfpfbppr
R10
R3
DE work wbsfnwwctpn czQVUaA6@^?;lKTFP_hz[0
l34
L23
VQB4=T3D8fARWzkGBi[]l[2
R18
31
R12
R13
R19
