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<doc>
<title>Configuration report for IGLOO2_Oversampling_CCC_0_</title>
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<table>
<header>
</header>
<row>
 <cell>Date:</cell>
 <cell>Fri Apr 11 17:04:18 2014</cell>
</row>
<separator/>
<row>
 <cell>Design:</cell>
 <cell>IGLOO2_Oversampling</cell>
</row>
<row>
 <cell>Instance:</cell>
 <cell>CCC_0</cell>
</row>
<row>
 <cell>Family:</cell>
 <cell>IGLOO2</cell>
</row>
<row>
 <cell>Die:</cell>
 <cell>M2GL010T</cell>
</row>
<row>
 <cell>Package:</cell>
 <cell>484 FBGA</cell>
</row>
</table>
<text></text>
<section>
<name>Outputs Configuration Summary</name>
<table>
<header>
 <cell>Name</cell>
 <cell>Type</cell>
 <cell>Source</cell>
 <cell>Source Frequency</cell>
 <cell>Required Output Frequency</cell>
 <cell>Actual Output Frequency</cell>
 <cell>Divider</cell>
</header>
<row>
 <cell>GL0</cell>
 <cell>primary clock</cell>
 <cell>PLL (0)</cell>
 <cell>250 MHz</cell>
 <cell>50 MHz</cell>
 <cell>50 MHz</cell>
 <cell>5 (GPD0)</cell>
</row>
<separator/>
<row>
 <cell>GL3</cell>
 <cell>primary clock</cell>
 <cell>PLL (0)</cell>
 <cell>250 MHz</cell>
 <cell>125 MHz</cell>
 <cell>125 MHz</cell>
 <cell>2 (GPD1)</cell>
</row>
<separator/>
</table>
</section>
<section>
<name>PLL Configuration Summary</name>
<table>
<header>
</header>
<row>
 <cell>Reference clock frequency</cell>
 <cell>50 MHz</cell>
</row>
<row>
 <cell>Reference clock source</cell>
 <cell>FPGA Fabric Input 0</cell>
</row>
<row>
 <cell>Output frequency</cell>
 <cell>250 MHz</cell>
</row>
<row>
 <cell>VCO frequency</cell>
 <cell>500 MHz</cell>
</row>
<separator/>
<row>
 <cell>PLL reference clock divider</cell>
 <cell>1</cell>
</row>
<row>
 <cell>CCC reference clock divider</cell>
 <cell>2</cell>
</row>
<separator/>
<row>
 <cell>Feedback source</cell>
 <cell>CCC Internal</cell>
</row>
<row>
 <cell>PLL feedback divider</cell>
 <cell>1</cell>
</row>
<row>
 <cell>CCC feedback divider</cell>
 <cell>10</cell>
</row>
<row>
 <cell>External feedback divider</cell>
 <cell>--</cell>
</row>
<separator/>
<row>
 <cell>PLL VCO divider</cell>
 <cell>2</cell>
</row>
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<row>
 <cell>Lock counter</cell>
 <cell>1024 cycles</cell>
</row>
<row>
 <cell>Lock window</cell>
 <cell>8000 ppm</cell>
</row>
<separator/>
<row>
 <cell>Spread Spectrum Modulation</cell>
 <cell>Disable</cell>
</row>
<row>
 <cell>Required Spread Spectrum Modulation Frequency</cell>
 <cell>--</cell>
</row>
<row>
 <cell>Actual Spread Spectrum Modulation Frequency</cell>
 <cell>--</cell>
</row>
<row>
 <cell>Spread Spectrum Modulation Depth</cell>
 <cell>--</cell>
</row>
</table>
</section>
<section>
<name>CCC Registers Reset Value</name>
<table>
<header>
 <cell>Register Name</cell>
 <cell>Address</cell>
 <cell>Value</cell>
</header>
<row>
 <cell>AD_CFG_CTL</cell>
 <cell>0x00</cell>
 <cell>0x00</cell>
</row>
<row>
 <cell>AD_CFG_RFD0</cell>
 <cell>0x01</cell>
 <cell>0x0c</cell>
</row>
<row>
 <cell>AD_CFG_RFD1</cell>
 <cell>0x02</cell>
 <cell>0x01</cell>
</row>
<row>
 <cell>AD_CFG_FDB0</cell>
 <cell>0x03</cell>
 <cell>0x07</cell>
</row>
<row>
 <cell>AD_CFG_FDB1</cell>
 <cell>0x04</cell>
 <cell>0x09</cell>
</row>
<row>
 <cell>AD_CFG_FDB2</cell>
 <cell>0x05</cell>
 <cell>0x00</cell>
</row>
<row>
 <cell>AD_CFG_GLM0</cell>
 <cell>0x06</cell>
 <cell>0x08</cell>
</row>
<row>
 <cell>AD_CFG_GLM1</cell>
 <cell>0x07</cell>
 <cell>0x18</cell>
</row>
<row>
 <cell>AD_CFG_GLM2</cell>
 <cell>0x08</cell>
 <cell>0x18</cell>
</row>
<row>
 <cell>AD_CFG_GLM3</cell>
 <cell>0x09</cell>
 <cell>0x18</cell>
</row>
<row>
 <cell>AD_CFG_GLM4</cell>
 <cell>0x0a</cell>
 <cell>0x18</cell>
</row>
<row>
 <cell>AD_CFG_GLM5</cell>
 <cell>0x0b</cell>
 <cell>0x18</cell>
</row>
<row>
 <cell>AD_CFG_GLM6</cell>
 <cell>0x0c</cell>
 <cell>0x09</cell>
</row>
<row>
 <cell>AD_CFG_GLM7</cell>
 <cell>0x0d</cell>
 <cell>0x18</cell>
</row>
<row>
 <cell>AD_CFG_GPDS0</cell>
 <cell>0x0e</cell>
 <cell>0x47</cell>
</row>
<row>
 <cell>AD_CFG_GPDS1</cell>
 <cell>0x0f</cell>
 <cell>0x47</cell>
</row>
<row>
 <cell>AD_CFG_GPDS2</cell>
 <cell>0x10</cell>
 <cell>0x58</cell>
</row>
<row>
 <cell>AD_CFG_GPDS3</cell>
 <cell>0x11</cell>
 <cell>0x58</cell>
</row>
<row>
 <cell>AD_CFG_GPDV0</cell>
 <cell>0x12</cell>
 <cell>0x05</cell>
</row>
<row>
 <cell>AD_CFG_GPDV1</cell>
 <cell>0x13</cell>
 <cell>0x02</cell>
</row>
<row>
 <cell>AD_CFG_GPDV2</cell>
 <cell>0x14</cell>
 <cell>0x01</cell>
</row>
<row>
 <cell>AD_CFG_GPDV3</cell>
 <cell>0x15</cell>
 <cell>0x01</cell>
</row>
<row>
 <cell>AD_CFG_PLL0</cell>
 <cell>0x16</cell>
 <cell>0x04</cell>
</row>
<row>
 <cell>AD_CFG_PLL1</cell>
 <cell>0x17</cell>
 <cell>0x05</cell>
</row>
<row>
 <cell>AD_CFG_PLL2</cell>
 <cell>0x18</cell>
 <cell>0x00</cell>
</row>
<row>
 <cell>AD_CFG_PLL3</cell>
 <cell>0x19</cell>
 <cell>0x01</cell>
</row>
<row>
 <cell>AD_CFG_PLL4</cell>
 <cell>0x1a</cell>
 <cell>0x00</cell>
</row>
<row>
 <cell>AD_CFG_PLL5</cell>
 <cell>0x1b</cell>
 <cell>0x02</cell>
</row>
<row>
 <cell>AD_CFG_PLL6</cell>
 <cell>0x1c</cell>
 <cell>0x00</cell>
</row>
<row>
 <cell>AD_CFG_PLL7</cell>
 <cell>0x1d</cell>
 <cell>0x00</cell>
</row>
<row>
 <cell>AD_CFG_PLL8</cell>
 <cell>0x1e</cell>
 <cell>0x01</cell>
</row>
<row>
 <cell>AD_CFG_PLL9</cell>
 <cell>0x1f</cell>
 <cell>0x00</cell>
</row>
<row>
 <cell>AD_CFG_PLL10</cell>
 <cell>0x20</cell>
 <cell>0x00</cell>
</row>
<row>
 <cell>AD_CFG_PLL11</cell>
 <cell>0x21</cell>
 <cell>0x07</cell>
</row>
<row>
 <cell>AD_CFG_SYN0</cell>
 <cell>0x22</cell>
 <cell>0x03</cell>
</row>
<row>
 <cell>AD_CFG_SYN1</cell>
 <cell>0x23</cell>
 <cell>0x03</cell>
</row>
<row>
 <cell>AD_CFG_SYN2</cell>
 <cell>0x24</cell>
 <cell>0x02</cell>
</row>
<row>
 <cell>AD_CFG_SYN3</cell>
 <cell>0x25</cell>
 <cell>0x02</cell>
</row>
<row>
 <cell>AD_CFG_PLLD</cell>
 <cell>0x26</cell>
 <cell>0x40</cell>
</row>
<row>
 <cell>AD_CFG_OVW0</cell>
 <cell>0x27</cell>
 <cell>0x00</cell>
</row>
<row>
 <cell>AD_CFG_OVW1</cell>
 <cell>0x28</cell>
 <cell>0x00</cell>
</row>
<row>
 <cell>AD_CFG_OVW2</cell>
 <cell>0x29</cell>
 <cell>0x00</cell>
</row>
<row>
 <cell>AD_CFG_OVW3</cell>
 <cell>0x2a</cell>
 <cell>0x00</cell>
</row>
</table>
</section>
<text></text>
</doc>
