# Actel Physical design constraints file

# Version: v11.3 11.3.0.112

# Design Name: IGLOO2_Oversampling_top 

# Input Netlist Format: EDIF 

# Family: IGLOO2 , Die: M2GL010T , Package: 484 FBGA , Speed grade: -1 

# Date generated: Fri Apr 18 09:32:10 2014 


#
# I/O constraints
#

set_io CLK0 -DIRECTION INPUT -pinname K1 -fixed no
set_io RX -DIRECTION INPUT -pinname G18 -fixed no
set_io TX -DIRECTION OUTPUT -pinname H19 -fixed no
set_io connect_o -DIRECTION OUTPUT -pinname H5 -fixed no
set_io start -DIRECTION OUTPUT -pinname H6 -fixed no

#
# Core cell constraints
#

set_location Transmitter_0/prbs7_10_0/LFSR\[6\] -fixed no 270 7
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[14\] -fixed no 285 61
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_cnt.xmit_bit_sel_3_i_0_o2\[2\] -fixed no 208 24
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1\[2\] -fixed no 84 28
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[0\] -fixed no 244 51
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[12\] -fixed no 55 28
set_location Transmitter_0/prbs7_10_0/W_0_x2\[7\] -fixed no 265 6
set_location IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0\[4\] -fixed no 358 43
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state\[4\] -fixed no 275 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_i_a3\[6\] -fixed no 294 57
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_state_ns_0\[5\] -fixed no 212 24
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[17\] -fixed no 258 52
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_7 -fixed no 358 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/envm_soft_reset\[0\] -fixed no 291 43
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[22\] -fixed no 350 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/bytecount\[6\] -fixed no 294 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_bytecount\[8\] -fixed no 296 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[27\] -fixed no 344 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[23\] -fixed no 347 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_bytecount4_3_RNIJNPS -fixed no 270 57
set_location UART_INTERFACE_0/FabUART_0/uart_data_out_t\[4\] -fixed no 187 22
set_location UART_INTERFACE_0/COREUART_0/genblk1.RXRDY4 -fixed no 234 12
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/prdata_0_iv_0\[0\] -fixed no 382 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_haddr_fetch_0_sqmuxa_1 -fixed no 268 57
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2_RNI9VUQ\[0\] -fixed no 277 45
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_state\[0\] -fixed no 240 13
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg_en_2\[10\] -fixed no 390 48
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR\[17\] -fixed no 278 45
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_tr10 -fixed no 281 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_count_0_sqmuxa_1 -fixed no 322 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_0_a3\[13\] -fixed no 303 51
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_state_ns_0\[0\] -fixed no 240 12
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/cntr_2bit_zero_RNO -fixed no 120 24
set_location UART_INTERFACE_0/FabUART_0/state\[12\] -fixed no 200 22
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out_7_0\[4\] -fixed no 260 3
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[30\] -fixed no 268 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[17\] -fixed no 241 49
set_location UART_INTERFACE_0/FabUART_0/uart_data_out_t_22_i_a2_1\[0\] -fixed no 191 21
set_location Transmitter_0/FIFO_PRBS_0/data\[24\] -fixed no 262 4
set_location Transmitter_0/prbs7_10_0/tx_count\[1\] -fixed no 271 10
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/mux_sel\[0\] -fixed no 98 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata_RNITITA6\[0\] -fixed no 360 60
set_location UART_INTERFACE_0/FabUART_0/un21_i_a2_i -fixed no 213 15
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[2\] -fixed no 79 31
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/paddr\[8\] -fixed no 354 46
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[12\] -fixed no 320 46
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR\[20\] -fixed no 286 48
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[16\] -fixed no 358 46
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[18\] -fixed no 343 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_sqmuxa_4_RNI8TH41 -fixed no 280 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_count_2_sqmuxa_RNIUMB67 -fixed no 314 60
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/d_masterRegAddrSel -fixed no 295 48
set_location UART_INTERFACE_0/FabUART_0/clear_t -fixed no 192 16
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_bit_sel\[2\] -fixed no 214 25
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PSLVERR -fixed no 399 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state\[17\] -fixed no 307 58
set_location UART_INTERFACE_0/COREUART_0/make_RX/samples\[0\] -fixed no 247 13
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL\[13\] -fixed no 308 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_haddr_write11 -fixed no 293 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1_RNIIKIR1\[22\] -fixed no 316 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/cntr_2bit_4_iv_0\[1\] -fixed no 121 24
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg_ldmx\[14\] -fixed no 379 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[29\] -fixed no 348 52
set_location Receiver_0/prbs7_10_0/un1_lock_count13_i_0 -fixed no 126 18
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO\[17\] -fixed no 374 48
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_2 -fixed no 367 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD3\[9\] -fixed no 87 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[29\] -fixed no 346 58
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns\[22\] -fixed no 88 27
set_location Receiver_0/Downsampler_0/reg_check\[2\] -fixed no 75 25
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[4\] -fixed no 279 46
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[3\] -fixed no 343 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_d_count_2_sqmuxa -fixed no 315 60
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1_RNO\[5\] -fixed no 101 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR_RNO\[3\] -fixed no 243 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[21\] -fixed no 82 28
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state\[16\] -fixed no 296 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[2\] -fixed no 339 63
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt\[12\] -fixed no 307 49
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/state_s0_0_a2_0_a2 -fixed no 390 51
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[29\] -fixed no 61 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[13\] -fixed no 262 61
set_location Receiver_0/Downsampler_0/reg_check\[9\] -fixed no 92 28
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D0\[3\] -fixed no 88 31
set_location Receiver_0/Downsampler_0/reg_check\[5\] -fixed no 107 22
set_location FCCC_0/GL1_INST -fixed no 223 54
set_location UART_INTERFACE_0/FabUART_0/un21_i_a2_i_a2_1 -fixed no 214 15
set_location UART_INTERFACE_0/COREUART_0/make_TX/tx_RNO -fixed no 215 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[5\] -fixed no 284 64
set_location Receiver_0/prbs7_10_0/reg_error_out_ldmx -fixed no 187 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_bytecount\[7\] -fixed no 308 60
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg_ldmx\[9\] -fixed no 389 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns\[19\] -fixed no 104 27
set_location IGLOO2_Oversampling_0/ConfigMaster_0/bytecount\[10\] -fixed no 297 64
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR\[25\] -fixed no 328 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_0\[2\] -fixed no 286 57
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt\[5\] -fixed no 304 49
set_location UART_INTERFACE_0/COREUART_0/make_TX/tx_byte\[0\] -fixed no 207 25
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg_ldmx\[12\] -fixed no 392 57
set_location IGLOO2_Oversampling_0/CORERESETP_0/init_done_clk_base_0_sqmuxa -fixed no 374 42
set_location UART_INTERFACE_0/COREUART_0/make_RX/rcv_cnt.receive_count_3\[3\] -fixed no 244 12
set_location UART_INTERFACE_0/COREUART_0/make_RX/receive_shift.rx_shift_11\[2\] -fixed no 211 12
set_location UART_INTERFACE_0/COREUART_0/make_TX/tx_byte\[4\] -fixed no 211 25
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/paddr\[4\] -fixed no 370 46
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out\[3\] -fixed no 259 4
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg_ldmx\[11\] -fixed no 386 57
set_location Transmitter_0/prbs7_10_0/tx_count\[0\] -fixed no 272 10
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[9\] -fixed no 350 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[23\] -fixed no 285 52
set_location Receiver_0/Downsampler_0/reg_data_out\[4\] -fixed no 113 19
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[9\] -fixed no 316 46
set_location Receiver_0/Downsampler_0/reg_check\[7\] -fixed no 105 22
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[16\] -fixed no 373 49
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[5\] -fixed no 352 46
set_location Receiver_0/Downsampler_0/temp_data\[0\] -fixed no 108 22
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg236_1 -fixed no 98 27
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/un1_D0_7 -fixed no 62 24
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/state\[0\] -fixed no 389 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[4\] -fixed no 328 52
set_location Receiver_0/AND3_0 -fixed no 138 15
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_17 -fixed no 342 51
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[17\] -fixed no 374 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[14\] -fixed no 285 60
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHWRITE -fixed no 330 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[11\] -fixed no 336 61
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[23\] -fixed no 347 64
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_m0\[13\] -fixed no 84 21
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2\[4\] -fixed no 92 22
set_location Receiver_0/Downsampler_0/reg_check_12\[9\] -fixed no 92 27
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_state128_0_I_26_i_x2 -fixed no 363 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[27\] -fixed no 350 61
set_location Receiver_0/Downsampler_0/reg_check_12\[8\] -fixed no 76 27
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[18\] -fixed no 81 16
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[30\] -fixed no 264 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/pause_count\[2\] -fixed no 297 43
set_location IGLOO2_Oversampling_0/ConfigMaster_0/bytecount\[12\] -fixed no 318 64
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHTRANS -fixed no 300 46
set_location UART_INTERFACE_0/COREUART_0/make_RX/receive_full_int -fixed no 234 13
set_location Receiver_0/prbs7_10_0/LFSR_RNO\[1\] -fixed no 119 21
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11s2 -fixed no 100 27
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_state128_0_I_32_i_0_x2 -fixed no 361 57
set_location Transmitter_0/prbs7_10_0/W_0_x2\[1\] -fixed no 267 6
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[21\] -fixed no 340 52
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNIDO2L\[0\] -fixed no 383 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[15\] -fixed no 275 61
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/un1_D0_5 -fixed no 64 30
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_sqmuxa -fixed no 287 57
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[24\] -fixed no 405 58
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[24\] -fixed no 65 22
set_location UART_INTERFACE_0/FabUART_0/state\[16\] -fixed no 202 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[13\] -fixed no 333 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[5\] -fixed no 340 66
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[11\] -fixed no 59 25
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PREADY_ldmx -fixed no 388 51
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg\[12\] -fixed no 392 58
set_location IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB -fixed no 397 92
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_bytecount_2_sqmuxa -fixed no 313 48
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/rx_val_debug -fixed no 71 25
set_location UART_INTERFACE_0/FabUART_0/state_RNO\[17\] -fixed no 186 21
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1_RNO\[2\] -fixed no 85 27
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_pause_count_1_sqmuxa_1_i_0 -fixed no 292 42
set_location UART_INTERFACE_0/FabUART_0/state_RNO\[3\] -fixed no 198 21
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[27\] -fixed no 70 19
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL\[8\] -fixed no 306 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_state128_0_I_20_i_0_x2 -fixed no 357 57
set_location Receiver_0/prbs7_10_0/rx_count_ns_i_i_a2\[1\] -fixed no 123 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[28\] -fixed no 260 58
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[22\] -fixed no 327 49
set_location UART_INTERFACE_0/FabUART_0/state\[17\] -fixed no 186 22
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/prdata_0_iv_0\[10\] -fixed no 383 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[20\] -fixed no 74 22
set_location UART_INTERFACE_0/COREUART_0/make_RX/receive_count\[2\] -fixed no 245 13
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[18\] -fixed no 378 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[29\] -fixed no 341 58
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D0\[9\] -fixed no 71 28
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/xmit_pulse -fixed no 207 21
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD3\[0\] -fixed no 97 31
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD3\[4\] -fixed no 90 22
set_location Receiver_0/receive_buffer_top_0/receive_control_0/RC_FSM_state_ns_0\[0\] -fixed no 68 24
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_bit_cnt\[2\] -fixed no 230 13
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[7\] -fixed no 81 31
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_0_i_o2\[7\] -fixed no 315 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[16\] -fixed no 365 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[7\] -fixed no 279 63
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2_9_4 -fixed no 309 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[4\] -fixed no 266 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[23\] -fixed no 284 52
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[19\] -fixed no 77 22
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[0\] -fixed no 70 28
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[28\] -fixed no 371 61
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1\[0\] -fixed no 90 28
set_location UART_INTERFACE_0/FabUART_0/state\[4\] -fixed no 182 22
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr\[10\] -fixed no 257 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/pause_count_RNO\[0\] -fixed no 297 42
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_m0\[17\] -fixed no 91 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/pause_count_n3_0_1901_o4 -fixed no 301 42
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HWRITE51 -fixed no 289 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[2\] -fixed no 329 61
set_location Receiver_0/AND3_0_RNI7UKC -fixed no 224 54
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[21\] -fixed no 262 52
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/prdata_0_iv_0_a2_0_2\[0\] -fixed no 384 48
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/make_xmit_clock.xmit_cntr_3_1.SUM\[2\] -fixed no 207 18
set_location Receiver_0/prbs7_10_0/lock_count_RNO\[0\] -fixed no 125 18
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out_7\[5\] -fixed no 255 3
set_location UART_INTERFACE_0/FabUART_0/genrate_err_t_3_iv_i -fixed no 193 15
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[6\] -fixed no 77 25
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD3_13\[2\] -fixed no 85 30
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[6\] -fixed no 277 46
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/un1_D0_4 -fixed no 63 24
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[17\] -fixed no 248 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[10\] -fixed no 331 61
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre37_0_a2_0 -fixed no 320 48
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/enable_lock5 -fixed no 71 24
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNI7I2L\[0\] -fixed no 393 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO\[3\] -fixed no 251 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_RNIE5BH3\[7\] -fixed no 322 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_RNO\[20\] -fixed no 288 42
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[0\] -fixed no 324 61
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/R_SDIF0_PSEL_1_0_a2 -fixed no 386 51
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHSIZE\[1\] -fixed no 331 49
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/INIT_DONE_q1 -fixed no 367 46
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[13\] -fixed no 261 61
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_2\[8\] -fixed no 283 60
set_location Receiver_0/Downsampler_0/reg_error -fixed no 90 19
set_location IGLOO2_Oversampling_0/CORERESETP_0/RESET_N_M2F_clk_base -fixed no 365 49
set_location Receiver_0/prbs7_10_0/reg_error\[3\] -fixed no 184 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[8\] -fixed no 331 58
set_location UART_INTERFACE_0/COREUART_0/make_TX/tx_byte\[2\] -fixed no 210 25
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/DA_FSM_STATE_ns_1_0_.N_10_i -fixed no 107 24
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_i_a3_0\[9\] -fixed no 272 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/DA_FSM_STATE\[0\] -fixed no 104 25
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out_7\[2\] -fixed no 253 3
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[14\] -fixed no 314 64
set_location Transmitter_0/prbs7_10_0/LFSR\[8\] -fixed no 265 7
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata_RNIGVEG6\[15\] -fixed no 350 63
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[19\] -fixed no 54 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[12\] -fixed no 367 61
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[20\] -fixed no 283 49
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg_RNIFN1F\[1\] -fixed no 402 57
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR\[29\] -fixed no 311 45
set_location Receiver_0/prbs7_10_0/lock_count\[1\] -fixed no 129 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_state128_0_I_14_i_0_x2 -fixed no 352 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[20\] -fixed no 285 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[5\] -fixed no 276 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_i_i\[5\] -fixed no 307 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[27\] -fixed no 271 58
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_filtered.m3 -fixed no 248 12
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/prdata_0_iv_0\[2\] -fixed no 380 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_d_haddr_fetch_0_sqmuxa -fixed no 282 57
set_location Receiver_0/prbs7_10_0/reg_error\[2\] -fixed no 183 19
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/prdata_0_iv_0_RNO_0\[0\] -fixed no 385 48
set_location Transmitter_0/Replicator_0/X\[0\] -fixed no 257 7
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[3\] -fixed no 303 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_bytecount\[2\] -fixed no 292 63
set_location IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_enable_RNO -fixed no 372 42
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[28\] -fixed no 69 19
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/state\[1\] -fixed no 384 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_RNO\[7\] -fixed no 314 57
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0\[1\] -fixed no 303 45
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[29\] -fixed no 356 66
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[9\] -fixed no 77 31
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[21\] -fixed no 268 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[25\] -fixed no 280 52
set_location UART_INTERFACE_0/COREUART_0/make_RX/receive_shift.rx_shift_11\[6\] -fixed no 210 12
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state\[15\] -fixed no 300 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[8\] -fixed no 275 64
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[22\] -fixed no 88 28
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[18\] -fixed no 259 52
set_location Receiver_0/Downsampler_0/reg_check_12\[5\] -fixed no 107 21
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg_ldmx\[4\] -fixed no 373 57
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[7\] -fixed no 350 46
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable -fixed no 294 48
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_state\[1\] -fixed no 241 13
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[2\] -fixed no 269 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[19\] -fixed no 347 58
set_location UART_INTERFACE_0/FabUART_0/clear_t_3_iv_0_o4 -fixed no 208 15
set_location UART_INTERFACE_0/FabUART_0/un1_uart_oen_t_0_sqmuxa_1_0_1 -fixed no 215 15
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_state\[3\] -fixed no 213 25
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[12\] -fixed no 370 52
set_location UART_INTERFACE_0/FabUART_0/state_3_sqmuxa_0_a2_2_a2 -fixed no 197 15
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[5\] -fixed no 71 31
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns\[28\] -fixed no 93 27
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/mux_sel_RNO\[2\] -fixed no 95 24
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/MADDRREADY_1_iv\[0\] -fixed no 292 48
set_location Receiver_0/prbs7_10_0/un1_lock_count13_i_o2_0_4 -fixed no 117 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/busy -fixed no 290 46
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[23\] -fixed no 359 46
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[18\] -fixed no 242 49
set_location UART_INTERFACE_0/FabUART_0/un1_start_t17_3_0_o2_0 -fixed no 207 15
set_location UART_INTERFACE_0/FabUART_0/uart_data_out_t_22_i_a2_0_0\[0\] -fixed no 184 21
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD3_13\[4\] -fixed no 90 21
set_location Transmitter_0/prbs7_10_0/LFSR\[4\] -fixed no 264 7
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/GATEDHTRANS -fixed no 300 45
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_i_o3_0_2_i_a2\[5\] -fixed no 319 48
set_location IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0\[8\] -fixed no 362 43
set_location Receiver_0/prbs7_10_0/un1_lock_count13_i_o2_0_6 -fixed no 115 18
set_location Receiver_0/prbs7_10_0/lock_count\[0\] -fixed no 125 19
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState\[2\] -fixed no 297 46
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out_7\[3\] -fixed no 261 3
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[3\] -fixed no 81 28
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[17\] -fixed no 245 52
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD3_13\[0\] -fixed no 97 30
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[10\] -fixed no 332 61
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[23\] -fixed no 285 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[6\] -fixed no 246 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[10\] -fixed no 286 63
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg_en_4\[10\] -fixed no 392 51
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg\[0\] -fixed no 315 49
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD3_RNO\[9\] -fixed no 61 18
set_location UART_INTERFACE_0/FabUART_0/clear_t_3_iv_i -fixed no 192 15
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/prdata_0_iv_0_RNO\[0\] -fixed no 387 48
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/trans_detect_bit9_0_sqmuxa -fixed no 67 27
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[9\] -fixed no 74 25
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/rx_data_debug\[3\] -fixed no 74 16
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[5\] -fixed no 84 31
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns_1\[19\] -fixed no 105 30
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[15\] -fixed no 315 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_rdata_0_sqmuxa -fixed no 329 51
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[16\] -fixed no 99 22
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D0\[2\] -fixed no 59 28
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[11\] -fixed no 330 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[9\] -fixed no 282 63
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNI0L5/U0_RGB1 -fixed no 218 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[10\] -fixed no 78 25
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D0\[7\] -fixed no 73 31
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[2\] -fixed no 380 58
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out_7\[9\] -fixed no 259 6
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_haddr_write19_1 -fixed no 299 60
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg\[9\] -fixed no 389 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[8\] -fixed no 280 61
set_location Receiver_0/prbs7_10_0/reg_lock_again5_0_a2_3 -fixed no 189 18
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNIOUKO\[0\] -fixed no 346 66
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[24\] -fixed no 354 61
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2_13\[2\] -fixed no 92 30
set_location IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int_RNICDJF_0/U0_RGB1 -fixed no 218 66
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg\[7\] -fixed no 376 58
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_shift\[1\] -fixed no 209 13
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata_RNI2PUA6\[7\] -fixed no 345 63
set_location Receiver_0/prbs7_10_0/LFSR_RNO\[4\] -fixed no 115 21
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr\[1\] -fixed no 248 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[2\] -fixed no 340 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0\[9\] -fixed no 281 63
set_location Receiver_0/Downsampler_0/temp_data_12\[4\] -fixed no 109 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[20\] -fixed no 370 63
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[4\] -fixed no 79 28
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[31\] -fixed no 317 58
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[16\] -fixed no 95 22
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns_1\[1\] -fixed no 71 18
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_27 -fixed no 353 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata_RNIVKTA6\[1\] -fixed no 342 66
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[15\] -fixed no 354 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[26\] -fixed no 356 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[19\] -fixed no 336 58
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_sel.tx_2_7_i_m2_am -fixed no 206 24
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_19 -fixed no 345 51
set_location UART_INTERFACE_0/COREUART_0/make_RX/receive_shift.rx_bit_cnt_4\[1\] -fixed no 236 12
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[6\] -fixed no 352 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[12\] -fixed no 277 61
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11\[23\] -fixed no 86 27
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[23\] -fixed no 284 51
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_m0\[2\] -fixed no 69 18
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_byte\[1\] -fixed no 209 16
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2\[2\] -fixed no 93 31
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt\[13\] -fixed no 308 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[13\] -fixed no 260 60
set_location Receiver_0/receive_buffer_top_0/receive_control_0/RX_VALIN_reg -fixed no 66 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_state_32_5 -fixed no 304 51
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg\[14\] -fixed no 379 58
set_location UART_INTERFACE_0/COREUART_0/make_RX/receive_shift.rx_bit_cnt_4\[0\] -fixed no 237 12
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HSIZE9 -fixed no 313 57
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2_RNITIUQ\[0\] -fixed no 285 45
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[0\] -fixed no 333 61
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[31\] -fixed no 352 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0\[10\] -fixed no 283 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_sqmuxa_4 -fixed no 317 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state\[0\] -fixed no 304 52
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out_7_0\[7\] -fixed no 258 3
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_bytecount\[6\] -fixed no 294 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/bytecount\[13\] -fixed no 323 64
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[4\] -fixed no 60 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_0_a3_0_5\[4\] -fixed no 273 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWRITE_RNO -fixed no 293 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/trans_detect_bit36 -fixed no 60 27
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[15\] -fixed no 54 25
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11\[10\] -fixed no 78 24
set_location IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_RNO\[0\] -fixed no 348 42
set_location IGLOO2_Oversampling_0/ConfigMaster_0/envm_busy\[0\] -fixed no 290 43
set_location Receiver_0/Downsampler_0/reg_data_out\[1\] -fixed no 111 19
set_location Transmitter_0/Replicator_0/X\[3\] -fixed no 260 7
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState\[3\] -fixed no 292 46
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2_13\[4\] -fixed no 92 21
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[4\] -fixed no 349 49
set_location Transmitter_0/FIFO_PRBS_0/data_0_sqmuxa_0_a3 -fixed no 266 3
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11\[2\] -fixed no 78 18
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNIAL2L\[0\] -fixed no 387 63
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11\[12\] -fixed no 100 21
set_location UART_INTERFACE_0/COREUART_0/make_RX/receive_count\[1\] -fixed no 249 13
set_location IGLOO2_Oversampling_0/CORERESETP_0/mss_reset_state -fixed no 364 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[8\] -fixed no 370 61
set_location UART_INTERFACE_0/FabUART_0/uart_oen_t -fixed no 215 16
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_sn.un1_RX_DATAOUT_reg252_sn_i_0 -fixed no 83 24
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_state_26_1 -fixed no 308 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2_13\[0\] -fixed no 100 30
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[3\] -fixed no 243 58
set_location IGLOO2_Oversampling_0/CORERESETP_0/mss_reset_select -fixed no 362 49
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[14\] -fixed no 378 58
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out\[2\] -fixed no 253 4
set_location IGLOO2_Oversampling_0/CCC_0/GL0_INST -fixed no 218 54
set_location UART_INTERFACE_0/FabUART_0/state_RNO\[16\] -fixed no 202 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[5\] -fixed no 305 64
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[2\] -fixed no 102 31
set_location UART_INTERFACE_0/FabUART_0/data_flag -fixed no 197 19
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO\[30\] -fixed no 401 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_i_a3_RNIUGV32\[6\] -fixed no 322 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[1\] -fixed no 254 58
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[14\] -fixed no 61 22
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg_ldmx\[6\] -fixed no 390 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[4\] -fixed no 369 63
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns\[6\] -fixed no 77 24
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[7\] -fixed no 377 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[21\] -fixed no 269 48
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/un1_D0_6 -fixed no 63 30
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1\[9\] -fixed no 83 19
set_location UART_INTERFACE_0/FabUART_0/state\[5\] -fixed no 183 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[6\] -fixed no 337 61
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[9\] -fixed no 75 31
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[31\] -fixed no 271 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[26\] -fixed no 357 58
set_location UART_INTERFACE_0/FabUART_0/start_t_3_iv_i_0 -fixed no 199 15
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[30\] -fixed no 265 49
set_location IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0\[2\] -fixed no 356 43
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PREADY -fixed no 388 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[24\] -fixed no 273 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[9\] -fixed no 352 67
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[4\] -fixed no 304 64
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/un9_count_hot_5 -fixed no 85 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[3\] -fixed no 245 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[27\] -fixed no 52 22
set_location Receiver_0/prbs7_10_0/un1_lock_count13_i_o2_0_RNIVE2N1 -fixed no 130 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[1\] -fixed no 325 52
set_location UART_INTERFACE_0/FabUART_0/genrate_err_t -fixed no 193 16
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[1\] -fixed no 343 67
set_location CFG0_GND_INST -fixed no 290 45
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D0\[4\] -fixed no 62 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HTRANS_0_sqmuxa -fixed no 307 60
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[29\] -fixed no 59 19
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[10\] -fixed no 101 25
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2_RNIVKUQ\[0\] -fixed no 315 45
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[18\] -fixed no 342 52
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[20\] -fixed no 72 22
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[27\] -fixed no 53 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/pause_count_RNO\[3\] -fixed no 296 42
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr\[2\] -fixed no 249 19
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_sn.m3_0 -fixed no 99 27
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_bit_cnt\[1\] -fixed no 236 13
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[11\] -fixed no 352 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[3\] -fixed no 365 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_bytecount\[11\] -fixed no 295 63
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_byte\[5\] -fixed no 206 16
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[26\] -fixed no 58 19
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11\[13\] -fixed no 102 21
set_location IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core -fixed no 349 43
set_location UART_INTERFACE_0/FabUART_0/un1_uart_data_out_t_0_sqmuxa_9_i_o4_1 -fixed no 201 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/count_RNIHIHO2_0\[1\] -fixed no 332 63
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[7\] -fixed no 92 31
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_3_1\[8\] -fixed no 308 45
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1\[7\] -fixed no 76 22
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[37\] -fixed no 49 25
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_m0\[16\] -fixed no 93 21
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/control_reg_29_0_a2_0_1 -fixed no 393 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[28\] -fixed no 261 58
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg_ldmx\[13\] -fixed no 375 57
set_location UART_INTERFACE_0/FabUART_0/state_ns_0\[12\] -fixed no 200 21
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_12 -fixed no 334 60
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNIQ0LO\[0\] -fixed no 371 63
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr\[6\] -fixed no 253 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[6\] -fixed no 335 52
set_location Receiver_0/prbs7_10_0/LFSR_RNO\[7\] -fixed no 118 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[24\] -fixed no 356 61
set_location Receiver_0/Downsampler_0/temp_data_12\[8\] -fixed no 110 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[14\] -fixed no 334 58
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[23\] -fixed no 404 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[20\] -fixed no 285 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[14\] -fixed no 285 58
set_location Receiver_0/Downsampler_0/reg_data_out\[7\] -fixed no 113 22
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/DA_FSM_STATE_ns_1_0_.m5_i_1 -fixed no 105 24
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/prdata_0_iv_0\[3\] -fixed no 397 57
set_location UART_INTERFACE_0/FabUART_0/uart_data_out_t_RNO\[3\] -fixed no 185 21
set_location IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core4 -fixed no 350 42
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2_RNID3VQ\[0\] -fixed no 281 45
set_location Receiver_0/prbs7_10_0/LFSR_RNO\[3\] -fixed no 111 21
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2_RNIB1VQ\[0\] -fixed no 313 45
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNI4F2L\[0\] -fixed no 356 63
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/DA_FSM_STATE_RNIEG3I\[1\] -fixed no 97 24
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[19\] -fixed no 243 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[26\] -fixed no 273 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/pause_count\[3\] -fixed no 296 43
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[28\] -fixed no 265 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[9\] -fixed no 309 64
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2\[6\] -fixed no 75 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[12\] -fixed no 369 60
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[23\] -fixed no 81 22
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out_7\[6\] -fixed no 252 3
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[13\] -fixed no 98 28
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[14\] -fixed no 103 22
set_location UART_INTERFACE_0/FabUART_0/clear_t_3_iv_0_0_tz -fixed no 210 15
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[16\] -fixed no 365 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[3\] -fixed no 346 61
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[13\] -fixed no 261 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_state_15 -fixed no 311 60
set_location UART_INTERFACE_0/FabUART_0/state_ns_i_i_o4_0\[0\] -fixed no 201 15
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_bytecount\[12\] -fixed no 319 63
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNIPVKO\[0\] -fixed no 382 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[8\] -fixed no 358 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[8\] -fixed no 308 64
set_location UART_INTERFACE_0/FabUART_0/state\[0\] -fixed no 194 16
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[18\] -fixed no 280 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_sqmuxa_3 -fixed no 300 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_0\[11\] -fixed no 305 51
set_location UART_INTERFACE_0/FabUART_0/uart_data_out_t_RNO\[5\] -fixed no 190 21
set_location IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0\[11\] -fixed no 365 43
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[25\] -fixed no 269 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[17\] -fixed no 351 52
set_location Receiver_0/Downsampler_0/temp_data\[7\] -fixed no 110 25
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg_ldmx\[7\] -fixed no 376 57
set_location IGLOO2_Oversampling_0/CORERESETP_0/mss_reset_select_RNO -fixed no 362 48
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[15\] -fixed no 98 22
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2\[0\] -fixed no 106 31
set_location IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_enable_rcosc -fixed no 367 43
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_clock_int -fixed no 245 19
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNI9L3L\[0\] -fixed no 373 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1_0\[31\] -fixed no 271 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/bytecount\[1\] -fixed no 289 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata_RNI0NUA6\[6\] -fixed no 345 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_0_1\[4\] -fixed no 265 57
set_location UART_INTERFACE_0/FabUART_0/un21_i_a2_i_1 -fixed no 199 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0\[20\] -fixed no 283 48
set_location UART_INTERFACE_0/FabUART_0/state\[8\] -fixed no 193 22
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[21\] -fixed no 80 22
set_location Transmitter_0/FIFO_PRBS_0/data\[3\] -fixed no 260 4
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[4\] -fixed no 327 52
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[28\] -fixed no 52 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_2\[14\] -fixed no 286 60
set_location UART_INTERFACE_0/FabUART_0/un1_uart_data_out_t_0_sqmuxa_7_0_o2 -fixed no 201 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO\[4\] -fixed no 264 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[6\] -fixed no 252 58
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out_RNIJ52H\[1\] -fixed no 252 6
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns\[18\] -fixed no 102 27
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[5\] -fixed no 284 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[18\] -fixed no 281 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[31\] -fixed no 270 49
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/psel_RNO -fixed no 383 51
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[27\] -fixed no 91 28
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_0_i_a4_0_RNIAKB54\[7\] -fixed no 316 63
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR\[16\] -fixed no 312 45
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr\[3\] -fixed no 250 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[18\] -fixed no 279 49
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO\[15\] -fixed no 406 57
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.make_baud_cntr.baud_cntr8 -fixed no 245 18
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11\[29\] -fixed no 94 27
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_state_i_a2 -fixed no 288 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[17\] -fixed no 89 22
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr\[5\] -fixed no 252 19
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1\[8\] -fixed no 82 19
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[19\] -fixed no 329 49
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[10\] -fixed no 371 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[25\] -fixed no 339 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa_1 -fixed no 289 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HWRITE_0_sqmuxa_2 -fixed no 297 60
set_location Receiver_0/prbs7_10_0/un1_lock_count13_i_o2_0_6_1 -fixed no 114 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[19\] -fixed no 343 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[0\] -fixed no 249 52
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1\[1\] -fixed no 73 28
set_location Receiver_0/Downsampler_0/reg_check_12\[1\] -fixed no 75 18
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_byte\[3\] -fixed no 211 16
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[15\] -fixed no 62 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[15\] -fixed no 354 63
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_29 -fixed no 355 57
set_location UART_INTERFACE_0/COREUART_0/make_RX/samples\[1\] -fixed no 248 13
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[10\] -fixed no 107 28
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[4\] -fixed no 265 64
set_location Receiver_0/receive_buffer_top_0/receive_control_0/RX_VALIN_reg_d -fixed no 65 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[24\] -fixed no 353 61
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[0\] -fixed no 366 64
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[15\] -fixed no 360 46
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[15\] -fixed no 274 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_bytecount\[13\] -fixed no 323 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_1_sqmuxa_6 -fixed no 283 57
set_location IGLOO2_Oversampling_0/CORERESETP_0/un1_next_sdif0_core_reset_n_0_sqmuxa_i_a2 -fixed no 378 42
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_i_i_1\[5\] -fixed no 308 51
set_location UART_INTERFACE_0/COREUART_0/make_TX/tx -fixed no 215 22
set_location IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core_clk_base -fixed no 379 43
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_m0\[14\] -fixed no 88 21
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_a2_0_RNI3F3I\[0\] -fixed no 295 45
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_state128_0_I_80_i_0_x2 -fixed no 361 60
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[22\] -fixed no 80 16
set_location IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int_RNICDJF -fixed no 363 48
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNILRKO\[0\] -fixed no 385 63
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[6\] -fixed no 100 28
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/mux_sel_RNO\[1\] -fixed no 100 24
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un14_f0\[1\] -fixed no 317 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[11\] -fixed no 352 61
set_location Receiver_0/prbs7_10_0/LFSR\[7\] -fixed no 116 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[22\] -fixed no 349 58
set_location Receiver_0/prbs7_10_0/un1_reg_error13_0_a2_3 -fixed no 188 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[27\] -fixed no 350 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata_RNISIUA6\[4\] -fixed no 360 63
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState_RNO -fixed no 317 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[11\] -fixed no 247 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HWRITE51_2_0 -fixed no 295 60
set_location Transmitter_0/Replicator_0/X\[9\] -fixed no 262 7
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[5\] -fixed no 329 52
set_location UART_INTERFACE_0/FabUART_0/state_ns_a2_0_0_a2\[12\] -fixed no 202 15
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg\[1\] -fixed no 395 58
set_location UART_INTERFACE_0/FabUART_0/clear_t_3_iv_0_o4_0 -fixed no 211 15
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_bytecount\[0\] -fixed no 290 60
set_location UART_INTERFACE_0/FabUART_0/clear_t_3_iv_0_a3 -fixed no 209 15
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/make_xmit_clock.xmit_cntr_3_1.SUM\[3\] -fixed no 208 18
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_8 -fixed no 335 60
set_location Receiver_0/Downsampler_0/reg_data_out\[9\] -fixed no 114 22
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[9\] -fixed no 104 31
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg\[5\] -fixed no 393 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_RNIF4QB6\[7\] -fixed no 323 48
set_location UART_INTERFACE_0/COREUART_0/make_RX/receive_shift.rx_bit_cnt_4\[3\] -fixed no 231 12
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[7\] -fixed no 76 25
set_location Receiver_0/prbs7_10_0/lock_count_RNO\[1\] -fixed no 129 18
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[14\] -fixed no 287 46
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[24\] -fixed no 364 61
set_location UART_INTERFACE_0/FabUART_0/uart_data_out_t_RNO\[4\] -fixed no 187 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[4\] -fixed no 362 63
set_location IGLOO2_Oversampling_0/CORERESETP_0/sdif0_state_ns_1_0_.N_4_i -fixed no 373 42
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0\[23\] -fixed no 283 51
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/trans_detect_bit3 -fixed no 64 28
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[17\] -fixed no 94 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[16\] -fixed no 362 61
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[18\] -fixed no 282 49
set_location UART_INTERFACE_0/COREUART_0/make_RX/un1_rx_bit_cnt_1.CO1 -fixed no 233 12
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[3\] -fixed no 74 19
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns_1\[11\] -fixed no 79 21
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[1\] -fixed no 82 31
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[21\] -fixed no 357 46
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/paddr\[6\] -fixed no 364 52
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out_7_0\[6\] -fixed no 259 3
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2_RNI7TUQ\[0\] -fixed no 280 45
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[22\] -fixed no 262 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[6\] -fixed no 337 60
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNIMSKO\[0\] -fixed no 368 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[10\] -fixed no 104 28
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR\[30\] -fixed no 335 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[10\] -fixed no 283 64
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_16 -fixed no 351 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[19\] -fixed no 344 61
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[0\] -fixed no 95 28
set_location IGLOO2_Oversampling_0/CORERESETP_0/sdif0_state\[1\] -fixed no 373 43
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_state_34 -fixed no 303 57
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt\[3\] -fixed no 310 49
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel -fixed no 302 46
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[31\] -fixed no 352 63
set_location UART_INTERFACE_0/FabUART_0/uart_data_out_t\[3\] -fixed no 185 22
set_location UART_INTERFACE_0/COREUART_0/make_RX/receive_shift.rx_shift_11\[7\] -fixed no 214 12
set_location Transmitter_0/prbs7_10_0/W_0_x2\[9\] -fixed no 274 6
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO\[26\] -fixed no 380 48
set_location UART_INTERFACE_0/COREUART_0/make_TX/tx_byte\[1\] -fixed no 208 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[7\] -fixed no 362 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HWRITE51_2_0_4 -fixed no 318 63
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_o2 -fixed no 391 51
set_location UART_INTERFACE_0/COREUART_0/make_RX/receive_full_int_1_sqmuxa_i -fixed no 235 12
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_RNIM49O1 -fixed no 295 57
set_location UART_INTERFACE_0/FabUART_0/state\[1\] -fixed no 199 19
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/trans_detect_bit97 -fixed no 66 27
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/control_reg_1 -fixed no 390 49
set_location Receiver_0/Downsampler_0/temp_data\[5\] -fixed no 108 19
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNIJPKO\[0\] -fixed no 388 63
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_15 -fixed no 362 60
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2_RNI376N\[0\] -fixed no 320 45
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[23\] -fixed no 349 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[6\] -fixed no 246 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[12\] -fixed no 278 61
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1_13\[9\] -fixed no 81 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[11\] -fixed no 249 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[15\] -fixed no 272 64
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2\[3\] -fixed no 101 31
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[25\] -fixed no 376 49
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL\[16\] -fixed no 291 45
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[18\] -fixed no 63 22
set_location Receiver_0/Downsampler_0/temp_data\[2\] -fixed no 71 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[16\] -fixed no 257 52
set_location Receiver_0/prbs7_10_0/LFSR\[5\] -fixed no 119 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[9\] -fixed no 326 61
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_sel.tx_2_7_i_m2_bm -fixed no 209 24
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un32_d_HADDR_axb_0 -fixed no 240 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HSIZE9_RNIE8F23_4 -fixed no 327 66
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO\[13\] -fixed no 262 60
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns\[11\] -fixed no 81 24
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_a2_0\[0\] -fixed no 298 45
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_iv -fixed no 289 57
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.make_baud_cntr.baud_cntr8_8 -fixed no 261 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata_RNIUKUA6\[5\] -fixed no 338 66
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD3\[7\] -fixed no 83 22
set_location Receiver_0/prbs7_10_0/reg_error\[5\] -fixed no 186 19
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO\[23\] -fixed no 404 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[18\] -fixed no 341 63
set_location Receiver_0/Downsampler_0/temp_val -fixed no 111 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HSIZE9_RNIE8F23_0 -fixed no 324 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[12\] -fixed no 312 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_0\[1\] -fixed no 298 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[29\] -fixed no 273 49
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11\[8\] -fixed no 72 24
set_location IGLOO2_Oversampling_0/ConfigMaster_0/busy_RNIR9SE -fixed no 294 42
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR\[23\] -fixed no 324 48
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNI7J3L\[0\] -fixed no 375 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[30\] -fixed no 266 49
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out_7\[8\] -fixed no 256 3
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[29\] -fixed no 303 46
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_bit_cnt\[0\] -fixed no 237 13
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg_ldmx\[5\] -fixed no 393 57
set_location UART_INTERFACE_0/COREUART_0/make_RX/receive_shift.rx_shift_11\[1\] -fixed no 209 12
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[7\] -fixed no 280 64
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_byte_1_sqmuxa -fixed no 228 12
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_m0\[15\] -fixed no 94 21
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/un9_count_hot_6 -fixed no 99 30
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[18\] -fixed no 82 25
set_location Receiver_0/Downsampler_0/temp_data\[1\] -fixed no 109 19
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg_ldmx\[3\] -fixed no 394 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D0\[6\] -fixed no 64 31
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[8\] -fixed no 107 31
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[20\] -fixed no 370 64
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD3_RNO\[8\] -fixed no 65 18
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/trans_detect_bit6_0_sqmuxa -fixed no 60 24
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD3\[3\] -fixed no 103 31
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/trans_detect_bit3_0_sqmuxa -fixed no 64 27
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_22 -fixed no 349 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[31\] -fixed no 339 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_d_count_0_sqmuxa_1 -fixed no 321 51
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out\[6\] -fixed no 252 4
set_location UART_INTERFACE_0/COREUART_0/make_RX/receive_shift.rx_shift_11\[4\] -fixed no 206 12
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/prdata_0_iv_0\[13\] -fixed no 374 57
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL\[12\] -fixed no 307 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_d_count_0_sqmuxa_1_1 -fixed no 316 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[29\] -fixed no 264 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[20\] -fixed no 337 58
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1_RNO\[0\] -fixed no 90 27
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1_RNO\[1\] -fixed no 73 27
set_location Transmitter_0/Replicator_0/X\[27\] -fixed no 273 4
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_bytecount_2_sqmuxa_0 -fixed no 321 57
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[26\] -fixed no 365 52
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/make_xmit_clock.xmit_cntr_3_1.CO0 -fixed no 210 18
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS -fixed no 333 60
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[14\] -fixed no 363 52
set_location IGLOO2_Oversampling_0/CORERESETP_0/sdif0_state\[0\] -fixed no 375 43
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[9\] -fixed no 271 61
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[15\] -fixed no 364 58
set_location Receiver_0/receive_buffer_top_0/receive_control_0/clear_errcnt_reg -fixed no 180 19
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_shift\[4\] -fixed no 206 13
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[9\] -fixed no 281 64
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/cntr_2bit_en -fixed no 103 25
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[14\] -fixed no 94 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/envm_soft_reset\[1\] -fixed no 292 43
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns_1\[22\] -fixed no 97 27
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[24\] -fixed no 326 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[29\] -fixed no 270 52
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[18\] -fixed no 102 28
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[13\] -fixed no 357 66
set_location Transmitter_0/prbs7_10_0/W_0_x2\[8\] -fixed no 272 6
set_location Receiver_0/receive_buffer_top_0/receive_control_0/RC_FSM_state\[0\] -fixed no 68 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_1_sqmuxa_7 -fixed no 299 51
set_location Receiver_0/receive_buffer_top_0/receive_control_0/start_lock_reg_RNO -fixed no 69 24
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[31\] -fixed no 346 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_2\[11\] -fixed no 248 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[1\] -fixed no 257 57
set_location UART_INTERFACE_0/FabUART_0/state\[3\] -fixed no 198 22
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNIDP3L\[0\] -fixed no 380 60
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/prdata_0_iv_0\[4\] -fixed no 372 57
set_location Receiver_0/Downsampler_0/reg_data_out\[6\] -fixed no 113 25
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_RNO\[1\] -fixed no 299 45
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/paddr\[2\] -fixed no 371 46
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL\[7\] -fixed no 301 48
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg\[3\] -fixed no 394 58
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg\[2\] -fixed no 381 58
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[13\] -fixed no 374 58
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[13\] -fixed no 104 22
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/enable_lock -fixed no 64 25
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[26\] -fixed no 63 19
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr\[9\] -fixed no 256 19
set_location Receiver_0/receive_buffer_top_0/receive_control_0/RC_FSM_state_ns_0_a2\[1\] -fixed no 67 24
set_location Receiver_0/AND3_0_RNI7UKC/U0_RGB1 -fixed no 218 30
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[3\] -fixed no 397 58
set_location IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int -fixed no 361 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[19\] -fixed no 278 49
set_location Transmitter_0/FIFO_PRBS_0/data\[15\] -fixed no 261 4
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[29\] -fixed no 379 49
set_location UART_INTERFACE_0/FabUART_0/uart_data_out_t_22_i_a2_0\[3\] -fixed no 180 21
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[1\] -fixed no 368 52
set_location Transmitter_0/FIFO_PRBS_0/i_RNO\[1\] -fixed no 267 3
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_state_32_4 -fixed no 307 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_sqmuxa_2 -fixed no 300 60
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD3_RNO\[7\] -fixed no 83 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_state_29 -fixed no 302 57
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/xmit_cntr\[0\] -fixed no 211 19
set_location Transmitter_0/prbs7_10_0/LFSR\[10\] -fixed no 274 7
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[12\] -fixed no 369 61
set_location Transmitter_0/prbs7_10_0/W_0_x2\[6\] -fixed no 268 6
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/DA_FSM_STATE_ns_1_0_.m9_0_0 -fixed no 106 24
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns_1\[18\] -fixed no 102 30
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_state\[2\] -fixed no 214 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[7\] -fixed no 307 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[14\] -fixed no 334 52
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[9\] -fixed no 388 58
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1_0_sqmuxa_i_o3 -fixed no 70 24
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[23\] -fixed no 57 22
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO\[31\] -fixed no 377 48
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR\[28\] -fixed no 297 48
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[2\] -fixed no 287 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[21\] -fixed no 272 49
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/paddr\[3\] -fixed no 368 46
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/enable_lock_dly -fixed no 105 25
set_location Receiver_0/Downsampler_0/temp_data_12\[2\] -fixed no 71 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[28\] -fixed no 259 57
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR\[31\] -fixed no 309 45
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_sel.tx_4_iv_i -fixed no 209 21
set_location Receiver_0/Downsampler_0/reg_check\[1\] -fixed no 75 19
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_RNO_0\[1\] -fixed no 296 45
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata_RNI54N23\[2\] -fixed no 336 63
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[18\] -fixed no 349 46
set_location UART_INTERFACE_0/FabUART_0/state_ns_i_i_o4_1\[0\] -fixed no 203 15
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[3\] -fixed no 91 31
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_state128_0_I_44_i_0_x2 -fixed no 336 51
set_location Transmitter_0/AND2_0_RNIEO99/U0_RGB1 -fixed no 219 15
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns\[1\] -fixed no 77 18
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/mux_sel_RNO\[0\] -fixed no 98 24
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out_7\[0\] -fixed no 260 6
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_6 -fixed no 362 57
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_shift\[3\] -fixed no 208 13
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[13\] -fixed no 313 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[2\] -fixed no 268 64
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2\[8\] -fixed no 68 19
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL\[10\] -fixed no 300 48
set_location Transmitter_0/FIFO_PRBS_0/data\[21\] -fixed no 258 4
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNIBM2L\[0\] -fixed no 347 66
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_state128_0_I_50_i_0_x2 -fixed no 348 57
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/prdata_0_iv_0_a2_1\[1\] -fixed no 388 48
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[21\] -fixed no 372 49
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[27\] -fixed no 81 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[4\] -fixed no 266 64
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNI5H3L\[0\] -fixed no 371 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[21\] -fixed no 85 19
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/un9_count_hot -fixed no 87 24
set_location Transmitter_0/prbs7_10_0/W_0_x2\[0\] -fixed no 269 6
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD3\[5\] -fixed no 86 22
set_location Transmitter_0/FIFO_PRBS_0/Error_Inject_i_delay2 -fixed no 201 16
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_30 -fixed no 346 51
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[20\] -fixed no 66 22
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_1\[10\] -fixed no 302 45
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg\[11\] -fixed no 386 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_1_sqmuxa_3 -fixed no 298 60
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/un17_count_hot -fixed no 86 24
set_location UART_INTERFACE_0/COREUART_0/tx_hold_reg\[2\] -fixed no 208 22
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[31\] -fixed no 362 46
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_26 -fixed no 344 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[24\] -fixed no 364 60
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[3\] -fixed no 351 46
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR_RNO\[16\] -fixed no 250 51
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[15\] -fixed no 282 46
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[5\] -fixed no 329 58
set_location UART_INTERFACE_0/FabUART_0/un1_uart_data_out_t_0_sqmuxa_9_i_a2_0_RNIDORG1 -fixed no 195 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR_fast\[0\] -fixed no 242 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state\[19\] -fixed no 288 46
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr\[0\] -fixed no 247 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[16\] -fixed no 360 61
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[9\] -fixed no 96 28
set_location Receiver_0/Downsampler_0/temp_data\[4\] -fixed no 109 22
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD3\[2\] -fixed no 85 31
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[25\] -fixed no 282 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[18\] -fixed no 281 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[6\] -fixed no 251 58
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[22\] -fixed no 59 22
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_25 -fixed no 359 57
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[13\] -fixed no 276 46
set_location UART_INTERFACE_0/COREUART_0/make_TX/txrdy_int_0_sqmuxa_i_o3_i_a2 -fixed no 208 21
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2_RNIF5VQ\[0\] -fixed no 316 45
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[25\] -fixed no 281 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[11\] -fixed no 273 61
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2_13\[6\] -fixed no 75 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_state_19_0 -fixed no 322 51
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/prdata_0_iv_0\[14\] -fixed no 378 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[16\] -fixed no 56 22
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[19\] -fixed no 105 28
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1_RNI132A2\[20\] -fixed no 323 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[28\] -fixed no 261 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[22\] -fixed no 348 58
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ss0 -fixed no 99 24
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[2\] -fixed no 325 58
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B -fixed no 221 54
set_location UART_INTERFACE_0/COREUART_0/make_RX/receive_shift.rx_bit_cnt_4\[2\] -fixed no 230 12
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[4\] -fixed no 264 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[10\] -fixed no 328 61
set_location UART_INTERFACE_0/COREUART_0/make_RX/stop_strobe -fixed no 242 13
set_location Receiver_0/prbs7_10_0/un1_lock_count13_i_o2 -fixed no 124 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[9\] -fixed no 335 61
set_location IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc -fixed no 370 43
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[4\] -fixed no 369 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[30\] -fixed no 356 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[25\] -fixed no 350 52
set_location Transmitter_0/FIFO_PRBS_0/i\[1\] -fixed no 266 4
set_location IGLOO2_Oversampling_0/CORERESETP_0/sdif0_areset_n_q1 -fixed no 373 46
set_location IGLOO2_Oversampling_0/ConfigMaster_0/count_RNO\[0\] -fixed no 320 51
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO\[29\] -fixed no 379 48
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR\[15\] -fixed no 282 45
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[1\] -fixed no 77 19
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[13\] -fixed no 93 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[22\] -fixed no 318 58
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2_9 -fixed no 312 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[26\] -fixed no 287 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[15\] -fixed no 273 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[27\] -fixed no 284 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[8\] -fixed no 279 61
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[5\] -fixed no 277 64
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/mux_sel\[2\] -fixed no 97 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[22\] -fixed no 263 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[23\] -fixed no 338 58
set_location Receiver_0/Downsampler_0/reg_check_12\[0\] -fixed no 79 18
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNIAM3L\[0\] -fixed no 377 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[31\] -fixed no 351 63
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR\[30\] -fixed no 301 45
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[8\] -fixed no 365 46
set_location IGLOO2_Oversampling_0/CORERESETP_0/sdif0_spll_lock_q1 -fixed no 376 43
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO\[28\] -fixed no 375 48
set_location Receiver_0/prbs7_10_0/LFSR\[3\] -fixed no 118 19
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[16\] -fixed no 102 22
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[19\] -fixed no 69 22
set_location UART_INTERFACE_0/FabUART_0/state\[13\] -fixed no 203 22
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[28\] -fixed no 62 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/count\[0\] -fixed no 320 52
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_state_ns_a3_2_1\[0\] -fixed no 211 21
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1\[5\] -fixed no 89 19
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr\[4\] -fixed no 251 19
set_location IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0\[10\] -fixed no 364 43
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[30\] -fixed no 348 61
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[15\] -fixed no 274 63
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[15\] -fixed no 406 58
set_location IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0\[7\] -fixed no 361 43
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState -fixed no 318 49
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out_RNIN92H\[5\] -fixed no 255 6
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[16\] -fixed no 312 46
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[11\] -fixed no 318 46
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[1\] -fixed no 400 58
set_location Receiver_0/Downsampler_0/reg_data_out\[0\] -fixed no 118 22
set_location UART_INTERFACE_0/COREUART_0/tx_hold_reg\[3\] -fixed no 205 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[7\] -fixed no 269 61
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2_0_sqmuxa -fixed no 64 24
set_location UART_INTERFACE_0/COREUART_0/make_RX/receive_shift.rx_shift_11\[0\] -fixed no 212 12
set_location IGLOO2_Oversampling_0/ConfigMaster_0/count_RNO_0\[1\] -fixed no 317 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1_RNIBCPT\[22\] -fixed no 320 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0\[18\] -fixed no 279 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_haddr_write11_1 -fixed no 292 60
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[11\] -fixed no 83 31
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR\[24\] -fixed no 326 48
set_location IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core4_8 -fixed no 352 42
set_location UART_INTERFACE_0/FabUART_0/state_RNO\[9\] -fixed no 193 18
set_location UART_INTERFACE_0/FabUART_0/state\[7\] -fixed no 192 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HTRANS_0_sqmuxa_4 -fixed no 309 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2\[5\] -fixed no 85 22
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_m0\[29\] -fixed no 95 27
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11\[5\] -fixed no 72 18
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[13\] -fixed no 96 22
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1\[3\] -fixed no 101 28
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_state\[5\] -fixed no 212 25
set_location Transmitter_0/prbs7_10_0/tx_count_ns_0_a2\[0\] -fixed no 271 9
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt\[14\] -fixed no 302 49
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/control_reg_2_1_sqmuxa_i_0 -fixed no 386 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[12\] -fixed no 278 58
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_bit_cnt_1_sqmuxa_0_a3 -fixed no 243 12
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[22\] -fixed no 53 22
set_location Receiver_0/prbs7_10_0/reg_lock_again -fixed no 70 25
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/un1_trans_detect_bit66 -fixed no 62 27
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[22\] -fixed no 353 46
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt\[10\] -fixed no 300 49
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns_1\[6\] -fixed no 82 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/bytecount\[5\] -fixed no 305 61
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/make_xmit_clock.xmit_clock5 -fixed no 209 18
set_location SERDES_IF_0/EPCS_1_TX_CLK_inferred_clock_RNI9VS5 -fixed no 219 54
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[1\] -fixed no 255 58
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2\[0\] -fixed no 286 45
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[17\] -fixed no 245 51
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg_ldmx\[10\] -fixed no 382 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD3_0_sqmuxa_i_o3 -fixed no 69 27
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/control_reg_29_0_a2 -fixed no 392 48
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHSIZE\[0\] -fixed no 333 49
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/xmit_clock -fixed no 209 19
set_location IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_clk_base -fixed no 372 46
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr\[12\] -fixed no 259 19
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[32\] -fixed no 52 19
set_location Receiver_0/prbs7_10_0/un1_data_in_2_0 -fixed no 112 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state\[12\] -fixed no 310 52
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[12\] -fixed no 83 16
set_location IGLOO2_Oversampling_0/ConfigMaster_0/bytecount\[9\] -fixed no 299 64
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[7\] -fixed no 313 46
set_location Receiver_0/Downsampler_0/temp_data_12\[3\] -fixed no 111 24
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/state_ns_0_0\[1\] -fixed no 384 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state\[14\] -fixed no 289 46
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_2\[4\] -fixed no 267 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[8\] -fixed no 370 60
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_bit_sel\[1\] -fixed no 205 25
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[25\] -fixed no 328 49
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_state_ns_i_a3_0\[1\] -fixed no 242 12
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_state\[0\] -fixed no 212 22
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns_1\[24\] -fixed no 78 27
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i -fixed no 316 48
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[11\] -fixed no 94 31
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[19\] -fixed no 344 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HSIZE_1_sqmuxa_1 -fixed no 304 60
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[1\] -fixed no 315 46
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_m0\[12\] -fixed no 89 21
set_location Receiver_0/Downsampler_0/temp_data\[6\] -fixed no 109 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_state_32_6 -fixed no 293 45
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns\[26\] -fixed no 77 27
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt\[7\] -fixed no 301 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_bytecount4_1_0 -fixed no 269 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[14\] -fixed no 330 61
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[23\] -fixed no 324 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0\[15\] -fixed no 272 63
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNICN2L\[0\] -fixed no 389 63
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[3\] -fixed no 80 28
set_location IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_enable_q1 -fixed no 368 43
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[27\] -fixed no 332 52
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[11\] -fixed no 81 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[13\] -fixed no 357 67
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD3\[6\] -fixed no 79 22
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/SDIF0_PENABLE_2_0_a2 -fixed no 381 51
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[17\] -fixed no 278 46
set_location Receiver_0/prbs7_10_0/LFSR\[4\] -fixed no 117 22
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[2\] -fixed no 78 19
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/rx_data_debug\[5\] -fixed no 51 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[17\] -fixed no 344 67
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[29\] -fixed no 275 48
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_18 -fixed no 343 51
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[0\] -fixed no 382 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[9\] -fixed no 327 61
set_location UART_INTERFACE_0/FabUART_0/un1_uart_data_out_t_0_sqmuxa_9_i_a2_0 -fixed no 196 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_busy_3 -fixed no 290 42
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[12\] -fixed no 58 25
set_location IGLOO2_Oversampling_0/CORERESETP_0/sdif0_areset_n_rcosc_q1 -fixed no 369 43
set_location Receiver_0/Downsampler_0/temp_data_12\[5\] -fixed no 108 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[26\] -fixed no 287 51
set_location UART_INTERFACE_0/COREUART_0/tx_hold_reg\[5\] -fixed no 206 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state\[18\] -fixed no 293 46
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_0_a3_0\[2\] -fixed no 291 57
set_location IGLOO2_Oversampling_0/CORERESETP_0/init_done_clk_base -fixed no 374 43
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[23\] -fixed no 313 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HSIZE9_RNIE8F23_1 -fixed no 328 66
set_location Transmitter_0/FIFO_PRBS_0/Error_Inject_i_delay1 -fixed no 195 16
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1\[6\] -fixed no 84 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[18\] -fixed no 280 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[1\] -fixed no 341 66
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/prdata_0_iv_0\[11\] -fixed no 387 57
set_location Receiver_0/Downsampler_0/reg_data_out\[8\] -fixed no 114 19
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[19\] -fixed no 77 16
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[19\] -fixed no 403 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0\[17\] -fixed no 248 51
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_3 -fixed no 347 51
set_location Transmitter_0/Replicator_0/X\[15\] -fixed no 263 7
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D0\[10\] -fixed no 66 28
set_location IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0\[5\] -fixed no 359 43
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[12\] -fixed no 366 61
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR\[19\] -fixed no 329 48
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_a3_0_a2 -fixed no 389 51
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2_RNI5RUQ\[0\] -fixed no 279 45
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_RNO\[0\] -fixed no 294 45
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2_RNI596N\[0\] -fixed no 276 45
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/prdata_0_iv_0\[8\] -fixed no 384 57
set_location Receiver_0/Downsampler_0/reg_check_12\[2\] -fixed no 75 24
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_sel.tx_2_7_i_m2_am_1_1 -fixed no 207 24
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNI9K2L\[0\] -fixed no 357 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[5\] -fixed no 338 52
set_location UART_INTERFACE_0/FabUART_0/un1_state_4_i_o4_0 -fixed no 196 21
set_location Transmitter_0/FIFO_PRBS_0/data\[18\] -fixed no 258 7
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[10\] -fixed no 338 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/count_RNIHIHO2\[0\] -fixed no 329 63
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[26\] -fixed no 332 49
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_bit_sel_RNO\[3\] -fixed no 215 24
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[30\] -fixed no 261 49
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns\[9\] -fixed no 74 24
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[21\] -fixed no 334 49
set_location IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1 -fixed no 218 102
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_bit_cnt\[3\] -fixed no 231 13
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/paddr\[9\] -fixed no 355 46
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1_13\[7\] -fixed no 73 24
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[19\] -fixed no 276 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[18\] -fixed no 341 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state\[7\] -fixed no 314 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[13\] -fixed no 326 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[19\] -fixed no 278 48
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg_ldmx\[1\] -fixed no 395 57
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO\[20\] -fixed no 383 48
set_location Transmitter_0/Replicator_0/X\[12\] -fixed no 272 4
set_location UART_INTERFACE_0/COREUART_0/make_TX/txrdy_int_1_sqmuxa_i -fixed no 210 21
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL\[14\] -fixed no 302 48
set_location Receiver_0/Downsampler_0/reg_check_12\[3\] -fixed no 80 24
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[5\] -fixed no 396 58
set_location UART_INTERFACE_0/FabUART_0/uart_wen_t -fixed no 203 19
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[28\] -fixed no 75 16
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[0\] -fixed no 366 63
set_location IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core_q1 -fixed no 378 43
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[13\] -fixed no 260 61
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2_13\[9\] -fixed no 70 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/bytecount\[4\] -fixed no 293 64
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/prdata_0_iv_0\[12\] -fixed no 398 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[16\] -fixed no 246 51
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2_RNIV26N\[0\] -fixed no 283 45
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[3\] -fixed no 245 58
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR\[21\] -fixed no 334 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_RNO\[12\] -fixed no 310 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWRITE -fixed no 320 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[31\] -fixed no 262 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state\[3\] -fixed no 276 58
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[11\] -fixed no 387 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[29\] -fixed no 355 66
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[12\] -fixed no 365 61
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[21\] -fixed no 57 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0\[1\] -fixed no 255 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[0\] -fixed no 243 51
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt\[16\] -fixed no 319 46
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/prdata_0_iv_0\[5\] -fixed no 396 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[0\] -fixed no 80 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[24\] -fixed no 265 52
set_location UART_INTERFACE_0/FabUART_0/state\[14\] -fixed no 205 19
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[38\] -fixed no 53 19
set_location IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0\[1\] -fixed no 355 43
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR\[27\] -fixed no 325 48
set_location UART_INTERFACE_0/COREUART_0/make_RX/receive_count\[3\] -fixed no 244 13
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0\[28\] -fixed no 260 57
set_location Receiver_0/receive_buffer_top_0/receive_control_0/RC_FSM_state5 -fixed no 66 24
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO\[22\] -fixed no 407 57
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[0\] -fixed no 285 46
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNI8K3L\[0\] -fixed no 390 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR_RNO_0\[30\] -fixed no 266 48
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt\[11\] -fixed no 309 49
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNI6H2L\[0\] -fixed no 369 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/rx_data_debug\[1\] -fixed no 50 25
set_location UART_INTERFACE_0/COREUART_0/tx_hold_reg\[0\] -fixed no 207 22
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[31\] -fixed no 51 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[25\] -fixed no 281 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HWDATA_0_sqmuxa_i_1 -fixed no 314 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_state128_0_I_98_i_0_x2 -fixed no 354 60
set_location UART_INTERFACE_0/FabUART_0/start_t -fixed no 199 16
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2\[9\] -fixed no 71 19
set_location Receiver_0/Downsampler_0/reg_error5_5 -fixed no 106 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR_RNO\[17\] -fixed no 247 51
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[1\] -fixed no 98 31
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata_RNIETEG6\[14\] -fixed no 348 60
set_location UART_INTERFACE_0/FabUART_0/un1_state_4_i_0 -fixed no 202 18
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNIR1LO\[0\] -fixed no 385 60
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns\[24\] -fixed no 74 27
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/trans_detect_bit6_2_sqmuxa_i -fixed no 61 24
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[7\] -fixed no 342 63
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[26\] -fixed no 76 19
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[27\] -fixed no 325 49
set_location UART_INTERFACE_0/FabUART_0/state\[9\] -fixed no 193 19
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[8\] -fixed no 80 31
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL\[9\] -fixed no 305 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[28\] -fixed no 351 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[0\] -fixed no 363 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_2\[3\] -fixed no 242 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR9_1 -fixed no 302 42
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr\[7\] -fixed no 254 19
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.make_baud_cntr.baud_cntr8_1 -fixed no 244 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/count_RNIHIHO2_2\[0\] -fixed no 330 63
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11\[7\] -fixed no 76 24
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch_RNO\[2\] -fixed no 263 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0\[19\] -fixed no 276 48
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/un2_count_hot_5 -fixed no 84 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR_RNO_1\[30\] -fixed no 267 48
set_location Transmitter_0/Replicator_0/reg_tx_val_out -fixed no 265 4
set_location IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0\[0\] -fixed no 354 43
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[3\] -fixed no 284 46
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[13\] -fixed no 334 61
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[22\] -fixed no 256 57
set_location UART_INTERFACE_0/COREUART_0/make_RX/receive_shift.rx_shift_11\[5\] -fixed no 207 12
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[17\] -fixed no 390 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_2_sqmuxa_1_2 -fixed no 315 57
set_location UART_INTERFACE_0/FabUART_0/state\[11\] -fixed no 189 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_RNO\[9\] -fixed no 274 57
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr\[8\] -fixed no 255 19
set_location UART_INTERFACE_0/COREUART_0/make_RX/rcv_cnt.receive_count_3\[1\] -fixed no 249 12
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[0\] -fixed no 325 61
set_location Receiver_0/prbs7_10_0/un1_lock_count13_i_o2_0 -fixed no 117 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_sqmuxa_4_RNO -fixed no 319 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[1\] -fixed no 257 58
set_location Receiver_0/prbs7_10_0/LFSR_RNO\[5\] -fixed no 119 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0\[16\] -fixed no 251 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HTRANS_1\[1\] -fixed no 302 58
set_location IGLOO2_Oversampling_0/CORERESETP_0/sdif0_state_ns_1_0_.N_5_mux_i -fixed no 376 42
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_state128_0_I_86_i_0_x2 -fixed no 328 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[5\] -fixed no 277 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0\[25\] -fixed no 280 51
set_location FCCC_0/GL0_INST/U0_RGB1 -fixed no 219 24
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[23\] -fixed no 73 22
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg\[13\] -fixed no 375 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[17\] -fixed no 335 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HTRANS_0_sqmuxa_3 -fixed no 311 57
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out\[4\] -fixed no 254 4
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[0\] -fixed no 243 52
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[6\] -fixed no 86 28
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR\[22\] -fixed no 327 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/pause_count\[4\] -fixed no 295 43
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[22\] -fixed no 262 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns_1\[20\] -fixed no 104 30
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[9\] -fixed no 352 66
set_location Receiver_0/prbs7_10_0/reg_error\[1\] -fixed no 182 19
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_m0\[3\] -fixed no 63 18
set_location UART_INTERFACE_0/FabUART_0/state_RNO\[14\] -fixed no 205 18
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_VALOUT_reg_1_sqmuxa_i -fixed no 105 27
set_location Receiver_0/Downsampler_0/temp_data_12\[0\] -fixed no 108 21
set_location UART_INTERFACE_0/FabUART_0/state_ns_i_i\[0\] -fixed no 194 15
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNI7TTB1\[0\] -fixed no 315 48
set_location UART_INTERFACE_0/COREUART_0/genblk1.RXRDY -fixed no 233 13
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns_1\[26\] -fixed no 81 27
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_0 -fixed no 337 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[0\] -fixed no 244 52
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_state_ns_a3_0_a2\[1\] -fixed no 213 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state\[6\] -fixed no 322 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[7\] -fixed no 371 64
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[19\] -fixed no 362 52
set_location Transmitter_0/Replicator_0/X\[24\] -fixed no 271 4
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_state_ns_a3_2\[0\] -fixed no 212 21
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/rx_data_debug\[8\] -fixed no 50 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR_RNO\[6\] -fixed no 241 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[9\] -fixed no 282 64
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[7\] -fixed no 97 28
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[20\] -fixed no 261 52
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[12\] -fixed no 100 22
set_location Receiver_0/Downsampler_0/reg_data_out\[5\] -fixed no 112 19
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[5\] -fixed no 78 28
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[10\] -fixed no 310 64
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[20\] -fixed no 383 49
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg_ldmx\[2\] -fixed no 381 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1_RNO\[3\] -fixed no 101 27
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[21\] -fixed no 64 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[24\] -fixed no 363 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[3\] -fixed no 265 61
set_location IGLOO2_Oversampling_0/ConfigMaster_0/bytecount\[15\] -fixed no 321 64
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[25\] -fixed no 60 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0\[27\] -fixed no 274 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata_RNI6TUA6\[9\] -fixed no 350 66
set_location Transmitter_0/Replicator_0/X\[6\] -fixed no 268 4
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[27\] -fixed no 284 58
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_shift\[2\] -fixed no 211 13
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[30\] -fixed no 355 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[12\] -fixed no 278 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/rx_data_debug\[2\] -fixed no 49 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[6\] -fixed no 341 61
set_location UART_INTERFACE_0/FabUART_0/state_RNO\[11\] -fixed no 189 21
set_location Transmitter_0/Replicator_0/X\[18\] -fixed no 259 7
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[19\] -fixed no 342 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_bytecount\[5\] -fixed no 305 60
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/paddr\[15\] -fixed no 392 52
set_location UART_INTERFACE_0/COREUART_0/make_RX/receive_shift.rx_shift_11\[3\] -fixed no 208 12
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR_RNO\[15\] -fixed no 273 63
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_shift\[0\] -fixed no 212 13
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1_13\[8\] -fixed no 76 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_tr34 -fixed no 289 45
set_location Receiver_0/Downsampler_0/reg_check\[0\] -fixed no 79 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[6\] -fixed no 330 58
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg_ldmx\[8\] -fixed no 385 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns_1\[25\] -fixed no 79 27
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_d_HADDR_2_sqmuxa_tz -fixed no 312 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata_RNIFTDG6\[10\] -fixed no 335 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[1\] -fixed no 327 58
set_location IGLOO2_Oversampling_0/CORERESETP_0/POWER_ON_RESET_N_q1 -fixed no 358 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/bytecount\[0\] -fixed no 288 61
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[27\] -fixed no 268 52
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/rx_data_debug\[7\] -fixed no 48 25
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_28 -fixed no 348 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_bytecount_3_sqmuxa -fixed no 313 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[8\] -fixed no 324 58
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[22\] -fixed no 73 25
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[20\] -fixed no 360 52
set_location SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1 -fixed no 225 54
set_location Receiver_0/prbs7_10_0/reg_lock -fixed no 127 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[23\] -fixed no 279 52
set_location Transmitter_0/prbs7_10_0/W_0_x2\[2\] -fixed no 271 6
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/DA_FSM_STATE_ns_1_0_.m5_i_a3_1_1 -fixed no 102 24
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/prdata_0_iv_0\[7\] -fixed no 377 57
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[30\] -fixed no 301 46
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNI6J4L\[0\] -fixed no 389 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[7\] -fixed no 361 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[2\] -fixed no 340 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[28\] -fixed no 352 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[31\] -fixed no 270 48
set_location Transmitter_0/FIFO_PRBS_0/data\[0\] -fixed no 255 7
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[25\] -fixed no 366 46
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[0\] -fixed no 100 31
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns_1\[27\] -fixed no 96 30
set_location UART_INTERFACE_0/COREUART_0/make_RX/rcv_sm.rx_state19_NE -fixed no 232 12
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO\[27\] -fixed no 381 48
set_location Receiver_0/Downsampler_0/reg_check_12\[6\] -fixed no 106 27
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_haddr_fetch_1_sqmuxa -fixed no 266 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_i_o3_0_2_i_a2_RNIDU0B2\[5\] -fixed no 318 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_state_32_12 -fixed no 290 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[26\] -fixed no 77 28
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD3_13\[3\] -fixed no 103 30
set_location Transmitter_0/prbs7_10_0/LFSR\[9\] -fixed no 272 7
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[20\] -fixed no 103 28
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata_RNI3PTA6\[3\] -fixed no 347 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_0\[4\] -fixed no 275 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[6\] -fixed no 306 64
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_byte\[4\] -fixed no 205 16
set_location Receiver_0/prbs7_10_0/un1_tx_count17_1_0_0 -fixed no 120 18
set_location Receiver_0/prbs7_10_0/reg_error\[0\] -fixed no 181 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[29\] -fixed no 274 48
set_location Transmitter_0/prbs7_10_0/LFSR\[2\] -fixed no 267 7
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[9\] -fixed no 287 64
set_location UART_INTERFACE_0/FabUART_0/un1_state_4_i_0_1 -fixed no 198 18
set_location Receiver_0/prbs7_10_0/un1_data_in_3 -fixed no 116 21
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/trans_detect_bit9_2_sqmuxa_i -fixed no 68 27
set_location UART_INTERFACE_0/FabUART_0/state_RNO\[5\] -fixed no 183 21
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_m0\[4\] -fixed no 66 18
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[5\] -fixed no 280 46
set_location Receiver_0/Downsampler_0/reg_error5_6 -fixed no 79 24
set_location UART_INTERFACE_0/COREUART_0/tx_hold_reg\[1\] -fixed no 204 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[2\] -fixed no 263 61
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[30\] -fixed no 354 58
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[26\] -fixed no 55 22
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[8\] -fixed no 87 31
set_location Transmitter_0/prbs7_10_0/W_0_x2\[4\] -fixed no 266 6
set_location IGLOO2_Oversampling_0/CORERESETP_0/ddr_ready_clk_base -fixed no 380 43
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_shift\[7\] -fixed no 214 13
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0\[2\] -fixed no 268 63
set_location Receiver_0/receive_buffer_top_0/receive_control_0/RC_FSM_state11 -fixed no 65 24
set_location UART_INTERFACE_0/FabUART_0/state_RNO\[13\] -fixed no 203 21
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_11 -fixed no 367 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[27\] -fixed no 351 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0\[12\] -fixed no 277 60
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/DA_FSM_STATE_ns_1_0_.N_427_i -fixed no 103 24
set_location Receiver_0/prbs7_10_0/LFSR\[2\] -fixed no 115 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[1\] -fixed no 254 57
set_location UART_INTERFACE_0/FabUART_0/uart_data_out_t\[5\] -fixed no 190 22
set_location Receiver_0/prbs7_10_0/reg_error_out -fixed no 187 19
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/mux_sel\[1\] -fixed no 99 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[23\] -fixed no 264 52
set_location Transmitter_0/FIFO_PRBS_0/un1_data_1_sqmuxa_0 -fixed no 265 3
set_location IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0\[12\] -fixed no 366 43
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[4\] -fixed no 372 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_i_i\[3\] -fixed no 276 57
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out_7_0\[3\] -fixed no 262 3
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_state128_0_I_62_i_0_x2 -fixed no 366 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[20\] -fixed no 284 49
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/rx_data_debug\[0\] -fixed no 78 16
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out_7\[4\] -fixed no 254 3
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[7\] -fixed no 278 64
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[36\] -fixed no 50 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[7\] -fixed no 360 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[3\] -fixed no 366 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/count\[1\] -fixed no 319 52
set_location Receiver_0/Downsampler_0/temp_data_12\[7\] -fixed no 110 24
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state\[2\] -fixed no 286 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_i_a3_0\[20\] -fixed no 289 42
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[17\] -fixed no 344 66
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[0\] -fixed no 369 46
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_13 -fixed no 334 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_bytecount\[4\] -fixed no 293 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0\[29\] -fixed no 273 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata_RNI4RUA6\[8\] -fixed no 368 63
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr\[11\] -fixed no 258 19
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out_7_0\[9\] -fixed no 258 6
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/lock_gen -fixed no 96 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_state128_0_I_38_i_0_x2_0 -fixed no 340 51
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO\[16\] -fixed no 373 48
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/prdata_0_iv_0\[9\] -fixed no 388 57
set_location UART_INTERFACE_0/FabUART_0/uart_data_out_t\[0\] -fixed no 184 22
set_location Receiver_0/Downsampler_0/reg_check\[8\] -fixed no 76 28
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNICO3L\[0\] -fixed no 394 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[7\] -fixed no 280 63
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[2\] -fixed no 369 52
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/control_reg_14_0_a2 -fixed no 391 48
set_location UART_INTERFACE_0/FabUART_0/uart_data_out_t\[2\] -fixed no 194 22
set_location Transmitter_0/prbs7_10_0/LFSR_RNO\[4\] -fixed no 264 6
set_location Receiver_0/prbs7_10_0/LFSR_RNO\[6\] -fixed no 112 18
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD3_13\[5\] -fixed no 86 21
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11\[0\] -fixed no 80 18
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/cntr_2bit_RNO\[0\] -fixed no 122 24
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0\[26\] -fixed no 277 51
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNI8J2L\[0\] -fixed no 393 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[14\] -fixed no 357 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[12\] -fixed no 278 60
set_location Receiver_0/receive_buffer_top_0/receive_control_0/RC_FSM_state\[1\] -fixed no 67 25
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwrite -fixed no 391 52
set_location Receiver_0/prbs7_10_0/un1_lock_count13_i_o2_0_2 -fixed no 113 21
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_m0\[0\] -fixed no 64 18
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREVDATASLAVEREADY_iv -fixed no 321 48
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[25\] -fixed no 57 19
set_location IGLOO2_Oversampling_0/CORERESETP_0/RESET_N_M2F_q1 -fixed no 366 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[10\] -fixed no 285 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_d_HWRITE51 -fixed no 314 51
set_location IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int_RNO -fixed no 361 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_bytecount\[3\] -fixed no 303 60
set_location Transmitter_0/prbs7_10_0/W_0_x2\[5\] -fixed no 270 6
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[27\] -fixed no 340 58
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/un2_count_hot_6 -fixed no 84 27
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[26\] -fixed no 337 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[9\] -fixed no 351 66
set_location UART_INTERFACE_0/FabUART_0/uart_data_out_t\[1\] -fixed no 195 22
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/DA_FSM_STATE_ns_1_0_.m5_i -fixed no 104 24
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[25\] -fixed no 353 67
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_state128_0_I_68_i_0_x2 -fixed no 331 60
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/cntr_2bit_zero -fixed no 120 25
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState\[1\] -fixed no 299 46
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[26\] -fixed no 277 52
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2_RNI3PUQ\[0\] -fixed no 284 45
set_location IGLOO2_Oversampling_0/ConfigMaster_0/pause_count_RNO\[4\] -fixed no 295 42
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[18\] -fixed no 326 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_tr13 -fixed no 279 51
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[35\] -fixed no 56 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_2\[13\] -fixed no 258 60
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg\[6\] -fixed no 390 58
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D0\[8\] -fixed no 63 31
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[23\] -fixed no 344 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[25\] -fixed no 266 52
set_location UART_INTERFACE_0/FabUART_0/state\[6\] -fixed no 200 19
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_RNO\[3\] -fixed no 292 45
set_location IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0\[6\] -fixed no 360 43
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[4\] -fixed no 73 19
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/xmit_cntr\[1\] -fixed no 206 19
set_location Transmitter_0/FIFO_PRBS_0/data\[9\] -fixed no 261 7
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[24\] -fixed no 276 51
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_bit_sel_RNO\[2\] -fixed no 213 24
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[31\] -fixed no 377 49
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[24\] -fixed no 73 16
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_state_ns_0_a3_0_4\[0\] -fixed no 246 12
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[24\] -fixed no 60 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[30\] -fixed no 355 61
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HWRITE_0_sqmuxa_1 -fixed no 313 51
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2_13\[3\] -fixed no 101 30
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11\[16\] -fixed no 99 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[5\] -fixed no 267 61
set_location UART_INTERFACE_0/FabUART_0/uart_data_out_t_RNO\[1\] -fixed no 195 21
set_location Receiver_0/Downsampler_0/reg_check_12\[7\] -fixed no 89 27
set_location IGLOO2_Oversampling_0/CORERESETP_0/sdif0_spll_lock_q2 -fixed no 377 43
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_state_RNO\[1\] -fixed no 238 12
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/trans_detect_bit37 -fixed no 61 27
set_location Receiver_0/prbs7_10_0/reg_lock_again5_0_a2 -fixed no 190 18
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_m0\[7\] -fixed no 76 21
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[34\] -fixed no 55 19
set_location UART_INTERFACE_0/FabUART_0/state_RNO\[7\] -fixed no 192 21
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/paddr\[7\] -fixed no 364 46
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL\[11\] -fixed no 305 45
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[15\] -fixed no 363 58
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PSLVERR_RNO -fixed no 399 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[17\] -fixed no 55 25
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[20\] -fixed no 86 19
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/paddr\[12\] -fixed no 358 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[24\] -fixed no 278 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_d_HWRITE_0_sqmuxa -fixed no 292 57
set_location Transmitter_0/FIFO_PRBS_0/i\[0\] -fixed no 263 4
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2\[7\] -fixed no 82 22
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[24\] -fixed no 351 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[0\] -fixed no 256 52
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out_7\[1\] -fixed no 257 6
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[19\] -fixed no 260 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[24\] -fixed no 276 52
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[17\] -fixed no 88 22
set_location UART_INTERFACE_0/COREUART_0/make_RX/rcv_cnt.receive_count_3\[2\] -fixed no 245 12
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_state128_0_I_56_i_0_x2 -fixed no 327 60
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D0\[11\] -fixed no 65 28
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2 -fixed no 311 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[17\] -fixed no 345 66
set_location IGLOO2_Oversampling_0/ConfigMaster_0/expected\[18\] -fixed no 336 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[7\] -fixed no 279 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[21\] -fixed no 269 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[20\] -fixed no 316 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HSIZE\[1\] -fixed no 311 61
set_location Receiver_0/Downsampler_0/reg_data_out\[2\] -fixed no 70 22
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_9 -fixed no 332 60
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD3_RNO\[6\] -fixed no 78 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/bytecount\[2\] -fixed no 292 64
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[10\] -fixed no 105 31
set_location IGLOO2_Oversampling_0/ConfigMaster_0/pause_count_RNO\[2\] -fixed no 300 42
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[2\] -fixed no 269 64
set_location UART_INTERFACE_0/FabUART_0/state\[10\] -fixed no 192 19
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[30\] -fixed no 79 16
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out_RNIPB2H\[7\] -fixed no 256 6
set_location FCCC_0/CCC_INST_RNIIJ03/U0_RGB1 -fixed no 220 24
set_location UART_INTERFACE_0/FabUART_0/state_RNO\[4\] -fixed no 182 21
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/lock_gen_RNO -fixed no 96 24
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[14\] -fixed no 284 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[19\] -fixed no 277 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/bytecount\[7\] -fixed no 308 61
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2_13\[5\] -fixed no 87 21
set_location IGLOO2_Oversampling_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_clk_base -fixed no 359 49
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL\[3\] -fixed no 306 45
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HWRITE51_10 -fixed no 291 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/pause_count_RNO\[1\] -fixed no 299 42
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO\[21\] -fixed no 372 48
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/prdata_0_iv_0_a2_3\[0\] -fixed no 394 48
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D0\[0\] -fixed no 61 28
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD3\[8\] -fixed no 66 19
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_RNO\[2\] -fixed no 297 45
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_1\[5\] -fixed no 310 45
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[11\] -fixed no 247 58
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/paddr\[5\] -fixed no 354 49
set_location SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_RGB1 -fixed no 219 30
set_location Receiver_0/Downsampler_0/temp_data\[9\] -fixed no 110 22
set_location Transmitter_0/FIFO_PRBS_0/data\[27\] -fixed no 270 4
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[23\] -fixed no 67 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/bytecount\[8\] -fixed no 296 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_bytecount\[14\] -fixed no 320 63
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out_7_0\[0\] -fixed no 261 6
set_location IGLOO2_Oversampling_0/ConfigMaster_0/envm_busy\[1\] -fixed no 289 43
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_ins2_0_sqmuxa -fixed no 271 57
set_location Receiver_0/Downsampler_0/reg_data_out\[3\] -fixed no 115 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0\[22\] -fixed no 258 57
set_location Receiver_0/prbs7_10_0/un1_tx_count17_1_0_0_o2 -fixed no 122 18
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_state_ns_i_a3_0_1\[1\] -fixed no 247 12
set_location IGLOO2_Oversampling_0/CORERESETP_0/next_sm0_state12 -fixed no 377 42
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO\[14\] -fixed no 282 60
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[24\] -fixed no 74 28
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[20\] -fixed no 361 63
set_location IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0\[3\] -fixed no 357 43
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_4 -fixed no 338 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[6\] -fixed no 341 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[10\] -fixed no 286 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[28\] -fixed no 259 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/count_RNIHIHO2\[1\] -fixed no 331 63
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/paddr\[14\] -fixed no 386 52
set_location Transmitter_0/AND2_0 -fixed no 139 15
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state\[5\] -fixed no 307 52
set_location IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_enable_RNO_0 -fixed no 375 42
set_location Receiver_0/Downsampler_0/reg_check\[6\] -fixed no 106 28
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[10\] -fixed no 383 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[4\] -fixed no 265 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_bytecount_2_sqmuxa_2 -fixed no 294 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_count_2_sqmuxa -fixed no 316 60
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[30\] -fixed no 363 46
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[33\] -fixed no 72 16
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[10\] -fixed no 283 46
set_location UART_INTERFACE_0/FabUART_0/uart_data_out_t_22_i_0\[1\] -fixed no 191 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state\[10\] -fixed no 308 58
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/HSIZE\[0\] -fixed no 333 48
set_location Receiver_0/prbs7_10_0/un1_lock_count13_i_o2_0_5 -fixed no 114 18
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_14 -fixed no 364 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[0\] -fixed no 300 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[14\] -fixed no 358 61
set_location IGLOO2_Oversampling_0/CORERESETP_0/CLR_INIT_DONE_q1 -fixed no 383 46
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[17\] -fixed no 97 22
set_location Receiver_0/prbs7_10_0/rx_count\[0\] -fixed no 122 19
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[28\] -fixed no 353 49
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[25\] -fixed no 75 28
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[25\] -fixed no 282 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[21\] -fixed no 336 66
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[13\] -fixed no 354 66
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[28\] -fixed no 269 52
set_location UART_INTERFACE_0/COREUART_0/make_RX/rcv_cnt.receive_count8 -fixed no 241 12
set_location UART_INTERFACE_0/FabUART_0/state_RNO\[10\] -fixed no 192 18
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11\[4\] -fixed no 73 18
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[25\] -fixed no 65 19
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/paddr\[11\] -fixed no 361 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_state128_0_I_92_i_x2 -fixed no 365 57
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[13\] -fixed no 356 46
set_location Receiver_0/Downsampler_0/reg_rx_val_out -fixed no 112 22
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/prdata_0_iv_0_a2_0_0\[0\] -fixed no 389 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/count_RNIHIHO2_0\[0\] -fixed no 328 63
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns_1\[28\] -fixed no 98 30
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNINTKO\[0\] -fixed no 370 57
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[6\] -fixed no 391 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[21\] -fixed no 341 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_d_HWRITE51_0 -fixed no 306 60
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/make_xmit_clock.xmit_cntr_3_1.SUM\[1\] -fixed no 206 18
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[18\] -fixed no 78 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[11\] -fixed no 311 64
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1_RNO\[6\] -fixed no 82 24
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2_13\[7\] -fixed no 81 21
set_location Transmitter_0/prbs7_10_0/LFSR\[3\] -fixed no 271 7
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_2\[6\] -fixed no 240 57
set_location UART_INTERFACE_0/COREUART_0/make_TX/tx_byte\[3\] -fixed no 206 25
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_21 -fixed no 350 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_m0\[10\] -fixed no 77 21
set_location UART_INTERFACE_0/FabUART_0/uart_data_out_t_RNO_0\[2\] -fixed no 194 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[26\] -fixed no 337 64
set_location Receiver_0/Downsampler_0/temp_data_12\[1\] -fixed no 109 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata_RNIHVDG6\[11\] -fixed no 349 60
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/prdata_0_iv_0\[6\] -fixed no 391 57
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_10 -fixed no 330 51
set_location Transmitter_0/FIFO_PRBS_0/data\[6\] -fixed no 267 4
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[1\] -fixed no 67 28
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/rx_data_debug\[6\] -fixed no 49 22
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/trans_detect_bit96 -fixed no 65 27
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNI5G2L\[0\] -fixed no 387 60
set_location Receiver_0/Downsampler_0/reg_check_12\[4\] -fixed no 104 21
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_m0\[5\] -fixed no 67 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_0_i_o2_RNIJIPV\[7\] -fixed no 319 60
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B/U0_RGB1 -fixed no 221 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11\[17\] -fixed no 97 21
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg\[0\] -fixed no 389 49
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_state_ns_i_i_o2\[3\] -fixed no 214 24
set_location Receiver_0/prbs7_10_0/LFSR_RNO\[2\] -fixed no 111 18
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2\[1\] -fixed no 99 31
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state\[11\] -fixed no 305 52
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_23 -fixed no 361 51
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1\[4\] -fixed no 95 19
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2_RNI156N\[0\] -fixed no 318 45
set_location IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc_RNIH0E4/U0_RGB1 -fixed no 220 42
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[20\] -fixed no 284 48
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg\[4\] -fixed no 373 58
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[22\] -fixed no 407 58
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/make_xmit_clock.xmit_cntr_3_1.SUM\[0\] -fixed no 211 18
set_location IGLOO2_Oversampling_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_q1 -fixed no 356 49
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/DA_FSM_STATE\[1\] -fixed no 107 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[5\] -fixed no 337 66
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_bytecount4_3 -fixed no 264 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_tr21 -fixed no 324 57
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_shift\[6\] -fixed no 210 13
set_location UART_INTERFACE_0/FabUART_0/un1_uart_data_out_t_0_sqmuxa_9_i_o4 -fixed no 197 18
set_location IGLOO2_Oversampling_0/CORERESETP_0/CLR_INIT_DONE_clk_base -fixed no 377 46
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/prdata_0_iv_0_a2_4\[0\] -fixed no 387 51
set_location Receiver_0/prbs7_10_0/LFSR\[6\] -fixed no 116 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[17\] -fixed no 331 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_state128_0_I_8_i_0_x2 -fixed no 325 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[26\] -fixed no 273 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[31\] -fixed no 263 48
set_location Receiver_0/Downsampler_0/reg_error5_i -fixed no 90 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[14\] -fixed no 358 60
set_location Receiver_0/prbs7_10_0/rx_count_RNO\[0\] -fixed no 121 18
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_cnt.xmit_bit_sel_3_a3_0_a2\[0\] -fixed no 204 24
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[8\] -fixed no 72 25
set_location IGLOO2_Oversampling_0/CORERESETP_0/CONFIG_DONE_clk_base -fixed no 382 43
set_location IGLOO2_Oversampling_0/CORERESETP_0/POWER_ON_RESET_N_clk_base -fixed no 359 52
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/paddr\[10\] -fixed no 357 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[26\] -fixed no 359 58
set_location IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core4_1 -fixed no 353 42
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[21\] -fixed no 272 48
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1_RNO\[4\] -fixed no 96 21
set_location UART_INTERFACE_0/FabUART_0/state_RNO\[2\] -fixed no 197 21
set_location UART_INTERFACE_0/FabUART_0/state_ns_i_i_1_0\[0\] -fixed no 196 15
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[12\] -fixed no 276 61
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out_7_0\[1\] -fixed no 263 3
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_m0\[21\] -fixed no 83 27
set_location IGLOO2_Oversampling_0/CORERESETP_0/CONFIG_DONE_q1 -fixed no 383 43
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNIKQKO\[0\] -fixed no 366 57
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_byte\[0\] -fixed no 214 16
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[8\] -fixed no 281 46
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2_8 -fixed no 304 48
set_location UART_INTERFACE_0/COREUART_0/make_RX/rcv_cnt.receive_count_3\[0\] -fixed no 250 12
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[31\] -fixed no 271 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[10\] -fixed no 338 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HWRITE51_2_0_5 -fixed no 299 63
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PREADY_RNO -fixed no 385 51
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO\[19\] -fixed no 403 57
set_location Receiver_0/prbs7_10_0/lock_count11_0_a2 -fixed no 127 18
set_location UART_INTERFACE_0/FabUART_0/un21_i_a2_i_1_0 -fixed no 212 15
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[10\] -fixed no 334 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/pause_count_n4_0_1871_o4 -fixed no 298 42
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[21\] -fixed no 339 67
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D0\[5\] -fixed no 72 31
set_location FCCC_0/GL0_INST -fixed no 222 54
set_location UART_INTERFACE_0/FabUART_0/state_ns_i_i_o4\[0\] -fixed no 206 15
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO\[24\] -fixed no 405 57
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_bit_sel_RNO\[1\] -fixed no 205 24
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11\[3\] -fixed no 74 18
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/HWRITE -fixed no 330 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[16\] -fixed no 250 52
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/xmit_cntr\[3\] -fixed no 208 19
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO\[18\] -fixed no 378 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[26\] -fixed no 333 63
set_location UART_INTERFACE_0/FabUART_0/genrate_err_t_3_iv_0_o4 -fixed no 205 15
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[15\] -fixed no 87 22
set_location Transmitter_0/prbs7_10_0/LFSR\[5\] -fixed no 266 7
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR\[18\] -fixed no 282 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HSIZE9_RNIE8F23 -fixed no 327 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_bytecount\[10\] -fixed no 297 63
set_location IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_clk_base_RNIBNH7/U0_RGB1 -fixed no 222 45
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11\[14\] -fixed no 103 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HTRANS_0_sqmuxa_1_0 -fixed no 301 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_state_2_sqmuxa_RNI284E1 -fixed no 302 60
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR\[20\] -fixed no 286 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[27\] -fixed no 267 57
set_location Receiver_0/Downsampler_0/temp_data_12\[6\] -fixed no 109 24
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.make_baud_cntr.baud_cntr8_7 -fixed no 260 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[16\] -fixed no 240 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[9\] -fixed no 287 63
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/rx_data_debug\[4\] -fixed no 54 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[11\] -fixed no 353 60
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/xmit_cntr\[2\] -fixed no 207 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0\[0\] -fixed no 249 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[1\] -fixed no 343 66
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_0\[16\] -fixed no 296 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_tr32 -fixed no 291 42
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_fast\[0\] -fixed no 242 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO\[11\] -fixed no 250 57
set_location Transmitter_0/prbs7_10_0/LFSR\[1\] -fixed no 269 7
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[8\] -fixed no 281 61
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_byte\[2\] -fixed no 208 16
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[31\] -fixed no 342 58
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/prdata_0_iv_0\[1\] -fixed no 400 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_d_HADDR_0_sqmuxa -fixed no 309 60
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNI6I3L\[0\] -fixed no 360 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[13\] -fixed no 253 61
set_location IGLOO2_Oversampling_0/CORERESETP_0/sdif0_areset_n_i -fixed no 370 48
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[5\] -fixed no 72 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[29\] -fixed no 356 67
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state\[9\] -fixed no 274 58
set_location UART_INTERFACE_0/FabUART_0/state_ns_i_i_0\[0\] -fixed no 188 21
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/HSIZE\[1\] -fixed no 331 48
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11\[15\] -fixed no 98 21
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/HTRANS -fixed no 319 45
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_state_ns_i_i\[3\] -fixed no 211 24
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR\[26\] -fixed no 332 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[21\] -fixed no 339 66
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[11\] -fixed no 249 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[7\] -fixed no 346 63
set_location Receiver_0/prbs7_10_0/rx_count\[1\] -fixed no 123 19
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD3_13\[1\] -fixed no 84 30
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_bytecount\[9\] -fixed no 298 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[2\] -fixed no 270 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[22\] -fixed no 338 60
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[4\] -fixed no 74 31
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0_1\[30\] -fixed no 264 48
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns_1\[9\] -fixed no 74 21
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[15\] -fixed no 101 22
set_location Transmitter_0/FIFO_PRBS_0/data\[12\] -fixed no 269 4
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out_RNIL72H\[3\] -fixed no 254 6
set_location Receiver_0/Downsampler_0/temp_data_12\[9\] -fixed no 110 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[4\] -fixed no 347 52
set_location UART_INTERFACE_0/FabUART_0/start_t_3_iv_i_m4 -fixed no 198 15
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[21\] -fixed no 333 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[2\] -fixed no 302 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/bytecount\[14\] -fixed no 320 64
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_sel.tx_2_7_i_m2_ns -fixed no 210 24
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[24\] -fixed no 67 19
set_location Receiver_0/prbs7_10_0/un1_lock_count13_i_o2_0_3 -fixed no 116 18
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2_13\[8\] -fixed no 68 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[25\] -fixed no 343 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[8\] -fixed no 281 60
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR\[31\] -fixed no 317 45
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2_RNI1NUQ\[0\] -fixed no 287 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_count_1_sqmuxa_1 -fixed no 322 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_0_a3_0\[8\] -fixed no 299 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[22\] -fixed no 340 60
set_location Transmitter_0/prbs7_10_0/reg_tx_val -fixed no 273 7
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/INIT_DONE_q2 -fixed no 385 49
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out\[7\] -fixed no 257 4
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_bit_cnt_0_sqmuxa_0_a3 -fixed no 239 12
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_state_2_sqmuxa -fixed no 298 57
set_location UART_INTERFACE_0/FabUART_0/state_ns_0\[6\] -fixed no 200 18
set_location Receiver_0/Downsampler_0/reg_check\[3\] -fixed no 80 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[20\] -fixed no 345 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0\[24\] -fixed no 278 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/bytecount\[11\] -fixed no 295 64
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR\[28\] -fixed no 293 48
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/cntr_2bit\[1\] -fixed no 121 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0\[7\] -fixed no 278 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/count_RNO\[1\] -fixed no 319 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0\[5\] -fixed no 276 63
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/control_reg_29_0_a2_2 -fixed no 395 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO\[6\] -fixed no 252 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[29\] -fixed no 275 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state\[13\] -fixed no 303 52
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[29\] -fixed no 64 19
set_location Transmitter_0/prbs7_10_0/LFSR\[7\] -fixed no 268 7
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/SDIF0_PENABLE -fixed no 381 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_state_32_10 -fixed no 310 57
set_location UART_INTERFACE_0/COREUART_0/make_TX/tx_byte\[5\] -fixed no 209 25
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2_9_5 -fixed no 310 48
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_byte\[7\] -fixed no 210 16
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[29\] -fixed no 274 49
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[28\] -fixed no 93 28
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out\[9\] -fixed no 253 7
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_m0\[8\] -fixed no 80 21
set_location UART_INTERFACE_0/FabUART_0/scan_t -fixed no 201 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[27\] -fixed no 267 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[10\] -fixed no 285 63
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_24 -fixed no 350 51
set_location Receiver_0/Downsampler_0/temp_data\[3\] -fixed no 111 25
set_location UART_INTERFACE_0/COREUART_0/tx_hold_reg\[4\] -fixed no 209 22
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/paddr\[13\] -fixed no 393 52
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt\[9\] -fixed no 305 49
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D0\[1\] -fixed no 60 28
set_location IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core4_7 -fixed no 351 42
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNI7K4L\[0\] -fixed no 359 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_tr23 -fixed no 325 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HSIZE\[0\] -fixed no 304 61
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_1\[8\] -fixed no 280 60
set_location UART_INTERFACE_0/COREUART_0/make_RX/samples\[2\] -fixed no 251 13
set_location Receiver_0/prbs7_10_0/un1_data_in_0 -fixed no 118 18
set_location UART_INTERFACE_0/FabUART_0/state_ns_0_a3\[1\] -fixed no 195 15
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[6\] -fixed no 78 31
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/un17_count_hot_5 -fixed no 84 24
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns\[20\] -fixed no 103 27
set_location Receiver_0/prbs7_10_0/LFSR\[1\] -fixed no 119 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_i_i_a4\[3\] -fixed no 305 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[27\] -fixed no 258 49
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/un17_count_hot_6 -fixed no 86 30
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out\[5\] -fixed no 255 4
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[8\] -fixed no 83 28
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HWRITE51_0_0 -fixed no 288 60
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11\[21\] -fixed no 82 27
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[23\] -fixed no 89 28
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[21\] -fixed no 321 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[1\] -fixed no 337 52
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[16\] -fixed no 84 22
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_1 -fixed no 329 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[16\] -fixed no 364 63
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[26\] -fixed no 380 49
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt\[8\] -fixed no 306 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[25\] -fixed no 353 66
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[19\] -fixed no 277 49
set_location Transmitter_0/Replicator_0/X\[21\] -fixed no 256 7
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[17\] -fixed no 247 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[4\] -fixed no 266 61
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[27\] -fixed no 381 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_state_30\[0\] -fixed no 318 51
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/trans_detect_bit9 -fixed no 69 28
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[16\] -fixed no 251 52
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_20 -fixed no 341 51
set_location UART_INTERFACE_0/FabUART_0/state\[15\] -fixed no 204 19
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[7\] -fixed no 85 28
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_shift\[5\] -fixed no 207 13
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[3\] -fixed no 72 28
set_location Receiver_0/prbs7_10_0/reg_error\[4\] -fixed no 185 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HWRITE_1_sqmuxa_1 -fixed no 296 60
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[2\] -fixed no 96 31
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState\[13\] -fixed no 296 46
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR\[14\] -fixed no 287 45
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2_13\[1\] -fixed no 80 27
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[13\] -fixed no 58 22
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[30\] -fixed no 401 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_bytecount\[15\] -fixed no 321 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state\[8\] -fixed no 304 58
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out_RNIRD2H\[9\] -fixed no 253 6
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO\[25\] -fixed no 376 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/pause_count\[0\] -fixed no 298 43
set_location IGLOO2_Oversampling_0/CORERESETP_0/ddr_ready -fixed no 371 43
set_location Receiver_0/Downsampler_0/reg_check\[4\] -fixed no 106 22
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out_7\[7\] -fixed no 257 3
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_VALOUT_reg -fixed no 83 25
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg5_0_a2 -fixed no 393 48
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[6\] -fixed no 241 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[25\] -fixed no 348 66
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[12\] -fixed no 368 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_0_a3_0_a5\[0\] -fixed no 288 45
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[2\] -fixed no 56 28
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/trans_detect_bit3_2_sqmuxa_i -fixed no 63 27
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNIBN3L\[0\] -fixed no 392 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/count_RNIHIHO2_1\[0\] -fixed no 329 66
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/control_reg_2 -fixed no 384 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state\[20\] -fixed no 288 43
set_location IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNIJHLS_5 -fixed no 335 51
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns\[25\] -fixed no 75 27
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[14\] -fixed no 93 19
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/psel -fixed no 383 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[14\] -fixed no 282 61
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_bit_sel\[0\] -fixed no 204 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[11\] -fixed no 250 58
set_location UART_INTERFACE_0/COREUART_0/make_RX/receive_count\[0\] -fixed no 250 13
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg\[10\] -fixed no 382 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_1_sqmuxa_1 -fixed no 296 57
set_location SERDES_IF_0/EPCS_1_TX_CLK_inferred_clock_RNI9VS5/U0_RGB1 -fixed no 223 15
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNIS2LO\[0\] -fixed no 359 66
set_location UART_INTERFACE_0/FabUART_0/state\[2\] -fixed no 197 22
set_location UART_INTERFACE_0/FabUART_0/state_RNO\[8\] -fixed no 193 21
set_location FCCC_0/GL1_INST/U0_RGB1 -fixed no 220 0
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[1\] -fixed no 301 64
set_location UART_INTERFACE_0/FabUART_0/state_RNO\[15\] -fixed no 204 18
set_location Receiver_0/Downsampler_0/temp_data\[8\] -fixed no 110 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/pause_count\[1\] -fixed no 299 43
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_state\[1\] -fixed no 213 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_state_32_9 -fixed no 306 57
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_m0\[23\] -fixed no 87 27
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/trans_detect_bit6 -fixed no 61 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[14\] -fixed no 284 61
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[16\] -fixed no 361 61
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[22\] -fixed no 340 61
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[11\] -fixed no 102 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata_RNITK783\[28\] -fixed no 367 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_d_state_1_sqmuxa_2\[0\] -fixed no 306 51
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/un2_count_hot -fixed no 83 18
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[28\] -fixed no 375 49
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[4\] -fixed no 89 31
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNIEQ3L\[0\] -fixed no 358 66
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/cntr_2bit\[0\] -fixed no 122 25
set_location UART_INTERFACE_0/COREUART_0/make_TX/txrdy_int -fixed no 211 22
set_location UART_INTERFACE_0/FabUART_0/state_ns_0_a2_0\[1\] -fixed no 200 15
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[0\] -fixed no 90 31
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg_11_ns\[27\] -fixed no 91 27
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[28\] -fixed no 365 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/bytecount\[3\] -fixed no 303 61
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out\[0\] -fixed no 254 7
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt\[1\] -fixed no 304 46
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[14\] -fixed no 56 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_0\[8\] -fixed no 304 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_state_18 -fixed no 279 57
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[11\] -fixed no 367 52
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[12\] -fixed no 398 58
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2\[6\] -fixed no 87 28
set_location Transmitter_0/FIFO_PRBS_0/flag_RNIUQIH -fixed no 264 3
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[23\] -fixed no 345 58
set_location Receiver_0/receive_buffer_top_0/receive_control_0/start_lock_reg -fixed no 69 25
set_location UART_INTERFACE_0/FabUART_0/connect_t -fixed no 198 19
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL\[5\] -fixed no 307 45
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_2_RNO\[8\] -fixed no 279 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1\[26\] -fixed no 288 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[3\] -fixed no 346 60
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3\[12\] -fixed no 91 22
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA\[5\] -fixed no 340 67
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_bit_sel\[3\] -fixed no 215 25
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL\[15\] -fixed no 303 48
set_location UART_INTERFACE_0/FabUART_0/un1_state_4_1_i_0 -fixed no 203 18
set_location IGLOO2_Oversampling_0/CORERESETP_0/ddr_ready_q1 -fixed no 381 43
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_0_i_a4_0\[7\] -fixed no 318 60
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg\[29\] -fixed no 94 28
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[2\] -fixed no 328 58
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out\[1\] -fixed no 252 7
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[27\] -fixed no 361 46
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/rx_data_debug\[9\] -fixed no 42 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state_ns_0_a3\[14\] -fixed no 293 42
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata\[28\] -fixed no 353 58
set_location Receiver_0/prbs7_10_0/lock_count_3_i_x2\[1\] -fixed no 128 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1_RNIIKIR1_0\[22\] -fixed no 318 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HSIZE9_RNIE8F23_3 -fixed no 325 63
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[1\] -fixed no 63 25
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[3\] -fixed no 367 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO\[28\] -fixed no 371 60
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState\[0\] -fixed no 294 46
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv\[24\] -fixed no 275 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[30\] -fixed no 355 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_state128_0_I_74_i_0_x2 -fixed no 354 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write\[22\] -fixed no 258 58
set_location IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0\[9\] -fixed no 363 43
set_location IGLOO2_Oversampling_0/ConfigMaster_0/rdata_RNIL3EG6\[13\] -fixed no 349 66
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA\[8\] -fixed no 384 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR\[24\] -fixed no 275 52
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/cntr_2bit_en_RNO -fixed no 101 24
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_bytecount\[1\] -fixed no 289 63
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/INIT_DONE_q3 -fixed no 386 49
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_state_29_1 -fixed no 301 57
set_location UART_INTERFACE_0/COREUART_0/make_TX/xmit_state_ns_0\[2\] -fixed no 214 21
set_location UART_INTERFACE_0/COREUART_0/make_RX/rx_byte\[6\] -fixed no 207 16
set_location IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int_RNICDJF_0 -fixed no 220 54
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL\[1\] -fixed no 304 45
set_location UART_INTERFACE_0/FabUART_0/uart_data_out_t_RNO\[0\] -fixed no 181 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_d_HWRITE_1_sqmuxa -fixed no 277 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[3\] -fixed no 244 58
set_location UART_INTERFACE_0/FabUART_0/state_ns_0\[1\] -fixed no 199 18
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg\[8\] -fixed no 385 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[2\] -fixed no 270 64
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[22\] -fixed no 287 58
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD3\[1\] -fixed no 86 31
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[29\] -fixed no 47 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[10\] -fixed no 272 61
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1\[25\] -fixed no 76 16
set_location IGLOO2_Oversampling_0/CORECONFIGP_0/pwdata\[29\] -fixed no 366 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un1_state_17 -fixed no 297 57
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[1\] -fixed no 253 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[11\] -fixed no 332 58
set_location Transmitter_0/FIFO_PRBS_0/flag -fixed no 264 4
set_location Receiver_0/prbs7_10_0/un1_lock_count13_i_o2_0_0 -fixed no 113 18
set_location IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt\[15\] -fixed no 303 49
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[5\] -fixed no 76 31
set_location UART_INTERFACE_0/FabUART_0/uart_data_out_t_RNO\[2\] -fixed no 194 21
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins2\[16\] -fixed no 246 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/haddr_fetch\[26\] -fixed no 267 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[8\] -fixed no 359 60
set_location UART_INTERFACE_0/COREUART_0/make_RX/un1_samples7_1_0 -fixed no 229 12
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_iv_0\[21\] -fixed no 268 48
set_location IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_enable -fixed no 372 43
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[15\] -fixed no 368 58
set_location Transmitter_0/FIFO_PRBS_0/reg_data_out\[8\] -fixed no 256 4
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_HSIZE9_RNIE8F23_2 -fixed no 326 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/mask\[20\] -fixed no 344 58
set_location IGLOO2_Oversampling_0/ConfigMaster_0/state\[1\] -fixed no 298 52
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HADDR_RNO\[30\] -fixed no 265 48
set_location Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data\[39\] -fixed no 43 19
set_location IGLOO2_Oversampling_0/ConfigMaster_0/HWDATA_RNO_0\[15\] -fixed no 353 63
set_location IGLOO2_Oversampling_0/CCC_0/CCC_INST -fixed no 390 92
set_location FCCC_0/CCC_INST -fixed no 372 92
set_location UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.make_baud_cntr.baud_cntr8_1_RNI29NL1 -fixed no 246 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/ins1_RNIL8BU8\[0\] -fixed no 300 63
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un11_d_HADDR_cry_27_1 -fixed no 252 51
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un32_d_HADDR_cry_0_0 -fixed no 240 48
set_location IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_s_132 -fixed no 354 42
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un32_d_HADDR_cry_0 -fixed no 240 60
set_location IGLOO2_Oversampling_0/ConfigMaster_0/un11_d_HADDR_s_1_133 -fixed no 264 60
set_location Receiver_0/prbs7_10_0/reg_error_cry_cy\[0\] -fixed no 180 18
set_location IGLOO2_Oversampling_0/ConfigMaster_0/d_state128_0_I_1 -fixed no 327 57
