<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<title>Compile Report</title>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.3 (Version 11.3.0.112)</text>
<text>Date: Fri Apr 18 09:31:10 2014
</text>
<section><name>Device Selection</name></section>
<table>
<header>
</header>
<row>
 <cell>Family</cell>
 <cell>IGLOO2</cell>
</row>
<row>
 <cell>Device</cell>
 <cell>M2GL010T</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Temp</cell>
 <cell>0:25:85</cell>
</row>
<row>
 <cell>Voltage</cell>
 <cell>1.26:1.20:1.14</cell>
</row>
<row>
 <cell>Core Voltage</cell>
 <cell>1.2V</cell>
</row>
<row>
 <cell>Ramp Rate</cell>
 <cell>100ms Minimum</cell>
</row>
<row>
 <cell>System Controller Suspend Mode</cell>
 <cell>No</cell>
</row>
<row>
 <cell>PLL Supply Voltage</cell>
 <cell>2.5V</cell>
</row>
<row>
 <cell>Default I/O technology</cell>
 <cell>LVCMOS 2.5V</cell>
</row>
<row>
 <cell>Restrict Probe Pins</cell>
 <cell>Yes</cell>
</row>
</table>
<section><name>Source Files</name></section>
<table>
<header>
</header>
<row>
 <cell>Topcell</cell>
 <cell>IGLOO2_Oversampling_top</cell>
</row>
<row>
 <cell>Format</cell>
 <cell>EDIF</cell>
</row>
<row>
 <cell>Source</cell>
 <cell>C:\Microsemi\IGLOO2_Oversampling\synthesis\IGLOO2_Oversampling_top.edn</cell>
</row>
<row>
 <cell>Source</cell>
 <cell>C:\Microsemi\IGLOO2_Oversampling\constraint\io\IGLOO2_Oversampling_top.io.pdc</cell>
</row>
</table>
<section><name>Options</name></section>
<table>
<header>
</header>
<row>
 <cell>Merge User SDC file(s) with Existing Timing Constraints</cell>
 <cell>true</cell>
</row>
<row>
 <cell>Abort Compile if errors are found in PDC file(s)</cell>
 <cell>true</cell>
</row>
<row>
 <cell>Limit the number of high fanout nets to display to</cell>
 <cell>10</cell>
</row>
</table>
<section><name>Netlist Optimization</name></section>
<table>
<header>
</header>
<row>
 <cell>Dangling net drivers</cell>
 <cell>21</cell>
</row>
<row>
 <cell>Buffers</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Inverters</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Tieoff</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Fan-In combining</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Logic combining</cell>
 <cell>0</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Total macros optimized</cell>
 <cell>21</cell>
</row>
</table>
<section><name>Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Used</cell>
 <cell>Total</cell>
 <cell>Percentage</cell>
</header>
<row>
 <cell>COMB</cell>
 <cell>1101</cell>
 <cell>12084</cell>
 <cell>9.11</cell>
</row>
<row>
 <cell>SEQ</cell>
 <cell>989</cell>
 <cell>12084</cell>
 <cell>8.18</cell>
</row>
<row>
 <cell>IO (W/ clocks)</cell>
 <cell>5</cell>
 <cell>231</cell>
 <cell>2.16</cell>
</row>
<row>
 <cell>Differential IO</cell>
 <cell>0</cell>
 <cell>115</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>GLOBAL</cell>
 <cell>8</cell>
 <cell>8</cell>
 <cell>100.00</cell>
</row>
<row>
 <cell>RGB</cell>
 <cell>13</cell>
 <cell>272</cell>
 <cell>4.78</cell>
</row>
<row>
 <cell>RAM64x18</cell>
 <cell>0</cell>
 <cell>22</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>RAM1K18</cell>
 <cell>0</cell>
 <cell>21</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>MACC</cell>
 <cell>0</cell>
 <cell>22</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>RCOSC_25_50MHZ</cell>
 <cell>1</cell>
 <cell>1</cell>
 <cell>100.00</cell>
</row>
<row>
 <cell>RCOSC_1MHZ</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>XTLOSC</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>CCC</cell>
 <cell>2</cell>
 <cell>2</cell>
 <cell>100.00</cell>
</row>
<row>
 <cell>SERDESIF</cell>
 <cell>1</cell>
 <cell>1</cell>
 <cell>100.00</cell>
</row>
<row>
 <cell>MSS</cell>
 <cell>1</cell>
 <cell>1</cell>
 <cell>100.00</cell>
</row>
<row>
 <cell>SYSCTRL</cell>
 <cell>1</cell>
 <cell>1</cell>
 <cell>100.00</cell>
</row>
</table>
<section><name>Carry Chains</name></section>
<table>
<header>
</header>
<row>
 <cell>Length</cell>
 <cell>Used</cell>
</row>
<row>
 <cell>7</cell>
 <cell>1</cell>
</row>
<row>
 <cell>13</cell>
 <cell>2</cell>
</row>
<row>
 <cell>14</cell>
 <cell>1</cell>
</row>
<row>
 <cell>16</cell>
 <cell>2</cell>
</row>
<row>
 <cell>17</cell>
 <cell>1</cell>
</row>
<row>
 <cell>21</cell>
 <cell>1</cell>
</row>
<row>
 <cell>23</cell>
 <cell>1</cell>
</row>
<row>
 <cell>Total</cell>
 <cell>9</cell>
</row>
</table>
<section><name>I/O Function</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>w/o register</cell>
 <cell>w/ register</cell>
 <cell>w/ DDR register</cell>
</header>
<row>
 <cell>Input I/O</cell>
 <cell>2</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Output I/O</cell>
 <cell>3</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Bidirectional I/O</cell>
 <cell>0</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Differential Input I/O Pairs</cell>
 <cell>0</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Differential Output I/O Pairs</cell>
 <cell>0</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
</table>
<section><name>I/O Technology</name></section>
<table>
<header>
 <cell>I/O Standard</cell>
 <cell>Vcci</cell>
 <cell>Vref</cell>
 <cell>Input</cell>
 <cell>Output</cell>
 <cell>Bidirectional</cell>
</header>
<row>
 <cell>LVCMOS25</cell>
 <cell> 2.50v</cell>
 <cell> N/A</cell>
 <cell> 2</cell>
 <cell> 3</cell>
 <cell> 0</cell>
</row>
</table>
<section><name>I/O Placement</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Count</cell>
 <cell>Percentage</cell>
</header>
<row>
 <cell>Locked</cell>
 <cell> 5</cell>
 <cell>100.00%</cell>
</row>
<row>
 <cell>Placed</cell>
 <cell> 0</cell>
 <cell>0.00%</cell>
</row>
<row>
 <cell>UnPlaced</cell>
 <cell> 0</cell>
 <cell>0.00%</cell>
</row>
</table>
<section><name>Nets assigned to chip global resources</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>423</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0/FAB_CCC_GL0</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>397</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0/HPMS_READY_i_0_i</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int_RNICDJF_0/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>288</cell>
 <cell>INT_NET</cell>
 <cell>Net   : Receiver_0/AND3_0_Y</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Receiver_0/AND3_0_RNI7UKC/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>288</cell>
 <cell>INT_NET</cell>
 <cell>Net   : SERDES_IF_0_EPCS_1_RX_CLK</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>106</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0_INIT_APB_S_PCLK</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>106</cell>
 <cell>INT_NET</cell>
 <cell>Net   : FCCC_0_GL0</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: FCCC_0/GL0_INST/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>49</cell>
 <cell>INT_NET</cell>
 <cell>Net   : SERDES_IF_0_EPCS_1_TX_CLK</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: SERDES_IF_0/EPCS_1_TX_CLK_inferred_clock_RNI9VS5/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>1</cell>
 <cell>INT_NET</cell>
 <cell>Net   : FCCC_0_GL1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: FCCC_0/GL1_INST/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
</table>
<section><name>Nets assigned to row global resources</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>108</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0_INIT_APB_S_PRESET_N</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST_RNI0L5/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>106</cell>
 <cell>INT_NET</cell>
 <cell>Net   : FCCC_0_LOCK</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: FCCC_0/CCC_INST_RNIIJ03/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>49</cell>
 <cell>INT_NET</cell>
 <cell>Net   : Transmitter_0/EPCS_TX_RESET_net_0</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Transmitter_0/AND2_0_RNIEO99/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>17</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc_0</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc_RNIH0E4/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>14</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_clk_base_0</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_clk_base_RNIBNH7/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
</table>
<section><name>High fanout nets</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>47</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0/CORECONFIGP_0/state_423_d</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/CORECONFIGP_0/state_s0_0_a2_0_a2</cell>
</row>
<row>
 <cell>42</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterRegAddrSel</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel</cell>
</row>
<row>
 <cell>40</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0/CORECONFIGP_0/state[1]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/CORECONFIGP_0/state[1]</cell>
</row>
<row>
 <cell>37</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/N_152</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2[0]</cell>
</row>
<row>
 <cell>36</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0_SDIF0_INIT_APB_PSELx</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/CORECONFIGP_0/R_SDIF0_PSEL_1_0_a2</cell>
</row>
<row>
 <cell>36</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0/defSlaveSMNextState_i_a2_9</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2_9</cell>
</row>
<row>
 <cell>35</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0/HREADY_M_pre37_0_a2_0</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre37_0_a2_0</cell>
</row>
<row>
 <cell>34</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0/masterDataInProg[0]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg[0]</cell>
</row>
<row>
 <cell>34</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable</cell>
</row>
<row>
 <cell>34</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0/ConfigMaster_0/state[7]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/ConfigMaster_0/state[7]</cell>
</row>
</table>
<section><name>High fanout nets (through buffer trees)</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>47</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0/CORECONFIGP_0/state_423_d</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/CORECONFIGP_0/state_s0_0_a2_0_a2</cell>
</row>
<row>
 <cell>42</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterRegAddrSel</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel</cell>
</row>
<row>
 <cell>40</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0/CORECONFIGP_0/state[1]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/CORECONFIGP_0/state[1]</cell>
</row>
<row>
 <cell>37</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/N_152</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2[0]</cell>
</row>
<row>
 <cell>36</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0_SDIF0_INIT_APB_PSELx</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/CORECONFIGP_0/R_SDIF0_PSEL_1_0_a2</cell>
</row>
<row>
 <cell>36</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0/defSlaveSMNextState_i_a2_9</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2_9</cell>
</row>
<row>
 <cell>35</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0/HREADY_M_pre37_0_a2_0</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre37_0_a2_0</cell>
</row>
<row>
 <cell>34</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0/masterDataInProg[0]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg[0]</cell>
</row>
<row>
 <cell>34</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable</cell>
</row>
<row>
 <cell>34</cell>
 <cell>INT_NET</cell>
 <cell>Net   : IGLOO2_Oversampling_0/ConfigMaster_0/state[7]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: IGLOO2_Oversampling_0/ConfigMaster_0/state[7]</cell>
</row>
</table>
</doc>
