<?xml version="1.0" encoding="UTF-8" ?>
<!-- *************************************************************************************
FILE DESCRIPTION
Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
*******************************************************************************************-->
<report_table display_priority="2" name="Timing Summary">
<report_link name="Detailed report">
<data>C:\Microsemi\IGLOO2_Oversampling\synthesis\synlog\IGLOO2_Oversampling_top_fpga_mapper.srr</data>
<title>START OF TIMING REPORT</title>
</report_link>
<row>
<data tcl_name="clock_name">Clock Name</data>
<data tcl_name="req_freq">Req Freq</data>
<data tcl_name="est_freq">Est Freq</data>
<data tcl_name="slack">Slack</data>
</row>
<row>
<data>IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock</data>
<data>100.0 MHz</data>
<data>110.5 MHz</data>
<data>0.947</data>
</row>
<row>
<data>IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock</data>
<data>100.0 MHz</data>
<data>408.6 MHz</data>
<data>7.553</data>
</row>
<row>
<data>IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock</data>
<data>100.0 MHz</data>
<data>120.8 MHz</data>
<data>0.862</data>
</row>
<row>
<data>IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock</data>
<data>100.0 MHz</data>
<data>219.4 MHz</data>
<data>5.443</data>
</row>
<row>
<data>IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock</data>
<data>100.0 MHz</data>
<data>148.4 MHz</data>
<data>3.262</data>
</row>
<row>
<data>IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock</data>
<data>100.0 MHz</data>
<data>400.7 MHz</data>
<data>7.504</data>
</row>
<row>
<data>System</data>
<data>100.0 MHz</data>
<data>NA</data>
<data>NA</data>
</row>
</report_table>
