<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<title>Timing Report Min Delay Analysis
</title>
<text>SmartTime Version 11.3.0.112</text>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.3 (Version 11.3.0.112)</text>
<text>Date: Fri Apr 18 10:01:21 2014
</text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>IGLOO2_Oversampling_top</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>IGLOO2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2GL010T</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Temperature</cell>
 <cell>COM</cell>
</row>
<row>
 <cell>Voltage</cell>
 <cell>COM</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Design State</cell>
 <cell>Post-Layout</cell>
</row>
<row>
 <cell>Data source</cell>
 <cell>Preliminary</cell>
</row>
<row>
 <cell>Min Operating Condition</cell>
 <cell>BEST</cell>
</row>
<row>
 <cell>Max Operating Condition</cell>
 <cell>WORST</cell>
</row>
<row>
 <cell>Scenario for Timing Analysis</cell>
 <cell>Primary</cell>
</row>
</table>
<text></text>
<section>
<name>Summary</name>
<table>
<header>
 <cell>Clock Domain</cell>
 <cell>Period (ns)</cell>
 <cell>Frequency (MHz)</cell>
 <cell>Required Period (ns)</cell>
 <cell>Required Frequency (MHz)</cell>
 <cell>External Setup (ns)</cell>
 <cell>External Hold (ns)</cell>
 <cell>Min Clock-To-Out (ns)</cell>
 <cell>Max Clock-To-Out (ns)</cell>
</header>
<row>
 <cell>CLK0</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>3.491</cell>
 <cell>286.451</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>2.944</cell>
 <cell>-1.460</cell>
 <cell>3.878</cell>
 <cell>6.498</cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL1</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>FCCC_GL0</cell>
 <cell>7.818</cell>
 <cell>127.910</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>2.778</cell>
 <cell>359.971</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB</cell>
 <cell>8.010</cell>
 <cell>124.844</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>5.379</cell>
 <cell>185.908</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>FCCC_GL1</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>8.482</cell>
 <cell>117.897</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>EPCS_TX_CLK</cell>
 <cell>0.796</cell>
 <cell>1256.281</cell>
 <cell>8.482</cell>
 <cell>117.897</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>EPCS_RX_CLK</cell>
 <cell>1.564</cell>
 <cell>639.386</cell>
 <cell>8.482</cell>
 <cell>117.897</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
<text></text>
<table>
<header>
 <cell></cell>
 <cell>Min Delay (ns)</cell>
 <cell>Max Delay (ns)</cell>
</header>
<row>
 <cell>Input to Output</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
</section>
<section>
<name>Clock Domain CLK0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain FCCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>UART_INTERFACE_0/COREUART_0/make_RX/receive_full_int:CLK</cell>
 <cell>UART_INTERFACE_0/COREUART_0/genblk1.RXRDY:D</cell>
 <cell>0.321</cell>
 <cell></cell>
 <cell>1.226</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>UART_INTERFACE_0/COREUART_0/make_RX/samples[2]:CLK</cell>
 <cell>UART_INTERFACE_0/COREUART_0/make_RX/samples[1]:D</cell>
 <cell>0.323</cell>
 <cell></cell>
 <cell>1.243</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>UART_INTERFACE_0/FabUART_0/state[8]:CLK</cell>
 <cell>UART_INTERFACE_0/FabUART_0/state[8]:D</cell>
 <cell>0.347</cell>
 <cell></cell>
 <cell>1.273</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>UART_INTERFACE_0/FabUART_0/state[4]:CLK</cell>
 <cell>UART_INTERFACE_0/FabUART_0/state[5]:D</cell>
 <cell>0.357</cell>
 <cell></cell>
 <cell>1.275</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>UART_INTERFACE_0/FabUART_0/state[13]:CLK</cell>
 <cell>UART_INTERFACE_0/FabUART_0/state[13]:D</cell>
 <cell>0.352</cell>
 <cell></cell>
 <cell>1.278</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: UART_INTERFACE_0/COREUART_0/make_RX/receive_full_int:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: UART_INTERFACE_0/COREUART_0/genblk1.RXRDY:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.226</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.168</cell>
 <cell>0.168</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.103</cell>
 <cell>0.271</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB3:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.192</cell>
 <cell>0.463</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB3:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>0.619</cell>
 <cell>16</cell>
 <cell>r</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/make_RX/receive_full_int:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB3_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.286</cell>
 <cell>0.905</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/make_RX/receive_full_int:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.067</cell>
 <cell>0.972</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/genblk1.RXRDY:D</cell>
 <cell>net</cell>
 <cell>UART_INTERFACE_0/COREUART_0/receive_full</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.254</cell>
 <cell>1.226</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.226</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.168</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.103</cell>
 <cell>N/C</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB3:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.192</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB3:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>N/C</cell>
 <cell>16</cell>
 <cell>r</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/genblk1.RXRDY:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB3_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.325</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/genblk1.RXRDY:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
 <cell>External Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>RX</cell>
 <cell>UART_INTERFACE_0/COREUART_0/make_RX/samples[2]:D</cell>
 <cell>2.482</cell>
 <cell></cell>
 <cell>2.482</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>-1.460</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: RX</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: UART_INTERFACE_0/COREUART_0/make_RX/samples[2]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.482</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>RX</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>RX_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>RX</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>RX_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.539</cell>
 <cell>1.539</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>RX_ibuf/U0/U_IOINFF:A</cell>
 <cell>net</cell>
 <cell>RX_ibuf/U0/YIN1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>1.539</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>RX_ibuf/U0/U_IOINFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOINFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.056</cell>
 <cell>1.595</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/make_RX/samples[2]:D</cell>
 <cell>net</cell>
 <cell>RX_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.887</cell>
 <cell>2.482</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.482</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.187</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.114</cell>
 <cell>N/C</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB3:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.213</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB3:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.173</cell>
 <cell>N/C</cell>
 <cell>16</cell>
 <cell>r</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/make_RX/samples[2]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB3_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.335</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/make_RX/samples[2]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>UART_INTERFACE_0/FabUART_0/connect_t:CLK</cell>
 <cell>connect_o</cell>
 <cell>2.968</cell>
 <cell></cell>
 <cell>3.878</cell>
 <cell></cell>
 <cell>3.878</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>UART_INTERFACE_0/COREUART_0/make_TX/tx:CLK</cell>
 <cell>TX</cell>
 <cell>2.978</cell>
 <cell></cell>
 <cell>3.906</cell>
 <cell></cell>
 <cell>3.906</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>UART_INTERFACE_0/FabUART_0/start_t:CLK</cell>
 <cell>start</cell>
 <cell>3.045</cell>
 <cell></cell>
 <cell>3.958</cell>
 <cell></cell>
 <cell>3.958</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: UART_INTERFACE_0/FabUART_0/connect_t:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: connect_o</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.878</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.168</cell>
 <cell>0.168</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.103</cell>
 <cell>0.271</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>0.462</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB1:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>0.618</cell>
 <cell>14</cell>
 <cell>r</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/FabUART_0/connect_t:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB1_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.292</cell>
 <cell>0.910</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/FabUART_0/connect_t:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.067</cell>
 <cell>0.977</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>connect_o_obuf/U0/U_IOOUTFF:A</cell>
 <cell>net</cell>
 <cell>connect_o_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.140</cell>
 <cell>2.117</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>connect_o_obuf/U0/U_IOOUTFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOOUTFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>2.329</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>connect_o_obuf/U0/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>connect_o_obuf/U0/DOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.329</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>connect_o_obuf/U0/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>1.549</cell>
 <cell>3.878</cell>
 <cell>0</cell>
 <cell>f</cell>
</row>
<row>
 <cell>connect_o</cell>
 <cell>net</cell>
 <cell>connect_o</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.878</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.878</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>connect_o</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain FCCC_0/CCC_INST/INST_CCC_IP:GL1</name>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain FCCC_GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/CLR_INIT_DONE_q1:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/CLR_INIT_DONE_clk_base:D</cell>
 <cell>0.285</cell>
 <cell>0.252</cell>
 <cell>1.201</cell>
 <cell>0.949</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sdif0_areset_n_q1:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_clk_base:D</cell>
 <cell>0.284</cell>
 <cell>0.257</cell>
 <cell>1.200</cell>
 <cell>0.943</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core_q1:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core_clk_base:D</cell>
 <cell>0.305</cell>
 <cell>0.264</cell>
 <cell>1.222</cell>
 <cell>0.958</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sdif0_spll_lock_q1:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sdif0_spll_lock_q2:D</cell>
 <cell>0.306</cell>
 <cell>0.265</cell>
 <cell>1.223</cell>
 <cell>0.958</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/RESET_N_M2F_q1:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/RESET_N_M2F_clk_base:D</cell>
 <cell>0.305</cell>
 <cell>0.266</cell>
 <cell>1.210</cell>
 <cell>0.944</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: IGLOO2_Oversampling_0/CORERESETP_0/CLR_INIT_DONE_q1:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: IGLOO2_Oversampling_0/CORERESETP_0/CLR_INIT_DONE_clk_base:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.201</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>0.949</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.252</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.168</cell>
 <cell>0.168</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.103</cell>
 <cell>0.271</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB6:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>0.461</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB6:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>0.617</cell>
 <cell>36</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/CLR_INIT_DONE_q1:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB6_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.299</cell>
 <cell>0.916</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/CLR_INIT_DONE_q1:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.067</cell>
 <cell>0.983</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/CLR_INIT_DONE_clk_base:D</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/CLR_INIT_DONE_q1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.218</cell>
 <cell>1.201</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.201</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.168</cell>
 <cell>0.168</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.103</cell>
 <cell>0.271</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB6:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>0.461</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB6:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>0.617</cell>
 <cell>36</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/CLR_INIT_DONE_clk_base:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB6_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.332</cell>
 <cell>0.949</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/CLR_INIT_DONE_clk_base:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.949</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.949</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int:ALn</cell>
 <cell>0.769</cell>
 <cell>0.737</cell>
 <cell>1.681</cell>
 <cell>0.944</cell>
 <cell>0.000</cell>
 <cell>-0.032</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/mss_reset_select:ALn</cell>
 <cell>0.769</cell>
 <cell>0.743</cell>
 <cell>1.681</cell>
 <cell>0.938</cell>
 <cell>0.000</cell>
 <cell>-0.026</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/mss_reset_state:ALn</cell>
 <cell>0.769</cell>
 <cell>0.744</cell>
 <cell>1.681</cell>
 <cell>0.937</cell>
 <cell>0.000</cell>
 <cell>-0.025</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sdif0_areset_n_q1:ALn</cell>
 <cell>1.017</cell>
 <cell>0.979</cell>
 <cell>1.928</cell>
 <cell>0.949</cell>
 <cell>0.000</cell>
 <cell>-0.038</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_clk_base:ALn</cell>
 <cell>1.017</cell>
 <cell>0.985</cell>
 <cell>1.928</cell>
 <cell>0.943</cell>
 <cell>0.000</cell>
 <cell>-0.032</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: IGLOO2_Oversampling_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.681</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>0.944</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.737</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.168</cell>
 <cell>0.168</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.103</cell>
 <cell>0.271</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB4:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.186</cell>
 <cell>0.457</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB4:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>0.613</cell>
 <cell>75</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB4_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.299</cell>
 <cell>0.912</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.054</cell>
 <cell>0.966</cell>
 <cell>3</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int:ALn</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/POWER_ON_RESET_N_clk_base</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.715</cell>
 <cell>1.681</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.681</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.168</cell>
 <cell>0.168</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.103</cell>
 <cell>0.271</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB5:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.187</cell>
 <cell>0.458</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB5:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>0.614</cell>
 <cell>61</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB5_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.330</cell>
 <cell>0.944</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.944</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.944</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT to FCCC_GL0</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/ddr_ready:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/ddr_ready_q1:D</cell>
 <cell>0.384</cell>
 <cell>0.930</cell>
 <cell>1.888</cell>
 <cell>0.958</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core_q1:D</cell>
 <cell>0.479</cell>
 <cell>1.408</cell>
 <cell>2.358</cell>
 <cell>0.950</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: IGLOO2_Oversampling_0/CORERESETP_0/ddr_ready:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: IGLOO2_Oversampling_0/CORERESETP_0/ddr_ready_q1:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.888</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>0.958</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.930</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.095</cell>
 <cell>0.095</cell>
 <cell>19</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/ddr_ready:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0_RCOSC_25_50MHZ_O2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.409</cell>
 <cell>1.504</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/ddr_ready:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.067</cell>
 <cell>1.571</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/ddr_ready_q1:D</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/ddr_ready</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.317</cell>
 <cell>1.888</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.888</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.168</cell>
 <cell>0.168</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.103</cell>
 <cell>0.271</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB7:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>0.461</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB7:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>0.617</cell>
 <cell>22</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/ddr_ready_q1:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB7_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.341</cell>
 <cell>0.958</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/ddr_ready_q1:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.958</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.958</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Clock Domain IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sdif0_areset_n_rcosc_q1:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:D</cell>
 <cell>0.304</cell>
 <cell>0.155</cell>
 <cell>1.807</cell>
 <cell>1.652</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_enable_rcosc:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[5]:EN</cell>
 <cell>0.753</cell>
 <cell>0.179</cell>
 <cell>2.256</cell>
 <cell>2.077</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_enable_rcosc:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[1]:EN</cell>
 <cell>0.753</cell>
 <cell>0.179</cell>
 <cell>2.256</cell>
 <cell>2.077</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_enable_rcosc:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[3]:EN</cell>
 <cell>0.753</cell>
 <cell>0.180</cell>
 <cell>2.256</cell>
 <cell>2.076</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_enable_rcosc:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[4]:EN</cell>
 <cell>0.753</cell>
 <cell>0.187</cell>
 <cell>2.256</cell>
 <cell>2.069</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: IGLOO2_Oversampling_0/CORERESETP_0/sdif0_areset_n_rcosc_q1:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.807</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>1.652</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.155</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.095</cell>
 <cell>0.095</cell>
 <cell>19</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sdif0_areset_n_rcosc_q1:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0_RCOSC_25_50MHZ_O2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.408</cell>
 <cell>1.503</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sdif0_areset_n_rcosc_q1:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.054</cell>
 <cell>1.557</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:D</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc_q1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>1.807</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.807</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.095</cell>
 <cell>0.095</cell>
 <cell>19</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0_RCOSC_25_50MHZ_O2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.557</cell>
 <cell>1.652</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>1.652</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.652</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core:ALn</cell>
 <cell>1.168</cell>
 <cell>0.588</cell>
 <cell>2.665</cell>
 <cell>2.077</cell>
 <cell>0.000</cell>
 <cell>-0.580</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[5]:ALn</cell>
 <cell>1.168</cell>
 <cell>0.588</cell>
 <cell>2.665</cell>
 <cell>2.077</cell>
 <cell>0.000</cell>
 <cell>-0.580</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[1]:ALn</cell>
 <cell>1.168</cell>
 <cell>0.588</cell>
 <cell>2.665</cell>
 <cell>2.077</cell>
 <cell>0.000</cell>
 <cell>-0.580</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[3]:ALn</cell>
 <cell>1.168</cell>
 <cell>0.589</cell>
 <cell>2.665</cell>
 <cell>2.076</cell>
 <cell>0.000</cell>
 <cell>-0.579</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[4]:ALn</cell>
 <cell>1.168</cell>
 <cell>0.596</cell>
 <cell>2.665</cell>
 <cell>2.069</cell>
 <cell>0.000</cell>
 <cell>-0.572</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.665</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>2.077</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.588</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.095</cell>
 <cell>0.095</cell>
 <cell>19</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0_RCOSC_25_50MHZ_O2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.402</cell>
 <cell>1.497</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.054</cell>
 <cell>1.551</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc_RNIH0E4/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.651</cell>
 <cell>2.202</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc_RNIH0E4/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>2.358</cell>
 <cell>17</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core:ALn</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc_0_RRight</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.307</cell>
 <cell>2.665</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.665</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.095</cell>
 <cell>0.095</cell>
 <cell>19</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0_RCOSC_25_50MHZ_O2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.982</cell>
 <cell>2.077</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.077</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.077</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_GL0 to IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_enable:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_enable_q1:D</cell>
 <cell>0.383</cell>
 <cell>-0.352</cell>
 <cell>1.300</cell>
 <cell>1.652</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sdif0_areset_n_rcosc_q1:ALn</cell>
 <cell>1.045</cell>
 <cell>0.297</cell>
 <cell>1.956</cell>
 <cell>1.659</cell>
 <cell></cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:ALn</cell>
 <cell>1.045</cell>
 <cell>0.304</cell>
 <cell>1.956</cell>
 <cell>1.652</cell>
 <cell></cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_enable:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_enable_q1:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.300</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>1.652</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-0.352</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.168</cell>
 <cell>0.168</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.103</cell>
 <cell>0.271</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB7:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>0.461</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB7:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>0.617</cell>
 <cell>22</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_enable:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB7_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.300</cell>
 <cell>0.917</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_enable:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.067</cell>
 <cell>0.984</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_enable_q1:D</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_enable</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>1.300</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.300</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.095</cell>
 <cell>0.095</cell>
 <cell>19</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_enable_q1:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0_RCOSC_25_50MHZ_O2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.557</cell>
 <cell>1.652</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_enable_q1:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>1.652</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.652</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Clock Domain IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/INIT_DONE_q2:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/INIT_DONE_q3:D</cell>
 <cell>0.332</cell>
 <cell></cell>
 <cell>1.994</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/state[1]:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/state[1]:D</cell>
 <cell>0.353</cell>
 <cell></cell>
 <cell>2.014</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:D</cell>
 <cell>0.360</cell>
 <cell></cell>
 <cell>2.021</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg[14]:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg[14]:D</cell>
 <cell>0.386</cell>
 <cell></cell>
 <cell>2.058</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg[5]:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/soft_reset_reg[5]:D</cell>
 <cell>0.387</cell>
 <cell></cell>
 <cell>2.059</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: IGLOO2_Oversampling_0/CORECONFIGP_0/INIT_DONE_q2:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: IGLOO2_Oversampling_0/CORECONFIGP_0/INIT_DONE_q3:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.994</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.895</cell>
 <cell>0.895</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.136</cell>
 <cell>1.031</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.177</cell>
 <cell>1.208</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>1.364</cell>
 <cell>25</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/INIT_DONE_q2:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.298</cell>
 <cell>1.662</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/INIT_DONE_q2:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.067</cell>
 <cell>1.729</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/INIT_DONE_q3:D</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/INIT_DONE_q2</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.265</cell>
 <cell>1.994</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.994</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.895</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.136</cell>
 <cell>N/C</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.177</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>N/C</cell>
 <cell>25</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/INIT_DONE_q3:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.325</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/INIT_DONE_q3:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/rx_data_debug[9]:D</cell>
 <cell>0.556</cell>
 <cell></cell>
 <cell>0.556</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/rx_data_debug[8]:D</cell>
 <cell>0.596</cell>
 <cell></cell>
 <cell>0.596</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/rx_data_debug[2]:D</cell>
 <cell>0.611</cell>
 <cell></cell>
 <cell>0.611</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/rx_data_debug[6]:D</cell>
 <cell>0.639</cell>
 <cell></cell>
 <cell>0.639</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/rx_data_debug[3]:D</cell>
 <cell>0.658</cell>
 <cell></cell>
 <cell>0.658</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: Receiver_0/receive_buffer_top_0/rx_data_aligner_0/rx_data_debug[9]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.556</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:S_RDATA_HRDATA[41]</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SERDESIF_IP</cell>
 <cell>+</cell>
 <cell>-0.025</cell>
 <cell>-0.025</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/rx_data_debug[9]:D</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0_EPCS_1_RX_DATA[9]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.581</cell>
 <cell>0.556</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.556</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1:An</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.451</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.136</cell>
 <cell>N/C</cell>
 <cell>6</cell>
 <cell>f</cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_RGB1_RGB3:An</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.197</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_RGB1_RGB3:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>N/C</cell>
 <cell>71</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/rx_data_debug[9]:CLK</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_RGB1_RGB3_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.330</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/rx_data_debug[9]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>Receiver_0/Downsampler_0/reg_check[5]:ALn</cell>
 <cell>2.530</cell>
 <cell></cell>
 <cell>2.530</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>-2.297</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>Receiver_0/Downsampler_0/reg_check[7]:ALn</cell>
 <cell>2.530</cell>
 <cell></cell>
 <cell>2.530</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>-2.297</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1[24]:ALn</cell>
 <cell>2.530</cell>
 <cell></cell>
 <cell>2.530</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>-2.297</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg[16]:ALn</cell>
 <cell>2.530</cell>
 <cell></cell>
 <cell>2.530</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>-2.297</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data[14]:ALn</cell>
 <cell>2.530</cell>
 <cell></cell>
 <cell>2.530</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>-2.297</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: Receiver_0/Downsampler_0/reg_check[5]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.530</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:M_ARBURST[1]</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SERDESIF_IP</cell>
 <cell>+</cell>
 <cell>0.322</cell>
 <cell>0.322</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/AND3_0:B</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0_EPCS_1_RX_RESET_N</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.455</cell>
 <cell>0.777</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/AND3_0:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.129</cell>
 <cell>0.906</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/AND3_0_RNI7UKC:An</cell>
 <cell>net</cell>
 <cell>Receiver_0/AND3_0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.819</cell>
 <cell>1.725</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Receiver_0/AND3_0_RNI7UKC:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.136</cell>
 <cell>1.861</cell>
 <cell>6</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Receiver_0/AND3_0_RNI7UKC/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>Receiver_0/AND3_0_RNI7UKC/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>2.052</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Receiver_0/AND3_0_RNI7UKC/U0_RGB1_RGB2:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>2.208</cell>
 <cell>69</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/Downsampler_0/reg_check[5]:ALn</cell>
 <cell>net</cell>
 <cell>Receiver_0/AND3_0_RNI7UKC/U0_RGB1_RGB2_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.322</cell>
 <cell>2.530</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.530</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1:An</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.451</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.136</cell>
 <cell>N/C</cell>
 <cell>6</cell>
 <cell>f</cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.197</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_RGB1_RGB2:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.156</cell>
 <cell>N/C</cell>
 <cell>69</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/Downsampler_0/reg_check[5]:CLK</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_RGB1_RGB2_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.357</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/Downsampler_0/reg_check[5]:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain FCCC_GL1</name>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain EPCS_TX_CLK</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>Transmitter_0/FIFO_PRBS_0/Error_Inject_i_delay1:CLK</cell>
 <cell>Transmitter_0/FIFO_PRBS_0/Error_Inject_i_delay2:D</cell>
 <cell>0.306</cell>
 <cell>0.274</cell>
 <cell>0.604</cell>
 <cell>0.330</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: Transmitter_0/FIFO_PRBS_0/Error_Inject_i_delay1:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: Transmitter_0/FIFO_PRBS_0/Error_Inject_i_delay2:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.604</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>0.330</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.274</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EPCS_TX_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_TX_CLK_inferred_clock_RNI9VS5/U0_RGB1:YL</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Transmitter_0/FIFO_PRBS_0/Error_Inject_i_delay1:CLK</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0_EPCS_1_TX_CLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.298</cell>
 <cell>0.298</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Transmitter_0/FIFO_PRBS_0/Error_Inject_i_delay1:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.067</cell>
 <cell>0.365</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Transmitter_0/FIFO_PRBS_0/Error_Inject_i_delay2:D</cell>
 <cell>net</cell>
 <cell>Transmitter_0/FIFO_PRBS_0/Error_Inject_i_delay1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.239</cell>
 <cell>0.604</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.604</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EPCS_TX_CLK</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_TX_CLK_inferred_clock_RNI9VS5/U0_RGB1:YL</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Transmitter_0/FIFO_PRBS_0/Error_Inject_i_delay2:CLK</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0_EPCS_1_TX_CLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.330</cell>
 <cell>0.330</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Transmitter_0/FIFO_PRBS_0/Error_Inject_i_delay2:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.330</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.330</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain EPCS_RX_CLK</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data[5]:CLK</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1[2]:D</cell>
 <cell>0.314</cell>
 <cell>0.273</cell>
 <cell>0.621</cell>
 <cell>0.348</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data[8]:CLK</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2[2]:D</cell>
 <cell>0.302</cell>
 <cell>0.275</cell>
 <cell>0.614</cell>
 <cell>0.339</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data[5]:CLK</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D0[5]:D</cell>
 <cell>0.314</cell>
 <cell>0.280</cell>
 <cell>0.621</cell>
 <cell>0.341</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data[3]:CLK</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D0[3]:D</cell>
 <cell>0.309</cell>
 <cell>0.281</cell>
 <cell>0.619</cell>
 <cell>0.338</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data[3]:CLK</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1[0]:D</cell>
 <cell>0.309</cell>
 <cell>0.281</cell>
 <cell>0.619</cell>
 <cell>0.338</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data[5]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1[2]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.621</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>0.348</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.273</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EPCS_RX_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_RGB1:YL</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data[5]:CLK</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0_EPCS_1_RX_CLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.307</cell>
 <cell>0.307</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data[5]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.067</cell>
 <cell>0.374</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1[2]:D</cell>
 <cell>net</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/buf_data[5]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.247</cell>
 <cell>0.621</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.621</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EPCS_RX_CLK</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_RGB1:YL</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1[2]:CLK</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0_EPCS_1_RX_CLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.348</cell>
 <cell>0.348</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D1[2]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.348</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.348</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set Pin to Pin</name>
<section>
<name>SET Input to Output</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set User Sets</name>
</section>
</doc>
