<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<title>Timing Report Max Delay Analysis
</title>
<text>SmartTime Version 11.3.0.112</text>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.3 (Version 11.3.0.112)</text>
<text>Date: Fri Apr 18 10:01:19 2014
</text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>IGLOO2_Oversampling_top</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>IGLOO2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2GL010T</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Temperature</cell>
 <cell>COM</cell>
</row>
<row>
 <cell>Voltage</cell>
 <cell>COM</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Design State</cell>
 <cell>Post-Layout</cell>
</row>
<row>
 <cell>Data source</cell>
 <cell>Preliminary</cell>
</row>
<row>
 <cell>Min Operating Condition</cell>
 <cell>BEST</cell>
</row>
<row>
 <cell>Max Operating Condition</cell>
 <cell>WORST</cell>
</row>
<row>
 <cell>Scenario for Timing Analysis</cell>
 <cell>Primary</cell>
</row>
</table>
<text></text>
<section>
<name>Summary</name>
<table>
<header>
 <cell>Clock Domain</cell>
 <cell>Period (ns)</cell>
 <cell>Frequency (MHz)</cell>
 <cell>Required Period (ns)</cell>
 <cell>Required Frequency (MHz)</cell>
 <cell>External Setup (ns)</cell>
 <cell>External Hold (ns)</cell>
 <cell>Min Clock-To-Out (ns)</cell>
 <cell>Max Clock-To-Out (ns)</cell>
</header>
<row>
 <cell>CLK0</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>3.491</cell>
 <cell>286.451</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>2.944</cell>
 <cell>-1.460</cell>
 <cell>3.878</cell>
 <cell>6.498</cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL1</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>FCCC_GL0</cell>
 <cell>7.818</cell>
 <cell>127.910</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>2.778</cell>
 <cell>359.971</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB</cell>
 <cell>8.010</cell>
 <cell>124.844</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>5.379</cell>
 <cell>185.908</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>FCCC_GL1</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>8.482</cell>
 <cell>117.897</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>EPCS_TX_CLK</cell>
 <cell>0.796</cell>
 <cell>1256.281</cell>
 <cell>8.482</cell>
 <cell>117.897</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>EPCS_RX_CLK</cell>
 <cell>1.564</cell>
 <cell>639.386</cell>
 <cell>8.482</cell>
 <cell>117.897</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
<text></text>
<table>
<header>
 <cell></cell>
 <cell>Min Delay (ns)</cell>
 <cell>Max Delay (ns)</cell>
</header>
<row>
 <cell>Input to Output</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
</section>
<section>
<name>Clock Domain CLK0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain FCCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr[9]:CLK</cell>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr[10]:D</cell>
 <cell>3.200</cell>
 <cell></cell>
 <cell>4.662</cell>
 <cell></cell>
 <cell>0.254</cell>
 <cell>3.491</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr[9]:CLK</cell>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr[9]:D</cell>
 <cell>3.142</cell>
 <cell></cell>
 <cell>4.604</cell>
 <cell></cell>
 <cell>0.254</cell>
 <cell>3.443</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr[9]:CLK</cell>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr[12]:D</cell>
 <cell>3.147</cell>
 <cell></cell>
 <cell>4.609</cell>
 <cell></cell>
 <cell>0.254</cell>
 <cell>3.438</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>UART_INTERFACE_0/FabUART_0/state[12]:CLK</cell>
 <cell>UART_INTERFACE_0/FabUART_0/uart_data_out_t[5]:EN</cell>
 <cell>2.998</cell>
 <cell></cell>
 <cell>4.482</cell>
 <cell></cell>
 <cell>0.339</cell>
 <cell>3.390</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>UART_INTERFACE_0/FabUART_0/state[12]:CLK</cell>
 <cell>UART_INTERFACE_0/FabUART_0/uart_data_out_t[0]:EN</cell>
 <cell>2.998</cell>
 <cell></cell>
 <cell>4.482</cell>
 <cell></cell>
 <cell>0.339</cell>
 <cell>3.390</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr[9]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr[10]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>4.662</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.271</cell>
 <cell>0.271</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.166</cell>
 <cell>0.437</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.309</cell>
 <cell>0.746</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>0.996</cell>
 <cell>14</cell>
 <cell>r</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr[9]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.466</cell>
 <cell>1.462</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr[9]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.108</cell>
 <cell>1.570</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.make_baud_cntr.baud_cntr8_7:C</cell>
 <cell>net</cell>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/baud_cntr[9]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.409</cell>
 <cell>1.979</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.make_baud_cntr.baud_cntr8_7:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.395</cell>
 <cell>2.374</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.make_baud_cntr.baud_cntr8:A</cell>
 <cell>net</cell>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/baud_cntr8_7</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.478</cell>
 <cell>2.852</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.make_baud_cntr.baud_cntr8:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.208</cell>
 <cell>3.060</cell>
 <cell>12</cell>
 <cell>r</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr_RNIEAUI6[6]:B</cell>
 <cell>net</cell>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/baud_cntr</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.506</cell>
 <cell>3.566</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr_RNIEAUI6[6]:P</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:ARI1_CC</cell>
 <cell>+</cell>
 <cell>0.177</cell>
 <cell>3.743</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1_make_baud_cntr_baud_cntr8_1_RNI29NL1_CC_1:P[1]</cell>
 <cell>net</cell>
 <cell>NET_CC_CONFIG22</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.743</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1_make_baud_cntr_baud_cntr8_1_RNI29NL1_CC_1:CC[5]</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CC_CONFIG</cell>
 <cell>+</cell>
 <cell>0.786</cell>
 <cell>4.529</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr_RNI3KTL8[10]:CC</cell>
 <cell>net</cell>
 <cell>NET_CC_CONFIG36</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>4.529</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr_RNI3KTL8[10]:S</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:ARI1_CC</cell>
 <cell>+</cell>
 <cell>0.056</cell>
 <cell>4.585</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr[10]:D</cell>
 <cell>net</cell>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/baud_cntr_s[10]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.077</cell>
 <cell>4.662</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.662</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.271</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.166</cell>
 <cell>N/C</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.309</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>N/C</cell>
 <cell>14</cell>
 <cell>r</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr[10]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.429</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/make_CLOCK_GEN/genblk1.baud_cntr[10]:D</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.254</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>External Setup (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>RX</cell>
 <cell>UART_INTERFACE_0/COREUART_0/make_RX/samples[2]:D</cell>
 <cell>4.023</cell>
 <cell></cell>
 <cell>4.023</cell>
 <cell></cell>
 <cell>0.254</cell>
 <cell>2.944</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: RX</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: UART_INTERFACE_0/COREUART_0/make_RX/samples[2]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>4.023</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>RX</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>RX_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>RX</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>RX_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>2.385</cell>
 <cell>2.385</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>RX_ibuf/U0/U_IOINFF:A</cell>
 <cell>net</cell>
 <cell>RX_ibuf/U0/YIN1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.385</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>RX_ibuf/U0/U_IOINFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOINFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.083</cell>
 <cell>2.468</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/make_RX/samples[2]:D</cell>
 <cell>net</cell>
 <cell>RX_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.555</cell>
 <cell>4.023</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.023</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.244</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.149</cell>
 <cell>N/C</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB3:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.279</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB3:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.225</cell>
 <cell>N/C</cell>
 <cell>16</cell>
 <cell>r</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/make_RX/samples[2]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB3_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.436</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/COREUART_0/make_RX/samples[2]:D</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.254</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>UART_INTERFACE_0/FabUART_0/start_t:CLK</cell>
 <cell>start</cell>
 <cell>5.027</cell>
 <cell></cell>
 <cell>6.498</cell>
 <cell></cell>
 <cell>6.498</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>UART_INTERFACE_0/COREUART_0/make_TX/tx:CLK</cell>
 <cell>TX</cell>
 <cell>4.916</cell>
 <cell></cell>
 <cell>6.412</cell>
 <cell></cell>
 <cell>6.412</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>UART_INTERFACE_0/FabUART_0/connect_t:CLK</cell>
 <cell>connect_o</cell>
 <cell>4.871</cell>
 <cell></cell>
 <cell>6.338</cell>
 <cell></cell>
 <cell>6.338</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: UART_INTERFACE_0/FabUART_0/start_t:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: start</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>6.498</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.271</cell>
 <cell>0.271</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.166</cell>
 <cell>0.437</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.309</cell>
 <cell>0.746</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB2:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.251</cell>
 <cell>0.997</cell>
 <cell>13</cell>
 <cell>r</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/FabUART_0/start_t:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB2_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.474</cell>
 <cell>1.471</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>UART_INTERFACE_0/FabUART_0/start_t:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>1.558</cell>
 <cell>5</cell>
 <cell>r</cell>
</row>
<row>
 <cell>start_obuf/U0/U_IOOUTFF:A</cell>
 <cell>net</cell>
 <cell>start_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.090</cell>
 <cell>3.648</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>start_obuf/U0/U_IOOUTFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOOUTFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.353</cell>
 <cell>4.001</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>start_obuf/U0/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>start_obuf/U0/DOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>4.001</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>start_obuf/U0/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>2.497</cell>
 <cell>6.498</cell>
 <cell>0</cell>
 <cell>r</cell>
</row>
<row>
 <cell>start</cell>
 <cell>net</cell>
 <cell>start</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>6.498</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.498</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>start</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain FCCC_0/CCC_INST/INST_CCC_IP:GL1</name>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain FCCC_GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/HADDR[1]:EN</cell>
 <cell>7.235</cell>
 <cell>12.182</cell>
 <cell>8.899</cell>
 <cell>21.081</cell>
 <cell>0.335</cell>
 <cell>7.818</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/HADDR[22]:EN</cell>
 <cell>7.235</cell>
 <cell>12.182</cell>
 <cell>8.899</cell>
 <cell>21.081</cell>
 <cell>0.335</cell>
 <cell>7.818</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/HADDR[28]:EN</cell>
 <cell>7.235</cell>
 <cell>12.189</cell>
 <cell>8.899</cell>
 <cell>21.088</cell>
 <cell>0.335</cell>
 <cell>7.811</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/mask[15]:CLK</cell>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/HADDR[1]:EN</cell>
 <cell>7.107</cell>
 <cell>12.511</cell>
 <cell>8.570</cell>
 <cell>21.081</cell>
 <cell>0.335</cell>
 <cell>7.489</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/mask[15]:CLK</cell>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/HADDR[22]:EN</cell>
 <cell>7.107</cell>
 <cell>12.511</cell>
 <cell>8.570</cell>
 <cell>21.081</cell>
 <cell>0.335</cell>
 <cell>7.489</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: IGLOO2_Oversampling_0/ConfigMaster_0/HADDR[1]:EN</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>21.081</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>8.899</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>12.182</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.271</cell>
 <cell>0.271</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.165</cell>
 <cell>0.436</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.310</cell>
 <cell>0.746</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>0.996</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.396</cell>
 <cell>1.392</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>1.601</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.063</cell>
 <cell>1.664</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:F_FM0_READYOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_010_IP</cell>
 <cell>+</cell>
 <cell>1.155</cell>
 <cell>2.819</cell>
 <cell>11</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNI7TTB1[0]:C</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CoreAHBLite_0_AHBmslave16_HREADY</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.980</cell>
 <cell>3.799</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg_RNI7TTB1[0]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.152</cell>
 <cell>3.951</cell>
 <cell>12</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_iv:A</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/d_bytecount_3_sqmuxa_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.028</cell>
 <cell>4.979</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_iv:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.163</cell>
 <cell>5.142</cell>
 <cell>32</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/un1_state_32_12:B</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/HREADY_i_3</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.258</cell>
 <cell>5.400</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/un1_state_32_12:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.208</cell>
 <cell>5.608</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_sqmuxa_4_RNI8TH41:D</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/un1_state_32_12</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.667</cell>
 <cell>6.275</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/d_HADDR_0_sqmuxa_4_RNI8TH41:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.225</cell>
 <cell>6.500</cell>
 <cell>33</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/HADDR[1]:EN</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/un1_state_32_i_0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.399</cell>
 <cell>8.899</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>8.899</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>20.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.271</cell>
 <cell>20.271</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.165</cell>
 <cell>20.436</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.299</cell>
 <cell>20.735</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>20.985</cell>
 <cell>93</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/HADDR[1]:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.431</cell>
 <cell>21.416</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/HADDR[1]:EN</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.335</cell>
 <cell>21.081</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>21.081</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Recovery (ns)</cell>
 <cell>Minimum Period (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int:CLK</cell>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/ins2[5]:ALn</cell>
 <cell>2.932</cell>
 <cell>16.666</cell>
 <cell>4.400</cell>
 <cell>21.066</cell>
 <cell>0.353</cell>
 <cell>3.334</cell>
 <cell>0.049</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int:CLK</cell>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/mask[0]:ALn</cell>
 <cell>2.932</cell>
 <cell>16.666</cell>
 <cell>4.400</cell>
 <cell>21.066</cell>
 <cell>0.353</cell>
 <cell>3.334</cell>
 <cell>0.049</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int:CLK</cell>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write[5]:ALn</cell>
 <cell>2.932</cell>
 <cell>16.666</cell>
 <cell>4.400</cell>
 <cell>21.066</cell>
 <cell>0.353</cell>
 <cell>3.334</cell>
 <cell>0.049</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int:CLK</cell>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/rdata[10]:ALn</cell>
 <cell>2.932</cell>
 <cell>16.666</cell>
 <cell>4.400</cell>
 <cell>21.066</cell>
 <cell>0.353</cell>
 <cell>3.334</cell>
 <cell>0.049</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int:CLK</cell>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/haddr_write[8]:ALn</cell>
 <cell>2.923</cell>
 <cell>16.666</cell>
 <cell>4.391</cell>
 <cell>21.057</cell>
 <cell>0.353</cell>
 <cell>3.334</cell>
 <cell>0.058</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: IGLOO2_Oversampling_0/ConfigMaster_0/ins2[5]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>21.066</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>4.400</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>16.666</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.271</cell>
 <cell>0.271</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.166</cell>
 <cell>0.437</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB5:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.303</cell>
 <cell>0.740</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB5:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>0.990</cell>
 <cell>61</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB5_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.478</cell>
 <cell>1.468</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>1.555</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int_RNICDJF:B</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.321</cell>
 <cell>1.876</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int_RNICDJF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.077</cell>
 <cell>1.953</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int_RNICDJF_0:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int_RNICDJF</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.196</cell>
 <cell>3.149</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int_RNICDJF_0:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.220</cell>
 <cell>3.369</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int_RNICDJF_0/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int_RNICDJF_0/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.274</cell>
 <cell>3.643</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int_RNICDJF_0/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>3.893</cell>
 <cell>63</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/ins2[5]:ALn</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int_RNICDJF_0/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.507</cell>
 <cell>4.400</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.400</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>20.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.271</cell>
 <cell>20.271</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.165</cell>
 <cell>20.436</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.301</cell>
 <cell>20.737</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>20.987</cell>
 <cell>63</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/ins2[5]:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.432</cell>
 <cell>21.419</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/ConfigMaster_0/ins2[5]:ALn</cell>
 <cell>Library recovery time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.353</cell>
 <cell>21.066</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>21.066</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT to FCCC_GL0</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core_q1:D</cell>
 <cell>0.798</cell>
 <cell>17.357</cell>
 <cell>3.818</cell>
 <cell>21.175</cell>
 <cell>0.254</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/ddr_ready:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/ddr_ready_q1:D</cell>
 <cell>0.621</cell>
 <cell>18.147</cell>
 <cell>3.038</cell>
 <cell>21.185</cell>
 <cell>0.254</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core_q1:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>21.175</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.818</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>17.357</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.152</cell>
 <cell>0.152</cell>
 <cell>19</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0_RCOSC_25_50MHZ_O2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.868</cell>
 <cell>3.020</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>3.107</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core_q1:D</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.711</cell>
 <cell>3.818</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.818</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>20.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.271</cell>
 <cell>20.271</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.166</cell>
 <cell>20.437</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB7:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.308</cell>
 <cell>20.745</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB7:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>20.995</cell>
 <cell>22</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core_q1:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB7_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.434</cell>
 <cell>21.429</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core_q1:D</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.254</cell>
 <cell>21.175</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>21.175</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Clock Domain IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[3]:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core:EN</cell>
 <cell>2.157</cell>
 <cell>17.222</cell>
 <cell>5.176</cell>
 <cell>22.398</cell>
 <cell>0.335</cell>
 <cell>2.778</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[1]:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[11]:D</cell>
 <cell>1.539</cell>
 <cell>17.378</cell>
 <cell>4.559</cell>
 <cell>21.937</cell>
 <cell>0.254</cell>
 <cell>2.622</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[0]:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[11]:D</cell>
 <cell>1.537</cell>
 <cell>17.391</cell>
 <cell>4.546</cell>
 <cell>21.937</cell>
 <cell>0.254</cell>
 <cell>2.609</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[3]:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[11]:D</cell>
 <cell>1.519</cell>
 <cell>17.399</cell>
 <cell>4.538</cell>
 <cell>21.937</cell>
 <cell>0.254</cell>
 <cell>2.601</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[1]:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[10]:D</cell>
 <cell>1.494</cell>
 <cell>17.413</cell>
 <cell>4.514</cell>
 <cell>21.927</cell>
 <cell>0.254</cell>
 <cell>2.587</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[3]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core:EN</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>22.398</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.176</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>17.222</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.152</cell>
 <cell>0.152</cell>
 <cell>19</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[3]:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0_RCOSC_25_50MHZ_O2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.867</cell>
 <cell>3.019</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[3]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>3.106</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core4_8:B</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[3]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.458</cell>
 <cell>3.564</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core4_8:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.416</cell>
 <cell>3.980</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core4:D</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core4_8</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.303</cell>
 <cell>4.283</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core4:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.371</cell>
 <cell>4.654</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core:EN</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core4</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.522</cell>
 <cell>5.176</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.176</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>20.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.152</cell>
 <cell>20.152</cell>
 <cell>19</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0_RCOSC_25_50MHZ_O2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.581</cell>
 <cell>22.733</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/release_sdif0_core:EN</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.335</cell>
 <cell>22.398</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>22.398</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Recovery (ns)</cell>
 <cell>Minimum Period (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[8]:ALn</cell>
 <cell>1.887</cell>
 <cell>17.535</cell>
 <cell>4.293</cell>
 <cell>21.828</cell>
 <cell>0.353</cell>
 <cell>2.465</cell>
 <cell>0.225</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[10]:ALn</cell>
 <cell>1.887</cell>
 <cell>17.535</cell>
 <cell>4.293</cell>
 <cell>21.828</cell>
 <cell>0.353</cell>
 <cell>2.465</cell>
 <cell>0.225</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_enable_q1:ALn</cell>
 <cell>1.887</cell>
 <cell>17.535</cell>
 <cell>4.293</cell>
 <cell>21.828</cell>
 <cell>0.353</cell>
 <cell>2.465</cell>
 <cell>0.225</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[12]:ALn</cell>
 <cell>1.887</cell>
 <cell>17.535</cell>
 <cell>4.293</cell>
 <cell>21.828</cell>
 <cell>0.353</cell>
 <cell>2.465</cell>
 <cell>0.225</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[6]:ALn</cell>
 <cell>1.887</cell>
 <cell>17.535</cell>
 <cell>4.293</cell>
 <cell>21.828</cell>
 <cell>0.353</cell>
 <cell>2.465</cell>
 <cell>0.225</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[8]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>21.828</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>4.293</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>17.535</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.152</cell>
 <cell>0.152</cell>
 <cell>19</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0_RCOSC_25_50MHZ_O2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.254</cell>
 <cell>2.406</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>2.493</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc_RNIH0E4/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.047</cell>
 <cell>3.540</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc_RNIH0E4/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>3.790</cell>
 <cell>17</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[8]:ALn</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc_0_RRight</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.503</cell>
 <cell>4.293</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.293</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>20.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.152</cell>
 <cell>20.152</cell>
 <cell>19</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[8]:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0_RCOSC_25_50MHZ_O2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.029</cell>
 <cell>22.181</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0[8]:ALn</cell>
 <cell>Library recovery time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.353</cell>
 <cell>21.828</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>21.828</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_GL0 to IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:ALn</cell>
 <cell>1.679</cell>
 <cell>18.681</cell>
 <cell>3.147</cell>
 <cell>21.828</cell>
 <cell></cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sdif0_areset_n_rcosc_q1:ALn</cell>
 <cell>1.679</cell>
 <cell>18.690</cell>
 <cell>3.147</cell>
 <cell>21.837</cell>
 <cell></cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_enable:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/count_sdif0_enable_q1:D</cell>
 <cell>0.634</cell>
 <cell>19.816</cell>
 <cell>2.111</cell>
 <cell>21.927</cell>
 <cell>0.254</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>21.828</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.147</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>18.681</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.271</cell>
 <cell>0.271</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.166</cell>
 <cell>0.437</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB5:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.303</cell>
 <cell>0.740</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB5:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>0.990</cell>
 <cell>61</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_RGB1_RGB5_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.478</cell>
 <cell>1.468</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>1.555</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sdif0_areset_n_i:A</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.321</cell>
 <cell>1.876</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sdif0_areset_n_i:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.077</cell>
 <cell>1.953</cell>
 <cell>4</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:ALn</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/N_74_i</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.194</cell>
 <cell>3.147</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.147</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>20.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.152</cell>
 <cell>20.152</cell>
 <cell>19</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/FABOSC_0_RCOSC_25_50MHZ_O2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.029</cell>
 <cell>22.181</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:ALn</cell>
 <cell>Library recovery time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.353</cell>
 <cell>21.828</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>21.828</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Clock Domain IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:APB_PSEL</cell>
 <cell>2.830</cell>
 <cell></cell>
 <cell>5.439</cell>
 <cell></cell>
 <cell>1.481</cell>
 <cell>8.010</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[1]:D</cell>
 <cell>2.998</cell>
 <cell></cell>
 <cell>5.607</cell>
 <cell></cell>
 <cell>0.254</cell>
 <cell>6.464</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[2]:D</cell>
 <cell>2.770</cell>
 <cell></cell>
 <cell>5.379</cell>
 <cell></cell>
 <cell>0.254</cell>
 <cell>6.008</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[14]:D</cell>
 <cell>2.770</cell>
 <cell></cell>
 <cell>5.379</cell>
 <cell></cell>
 <cell>0.254</cell>
 <cell>6.008</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[13]:D</cell>
 <cell>2.770</cell>
 <cell></cell>
 <cell>5.379</cell>
 <cell></cell>
 <cell>0.254</cell>
 <cell>6.008</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: IGLOO2_Oversampling_0/CORECONFIGP_0/psel:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:APB_PSEL</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.439</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.500</cell>
 <cell>1.500</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.223</cell>
 <cell>1.723</cell>
 <cell>4</cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.286</cell>
 <cell>2.009</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.182</cell>
 <cell>2.191</cell>
 <cell>22</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.418</cell>
 <cell>2.609</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/psel:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.108</cell>
 <cell>2.717</cell>
 <cell>20</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/R_SDIF0_PSEL_1_0_a2:C</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/psel</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.454</cell>
 <cell>3.171</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/CORECONFIGP_0/R_SDIF0_PSEL_1_0_a2:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>3.380</cell>
 <cell>36</cell>
 <cell>f</cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/IP_INTERFACE_165:A</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0_SDIF0_INIT_APB_PSELx</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.782</cell>
 <cell>5.162</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/IP_INTERFACE_165:IPA</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.199</cell>
 <cell>5.361</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:APB_PSEL</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0/SERDESIF_INST/APB_PSEL_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.078</cell>
 <cell>5.439</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.439</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.439</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.221</cell>
 <cell>N/C</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B/U0_RGB1_RGB3:An</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.295</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B/U0_RGB1_RGB3:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.251</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/IP_INTERFACE_160:B</cell>
 <cell>net</cell>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B/U0_RGB1_RGB3_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.393</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/IP_INTERFACE_160:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:APB_CLK</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0/SERDESIF_INST/APB_CLK_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.107</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:APB_PSEL</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SERDESIF_IP</cell>
 <cell>-</cell>
 <cell>1.481</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>Receiver_0/Downsampler_0/reg_data_out[2]:CLK</cell>
 <cell>Receiver_0/prbs7_10_0/reg_lock:EN</cell>
 <cell>4.976</cell>
 <cell></cell>
 <cell>8.607</cell>
 <cell></cell>
 <cell>0.335</cell>
 <cell>5.379</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>Receiver_0/prbs7_10_0/LFSR[5]:CLK</cell>
 <cell>Receiver_0/prbs7_10_0/reg_lock:EN</cell>
 <cell>4.855</cell>
 <cell></cell>
 <cell>8.483</cell>
 <cell></cell>
 <cell>0.335</cell>
 <cell>5.255</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>Receiver_0/prbs7_10_0/LFSR[7]:CLK</cell>
 <cell>Receiver_0/prbs7_10_0/reg_lock:EN</cell>
 <cell>4.714</cell>
 <cell></cell>
 <cell>8.342</cell>
 <cell></cell>
 <cell>0.335</cell>
 <cell>5.114</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>Receiver_0/prbs7_10_0/LFSR[4]:CLK</cell>
 <cell>Receiver_0/prbs7_10_0/reg_lock:EN</cell>
 <cell>4.632</cell>
 <cell></cell>
 <cell>8.272</cell>
 <cell></cell>
 <cell>0.335</cell>
 <cell>5.044</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>Receiver_0/Downsampler_0/reg_data_out[7]:CLK</cell>
 <cell>Receiver_0/prbs7_10_0/reg_lock:EN</cell>
 <cell>4.457</cell>
 <cell></cell>
 <cell>8.097</cell>
 <cell></cell>
 <cell>0.335</cell>
 <cell>4.869</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: Receiver_0/Downsampler_0/reg_data_out[2]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: Receiver_0/prbs7_10_0/reg_lock:EN</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>8.607</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1:An</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.333</cell>
 <cell>2.333</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.221</cell>
 <cell>2.554</cell>
 <cell>6</cell>
 <cell>f</cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.319</cell>
 <cell>2.873</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_RGB1_RGB2:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.251</cell>
 <cell>3.124</cell>
 <cell>69</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/Downsampler_0/reg_data_out[2]:CLK</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_RGB1_RGB2_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.507</cell>
 <cell>3.631</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/Downsampler_0/reg_data_out[2]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.092</cell>
 <cell>3.723</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/prbs7_10_0/un1_data_in_2_0:B</cell>
 <cell>net</cell>
 <cell>Receiver_0/Downsampler_0_data_out[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.702</cell>
 <cell>4.425</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/prbs7_10_0/un1_data_in_2_0:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.096</cell>
 <cell>4.521</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Receiver_0/prbs7_10_0/un1_lock_count13_i_o2_0_2:D</cell>
 <cell>net</cell>
 <cell>Receiver_0/prbs7_10_0/un1_data_in_2_0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.088</cell>
 <cell>4.609</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Receiver_0/prbs7_10_0/un1_lock_count13_i_o2_0_2:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.098</cell>
 <cell>4.707</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/prbs7_10_0/un1_lock_count13_i_o2_0_6_1:D</cell>
 <cell>net</cell>
 <cell>Receiver_0/prbs7_10_0/un1_lock_count13_i_o2_0_2</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.244</cell>
 <cell>4.951</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/prbs7_10_0/un1_lock_count13_i_o2_0_6_1:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.234</cell>
 <cell>5.185</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Receiver_0/prbs7_10_0/un1_lock_count13_i_o2_0_6:C</cell>
 <cell>net</cell>
 <cell>Receiver_0/prbs7_10_0/un1_lock_count13_i_o2_0_6_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.598</cell>
 <cell>5.783</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Receiver_0/prbs7_10_0/un1_lock_count13_i_o2_0_6:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.228</cell>
 <cell>6.011</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/prbs7_10_0/un1_lock_count13_i_o2_0:D</cell>
 <cell>net</cell>
 <cell>Receiver_0/prbs7_10_0/un1_lock_count13_i_o2_0_6</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.230</cell>
 <cell>6.241</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/prbs7_10_0/un1_lock_count13_i_o2_0:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.077</cell>
 <cell>6.318</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/prbs7_10_0/un1_lock_count13_i_o2:B</cell>
 <cell>net</cell>
 <cell>Receiver_0/prbs7_10_0/N_164</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.458</cell>
 <cell>6.776</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/prbs7_10_0/un1_lock_count13_i_o2:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.208</cell>
 <cell>6.984</cell>
 <cell>5</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/prbs7_10_0/un1_lock_count13_i_0:B</cell>
 <cell>net</cell>
 <cell>Receiver_0/prbs7_10_0/N_165</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.116</cell>
 <cell>7.100</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/prbs7_10_0/un1_lock_count13_i_0:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.100</cell>
 <cell>7.200</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Receiver_0/prbs7_10_0/reg_lock:EN</cell>
 <cell>net</cell>
 <cell>Receiver_0/prbs7_10_0/un1_lock_count13_i_0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.407</cell>
 <cell>8.607</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>8.607</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1:An</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.333</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.221</cell>
 <cell>N/C</cell>
 <cell>6</cell>
 <cell>f</cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_RGB1_RGB3:An</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.319</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_RGB1_RGB3:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.251</cell>
 <cell>N/C</cell>
 <cell>71</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/prbs7_10_0/reg_lock:CLK</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_RGB1_RGB3_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.439</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/prbs7_10_0/reg_lock:EN</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.335</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Recovery (ns)</cell>
 <cell>Minimum Period (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1[2]:ALn</cell>
 <cell>4.666</cell>
 <cell></cell>
 <cell>4.666</cell>
 <cell></cell>
 <cell>0.353</cell>
 <cell>1.458</cell>
 <cell>-3.561</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg[21]:ALn</cell>
 <cell>4.668</cell>
 <cell></cell>
 <cell>4.668</cell>
 <cell></cell>
 <cell>0.353</cell>
 <cell>1.458</cell>
 <cell>-3.563</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>Receiver_0/Downsampler_0/reg_check[9]:ALn</cell>
 <cell>4.666</cell>
 <cell></cell>
 <cell>4.666</cell>
 <cell></cell>
 <cell>0.353</cell>
 <cell>1.458</cell>
 <cell>-3.561</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1[0]:ALn</cell>
 <cell>4.666</cell>
 <cell></cell>
 <cell>4.666</cell>
 <cell></cell>
 <cell>0.353</cell>
 <cell>1.458</cell>
 <cell>-3.561</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/RX_DATAOUT_reg[22]:ALn</cell>
 <cell>4.666</cell>
 <cell></cell>
 <cell>4.666</cell>
 <cell></cell>
 <cell>0.353</cell>
 <cell>1.458</cell>
 <cell>-3.561</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1[2]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>4.666</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:M_ARADDR[5]</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SERDESIF_IP</cell>
 <cell>+</cell>
 <cell>0.767</cell>
 <cell>0.767</cell>
 <cell>4</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/AND3_0:A</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0_EPCS_1_RX_VAL</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.208</cell>
 <cell>1.975</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/AND3_0:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.077</cell>
 <cell>2.052</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/AND3_0_RNI7UKC:An</cell>
 <cell>net</cell>
 <cell>Receiver_0/AND3_0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.316</cell>
 <cell>3.368</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Receiver_0/AND3_0_RNI7UKC:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.221</cell>
 <cell>3.589</cell>
 <cell>6</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Receiver_0/AND3_0_RNI7UKC/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>Receiver_0/AND3_0_RNI7UKC/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.307</cell>
 <cell>3.896</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Receiver_0/AND3_0_RNI7UKC/U0_RGB1_RGB0:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.251</cell>
 <cell>4.147</cell>
 <cell>47</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1[2]:ALn</cell>
 <cell>net</cell>
 <cell>Receiver_0/AND3_0_RNI7UKC/U0_RGB1_RGB0_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.519</cell>
 <cell>4.666</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.666</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1:An</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.333</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.221</cell>
 <cell>N/C</cell>
 <cell>6</cell>
 <cell>f</cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.314</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_RGB1_RGB0:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.251</cell>
 <cell>N/C</cell>
 <cell>47</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1[2]:CLK</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_RGB1_RGB0_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.442</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD1[2]:ALn</cell>
 <cell>Library recovery time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.353</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain FCCC_GL1</name>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain EPCS_TX_CLK</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>Transmitter_0/FIFO_PRBS_0/Error_Inject_i_delay1:CLK</cell>
 <cell>Transmitter_0/FIFO_PRBS_0/Error_Inject_i_delay2:D</cell>
 <cell>0.493</cell>
 <cell>7.686</cell>
 <cell>0.972</cell>
 <cell>8.658</cell>
 <cell>0.254</cell>
 <cell>0.796</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: Transmitter_0/FIFO_PRBS_0/Error_Inject_i_delay1:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: Transmitter_0/FIFO_PRBS_0/Error_Inject_i_delay2:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>8.658</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>0.972</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.686</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EPCS_TX_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_TX_CLK_inferred_clock_RNI9VS5/U0_RGB1:YL</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Transmitter_0/FIFO_PRBS_0/Error_Inject_i_delay1:CLK</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0_EPCS_1_TX_CLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.479</cell>
 <cell>0.479</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Transmitter_0/FIFO_PRBS_0/Error_Inject_i_delay1:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>0.566</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Transmitter_0/FIFO_PRBS_0/Error_Inject_i_delay2:D</cell>
 <cell>net</cell>
 <cell>Transmitter_0/FIFO_PRBS_0/Error_Inject_i_delay1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.406</cell>
 <cell>0.972</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.972</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EPCS_TX_CLK</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>8.482</cell>
 <cell>8.482</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_TX_CLK_inferred_clock_RNI9VS5/U0_RGB1:YL</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>8.482</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Transmitter_0/FIFO_PRBS_0/Error_Inject_i_delay2:CLK</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0_EPCS_1_TX_CLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.430</cell>
 <cell>8.912</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Transmitter_0/FIFO_PRBS_0/Error_Inject_i_delay2:D</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.254</cell>
 <cell>8.658</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>8.658</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain EPCS_RX_CLK</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2[9]:CLK</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2[3]:D</cell>
 <cell>1.258</cell>
 <cell>6.918</cell>
 <cell>1.762</cell>
 <cell>8.680</cell>
 <cell>0.254</cell>
 <cell>1.564</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2[1]:CLK</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2[0]:D</cell>
 <cell>1.202</cell>
 <cell>6.975</cell>
 <cell>1.695</cell>
 <cell>8.670</cell>
 <cell>0.254</cell>
 <cell>1.507</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2[2]:CLK</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2[0]:D</cell>
 <cell>1.110</cell>
 <cell>7.069</cell>
 <cell>1.601</cell>
 <cell>8.670</cell>
 <cell>0.254</cell>
 <cell>1.413</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3[9]:CLK</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD3[3]:D</cell>
 <cell>1.083</cell>
 <cell>7.106</cell>
 <cell>1.574</cell>
 <cell>8.680</cell>
 <cell>0.254</cell>
 <cell>1.376</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D3[4]:CLK</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD3[1]:D</cell>
 <cell>0.967</cell>
 <cell>7.202</cell>
 <cell>1.466</cell>
 <cell>8.668</cell>
 <cell>0.254</cell>
 <cell>1.280</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2[9]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2[3]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>8.680</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>1.762</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.918</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EPCS_RX_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_RGB1:YL</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2[9]:CLK</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0_EPCS_1_RX_CLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.504</cell>
 <cell>0.504</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2[9]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.108</cell>
 <cell>0.612</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2_13[3]:A</cell>
 <cell>net</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/D2[9]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.680</cell>
 <cell>1.292</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2_13[3]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.395</cell>
 <cell>1.687</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2[3]:D</cell>
 <cell>net</cell>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2_13[3]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.075</cell>
 <cell>1.762</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.762</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EPCS_RX_CLK</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>8.482</cell>
 <cell>8.482</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_RGB1:YL</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>8.482</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2[3]:CLK</cell>
 <cell>net</cell>
 <cell>SERDES_IF_0_EPCS_1_RX_CLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.452</cell>
 <cell>8.934</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Receiver_0/receive_buffer_top_0/rx_data_aligner_0/checkD2[3]:D</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.254</cell>
 <cell>8.680</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>8.680</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set Pin to Pin</name>
<section>
<name>SET Input to Output</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set User Sets</name>
</section>
</doc>
