quietly set ACTELLIBNAME smartfusion2
quietly set PROJECT_DIR "C:/Microsemi/IGLOO2_Oversampling"
source "${PROJECT_DIR}/simulation/SERDESIF_0_compile_bfm.tcl";source "${PROJECT_DIR}/simulation/bfmtovec_compile.tcl";source "${PROJECT_DIR}/simulation/CompileDssBfm.tcl";

if {[file exists presynth/_info]} {
   echo "INFO: Simulation library presynth already exists"
} else {
   file delete -force presynth 
   vlib presynth
}
vmap presynth presynth
vmap smartfusion2 "C:/Microsemi/Libero_v11.3/Designer/lib/modelsim/precompiled/vlog/smartfusion2"
vmap SmartFusion2 "C:/Microsemi/Libero_v11.3/Designer/lib/modelsim/precompiled/vlog/smartfusion2"
vmap COREAHBLITE_LIB "../component/Actel/DirectCore/CoreAHBLite/5.0.100/mti/user_vlog/COREAHBLITE_LIB"
vcom -work COREAHBLITE_LIB -force_refresh
vlog -work COREAHBLITE_LIB -force_refresh

vlog  -work presynth "${PROJECT_DIR}/component/work/IGLOO2_Oversampling_top/FCCC_0/IGLOO2_Oversampling_top_FCCC_0_FCCC.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/IGLOO2_Oversampling/CCC_0/IGLOO2_Oversampling_CCC_0_FCCC.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigMaster/2.0.101/rtl/vlog/core/coreconfigmaster.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigP/5.0.101/rtl/vlog/core/coreconfigp.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.1.100/rtl/vlog/core/coreresetp_pcie_hotreset.v"
vlog  -work presynth "${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.1.100/rtl/vlog/core/coreresetp.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/IGLOO2_Oversampling/FABOSC_0/IGLOO2_Oversampling_FABOSC_0_OSC.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/IGLOO2_Oversampling_HPMS/IGLOO2_Oversampling_HPMS.v"
vlog  -work COREAHBLITE_LIB "${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_addrdec.v"
vlog  -work COREAHBLITE_LIB "${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_defaultslavesm.v"
vlog  -work COREAHBLITE_LIB "${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_masterstage.v"
vlog  -work COREAHBLITE_LIB "${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_slavearbiter.v"
vlog  -work COREAHBLITE_LIB "${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_slavestage.v"
vlog  -work COREAHBLITE_LIB "${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_matrix4x16.v"
vlog  -work COREAHBLITE_LIB "${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/IGLOO2_Oversampling/IGLOO2_Oversampling.v"
vlog  -work presynth "${PROJECT_DIR}/hdl/Downsampler_Rx.v"
vlog  -work presynth "${PROJECT_DIR}/hdl/PRBS_GenCheck.v"
vlog  -work presynth "${PROJECT_DIR}/hdl/rx_data_aligner.v"
vlog  -work presynth "${PROJECT_DIR}/hdl/receive_control.v"
vlog  -work presynth "${PROJECT_DIR}/hdl/receive_buffer_top.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/Receiver/Receiver.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/IGLOO2_Oversampling_top/SERDES_IF_0/IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF.v"
vlog  -work presynth "${PROJECT_DIR}/hdl/FIFO_PRBS.v"
vlog  -work presynth "${PROJECT_DIR}/hdl/Replicator_Tx.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/Transmitter/Transmitter.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/UART_INTERFACE/COREUART_0/rtl/vlog/core/Clock_gen.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/UART_INTERFACE/COREUART_0/rtl/vlog/core/Tx_async.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/UART_INTERFACE/COREUART_0/rtl/vlog/core/Rx_async.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/UART_INTERFACE/COREUART_0/rtl/vlog/core/fifo_256x8_smartfusion2.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/UART_INTERFACE/COREUART_0/rtl/vlog/core/CoreUART.v"
vlog  -work presynth "${PROJECT_DIR}/hdl/FabUART.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/UART_INTERFACE/UART_INTERFACE.v"
vlog  -work presynth "${PROJECT_DIR}/component/work/IGLOO2_Oversampling_top/IGLOO2_Oversampling_top.v"
vlog "+incdir+${PROJECT_DIR}/stimulus"  -work presynth "${PROJECT_DIR}/stimulus/testbench_tb.v"

vsim -L smartfusion2 -L presynth -L COREAHBLITE_LIB  -t 1ps presynth.testbench
do "wave.do"
add log -r /*
run 2us
