@N|Running in 64-bit mode
@N: CG364 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":362:7:362:12|Synthesizing module CLKINT
@N: CG364 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":371:7:371:9|Synthesizing module VCC
@N: CG364 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":367:7:367:9|Synthesizing module GND
@N: CG364 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":722:7:722:9|Synthesizing module CCC
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling_top\FCCC_0\IGLOO2_Oversampling_top_FCCC_0_FCCC.v":5:7:5:41|Synthesizing module IGLOO2_Oversampling_top_FCCC_0_FCCC
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling\CCC_0\IGLOO2_Oversampling_CCC_0_FCCC.v":5:7:5:36|Synthesizing module IGLOO2_Oversampling_CCC_0_FCCC
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreConfigMaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":24:7:24:22|Synthesizing module CoreConfigMaster
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v":29:7:29:25|Synthesizing module COREAHBLITE_ADDRDEC
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v":29:7:29:32|Synthesizing module COREAHBLITE_DEFAULTSLAVESM
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":31:7:31:29|Synthesizing module COREAHBLITE_MASTERSTAGE
@N: CL177 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":629:0:629:5|Sharing sequential element addrRegSMCurrentState.
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v":29:7:29:25|Synthesizing module COREAHBLITE_ADDRDEC
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":31:7:31:29|Synthesizing module COREAHBLITE_MASTERSTAGE
@N: CL177 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":629:0:629:5|Sharing sequential element addrRegSMCurrentState.
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":28:7:28:30|Synthesizing module COREAHBLITE_SLAVEARBITER
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":30:7:30:28|Synthesizing module COREAHBLITE_SLAVESTAGE
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":31:7:31:28|Synthesizing module COREAHBLITE_MATRIX4X16
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":32:7:32:17|Synthesizing module CoreAHBLite
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreConfigP\5.0.101\rtl\vlog\core\coreconfigp.v":22:7:22:17|Synthesizing module CoreConfigP
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":23:7:23:16|Synthesizing module CoreResetP
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v":31:7:31:30|Synthesizing module coreresetp_pcie_hotreset
@N: CL177 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1337:4:1337:9|Sharing sequential element M3_RESET_N_int.
@N: CL177 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":936:4:936:9|Sharing sequential element sdif2_spll_lock_q1.
@N: CL177 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":936:4:936:9|Sharing sequential element sdif1_spll_lock_q1.
@N: CL177 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":936:4:936:9|Sharing sequential element fpll_lock_q1.
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\SgCore\OSC\1.0.100\osc_comps.v":51:7:51:24|Synthesizing module RCOSC_25_50MHZ_FAB
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\SgCore\OSC\1.0.100\osc_comps.v":11:7:11:20|Synthesizing module RCOSC_25_50MHZ
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling\FABOSC_0\IGLOO2_Oversampling_FABOSC_0_OSC.v":5:7:5:38|Synthesizing module IGLOO2_Oversampling_FABOSC_0_OSC
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling_HPMS\IGLOO2_Oversampling_HPMS_syn.v":5:7:5:13|Synthesizing module MSS_010
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling_HPMS\IGLOO2_Oversampling_HPMS.v":9:7:9:30|Synthesizing module IGLOO2_Oversampling_HPMS
@N: CG364 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":713:7:713:14|Synthesizing module SYSRESET
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling\IGLOO2_Oversampling.v":9:7:9:25|Synthesizing module IGLOO2_Oversampling
@N: CG364 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":156:7:156:10|Synthesizing module AND3
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\hdl\Downsampler_Rx.v":29:7:29:17|Synthesizing module Downsampler
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\hdl\PRBS_GenCheck.v":26:7:26:14|Synthesizing module prbs7_10
@N: CG179 :"C:\Microsemi\IGLOO2_Oversampling\hdl\PRBS_GenCheck.v":193:24:193:36|Removing redundant assignment
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\hdl\rx_data_aligner.v":29:7:29:21|Synthesizing module rx_data_aligner
@N: CG179 :"C:\Microsemi\IGLOO2_Oversampling\hdl\rx_data_aligner.v":506:22:506:35|Removing redundant assignment
@N: CG179 :"C:\Microsemi\IGLOO2_Oversampling\hdl\rx_data_aligner.v":507:22:507:34|Removing redundant assignment
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\hdl\receive_control.v":29:7:29:21|Synthesizing module receive_control
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\hdl\receive_buffer_top.v":26:7:26:24|Synthesizing module receive_buffer_top
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\work\Receiver\Receiver.v":9:7:9:14|Synthesizing module Receiver
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling_top\SERDES_IF_0\IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF_syn.v":5:7:5:16|Synthesizing module SERDESIF_0
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling_top\SERDES_IF_0\IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF.v":5:7:5:51|Synthesizing module IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF
@N: CG364 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v":126:7:126:10|Synthesizing module AND2
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\hdl\FIFO_PRBS.v":23:7:23:15|Synthesizing module FIFO_PRBS
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\hdl\Replicator_Tx.v":26:7:26:16|Synthesizing module Replicator
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\work\Transmitter\Transmitter.v":9:7:9:17|Synthesizing module Transmitter
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\work\UART_INTERFACE\COREUART_0\rtl\vlog\core\Clock_gen.v":38:7:38:41|Synthesizing module UART_INTERFACE_COREUART_0_Clock_gen
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\work\UART_INTERFACE\COREUART_0\rtl\vlog\core\Tx_async.v":31:7:31:40|Synthesizing module UART_INTERFACE_COREUART_0_Tx_async
@N: CG179 :"C:\Microsemi\IGLOO2_Oversampling\component\work\UART_INTERFACE\COREUART_0\rtl\vlog\core\Tx_async.v":349:21:349:29|Removing redundant assignment
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\work\UART_INTERFACE\COREUART_0\rtl\vlog\core\Rx_async.v":30:7:30:40|Synthesizing module UART_INTERFACE_COREUART_0_Rx_async
@N: CG179 :"C:\Microsemi\IGLOO2_Oversampling\component\work\UART_INTERFACE\COREUART_0\rtl\vlog\core\Rx_async.v":243:23:243:35|Removing redundant assignment
@N: CL177 :"C:\Microsemi\IGLOO2_Oversampling\component\work\UART_INTERFACE\COREUART_0\rtl\vlog\core\Rx_async.v":459:0:459:5|Sharing sequential element clear_framing_error_en.
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\work\UART_INTERFACE\COREUART_0\rtl\vlog\core\CoreUART.v":31:7:31:40|Synthesizing module UART_INTERFACE_COREUART_0_COREUART
@N: CG179 :"C:\Microsemi\IGLOO2_Oversampling\component\work\UART_INTERFACE\COREUART_0\rtl\vlog\core\CoreUART.v":374:22:374:33|Removing redundant assignment
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\hdl\FabUART.v":26:7:26:13|Synthesizing module FabUART
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\work\UART_INTERFACE\UART_INTERFACE.v":9:7:9:20|Synthesizing module UART_INTERFACE
@N: CG364 :"C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling_top\IGLOO2_Oversampling_top.v":9:7:9:29|Synthesizing module IGLOO2_Oversampling_top
@N: CL201 :"C:\Microsemi\IGLOO2_Oversampling\hdl\FabUART.v":91:0:91:5|Trying to extract state machine for register state
@N: CL201 :"C:\Microsemi\IGLOO2_Oversampling\component\work\UART_INTERFACE\COREUART_0\rtl\vlog\core\Rx_async.v":255:0:255:5|Trying to extract state machine for register rx_state
@N: CL201 :"C:\Microsemi\IGLOO2_Oversampling\component\work\UART_INTERFACE\COREUART_0\rtl\vlog\core\Tx_async.v":112:0:112:5|Trying to extract state machine for register xmit_state
@N: CL201 :"C:\Microsemi\IGLOO2_Oversampling\hdl\FIFO_PRBS.v":74:1:74:6|Trying to extract state machine for register i
@N: CL201 :"C:\Microsemi\IGLOO2_Oversampling\hdl\receive_control.v":82:4:82:9|Trying to extract state machine for register RC_FSM_state
@N: CL201 :"C:\Microsemi\IGLOO2_Oversampling\hdl\rx_data_aligner.v":349:4:349:9|Trying to extract state machine for register DA_FSM_STATE
@N: CL201 :"C:\Microsemi\IGLOO2_Oversampling\hdl\PRBS_GenCheck.v":92:2:92:7|Trying to extract state machine for register tx_count
@N: CL201 :"C:\Microsemi\IGLOO2_Oversampling\hdl\PRBS_GenCheck.v":92:2:92:7|Trying to extract state machine for register rx_count
@N: CL201 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v":179:4:179:9|Trying to extract state machine for register state
@N: CL177 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":936:4:936:9|Sharing sequential element sdif1_spll_lock_q2.
@N: CL177 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":936:4:936:9|Sharing sequential element sdif2_spll_lock_q2.
@N: CL177 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":936:4:936:9|Sharing sequential element fpll_lock_q2.
@N: CL201 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1314:4:1314:9|Trying to extract state machine for register sdif3_state
@N: CL201 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1249:4:1249:9|Trying to extract state machine for register sdif2_state
@N: CL201 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1184:4:1184:9|Trying to extract state machine for register sdif1_state
@N: CL201 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1119:4:1119:9|Trying to extract state machine for register sdif0_state
@N: CL201 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v":1031:4:1031:9|Trying to extract state machine for register sm0_state
@N: CL201 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreConfigP\5.0.101\rtl\vlog\core\coreconfigp.v":433:4:433:9|Trying to extract state machine for register state
@N: CL201 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Trying to extract state machine for register arbRegSMCurrentState
@N: CL201 :"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreConfigMaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":541:4:541:9|Trying to extract state machine for register state

