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<?xml-stylesheet type="text/xsl" href="datasheet.xsl"?>
<datasheet>
  <header>IGLOO2_Oversampling_top</header>
  <project-settings>
    <fam>IGLOO2</fam>
    <die>M2GL010T</die>
    <package>484 FBGA</package>
    <speed-grade>-1</speed-grade>
    <voltage>1.2</voltage>
    <hdl-type>Verilog</hdl-type>
    <project-description>
    </project-description>
    <location>C:/Microsemi/IGLOO2_Oversampling/component/work/IGLOO2_Oversampling_top</location>
    <state>GENERATED ( Mon Apr 14 10:26:11 2014 )</state>
    <swide-toolchain>SoftConsole workspace has not been generated</swide-toolchain>
  </project-settings>
  <site-map>
  </site-map>
  <fileset>
    <name>HDL File(s)</name>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreConfigMaster\2.0.101\rtl\vlog\core\coreconfigmaster.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreConfigP\5.0.101\rtl\vlog\core\coreconfigp.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\Actel\SgCore\OSC\1.0.100\osc_comps.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling\CCC_0\IGLOO2_Oversampling_CCC_0_FCCC.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling\FABOSC_0\IGLOO2_Oversampling_FABOSC_0_OSC.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling\IGLOO2_Oversampling.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling_HPMS\IGLOO2_Oversampling_HPMS.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling_HPMS\IGLOO2_Oversampling_HPMS_pre.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling_HPMS\IGLOO2_Oversampling_HPMS_syn.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling_top\FCCC_0\IGLOO2_Oversampling_top_FCCC_0_FCCC.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling_top\IGLOO2_Oversampling_top.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling_top\SERDES_IF_0\IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling_top\SERDES_IF_0\IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF_pre.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling_top\SERDES_IF_0\IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF_syn.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\work\Receiver\Receiver.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\work\Transmitter\Transmitter.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\work\UART_INTERFACE\COREUART_0\rtl\vlog\core\Clock_gen.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\work\UART_INTERFACE\COREUART_0\rtl\vlog\core\CoreUART.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\work\UART_INTERFACE\COREUART_0\rtl\vlog\core\fifo_256x8_smartfusion2.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\work\UART_INTERFACE\COREUART_0\rtl\vlog\core\Rx_async.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\work\UART_INTERFACE\COREUART_0\rtl\vlog\core\Tx_async.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\component\work\UART_INTERFACE\UART_INTERFACE.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\hdl\Downsampler_Rx.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\hdl\FabUART.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\hdl\FIFO_PRBS.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\hdl\PRBS_GenCheck.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\hdl\receive_buffer_top.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\hdl\receive_control.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\hdl\Replicator_Tx.v</file>
    <file>C:\Microsemi\IGLOO2_Oversampling\hdl\rx_data_aligner.v</file>
  </fileset>
  <core type="SpiritModule">
    <core-exttype>IP</core-exttype>
    <core-type>SpiritModule</core-type>
    <core-vendor>Actel</core-vendor>
    <core-lib>SgCore</core-lib>
    <core-intname>FCCC</core-intname>
    <core-ver>2.0.200</core-ver>
    <core-desc>  "SmartFusion2 Clock Conditioning Circuit (CCC)"  </core-desc>
    <core-name>FCCC_0</core-name>
  </core>
  <core type="ComponentModule">
    <core-type>ComponentModule</core-type>
    <core-exttype>SysBldDesign</core-exttype>
    <core-location>C:/Microsemi/IGLOO2_Oversampling/component/work/IGLOO2_Oversampling</core-location>
    <core-name>IGLOO2_Oversampling_0</core-name>
  </core>
  <core type="ComponentModule">
    <core-type>ComponentModule</core-type>
    <core-exttype>SmartDesign</core-exttype>
    <core-location>C:/Microsemi/IGLOO2_Oversampling/component/work/Receiver</core-location>
    <core-name>Receiver_0</core-name>
  </core>
  <core type="SpiritModule">
    <core-exttype>IP</core-exttype>
    <core-type>SpiritModule</core-type>
    <core-vendor>Actel</core-vendor>
    <core-lib>SgCore</core-lib>
    <core-intname>SERDES_IF</core-intname>
    <core-ver>1.2.005</core-ver>
    <core-desc>High Speed Serial Interface</core-desc>
    <core-name>SERDES_IF_0</core-name>
  </core>
  <core type="ComponentModule">
    <core-type>ComponentModule</core-type>
    <core-exttype>SmartDesign</core-exttype>
    <core-location>C:/Microsemi/IGLOO2_Oversampling/component/work/Transmitter</core-location>
    <core-name>Transmitter_0</core-name>
  </core>
  <core type="ComponentModule">
    <core-type>ComponentModule</core-type>
    <core-exttype>SmartDesign</core-exttype>
    <core-location>C:/Microsemi/IGLOO2_Oversampling/component/work/UART_INTERFACE</core-location>
    <core-name>UART_INTERFACE_0</core-name>
  </core>
  <memorysystem>
    <title>Memory Map for IGLOO2_Oversampling_top</title>
    <description>The project contains the following subsystems:</description>
    <subsystems>
      <subsystem>
        <name>HPMS_MASTERS</name>
        <master>HPMS_MASTERS</master>
        <master>FAB_TO_FIC_0_AHB_BRIDGE</master>
        <addressNames>
          <count>1</count>
          <name>
          </name>
        </addressNames>
        <slave>
          <name>FIC_REGION_5</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0xF0000000</remapAddress>
          <fullAddressSpace>0xF0000000 - 0xFFFFFFFF</fullAddressSpace>
          <range>0x10000000</range>
        </slave>
        <slave>
          <name>DDR_0_SPACE_3</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0xD0000000</remapAddress>
          <fullAddressSpace>0xD0000000 - 0xDFFFFFFF</fullAddressSpace>
          <range>0x10000000</range>
        </slave>
        <slave>
          <name>DDR_0_SPACE_2</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0xC0000000</remapAddress>
          <fullAddressSpace>0xC0000000 - 0xCFFFFFFF</fullAddressSpace>
          <range>0x10000000</range>
        </slave>
        <slave>
          <name>DDR_0_SPACE_1</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0xB0000000</remapAddress>
          <fullAddressSpace>0xB0000000 - 0xBFFFFFFF</fullAddressSpace>
          <range>0x10000000</range>
        </slave>
        <slave>
          <name>DDR_0_SPACE_0</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0xA0000000</remapAddress>
          <fullAddressSpace>0xA0000000 - 0xAFFFFFFF</fullAddressSpace>
          <range>0x10000000</range>
        </slave>
        <slave>
          <name>FIC_REGION_4</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x90000000</remapAddress>
          <fullAddressSpace>0x90000000 - 0x9FFFFFFF</fullAddressSpace>
          <range>0x10000000</range>
        </slave>
        <slave>
          <name>FIC_REGION_3</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x80000000</remapAddress>
          <fullAddressSpace>0x80000000 - 0x8FFFFFFF</fullAddressSpace>
          <range>0x10000000</range>
        </slave>
        <slave>
          <name>AHB_TO_ENVM_1_REGISTERS</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x600C0000</remapAddress>
          <fullAddressSpace>0x600C0000 - 0x600FFFFF</fullAddressSpace>
          <range>0x00040000</range>
        </slave>
        <slave>
          <name>AHB_TO_ENVM_0_REGISTERS</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x60080000</remapAddress>
          <fullAddressSpace>0x60080000 - 0x600BFFFF</fullAddressSpace>
          <range>0x00040000</range>
        </slave>
        <slave>
          <name>ENVM_1</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x60040000</remapAddress>
          <fullAddressSpace>0x60040000 - 0x6007FFFF</fullAddressSpace>
          <range>0x00040000</range>
        </slave>
        <slave>
          <name>ENVM_0</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x60000000</remapAddress>
          <fullAddressSpace>0x60000000 - 0x6003FFFF</fullAddressSpace>
          <range>0x00040000</range>
        </slave>
        <slave>
          <name>FIC_REGION_1</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x50000000</remapAddress>
          <fullAddressSpace>0x50000000 - 0x5FFFFFFF</fullAddressSpace>
          <range>0x10000000</range>
        </slave>
        <slave>
          <name>SYSREG</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x40038000</remapAddress>
          <fullAddressSpace>0x40038000 - 0x40038FFF</fullAddressSpace>
          <range>0x00001000</range>
        </slave>
        <slave>
          <name>CORECONFIGP_0</name>
          <fullPinName>IGLOO2_Oversampling:SDIF0_INIT_APB</fullPinName>
          <remapAddress>0x40028000</remapAddress>
          <fullAddressSpace>0x40028000 - 0x4002A3FF</fullAddressSpace>
          <range>0x2400</range>
        </slave>
        <slave>
          <name>COMM_BLK</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x40016000</remapAddress>
          <fullAddressSpace>0x40016000 - 0x40016FFF</fullAddressSpace>
          <range>0x1000</range>
        </slave>
        <slave>
          <name>HPDMA</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x40014000</remapAddress>
          <fullAddressSpace>0x40014000 - 0x40014FFF</fullAddressSpace>
          <range>0x1000</range>
        </slave>
        <slave>
          <name>H2FINTERRUPT</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x40006000</remapAddress>
          <fullAddressSpace>0x40006000 - 0x40006FFF</fullAddressSpace>
          <range>0x1000</range>
        </slave>
        <slave>
          <name>PDMA</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x40003000</remapAddress>
          <fullAddressSpace>0x40003000 - 0x40003FFF</fullAddressSpace>
          <range>0x1000</range>
        </slave>
        <slave>
          <name>ESRAM_1</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x20008000</remapAddress>
          <fullAddressSpace>0x20008000 - 0x2000FFFF</fullAddressSpace>
          <range>0x00008000</range>
        </slave>
        <slave>
          <name>ESRAM_0</name>
          <fullPinName>
          </fullPinName>
          <remapAddress>0x20080000</remapAddress>
          <fullAddressSpace>0x20080000 - 0x20087FFF</fullAddressSpace>
          <range>0x00008000</range>
        </slave>
      </subsystem>
      <subsystem>
        <name>ConfigMaster_0</name>
        <master>ConfigMaster_0</master>
        <addressNames>
          <count>1</count>
          <name>
          </name>
        </addressNames>
        <slave>
          <name>FIC32_0</name>
          <fullPinName>IGLOO2_Oversampling_HPMS_0:FIC_0_AHB_SLAVE</fullPinName>
          <remapAddress>0x80000000</remapAddress>
          <fullAddressSpace>0x80000000 - 0x7FFFFFFF</fullAddressSpace>
          <range>0x00000000</range>
        </slave>
      </subsystem>
    </subsystems>
  </memorysystem>
</datasheet>
