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<doc>
<title>Global Net Report</title>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.3 (Version 11.3.0.112)</text>
<text>Date: Fri Apr 18 09:32:10 2014
</text>
<section>
<name>Global Nets Information</name>
<table>
<header>
 <cell/>
 <cell> From </cell>
 <cell> GB Location </cell>
 <cell> Net Name </cell>
 <cell> Fanout </cell>
</header>
<row>
 <cell>1</cell>
 <cell>GB[0] </cell>
 <cell>(218, 54)</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell>423</cell>
</row>
<row>
 <cell>2</cell>
 <cell>GB[2] </cell>
 <cell>(220, 54)</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int_RNICDJF_0/U0_YNn</cell>
 <cell>397</cell>
</row>
<row>
 <cell>3</cell>
 <cell>GB[6] </cell>
 <cell>(224, 54)</cell>
 <cell>Receiver_0/AND3_0_RNI7UKC/U0_YNn_GSouth</cell>
 <cell>288</cell>
</row>
<row>
 <cell>4</cell>
 <cell>GB[7] </cell>
 <cell>(225, 54)</cell>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK_inferred_clock_RNI7NV1/U0_YNn_GSouth</cell>
 <cell>288</cell>
</row>
<row>
 <cell>5</cell>
 <cell>GB[3] </cell>
 <cell>(221, 54)</cell>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIO88B/U0_YNn</cell>
 <cell>106</cell>
</row>
<row>
 <cell>6</cell>
 <cell>GB[4] </cell>
 <cell>(222, 54)</cell>
 <cell>FCCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell>106</cell>
</row>
<row>
 <cell>7</cell>
 <cell>GB[1] </cell>
 <cell>(219, 54)</cell>
 <cell>SERDES_IF_0/EPCS_1_TX_CLK_inferred_clock_RNI9VS5/U0_YNn_GSouth</cell>
 <cell>49</cell>
</row>
<row>
 <cell>8</cell>
 <cell>GB[5] </cell>
 <cell>(223, 54)</cell>
 <cell>FCCC_0/GL1_INST/U0_YNn_GSouth</cell>
 <cell>1</cell>
</row>
</table>
<text></text>
</section>
<section>
<name>I/O to GB Connections</name>
<text>(none)</text>
</section>
<section>
<name>Fabric to GB Connections</name>
<table>
<header>
 <cell/>
 <cell> From </cell>
 <cell> From Location </cell>
 <cell> To </cell>
 <cell> Net name </cell>
 <cell> Net type </cell>
 <cell> Fanout </cell>
</header>
<row>
 <cell>1</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int_RNICDJF:Y</cell>
 <cell>(363, 48)</cell>
 <cell>GB[2] </cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/FAB_RESET_N_int_RNICDJF</cell>
 <cell>ROUTED</cell>
 <cell>1</cell>
</row>
<row>
 <cell>2</cell>
 <cell>Receiver_0/AND3_0/U0:Y</cell>
 <cell>(138, 15)</cell>
 <cell>GB[6] </cell>
 <cell>Receiver_0/AND3_0</cell>
 <cell>ROUTED</cell>
 <cell>1</cell>
</row>
<row>
 <cell>3</cell>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK_1</cell>
 <cell>(12, 2)</cell>
 <cell>GB[7] </cell>
 <cell>SERDES_IF_0/EPCS_1_RX_CLK</cell>
 <cell>ROUTED</cell>
 <cell>1</cell>
</row>
<row>
 <cell>4</cell>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_CONFIG_APB</cell>
 <cell>(300, 104)</cell>
 <cell>GB[3] </cell>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/FIC_2_APB_M_PCLK</cell>
 <cell>ROUTED</cell>
 <cell>1</cell>
</row>
<row>
 <cell>5</cell>
 <cell>SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK_1</cell>
 <cell>(12, 2)</cell>
 <cell>GB[1] </cell>
 <cell>SERDES_IF_0/EPCS_1_TX_CLK</cell>
 <cell>ROUTED</cell>
 <cell>1</cell>
</row>
</table>
<text></text>
</section>
<section>
<name>CCC to GB Connections</name>
<table>
<header>
 <cell/>
 <cell> From </cell>
 <cell> From Location </cell>
 <cell> To </cell>
 <cell> Net name </cell>
 <cell> Net type </cell>
 <cell> Fanout </cell>
</header>
<row>
 <cell>1</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>CCC-NE1 (390, 92)</cell>
 <cell>GB[0] </cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/GL0_net</cell>
 <cell>HARDWIRED</cell>
 <cell>1</cell>
</row>
<row>
 <cell>2</cell>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>CCC-NE0 (372, 92)</cell>
 <cell>GB[4] </cell>
 <cell>FCCC_0/GL0_net</cell>
 <cell>HARDWIRED</cell>
 <cell>1</cell>
</row>
<row>
 <cell>3</cell>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL1</cell>
 <cell>CCC-NE0 (372, 92)</cell>
 <cell>GB[5] </cell>
 <cell>FCCC_0/GL1_net</cell>
 <cell>HARDWIRED</cell>
 <cell>1</cell>
</row>
</table>
<text></text>
</section>
<section>
<name>CCC Input Connections</name>
<table>
<header>
 <cell/>
 <cell> Port Name </cell>
 <cell> Pin Number </cell>
 <cell> I/O Function </cell>
 <cell> From </cell>
 <cell> From Location </cell>
 <cell> To </cell>
 <cell> CCC Location </cell>
 <cell> Net name </cell>
 <cell> Net type </cell>
 <cell> Fanout </cell>
</header>
<row>
 <cell>1</cell>
 <cell>CLK0</cell>
 <cell>K1</cell>
 <cell>MSIOD85PB6/CCC_NE1_CLKI1</cell>
 <cell>CLK0_ibuf/U0/U_IOIN:Y</cell>
 <cell>West IO #0 (0, 43)</cell>
 <cell>IGLOO2_Oversampling_0/CCC_0/CCC_INST/INST_CCC_IP:CLK0</cell>
 <cell>CCC-NE1 (390, 92)</cell>
 <cell>CLK0_c</cell>
 <cell>ROUTED</cell>
 <cell>2</cell>
</row>
</table>
<text></text>
</section>
<section>
<name>Local Clock Nets to RGB Connections</name>
<table>
<header>
 <cell/>
 <cell> From </cell>
 <cell> From Location </cell>
 <cell> Net Name </cell>
 <cell> Fanout </cell>
 <cell> RGB Location </cell>
 <cell> Local Fanout </cell>
</header>
<row>
 <cell>1</cell>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CONFIG_PRESET_N</cell>
 <cell>(300, 104)</cell>
 <cell>IGLOO2_Oversampling_0/IGLOO2_Oversampling_HPMS_0/CONFIG_PRESET_N</cell>
 <cell>108</cell>
 <cell>(218, 0)</cell>
 <cell>1</cell>
</row>
<row>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell>(218, 45)</cell>
 <cell>23</cell>
</row>
<row>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell>(218, 48)</cell>
 <cell>27</cell>
</row>
<row>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell>(218, 51)</cell>
 <cell>22</cell>
</row>
<row>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell>(218, 57)</cell>
 <cell>35</cell>
</row>
<row>
 <cell>2</cell>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:LOCK</cell>
 <cell>CCC-NE0 (372, 92)</cell>
 <cell>FCCC_0/LOCK</cell>
 <cell>106</cell>
 <cell>(219, 12)</cell>
 <cell>24</cell>
</row>
<row>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell>(220, 18)</cell>
 <cell>28</cell>
</row>
<row>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell>(220, 21)</cell>
 <cell>29</cell>
</row>
<row>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell>(220, 24)</cell>
 <cell>12</cell>
</row>
<row>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell>(221, 15)</cell>
 <cell>13</cell>
</row>
<row>
 <cell>3</cell>
 <cell>Transmitter_0/AND2_0/U0:Y</cell>
 <cell>(139, 15)</cell>
 <cell>Transmitter_0/AND2_0</cell>
 <cell>49</cell>
 <cell>(218, 3)</cell>
 <cell>22</cell>
</row>
<row>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell>(218, 6)</cell>
 <cell>23</cell>
</row>
<row>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell>(218, 9)</cell>
 <cell>2</cell>
</row>
<row>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell>(219, 15)</cell>
 <cell>2</cell>
</row>
<row>
 <cell>4</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc:Q</cell>
 <cell>(370, 43)</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_rcosc</cell>
 <cell>17</cell>
 <cell>(220, 42)</cell>
 <cell>17</cell>
</row>
<row>
 <cell>5</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_clk_base:Q</cell>
 <cell>(372, 46)</cell>
 <cell>IGLOO2_Oversampling_0/CORERESETP_0/sm0_areset_n_clk_base</cell>
 <cell>14</cell>
 <cell>(221, 42)</cell>
 <cell>12</cell>
</row>
<row>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell> </cell>
 <cell>(222, 45)</cell>
 <cell>2</cell>
</row>
</table>
<text></text>
</section>
</doc>
