`

    @W:CG775 : coreahblite.v(32) | Found Component CoreAHBLite in library COREAHBLITE_LIB
    @W:CL190 : Tx_async.v(112) | Optimizing register bit fifo_read_en0 to a constant 1
    @W:CL169 : Tx_async.v(112) | Pruning register fifo_read_en0
    @W:CG360 : CoreUART.v(111) | No assignment to wire tx_dout_reg
    @W:CG360 : CoreUART.v(112) | No assignment to wire rx_dout
    @W:CG360 : CoreUART.v(118) | No assignment to wire fifo_empty_tx
    @W:CG360 : CoreUART.v(119) | No assignment to wire fifo_empty_rx
    @W:CG360 : CoreUART.v(123) | No assignment to wire fifo_full_tx
    @W:CG360 : CoreUART.v(124) | No assignment to wire fifo_full_rx
    @W:CG133 : CoreUART.v(135) | No assignment to data_ready
    @W:CL169 : CoreUART.v(360) | Pruning register overflow_reg
    @W:CL169 : CoreUART.v(335) | Pruning register rx_dout_reg_empty
    @W:CL169 : CoreUART.v(335) | Pruning register rx_dout_reg_empty_q
    @W:CL169 : CoreUART.v(320) | Pruning register rx_dout_reg[7:0]
    @W:CL169 : CoreUART.v(287) | Pruning register rx_state[1:0]
    @W:CL169 : CoreUART.v(272) | Pruning register clear_framing_error_reg
    @W:CL169 : CoreUART.v(272) | Pruning register clear_framing_error_reg0
    @W:CL169 : CoreUART.v(257) | Pruning register clear_parity_reg
    @W:CL169 : CoreUART.v(257) | Pruning register clear_parity_reg0
    @W:CL169 : CoreUART.v(154) | Pruning register fifo_write_tx
    @W:CL190 : FabUART.v(71) | Optimizing register bit uart_data_out_t[6] to a constant 0
    @W:CL190 : FabUART.v(71) | Optimizing register bit uart_data_out_t[7] to a constant 0
    @W:CL279 : FabUART.v(71) | Pruning register bits 7 to 6 of uart_data_out_t[7:0]
    @W:CL190 : FIFO_PRBS.v(68) | Optimizing register bit reg_tx_val_out to a constant 1
    @W:CL190 : coreconfigmaster.v(541) | Optimizing register bit HTRANS[0] to a constant 0
    @W:CL260 : coreconfigmaster.v(541) | Pruning register bit 0 of HTRANS[1:0]
    @W:CG775 : coreahblite.v(32) | Found Component CoreAHBLite in library COREAHBLITE_LIB
    @W:CL169 : coreresetp.v(1562) | Pruning register count_ddr[13:0]
    @W:CL169 : coreresetp.v(1530) | Pruning register count_sdif3[12:0]
    @W:CL169 : coreresetp.v(1498) | Pruning register count_sdif2[12:0]
    @W:CL169 : coreresetp.v(1466) | Pruning register count_sdif1[12:0]
    @W:CL169 : coreresetp.v(1404) | Pruning register count_sdif1_enable_q1
    @W:CL169 : coreresetp.v(1404) | Pruning register count_sdif2_enable_q1
    @W:CL169 : coreresetp.v(1404) | Pruning register count_sdif3_enable_q1
    @W:CL169 : coreresetp.v(1404) | Pruning register count_sdif1_enable_rcosc
    @W:CL169 : coreresetp.v(1404) | Pruning register count_sdif2_enable_rcosc
    @W:CL169 : coreresetp.v(1404) | Pruning register count_sdif3_enable_rcosc
    @W:CL169 : coreresetp.v(1404) | Pruning register count_ddr_enable_q1
    @W:CL169 : coreresetp.v(1404) | Pruning register count_ddr_enable_rcosc
    @W:CL169 : coreresetp.v(1314) | Pruning register count_sdif3_enable
    @W:CL169 : coreresetp.v(1249) | Pruning register count_sdif2_enable
    @W:CL169 : coreresetp.v(1184) | Pruning register count_sdif1_enable
    @W:CL169 : coreresetp.v(1031) | Pruning register count_ddr_enable
    @W:CL190 : coreresetp.v(1382) | Optimizing register bit EXT_RESET_OUT_int to a constant 0
    @W:CL169 : coreresetp.v(1031) | Pruning register release_ext_reset
    @W:CL169 : coreresetp.v(1382) | Pruning register EXT_RESET_OUT_int
    @W:CL169 : coreresetp.v(1382) | Pruning register sm2_state[2:0]
    @W:CL169 : coreresetp.v(756) | Pruning register sm2_areset_n_q1
    @W:CL169 : coreresetp.v(756) | Pruning register sm2_areset_n_clk_base
    @W:CL247 : IGLOO2_Oversampling_HPMS.v(51) | Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused
    @W:CL157 : IGLOO2_Oversampling_FABOSC_0_OSC.v(15) | *Output RCOSC_25_50MHZ_CCC has undriven bits -- simulation mismatch possible.
    @W:CL157 : IGLOO2_Oversampling_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible.
    @W:CL157 : IGLOO2_Oversampling_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible.
    @W:CL157 : IGLOO2_Oversampling_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits -- simulation mismatch possible.
    @W:CL157 : IGLOO2_Oversampling_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits -- simulation mismatch possible.
    @W:CL159 : IGLOO2_Oversampling_FABOSC_0_OSC.v(14) | Input XTL is unused
    @W:CL247 : coreresetp_pcie_hotreset.v(36) | Input port bit 31 of prdata[31:0] is unused
    @W:CL246 : coreresetp_pcie_hotreset.v(36) | Input port bits 25 to 0 of prdata[31:0] are unused
    @W:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused
    @W:CL159 : coreresetp.v(63) | Input SDIF1_SPLL_LOCK is unused
    @W:CL159 : coreresetp.v(67) | Input SDIF2_SPLL_LOCK is unused
    @W:CL159 : coreresetp.v(71) | Input SDIF3_SPLL_LOCK is unused
    @W:CL159 : coreresetp.v(88) | Input SDIF1_PSEL is unused
    @W:CL159 : coreresetp.v(89) | Input SDIF1_PWRITE is unused
    @W:CL159 : coreresetp.v(90) | Input SDIF1_PRDATA is unused
    @W:CL159 : coreresetp.v(91) | Input SDIF2_PSEL is unused
    @W:CL159 : coreresetp.v(92) | Input SDIF2_PWRITE is unused
    @W:CL159 : coreresetp.v(93) | Input SDIF2_PRDATA is unused
    @W:CL159 : coreresetp.v(94) | Input SDIF3_PSEL is unused
    @W:CL159 : coreresetp.v(95) | Input SDIF3_PWRITE is unused
    @W:CL159 : coreresetp.v(96) | Input SDIF3_PRDATA is unused
    @W:CL247 : coreahblite.v(128) | Input port bit 0 of HTRANS_M0[1:0] is unused
    @W:CL247 : coreahblite.v(139) | Input port bit 0 of HTRANS_M1[1:0] is unused
    @W:CL247 : coreahblite.v(150) | Input port bit 0 of HTRANS_M2[1:0] is unused
    @W:CL247 : coreahblite.v(161) | Input port bit 0 of HTRANS_M3[1:0] is unused
    @W:CL247 : coreahblite.v(171) | Input port bit 1 of HRESP_S0[1:0] is unused
    @W:CL247 : coreahblite.v(184) | Input port bit 1 of HRESP_S1[1:0] is unused
    @W:CL247 : coreahblite.v(197) | Input port bit 1 of HRESP_S2[1:0] is unused
    @W:CL247 : coreahblite.v(210) | Input port bit 1 of HRESP_S3[1:0] is unused
    @W:CL247 : coreahblite.v(223) | Input port bit 1 of HRESP_S4[1:0] is unused
    @W:CL247 : coreahblite.v(236) | Input port bit 1 of HRESP_S5[1:0] is unused
    @W:CL247 : coreahblite.v(249) | Input port bit 1 of HRESP_S6[1:0] is unused
    @W:CL247 : coreahblite.v(262) | Input port bit 1 of HRESP_S7[1:0] is unused
    @W:CL247 : coreahblite.v(275) | Input port bit 1 of HRESP_S8[1:0] is unused
    @W:CL247 : coreahblite.v(288) | Input port bit 1 of HRESP_S9[1:0] is unused
    @W:CL247 : coreahblite.v(301) | Input port bit 1 of HRESP_S10[1:0] is unused
    @W:CL247 : coreahblite.v(314) | Input port bit 1 of HRESP_S11[1:0] is unused
    @W:CL247 : coreahblite.v(327) | Input port bit 1 of HRESP_S12[1:0] is unused
    @W:CL247 : coreahblite.v(340) | Input port bit 1 of HRESP_S13[1:0] is unused
    @W:CL247 : coreahblite.v(353) | Input port bit 1 of HRESP_S14[1:0] is unused
    @W:CL247 : coreahblite.v(366) | Input port bit 1 of HRESP_S15[1:0] is unused
    @W:CL247 : coreahblite.v(379) | Input port bit 1 of HRESP_S16[1:0] is unused
    @W:CL159 : coreahblite.v(131) | Input HBURST_M0 is unused
    @W:CL159 : coreahblite.v(132) | Input HPROT_M0 is unused
    @W:CL159 : coreahblite.v(142) | Input HBURST_M1 is unused
    @W:CL159 : coreahblite.v(143) | Input HPROT_M1 is unused
    @W:CL159 : coreahblite.v(153) | Input HBURST_M2 is unused
    @W:CL159 : coreahblite.v(154) | Input HPROT_M2 is unused
    @W:CL159 : coreahblite.v(164) | Input HBURST_M3 is unused
    @W:CL159 : coreahblite.v(165) | Input HPROT_M3 is unused
    @W:CL159 : coreahblite_matrix4x16.v(58) | Input HWDATA_M1 is unused
    @W:CL159 : coreahblite_matrix4x16.v(67) | Input HWDATA_M2 is unused
    @W:CL159 : coreahblite_matrix4x16.v(76) | Input HWDATA_M3 is unused
    @W:CL159 : coreahblite_matrix4x16.v(80) | Input HRDATA_S0 is unused
    @W:CL159 : coreahblite_matrix4x16.v(81) | Input HREADYOUT_S0 is unused
    @W:CL159 : coreahblite_matrix4x16.v(82) | Input HRESP_S0 is unused
    @W:CL159 : coreahblite_matrix4x16.v(91) | Input HRDATA_S1 is unused
    @W:CL159 : coreahblite_matrix4x16.v(92) | Input HREADYOUT_S1 is unused
    @W:CL159 : coreahblite_matrix4x16.v(93) | Input HRESP_S1 is unused
    @W:CL159 : coreahblite_matrix4x16.v(102) | Input HRDATA_S2 is unused
    @W:CL159 : coreahblite_matrix4x16.v(103) | Input HREADYOUT_S2 is unused
    @W:CL159 : coreahblite_matrix4x16.v(104) | Input HRESP_S2 is unused
    @W:CL159 : coreahblite_matrix4x16.v(113) | Input HRDATA_S3 is unused
    @W:CL159 : coreahblite_matrix4x16.v(114) | Input HREADYOUT_S3 is unused
    @W:CL159 : coreahblite_matrix4x16.v(115) | Input HRESP_S3 is unused
    @W:CL159 : coreahblite_matrix4x16.v(124) | Input HRDATA_S4 is unused
    @W:CL159 : coreahblite_matrix4x16.v(125) | Input HREADYOUT_S4 is unused
    @W:CL159 : coreahblite_matrix4x16.v(126) | Input HRESP_S4 is unused
    @W:CL159 : coreahblite_matrix4x16.v(135) | Input HRDATA_S5 is unused
    @W:CL159 : coreahblite_matrix4x16.v(136) | Input HREADYOUT_S5 is unused
    @W:CL159 : coreahblite_matrix4x16.v(137) | Input HRESP_S5 is unused
    @W:CL159 : coreahblite_matrix4x16.v(146) | Input HRDATA_S6 is unused
    @W:CL159 : coreahblite_matrix4x16.v(147) | Input HREADYOUT_S6 is unused
    @W:CL159 : coreahblite_matrix4x16.v(148) | Input HRESP_S6 is unused
    @W:CL159 : coreahblite_matrix4x16.v(157) | Input HRDATA_S7 is unused
    @W:CL159 : coreahblite_matrix4x16.v(158) | Input HREADYOUT_S7 is unused
    @W:CL159 : coreahblite_matrix4x16.v(159) | Input HRESP_S7 is unused
    @W:CL159 : coreahblite_matrix4x16.v(168) | Input HRDATA_S8 is unused
    @W:CL159 : coreahblite_matrix4x16.v(169) | Input HREADYOUT_S8 is unused
    @W:CL159 : coreahblite_matrix4x16.v(170) | Input HRESP_S8 is unused
    @W:CL159 : coreahblite_matrix4x16.v(179) | Input HRDATA_S9 is unused
    @W:CL159 : coreahblite_matrix4x16.v(180) | Input HREADYOUT_S9 is unused
    @W:CL159 : coreahblite_matrix4x16.v(181) | Input HRESP_S9 is unused
    @W:CL159 : coreahblite_matrix4x16.v(190) | Input HRDATA_S10 is unused
    @W:CL159 : coreahblite_matrix4x16.v(191) | Input HREADYOUT_S10 is unused
    @W:CL159 : coreahblite_matrix4x16.v(192) | Input HRESP_S10 is unused
    @W:CL159 : coreahblite_matrix4x16.v(201) | Input HRDATA_S11 is unused
    @W:CL159 : coreahblite_matrix4x16.v(202) | Input HREADYOUT_S11 is unused
    @W:CL159 : coreahblite_matrix4x16.v(203) | Input HRESP_S11 is unused
    @W:CL159 : coreahblite_matrix4x16.v(212) | Input HRDATA_S12 is unused
    @W:CL159 : coreahblite_matrix4x16.v(213) | Input HREADYOUT_S12 is unused
    @W:CL159 : coreahblite_matrix4x16.v(214) | Input HRESP_S12 is unused
    @W:CL159 : coreahblite_matrix4x16.v(223) | Input HRDATA_S13 is unused
    @W:CL159 : coreahblite_matrix4x16.v(224) | Input HREADYOUT_S13 is unused
    @W:CL159 : coreahblite_matrix4x16.v(225) | Input HRESP_S13 is unused
    @W:CL159 : coreahblite_matrix4x16.v(234) | Input HRDATA_S14 is unused
    @W:CL159 : coreahblite_matrix4x16.v(235) | Input HREADYOUT_S14 is unused
    @W:CL159 : coreahblite_matrix4x16.v(236) | Input HRESP_S14 is unused
    @W:CL159 : coreahblite_matrix4x16.v(245) | Input HRDATA_S15 is unused
    @W:CL159 : coreahblite_matrix4x16.v(246) | Input HREADYOUT_S15 is unused
    @W:CL159 : coreahblite_matrix4x16.v(247) | Input HRESP_S15 is unused
    @W:CL246 : coreahblite_slavestage.v(46) | Input port bits 3 to 2 of MPREVDATASLAVEREADY[3:0] are unused
    @W:CL159 : coreahblite_masterstage.v(50) | Input SDATAREADY is unused
    @W:CL159 : coreahblite_masterstage.v(51) | Input SHRESP is unused
    @W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S0 is unused
    @W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S0 is unused
    @W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S1 is unused
    @W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S1 is unused
    @W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S2 is unused
    @W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S2 is unused
    @W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S3 is unused
    @W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S3 is unused
    @W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S4 is unused
    @W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S4 is unused
    @W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S5 is unused
    @W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S5 is unused
    @W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S6 is unused
    @W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S6 is unused
    @W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S7 is unused
    @W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S7 is unused
    @W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S8 is unused
    @W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S8 is unused
    @W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S9 is unused
    @W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S9 is unused
    @W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S10 is unused
    @W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S10 is unused
    @W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S11 is unused
    @W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S11 is unused
    @W:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S12 is unused
    @W:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S12 is unused
    @W:CL159 : coreahblite_masterstage.v(86) | Input HRDATA_S13 is unused
    @W:CL159 : coreahblite_masterstage.v(87) | Input HREADYOUT_S13 is unused
    @W:CL159 : coreahblite_masterstage.v(88) | Input HRDATA_S14 is unused
    @W:CL159 : coreahblite_masterstage.v(89) | Input HREADYOUT_S14 is unused
    @W:CL159 : coreahblite_masterstage.v(90) | Input HRDATA_S15 is unused
    @W:CL159 : coreahblite_masterstage.v(91) | Input HREADYOUT_S15 is unused
    @W:CL159 : coreahblite_masterstage.v(92) | Input HRDATA_S16 is unused
    @W:CL159 : coreahblite_masterstage.v(93) | Input HREADYOUT_S16 is unused
    @W:CL246 : coreahblite_masterstage.v(50) | Input port bits 15 to 0 of SDATAREADY[16:0] are unused
    @W:CL246 : coreahblite_masterstage.v(51) | Input port bits 15 to 0 of SHRESP[16:0] are unused
    @W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S0 is unused
    @W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S0 is unused
    @W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S1 is unused
    @W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S1 is unused
    @W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S2 is unused
    @W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S2 is unused
    @W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S3 is unused
    @W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S3 is unused
    @W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S4 is unused
    @W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S4 is unused
    @W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S5 is unused
    @W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S5 is unused
    @W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S6 is unused
    @W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S6 is unused
    @W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S7 is unused
    @W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S7 is unused
    @W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S8 is unused
    @W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S8 is unused
    @W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S9 is unused
    @W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S9 is unused
    @W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S10 is unused
    @W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S10 is unused
    @W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S11 is unused
    @W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S11 is unused
    @W:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S12 is unused
    @W:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S12 is unused
    @W:CL159 : coreahblite_masterstage.v(86) | Input HRDATA_S13 is unused
    @W:CL159 : coreahblite_masterstage.v(87) | Input HREADYOUT_S13 is unused
    @W:CL159 : coreahblite_masterstage.v(88) | Input HRDATA_S14 is unused
    @W:CL159 : coreahblite_masterstage.v(89) | Input HREADYOUT_S14 is unused
    @W:CL159 : coreahblite_masterstage.v(90) | Input HRDATA_S15 is unused
    @W:CL159 : coreahblite_masterstage.v(91) | Input HREADYOUT_S15 is unused
    @W:CL190 : FIFO_PRBS.v(68) | Optimizing register bit reg_tx_val_out to a constant 1
    @W:CL156 : CoreUART.v(111) | *Input tx_dout_reg[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
    @W:CL156 : CoreUART.v(118) | *Input fifo_empty_tx to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
    @W:CL156 : CoreUART.v(123) | *Input fifo_full_tx to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
    @W:CL159 : Tx_async.v(43) | Input tx_dout_reg is unused
    @W:CL159 : Tx_async.v(44) | Input fifo_empty is unused
    @W:CL159 : Tx_async.v(45) | Input fifo_full is unused

`