//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Mon Apr 14 10:26:10 2014
// Version: v11.3 11.3.0.112
//////////////////////////////////////////////////////////////////////

`timescale 1 ns/100 ps

// IGLOO2_Oversampling_top
module IGLOO2_Oversampling_top(
    // Inputs
    CLK0,
    DEVRST_N,
    RX,
    RXD0_N,
    RXD0_P,
    RXD1_N,
    RXD1_P,
    RXD2_N,
    RXD2_P,
    RXD3_N,
    RXD3_P,
    // Outputs
    TX,
    TXD0_N,
    TXD0_P,
    TXD1_N,
    TXD1_P,
    TXD2_N,
    TXD2_P,
    TXD3_N,
    TXD3_P,
    connect_o,
    start
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input  CLK0;
input  DEVRST_N;
input  RX;
input  RXD0_N;
input  RXD0_P;
input  RXD1_N;
input  RXD1_P;
input  RXD2_N;
input  RXD2_P;
input  RXD3_N;
input  RXD3_P;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output TX;
output TXD0_N;
output TXD0_P;
output TXD1_N;
output TXD1_P;
output TXD2_N;
output TXD2_P;
output TXD3_N;
output TXD3_P;
output connect_o;
output start;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire          CLK0;
wire          connect_o_net_0;
wire          DEVRST_N;
wire          FCCC_0_GL0;
wire          FCCC_0_GL1;
wire          FCCC_0_LOCK;
wire          IGLOO2_Oversampling_0_INIT_APB_S_PCLK;
wire          IGLOO2_Oversampling_0_INIT_APB_S_PRESET_N;
wire          IGLOO2_Oversampling_0_SDIF0_INIT_APB_PENABLE;
wire   [31:0] IGLOO2_Oversampling_0_SDIF0_INIT_APB_PRDATA;
wire          IGLOO2_Oversampling_0_SDIF0_INIT_APB_PREADY;
wire          IGLOO2_Oversampling_0_SDIF0_INIT_APB_PSELx;
wire          IGLOO2_Oversampling_0_SDIF0_INIT_APB_PSLVERR;
wire   [31:0] IGLOO2_Oversampling_0_SDIF0_INIT_APB_PWDATA;
wire          IGLOO2_Oversampling_0_SDIF0_INIT_APB_PWRITE;
wire   [5:0]  Receiver_0_error_count;
wire          Receiver_0_error_out;
wire          Receiver_0_lock;
wire          RX;
wire          RXD0_N;
wire          RXD0_P;
wire          RXD1_N;
wire          RXD1_P;
wire          RXD2_N;
wire          RXD2_P;
wire          RXD3_N;
wire          RXD3_P;
wire          SERDES_IF_0_EPCS_1_READY;
wire          SERDES_IF_0_EPCS_1_RX_CLK;
wire   [9:0]  SERDES_IF_0_EPCS_1_RX_DATA;
wire          SERDES_IF_0_EPCS_1_RX_RESET_N;
wire          SERDES_IF_0_EPCS_1_RX_VAL;
wire          SERDES_IF_0_EPCS_1_TX_CLK;
wire          SERDES_IF_0_EPCS_1_TX_RESET_N;
wire          start_net_0;
wire   [9:0]  Transmitter_0_EPCS_TX_DATA;
wire          Transmitter_0_EPCS_TX_VAL;
wire          TX_net_0;
wire          TXD0_N_net_0;
wire          TXD0_P_net_0;
wire          TXD1_N_net_0;
wire          TXD1_P_net_0;
wire          TXD2_N_net_0;
wire          TXD2_P_net_0;
wire          TXD3_N_net_0;
wire          TXD3_P_net_0;
wire          UART_INTERFACE_0_clear;
wire          UART_INTERFACE_0_genrate_err;
wire          TXD0_P_net_1;
wire          TXD0_N_net_1;
wire          TXD1_P_net_1;
wire          TXD1_N_net_1;
wire          TXD2_P_net_1;
wire          TXD2_N_net_1;
wire          TXD3_P_net_1;
wire          TXD3_N_net_1;
wire          TX_net_1;
wire          start_net_1;
wire          connect_o_net_1;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire          VCC_net;
wire          GND_net;
wire   [9:0]  EPCS_0_TX_DATA_const_net_0;
wire   [7:2]  PADDR_const_net_0;
wire   [7:0]  PWDATA_const_net_0;
wire   [19:0] EPCS_2_TX_DATA_const_net_0;
wire   [19:0] EPCS_3_TX_DATA_const_net_0;
wire   [9:0]  SGMII_TX_DATA_const_net_0;
wire   [3:0]  AXI_M_BID_const_net_0;
wire   [1:0]  AXI_M_BRESP_const_net_0;
wire   [3:0]  AXI_M_RID_const_net_0;
wire   [63:0] AXI_M_RDATA_const_net_0;
wire   [1:0]  AXI_M_RRESP_const_net_0;
wire   [3:0]  AXI_S_AWID_const_net_0;
wire   [31:0] AXI_S_AWADDR_const_net_0;
wire   [3:0]  AXI_S_AWLEN_const_net_0;
wire   [1:0]  AXI_S_AWSIZE_const_net_0;
wire   [1:0]  AXI_S_AWBURST_const_net_0;
wire   [1:0]  AXI_S_AWLOCK_const_net_0;
wire   [3:0]  AXI_S_WID_const_net_0;
wire   [7:0]  AXI_S_WSTRB_const_net_0;
wire   [63:0] AXI_S_WDATA_const_net_0;
wire   [3:0]  AXI_S_ARID_const_net_0;
wire   [31:0] AXI_S_ARADDR_const_net_0;
wire   [3:0]  AXI_S_ARLEN_const_net_0;
wire   [1:0]  AXI_S_ARSIZE_const_net_0;
wire   [1:0]  AXI_S_ARBURST_const_net_0;
wire   [1:0]  AXI_S_ARLOCK_const_net_0;
wire   [31:0] AHB_M_HRDATA_const_net_0;
wire   [31:0] AHB_S_HADDR_const_net_0;
wire   [1:0]  AHB_S_HBURST_const_net_0;
wire   [1:0]  AHB_S_HSIZE_const_net_0;
wire   [1:0]  AHB_S_HTRANS_const_net_0;
wire   [31:0] AHB_S_HWDATA_const_net_0;
wire   [4:0]  XAUI_MMD_PRTAD_const_net_0;
wire   [4:0]  XAUI_MMD_DEVID_const_net_0;
wire   [63:0] XAUI_TXD_const_net_0;
wire   [7:0]  XAUI_TXC_const_net_0;
wire   [3:0]  PCIE_INTERRUPT_const_net_0;
//--------------------------------------------------------------------
// Bus Interface Nets Declarations - Unequal Pin Widths
//--------------------------------------------------------------------
wire   [15:2] IGLOO2_Oversampling_0_SDIF0_INIT_APB_PADDR;
wire   [13:2] IGLOO2_Oversampling_0_SDIF0_INIT_APB_PADDR_0_13to2;
wire   [13:2] IGLOO2_Oversampling_0_SDIF0_INIT_APB_PADDR_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign VCC_net                    = 1'b1;
assign GND_net                    = 1'b0;
assign EPCS_0_TX_DATA_const_net_0 = 10'h000;
assign PADDR_const_net_0          = 6'h00;
assign PWDATA_const_net_0         = 8'h00;
assign EPCS_2_TX_DATA_const_net_0 = 20'h00000;
assign EPCS_3_TX_DATA_const_net_0 = 20'h00000;
assign SGMII_TX_DATA_const_net_0  = 10'h000;
assign AXI_M_BID_const_net_0      = 4'h0;
assign AXI_M_BRESP_const_net_0    = 2'h0;
assign AXI_M_RID_const_net_0      = 4'h0;
assign AXI_M_RDATA_const_net_0    = 64'h0000000000000000;
assign AXI_M_RRESP_const_net_0    = 2'h0;
assign AXI_S_AWID_const_net_0     = 4'h0;
assign AXI_S_AWADDR_const_net_0   = 32'h00000000;
assign AXI_S_AWLEN_const_net_0    = 4'h0;
assign AXI_S_AWSIZE_const_net_0   = 2'h0;
assign AXI_S_AWBURST_const_net_0  = 2'h0;
assign AXI_S_AWLOCK_const_net_0   = 2'h0;
assign AXI_S_WID_const_net_0      = 4'h0;
assign AXI_S_WSTRB_const_net_0    = 8'h00;
assign AXI_S_WDATA_const_net_0    = 64'h0000000000000000;
assign AXI_S_ARID_const_net_0     = 4'h0;
assign AXI_S_ARADDR_const_net_0   = 32'h00000000;
assign AXI_S_ARLEN_const_net_0    = 4'h0;
assign AXI_S_ARSIZE_const_net_0   = 2'h0;
assign AXI_S_ARBURST_const_net_0  = 2'h0;
assign AXI_S_ARLOCK_const_net_0   = 2'h0;
assign AHB_M_HRDATA_const_net_0   = 32'h00000000;
assign AHB_S_HADDR_const_net_0    = 32'h00000000;
assign AHB_S_HBURST_const_net_0   = 2'h0;
assign AHB_S_HSIZE_const_net_0    = 2'h0;
assign AHB_S_HTRANS_const_net_0   = 2'h0;
assign AHB_S_HWDATA_const_net_0   = 32'h00000000;
assign XAUI_MMD_PRTAD_const_net_0 = 5'h00;
assign XAUI_MMD_DEVID_const_net_0 = 5'h00;
assign XAUI_TXD_const_net_0       = 64'h0000000000000000;
assign XAUI_TXC_const_net_0       = 8'h00;
assign PCIE_INTERRUPT_const_net_0 = 4'h0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign TXD0_P_net_1    = TXD0_P_net_0;
assign TXD0_P          = TXD0_P_net_1;
assign TXD0_N_net_1    = TXD0_N_net_0;
assign TXD0_N          = TXD0_N_net_1;
assign TXD1_P_net_1    = TXD1_P_net_0;
assign TXD1_P          = TXD1_P_net_1;
assign TXD1_N_net_1    = TXD1_N_net_0;
assign TXD1_N          = TXD1_N_net_1;
assign TXD2_P_net_1    = TXD2_P_net_0;
assign TXD2_P          = TXD2_P_net_1;
assign TXD2_N_net_1    = TXD2_N_net_0;
assign TXD2_N          = TXD2_N_net_1;
assign TXD3_P_net_1    = TXD3_P_net_0;
assign TXD3_P          = TXD3_P_net_1;
assign TXD3_N_net_1    = TXD3_N_net_0;
assign TXD3_N          = TXD3_N_net_1;
assign TX_net_1        = TX_net_0;
assign TX              = TX_net_1;
assign start_net_1     = start_net_0;
assign start           = start_net_1;
assign connect_o_net_1 = connect_o_net_0;
assign connect_o       = connect_o_net_1;
//--------------------------------------------------------------------
// Bus Interface Nets Assignments - Unequal Pin Widths
//--------------------------------------------------------------------
assign IGLOO2_Oversampling_0_SDIF0_INIT_APB_PADDR_0_13to2 = IGLOO2_Oversampling_0_SDIF0_INIT_APB_PADDR[13:2];
assign IGLOO2_Oversampling_0_SDIF0_INIT_APB_PADDR_0 = { IGLOO2_Oversampling_0_SDIF0_INIT_APB_PADDR_0_13to2 };

//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------IGLOO2_Oversampling_top_FCCC_0_FCCC   -   Actel:SgCore:FCCC:2.0.200
IGLOO2_Oversampling_top_FCCC_0_FCCC FCCC_0(
        // Inputs
        .CLK0 ( CLK0 ),
        // Outputs
        .GL0  ( FCCC_0_GL0 ),
        .GL1  ( FCCC_0_GL1 ),
        .LOCK ( FCCC_0_LOCK ) 
        );

//--------IGLOO2_Oversampling
IGLOO2_Oversampling IGLOO2_Oversampling_0(
        // Inputs
        .FAB_RESET_N         ( VCC_net ),
        .SDIF0_PREADY        ( IGLOO2_Oversampling_0_SDIF0_INIT_APB_PREADY ),
        .SDIF0_PSLVERR       ( IGLOO2_Oversampling_0_SDIF0_INIT_APB_PSLVERR ),
        .DEVRST_N            ( DEVRST_N ),
        .SDIF0_SPLL_LOCK     ( VCC_net ),
        .SDIF0_PERST_N       ( VCC_net ),
        .CLK0                ( CLK0 ),
        .SDIF0_PRDATA        ( IGLOO2_Oversampling_0_SDIF0_INIT_APB_PRDATA ),
        // Outputs
        .POWER_ON_RESET_N    (  ),
        .HPMS_READY          (  ),
        .INIT_DONE           (  ),
        .SDIF0_PSEL          ( IGLOO2_Oversampling_0_SDIF0_INIT_APB_PSELx ),
        .SDIF0_PENABLE       ( IGLOO2_Oversampling_0_SDIF0_INIT_APB_PENABLE ),
        .SDIF0_PWRITE        ( IGLOO2_Oversampling_0_SDIF0_INIT_APB_PWRITE ),
        .INIT_APB_S_PCLK     ( IGLOO2_Oversampling_0_INIT_APB_S_PCLK ),
        .INIT_APB_S_PRESET_N ( IGLOO2_Oversampling_0_INIT_APB_S_PRESET_N ),
        .SDIF0_PHY_RESET_N   (  ),
        .SDIF0_CORE_RESET_N  (  ),
        .FAB_CCC_GL0         (  ),
        .FAB_CCC_GL3         (  ),
        .COMM_BLK_INT        (  ),
        .SDIF0_PADDR         ( IGLOO2_Oversampling_0_SDIF0_INIT_APB_PADDR ),
        .SDIF0_PWDATA        ( IGLOO2_Oversampling_0_SDIF0_INIT_APB_PWDATA ),
        .HPMS_INT_M2F        (  ) 
        );

//--------Receiver
Receiver Receiver_0(
        // Inputs
        .EPCS_RX_VAL   ( SERDES_IF_0_EPCS_1_RX_VAL ),
        .EPCS_RX_READY ( SERDES_IF_0_EPCS_1_READY ),
        .EPCS_RX_CLK   ( SERDES_IF_0_EPCS_1_RX_CLK ),
        .CLEAR         ( UART_INTERFACE_0_clear ),
        .EPCS_RX_RESET ( SERDES_IF_0_EPCS_1_RX_RESET_N ),
        .START         ( start_net_0 ),
        .EPCS_RX_DATA  ( SERDES_IF_0_EPCS_1_RX_DATA ),
        // Outputs
        .lock          ( Receiver_0_lock ),
        .error_out     ( Receiver_0_error_out ),
        .error_count   ( Receiver_0_error_count ) 
        );

//--------IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF   -   Actel:SgCore:SERDES_IF:1.2.005
IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF SERDES_IF_0(
        // Inputs
        .EPCS_0_PWRDN         ( GND_net ),
        .EPCS_1_PWRDN         ( GND_net ),
        .EPCS_0_TX_VAL        ( GND_net ),
        .EPCS_1_TX_VAL        ( Transmitter_0_EPCS_TX_VAL ),
        .EPCS_0_TX_OOB        ( GND_net ),
        .EPCS_1_TX_OOB        ( GND_net ),
        .EPCS_0_RX_ERR        ( GND_net ),
        .EPCS_1_RX_ERR        ( GND_net ),
        .EPCS_0_RESET_N       ( IGLOO2_Oversampling_0_INIT_APB_S_PRESET_N ),
        .EPCS_1_RESET_N       ( IGLOO2_Oversampling_0_INIT_APB_S_PRESET_N ),
        .APB_S_PENABLE        ( IGLOO2_Oversampling_0_SDIF0_INIT_APB_PENABLE ),
        .APB_S_PSEL           ( IGLOO2_Oversampling_0_SDIF0_INIT_APB_PSELx ),
        .APB_S_PWRITE         ( IGLOO2_Oversampling_0_SDIF0_INIT_APB_PWRITE ),
        .APB_S_PRESET_N       ( IGLOO2_Oversampling_0_INIT_APB_S_PRESET_N ),
        .APB_S_PCLK           ( IGLOO2_Oversampling_0_INIT_APB_S_PCLK ),
        .EPCS_FAB_REF_CLK     ( FCCC_0_GL1 ),
        .RXD0_P               ( RXD0_P ),
        .RXD0_N               ( RXD0_N ),
        .RXD1_P               ( RXD1_P ),
        .RXD1_N               ( RXD1_N ),
        .RXD2_P               ( RXD2_P ),
        .RXD2_N               ( RXD2_N ),
        .RXD3_P               ( RXD3_P ),
        .RXD3_N               ( RXD3_N ),
        .EPCS_0_TX_DATA       ( EPCS_0_TX_DATA_const_net_0 ),
        .EPCS_1_TX_DATA       ( Transmitter_0_EPCS_TX_DATA ),
        .APB_S_PADDR          ( IGLOO2_Oversampling_0_SDIF0_INIT_APB_PADDR_0 ),
        .APB_S_PWDATA         ( IGLOO2_Oversampling_0_SDIF0_INIT_APB_PWDATA ),
        // Outputs
        .EPCS_0_READY         (  ),
        .EPCS_1_READY         ( SERDES_IF_0_EPCS_1_READY ),
        .EPCS_0_RX_VAL        (  ),
        .EPCS_1_RX_VAL        ( SERDES_IF_0_EPCS_1_RX_VAL ),
        .EPCS_0_RX_IDLE       (  ),
        .EPCS_1_RX_IDLE       (  ),
        .EPCS_0_TX_CLK_STABLE (  ),
        .EPCS_1_TX_CLK_STABLE (  ),
        .EPCS_0_RX_RESET_N    (  ),
        .EPCS_1_RX_RESET_N    ( SERDES_IF_0_EPCS_1_RX_RESET_N ),
        .EPCS_0_TX_RESET_N    (  ),
        .EPCS_1_TX_RESET_N    ( SERDES_IF_0_EPCS_1_TX_RESET_N ),
        .EPCS_0_RX_CLK        (  ),
        .EPCS_1_RX_CLK        ( SERDES_IF_0_EPCS_1_RX_CLK ),
        .EPCS_0_TX_CLK        (  ),
        .EPCS_1_TX_CLK        ( SERDES_IF_0_EPCS_1_TX_CLK ),
        .APB_S_PREADY         ( IGLOO2_Oversampling_0_SDIF0_INIT_APB_PREADY ),
        .APB_S_PSLVERR        ( IGLOO2_Oversampling_0_SDIF0_INIT_APB_PSLVERR ),
        .TXD0_P               ( TXD0_P_net_0 ),
        .TXD0_N               ( TXD0_N_net_0 ),
        .TXD1_P               ( TXD1_P_net_0 ),
        .TXD1_N               ( TXD1_N_net_0 ),
        .TXD2_P               ( TXD2_P_net_0 ),
        .TXD2_N               ( TXD2_N_net_0 ),
        .TXD3_P               ( TXD3_P_net_0 ),
        .TXD3_N               ( TXD3_N_net_0 ),
        .EPCS_0_RX_DATA       (  ),
        .EPCS_1_RX_DATA       ( SERDES_IF_0_EPCS_1_RX_DATA ),
        .APB_S_PRDATA         ( IGLOO2_Oversampling_0_SDIF0_INIT_APB_PRDATA ) 
        );

//--------Transmitter
Transmitter Transmitter_0(
        // Inputs
        .Error_Inject_i ( UART_INTERFACE_0_genrate_err ),
        .EPCS_TX_RESET  ( SERDES_IF_0_EPCS_1_TX_RESET_N ),
        .EPCS_TX_CLK    ( SERDES_IF_0_EPCS_1_TX_CLK ),
        .START          ( start_net_0 ),
        // Outputs
        .EPCS_TX_VAL    ( Transmitter_0_EPCS_TX_VAL ),
        .EPCS_TX_DATA   ( Transmitter_0_EPCS_TX_DATA ) 
        );

//--------UART_INTERFACE
UART_INTERFACE UART_INTERFACE_0(
        // Inputs
        .CLK         ( FCCC_0_GL0 ),
        .RX          ( RX ),
        .RESET_N     ( FCCC_0_LOCK ),
        .EPCS_RX_VAL ( SERDES_IF_0_EPCS_1_RX_VAL ),
        .rx_lock     ( Receiver_0_lock ),
        .rx_error    ( Receiver_0_error_out ),
        .error_count ( Receiver_0_error_count ),
        // Outputs
        .TX          ( TX_net_0 ),
        .clear       ( UART_INTERFACE_0_clear ),
        .genrate_err ( UART_INTERFACE_0_genrate_err ),
        .connect_o   ( connect_o_net_0 ),
        .start       ( start_net_0 ) 
        );


endmodule
