@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 
@N: BN362 :"c:\microsemi\igloo2_oversampling\hdl\prbs_gencheck.v":92:2:92:7|Removing sequential instance tx_count[2:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.prbs7_10_prbs7_10_0(verilog) because there are no references to its outputs 
@N: BN362 :"c:\microsemi\igloo2_oversampling\hdl\prbs_gencheck.v":92:2:92:7|Removing sequential instance rx_count[2:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.prbs7_10_prbs7_10_0_0(verilog) because there are no references to its outputs 
@N: BN362 :"c:\microsemi\igloo2_oversampling\hdl\prbs_gencheck.v":183:2:183:7|Removing sequential instance reg_error[5:0] of view:PrimLib.dffr(prim) in hierarchy view:work.prbs7_10_prbs7_10_0_0(verilog) because there are no references to its outputs 
@N: BN362 :"c:\microsemi\igloo2_oversampling\component\work\uart_interface\coreuart_0\rtl\vlog\core\rx_async.v":379:0:379:5|Removing sequential instance rx_parity_calc of view:PrimLib.dffre(prim) in hierarchy view:work.UART_INTERFACE_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs 
@N: BN362 :"c:\microsemi\igloo2_oversampling\hdl\fabuart.v":91:0:91:5|Removing sequential instance switch_t of view:PrimLib.dffre(prim) in hierarchy view:work.FabUART(verilog) because there are no references to its outputs 
@N: BN362 :"c:\microsemi\igloo2_oversampling\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] in hierarchy view:work.IGLOO2_Oversampling(verilog) because there are no references to its outputs 
@N: BN362 :"c:\microsemi\igloo2_oversampling\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[3] in hierarchy view:work.IGLOO2_Oversampling(verilog) because there are no references to its outputs 
@N: BN362 :"c:\microsemi\igloo2_oversampling\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[2] in hierarchy view:work.IGLOO2_Oversampling(verilog) because there are no references to its outputs 
@N: BN362 :"c:\microsemi\igloo2_oversampling\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[1] in hierarchy view:work.IGLOO2_Oversampling(verilog) because there are no references to its outputs 
@N: BN362 :"c:\microsemi\igloo2_oversampling\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":233:0:233:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[0] in hierarchy view:work.IGLOO2_Oversampling(verilog) because there are no references to its outputs 
@N: BN362 :"c:\microsemi\igloo2_oversampling\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":233:0:233:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[2] in hierarchy view:work.IGLOO2_Oversampling(verilog) because there are no references to its outputs 
@N: BN362 :"c:\microsemi\igloo2_oversampling\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":233:0:233:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[4] in hierarchy view:work.IGLOO2_Oversampling(verilog) because there are no references to its outputs 
@N: BN362 :"c:\microsemi\igloo2_oversampling\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":233:0:233:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[6] in hierarchy view:work.IGLOO2_Oversampling(verilog) because there are no references to its outputs 
@N: MF179 :"c:\microsemi\igloo2_oversampling\component\actel\directcore\coreconfigmaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":509:21:509:46|Found 32 bit by 32 bit '==' comparator, 'd_state128'
@N: BN362 :"c:\microsemi\igloo2_oversampling\component\actel\directcore\coreconfigmaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":541:4:541:9|Removing sequential instance HSIZE[2] in hierarchy view:work.CoreConfigMaster_Z1(verilog) because there are no references to its outputs 
@N: BN362 :"c:\microsemi\igloo2_oversampling\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":241:4:241:9|Removing sequential instance paddr[16] in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"c:\microsemi\igloo2_oversampling\hdl\prbs_gencheck.v":92:2:92:7|Removing sequential instance LFSR[8] in hierarchy view:work.prbs7_10_prbs7_10_0(verilog) because there are no references to its outputs 
@N: BN362 :"c:\microsemi\igloo2_oversampling\hdl\prbs_gencheck.v":92:2:92:7|Removing sequential instance LFSR[9] in hierarchy view:work.prbs7_10_prbs7_10_0(verilog) because there are no references to its outputs 
@N: BN362 :"c:\microsemi\igloo2_oversampling\hdl\prbs_gencheck.v":92:2:92:7|Removing sequential instance LFSR[10] in hierarchy view:work.prbs7_10_prbs7_10_0(verilog) because there are no references to its outputs 
@N: MF179 :"c:\microsemi\igloo2_oversampling\hdl\prbs_gencheck.v":188:118:188:131|Found 10 bit by 10 bit '==' comparator, 'un1_data_in'
@N: BN362 :"c:\microsemi\igloo2_oversampling\component\work\uart_interface\coreuart_0\rtl\vlog\core\coreuart.v":154:0:154:5|Removing sequential instance tx_hold_reg[6] in hierarchy view:work.UART_INTERFACE_COREUART_0_COREUART_0s_0s_0s_19s_0s(verilog) because there are no references to its outputs 
@N: BN362 :"c:\microsemi\igloo2_oversampling\component\work\uart_interface\coreuart_0\rtl\vlog\core\tx_async.v":332:0:332:5|Removing sequential instance tx_parity in hierarchy view:work.UART_INTERFACE_COREUART_0_Tx_async_0s_0s_1s_2s_3s_4s_5s_6s(verilog) because there are no references to its outputs 
@N: BN362 :"c:\microsemi\igloo2_oversampling\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28] in hierarchy view:work.IGLOO2_Oversampling_top(verilog) because there are no references to its outputs 
@N: BN362 :"c:\microsemi\igloo2_oversampling\component\work\uart_interface\coreuart_0\rtl\vlog\core\tx_async.v":112:0:112:5|Removing sequential instance UART_INTERFACE_0.COREUART_0.make_TX.tx_byte[6] in hierarchy view:work.IGLOO2_Oversampling_top(verilog) because there are no references to its outputs 
@N: BN362 :"c:\microsemi\igloo2_oversampling\component\work\uart_interface\coreuart_0\rtl\vlog\core\rx_async.v":335:0:335:5|Removing sequential instance UART_INTERFACE_0.COREUART_0.make_RX.rx_shift[8] in hierarchy view:work.IGLOO2_Oversampling_top(verilog) because there are no references to its outputs 
@N: BN362 :"c:\microsemi\igloo2_oversampling\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing sequential instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11] in hierarchy view:work.IGLOO2_Oversampling_top(verilog) because there are no references to its outputs 
@N: FX404 :"c:\microsemi\igloo2_oversampling\component\actel\directcore\coreconfigmaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":147:8:147:11|Found addmux in view:work.IGLOO2_Oversampling_top(verilog) inst IGLOO2_Oversampling_0.ConfigMaster_0.d_bytecount_0[15:0] from IGLOO2_Oversampling_0.ConfigMaster_0.un1_bytecount_16[15:0] 
@N: BN362 :"c:\microsemi\igloo2_oversampling\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing sequential instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[6] in hierarchy view:work.IGLOO2_Oversampling_top(verilog) because there are no references to its outputs 
@N: BN362 :"c:\microsemi\igloo2_oversampling\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing sequential instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[5] in hierarchy view:work.IGLOO2_Oversampling_top(verilog) because there are no references to its outputs 
@N: FX271 :"c:\microsemi\igloo2_oversampling\component\actel\directcore\coreconfigmaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":541:4:541:9|Instance "IGLOO2_Oversampling_0.ConfigMaster_0.HADDR[0]" with 5 loads replicated 1 times to improve timing 
@N: FP130 |Promoting Net SERDES_IF_0_EPCS_1_TX_CLK on CLKINT  I_134 
@N: FP130 |Promoting Net IGLOO2_Oversampling_0_INIT_APB_S_PCLK on CLKINT  I_135 
@N: FP130 |Promoting Net IGLOO2_Oversampling_0_INIT_APB_S_PRESET_N on CLKINT  I_136 
@N: FP130 |Promoting Net SERDES_IF_0_EPCS_1_RX_CLK on CLKINT  I_137 
@N: FP130 |Promoting Net IGLOO2_Oversampling_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT  I_138 
@N: FP130 |Promoting Net IGLOO2_Oversampling_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT  I_139 
@N: FP130 |Promoting Net Receiver_0.AND3_0_Y on CLKINT  I_140 
@N: FP130 |Promoting Net Transmitter_0.EPCS_TX_RESET_net_0 on CLKINT  I_141 
@N: FP130 |Promoting Net FCCC_0_LOCK on CLKINT  I_142 
@N: FP130 |Promoting Net IGLOO2_Oversampling_0.HPMS_READY_i_0_i on CLKINT  I_143 
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
