//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Fri Mar 28 16:08:33 2014
// Version: v11.3 11.3.0.112
//////////////////////////////////////////////////////////////////////

`timescale 1 ns/100 ps

// UART_INTERFACE
module UART_INTERFACE(
    // Inputs
    CLK,
    EPCS_RX_VAL,
    RESET_N,
    RX,
    error_count,
    rx_error,
    rx_lock,
    // Outputs
    TX,
    clear,
    connect_o,
    genrate_err,
    start
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input        CLK;
input        EPCS_RX_VAL;
input        RESET_N;
input        RX;
input  [5:0] error_count;
input        rx_error;
input        rx_lock;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output       TX;
output       clear;
output       connect_o;
output       genrate_err;
output       start;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire         clear_net_0;
wire         CLK;
wire         connect_o_net_0;
wire   [7:0] COREUART_0_DATA_OUT;
wire         COREUART_0_RXRDY;
wire         COREUART_0_TXRDY;
wire         EPCS_RX_VAL;
wire   [5:0] error_count;
wire   [7:0] FabUART_0_uart_data_out;
wire         FabUART_0_uart_oen;
wire         FabUART_0_uart_wen;
wire         genrate_err_net_0;
wire         RESET_N;
wire         RX;
wire         rx_error;
wire         rx_lock;
wire         start_net_0;
wire         TX_net_0;
wire         TX_net_1;
wire         clear_net_1;
wire         genrate_err_net_1;
wire         connect_o_net_1;
wire         start_net_1;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire   [12:0]BAUD_VAL_const_net_0;
wire         VCC_net;
wire         GND_net;
wire   [2:0] BAUD_VAL_FRACTION_const_net_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign BAUD_VAL_const_net_0          = 13'h0144;
assign VCC_net                       = 1'b1;
assign GND_net                       = 1'b0;
assign BAUD_VAL_FRACTION_const_net_0 = 3'h0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign TX_net_1          = TX_net_0;
assign TX                = TX_net_1;
assign clear_net_1       = clear_net_0;
assign clear             = clear_net_1;
assign genrate_err_net_1 = genrate_err_net_0;
assign genrate_err       = genrate_err_net_1;
assign connect_o_net_1   = connect_o_net_0;
assign connect_o         = connect_o_net_1;
assign start_net_1       = start_net_0;
assign start             = start_net_1;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------UART_INTERFACE_COREUART_0_COREUART   -   Actel:DirectCore:COREUART:5.2.2
UART_INTERFACE_COREUART_0_COREUART #( 
        .BAUD_VAL_FRCTN_EN ( 0 ),
        .FAMILY            ( 19 ),
        .RX_FIFO           ( 0 ),
        .RX_LEGACY_MODE    ( 0 ),
        .TX_FIFO           ( 0 ) )
COREUART_0(
        // Inputs
        .BAUD_VAL          ( BAUD_VAL_const_net_0 ),
        .BIT8              ( VCC_net ),
        .CLK               ( CLK ),
        .CSN               ( GND_net ),
        .DATA_IN           ( FabUART_0_uart_data_out ),
        .ODD_N_EVEN        ( GND_net ),
        .OEN               ( FabUART_0_uart_oen ),
        .PARITY_EN         ( GND_net ),
        .RESET_N           ( RESET_N ),
        .RX                ( RX ),
        .WEN               ( FabUART_0_uart_wen ),
        .BAUD_VAL_FRACTION ( BAUD_VAL_FRACTION_const_net_0 ), // tied to 3'h0 from definition
        // Outputs
        .DATA_OUT          ( COREUART_0_DATA_OUT ),
        .OVERFLOW          (  ),
        .PARITY_ERR        (  ),
        .RXRDY             ( COREUART_0_RXRDY ),
        .TX                ( TX_net_0 ),
        .TXRDY             ( COREUART_0_TXRDY ),
        .FRAMING_ERR       (  ) 
        );

//--------FabUART
FabUART FabUART_0(
        // Inputs
        .clk           ( CLK ),
        .reset         ( RESET_N ),
        .uart_txrdy    ( COREUART_0_TXRDY ),
        .uart_rxrdy    ( COREUART_0_RXRDY ),
        .rx_val        ( EPCS_RX_VAL ),
        .rx_lock       ( rx_lock ),
        .rx_error      ( rx_error ),
        .uart_data_in  ( COREUART_0_DATA_OUT ),
        .error_count   ( error_count ),
        // Outputs
        .uart_wen      ( FabUART_0_uart_wen ),
        .uart_oen      ( FabUART_0_uart_oen ),
        .start         ( start_net_0 ),
        .switch        (  ),
        .clear         ( clear_net_0 ),
        .genrate_err   ( genrate_err_net_0 ),
        .connect_o     ( connect_o_net_0 ),
        .timer_switch  (  ),
        .uart_data_out ( FabUART_0_uart_data_out ) 
        );


endmodule
