#--  Synopsys, Inc.
#--  Version I-2013.09M-SP1 
#--  Project file C:\Microsemi\IGLOO2_Oversampling\synthesis\run_options.txt
#--  Written on Fri Apr 18 09:30:48 2014


#project files
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/component/work/IGLOO2_Oversampling_top/FCCC_0/IGLOO2_Oversampling_top_FCCC_0_FCCC.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/component/work/IGLOO2_Oversampling/CCC_0/IGLOO2_Oversampling_CCC_0_FCCC.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/component/Actel/DirectCore/CoreConfigMaster/2.0.101/rtl/vlog/core/coreconfigmaster.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/component/Actel/DirectCore/CoreConfigP/5.0.101/rtl/vlog/core/coreconfigp.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/component/Actel/DirectCore/CoreResetP/5.1.100/rtl/vlog/core/coreresetp_pcie_hotreset.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/component/Actel/DirectCore/CoreResetP/5.1.100/rtl/vlog/core/coreresetp.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/component/Actel/SgCore/OSC/1.0.100/osc_comps.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/component/work/IGLOO2_Oversampling/FABOSC_0/IGLOO2_Oversampling_FABOSC_0_OSC.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/component/work/IGLOO2_Oversampling_HPMS/IGLOO2_Oversampling_HPMS_syn.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/component/work/IGLOO2_Oversampling_HPMS/IGLOO2_Oversampling_HPMS.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/Microsemi/IGLOO2_Oversampling/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_addrdec.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/Microsemi/IGLOO2_Oversampling/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_defaultslavesm.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/Microsemi/IGLOO2_Oversampling/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_masterstage.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/Microsemi/IGLOO2_Oversampling/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_slavearbiter.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/Microsemi/IGLOO2_Oversampling/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_slavestage.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/Microsemi/IGLOO2_Oversampling/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_matrix4x16.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/Microsemi/IGLOO2_Oversampling/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/component/work/IGLOO2_Oversampling/IGLOO2_Oversampling.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/hdl/Downsampler_Rx.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/hdl/PRBS_GenCheck.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/hdl/rx_data_aligner.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/hdl/receive_control.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/hdl/receive_buffer_top.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/component/work/Receiver/Receiver.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/component/work/IGLOO2_Oversampling_top/SERDES_IF_0/IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF_syn.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/component/work/IGLOO2_Oversampling_top/SERDES_IF_0/IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/hdl/FIFO_PRBS.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/hdl/Replicator_Tx.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/component/work/Transmitter/Transmitter.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/component/work/UART_INTERFACE/COREUART_0/rtl/vlog/core/Clock_gen.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/component/work/UART_INTERFACE/COREUART_0/rtl/vlog/core/Tx_async.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/component/work/UART_INTERFACE/COREUART_0/rtl/vlog/core/Rx_async.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/component/work/UART_INTERFACE/COREUART_0/rtl/vlog/core/fifo_256x8_smartfusion2.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/component/work/UART_INTERFACE/COREUART_0/rtl/vlog/core/CoreUART.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/hdl/FabUART.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/component/work/UART_INTERFACE/UART_INTERFACE.v"
add_file -verilog "C:/Microsemi/IGLOO2_Oversampling/component/work/IGLOO2_Oversampling_top/IGLOO2_Oversampling_top.v"



#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology IGLOO2
set_option -part M2GL010T
set_option -package FBGA484
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "IGLOO2_Oversampling_top"

# mapper_options
set_option -frequency 100
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1

# actel_options
set_option -RWCheckOnRam 0

# Microsemi G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -opcond COMWC
set_option -retiming 0
set_option -report_path 0
set_option -update_models_cp 0
set_option -preserve_registers 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./IGLOO2_Oversampling_top.edn"
impl -active "synthesis"
