#-- Synplicity, Inc.
#-- Version 9.0
#-- Project file D:\actel_ip\GPIO_EXPANSION_USING_UART\igloo\uart2gpio\synthesis\run_options.txt
#-- Written on Wed Sep 17 13:03:31 2008


#add_file options
add_file -vhdl -lib work "D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/smartgen/reset_buffer/reset_buffer.vhd"
add_file -vhdl -lib work "D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/smartgen/pll20mhz/pll20mhz.vhd"
add_file -vhdl -lib COREUART_LIB "D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/Clock_gen.vhd"
add_file -vhdl -lib COREUART_LIB "D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/Tx_async.vhd"
add_file -vhdl -lib COREUART_LIB "D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/Rx_async.vhd"
add_file -vhdl -lib COREUART_LIB "D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/CoreUART.vhd"
add_file -vhdl -lib COREUART_LIB "D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/components.vhd"
add_file -vhdl -lib work "D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/uart/uart.vhd"
add_file -vhdl -lib work "D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/hdl/dff_wth_enb.vhd"
add_file -vhdl -lib work "D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/hdl/bdir_buff.vhd"
add_file -vhdl -lib work "D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/hdl/uart2gpio.vhd"


#implementation: "synthesis"
impl -add synthesis -type fpga

#device options
set_option -technology IGLOO
set_option -part M1AGL600V2
set_option -speed_grade Std

#compilation/mapping options
set_option -default_enum_encoding default
set_option -resource_sharing 1
set_option -top_module "work.uart2gpio"

#map options
set_option -frequency 100.000
set_option -run_prop_extract 1
set_option -fanout_limit 12
set_option -globalthreshold 50
set_option -maxfan_hard 0
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -report_path 4000
set_option -opcond COMWC
set_option -update_models_cp 0
set_option -preserve_registers 0


#sequential_optimizations options
set_option -symbolic_fsm_compiler 1

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_format "edif"
project -result_file "./uart2gpio.edn"
impl -active "synthesis"
