m255
K3
13
cModel Technology
Z0 dD:\actel_ip\GPIO_EXPANSION_USING_UART\igloo\uart2gpio\simulation
Ebidir_buff
Z1 w1216274546
Z2 DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
Z3 8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/hdl/bdir_buff.vhd
Z4 FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/hdl/bdir_buff.vhd
l0
L6
V`h0zlk`NN@0OoDll?CG9L3
Z5 OW;C;6.3c;37
31
Z6 o-work work -O0
Z7 tExplicit 1 NoCoverage 1 CoverOpt 2
Abidir_buff_arch
R2
DE work bidir_buff `h0zlk`NN@0OoDll?CG9L3
l26
L25
VoLP@9feU20n[<TWFoOJcH0
R5
31
Z8 M1 ieee std_logic_1164
R6
R7
Eclock_gen
Z9 w1217911496
Z10 DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
Z11 DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
R2
Z12 8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/Clock_gen.vhd
Z13 FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/Clock_gen.vhd
l0
L10
VmLFKXzBhd?YMXJT5?<eNC3
R5
31
R6
R7
Acuarto
R10
R11
R2
DE work clock_gen mLFKXzBhd?YMXJT5?<eNC3
l28
L18
VZZl>bnHd[ghckAk=0n=b92
R5
31
Z14 M3 ieee std_logic_1164
Z15 M2 ieee std_logic_arith
Z16 M1 ieee std_logic_unsigned
R6
R7
Pcomponents
R10
R11
R2
R9
8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/components.vhd
FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/components.vhd
l0
L34
Vn0Jb88lODiB6Ba0hFJ[P>0
R5
31
R14
R15
R16
R6
R7
Pcoreparameters
R9
8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/coreparameters.vhd
FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/coreparameters.vhd
l0
L5
VHI3]aO[CX`1NJ6Jmn?mCN3
R5
31
R6
R7
Ecoreuart
R9
R10
R11
R2
Z17 8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/CoreUART.vhd
Z18 FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/CoreUART.vhd
l0
L10
V[G@=ljJiRhIz^BU`NgKFd3
R5
31
R6
R7
Atranslated
R10
R11
R2
DE work coreuart [G@=ljJiRhIz^BU`NgKFd3
l191
L32
VnfBB0`Gok[cjd5HMbIAP<2
R5
31
R14
R15
R16
R6
R7
Edff_ck_en
Z19 w1216975555
R2
Z20 8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/hdl/dff_wth_enb.vhd
Z21 FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/hdl/dff_wth_enb.vhd
l0
L6
V[b8<IfL]2`MmLf`WI3lkR2
R5
31
R6
R7
Abehav
R2
DE work dff_ck_en [b8<IfL]2`MmLf`WI3lkR2
l24
L22
V0@g@hz53FkOoVUakh=T?h1
R5
31
R8
R6
R7
Epll20mhz
Z22 w1221566683
R2
Z23 8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/smartgen/pll20mhz/pll20mhz.vhd
Z24 FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/smartgen/pll20mhz/pll20mhz.vhd
l0
L8
VY7]ho6nR>efOVQ:2L<^0]2
R5
31
R6
R7
Adef_arch
R2
DE work pll20mhz Y7]ho6nR>efOVQ:2L<^0]2
l48
L14
VMM3`kb0ZPI<^`dL]^@FI`0
R5
31
R8
R6
R7
Ereset_buffer
Z25 w1219312822
R2
Z26 8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/smartgen/reset_buffer/reset_buffer.vhd
Z27 FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/smartgen/reset_buffer/reset_buffer.vhd
l0
L8
Vnc^C3GZfaIE0ICVC[CNlM3
R5
31
R6
R7
Adef_arch
R2
DE work reset_buffer nc^C3GZfaIE0ICVC[CNlM3
l19
L13
V;NUFnHUEe^Q_CS>h4PW4d3
R5
31
R8
R6
R7
Erx_async
R9
R10
R11
R2
Z28 8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/Rx_async.vhd
Z29 FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/Rx_async.vhd
l0
L10
V1ADYfVb;<G?njQH0RBe2O0
R5
31
R6
R7
Atranslated
R10
R11
R2
DE work rx_async 1ADYfVb;<G?njQH0RBe2O0
l74
L28
V^]bKnWIZJBAj;oGI5HKYD1
R5
31
R14
R15
R16
R6
R7
Etx_async
R9
R10
R11
R2
Z30 8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/Tx_async.vhd
Z31 FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/Tx_async.vhd
l0
L10
V]ZCG^HlAERXb6ng9iAXmE3
R5
31
R6
R7
Atranslated
R10
R11
R2
DE work tx_async ]ZCG^HlAERXb6ng9iAXmE3
l81
L27
V?Wo[T[Dd_<B2?>B`;hPTg0
R5
31
R14
R15
R16
R6
R7
Euart
R9
R10
R11
Z32 DP coreuart_lib components `fFXblo50o:3QchifOA0M3
R2
Z33 8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/uart/uart.vhd
Z34 FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/uart/uart.vhd
l0
L19
V]i2=2CJlFTLJjPQoj8WW?2
R5
31
R6
R7
Artl
R10
R11
R32
R2
DE work uart ]i2=2CJlFTLJjPQoj8WW?2
l86
L48
VznHO_Y>W`N;VD?YVK4IQ_3
R5
31
Z35 M4 ieee std_logic_1164
M3 coreuart_lib components
R15
R16
R6
R7
Euart2gpio
Z36 w1221568444
R11
R10
R2
Z37 8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/hdl/uart2gpio.vhd
Z38 FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/hdl/uart2gpio.vhd
l0
L42
V0GlLGR3m`<LJYX]Y]hVQC3
R5
31
R6
R7
Auart2gpio_arch
R11
R10
R2
DE work uart2gpio 0GlLGR3m`<LJYX]Y]hVQC3
l174
L64
VPj1WTod@JC>38``=JO^El3
R5
31
R14
M2 ieee std_logic_unsigned
Z39 M1 ieee std_logic_arith
R6
R7
Euart2gpio_tb
Z40 w1221636499
Z41 DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
R11
R10
R2
Z42 8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/hdl/uart2gpio_tb.vhd
Z43 FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/hdl/uart2gpio_tb.vhd
l0
L42
VXk5`O5SjD8V:6HM7UAZBF1
R5
31
R6
R7
Auart2gpio_tb_archi
R41
R11
R10
R2
Z44 DE work uart2gpio_tb Xk5`O5SjD8V:6HM7UAZBF1
l77
L50
VPBm6TDHj=cGoDn8UA7R1i3
R5
31
R35
Z45 M3 ieee std_logic_unsigned
R15
Z46 M1 ieee numeric_std
R6
R7
