m255
K3
13
cModel Technology
Z0 dD:\actel_ip\GPIO_EXPANSION_USING_UART\igloo\uart2gpio\simulation
Ebidir_buff
Z1 w1216274546
Z2 DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
Z3 8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/hdl/bdir_buff.vhd
Z4 FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/hdl/bdir_buff.vhd
l0
L6
VLOV@]ahG]II8_9AFAh^z=2
Z5 OW;C;6.3c;37
31
Z6 o-93 -explicit -work presynth -O0
Z7 tExplicit 1 NoCoverage 1 CoverOpt 2
Abidir_buff_arch
R2
DE work bidir_buff LOV@]ahG]II8_9AFAh^z=2
l26
L25
VXaUAGbi]:P_U36@H[D0IG2
R5
31
Z8 M1 ieee std_logic_1164
R6
R7
Edff_ck_en
Z9 w1216975555
R2
Z10 8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/hdl/dff_wth_enb.vhd
Z11 FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/hdl/dff_wth_enb.vhd
l0
L6
V^N=AYg[hP1]jJf__Il[7X1
R5
31
R6
R7
Abehav
R2
DE work dff_ck_en ^N=AYg[hP1]jJf__Il[7X1
l24
L22
VEaWbjFnGaYX]PjZSUDahV1
R5
31
R8
R6
R7
Epll20mhz
Z12 w1221566683
R2
Z13 8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/smartgen/pll20mhz/pll20mhz.vhd
Z14 FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/smartgen/pll20mhz/pll20mhz.vhd
l0
L8
VBN>^b=dUFV:9hN9_5KWlY3
R5
31
R6
R7
Adef_arch
R2
DE work pll20mhz BN>^b=dUFV:9hN9_5KWlY3
l48
L14
V<^MW`QcnW[G:YaMbY8O^f2
R5
31
R8
R6
R7
Ereset_buffer
Z15 w1219312822
R2
Z16 8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/smartgen/reset_buffer/reset_buffer.vhd
Z17 FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/smartgen/reset_buffer/reset_buffer.vhd
l0
L8
VL@md@O0c^YbjG[d2;H^G@1
R5
31
R6
R7
Adef_arch
R2
DE work reset_buffer L@md@O0c^YbjG[d2;H^G@1
l19
L13
VmUh9WiAEVD568<_7df:DH2
R5
31
R8
R6
R7
Euart
Z18 w1217911496
Z19 DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
Z20 DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
Z21 DP coreuart_lib components `fFXblo50o:3QchifOA0M3
R2
Z22 8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/uart/uart.vhd
Z23 FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/uart/uart.vhd
l0
L19
V4oiUVGQBDCQbE5?NHQhAS0
R5
31
R6
R7
Artl
R19
R20
R21
R2
DE work uart 4oiUVGQBDCQbE5?NHQhAS0
l86
L48
VF6<cM=l6nT2XEW<8da92j2
R5
31
M4 ieee std_logic_1164
M3 coreuart_lib components
M2 ieee std_logic_arith
M1 ieee std_logic_unsigned
R6
R7
Euart2gpio
Z24 w1221566759
R20
R19
R2
Z25 8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/hdl/uart2gpio.vhd
Z26 FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/hdl/uart2gpio.vhd
l0
L48
V?l:]e7N1TojMI]Od`mK=H0
R5
31
R6
R7
Auart2gpio_arch
R20
R19
R2
Z27 DE work uart2gpio ?l:]e7N1TojMI]Od`mK=H0
l180
L70
Z28 VVGMiEzM`GeV2cFiPLz1U02
R5
31
Z29 M3 ieee std_logic_1164
Z30 M2 ieee std_logic_unsigned
Z31 M1 ieee std_logic_arith
R6
R7
