m255
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13
Z0 cModel Technology
Z1 dD:\actel_ip\GPIO_EXPANSION_USING_UART\igloo\uart2gpio\simulation
Eclock_gen
Z2 w1221568581
Z3 DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
Z4 8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/synthesis/uart2gpio.vhd
Z5 FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/synthesis/uart2gpio.vhd
l0
L1486
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Z6 OW;C;6.3c;37
31
Z7 o-93 -explicit -work postsynth -O0
Z8 tExplicit 1 NoCoverage 1 CoverOpt 2
Adef_arch
R3
Z9 DE work clock_gen ZM2`BJkQZXJBh=mMKVEc;1
l1743
L1509
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R6
31
Z10 M1 ieee std_logic_1164
R7
R8
Ecoreuart
R2
R3
R4
R5
l0
L2064
VUP=g_8>D=P5<dL8m?0PAo1
R6
31
R7
R8
Adef_arch
R9
Z11 DE work rx_async Oe_I[;eo2RDW]V@GZzk`k2
Z12 DE work tx_async QX[>Jf2XTEa;JEcR@1W@i3
R3
Z13 DE work coreuart UP=g_8>D=P5<dL8m?0PAo1
l2181
L2080
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R6
31
R10
R7
R8
Edff_ck_en
R2
R3
R4
R5
l0
L430
V7LUYTBR4H]bV:0XgH]D]f2
R6
31
R7
R8
Adef_arch
R3
Z14 DE work dff_ck_en 7LUYTBR4H]bV:0XgH]D]f2
l464
L441
Vz`:zjClIC]fMA^gSDWiSn1
R6
31
R10
R7
R8
Edff_ck_en_1
R2
R3
R4
R5
l0
L341
VfzLFcmNXl81mK>E;B6kQ[0
R6
31
R7
R8
Adef_arch
R3
Z15 DE work dff_ck_en_1 fzLFcmNXl81mK>E;B6kQ[0
l375
L352
Ve3B6^VXPmbk5fj7WnM>JN3
R6
31
R10
R7
R8
Edff_ck_en_2
R2
R3
R4
R5
l0
L2370
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R6
31
R7
R8
Adef_arch
R3
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l2404
L2381
VTTQ>=eVehKH27mi]Xz=9Y1
R6
31
R10
R7
R8
Edff_ck_en_3
R2
R3
R4
R5
l0
L8
V891`2nG6H>_59<PD`;E>G1
R6
31
R7
R8
Adef_arch
R3
Z17 DE work dff_ck_en_3 891`2nG6H>_59<PD`;E>G1
l42
L19
Vo7lBznQ^k3NL7AzI2[L1G3
R6
31
R10
R7
R8
Epll20mhz
R2
R3
R4
R5
l0
L151
V7KE[JZfSHFSeI?LzYOK0M3
R6
31
R7
R8
Adef_arch
R3
Z18 DE work pll20mhz 7KE[JZfSHFSeI?LzYOK0M3
l271
L161
V40@koO;`N7g4L5T>HOj<N1
R6
31
R10
R7
R8
Ereset_buffer
R2
R3
R4
R5
l0
L97
VnR<zM0nVl_0I;=z^UU3OW2
R6
31
R7
R8
Adef_arch
R3
Z19 DE work reset_buffer nR<zM0nVl_0I;=z^UU3OW2
l125
L105
Z20 Vl;4?d>zHB_;nmKK@S2nk?1
R6
31
R10
R7
R8
Erx_async
R2
R3
R4
R5
l0
L916
VOe_I[;eo2RDW]V@GZzk`k2
R6
31
R7
R8
Adef_arch
R3
R11
l1161
L931
VI[hOR>h>;do]_73D@FdZb1
R6
31
R10
R7
R8
Etx_async
R2
R3
R4
R5
l0
L519
VQX[>Jf2XTEa;JEcR@1W@i3
R6
31
R7
R8
Adef_arch
R3
R12
l714
L549
V?nC_Z7OPaURBS;4;e>fma2
R6
31
R10
R7
R8
Euart
R2
R3
R4
R5
l0
L2285
VaijWom[QDD@5CWR?dNEUG1
R6
31
R7
R8
Adef_arch
R13
R3
Z21 DE work uart aijWom[QDD@5CWR?dNEUG1
l2331
L2301
VIe;dO@UQYE9`F=aP=H6`Z0
R6
31
R10
R7
R8
Euart2gpio
R2
R3
R4
R5
l0
L2459
VCeTIF3W8fKh3n^NZ]mBdl3
R6
31
R7
R8
Adef_arch
R16
R21
R14
R15
R18
R19
R17
R3
DE work uart2gpio CeTIF3W8fKh3n^NZ]mBdl3
l2828
L2473
VlSgf;ERe<UCHPI6m3FFf;3
R6
31
R10
R7
R8
