m255
K3
13
Z0 cModel Technology
Z1 dD:\actel_ip\GPIO_EXPANSION_USING_UART\igloo\uart2gpio\simulation
Euart2gpio
Z2 w1221632464
Z3 DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
Z4 8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/designer/impl1/uart2gpio_ba.vhd
Z5 FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/designer/impl1/uart2gpio_ba.vhd
l0
L9
V`?RCIkfeoz@X6jG6ilGCl2
Z6 OW;C;6.3c;37
31
Z7 o-93 -explicit -work postlayout -O0
Z8 tExplicit 1 NoCoverage 1 CoverOpt 2
Adef_arch
R3
Z9 DE work uart2gpio `?RCIkfeoz@X6jG6ilGCl2
l861
L23
Z10 VaN84]mCd1jfBg`]RMWg=^2
R6
31
Z11 M1 ieee std_logic_1164
R7
R8
