m255
K3
13
cModel Technology
dI:\appsvc\jagarlamudih\DCCCproject\CoreUART\working\mti\lib_vhdl_obs
Eclock_gen
Z0 w1217911496
Z1 DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
Z2 DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
Z3 DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
Z4 dD:\actel_ip\GPIO_EXPANSION_USING_UART\igloo\uart2gpio\simulation
Z5 8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/Clock_gen.vhd
Z6 FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/Clock_gen.vhd
l0
L10
VMeBLoN7K]Z82J`1::mz?h0
Z7 OW;C;6.3c;37
31
Z8 o-93 -explicit -work COREUART_LIB -O0
Z9 tExplicit 1 NoCoverage 1 CoverOpt 2
Acuarto
R1
R2
R3
DE work clock_gen MeBLoN7K]Z82J`1::mz?h0
l28
L18
VjM7W4KV<S[;noXHo?S^]>2
R7
31
Z10 M3 ieee std_logic_1164
Z11 M2 ieee std_logic_arith
Z12 M1 ieee std_logic_unsigned
R8
R9
Pcomponents
R1
R2
R3
Z13 w1217911496
R4
8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/components.vhd
FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/components.vhd
l0
L34
V`fFXblo50o:3QchifOA0M3
R7
31
R10
R11
R12
R8
R9
Pcoreparameters
R13
R4
8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/coreparameters.vhd
FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/coreparameters.vhd
l0
L5
Vo@@cPQmJB:J`lb^WcKlz21
R7
31
R8
R9
Ecoreuart
R13
R1
R2
R3
R4
Z14 8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/CoreUART.vhd
Z15 FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/CoreUART.vhd
l0
L10
VTY0fl^k7e]I=e_WR=nf192
R7
31
R8
R9
Atranslated
R1
R2
R3
DE work coreuart TY0fl^k7e]I=e_WR=nf192
l191
L32
VP0W643<kJBFY_Jao=oTJ[0
R7
31
R10
R11
R12
R8
R9
Erx_async
R13
R1
R2
R3
R4
Z16 8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/Rx_async.vhd
Z17 FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/Rx_async.vhd
l0
L10
V6RKid3OiR;_[[bQDSj:TC1
R7
31
R8
R9
Atranslated
R1
R2
R3
DE work rx_async 6RKid3OiR;_[[bQDSj:TC1
l74
L28
VH_W3QB9FDLb@BM4c28_812
R7
31
R10
R11
R12
R8
R9
Etx_async
R13
R1
R2
R3
R4
Z18 8D:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/Tx_async.vhd
Z19 FD:/actel_ip/GPIO_EXPANSION_USING_UART/igloo/uart2gpio/coreconsole/common/COREUART/rtl/vhdl/core_obfuscated/Tx_async.vhd
l0
L10
Vcmjmn^54@dLS;n`H]5FW32
R7
31
R8
R9
Atranslated
R1
R2
R3
DE work tx_async cmjmn^54@dLS;n`H]5FW32
l81
L27
V4ZEhcTREd0P@4:GgmW7Qb0
R7
31
R10
R11
R12
R8
R9
