m255
K3
13
cModel Technology
Z0 dD:\Mathblock\SF2 DSP Application Notes\DSP Reference Guide\Ref. Guide Design Examples\VHDL\Filters\Parallel FIR Filters\Transpose FIR Filter\Transpose_FIR_w_macc\simulation
Emultadd
Z1 w1383230558
Z2 DPx3 std 6 textio 0 22 5>J:;AW>W0[[dW0I6EN1Q0
Z3 DPx4 ieee 14 std_logic_1164 0 22 5=aWaoGZSMWIcH0i^f`XF1
Z4 dD:\Mathblock\SF2 DSP Application Notes\DSP Reference Guide\Ref. Guide Design Examples\VHDL\Filters\Parallel FIR Filters\Transpose FIR Filter\Transpose_FIR_w_macc\simulation
Z5 8D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Parallel FIR Filters/Transpose FIR Filter/Transpose_FIR_w_macc/component/work/multadd/multadd.vhd
Z6 FD:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Parallel FIR Filters/Transpose FIR Filter/Transpose_FIR_w_macc/component/work/multadd/multadd.vhd
l0
L17
VP0;iha^nb?A_K_4;]Jh6h2
Z7 OW;C;10.1c;51
31
Z8 !s108 1383282959.016000
Z9 !s90 -reportprogress|300|-93|-explicit|-work|presynth|D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Parallel FIR Filters/Transpose FIR Filter/Transpose_FIR_w_macc/component/work/multadd/multadd.vhd|
Z10 !s107 D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Parallel FIR Filters/Transpose FIR Filter/Transpose_FIR_w_macc/component/work/multadd/multadd.vhd|
Z11 o-93 -explicit -work presynth -O0
!s100 h]?FTffDm=zIdg2DoHO0>0
!i10b 1
Artl
R2
R3
DEx4 work 7 multadd 0 22 P0;iha^nb?A_K_4;]Jh6h2
l82
L42
VbDR<Zf`H:NG?bYBE743bk1
R7
31
R8
R9
R10
R11
!s100 JCMo39En5RB_ZkRzzmE;K1
!i10b 1
Emultadd_multadd_0_hard_mult_addsub
Z12 w1383230557
R2
R3
R4
Z13 8D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Parallel FIR Filters/Transpose FIR Filter/Transpose_FIR_w_macc/component/work/multadd/multadd_0/multadd_multadd_0_HARD_MULT_ADDSUB.vhd
Z14 FD:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Parallel FIR Filters/Transpose FIR Filter/Transpose_FIR_w_macc/component/work/multadd/multadd_0/multadd_multadd_0_HARD_MULT_ADDSUB.vhd
l0
L8
VDQ1OEc:=oCnAJeFaiH^cz2
R7
31
Z15 !s108 1383282958.095000
Z16 !s90 -reportprogress|300|-93|-explicit|-work|presynth|D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Parallel FIR Filters/Transpose FIR Filter/Transpose_FIR_w_macc/component/work/multadd/multadd_0/multadd_multadd_0_HARD_MULT_ADDSUB.vhd|
Z17 !s107 D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Parallel FIR Filters/Transpose FIR Filter/Transpose_FIR_w_macc/component/work/multadd/multadd_0/multadd_multadd_0_HARD_MULT_ADDSUB.vhd|
R11
!s100 Wfd1m[z69=AS8Of0<l7IJ1
!i10b 1
Adef_arch
R2
R3
DEx4 work 34 multadd_multadd_0_hard_mult_addsub 0 22 DQ1OEc:=oCnAJeFaiH^cz2
l103
L29
V:^D@QhZ[k:a1=Y3JFUb3E0
R7
31
R15
R16
R17
R11
!s100 Az7WC<:ZKKFIWTm^dhoUB0
!i10b 1
Etranspose_fir
Z18 w1383282615
Z19 DPx4 ieee 11 numeric_std 0 22 O3PF8EB`?j9=z7KT`fn941
Z20 DPx4 ieee 15 std_logic_arith 0 22 4`Y?g_lkdn;7UL9IiJck01
Z21 DPx4 ieee 16 std_logic_signed 0 22 E>OLoMaBGQ?hbGgOoNXM^1
R2
R3
R4
Z22 8D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Parallel FIR Filters/Transpose FIR Filter/Transpose_FIR_w_macc/hdl/Transpose_FIR.vhd
Z23 FD:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Parallel FIR Filters/Transpose FIR Filter/Transpose_FIR_w_macc/hdl/Transpose_FIR.vhd
l0
L23
V8:0I;8O:APS_H`UK3g2<?2
R7
31
Z24 !s108 1383282959.920000
Z25 !s90 -reportprogress|300|-93|-explicit|-work|presynth|D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Parallel FIR Filters/Transpose FIR Filter/Transpose_FIR_w_macc/hdl/Transpose_FIR.vhd|
Z26 !s107 D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Parallel FIR Filters/Transpose FIR Filter/Transpose_FIR_w_macc/hdl/Transpose_FIR.vhd|
R11
!s100 U_^zV7X=`E8Ab>j=z^0:Q0
!i10b 1
Atranspose_fir_arch
R19
R20
R21
R2
R3
DEx4 work 13 transpose_fir 0 22 8:0I;8O:APS_H`UK3g2<?2
l95
L36
V:TMS7]zIm<e16G57m0PW41
R7
31
R24
R25
R26
R11
!s100 7Y36BE0?DfHOE_Ul[gCH20
!i10b 1
Etranspose_fir_testbench
Z27 w1383236192
R20
R21
R2
R3
R4
Z28 8D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Parallel FIR Filters/Transpose FIR Filter/Transpose_FIR_w_macc/stimulus/Transpose_FIR_testbench.vhd
Z29 FD:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Parallel FIR Filters/Transpose FIR Filter/Transpose_FIR_w_macc/stimulus/Transpose_FIR_testbench.vhd
l0
L34
V0AljZ8kZVa@gXFG2JXL8]0
!s100 fBE=i;aO2KHQ]J34Z2N643
R7
31
!i10b 1
Z30 !s108 1383282960.529000
Z31 !s90 -reportprogress|300|-93|-explicit|-work|presynth|D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Parallel FIR Filters/Transpose FIR Filter/Transpose_FIR_w_macc/stimulus/Transpose_FIR_testbench.vhd|
Z32 !s107 D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Filters/Parallel FIR Filters/Transpose FIR Filter/Transpose_FIR_w_macc/stimulus/Transpose_FIR_testbench.vhd|
R11
Atestbench_arch
R20
R21
R2
R3
Z33 DEx4 work 23 transpose_fir_testbench 0 22 0AljZ8kZVa@gXFG2JXL8]0
l63
L38
Z34 VO5z2iZ<DQ3gcfeUYBJKE50
Z35 !s100 2<m[WLI7;H`U;Y2jlBf]e2
R7
31
!i10b 1
R30
R31
R32
R11
