Project Settings
Project Name Systolic_Symmetric_FIR_syn Implementation Name synthesis
Top Module work.Systolic_Symmetric_FIR Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
Compile InputComplete 9 47 0 - 0m:01s - 5/21/2014
8:34:14 PM
Pre-mappingComplete 3 1 0 0m:00s 0m:00s 134MB 5/21/2014
8:34:15 PM
Map & OptimizeComplete 13 1 0 0m:01s 0m:01s 135MB 5/21/2014
8:34:17 PM

Area Summary
Carry Cells 144 Sequential Cells 434
DSP Blocks (MACC) (dsp_used) 8 I/O Cells 64
Global Clock Buffers 2 LUTs (total_luts) 144

Timing Summary
Clock NameReq FreqEst FreqSlack
Systolic_Symmetric_FIR|Clk469.7 MHz399.3 MHz-0.376
System1211.1 MHz1029.4 MHz-0.146

Optimizations Summary
Combined Clock Conversion 1 / 0