@W: MT530 :"d:\dsp reference guide\dsp reference guide\ref. guide design examples\liberov11.3\vhdl\filters\parallel fir\systolic_symmetric_fir\component\work\multadd_0\multadd_0_0\multadd_0_multadd_0_0_hard_mult_addsub.vhd":108:4:108:5|Found inferred clock Systolic_Symmetric_FIR|Clk which controls 432 sequential elements including MUL1.multadd_0_0.U0. This clock has no specified timing constraint which may adversely impact design performance. 
