@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 
@N: MT206 |Auto Constrain mode is enabled
@N: FX271 :"d:\dsp reference guide\dsp reference guide\ref. guide design examples\liberov11.3\vhdl\filters\parallel fir\systolic_symmetric_fir\hdl\systolic_symmetric_fir.vhd":135:4:135:5|Instance "Xreg_15[0]" with 8 loads replicated 1 times to improve timing 
@N: FX271 :"d:\dsp reference guide\dsp reference guide\ref. guide design examples\liberov11.3\vhdl\filters\parallel fir\systolic_symmetric_fir\hdl\systolic_symmetric_fir.vhd":135:4:135:5|Instance "Xreg_15[1]" with 8 loads replicated 1 times to improve timing 
@N: FP130 |Promoting Net Clk_c on CLKINT  I_1 
@N: FP130 |Promoting Net resetn_c on CLKINT  I_2 
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
