#Build: Synplify Pro I-2013.09M-SP1 , Build 034R, Jan 17 2014 #install: C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1 #OS: Windows 7 6.1 #Hostname: W764-TADIGADAPA #Implementation: synthesis $ Start of Compile #Wed May 21 19:46:21 2014 Synopsys VHDL Compiler, version comp201309rcp1, Build 078R, built Jan 14 2014 @N: : | Running in 64-bit mode Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. @N:CD720 : std.vhd(146) | Setting time resolution to ns @N: : Symmetric_MAC_FIR.vhd(21) | Top entity is set to Symmetric_MAC_FIR. VHDL syntax check successful! @N:CD231 : std1164.vhd(913) | Using onehot encoding for type mvl9plus ('U'="1000000000") @N:CD630 : Symmetric_MAC_FIR.vhd(21) | Synthesizing work.symmetric_mac_fir.symmetric_mac_fir_arch @N:CD231 : Symmetric_MAC_FIR.vhd(149) | Using onehot encoding for type state (mac_idle="100000") @W:CD638 : Symmetric_MAC_FIR.vhd(194) | Signal coef_rdaddr2 is undriven @W:CD638 : Symmetric_MAC_FIR.vhd(197) | Signal coef1_rden is undriven @W:CD638 : Symmetric_MAC_FIR.vhd(201) | Signal coef_rddata2 is undriven @W:CD638 : Symmetric_MAC_FIR.vhd(229) | Signal portc_addr is undriven @W:CD638 : Symmetric_MAC_FIR.vhd(230) | Signal portc_din is undriven @W:CD638 : Symmetric_MAC_FIR.vhd(231) | Signal portb_coefaddr is undriven @W:CD638 : Symmetric_MAC_FIR.vhd(232) | Signal portb_inpaddr is undriven @N:CD630 : Inp_RAM1.vhd(17) | Synthesizing work.inp_ram1.rtl @N:CD630 : Inp_RAM1_Inp_RAM1_0_URAM.vhd(8) | Synthesizing work.inp_ram1_inp_ram1_0_uram.def_arch @N:CD630 : smartfusion2.vhd(620) | Synthesizing smartfusion2.ram64x18.syn_black_box Post processing for smartfusion2.ram64x18.syn_black_box @N:CD630 : smartfusion2.vhd(575) | Synthesizing smartfusion2.vcc.syn_black_box Post processing for smartfusion2.vcc.syn_black_box @N:CD630 : smartfusion2.vhd(569) | Synthesizing smartfusion2.gnd.syn_black_box Post processing for smartfusion2.gnd.syn_black_box Post processing for work.inp_ram1_inp_ram1_0_uram.def_arch Post processing for work.inp_ram1.rtl @N:CD630 : Inp_RAM.vhd(17) | Synthesizing work.inp_ram.rtl @N:CD630 : Inp_RAM_Inp_RAM_0_URAM.vhd(8) | Synthesizing work.inp_ram_inp_ram_0_uram.def_arch Post processing for work.inp_ram_inp_ram_0_uram.def_arch Post processing for work.inp_ram.rtl @N:CD630 : Coef_RAM.vhd(17) | Synthesizing work.coef_ram.rtl @N:CD630 : Coef_RAM_Coef_RAM_0_URAM.vhd(8) | Synthesizing work.coef_ram_coef_ram_0_uram.def_arch Post processing for work.coef_ram_coef_ram_0_uram.def_arch Post processing for work.coef_ram.rtl @N:CD630 : mulacc_18x18.vhd(17) | Synthesizing work.mulacc_18x18.rtl @N:CD630 : mulacc_18x18_mulacc_18x18_0_HARD_MULT_ACC.vhd(8) | Synthesizing work.mulacc_18x18_mulacc_18x18_0_hard_mult_acc.def_arch @N:CD630 : smartfusion2.vhd(695) | Synthesizing smartfusion2.macc.syn_black_box Post processing for smartfusion2.macc.syn_black_box Post processing for work.mulacc_18x18_mulacc_18x18_0_hard_mult_acc.def_arch Post processing for work.mulacc_18x18.rtl Post processing for work.symmetric_mac_fir.symmetric_mac_fir_arch @W:CL252 : Symmetric_MAC_FIR.vhd(231) | Bit 0 of signal PORTB_Coefaddr is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(231) | Bit 1 of signal PORTB_Coefaddr is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(231) | Bit 2 of signal PORTB_Coefaddr is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(231) | Bit 3 of signal PORTB_Coefaddr is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(231) | Bit 4 of signal PORTB_Coefaddr is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(231) | Bit 5 of signal PORTB_Coefaddr is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(229) | Bit 0 of signal PORTC_ADDR is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(229) | Bit 1 of signal PORTC_ADDR is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(229) | Bit 2 of signal PORTC_ADDR is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(229) | Bit 3 of signal PORTC_ADDR is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(229) | Bit 4 of signal PORTC_ADDR is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(229) | Bit 5 of signal PORTC_ADDR is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(201) | Bit 0 of signal Coef_rddata2 is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(201) | Bit 1 of signal Coef_rddata2 is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(201) | Bit 2 of signal Coef_rddata2 is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(201) | Bit 3 of signal Coef_rddata2 is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(201) | Bit 4 of signal Coef_rddata2 is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(201) | Bit 5 of signal Coef_rddata2 is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(201) | Bit 6 of signal Coef_rddata2 is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(201) | Bit 7 of signal Coef_rddata2 is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(201) | Bit 8 of signal Coef_rddata2 is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(201) | Bit 9 of signal Coef_rddata2 is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(201) | Bit 10 of signal Coef_rddata2 is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(201) | Bit 11 of signal Coef_rddata2 is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(201) | Bit 12 of signal Coef_rddata2 is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(201) | Bit 13 of signal Coef_rddata2 is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(201) | Bit 14 of signal Coef_rddata2 is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(201) | Bit 15 of signal Coef_rddata2 is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(201) | Bit 16 of signal Coef_rddata2 is floating -- simulation mismatch possible. @W:CL252 : Symmetric_MAC_FIR.vhd(201) | Bit 17 of signal Coef_rddata2 is floating -- simulation mismatch possible. @W:CL240 : Symmetric_MAC_FIR.vhd(197) | Coef1_rden is not assigned a value (floating) -- simulation mismatch possible. @W:CL169 : Symmetric_MAC_FIR.vhd(683) | Pruning register rden_2 @W:CL271 : Symmetric_MAC_FIR.vhd(615) | Pruning bits 7 to 6 of inp_wraddr2_3(7 downto 0) -- not in use ... @W:CL271 : Symmetric_MAC_FIR.vhd(615) | Pruning bits 7 to 6 of inp_wraddr1_3(7 downto 0) -- not in use ... @W:CL271 : Symmetric_MAC_FIR.vhd(516) | Pruning bits 7 to 6 of InpB_rdaddr1_4(7 downto 0) -- not in use ... @W:CL271 : Symmetric_MAC_FIR.vhd(500) | Pruning bits 7 to 6 of InpA_rdaddr1_4(7 downto 0) -- not in use ... @W:CL271 : Symmetric_MAC_FIR.vhd(409) | Pruning bits 7 to 6 of Coef_rdaddr1_2(7 downto 0) -- not in use ... @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 0 of input b_addr of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 1 of input b_addr of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 2 of input b_addr of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 3 of input b_addr of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 4 of input b_addr of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 5 of input b_addr of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 0 of input c_addr of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 1 of input c_addr of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 2 of input c_addr of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 3 of input c_addr of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 4 of input c_addr of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 5 of input c_addr of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 0 of input c_din of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 1 of input c_din of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 2 of input c_din of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 3 of input c_din of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 4 of input c_din of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 5 of input c_din of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 6 of input c_din of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 7 of input c_din of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 8 of input c_din of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 9 of input c_din of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 10 of input c_din of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 11 of input c_din of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 12 of input c_din of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 13 of input c_din of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 14 of input c_din of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 15 of input c_din of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 16 of input c_din of instance U1 is floating @W:CL245 : Symmetric_MAC_FIR.vhd(712) | Bit 17 of input c_din of instance U1 is floating @W:CL111 : Symmetric_MAC_FIR.vhd(769) | All reachable assignments to Sel_Coef2 assign '0'; register removed by optimization @N:CL201 : Symmetric_MAC_FIR.vhd(293) | Trying to extract state machine for register mac_state Extracted state machine for register mac_state State machine has 6 reachable states with original encodings of: 000001 000010 000100 001000 010000 100000 @END At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 78MB peak: 79MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed May 21 19:46:21 2014 ###########################################################] Pre-mapping Report Synopsys Generic Technology Pre-mapping, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2013.09M-SP1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Linked File: DSP Printing clock summary report in "D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\synthesis\Symmetric_MAC_FIR_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB) syn_allowed_resources : blockrams=69 set on top level netlist Symmetric_MAC_FIR Clock Summary ************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ---------------------------------------------------------------------------------------- Symmetric_MAC_FIR|clk 231.9 MHz 4.312 inferred Autoconstr_clkgroup_0 System 1.0 MHz 1000.000 system system_clkgroup ======================================================================================== @W:MT530 : mulacc_18x18_mulacc_18x18_0_hard_mult_acc.vhd(108) | Found inferred clock Symmetric_MAC_FIR|clk which controls 229 sequential elements including U0.mulacc_18x18_0.U0. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\synthesis\Symmetric_MAC_FIR.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 134MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed May 21 19:46:23 2014 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2013.09M-SP1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Encoding state machine mac_state[0:5] (view:work.Symmetric_MAC_FIR(symmetric_mac_fir_arch)) original code -> new code 000001 -> 000001 000010 -> 000010 000100 -> 000100 001000 -> 001000 010000 -> 010000 100000 -> 100000 @N: : symmetric_mac_fir.vhd(457) | Found counter in view:work.Symmetric_MAC_FIR(symmetric_mac_fir_arch) inst inpA_rdaddr[7:0] @N: : symmetric_mac_fir.vhd(437) | Found counter in view:work.Symmetric_MAC_FIR(symmetric_mac_fir_arch) inst B_rdaddr[7:0] Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB) @N:FX404 : symmetric_mac_fir.vhd(487) | Found addmux in view:work.Symmetric_MAC_FIR(symmetric_mac_fir_arch) inst inpB_rdaddr_4_1_0_m2[7:0] from un1_inpB_rdaddr_1[7:0] Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s -13.65ns 281 / 229 ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s -13.65ns 281 / 229 ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s -13.65ns 281 / 229 ------------------------------------------------------------ @N:FP130 : | Promoting Net clk_c on CLKINT I_707 @N:FP130 : | Promoting Net reset_n_c on CLKINT I_708 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 134MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 1 non-gated/non-generated clock tree(s) driving 231 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId0001 clk port 231 inp_wraddr[0] ======================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Writing Analyst data base D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\synthesis\Symmetric_MAC_FIR.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 135MB) Writing EDIF Netlist and constraint files @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF I-2013.09M-SP1 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 135MB) @W:MT246 : inp_ram1_inp_ram1_0_uram.vhd(89) | Blackbox RAM64x18 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock Symmetric_MAC_FIR|clk with period 2.97ns. Please declare a user-defined clock on object "p:clk" ##### START OF TIMING REPORT #####[ # Timing Report written on Wed May 21 19:46:25 2014 # Top view: Symmetric_MAC_FIR Requested Frequency: 337.3 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: -0.845 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------- Symmetric_MAC_FIR|clk 337.3 MHz 286.7 MHz 2.965 3.488 -0.523 inferred Autoconstr_clkgroup_0 System 1.0 MHz 1.0 MHz 1000.000 1000.845 -0.845 system system_clkgroup =============================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------- System Symmetric_MAC_FIR|clk | 2.965 -0.845 | No paths - | No paths - | No paths - Symmetric_MAC_FIR|clk System | 2.965 0.350 | No paths - | No paths - | No paths - Symmetric_MAC_FIR|clk Symmetric_MAC_FIR|clk | 2.965 -0.523 | No paths - | No paths - | No paths - ===================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: Symmetric_MAC_FIR|clk ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------- mac_state[1] Symmetric_MAC_FIR|clk SLE Q mac_state[1] 0.094 -0.523 Coef_rdaddr[1] Symmetric_MAC_FIR|clk SLE Q Coef_rdaddr[1] 0.094 -0.454 mac_state[0] Symmetric_MAC_FIR|clk SLE Q mac_state[0] 0.094 -0.322 A_rdaddr[1] Symmetric_MAC_FIR|clk SLE Q A_rdaddr[1] 0.094 -0.314 inpA_rdaddr[5] Symmetric_MAC_FIR|clk SLE Q inpA_rdaddr[5] 0.094 -0.287 inpA_rdaddr[1] Symmetric_MAC_FIR|clk SLE Q inpA_rdaddr[1] 0.094 -0.214 Coef_rdaddr[6] Symmetric_MAC_FIR|clk SLE Q Coef_rdaddr[6] 0.094 -0.206 Coef_rdaddr[0] Symmetric_MAC_FIR|clk SLE Q Coef_rdaddr[0] 0.094 -0.200 Coef_rdaddr[5] Symmetric_MAC_FIR|clk SLE Q Coef_rdaddr[5] 0.094 -0.180 Coef_rdaddr[2] Symmetric_MAC_FIR|clk SLE Q Coef_rdaddr[2] 0.094 -0.161 =================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------- inpB_rdaddr[7] Symmetric_MAC_FIR|clk SLE D N_51_i_0 2.743 -0.523 Coef0_rden Symmetric_MAC_FIR|clk SLE D N_10_i_0 2.743 -0.454 A_rdaddr[5] Symmetric_MAC_FIR|clk SLE D N_34_i_0 2.743 -0.314 A_rdaddr[6] Symmetric_MAC_FIR|clk SLE D N_36_i_0 2.743 -0.314 inpA_rdaddr[0] Symmetric_MAC_FIR|clk SLE D inpA_rdaddr_lm[0] 2.743 -0.287 A_rdaddr[2] Symmetric_MAC_FIR|clk SLE D N_7_i_0 2.743 -0.247 inpA_rdaddr[1] Symmetric_MAC_FIR|clk SLE D inpA_rdaddr_lm[1] 2.743 -0.230 inpA_rdaddr[2] Symmetric_MAC_FIR|clk SLE D inpA_rdaddr_lm[2] 2.743 -0.230 inpA_rdaddr[3] Symmetric_MAC_FIR|clk SLE D inpA_rdaddr_lm[3] 2.743 -0.230 inpA_rdaddr[4] Symmetric_MAC_FIR|clk SLE D inpA_rdaddr_lm[4] 2.743 -0.230 ======================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 2.965 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.743 - Propagation time: 3.266 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.523 Number of logic level(s): 2 Starting point: mac_state[1] / Q Ending point: inpB_rdaddr[7] / D The start point is clocked by Symmetric_MAC_FIR|clk [rising] on pin CLK The end point is clocked by Symmetric_MAC_FIR|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------- mac_state[1] SLE Q Out 0.094 0.094 - mac_state[1] Net - - 1.374 - 30 inpB_rdaddr_RNO_1[7] ARI1 D In - 1.468 - inpB_rdaddr_RNO_1[7] ARI1 S Out 0.545 2.014 - N_125 Net - - 0.971 - 1 inpB_rdaddr_RNO[7] CFG4 B In - 2.985 - inpB_rdaddr_RNO[7] CFG4 Y Out 0.143 3.128 - N_51_i_0 Net - - 0.138 - 1 inpB_rdaddr[7] SLE D In - 3.266 - =================================================================================== Total path delay (propagation time + setup) of 3.488 is 1.005(28.8%) logic and 2.484(71.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 2.965 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.743 - Propagation time: 3.197 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.454 Number of logic level(s): 3 Starting point: Coef_rdaddr[1] / Q Ending point: Coef0_rden / D The start point is clocked by Symmetric_MAC_FIR|clk [rising] on pin CLK The end point is clocked by Symmetric_MAC_FIR|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------ Coef_rdaddr[1] SLE Q Out 0.094 0.094 - Coef_rdaddr[1] Net - - 0.885 - 7 op_eq\.new_data2_0_o3 CFG3 C In - 0.979 - op_eq\.new_data2_0_o3 CFG3 Y Out 0.182 1.162 - N_14 Net - - 0.622 - 4 Coef0_rden_1_f0_i_o2 CFG4 D In - 1.783 - Coef0_rden_1_f0_i_o2 CFG4 Y Out 0.408 2.192 - N_19 Net - - 0.483 - 1 Coef0_rden_RNO CFG4 D In - 2.675 - Coef0_rden_RNO CFG4 Y Out 0.384 3.059 - N_10_i_0 Net - - 0.138 - 1 Coef0_rden SLE D In - 3.197 - ==================================================================================== Total path delay (propagation time + setup) of 3.419 is 1.291(37.8%) logic and 2.128(62.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 2.965 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.743 - Propagation time: 3.065 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.322 Number of logic level(s): 3 Starting point: mac_state[0] / Q Ending point: inpB_rdaddr[7] / D The start point is clocked by Symmetric_MAC_FIR|clk [rising] on pin CLK The end point is clocked by Symmetric_MAC_FIR|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------- mac_state[0] SLE Q Out 0.094 0.094 - mac_state[0] Net - - 0.933 - 19 inpB_rdaddr_RNO_3[7] CFG1 A In - 1.027 - inpB_rdaddr_RNO_3[7] CFG1 Y Out 0.090 1.117 - mac_state_i_0[0] Net - - 0.483 - 1 inpB_rdaddr_RNO_1[7] ARI1 A In - 1.600 - inpB_rdaddr_RNO_1[7] ARI1 S Out 0.213 1.813 - N_125 Net - - 0.971 - 1 inpB_rdaddr_RNO[7] CFG4 B In - 2.784 - inpB_rdaddr_RNO[7] CFG4 Y Out 0.143 2.927 - N_51_i_0 Net - - 0.138 - 1 inpB_rdaddr[7] SLE D In - 3.065 - =================================================================================== Total path delay (propagation time + setup) of 3.287 is 0.762(23.2%) logic and 2.526(76.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 2.965 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.743 - Propagation time: 3.057 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.314 Number of logic level(s): 3 Starting point: A_rdaddr[1] / Q Ending point: A_rdaddr[5] / D The start point is clocked by Symmetric_MAC_FIR|clk [rising] on pin CLK The end point is clocked by Symmetric_MAC_FIR|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------- A_rdaddr[1] SLE Q Out 0.094 0.094 - A_rdaddr[1] Net - - 0.735 - 6 A_rdaddr_2_i_0_a2_3[2] CFG4 D In - 0.830 - A_rdaddr_2_i_0_a2_3[2] CFG4 Y Out 0.408 1.238 - A_rdaddr_2_i_0_a2_3[2] Net - - 0.483 - 1 A_rdaddr_2_i_0_a2[2] CFG4 D In - 1.721 - A_rdaddr_2_i_0_a2[2] CFG4 Y Out 0.408 2.130 - N_146 Net - - 0.590 - 3 A_rdaddr_RNO[5] CFG4 C In - 2.719 - A_rdaddr_RNO[5] CFG4 Y Out 0.200 2.919 - N_34_i_0 Net - - 0.138 - 1 A_rdaddr[5] SLE D In - 3.057 - ===================================================================================== Total path delay (propagation time + setup) of 3.279 is 1.333(40.6%) logic and 1.946(59.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 2.965 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.743 - Propagation time: 3.057 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.314 Number of logic level(s): 3 Starting point: A_rdaddr[1] / Q Ending point: A_rdaddr[6] / D The start point is clocked by Symmetric_MAC_FIR|clk [rising] on pin CLK The end point is clocked by Symmetric_MAC_FIR|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------- A_rdaddr[1] SLE Q Out 0.094 0.094 - A_rdaddr[1] Net - - 0.735 - 6 A_rdaddr_2_i_0_a2_3[2] CFG4 D In - 0.830 - A_rdaddr_2_i_0_a2_3[2] CFG4 Y Out 0.408 1.238 - A_rdaddr_2_i_0_a2_3[2] Net - - 0.483 - 1 A_rdaddr_2_i_0_a2[2] CFG4 D In - 1.721 - A_rdaddr_2_i_0_a2[2] CFG4 Y Out 0.408 2.130 - N_146 Net - - 0.590 - 3 A_rdaddr_RNO[6] CFG4 C In - 2.719 - A_rdaddr_RNO[6] CFG4 Y Out 0.200 2.919 - N_36_i_0 Net - - 0.138 - 1 A_rdaddr[6] SLE D In - 3.057 - ===================================================================================== Total path delay (propagation time + setup) of 3.279 is 1.333(40.6%) logic and 1.946(59.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------- U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0 System RAM64x18 B_DOUT[0] inpB_rddata2[0] 0.000 -0.845 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0 System RAM64x18 B_DOUT[1] inpB_rddata2[1] 0.000 -0.831 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0 System RAM64x18 B_DOUT[2] inpB_rddata2[2] 0.000 -0.817 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0 System RAM64x18 B_DOUT[3] inpB_rddata2[3] 0.000 -0.802 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0 System RAM64x18 B_DOUT[4] inpB_rddata2[4] 0.000 -0.788 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0 System RAM64x18 A_DOUT[0] inpA_rddata2[0] 0.000 -0.776 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0 System RAM64x18 B_DOUT[5] inpB_rddata2[5] 0.000 -0.774 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0 System RAM64x18 A_DOUT[1] inpA_rddata2[1] 0.000 -0.761 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0 System RAM64x18 B_DOUT[6] inpB_rddata2[6] 0.000 -0.760 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0 System RAM64x18 A_DOUT[2] inpA_rddata2[2] 0.000 -0.747 ================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------- inp_rddata[17] System SLE D N_186 2.743 -0.845 inp_rddata[16] System SLE D N_189 2.743 -0.831 inp_rddata[15] System SLE D inp_rddata_RNO[15] 2.743 -0.817 inp_rddata[14] System SLE D inp_rddata_RNO[14] 2.743 -0.802 inp_rddata[13] System SLE D N_198 2.743 -0.788 inp_rddata[12] System SLE D N_201 2.743 -0.774 inp_rddata[11] System SLE D N_204 2.743 -0.760 inp_rddata[10] System SLE D N_207 2.743 -0.746 inp_rddata[9] System SLE D N_210 2.743 -0.731 inp_rddata[8] System SLE D N_213 2.743 -0.717 ============================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 2.965 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.743 - Propagation time: 3.588 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (critical) : -0.845 Number of logic level(s): 20 Starting point: U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0 / B_DOUT[0] Ending point: inp_rddata[17] / D The start point is clocked by System [rising] The end point is clocked by Symmetric_MAC_FIR|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------ U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0 RAM64x18 B_DOUT[0] Out 0.000 0.000 - inpB_rddata2[0] Net - - 0.977 - 2 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ3OS ARI1 B In - 0.977 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ3OS ARI1 FCO Out 0.174 1.151 - un1_inpA_rddata2_cry_0 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIK7GP1 ARI1 FCI In - 1.151 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIK7GP1 ARI1 FCO Out 0.014 1.165 - un1_inpA_rddata2_cry_1 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIEB8M2 ARI1 FCI In - 1.165 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIEB8M2 ARI1 FCO Out 0.014 1.179 - un1_inpA_rddata2_cry_2 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI8F0J3 ARI1 FCI In - 1.179 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI8F0J3 ARI1 FCO Out 0.014 1.194 - un1_inpA_rddata2_cry_3 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI2JOF4 ARI1 FCI In - 1.194 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI2JOF4 ARI1 FCO Out 0.014 1.208 - un1_inpA_rddata2_cry_4 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNISMGC5 ARI1 FCI In - 1.208 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNISMGC5 ARI1 FCO Out 0.014 1.222 - un1_inpA_rddata2_cry_5 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIMQ896 ARI1 FCI In - 1.222 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIMQ896 ARI1 FCO Out 0.014 1.236 - un1_inpA_rddata2_cry_6 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIGU067 ARI1 FCI In - 1.236 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIGU067 ARI1 FCO Out 0.014 1.250 - un1_inpA_rddata2_cry_7 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIA2P28 ARI1 FCI In - 1.250 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIA2P28 ARI1 FCO Out 0.014 1.265 - un1_inpA_rddata2_cry_8 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI46HV8 ARI1 FCI In - 1.265 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI46HV8 ARI1 FCO Out 0.014 1.279 - un1_inpA_rddata2_cry_9 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIU99S9 ARI1 FCI In - 1.279 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIU99S9 ARI1 FCO Out 0.014 1.293 - un1_inpA_rddata2_cry_10 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIOD1PA ARI1 FCI In - 1.293 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIOD1PA ARI1 FCO Out 0.014 1.307 - un1_inpA_rddata2_cry_11 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIIHPLB ARI1 FCI In - 1.307 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIIHPLB ARI1 FCO Out 0.014 1.321 - un1_inpA_rddata2_cry_12 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNICLHIC ARI1 FCI In - 1.321 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNICLHIC ARI1 FCO Out 0.014 1.336 - un1_inpA_rddata2_cry_13 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI6P9FD ARI1 FCI In - 1.336 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI6P9FD ARI1 FCO Out 0.014 1.350 - un1_inpA_rddata2_cry_14 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI0T1CE ARI1 FCI In - 1.350 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI0T1CE ARI1 FCO Out 0.014 1.364 - un1_inpA_rddata2_cry_15 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ0Q8F ARI1 FCI In - 1.364 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ0Q8F ARI1 FCO Out 0.014 1.378 - un1_inpA_rddata2_cry_16 Net - - 0.000 - 1 inp_rddata_RNO_4[17] ARI1 FCI In - 1.378 - inp_rddata_RNO_4[17] ARI1 S Out 0.063 1.442 - un1_inpA_rddata2_10[17] Net - - 0.971 - 1 inp_rddata_RNO_1[17] CFG4 D In - 2.413 - inp_rddata_RNO_1[17] CFG4 Y Out 0.411 2.824 - un1_inpA_rddata2_1_m_3_10_i_m2_i_m2_1_1 Net - - 0.483 - 1 inp_rddata_RNO[17] CFG4 B In - 3.307 - inp_rddata_RNO[17] CFG4 Y Out 0.143 3.450 - N_186 Net - - 0.138 - 1 inp_rddata[17] SLE D In - 3.588 - ============================================================================================================================== Total path delay (propagation time + setup) of 3.810 is 1.241(32.6%) logic and 2.569(67.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 2.965 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.743 - Propagation time: 3.574 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.831 Number of logic level(s): 19 Starting point: U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0 / B_DOUT[1] Ending point: inp_rddata[17] / D The start point is clocked by System [rising] The end point is clocked by Symmetric_MAC_FIR|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------ U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0 RAM64x18 B_DOUT[1] Out 0.000 0.000 - inpB_rddata2[1] Net - - 0.977 - 2 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIK7GP1 ARI1 B In - 0.977 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIK7GP1 ARI1 FCO Out 0.174 1.151 - un1_inpA_rddata2_cry_1 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIEB8M2 ARI1 FCI In - 1.151 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIEB8M2 ARI1 FCO Out 0.014 1.165 - un1_inpA_rddata2_cry_2 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI8F0J3 ARI1 FCI In - 1.165 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI8F0J3 ARI1 FCO Out 0.014 1.179 - un1_inpA_rddata2_cry_3 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI2JOF4 ARI1 FCI In - 1.179 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI2JOF4 ARI1 FCO Out 0.014 1.194 - un1_inpA_rddata2_cry_4 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNISMGC5 ARI1 FCI In - 1.194 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNISMGC5 ARI1 FCO Out 0.014 1.208 - un1_inpA_rddata2_cry_5 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIMQ896 ARI1 FCI In - 1.208 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIMQ896 ARI1 FCO Out 0.014 1.222 - un1_inpA_rddata2_cry_6 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIGU067 ARI1 FCI In - 1.222 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIGU067 ARI1 FCO Out 0.014 1.236 - un1_inpA_rddata2_cry_7 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIA2P28 ARI1 FCI In - 1.236 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIA2P28 ARI1 FCO Out 0.014 1.250 - un1_inpA_rddata2_cry_8 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI46HV8 ARI1 FCI In - 1.250 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI46HV8 ARI1 FCO Out 0.014 1.265 - un1_inpA_rddata2_cry_9 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIU99S9 ARI1 FCI In - 1.265 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIU99S9 ARI1 FCO Out 0.014 1.279 - un1_inpA_rddata2_cry_10 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIOD1PA ARI1 FCI In - 1.279 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIOD1PA ARI1 FCO Out 0.014 1.293 - un1_inpA_rddata2_cry_11 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIIHPLB ARI1 FCI In - 1.293 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIIHPLB ARI1 FCO Out 0.014 1.307 - un1_inpA_rddata2_cry_12 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNICLHIC ARI1 FCI In - 1.307 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNICLHIC ARI1 FCO Out 0.014 1.321 - un1_inpA_rddata2_cry_13 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI6P9FD ARI1 FCI In - 1.321 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI6P9FD ARI1 FCO Out 0.014 1.336 - un1_inpA_rddata2_cry_14 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI0T1CE ARI1 FCI In - 1.336 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI0T1CE ARI1 FCO Out 0.014 1.350 - un1_inpA_rddata2_cry_15 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ0Q8F ARI1 FCI In - 1.350 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ0Q8F ARI1 FCO Out 0.014 1.364 - un1_inpA_rddata2_cry_16 Net - - 0.000 - 1 inp_rddata_RNO_4[17] ARI1 FCI In - 1.364 - inp_rddata_RNO_4[17] ARI1 S Out 0.063 1.427 - un1_inpA_rddata2_10[17] Net - - 0.971 - 1 inp_rddata_RNO_1[17] CFG4 D In - 2.399 - inp_rddata_RNO_1[17] CFG4 Y Out 0.411 2.810 - un1_inpA_rddata2_1_m_3_10_i_m2_i_m2_1_1 Net - - 0.483 - 1 inp_rddata_RNO[17] CFG4 B In - 3.293 - inp_rddata_RNO[17] CFG4 Y Out 0.143 3.436 - N_186 Net - - 0.138 - 1 inp_rddata[17] SLE D In - 3.574 - ============================================================================================================================== Total path delay (propagation time + setup) of 3.796 is 1.227(32.3%) logic and 2.569(67.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 2.965 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.743 - Propagation time: 3.574 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.831 Number of logic level(s): 19 Starting point: U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0 / B_DOUT[0] Ending point: inp_rddata[16] / D The start point is clocked by System [rising] The end point is clocked by Symmetric_MAC_FIR|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------ U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0 RAM64x18 B_DOUT[0] Out 0.000 0.000 - inpB_rddata2[0] Net - - 0.977 - 2 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ3OS ARI1 B In - 0.977 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ3OS ARI1 FCO Out 0.174 1.151 - un1_inpA_rddata2_cry_0 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIK7GP1 ARI1 FCI In - 1.151 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIK7GP1 ARI1 FCO Out 0.014 1.165 - un1_inpA_rddata2_cry_1 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIEB8M2 ARI1 FCI In - 1.165 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIEB8M2 ARI1 FCO Out 0.014 1.179 - un1_inpA_rddata2_cry_2 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI8F0J3 ARI1 FCI In - 1.179 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI8F0J3 ARI1 FCO Out 0.014 1.194 - un1_inpA_rddata2_cry_3 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI2JOF4 ARI1 FCI In - 1.194 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI2JOF4 ARI1 FCO Out 0.014 1.208 - un1_inpA_rddata2_cry_4 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNISMGC5 ARI1 FCI In - 1.208 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNISMGC5 ARI1 FCO Out 0.014 1.222 - un1_inpA_rddata2_cry_5 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIMQ896 ARI1 FCI In - 1.222 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIMQ896 ARI1 FCO Out 0.014 1.236 - un1_inpA_rddata2_cry_6 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIGU067 ARI1 FCI In - 1.236 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIGU067 ARI1 FCO Out 0.014 1.250 - un1_inpA_rddata2_cry_7 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIA2P28 ARI1 FCI In - 1.250 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIA2P28 ARI1 FCO Out 0.014 1.265 - un1_inpA_rddata2_cry_8 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI46HV8 ARI1 FCI In - 1.265 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI46HV8 ARI1 FCO Out 0.014 1.279 - un1_inpA_rddata2_cry_9 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIU99S9 ARI1 FCI In - 1.279 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIU99S9 ARI1 FCO Out 0.014 1.293 - un1_inpA_rddata2_cry_10 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIOD1PA ARI1 FCI In - 1.293 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIOD1PA ARI1 FCO Out 0.014 1.307 - un1_inpA_rddata2_cry_11 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIIHPLB ARI1 FCI In - 1.307 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIIHPLB ARI1 FCO Out 0.014 1.321 - un1_inpA_rddata2_cry_12 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNICLHIC ARI1 FCI In - 1.321 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNICLHIC ARI1 FCO Out 0.014 1.336 - un1_inpA_rddata2_cry_13 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI6P9FD ARI1 FCI In - 1.336 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI6P9FD ARI1 FCO Out 0.014 1.350 - un1_inpA_rddata2_cry_14 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI0T1CE ARI1 FCI In - 1.350 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI0T1CE ARI1 FCO Out 0.014 1.364 - un1_inpA_rddata2_cry_15 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ0Q8F ARI1 FCI In - 1.364 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ0Q8F ARI1 S Out 0.063 1.427 - un1_inpA_rddata2_10[16] Net - - 0.971 - 1 inp_rddata_RNO_0[16] CFG4 D In - 2.399 - inp_rddata_RNO_0[16] CFG4 Y Out 0.411 2.810 - un1_inpA_rddata2_1_m_3_9_i_m2_i_m2_1_1 Net - - 0.483 - 1 inp_rddata_RNO[16] CFG4 B In - 3.293 - inp_rddata_RNO[16] CFG4 Y Out 0.143 3.436 - N_189 Net - - 0.138 - 1 inp_rddata[16] SLE D In - 3.574 - ============================================================================================================================== Total path delay (propagation time + setup) of 3.796 is 1.227(32.3%) logic and 2.569(67.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 2.965 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.743 - Propagation time: 3.560 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.817 Number of logic level(s): 18 Starting point: U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0 / B_DOUT[2] Ending point: inp_rddata[17] / D The start point is clocked by System [rising] The end point is clocked by Symmetric_MAC_FIR|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------ U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0 RAM64x18 B_DOUT[2] Out 0.000 0.000 - inpB_rddata2[2] Net - - 0.977 - 2 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIEB8M2 ARI1 B In - 0.977 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIEB8M2 ARI1 FCO Out 0.174 1.151 - un1_inpA_rddata2_cry_2 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI8F0J3 ARI1 FCI In - 1.151 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI8F0J3 ARI1 FCO Out 0.014 1.165 - un1_inpA_rddata2_cry_3 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI2JOF4 ARI1 FCI In - 1.165 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI2JOF4 ARI1 FCO Out 0.014 1.179 - un1_inpA_rddata2_cry_4 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNISMGC5 ARI1 FCI In - 1.179 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNISMGC5 ARI1 FCO Out 0.014 1.194 - un1_inpA_rddata2_cry_5 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIMQ896 ARI1 FCI In - 1.194 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIMQ896 ARI1 FCO Out 0.014 1.208 - un1_inpA_rddata2_cry_6 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIGU067 ARI1 FCI In - 1.208 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIGU067 ARI1 FCO Out 0.014 1.222 - un1_inpA_rddata2_cry_7 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIA2P28 ARI1 FCI In - 1.222 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIA2P28 ARI1 FCO Out 0.014 1.236 - un1_inpA_rddata2_cry_8 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI46HV8 ARI1 FCI In - 1.236 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI46HV8 ARI1 FCO Out 0.014 1.250 - un1_inpA_rddata2_cry_9 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIU99S9 ARI1 FCI In - 1.250 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIU99S9 ARI1 FCO Out 0.014 1.265 - un1_inpA_rddata2_cry_10 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIOD1PA ARI1 FCI In - 1.265 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIOD1PA ARI1 FCO Out 0.014 1.279 - un1_inpA_rddata2_cry_11 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIIHPLB ARI1 FCI In - 1.279 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIIHPLB ARI1 FCO Out 0.014 1.293 - un1_inpA_rddata2_cry_12 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNICLHIC ARI1 FCI In - 1.293 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNICLHIC ARI1 FCO Out 0.014 1.307 - un1_inpA_rddata2_cry_13 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI6P9FD ARI1 FCI In - 1.307 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI6P9FD ARI1 FCO Out 0.014 1.321 - un1_inpA_rddata2_cry_14 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI0T1CE ARI1 FCI In - 1.321 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI0T1CE ARI1 FCO Out 0.014 1.336 - un1_inpA_rddata2_cry_15 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ0Q8F ARI1 FCI In - 1.336 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ0Q8F ARI1 FCO Out 0.014 1.350 - un1_inpA_rddata2_cry_16 Net - - 0.000 - 1 inp_rddata_RNO_4[17] ARI1 FCI In - 1.350 - inp_rddata_RNO_4[17] ARI1 S Out 0.063 1.413 - un1_inpA_rddata2_10[17] Net - - 0.971 - 1 inp_rddata_RNO_1[17] CFG4 D In - 2.385 - inp_rddata_RNO_1[17] CFG4 Y Out 0.411 2.795 - un1_inpA_rddata2_1_m_3_10_i_m2_i_m2_1_1 Net - - 0.483 - 1 inp_rddata_RNO[17] CFG4 B In - 3.279 - inp_rddata_RNO[17] CFG4 Y Out 0.143 3.422 - N_186 Net - - 0.138 - 1 inp_rddata[17] SLE D In - 3.560 - ============================================================================================================================== Total path delay (propagation time + setup) of 3.782 is 1.213(32.1%) logic and 2.569(67.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 2.965 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.743 - Propagation time: 3.560 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.817 Number of logic level(s): 18 Starting point: U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0 / B_DOUT[0] Ending point: inp_rddata[15] / D The start point is clocked by System [rising] The end point is clocked by Symmetric_MAC_FIR|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------ U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0 RAM64x18 B_DOUT[0] Out 0.000 0.000 - inpB_rddata2[0] Net - - 0.977 - 2 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ3OS ARI1 B In - 0.977 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ3OS ARI1 FCO Out 0.174 1.151 - un1_inpA_rddata2_cry_0 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIK7GP1 ARI1 FCI In - 1.151 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIK7GP1 ARI1 FCO Out 0.014 1.165 - un1_inpA_rddata2_cry_1 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIEB8M2 ARI1 FCI In - 1.165 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIEB8M2 ARI1 FCO Out 0.014 1.179 - un1_inpA_rddata2_cry_2 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI8F0J3 ARI1 FCI In - 1.179 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI8F0J3 ARI1 FCO Out 0.014 1.194 - un1_inpA_rddata2_cry_3 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI2JOF4 ARI1 FCI In - 1.194 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI2JOF4 ARI1 FCO Out 0.014 1.208 - un1_inpA_rddata2_cry_4 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNISMGC5 ARI1 FCI In - 1.208 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNISMGC5 ARI1 FCO Out 0.014 1.222 - un1_inpA_rddata2_cry_5 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIMQ896 ARI1 FCI In - 1.222 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIMQ896 ARI1 FCO Out 0.014 1.236 - un1_inpA_rddata2_cry_6 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIGU067 ARI1 FCI In - 1.236 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIGU067 ARI1 FCO Out 0.014 1.250 - un1_inpA_rddata2_cry_7 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIA2P28 ARI1 FCI In - 1.250 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIA2P28 ARI1 FCO Out 0.014 1.265 - un1_inpA_rddata2_cry_8 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI46HV8 ARI1 FCI In - 1.265 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI46HV8 ARI1 FCO Out 0.014 1.279 - un1_inpA_rddata2_cry_9 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIU99S9 ARI1 FCI In - 1.279 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIU99S9 ARI1 FCO Out 0.014 1.293 - un1_inpA_rddata2_cry_10 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIOD1PA ARI1 FCI In - 1.293 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIOD1PA ARI1 FCO Out 0.014 1.307 - un1_inpA_rddata2_cry_11 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIIHPLB ARI1 FCI In - 1.307 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIIHPLB ARI1 FCO Out 0.014 1.321 - un1_inpA_rddata2_cry_12 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNICLHIC ARI1 FCI In - 1.321 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNICLHIC ARI1 FCO Out 0.014 1.336 - un1_inpA_rddata2_cry_13 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI6P9FD ARI1 FCI In - 1.336 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI6P9FD ARI1 FCO Out 0.014 1.350 - un1_inpA_rddata2_cry_14 Net - - 0.000 - 1 U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI0T1CE ARI1 FCI In - 1.350 - U2_1.Inp_RAM1_0.Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI0T1CE ARI1 S Out 0.063 1.413 - un1_inpA_rddata2_10[15] Net - - 0.971 - 1 inp_rddata_RNO_0[15] CFG4 D In - 2.385 - inp_rddata_RNO_0[15] CFG4 Y Out 0.411 2.795 - un1_inpA_rddata2_1_m_3_8_i_m2_i_m2_1_1 Net - - 0.483 - 1 inp_rddata_RNO[15] CFG4 B In - 3.279 - inp_rddata_RNO[15] CFG4 Y Out 0.143 3.422 - inp_rddata_RNO[15] Net - - 0.138 - 1 inp_rddata[15] SLE D In - 3.560 - ============================================================================================================================== Total path delay (propagation time + setup) of 3.782 is 1.213(32.1%) logic and 2.569(67.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report for Symmetric_MAC_FIR Mapping to part: m2s050fbga896-1 Cell usage: CLKINT 2 uses CFG1 4 uses CFG2 35 uses CFG3 27 uses CFG4 118 uses Carry primitives used for arithmetic functions: ARI1 96 uses Sequential Cells: SLE 229 uses DSP Blocks: 1 MACC: 1 Mult I/O ports: 67 I/O primitives: 67 INBUF 22 uses OUTBUF 45 uses Global Clock Buffers: 2 RAM/ROM usage summary Block Rams (RAM64x18) : 3 Total LUTs: 280 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 50MB peak: 135MB) Process took 0h:00m:02s realtime, 0h:00m:01s cputime # Wed May 21 19:46:25 2014 ###########################################################]