@W: MT246 :"d:\dsp reference guide\dsp reference guide\ref. guide design examples\liberov11.3\vhdl\filters\single mac fir filters\symmetric_mac_fir_filter\component\work\inp_ram1\inp_ram1_0\inp_ram1_inp_ram1_0_uram.vhd":89:4:89:32|Blackbox RAM64x18 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock Symmetric_MAC_FIR|clk with period 2.97ns. Please declare a user-defined clock on object "p:clk"
