@W: CL111 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Shiftreg_SLL_SRL\hdl\SLL_SRL.vhd":90:1:90:2|All reachable assignments to SHIFT_VAL(17) assign '0'; register removed by optimization
@W: CL247 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Shiftreg_SLL_SRL\hdl\SLL_SRL.vhd":29:1:29:9|Input port bit 17 of shift_inp(17 downto 0) is unused 

