m255
K3
13
cModel Technology
Z0 dD:\Mathblock\SF2 DSP Application Notes\DSP Reference Guide\Ref. Guide Design Examples\VHDL\Shiftreg_SLL_SRL\simulation
Emult18x18
Z1 w1380886413
Z2 DPx3 std 6 textio 0 22 5>J:;AW>W0[[dW0I6EN1Q0
Z3 DPx4 ieee 14 std_logic_1164 0 22 5=aWaoGZSMWIcH0i^f`XF1
Z4 dD:\Mathblock\SF2 DSP Application Notes\DSP Reference Guide\Ref. Guide Design Examples\VHDL\Shiftreg_SLL_SRL\simulation
Z5 8D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Shiftreg_SLL_SRL/synthesis/SLL_SRL.vhd
Z6 FD:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Shiftreg_SLL_SRL/synthesis/SLL_SRL.vhd
l0
L230
VII@DT@nzamcGoQ2[MVX>R3
Z7 OW;C;10.1c;51
31
Z8 !s108 1380889940.501000
Z9 !s90 -reportprogress|300|-93|-explicit|-work|postsynth|D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Shiftreg_SLL_SRL/synthesis/SLL_SRL.vhd|
Z10 !s107 D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Shiftreg_SLL_SRL/synthesis/SLL_SRL.vhd|
Z11 o-93 -explicit -work postsynth -O0
!s100 zaT?=6PVe[MCQOl<eUW]e3
!i10b 1
Adef_arch
Z12 DEx4 work 31 mult18x18_mult18x18_0_hard_mult 0 22 fIO:=GD0KMW8W7iUTQhai1
R2
R3
Z13 DEx4 work 9 mult18x18 0 22 II@DT@nzamcGoQ2[MVX>R3
l266
L241
V8n[n2]G5FWhTE^JXfJfaX0
!s100 zIfFaCknUh0e[E<X:K:z<1
R7
31
R8
R9
R10
R11
!i10b 1
Emult18x18_mult18x18_0_hard_mult
R1
R2
R3
R4
R5
R6
l0
L8
VfIO:=GD0KMW8W7iUTQhai1
R7
31
R8
R9
R10
R11
!s100 A7PMoUP?2gijNEZo[f>Cd0
!i10b 1
Adef_arch
R2
R3
R12
l99
L19
VNMY7k4gc5^IzP><>djoio1
!s100 _YI15C4XChjYQNF6bG<ib3
R7
31
R8
R9
R10
R11
!i10b 1
Esll_srl
R1
R2
R3
R4
R5
R6
l0
L317
V2FQWVH4m@dXF>z8C845HK2
R7
31
R8
R9
R10
R11
!s100 c?O>o;T1O2=m8I5aedB9n0
!i10b 1
Adef_arch
R13
R2
R3
DEx4 work 7 sll_srl 0 22 2FQWVH4m@dXF>z8C845HK2
l387
L328
V9>TS2ccoI50fSgO@97jPi3
!s100 iDmEkgARXe`Y;^8FkjP2J3
R7
31
R8
R9
R10
R11
!i10b 1
Esll_srl_testbench
Z14 w1380886567
R2
R3
R4
Z15 8D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Shiftreg_SLL_SRL/stimulus/SLL_SRL_TESTBENCH.vhd
Z16 FD:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Shiftreg_SLL_SRL/stimulus/SLL_SRL_TESTBENCH.vhd
l0
L21
V]L@RmjM;l7KhiG`I]YPH>1
!s100 0Z6B`HJ]An0>me5Zi3kia2
R7
31
!i10b 1
Z17 !s108 1380889941.780000
Z18 !s90 -reportprogress|300|-93|-explicit|-work|postsynth|D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Shiftreg_SLL_SRL/stimulus/SLL_SRL_TESTBENCH.vhd|
Z19 !s107 D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Shiftreg_SLL_SRL/stimulus/SLL_SRL_TESTBENCH.vhd|
R11
Asll_srl_arch
R2
R3
Z20 DEx4 work 17 sll_srl_testbench 0 22 ]L@RmjM;l7KhiG`I]YPH>1
l50
L24
VV2eG@fhmj4VSZ0z;?Qf?12
!s100 O=H`AH:OMPgGEWzF6No_j3
R7
31
!i10b 1
R17
R18
R19
R11
