Synopsys Generic Technology Mapper, Version mapact, Build 904R, Built Feb 15 2013 10:31:12 Copyright (C) 1994-2012, Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. Product Version G-2012.09M-SP1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 49MB peak: 49MB) @N:MF249 : | Running in 32-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 49MB peak: 50MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 49MB peak: 52MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 67MB peak: 69MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 67MB peak: 69MB) Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 67MB peak: 69MB) @N:FF150 : tinyiir_sf2_template.vhd(45) | Multiplier mul_out[47:0] implemented with multiple MACC blocks using cascade/shift feature. Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:29s; CPU Time elapsed 0h:00m:27s; Memory used current: 87MB peak: 88MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:30s; CPU Time elapsed 0h:00m:28s; Memory used current: 71MB peak: 88MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:30s; CPU Time elapsed 0h:00m:28s; Memory used current: 71MB peak: 88MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:30s; CPU Time elapsed 0h:00m:28s; Memory used current: 71MB peak: 88MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:30s; CPU Time elapsed 0h:00m:28s; Memory used current: 71MB peak: 88MB) Finished preparing to map (Real Time elapsed 0h:00m:31s; CPU Time elapsed 0h:00m:28s; Memory used current: 71MB peak: 88MB) Finished technology mapping (Real Time elapsed 0h:00m:31s; CPU Time elapsed 0h:00m:28s; Memory used current: 71MB peak: 88MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ ------------------------------------------------------------ @N:FP130 : | Promoting Net clk_c on CLKINT I_1 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:31s; CPU Time elapsed 0h:00m:29s; Memory used current: 71MB peak: 88MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:32s; CPU Time elapsed 0h:00m:29s; Memory used current: 71MB peak: 88MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId0001 clk port 8 WideMult_0_0 ======================================================================================= ===== Gated/Generated Clocks ===== ************** None ************** ---------------------------------- ================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Writing Analyst data base D:\Projects\Libero_11_0_0_23\Mathblock_widemult_exmp\synopysis_impl\Mult32x32\synthesis\Mult32x32_SF2.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:34s; CPU Time elapsed 0h:00m:31s; Memory used current: 70MB peak: 88MB) Writing EDIF Netlist and constraint files G-2012.09M-SP1 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:37s; CPU Time elapsed 0h:00m:34s; Memory used current: 71MB peak: 88MB) @W:MT246 : tinyiir_sf2_template.vhd(45) | Blackbox MACC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : tinyiir_sf2_template.vhd(45) | Blackbox MACC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock Mult32x32_SF2|clk with period 1000.00ns. Please declare a user-defined clock on object "p:clk" ##### START OF TIMING REPORT #####[ # Timing Report written on Wed Apr 17 19:11:33 2013 # Top view: Mult32x32_SF2 Requested Frequency: 1.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: -0.028 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------ System 6297.2 MHz 5353.3 MHz 0.159 0.187 -0.028 system system_clkgroup ================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------- System System | 0.159 -0.028 | No paths - | No paths - | No paths - ========================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------- WideMult_0_0 System MACC CDOUT[0] WideMult_1_0_cas[0] 0.000 -0.028 WideMult_0_0 System MACC CDOUT[0] WideMult_1_0_cas[0] 0.000 -0.028 WideMult_0_0 System MACC CDOUT[1] WideMult_1_0_cas[1] 0.000 -0.028 WideMult_0_0 System MACC CDOUT[1] WideMult_1_0_cas[1] 0.000 -0.028 WideMult_0_0 System MACC CDOUT[2] WideMult_1_0_cas[2] 0.000 -0.028 WideMult_0_0 System MACC CDOUT[2] WideMult_1_0_cas[2] 0.000 -0.028 WideMult_0_0 System MACC CDOUT[3] WideMult_1_0_cas[3] 0.000 -0.028 WideMult_0_0 System MACC CDOUT[3] WideMult_1_0_cas[3] 0.000 -0.028 WideMult_0_0 System MACC CDOUT[4] WideMult_1_0_cas[4] 0.000 -0.028 WideMult_0_0 System MACC CDOUT[4] WideMult_1_0_cas[4] 0.000 -0.028 =============================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------- WideMult_1_0 System MACC CDIN[0] WideMult_1_0_cas[0] 0.159 -0.028 WideMult_1_0 System MACC CDIN[0] WideMult_1_0_cas[0] 0.159 -0.028 WideMult_1_0 System MACC CDIN[1] WideMult_1_0_cas[1] 0.159 -0.028 WideMult_1_0 System MACC CDIN[1] WideMult_1_0_cas[1] 0.159 -0.028 WideMult_1_0 System MACC CDIN[2] WideMult_1_0_cas[2] 0.159 -0.028 WideMult_1_0 System MACC CDIN[2] WideMult_1_0_cas[2] 0.159 -0.028 WideMult_1_0 System MACC CDIN[3] WideMult_1_0_cas[3] 0.159 -0.028 WideMult_1_0 System MACC CDIN[3] WideMult_1_0_cas[3] 0.159 -0.028 WideMult_1_0 System MACC CDIN[4] WideMult_1_0_cas[4] 0.159 -0.028 WideMult_1_0 System MACC CDIN[4] WideMult_1_0_cas[4] 0.159 -0.028 =============================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 0.159 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.159 - Propagation time: 0.187 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (critical) : -0.028 Number of logic level(s): 0 Starting point: WideMult_0_0 / CDOUT[0] Ending point: WideMult_1_0 / CDIN[0] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------- WideMult_0_0 MACC CDOUT[0] Out 0.000 0.000 - WideMult_1_0_cas[0] Net - - 0.187 - 1 WideMult_1_0 MACC CDIN[0] In - 0.187 - ====================================================================================== Total path delay (propagation time + setup) of 0.187 is 0.000(0.0%) logic and 0.187(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 0.159 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.159 - Propagation time: 0.187 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (critical) : -0.028 Number of logic level(s): 0 Starting point: WideMult_0_0 / CDOUT[0] Ending point: WideMult_1_0 / CDIN[0] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------- WideMult_0_0 MACC CDOUT[0] Out 0.000 0.000 - WideMult_1_0_cas[0] Net - - 0.187 - 1 WideMult_1_0 MACC CDIN[0] In - 0.187 - ====================================================================================== Total path delay (propagation time + setup) of 0.187 is 0.000(0.0%) logic and 0.187(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 0.159 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.159 - Propagation time: 0.187 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (critical) : -0.028 Number of logic level(s): 0 Starting point: WideMult_0_0 / CDOUT[1] Ending point: WideMult_1_0 / CDIN[1] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------- WideMult_0_0 MACC CDOUT[1] Out 0.000 0.000 - WideMult_1_0_cas[1] Net - - 0.187 - 1 WideMult_1_0 MACC CDIN[1] In - 0.187 - ====================================================================================== Total path delay (propagation time + setup) of 0.187 is 0.000(0.0%) logic and 0.187(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 0.159 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.159 - Propagation time: 0.187 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (critical) : -0.028 Number of logic level(s): 0 Starting point: WideMult_0_0 / CDOUT[1] Ending point: WideMult_1_0 / CDIN[1] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------- WideMult_0_0 MACC CDOUT[1] Out 0.000 0.000 - WideMult_1_0_cas[1] Net - - 0.187 - 1 WideMult_1_0 MACC CDIN[1] In - 0.187 - ====================================================================================== Total path delay (propagation time + setup) of 0.187 is 0.000(0.0%) logic and 0.187(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 0.159 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.159 - Propagation time: 0.187 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (critical) : -0.028 Number of logic level(s): 0 Starting point: WideMult_0_0 / CDOUT[2] Ending point: WideMult_1_0 / CDIN[2] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------- WideMult_0_0 MACC CDOUT[2] Out 0.000 0.000 - WideMult_1_0_cas[2] Net - - 0.187 - 1 WideMult_1_0 MACC CDIN[2] In - 0.187 - ====================================================================================== Total path delay (propagation time + setup) of 0.187 is 0.000(0.0%) logic and 0.187(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report for Mult32x32_SF2 Mapping to part: m2s050tfbga896std Cell usage: CLKINT 1 use Sequential Cells: SLE 0 uses DSP Blocks: 4 MACC: 1 Mult MACC: 3 MultAdds I/O ports: 98 I/O primitives: 98 INBUF 50 uses OUTBUF 48 uses Global Clock Buffers: 1 Total LUTs: 0 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:39s; CPU Time elapsed 0h:00m:35s; Memory used current: 21MB peak: 88MB) Process took 0h:00m:39s realtime, 0h:00m:35s cputime # Wed Apr 17 19:11:34 2013 ###########################################################]