@W: MT530 :"d:\projects\libero_11_0_0_23\mathblock_widemult_exmp\synopysis_impl\mult32x32\component\work\acc_0\acc_0_0\acc_0_acc_0_0_hard_mult_acc.vhd":116:4:116:5|Found inferred clock Mult32x32_SF2|clk which controls 111 sequential elements including U1.acc_0_0.U0. This clock has no specified timing constraint which may adversely impact design performance. 
