@W: MT530 :"d:\dsp reference guide\dsp reference guide\ref. guide design examples\liberov11.3\vhdl\fourinput_42bit_adder\component\work\multadder\multadder_0\multadder_multadder_0_hard_mult_addsub.vhd":112:4:112:5|Found inferred clock Fourinput_42bit_Adder|CLK which controls 80 sequential elements including U0.MultAdder_0.U0. This clock has no specified timing constraint which may adversely impact design performance. 
