m255
K3
13
cModel Technology
Z0 dD:\Mathblock\SF2 DSP Application Notes\DSP Reference Guide\Ref. Guide Design Examples\VHDL\Fourinput_42bit_Adder\simulation
Efourinput_42bit_adder
Z1 w1381084840
Z2 DPx4 ieee 15 std_logic_arith 0 22 4`Y?g_lkdn;7UL9IiJck01
Z3 DPx4 ieee 18 std_logic_unsigned 0 22 RYmj;=TK`k=k>D@Cz`zoB3
Z4 DPx3 std 6 textio 0 22 5>J:;AW>W0[[dW0I6EN1Q0
Z5 DPx4 ieee 14 std_logic_1164 0 22 5=aWaoGZSMWIcH0i^f`XF1
Z6 dD:\Mathblock\SF2 DSP Application Notes\DSP Reference Guide\Ref. Guide Design Examples\VHDL\Fourinput_42bit_Adder\simulation
Z7 8D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/hdl/Fourinput_42bit_Adder.vhd
Z8 FD:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/hdl/Fourinput_42bit_Adder.vhd
l0
L33
V]?;lM8hoU4=SfgelU@K?g0
!s100 gKkSXndi15TSz`VgC1WB42
Z9 OW;C;10.1c;51
31
!i10b 1
Z10 !s108 1381084886.047000
Z11 !s90 -reportprogress|300|-93|-explicit|-work|presynth|-O0|D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/hdl/Fourinput_42bit_Adder.vhd|
Z12 !s107 D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/hdl/Fourinput_42bit_Adder.vhd|
Z13 o-93 -explicit -work presynth -O0
Aadder42bit_arch
R2
R3
R4
R5
Z14 DEx4 work 21 fourinput_42bit_adder 0 22 ]?;lM8hoU4=SfgelU@K?g0
l136
L57
Vg62VD9gKV9FG1R8C]i9AR1
!s100 `dkXhfBTMX;i7KDcYzRGC0
R9
31
!i10b 1
R10
R11
R12
R13
Efourinput_42bitadder_testbench
Z15 w1381082803
R2
R3
R4
R5
R6
Z16 8D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/stimulus/Fourinput_42bitAdder_Testbench.vhd
Z17 FD:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/stimulus/Fourinput_42bitAdder_Testbench.vhd
l0
L21
V<G_`S=3N:QfiD7F:KUG?K1
R9
31
Z18 !s108 1381084081.419000
Z19 !s90 -reportprogress|300|-93|-explicit|-work|presynth|D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/stimulus/Fourinput_42bitAdder_Testbench.vhd|
Z20 !s107 D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/stimulus/Fourinput_42bitAdder_Testbench.vhd|
R13
!s100 _8]_]E8;IPZDCWIX:C^g02
!i10b 1
Abehavioral
R2
R3
R4
R5
DEx4 work 30 fourinput_42bitadder_testbench 0 22 <G_`S=3N:QfiD7F:KUG?K1
l67
L24
VVk5M:zR>5cDlZIjC^e8?]3
!s100 O8^?nQ@<gPGmdR?a0N@Z?0
R9
31
R18
R19
R20
R13
!i10b 1
Emultadder
Z21 w1381083557
R4
R5
R6
Z22 8D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/component/work/MultAdder/MultAdder.vhd
Z23 FD:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/component/work/MultAdder/MultAdder.vhd
l0
L17
VzgOP<ikRg38zbV7:3fcej3
R9
31
Z24 !s108 1381084064.175000
Z25 !s90 -reportprogress|300|-93|-explicit|-work|presynth|D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/component/work/MultAdder/MultAdder.vhd|
Z26 !s107 D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/component/work/MultAdder/MultAdder.vhd|
R13
!s100 @9UdAiR0jVoVgC?UfT5a90
!i10b 1
Artl
R4
R5
DEx4 work 9 multadder 0 22 zgOP<ikRg38zbV7:3fcej3
l92
L46
V9hbOm=cnPM9HN^CP@li[73
R9
31
R24
R25
R26
R13
!s100 i<AmYWNicP=6IW:zKeN>Q0
!i10b 1
Emultadder_multadder_0_hard_mult_addsub
R21
R4
R5
R6
Z27 8D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/component/work/MultAdder/MultAdder_0/MultAdder_MultAdder_0_HARD_MULT_ADDSUB.vhd
Z28 FD:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/component/work/MultAdder/MultAdder_0/MultAdder_MultAdder_0_HARD_MULT_ADDSUB.vhd
l0
L8
VmV6c9o]_TB7^E5?_=h4H?0
R9
31
Z29 !s108 1381084057.985000
Z30 !s90 -reportprogress|300|-93|-explicit|-work|presynth|D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/component/work/MultAdder/MultAdder_0/MultAdder_MultAdder_0_HARD_MULT_ADDSUB.vhd|
Z31 !s107 D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/component/work/MultAdder/MultAdder_0/MultAdder_MultAdder_0_HARD_MULT_ADDSUB.vhd|
R13
!s100 f:=k;E`nmk@0@`RiPZ?^m0
!i10b 1
Adef_arch
R4
R5
DEx4 work 38 multadder_multadder_0_hard_mult_addsub 0 22 mV6c9o]_TB7^E5?_=h4H?0
l107
L33
V>N97K:J6c4]h`li:[4iGm3
R9
31
R29
R30
R31
R13
!s100 EPRJGBa72hc2k]1K^YnXT0
!i10b 1
Emultadder_w_din
Z32 w1381071935
R4
R5
R6
Z33 8D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/component/work/MultAdder_w_Din/MultAdder_w_Din.vhd
Z34 FD:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/component/work/MultAdder_w_Din/MultAdder_w_Din.vhd
l0
L17
VfIiGHVAMFY:6je0DQI2Jg3
R9
31
Z35 !s108 1381084072.970000
Z36 !s90 -reportprogress|300|-93|-explicit|-work|presynth|D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/component/work/MultAdder_w_Din/MultAdder_w_Din.vhd|
Z37 !s107 D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/component/work/MultAdder_w_Din/MultAdder_w_Din.vhd|
R13
!s100 Q2HWJk1e?]<WlFNSC_QQe3
!i10b 1
Artl
R4
R5
DEx4 work 15 multadder_w_din 0 22 fIiGHVAMFY:6je0DQI2Jg3
l95
L48
VPkn:5Y]5>LgEUo2VoR4:z3
R9
31
R35
R36
R37
R13
!s100 VGCj9QJGWH`oIQiABGeIV2
!i10b 1
Emultadder_w_din_multadder_w_din_0_hard_mult_addsub
R32
R4
R5
R6
Z38 8D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/component/work/MultAdder_w_Din/MultAdder_w_Din_0/MultAdder_w_Din_MultAdder_w_Din_0_HARD_MULT_ADDSUB.vhd
Z39 FD:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/component/work/MultAdder_w_Din/MultAdder_w_Din_0/MultAdder_w_Din_MultAdder_w_Din_0_HARD_MULT_ADDSUB.vhd
l0
L8
VIY4_6R@7R;`k4A54P97I11
R9
31
Z40 !s108 1381084068.600000
Z41 !s90 -reportprogress|300|-93|-explicit|-work|presynth|D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/component/work/MultAdder_w_Din/MultAdder_w_Din_0/MultAdder_w_Din_MultAdder_w_Din_0_HARD_MULT_ADDSUB.vhd|
Z42 !s107 D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Fourinput_42bit_Adder/component/work/MultAdder_w_Din/MultAdder_w_Din_0/MultAdder_w_Din_MultAdder_w_Din_0_HARD_MULT_ADDSUB.vhd|
R13
!s100 VD[1:cMjBo2OJQSjaHC<G3
!i10b 1
Adef_arch
R4
R5
DEx4 work 50 multadder_w_din_multadder_w_din_0_hard_mult_addsub 0 22 IY4_6R@7R;`k4A54P97I11
l110
L36
V:J=J`Za9GIVZk0P?FdQGR1
R9
31
R40
R41
R42
R13
!s100 C_O@8nlV]e?KI[46`2VOg3
!i10b 1
