Project Settings Project Name Extended_adder_3_input_syn Implementation Name synthesis Top Module work.Extended_adder_3_input Retiming 0 Resource Sharing 1 Fanout Guide 10000 Disable I/O Insertion 0 FSM Compiler 1 Run Status Job Name Status CPU Time Real Time Memory Date/Time Compile Input Complete 12 2 0 - 0m:00s - 5/21/2014 6:58:52 PM Pre-mapping Complete 3 1 0 0m:00s 0m:00s 133MB 5/21/2014 6:58:54 PM Map & Optimize Complete 11 1 0 0m:01s 0m:01s 133MB 5/21/2014 6:58:55 PM Area Summary Carry Cells 18 Sequential Cells 48 DSP Blocks (MACC) (dsp_used) 2 I/O Cells 194 Global Clock Buffers 2 LUTs (total_luts) 19 Timing Summary Clock Name Req Freq Est Freq Slack Extended_adder_3_input|clk 432.2 MHz 367.3 MHz -0.408 System 1053.2 MHz 895.2 MHz -0.168 Optimizations Summary Combined Clock Conversion 1 / 0