#Build: Synplify Pro I-2013.09M-SP1 , Build 034R, Jan 17 2014 #install: C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1 #OS: Windows 7 6.1 #Hostname: W764-TADIGADAPA #Implementation: synthesis $ Start of Compile #Wed May 21 18:58:52 2014 Synopsys VHDL Compiler, version comp201309rcp1, Build 078R, built Jan 14 2014 @N: : | Running in 64-bit mode Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. @N:CD720 : std.vhd(146) | Setting time resolution to ns @N: : Extended_adder_3_input.vhd(23) | Top entity is set to Extended_adder_3_input. File C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.vhd changed - recompiling File D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Extended Adder\Extended_adder_3_input\component\work\dotp_multadd1\dotp_multadd1.vhd changed - recompiling File D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Extended Adder\Extended_adder_3_input\component\work\dotp_multadd\dotp_multadd.vhd changed - recompiling File D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Extended Adder\Extended_adder_3_input\hdl\Extended_adder_3_input.vhd changed - recompiling File C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vhd2008\signed.vhd changed - recompiling VHDL syntax check successful! @N:CD231 : std1164.vhd(913) | Using onehot encoding for type mvl9plus ('U'="1000000000") @N:CD630 : Extended_adder_3_input.vhd(23) | Synthesizing work.extended_adder_3_input.extended_adder_3_input_arch @N:CD630 : dotp_multadd.vhd(17) | Synthesizing work.dotp_multadd.rtl @N:CD630 : dotp_multadd_dotp_multadd_0_HARD_MULT_ADDSUB.vhd(8) | Synthesizing work.dotp_multadd_dotp_multadd_0_hard_mult_addsub.def_arch @N:CD630 : smartfusion2.vhd(575) | Synthesizing smartfusion2.vcc.syn_black_box Post processing for smartfusion2.vcc.syn_black_box @N:CD630 : smartfusion2.vhd(569) | Synthesizing smartfusion2.gnd.syn_black_box Post processing for smartfusion2.gnd.syn_black_box @N:CD630 : smartfusion2.vhd(695) | Synthesizing smartfusion2.macc.syn_black_box Post processing for smartfusion2.macc.syn_black_box Post processing for work.dotp_multadd_dotp_multadd_0_hard_mult_addsub.def_arch Post processing for work.dotp_multadd.rtl @N:CD630 : dotp_multadd1.vhd(17) | Synthesizing work.dotp_multadd1.rtl @N:CD630 : dotp_multadd1_dotp_multadd1_0_HARD_MULT_ADDSUB.vhd(8) | Synthesizing work.dotp_multadd1_dotp_multadd1_0_hard_mult_addsub.def_arch @W:CD275 : dotp_multadd1_dotp_multadd1_0_HARD_MULT_ADDSUB.vhd(25) | Component declarations with different initial values are not supported. Port cdin of component macc may have been given a different initial value in two different component declarations Post processing for work.dotp_multadd1_dotp_multadd1_0_hard_mult_addsub.def_arch Post processing for work.dotp_multadd1.rtl Post processing for work.extended_adder_3_input.extended_adder_3_input_arch @W:CL279 : Extended_adder_3_input.vhd(200) | Pruning register bits 8 to 3 of Res_Upper_reg(8 downto 0) @END At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 77MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed May 21 18:58:52 2014 ###########################################################] Pre-mapping Report Synopsys Generic Technology Pre-mapping, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2013.09M-SP1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Linked File: DSP Printing clock summary report in "D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Extended Adder\Extended_adder_3_input\synthesis\Extended_adder_3_input_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB) syn_allowed_resources : blockrams=69 set on top level netlist Extended_adder_3_input Clock Summary ************** Start Requested Requested Clock Clock Clock Frequency Period Type Group --------------------------------------------------------------------------------------------- Extended_adder_3_input|clk 427.3 MHz 2.340 inferred Autoconstr_clkgroup_0 System 1.0 MHz 1000.000 system system_clkgroup ============================================================================================= @W:MT530 : dotp_multadd1_dotp_multadd1_0_hard_mult_addsub.vhd(102) | Found inferred clock Extended_adder_3_input|clk which controls 48 sequential elements including U0.dotp_multadd1_0.U0. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Extended Adder\Extended_adder_3_input\synthesis\Extended_adder_3_input.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 133MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed May 21 18:58:54 2014 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2013.09M-SP1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s -4.11ns 20 / 48 ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s -4.11ns 20 / 48 ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s -4.11ns 20 / 48 ------------------------------------------------------------ @N:FP130 : | Promoting Net clk_c on CLKINT I_1 @N:FP130 : | Promoting Net reset_n_c on CLKINT I_2 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 1 non-gated/non-generated clock tree(s) driving 52 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId0001 clk port 52 INPUTD_reg1[0] ======================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Writing Analyst data base D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Extended Adder\Extended_adder_3_input\synthesis\Extended_adder_3_input.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB) Writing EDIF Netlist and constraint files @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF I-2013.09M-SP1 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB) @W:MT420 : | Found inferred clock Extended_adder_3_input|clk with period 2.31ns. Please declare a user-defined clock on object "p:clk" ##### START OF TIMING REPORT #####[ # Timing Report written on Wed May 21 18:58:55 2014 # Top view: Extended_adder_3_input Requested Frequency: 432.2 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: -0.408 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------- Extended_adder_3_input|clk 432.2 MHz 367.3 MHz 2.314 2.722 -0.408 inferred Autoconstr_clkgroup_0 System 1053.2 MHz 895.2 MHz 0.950 1.117 -0.168 system system_clkgroup ===================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------------------------------------------- System System | 0.950 -0.168 | No paths - | No paths - | No paths - System Extended_adder_3_input|clk | 2.314 0.613 | No paths - | No paths - | No paths - Extended_adder_3_input|clk Extended_adder_3_input|clk | 2.314 -0.408 | No paths - | No paths - | No paths - =============================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: Extended_adder_3_input|clk ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------ Res_Upper_reg[2] Extended_adder_3_input|clk SLE Q Res_Upper_reg[2] 0.108 -0.408 INPUTD_reg1[0] Extended_adder_3_input|clk SLE Q INPUTD_reg1[0] 0.108 -0.140 Res_Upper_reg[0] Extended_adder_3_input|clk SLE Q Res_Upper_reg[0] 0.108 -0.140 INPUTD_reg1[1] Extended_adder_3_input|clk SLE Q INPUTD_reg1[1] 0.108 -0.123 Res_Upper_reg[1] Extended_adder_3_input|clk SLE Q Res_Upper_reg[1] 0.108 -0.123 INPUTD_reg1[8] Extended_adder_3_input|clk SLE Q INPUTD_reg1[8] 0.108 -0.121 INPUTD_reg1[2] Extended_adder_3_input|clk SLE Q INPUTD_reg1[2] 0.108 -0.107 INPUTD_reg1[3] Extended_adder_3_input|clk SLE Q INPUTD_reg1[3] 0.108 -0.091 INPUTD_reg1[4] Extended_adder_3_input|clk SLE Q INPUTD_reg1[4] 0.108 -0.074 Adderop_reg[8] Extended_adder_3_input|clk SLE Q Adderop_reg[8] 0.108 -0.060 ============================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------- Adderop_reg1[8] Extended_adder_3_input|clk SLE D un2_adderop_reg1_s_8_S 2.059 -0.408 Adderop_reg1[7] Extended_adder_3_input|clk SLE D un2_adderop_reg1_cry_7_S 2.059 -0.379 Adderop_reg1[6] Extended_adder_3_input|clk SLE D un2_adderop_reg1_cry_6_S 2.059 -0.362 Adderop_reg1[2] Extended_adder_3_input|clk SLE D un2_adderop_reg1_cry_2_S 2.059 -0.348 Adderop_reg1[3] Extended_adder_3_input|clk SLE D un2_adderop_reg1_cry_3_S 2.059 -0.348 Adderop_reg1[4] Extended_adder_3_input|clk SLE D un2_adderop_reg1_cry_4_S 2.059 -0.348 Adderop_reg1[5] Extended_adder_3_input|clk SLE D un2_adderop_reg1_cry_5_S 2.059 -0.348 Adderop_reg[8] Extended_adder_3_input|clk SLE D un2_adderop_reg_s_8_S 2.059 -0.140 Adderop_reg[7] Extended_adder_3_input|clk SLE D un2_adderop_reg_cry_7_S 2.059 -0.123 Adderop_reg[6] Extended_adder_3_input|clk SLE D un2_adderop_reg_cry_6_S 2.059 -0.107 ==================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 2.314 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.059 - Propagation time: 2.467 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.408 Number of logic level(s): 1 Starting point: Res_Upper_reg[2] / Q Ending point: Adderop_reg1[8] / D The start point is clocked by Extended_adder_3_input|clk [rising] on pin CLK The end point is clocked by Extended_adder_3_input|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------- Res_Upper_reg[2] SLE Q Out 0.108 0.108 - Res_Upper_reg[2] Net - - 0.873 - 7 un2_adderop_reg1_s_8 ARI1 C In - 0.981 - un2_adderop_reg1_s_8 ARI1 S Out 0.369 1.350 - un2_adderop_reg1_s_8_S Net - - 1.117 - 1 Adderop_reg1[8] SLE D In - 2.467 - ===================================================================================== Total path delay (propagation time + setup) of 2.722 is 0.732(26.9%) logic and 1.990(73.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 2.314 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.059 - Propagation time: 2.454 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.395 Number of logic level(s): 7 Starting point: Res_Upper_reg[2] / Q Ending point: Adderop_reg1[8] / D The start point is clocked by Extended_adder_3_input|clk [rising] on pin CLK The end point is clocked by Extended_adder_3_input|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------- Res_Upper_reg[2] SLE Q Out 0.108 0.108 - Res_Upper_reg[2] Net - - 0.873 - 7 un2_adderop_reg1_cry_2 ARI1 B In - 0.981 - un2_adderop_reg1_cry_2 ARI1 FCO Out 0.201 1.182 - un2_adderop_reg1_cry_2 Net - - 0.000 - 1 un2_adderop_reg1_cry_3 ARI1 FCI In - 1.182 - un2_adderop_reg1_cry_3 ARI1 FCO Out 0.016 1.198 - un2_adderop_reg1_cry_3 Net - - 0.000 - 1 un2_adderop_reg1_cry_4 ARI1 FCI In - 1.198 - un2_adderop_reg1_cry_4 ARI1 FCO Out 0.016 1.214 - un2_adderop_reg1_cry_4 Net - - 0.000 - 1 un2_adderop_reg1_cry_5 ARI1 FCI In - 1.214 - un2_adderop_reg1_cry_5 ARI1 FCO Out 0.016 1.231 - un2_adderop_reg1_cry_5 Net - - 0.000 - 1 un2_adderop_reg1_cry_6 ARI1 FCI In - 1.231 - un2_adderop_reg1_cry_6 ARI1 FCO Out 0.016 1.247 - un2_adderop_reg1_cry_6 Net - - 0.000 - 1 un2_adderop_reg1_cry_7 ARI1 FCI In - 1.247 - un2_adderop_reg1_cry_7 ARI1 FCO Out 0.016 1.263 - un2_adderop_reg1_cry_7 Net - - 0.000 - 1 un2_adderop_reg1_s_8 ARI1 FCI In - 1.263 - un2_adderop_reg1_s_8 ARI1 S Out 0.073 1.336 - un2_adderop_reg1_s_8_S Net - - 1.117 - 1 Adderop_reg1[8] SLE D In - 2.454 - ===================================================================================== Total path delay (propagation time + setup) of 2.709 is 0.719(26.5%) logic and 1.990(73.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 2.314 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.059 - Propagation time: 2.437 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.378 Number of logic level(s): 6 Starting point: Res_Upper_reg[2] / Q Ending point: Adderop_reg1[8] / D The start point is clocked by Extended_adder_3_input|clk [rising] on pin CLK The end point is clocked by Extended_adder_3_input|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------- Res_Upper_reg[2] SLE Q Out 0.108 0.108 - Res_Upper_reg[2] Net - - 0.873 - 7 un2_adderop_reg1_cry_3 ARI1 B In - 0.981 - un2_adderop_reg1_cry_3 ARI1 FCO Out 0.201 1.182 - un2_adderop_reg1_cry_3 Net - - 0.000 - 1 un2_adderop_reg1_cry_4 ARI1 FCI In - 1.182 - un2_adderop_reg1_cry_4 ARI1 FCO Out 0.016 1.198 - un2_adderop_reg1_cry_4 Net - - 0.000 - 1 un2_adderop_reg1_cry_5 ARI1 FCI In - 1.198 - un2_adderop_reg1_cry_5 ARI1 FCO Out 0.016 1.214 - un2_adderop_reg1_cry_5 Net - - 0.000 - 1 un2_adderop_reg1_cry_6 ARI1 FCI In - 1.214 - un2_adderop_reg1_cry_6 ARI1 FCO Out 0.016 1.231 - un2_adderop_reg1_cry_6 Net - - 0.000 - 1 un2_adderop_reg1_cry_7 ARI1 FCI In - 1.231 - un2_adderop_reg1_cry_7 ARI1 FCO Out 0.016 1.247 - un2_adderop_reg1_cry_7 Net - - 0.000 - 1 un2_adderop_reg1_s_8 ARI1 FCI In - 1.247 - un2_adderop_reg1_s_8 ARI1 S Out 0.073 1.320 - un2_adderop_reg1_s_8_S Net - - 1.117 - 1 Adderop_reg1[8] SLE D In - 2.437 - ===================================================================================== Total path delay (propagation time + setup) of 2.692 is 0.703(26.1%) logic and 1.990(73.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 2.314 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.059 - Propagation time: 2.437 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.378 Number of logic level(s): 6 Starting point: Res_Upper_reg[2] / Q Ending point: Adderop_reg1[7] / D The start point is clocked by Extended_adder_3_input|clk [rising] on pin CLK The end point is clocked by Extended_adder_3_input|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- Res_Upper_reg[2] SLE Q Out 0.108 0.108 - Res_Upper_reg[2] Net - - 0.873 - 7 un2_adderop_reg1_cry_2 ARI1 B In - 0.981 - un2_adderop_reg1_cry_2 ARI1 FCO Out 0.201 1.182 - un2_adderop_reg1_cry_2 Net - - 0.000 - 1 un2_adderop_reg1_cry_3 ARI1 FCI In - 1.182 - un2_adderop_reg1_cry_3 ARI1 FCO Out 0.016 1.198 - un2_adderop_reg1_cry_3 Net - - 0.000 - 1 un2_adderop_reg1_cry_4 ARI1 FCI In - 1.198 - un2_adderop_reg1_cry_4 ARI1 FCO Out 0.016 1.214 - un2_adderop_reg1_cry_4 Net - - 0.000 - 1 un2_adderop_reg1_cry_5 ARI1 FCI In - 1.214 - un2_adderop_reg1_cry_5 ARI1 FCO Out 0.016 1.231 - un2_adderop_reg1_cry_5 Net - - 0.000 - 1 un2_adderop_reg1_cry_6 ARI1 FCI In - 1.231 - un2_adderop_reg1_cry_6 ARI1 FCO Out 0.016 1.247 - un2_adderop_reg1_cry_6 Net - - 0.000 - 1 un2_adderop_reg1_cry_7 ARI1 FCI In - 1.247 - un2_adderop_reg1_cry_7 ARI1 S Out 0.073 1.320 - un2_adderop_reg1_cry_7_S Net - - 1.117 - 1 Adderop_reg1[7] SLE D In - 2.437 - ======================================================================================= Total path delay (propagation time + setup) of 2.692 is 0.703(26.1%) logic and 1.990(73.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 2.314 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.059 - Propagation time: 2.421 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.362 Number of logic level(s): 5 Starting point: Res_Upper_reg[2] / Q Ending point: Adderop_reg1[8] / D The start point is clocked by Extended_adder_3_input|clk [rising] on pin CLK The end point is clocked by Extended_adder_3_input|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------- Res_Upper_reg[2] SLE Q Out 0.108 0.108 - Res_Upper_reg[2] Net - - 0.873 - 7 un2_adderop_reg1_cry_4 ARI1 B In - 0.981 - un2_adderop_reg1_cry_4 ARI1 FCO Out 0.201 1.182 - un2_adderop_reg1_cry_4 Net - - 0.000 - 1 un2_adderop_reg1_cry_5 ARI1 FCI In - 1.182 - un2_adderop_reg1_cry_5 ARI1 FCO Out 0.016 1.198 - un2_adderop_reg1_cry_5 Net - - 0.000 - 1 un2_adderop_reg1_cry_6 ARI1 FCI In - 1.198 - un2_adderop_reg1_cry_6 ARI1 FCO Out 0.016 1.214 - un2_adderop_reg1_cry_6 Net - - 0.000 - 1 un2_adderop_reg1_cry_7 ARI1 FCI In - 1.214 - un2_adderop_reg1_cry_7 ARI1 FCO Out 0.016 1.231 - un2_adderop_reg1_cry_7 Net - - 0.000 - 1 un2_adderop_reg1_s_8 ARI1 FCI In - 1.231 - un2_adderop_reg1_s_8 ARI1 S Out 0.073 1.304 - un2_adderop_reg1_s_8_S Net - - 1.117 - 1 Adderop_reg1[8] SLE D In - 2.421 - ===================================================================================== Total path delay (propagation time + setup) of 2.676 is 0.686(25.6%) logic and 1.990(74.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------- U0.dotp_multadd1_0.U0 System MACC CDOUT[0] CDOUT[0] 0.000 -0.168 U0.dotp_multadd1_0.U0 System MACC CDOUT[0] CDOUT[0] 0.000 -0.168 U0.dotp_multadd1_0.U0 System MACC CDOUT[1] CDOUT[1] 0.000 -0.168 U0.dotp_multadd1_0.U0 System MACC CDOUT[1] CDOUT[1] 0.000 -0.168 U0.dotp_multadd1_0.U0 System MACC CDOUT[2] CDOUT[2] 0.000 -0.168 U0.dotp_multadd1_0.U0 System MACC CDOUT[2] CDOUT[2] 0.000 -0.168 U0.dotp_multadd1_0.U0 System MACC CDOUT[3] CDOUT[3] 0.000 -0.168 U0.dotp_multadd1_0.U0 System MACC CDOUT[3] CDOUT[3] 0.000 -0.168 U0.dotp_multadd1_0.U0 System MACC CDOUT[4] CDOUT[4] 0.000 -0.168 U0.dotp_multadd1_0.U0 System MACC CDOUT[4] CDOUT[4] 0.000 -0.168 ============================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------- U1.dotp_multadd_0.U0 System MACC CDIN[0] CDOUT_0[0] 0.950 -0.168 U1.dotp_multadd_0.U0 System MACC CDIN[0] CDOUT_0[0] 0.950 -0.168 U1.dotp_multadd_0.U0 System MACC CDIN[1] CDOUT_0[1] 0.950 -0.168 U1.dotp_multadd_0.U0 System MACC CDIN[1] CDOUT_0[1] 0.950 -0.168 U1.dotp_multadd_0.U0 System MACC CDIN[2] CDOUT_0[2] 0.950 -0.168 U1.dotp_multadd_0.U0 System MACC CDIN[2] CDOUT_0[2] 0.950 -0.168 U1.dotp_multadd_0.U0 System MACC CDIN[3] CDOUT_0[3] 0.950 -0.168 U1.dotp_multadd_0.U0 System MACC CDIN[3] CDOUT_0[3] 0.950 -0.168 U1.dotp_multadd_0.U0 System MACC CDIN[4] CDOUT_0[4] 0.950 -0.168 U1.dotp_multadd_0.U0 System MACC CDIN[4] CDOUT_0[4] 0.950 -0.168 ============================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 0.950 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.950 - Propagation time: 1.117 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.168 Number of logic level(s): 0 Starting point: U0.dotp_multadd1_0.U0 / CDOUT[0] Ending point: U1.dotp_multadd_0.U0 / CDIN[0] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------- U0.dotp_multadd1_0.U0 MACC CDOUT[0] Out 0.000 0.000 - CDOUT[0] Net - - 1.117 - 1 U1.dotp_multadd_0.U0 MACC CDIN[0] In - 1.117 - ======================================================================================== Total path delay (propagation time + setup) of 1.117 is 0.000(0.0%) logic and 1.117(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 0.950 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.950 - Propagation time: 1.117 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.168 Number of logic level(s): 0 Starting point: U0.dotp_multadd1_0.U0 / CDOUT[0] Ending point: U1.dotp_multadd_0.U0 / CDIN[0] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------- U0.dotp_multadd1_0.U0 MACC CDOUT[0] Out 0.000 0.000 - CDOUT[0] Net - - 1.117 - 1 U1.dotp_multadd_0.U0 MACC CDIN[0] In - 1.117 - ======================================================================================== Total path delay (propagation time + setup) of 1.117 is 0.000(0.0%) logic and 1.117(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 0.950 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.950 - Propagation time: 1.117 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.168 Number of logic level(s): 0 Starting point: U0.dotp_multadd1_0.U0 / CDOUT[1] Ending point: U1.dotp_multadd_0.U0 / CDIN[1] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------- U0.dotp_multadd1_0.U0 MACC CDOUT[1] Out 0.000 0.000 - CDOUT[1] Net - - 1.117 - 1 U1.dotp_multadd_0.U0 MACC CDIN[1] In - 1.117 - ======================================================================================== Total path delay (propagation time + setup) of 1.117 is 0.000(0.0%) logic and 1.117(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 0.950 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.950 - Propagation time: 1.117 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.168 Number of logic level(s): 0 Starting point: U0.dotp_multadd1_0.U0 / CDOUT[1] Ending point: U1.dotp_multadd_0.U0 / CDIN[1] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------- U0.dotp_multadd1_0.U0 MACC CDOUT[1] Out 0.000 0.000 - CDOUT[1] Net - - 1.117 - 1 U1.dotp_multadd_0.U0 MACC CDIN[1] In - 1.117 - ======================================================================================== Total path delay (propagation time + setup) of 1.117 is 0.000(0.0%) logic and 1.117(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 0.950 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.950 - Propagation time: 1.117 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.168 Number of logic level(s): 0 Starting point: U0.dotp_multadd1_0.U0 / CDOUT[2] Ending point: U1.dotp_multadd_0.U0 / CDIN[2] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------- U0.dotp_multadd1_0.U0 MACC CDOUT[2] Out 0.000 0.000 - CDOUT[2] Net - - 1.117 - 1 U1.dotp_multadd_0.U0 MACC CDIN[2] In - 1.117 - ======================================================================================== Total path delay (propagation time + setup) of 1.117 is 0.000(0.0%) logic and 1.117(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report for Extended_adder_3_input Mapping to part: m2s050tfbga896std Cell usage: CLKINT 2 uses CFG2 1 use Carry primitives used for arithmetic functions: ARI1 18 uses Sequential Cells: SLE 48 uses DSP Blocks: 2 MACC: 2 Mults I/O ports: 194 I/O primitives: 194 INBUF 142 uses OUTBUF 52 uses Global Clock Buffers: 2 Total LUTs: 19 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 49MB peak: 133MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed May 21 18:58:55 2014 ###########################################################]